WO2024027397A1 - Substrat matriciel et écran d'affichage - Google Patents

Substrat matriciel et écran d'affichage Download PDF

Info

Publication number
WO2024027397A1
WO2024027397A1 PCT/CN2023/103682 CN2023103682W WO2024027397A1 WO 2024027397 A1 WO2024027397 A1 WO 2024027397A1 CN 2023103682 W CN2023103682 W CN 2023103682W WO 2024027397 A1 WO2024027397 A1 WO 2024027397A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal layer
layer
substrate
electrically connected
light
Prior art date
Application number
PCT/CN2023/103682
Other languages
English (en)
Chinese (zh)
Inventor
阳志林
戴超
张淑媛
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Publication of WO2024027397A1 publication Critical patent/WO2024027397A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present application relates to the field of display technology, and specifically to an array substrate and a display panel.
  • LCD Liquid Crystal Display, liquid crystal display
  • AMOLED Active-Matrix Organic Light-Emitting Diode, active matrix organic light-emitting diode
  • LCD Liquid Crystal Display, liquid crystal display
  • AMOLED Active-Matrix Organic Light-Emitting Diode, active matrix organic light-emitting diode
  • AMOLED's array substrate pixel circuit and array are highly complex, and mobile terminal displays using AMOLED need to continuously optimize power consumption reduction solutions.
  • AMOLED displays are gradually used in high-resolution tablets and notebooks, it is of great significance to further reduce the load on the array substrate.
  • This application provides an array substrate and a display panel to reduce the load of the array substrate.
  • This application provides an array substrate, which includes:
  • An active layer is provided on the substrate;
  • a first metal layer disposed on a side of the active layer away from the substrate, where the first metal layer includes scanning lines;
  • a second metal layer is provided on the side of the first metal layer away from the substrate.
  • the second metal layer includes a source electrode, a drain electrode and an auxiliary scan line.
  • the source electrode and the drain electrode are respectively connected to the
  • the active layer is electrically connected
  • the auxiliary scanning line is electrically connected to the scanning line.
  • the resistivity of the auxiliary scan line is smaller than the resistivity of the scan line, and the width of the auxiliary scan line is greater than the width of the scan line.
  • the array substrate further includes a third metal layer, the third metal layer is disposed on a side of the active layer close to the substrate, and the third metal layer It includes a light-shielding member, the orthographic projection of the light-shielding member on the substrate at least covers the orthographic projection of the active layer on the substrate, the light-shielding member is electrically connected to the scan line, and is connected to the same electrical signal. .
  • the third metal layer includes a plurality of the light-shielding parts, each of the light-shielding parts includes a first light-shielding part and a second light-shielding part, and the first light-shielding part
  • the orthographic projection on the substrate at least covers the orthographic projection of the active layer on the substrate, the second light shielding part is electrically connected to the scan line; two adjacent first light shielding parts It is electrically connected through the second light shielding part.
  • the line width of the first light shielding part is greater than the line width of the active layer, and the line width of the second light shielding part is greater than or equal to the line width of the auxiliary scanning line. Width.
  • the array substrate further includes a third metal layer, the third metal layer is disposed on a side of the active layer close to the substrate, and the third metal layer It includes a light-shielding component, the light-shielding component includes a first light-shielding part and a second light-shielding part, and the orthographic projection of the first light-shielding part on the substrate at least covers the orthographic projection of the active layer on the substrate, so The second light shielding part is spaced apart from and insulated from the first light shielding part, and the second light shielding part is electrically connected to the scan line.
  • the first metal layer further includes a plurality of gates spaced apart and insulated, and the second metal layer further includes a plurality of gate scan lines;
  • each gate electrode is electrically connected to the corresponding gate scan line, and two adjacent gate electrodes are electrically connected through the corresponding gate scan line, and the gate scan line is electrically connected to the corresponding gate scan line.
  • the auxiliary scan lines are electrically connected.
  • the material of the first metal layer is molybdenum or molybdenum-titanium alloy
  • the material of the second metal layer is copper, copper/copper, molybdenum/copper or molybdenum-titanium alloy/ copper.
  • the array substrate further includes a fourth metal layer, the fourth metal layer is disposed on a side of the second metal layer away from the substrate, and the fourth metal layer A layer includes data lines electrically connected to the source.
  • the array substrate further includes a first insulating layer, a second insulating layer, a fifth metal layer and an interlayer insulating layer;
  • the first insulating layer is disposed on a side of the first metal layer close to the active layer, and the second insulating layer is disposed on a side of the first metal layer close to the second metal layer.
  • the fifth metal layer is disposed on the side of the second insulating layer close to the second metal layer, and the interlayer insulating layer is disposed on the side of the fifth metal layer close to the second metal layer.
  • the first metal layer also includes a first electrode plate
  • the fifth metal layer includes a second electrode plate
  • the second metal layer also includes a third electrode plate; the first electrode plate and the second The electrode plate forms a first capacitor, and the second electrode plate and the third electrode plate form a second capacitor.
  • the array substrate further includes a passivation layer, a first planar layer and a second planar layer, and the passivation layer is disposed on the second metal layer close to the fourth
  • the first flat layer is disposed on a side of the passivation layer close to the fourth metal layer
  • the second flat layer is disposed on a side of the fourth metal layer away from the substrate. side;
  • the passivation layer has a first via hole, the first via hole penetrates the passivation layer, and the first flat layer fills the first via hole.
  • the interlayer insulating layer has a second via hole, and the second via hole penetrates the interlayer insulating layer and extends to the first insulating layer.
  • the first insulating layer has a third via hole, and the third via hole at least penetrates the first insulating layer;
  • the first via hole, the second via hole and the third via hole are all connected, and the aperture of the second via hole is larger than the aperture of the third via hole.
  • this application also provides a display panel, which includes the array substrate described in any one of the above.
  • the array substrate includes:
  • An active layer is provided on the substrate;
  • a first metal layer is provided on a side of the active layer away from the substrate, the first metal layer includes scanning lines;
  • a second metal layer is provided on the side of the first metal layer away from the substrate.
  • the second metal layer includes a source electrode, a drain electrode and an auxiliary scan line.
  • the source electrode and the drain electrode are respectively connected to the
  • the active layer is electrically connected
  • the auxiliary scanning line is electrically connected to the scanning line.
  • the resistivity of the auxiliary scan line is smaller than the resistivity of the scan line, and the width of the auxiliary scan line is greater than the width of the scan line.
  • the array substrate further includes a third metal layer, the third metal layer is disposed on a side of the active layer close to the substrate, and the third metal layer It includes a light-shielding member, the orthographic projection of the light-shielding member on the substrate at least covers the orthographic projection of the active layer on the substrate, the light-shielding member is electrically connected to the scan line, and is connected to the same electrical signal. .
  • the third metal layer includes a plurality of the light-shielding parts, each of the light-shielding parts includes a first light-shielding part and a second light-shielding part, and the first light-shielding part
  • the orthographic projection on the substrate at least covers the orthographic projection of the active layer on the substrate, the second light shielding part is electrically connected to the scan line; two adjacent first light shielding parts It is electrically connected through the second light shielding part.
  • the line width of the first light shielding part is greater than the line width of the active layer, and the line width of the second light shielding part is greater than or equal to the line width of the auxiliary scanning line. Width.
  • the array substrate further includes a third metal layer, the third metal layer is disposed on a side of the active layer close to the substrate, and the third metal layer It includes a light-shielding component, the light-shielding component includes a first light-shielding part and a second light-shielding part, and the orthographic projection of the first light-shielding part on the substrate at least covers the orthographic projection of the active layer on the substrate, so The second light shielding part is spaced apart from and insulated from the first light shielding part, and the second light shielding part is electrically connected to the scan line.
  • the first metal layer further includes a plurality of gates spaced apart and insulated, and the second metal layer further includes a plurality of gate scan lines;
  • each gate electrode is electrically connected to the corresponding gate scan line, and two adjacent gate electrodes are electrically connected through the corresponding gate scan line, and the gate scan line is electrically connected to the corresponding gate scan line.
  • the auxiliary scan lines are electrically connected.
  • the material of the first metal layer is molybdenum or molybdenum-titanium alloy
  • the material of the second metal layer is copper, copper/copper, molybdenum/copper or molybdenum-titanium alloy/ copper.
  • the array substrate includes a substrate, an active layer, a first metal layer and a second metal layer.
  • the active layer is provided on the substrate;
  • the first metal layer is provided on a side of the active layer away from the substrate, and the first metal layer includes a gate electrode and a scan line;
  • the second metal layer is disposed on the side of the first metal layer away from the substrate.
  • the second metal layer includes a source electrode, a drain electrode and an auxiliary scan line. The source electrode and the drain electrode are respectively connected with the The active layer is electrically connected, and the auxiliary scan line is electrically connected to the scan line.
  • This application can reduce the impedance of the scan line by setting the auxiliary scan line to be electrically connected to the scan line, thereby reducing the load on the array substrate.
  • the auxiliary scan line, source electrode and drain electrode are patterned and formed from the same layer of metal, the manufacturing process can be simplified.
  • Figure 1 is a first structural schematic diagram of the array substrate provided by this application.
  • Figure 2 is a second structural schematic diagram of the array substrate provided by this application.
  • Figure 3 is a first top schematic view of the array substrate provided by the present application.
  • Figure 4 is a third structural schematic diagram of the array substrate provided by this application.
  • Figure 5 is a second top schematic view of the array substrate provided by the present application.
  • Figures 6A-6K are schematic structural diagrams of each step obtained in a manufacturing method of an array substrate provided by this application;
  • Figure 7 is a schematic structural diagram of a display panel provided by this application.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as “first”, “second”, etc. may explicitly or implicitly include one or more of the described features, and therefore cannot be construed as a limitation of the present application.
  • the terms “connected” and “connected” should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection; it can be a direct connection or a connection through The intermediate medium is indirectly connected, which can be the internal connection between two components.
  • the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.
  • This application provides an array substrate and a display panel, which are described in detail below. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments of the present application.
  • the array substrate 100 includes a substrate 10, an active layer 16, a first metal layer 18 and a second metal layer 21.
  • the active layer 16 is provided on the substrate 10 .
  • the first metal layer 18 is disposed on a side of the active layer 16 away from the substrate 10 .
  • the first metal layer 18 includes scan lines 182 .
  • the second metal layer 21 is disposed on the side of the first metal layer 18 away from the substrate 10 .
  • the second metal layer 21 includes a source electrode 211, a drain electrode 212 and an auxiliary scanning line 213.
  • the source electrode 211 and the drain electrode 212 are electrically connected to the active layer 16 respectively.
  • the auxiliary scan line 213 is electrically connected to the scan line 182.
  • the auxiliary scan line 213 is provided in the array substrate 100 and the auxiliary scan line 213 is electrically connected to the scan line 182, which is equivalent to connecting the auxiliary scan line 213 and the scan line 213 in parallel, so the impedance of the scan line 182 can be reduced. , thereby reducing the load on the array substrate 100 and obtaining a high-quality display product.
  • the auxiliary scanning line 213, the source electrode 211 and the drain electrode 212 are patterned and formed from the same layer of metal, the manufacturing process can be simplified.
  • the first metal layer 18 also includes a gate electrode 181 .
  • the gate electrode 181 is electrically connected to the scan line 182 .
  • the resistivity of the auxiliary scanning line 213 is smaller than the resistivity of the scanning line 182 , and the width of the auxiliary scanning line 213 is larger than the width of the scanning line 182 .
  • the material of the first metal layer 18 is molybdenum, molybdenum-titanium alloy and other metals with small line width deviation. Therefore, dry etching can be used to obtain the gate electrode 181 and the scan line 182 with a smaller line width, thereby achieving higher PPI (Pixels Per Inch, pixel density unit) performance. At the same time, the line width of the gate 181 can be uniform, and stable electrical characteristics of the transistor can be achieved.
  • the resistivity of the second metal layer 21 is smaller than the resistivity of the first metal layer 18 .
  • the second metal layer 21 may be a single layer of metal copper, a double layer of metal, a bottom layer of molybdenum and a layer of copper, a bottom layer of molybdenum and titanium alloy and a layer of copper, etc. Since the resistivity of the second metal layer 21 is smaller than the resistivity of the first metal layer 18 , the impedance of the scan line 182 can be further reduced and the load of the array substrate 100 can be reduced.
  • the material of the active layer 16 may be a metal oxide semiconductor or low-temperature polysilicon.
  • LTPO Low Temperature Polycrystalline-Si Oxide, low temperature polycrystalline oxide
  • the substrate 10 may include, but is not limited to, a substrate 11 , a double-layer PI (Polyimide, polyimide) layer 12 and a barrier layer 13 that are stacked sequentially from bottom to top.
  • the substrate 11 may be a glass substrate.
  • the material of the barrier layer 13 may be silicon oxide, silicon nitride, etc.
  • the barrier layer 13 can function as a water barrier and oxygen barrier.
  • the second metal layer 21 may also include gate scanning lines 214 .
  • the gate scanning line 214 is electrically connected to the gate electrode 181 . Since the resistivity of the second metal layer 21 is small, the resistance of the gate electrode 181 can be reduced.
  • the array substrate 100 may further include a first insulating layer 17 and an interlayer insulating layer 20 .
  • the first insulating layer 17 is disposed on the side of the first metal layer 18 close to the active layer 16 .
  • the first insulating layer 17 includes a gate insulating layer 171 .
  • the gate insulating layer 171 is provided between the gate electrode 181 and the active layer 16 .
  • the interlayer insulating layer 20 is provided on the side of the first metal layer 18 close to the second metal layer 21 .
  • the interlayer insulating layer 20 has a first contact hole 20a, a second contact hole 20b and a third contact hole 20c.
  • the first contact hole 20 a and the second contact hole 20 b both penetrate the interlayer insulating layer 20 and extend to the active layer 16 . Both the first contact hole 20 a and the second contact hole 20 b expose a side surface of the active layer 16 away from the substrate 10 .
  • the source electrode 211 is electrically connected to the active layer 16 through the first contact hole 20a.
  • the drain electrode 212 is electrically connected to the active layer 16 through the second contact hole 20b.
  • the third contact hole 20 c penetrates the interlayer insulating layer 20 and extends to the scan line 182 .
  • the third contact hole 20 c exposes a side surface of the scan line 182 away from the substrate 10 .
  • the auxiliary scan line 213 is electrically connected to the scan line 182 through the third contact hole 20c.
  • the interlayer insulating layer 20 also has a fourth contact hole 20d.
  • the fourth contact hole 20d penetrates the interlayer insulating layer 20 and extends to the gate electrode 181.
  • the fourth contact hole 20d exposes a side surface of the gate 181 away from the substrate 10 .
  • the gate scanning line 214 is electrically connected to the gate electrode 181 through the fourth contact hole 20d.
  • the first metal layer 18 also includes a first electrode plate 183 .
  • the second metal layer 21 also includes a third electrode plate 215 . In a direction perpendicular to the substrate 100, the first electrode plate 183 and the third electrode plate 215 are at least partially overlapped.
  • the first electrode plate 183 and the third electrode plate 215 may constitute a storage capacitor.
  • the source electrode 211 and the drain electrode 212 may also be electrically connected to the active layer 16 respectively, and in this case, the interlayer insulating layer 20 may not be provided.
  • the array substrate 100 may also include a second insulation layer 19 and a fifth metal layer 30 .
  • the second insulating layer 19 is disposed on the side of the first metal layer 18 close to the second metal layer 21 .
  • the fifth metal layer 30 is provided on the side of the second insulating layer 19 close to the second metal layer 21 .
  • the interlayer insulating layer 20 is provided on the side of the fifth metal layer 30 close to the second metal layer 21 .
  • the fifth metal layer 30 includes the second electrode plate 31 .
  • the first electrode plate 183 and the second electrode plate 31 form a first capacitor.
  • the second electrode plate 31 and the third electrode plate 215 form a second capacitor.
  • the array substrate 100 may further include a fourth metal layer 24 .
  • the fourth metal layer 24 is disposed on the side of the second metal layer 21 away from the substrate 10 .
  • the fourth metal layer 24 includes data lines (not shown in the figure).
  • auxiliary scan line 213 and the data line are arranged crosswise in the plane. Since the auxiliary scan line 213, the source electrode 211 and the drain electrode 212 are arranged in the same layer, the data line is arranged in the fourth metal layer 24, so that the data The lines and the auxiliary scanning lines 213 are arranged in different layers to avoid cross-short circuits between the data lines and the auxiliary scanning lines 213 .
  • the fourth metal layer 24 also includes a first electrode 241 and a second electrode 242.
  • the data line is electrically connected to the source electrode 211 through the first electrode 241.
  • the second electrode 242 is electrically connected to the drain electrode 212 .
  • the first electrode 241 can also be considered as a data line.
  • the fourth metal layer 24 may be a single layer of metal copper, a double layer of metal, a bottom layer of molybdenum and a layer of copper, a bottom layer of molybdenum and titanium alloy and a layer of copper, etc.
  • the material of the fourth metal layer 24 may be the same as the material of the second metal layer 21 , or may be different.
  • the first electrode 241 is electrically connected to the source electrode 211
  • the second electrode 242 is electrically connected to the drain electrode 212, which can further reduce the impedance of the source electrode 211 and the drain electrode 212 and reduce the load of the array substrate 100.
  • the line width of the second metal layer 21 and the fourth metal layer 24 can be About 20% thinner, further achieving higher PPI performance.
  • the array substrate 100 may further include a passivation layer 22 , a first planarization layer 23 and a second planarization layer 25 .
  • the passivation layer 22 is provided on the side of the second metal layer 21 close to the fourth metal layer 24 .
  • the first flat layer 23 is disposed on the side of the passivation layer 22 close to the fourth metal layer 24 and the second flat layer 25 is disposed on the side of the fourth metal layer 24 away from the substrate 10 .
  • the first flat layer 23 has a first electrical connection hole 23a and a second electrical connection hole 23b.
  • the first electrical connection hole 23 a penetrates the first planar layer 23 and extends to the source electrode 211 .
  • the first electrical connection hole 23 a exposes a side surface of the source electrode 211 away from the substrate 10 .
  • the first electrode 241 is electrically connected to the source electrode 211 through the first electrical connection hole 23a.
  • the second electrical connection hole 23b penetrates the first planar layer 23 and extends to the drain electrode 212 .
  • the second electrical connection hole 23 b exposes a side surface of the drain electrode 212 away from the substrate 10 .
  • the second electrode 242 is electrically connected to the drain electrode 212 through the second electrical connection hole 23b.
  • the passivation layer 22 has a first via hole 22a.
  • the first via hole 22 a penetrates the passivation layer 22 .
  • the first flat layer 23 fills the first via hole 22a.
  • the first flat layer 23 and the second flat layer 25 are made of organic materials to improve the flexibility of the array substrate 100 .
  • the organic material can be a positive organic photoresist (the main component is PI).
  • the material of the first flat layer 23 is an organic material, providing the first via hole 22 a in the passivation layer 22 and filling the first flat layer 23 can further improve the bending resistance of the array substrate 100 .
  • the interlayer insulating layer 20 has a second via hole 20e.
  • the second via hole 20 e penetrates the interlayer insulating layer 20 and extends to the first insulating layer 17 .
  • the first insulating layer 17 has a third via hole 17a.
  • the third via hole 17 a at least penetrates the first insulating layer 17 .
  • the first via hole 22a, the second via hole 20e and the third via hole 17a are all connected.
  • the diameter of the second via hole 20e is larger than the diameter of the third via hole 17a.
  • the third via hole 17 a may penetrate the first insulating layer 17 and extend to the side of the double-layer PI layer 12 away from the substrate 11 .
  • the first flat layer 23 is filled in the first via hole 22a, the second via hole 20e and the third via hole 17a, which can further improve the bending resistance of the array substrate 100.
  • the fourth metal layer 24 also includes at least one signal trace 243 .
  • the signal trace 243 is provided corresponding to the first via hole 22a.
  • the signal wiring 243 is a bridge connecting the signal lines at the Fan-out (fan-shaped wiring area) on the periphery of the display area in the array substrate 100 .
  • the array substrate 100 may further include a third metal layer 14 .
  • the third metal layer 14 is disposed on the side of the active layer 16 close to the substrate 10 .
  • the third metal layer 14 includes a light shielding member 141 .
  • the orthographic projection of the light shielding member 141 on the substrate 10 at least covers the orthographic projection of the active layer 16 on the substrate 10 .
  • the material of the third metal layer 14 is a metal with excellent conductivity and good light-shielding properties, generally molybdenum, copper, aluminum, titanium or composite metal, which is not limited in this application.
  • the array substrate 100 further includes a buffer layer 15 .
  • the buffer layer 15 is disposed between the third metal layer 14 and the active layer 16 to play the role of insulation protection.
  • the light-shielding member 141 can block the light incident from the substrate 10 in a direction away from the light-shielding member 141 , thereby reducing the interference of external light on the active layer 16 , thereby improving the working performance of the array substrate 100 .
  • the array substrate 100 may further include a sixth metal layer 26, a pixel definition layer 27 and a spacer 28.
  • the sixth metal layer 26 includes an anode 261 .
  • Anode 261 and drain 212 are electrically connected.
  • the pixel definition layer 27 has openings 27a.
  • the opening 27 a exposes the side surface of the anode 261 away from the substrate 10 .
  • Functional film layers such as a light-emitting layer may be provided in the opening 27a, which will not be described again here.
  • Figure 2 is a second structural schematic diagram of the array substrate provided by the present application. The difference from the array substrate 100 shown in FIG. 1 is that in the embodiment of the present application, the light shielding member 141 is electrically connected to the scanning line 182 .
  • the first insulation layer 17 has a fourth via hole 17b.
  • the light shielding member 141 is electrically connected to the scanning line 182 through the fourth via hole 17b.
  • the light shielding member 141 , the scanning line 182 and the auxiliary scanning line 213 are all electrically connected together, further reducing the resistivity of the scanning line 182 and reducing the load on the array substrate 100 .
  • the transistors in the array substrate 100 have a top-bottom dual-gate structure.
  • the transistor includes an active layer 16, a gate electrode 181, a source electrode 211, a drain electrode 212, and a light shielding member 141 (as a bottom gate).
  • the light shielding member 141 and the gate 181 receive the same electrical signal through the scanning line 182 and the auxiliary scanning line 213 .
  • FIG. 3 is a first schematic top view of the array substrate provided by this application.
  • the third metal layer 14 includes a plurality of light shielding members 141 .
  • Each light shielding member 141 includes a first light shielding portion 1411 and a second light shielding portion 1412 .
  • the orthographic projection of the first light shielding portion 1411 on the substrate 10 at least covers the orthographic projection of the active layer 16 on the substrate 10 .
  • the second light shielding part 1412 and the scanning line 182 are electrically connected together. Two adjacent first light shielding parts 1411 are electrically connected through the second light shielding part 1412. That is, in the display area of the array substrate 100, the plurality of light shielding members 141 have a continuous structure.
  • the second metal layer 21 includes a plurality of gate scanning lines 214 arranged at intervals.
  • the first metal layer 18 includes a plurality of gate electrodes 181 that are spaced apart and insulated. One end of each gate is electrically connected to a corresponding gate scan line 214 . The other end of each gate is also electrically connected to a corresponding gate scan line 214 .
  • a gate 181 (top gate) and a light shield 141 (bottom gate) are respectively provided on the upper and lower sides of the active layer 16, and the active layer 16 is driven by dual gates, making it easier to control the threshold voltage; at the same time, , and can also significantly increase carrier mobility.
  • the line width of the first light shielding portion 1411 is greater than the line width of the active layer 16
  • the line width of the second light shielding portion 1412 is greater than or equal to the line width of the auxiliary scanning line 213 .
  • the line width of the first light shielding portion 1411 By setting the line width of the first light shielding portion 1411 to be larger than the line width of the active layer 16 , interference caused by external light to the active layer 16 can be reduced.
  • the line width of the second light shielding portion 1412 By setting the line width of the second light shielding portion 1412 to be greater than or equal to the line width of the auxiliary scanning line 213, the coupling capacitance of the same layer of the auxiliary scanning line 213 can be reduced. At the same time, the parasitic capacitance generated by the overlap between the auxiliary scan line 213 and other layers of metal can also be reduced.
  • auxiliary scanning line 213 and the gate scanning line 214 belong to the second metal layer 21 , and the auxiliary scanning line 213 and the gate scanning line 214 may be the same.
  • the transistors in the array substrate 100 have a top-gate structure.
  • FIG. 4 is a third structural schematic diagram of the array substrate provided by the present application
  • FIG. 5 is a second schematic top view of the array substrate provided by the present application.
  • the light shielding member 141 includes a first light shielding part 1411 and a second light shielding part 1412.
  • the orthographic projection of the first light shielding portion 1411 on the substrate 10 at least covers the orthographic projection of the active layer 16 on the substrate 10 .
  • the second light shielding part 1412 is spaced apart from the first light shielding part 1411 and is insulated.
  • the second light shielding part 1412 is electrically connected to the scanning line 182 .
  • the second metal layer 21 further includes a plurality of gate scan lines 214 arranged at intervals.
  • the first metal layer 18 includes a plurality of gate electrodes 181 that are spaced apart and insulated. Each gate electrode 181 is electrically connected to the corresponding gate scanning line 214 through the fourth contact hole 20d, and two adjacent gate electrodes 181 are electrically connected through the corresponding gate scanning line 214.
  • FIGS. 6A to 6K are schematic structural diagrams of each step obtained in a manufacturing method of an array substrate provided by the present application.
  • This application takes the array substrate 100 shown in FIG. 2 as an example for description, but this application should not be understood as limiting the application.
  • the manufacturing method of the array substrate 100 provided by the embodiment of the present application specifically includes the following steps:
  • the substrate 10 may include, but is not limited to, a substrate 11 , a double-layer PI (Polyimide, polyimide) layer 12 and a barrier layer 13 that are stacked sequentially from bottom to top.
  • the substrate 11 may be a glass substrate.
  • the third metal layer 14 includes a light shielding member 141.
  • the first insulating layer 17 is formed on the side of the active layer 16 away from the substrate 10 , and the first photoresist 41 is coated on the side of the first insulating layer 17 away from the substrate 10 , as shown in FIG. 6A .
  • the first metal layer 18 is patterned to form a gate electrode 181, a scan line 182 and a first electrode plate 183, as shown in FIG. 6D.
  • the fifth metal layer 30 is patterned to form a second electrode plate 31 .
  • An interlayer insulating layer 20 is formed on the fifth metal layer 30, as shown in FIG. 6E.
  • first contact holes 20a, second contact holes 20b, third contact holes 20c, and fourth contact holes 20d are formed in the interlayer insulating layer 20.
  • the first contact hole 20 a and the second contact hole 20 b both penetrate the interlayer insulating layer 20 and extend to the active layer 16 .
  • Both the first contact hole 20 a and the second contact hole 20 b expose a side surface of the active layer 16 away from the substrate 10 .
  • the third contact hole 20 c exposes a side surface of the scan line 182 away from the substrate 10 .
  • the fourth contact hole 20d exposes a side surface of the gate 181 away from the substrate 10 . As shown in Figure 6G.
  • a second metal layer 21 having low resistivity is formed, as shown in FIG. 6H.
  • the fourth photoresist 44 is coated on the second metal layer 21, as shown in FIG. 6I. Patterning is completed after exposure and etching, and the source electrode 211, the drain electrode 212, the auxiliary scanning line 213, the gate scanning line 214 and the third electrode plate 215 are formed.
  • the source electrode 211 is electrically connected to the active layer 16 through the first contact hole 20a.
  • the drain electrode 212 is electrically connected to the active layer 16 through the second contact hole 20b.
  • the auxiliary scan line 213 is electrically connected to the scan line 182 through the third contact hole 20c.
  • the gate electrode 181 is electrically connected to the gate scanning line 214 through the fourth contact hole 20d.
  • the first electrode plate 183 and the second electrode plate 31 form a first capacitor.
  • the second electrode plate 31 and the third electrode plate 215 form a second capacitor. As shown in Figure 6J.
  • the fourth metal layer 24 is patterned to form a first electrode 241, a second electrode 242 and at least one signal trace 243.
  • the first electrode 241 is electrically connected to the source electrode 211 .
  • the second electrode 242 is electrically connected to the drain electrode 212 .
  • the formation of the second flat layer 25 and the formation of the sixth metal layer 26 are completed.
  • the sixth metal layer 26 is patterned to form an anode 261 .
  • the pixel definition layer 27 and the spacers 28 are patterned to complete the entire array substrate 100 process.
  • Deep holes are formed through three etchings.
  • the passivation layer 22 has a first via hole 22a.
  • the first via hole 22 a penetrates the passivation layer 22 .
  • the interlayer insulating layer 20 has a second via hole 20e.
  • the second via hole 20 e penetrates the interlayer insulating layer 20 and extends to the first insulating layer 17 .
  • the first insulating layer 17 has a third via hole 17a.
  • the third via hole 17 a at least penetrates the first insulating layer 17 .
  • the first via hole 22a, the second via hole 20e and the third via hole 17a are all connected to form a deep hole.
  • the diameter of the second via hole 20e is larger than the diameter of the third via hole 17a.
  • the three etchings of the first via hole 22a, the second via hole 20e, and the third via hole 17a can be combined with the etching step of each hole in the above steps, thereby simplifying the manufacturing process.
  • the first flat layer 23 is filled in the first via hole 22a, the second via hole 20e and the third via hole 17a, which can further improve the bending resistance of the array substrate 100.
  • each film layer in the array substrate 100 can be referred to the above embodiments, and will not be described again in the manufacturing method of the array substrate 100 .
  • this application also provides a display panel, which includes the array substrate 100 described in any of the above embodiments.
  • the display panel provided by this application can be an organic light-emitting diode display panel, an active matrix organic light-emitting diode display panel, a passive matrix organic light-emitting diode display panel, a quantum dot organic light-emitting diode display panel or a micro-light emitting diode display panel. No specific limitation is made.
  • FIG. 7 is a schematic structural diagram of a display panel provided by the present application.
  • the display panel 1000 provided by the embodiment of the present application also includes a GOA circuit 300 and other functional components.
  • the GOA circuit 300 and other functional components in the embodiment of the present application are related technologies well known to those skilled in the art, and will not be described again here.
  • the display panel 1000 provided by this application includes an array substrate 100.
  • the array substrate includes a substrate, an active layer, a first metal layer, and a second metal layer.
  • the active layer is disposed on the substrate;
  • the first metal layer is disposed on a side of the active layer away from the substrate, and the first metal layer includes gate electrodes and scan lines;
  • the second metal layer is disposed on a side away from the first metal layer.
  • the second metal layer includes a source electrode, a drain electrode and an auxiliary scan line; the source electrode and the drain electrode are electrically connected to the active layer respectively, and the auxiliary scan line is electrically connected to the scan line.
  • Embodiments of the present application can reduce the impedance of the scan lines by setting auxiliary scan lines to be electrically connected to the scan lines, thereby reducing the load on the array substrate and improving the quality of the display panel 1000 .
  • the auxiliary scan line, source electrode and drain electrode are patterned and formed from the same layer of metal, the manufacturing process can be simplified.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

La présente invention concerne un substrat matriciel et un écran d'affichage. Le substrat matriciel comprend un substrat, une couche active, une première couche métallique et une seconde couche métallique, la couche active étant disposée sur le substrat ; la première couche métallique comprend une ligne de balayage ; et la seconde couche métallique est disposée sur le côté de la première couche métallique qui est éloigné du substrat, et la seconde couche métallique comprend une électrode de source, une électrode de drain et une ligne de balayage auxiliaire, l'électrode de source et l'électrode de drain étant électriquement connectées à la couche active, respectivement, et la ligne de balayage auxiliaire étant électriquement connectée à la ligne de balayage.
PCT/CN2023/103682 2022-08-03 2023-06-29 Substrat matriciel et écran d'affichage WO2024027397A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210927862.3A CN115347001A (zh) 2022-08-03 2022-08-03 阵列基板及显示面板
CN202210927862.3 2022-08-03

Publications (1)

Publication Number Publication Date
WO2024027397A1 true WO2024027397A1 (fr) 2024-02-08

Family

ID=83950724

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/103682 WO2024027397A1 (fr) 2022-08-03 2023-06-29 Substrat matriciel et écran d'affichage

Country Status (2)

Country Link
CN (1) CN115347001A (fr)
WO (1) WO2024027397A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115347001A (zh) * 2022-08-03 2022-11-15 武汉华星光电半导体显示技术有限公司 阵列基板及显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110782795A (zh) * 2019-04-24 2020-02-11 友达光电股份有限公司 像素阵列基板
CN112419954A (zh) * 2019-08-21 2021-02-26 群创光电股份有限公司 电子装置
CN114512523A (zh) * 2022-02-15 2022-05-17 深圳市华星光电半导体显示技术有限公司 阵列基板及显示面板
CN115347001A (zh) * 2022-08-03 2022-11-15 武汉华星光电半导体显示技术有限公司 阵列基板及显示面板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110782795A (zh) * 2019-04-24 2020-02-11 友达光电股份有限公司 像素阵列基板
CN112419954A (zh) * 2019-08-21 2021-02-26 群创光电股份有限公司 电子装置
CN114512523A (zh) * 2022-02-15 2022-05-17 深圳市华星光电半导体显示技术有限公司 阵列基板及显示面板
CN115347001A (zh) * 2022-08-03 2022-11-15 武汉华星光电半导体显示技术有限公司 阵列基板及显示面板

Also Published As

Publication number Publication date
CN115347001A (zh) 2022-11-15

Similar Documents

Publication Publication Date Title
CN108598089B (zh) Tft基板的制作方法及tft基板
WO2016041304A1 (fr) Transistor à couches minces et procédé de fabrication correspondant, substrat matriciel et procédé de fabrication correspondant, et dispositif d'affichage
US11462602B2 (en) Array substrate, manufacturing method thereof, and display device
US20240049529A1 (en) Display panel and display device
WO2015100898A1 (fr) Transistor en couches minces (tft), substrat de réseau de tft, son procédé de fabrication et dispositif d'affichage
WO2020215603A1 (fr) Panneau d'affichage oled et son procédé de fabrication
WO2021098475A1 (fr) Substrat d'affichage et procédé de fabrication associé, et appareil d'affichage
US11374033B2 (en) Thin film transistor, manufacturing method thereof, array substrate and display device
WO2016029612A1 (fr) Transistor en couches minces, procédé de fabrication associé, substrat d'affichage et dispositif d'affichage
WO2018209761A1 (fr) Substrat matriciel, son procédé de fabrication, et panneau d'affichage à cristaux liquides
US20230098341A1 (en) Array substrate and display panel
US20240023388A1 (en) Display panel and electronic device
US20220115473A1 (en) Display Substrate, Preparation Method thereof, Display Mother Plate and Display Device
CN109671722B (zh) 有机发光二极管阵列基板及其制造方法
WO2024027397A1 (fr) Substrat matriciel et écran d'affichage
TWI555183B (zh) 薄膜電晶體以及畫素結構
WO2022088365A1 (fr) Panneau d'affichage et procédé de préparation s'y rapportant
CN109309122A (zh) 阵列基板及其制造方法、显示装置
CN103681514B (zh) 阵列基板及其制作方法、显示装置
US20230137855A1 (en) Method of fabricating array substrate and array substrate thereof
WO2022213420A1 (fr) Substrat matriciel et son procédé de préparation, et écran delo
WO2021227106A1 (fr) Écran d'affichage et son procédé de fabrication
WO2024036766A1 (fr) Substrat matriciel et panneau d'affichage
WO2020215414A1 (fr) Substrat de réseau et son procédé de préparation
WO2021190049A1 (fr) Substrat d'affichage, procédé de fabrication associé et écran d'affichage

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23849107

Country of ref document: EP

Kind code of ref document: A1