WO2024022195A1 - 电子设备、快充方法、装置、系统及可读存储介质 - Google Patents

电子设备、快充方法、装置、系统及可读存储介质 Download PDF

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Publication number
WO2024022195A1
WO2024022195A1 PCT/CN2023/108155 CN2023108155W WO2024022195A1 WO 2024022195 A1 WO2024022195 A1 WO 2024022195A1 CN 2023108155 W CN2023108155 W CN 2023108155W WO 2024022195 A1 WO2024022195 A1 WO 2024022195A1
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WIPO (PCT)
Prior art keywords
pin
switch
pins
sets
fast charging
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PCT/CN2023/108155
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English (en)
French (fr)
Inventor
李深龙
Original Assignee
维沃移动通信有限公司
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Publication of WO2024022195A1 publication Critical patent/WO2024022195A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/263—Arrangements for using multiple switchable power supplies, e.g. battery and AC
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0042—Universal serial bus [USB]

Definitions

  • This application belongs to the field of communication technology, and specifically relates to an electronic device, a fast charging method, a device, a system and a readable storage medium.
  • USB Universal Serial Bus
  • the electronic device uses a private fast charging protocol
  • the electronic device needs to occupy the pins used for data transmission for fast charging. Therefore, the electronic device cannot perform data transmission when fast charging. transmission.
  • the purpose of the embodiments of this application is to provide an electronic device, a fast charging method, a device, a system, and a readable storage medium that can solve the problem of being unable to transmit data when the electronic device uses a private fast charging protocol for fast charging.
  • embodiments of the present application provide an electronic device, including: a female base and a switch chip.
  • the female base includes two sets of pins, and the switch chip is respectively connected to the two sets of pins; when the switch chip is in a first conductive state In this case, one set of pins in the two sets of pins is used for charging, and the other set of pins in the two sets of pins is used for data transmission; when the switch chip is in the second conduction state, the two sets of pins are used for charging. Both pins are used for charging; when the switch chip is in the third conduction state, both sets of pins are used for data transmission.
  • embodiments of the present application provide a fast charging method, which is applied to the electronic device of the first aspect.
  • the method includes: when the electronic device is connected to a target device through a fast charging data line, if the target device satisfies The first condition and the fast charging data line meet the second condition, then the switch chip in the control electronic device is in the first conduction state; where the target device meets the first condition including: the target device supports a dedicated charging port (Dedicated Charging Port, DCP) and has data transmission capabilities; the fast charging data cable meeting the second condition includes: two sets of target pins in the fast charging data cable are respectively connected to two sets of cables in the fast charging data cable.
  • DCP dedicated Charging Port
  • the two sets of target pins are the pins in the fast charging data line that correspond to the two sets of pins in the electronic device; among them, when the switch chip is in the first conductive state, one set of pins in the two sets of pins For charging, the other of the two sets of pins is for data transmission.
  • the fast charging device includes a control module; a control module configured to, when an electronic device is connected to a target device through a fast charging data line, if the target device meets the first requirement. condition and the fast charging data line meets the second condition, then the switch chip in the control electronic device is in the first conductive state.
  • the target device meeting the first condition includes: the target device is a device that supports DCP and has data transmission capabilities; the fast charging data line meeting the second condition includes: the two sets of target pins in the fast charging data line are connected to the fast charging data line respectively. Two sets of cable connections in One set of pins is used for charging and the other set of pins of the two sets is used for data transmission.
  • inventions of the present application provide a fast charging system.
  • the fast charging system includes a target device, a fast charging data cable and the electronic device of the first aspect.
  • the fast charging data cable is connected to a female socket and a socket in the electronic device respectively.
  • target device port connection among them, the fast charging data line includes two sets of target pins and two sets of cables, the two sets of target pins are respectively connected to the two sets of cables, and the two sets of target pins are respectively connected to the two sets of pins in the female socket. feet connection.
  • inventions of the present application provide an electronic device.
  • the electronic device includes a processor and a memory.
  • the memory stores programs or instructions that can be run on the processor.
  • the programs or instructions are processed by the processor.
  • the processor is executed, the steps of the method described in the second aspect are implemented.
  • embodiments of the present application provide a readable storage medium.
  • Programs or instructions are stored on the readable storage medium.
  • the steps of the method described in the second aspect are implemented. .
  • inventions of the present application provide a chip.
  • the chip includes a processor and a communication interface.
  • the communication interface is coupled to the processor.
  • the processor is used to run programs or instructions to implement the second aspect. the method described.
  • embodiments of the present application provide a computer program product, the program product is stored in a storage medium, and the program product is executed by at least one processor to implement the method described in the second aspect.
  • one of the two sets of pins of the female socket in the electronic device is used for data transmission.
  • Another set of pins in the pins can be used for data transmission; when the switch chip is in the second conduction state, both sets of pins are used for charging; when the switch chip is in the third conduction state, Both sets of pins are used for data transmission; that is, the switch chip is in a different conduction state.
  • the two sets of pins in the female base can be used for data transmission or charging respectively. Therefore, when electronic devices use a private fast charging protocol for fast charging At this time, electronic devices can not only achieve fast charging, but also perform data transmission.
  • Figure 1 is one of the structural schematic diagrams of an electronic device provided by an embodiment of the present application.
  • Figure 2 is a schematic structural diagram of a female socket in an electronic device provided by an embodiment of the present application.
  • Figure 3 is a second structural schematic diagram of an electronic device provided by an embodiment of the present application.
  • Figure 4 is a third schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • Figure 5 is a schematic diagram of an electronic device provided by an embodiment of the present application connected to a target device through a data line;
  • Figure 6 is a fourth schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • Figure 7 is a fifth structural schematic diagram of an electronic device provided by an embodiment of the present application.
  • Figure 8 is a flow chart of a fast charging method provided by an embodiment of the present application.
  • Figure 9 is one of the structural schematic diagrams of a fast charging system provided by an embodiment of the present application.
  • Figure 10 is a structural diagram of a male connector of a fast charging data cable provided by an embodiment of the present application.
  • Figure 11 is the second structural schematic diagram of a fast charging system provided by an embodiment of the present application.
  • Figure 12 is a schematic structural diagram of a fast charging device provided by an embodiment of the present application.
  • Figure 13 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • Figure 14 is a hardware schematic diagram of an electronic device provided by an embodiment of the present application.
  • Figures 1 to 11 are as follows: 10. Electronic equipment; 11. Female base; 12. Switch chip; 13. Two sets of pins; 14. The first switch group; 15. Second switch group; 16, application processor; 17, protocol chip; 18, first pin; 19, second pin; 20, third pin; 21, fourth pin; 24, fifth pin ; 25. Sixth pin; 26. Seventh pin; 27. Eighth pin; 28. Fast charging data line; 29. Target device; 30. Third switch; 31. Fourth switch; 32. Fifth Switch; 33. Sixth switch; 34. Seventh switch; 35. Eighth switch; 36. Ninth switch; 37. Tenth switch; 38. Eleventh switch; 39. Twelfth switch; 40. Tenth switch Three switches; 41. Fourteenth switch; 42. Power supply adapter; 43.
  • first, second, etc. in the description and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It is to be understood that the figures so used are interchangeable under appropriate circumstances so that the embodiments of the present application can be practiced in orders other than those illustrated or described herein, and that "first,” “second,” etc. are distinguished Objects are usually of one type, and the number of objects is not limited. For example, the first object can be one or multiple.
  • “and/or” in the description and claims indicates at least one of the connected objects, and the character “/" generally indicates that the related objects are in an "or” relationship.
  • BC1.2 is a protocol developed by the BC group under the USB Standardization Organization (USB-IF (Implementers Forum)). It is mainly used to standardize battery charging requirements. The protocol was first implemented based on the USB2.0 protocol.
  • USB-IF examplementers Forum
  • the USB2.0 protocol stipulates that the maximum current that peripherals can draw from the USB charger is 500mA.
  • the current limit of 500mA cannot meet the growing demand for fast charging. Therefore, the BC1.2 protocol introduces a charging port identification mechanism, which mainly includes the following USB port types:
  • SDP Standard Downstream Port
  • DCP Dedicated Charging Port
  • CDP Charging Downstream Port
  • Power supply device Provides power and is connected to the charging device through cables, such as a power adapter.
  • Charging equipment equipment that receives power through cables, such as mobile terminals, laptops, etc.
  • Cable electronic tag A chip that can read the properties of the cable, power transmission capability, data transmission capability, identity document (ID) and other information.
  • USB-Power Delivery (PD) protocol Power supply equipment that supports the USB-PD protocol, such as the output interface of a charger is a Type-C interface.
  • USB Type-C interface is a USB interface that can be used in both forward and reverse directions. It can be inserted in any direction; no matter how the USB Type-C interface is inserted, the power connection is correct. Since the socket contains two sets of data lines D+/D- connected together, the data lines are connected when the Type-C interface is inserted in any direction.
  • the TX/RX of the USB Type-C interface for high-speed communication cannot be connected together, so the CC pin of the USB Type-C interface is used to mark the insertion direction of the Type-C interface, and to TX via the hardware line. /RX for routing and make sure the configuration is correct.
  • the Type-C interface supports: power transmission with a maximum power of 100W and a transmission speed with a maximum speed of 10Gbps.
  • USB defines three roles according to the direction of data transmission: host port, slave device port and (On-The-Go, OTG) port. Among them, a device that supports OTG can be used as a Host or a Device. OTG technology allows implementation without a host (Host). For data transmission between current devices, in the Type-C interface, the definition has been modified. The modified definition is shown in Table A below:
  • the data role of the USB Type-C interface must be consistent with the power role. Because the Type-C protocol does not provide a redundant mechanism to independently negotiate data roles, that is, the power supply side serves as the data master device at the same time, and the charger (power receiver) serves as the data slave device at the same time.
  • embodiments of the present application provide an electronic device, a female base and a switch chip.
  • the female base includes two sets of pins, and the switch chip is connected to the two sets of pins respectively.
  • the switch chip is in different conduction states, the functions of these two sets of pins can be different. Specifically, when the switch chip is in the first conductive state, one set of pins in the two sets of pins is used for charging, and the other set of pins in the two sets of pins is used for data transmission; when the switch chip is in the When the switch chip is in the third conductive state, both sets of pins are used for charging; when the switch chip is in the third conductive state, both sets of pins are used for data transmission.
  • the switch chip can be controlled to be in the first conductive state, so that the electronic device can realize fast charging (private protocol) and data transmission at the same time.
  • FIG. 1 shows a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • the electronic device 10 provided by the embodiment of the present application may include: a female base 11 and a switch chip 12.
  • the female base 11 includes two sets of pins 13, and the switch chip 12 is connected to the two sets of pins 13 respectively.
  • the electronic device when the electronic device requires fast charging and data transmission at the same time, can control the switch chip to be in the first conductive state. Specifically, the electronic device can control the switch chip to be in the first conductive state when the electronic device is connected to the target device and the target device is a device that supports DCP and has data transmission capabilities.
  • the electronic device can control the switch chip to be in the second conductive state.
  • the switch chip can be controlled to be in the second conductive state to increase the charging power.
  • the target device may be a device with data transmission capability or a device without data transmission capability. That is to say, even if the target device supports data transmission, the electronic device still adjusts the switch chip to the second conductive state.
  • the electronic device can control the switch chip to be in the third conductive state.
  • the switch chip can be controlled to be in the third conduction state to increase the data transmission power.
  • the target device may be a device that supports DCP or a device that does not support DCP. That is to say, even if the target device supports DCP, the electronic device still adjusts the switch chip to the third conductive state.
  • the female base may include a female base body and two sets of pins, wherein the two sets of pins are symmetrically arranged on the same surface of the female base body.
  • Figure 2 is a schematic structural diagram of the female base 11. As shown in Figure 2, two rows of pin positions are symmetrically arranged on one surface of the female base body, namely row A pin positions and row B pin positions. Each row of pins includes 12 pins; specifically, row A of pins includes pins A1 to pins A12, and row B of pins includes pins B1 to B12. Set one pin on each pin position.
  • D1+ pin can be set at pin position A6 On, the D1- pin can be set on pin A7; the D2+ pin can be set on pin B6, and the D2- pin can be set on pin B7. As can be seen from Figure 2, the D1+ pin is opposite to the D2- pin, and the D1- pin is opposite to the D2 pin+.
  • the D1+ pin is short-circuited with the D2+ pin
  • the D1- pin is short-circuited with the D2- pin. That is, the female socket in the related art has one and only one set of D+ and D- pins.
  • the D1+ and D1- pins are independent of the D2+ and D2- pins, thereby ensuring that the female socket in the embodiment of the present application can include two sets of D+ and D- pins.
  • one set of pins in the two sets of pins is used for charging, and the other set of pins in the two sets of pins is used for data transmission. Therefore, when one of the two sets of pins includes the D1+ pin and the D1- pin, and the other set of the two sets of pins includes the D2+ pin and the D2- pin, a possible situation , D1+ pin and D1- pin are used for charging, D2+ pin and D2- pin are used for data transmission; another possible situation, D1+ pin and D1- pin are used for data transmission, D2+ pin and D2-pin is used for charging.
  • the female base 11 may also include other pins.
  • the female base can also include:
  • one set of transmitting pins includes: TX1+ pin, TX1- pin, which are set at pin position A2 and pin position A3 respectively;
  • the other set of transmitting pins includes: TX2+ pin, TX2 -The pins are set at pin B2 and pin B3 respectively;
  • one set of receiving pins includes: RX1+ pin, RX1- pin, which are set at pin position B11 and pin position B10 respectively;
  • the other set of receiving pins includes: RX2+ pin, RX2- pin pins, respectively set at pin A11 and pin A12;
  • CC pins which are the CC1 pin and CC2 pin set at pin position A5 and pin position B5 respectively; among them, the CC pin is used for transmission direction confirmation and forward and reverse insertion confirmation, and USB-PD communication.
  • SBU pins There are 2 SBU pins, respectively set at pin A8 and pin B8; the SBU pin is used for sideband use.
  • the above-mentioned female socket is a female socket that supports USB Type-C interface.
  • the female socket can be a female socket that supports both the USB2.0 interface and the USB Type-C interface.
  • the electronic device 10 may also include: an application processor 16 and a protocol chip 17 ; the switch chip 12 may include a first switch group 14 and a second switch group 15 .
  • the fast charging protocol chip 17 is used for fast charging, and the application processor 16 is used for transmitting and processing data.
  • the switch chip 12 When the switch chip 12 is in the first conductive state: one of the two sets of pins 13 passes through The first switch group 14 is connected to the application processor 16 to realize data transmission; the other group of pins in the above two sets of pins 13 is connected to the protocol chip 17 through the second switch group 15 to realize charging.
  • the electronic device 10 uses a private fast charging protocol for charging, since one set of pins can support the electronic device 10 for fast charging and the other set of pins supports data transmission, when the electronic device 10 uses a private protocol for fast charging, While charging, the electronic device 10 can still transmit data.
  • one of the two groups of pins 13 is connected to the protocol chip 17 through the first switch group 14 to achieve charging; Another set of pins is connected to the protocol chip 17 through the second switch set 15 to implement charging.
  • one of the two groups of pins 13 is connected to the application processor 16 through the first switch group 14 to realize data transmission; the two groups of pins 13 Another set of pins is connected to the application processor 16 through the second switch set 15 to implement data transmission.
  • the above-mentioned protocol chip is a fast charging protocol chip in electronic equipment.
  • the fast charging protocol chip is a bridge between electronic devices and target devices.
  • the stability of the protocol chip plays a decisive role in the fast charging experience and reliability.
  • a stable and reliable protocol chip can adjust the output voltage in real time according to the requirements of electronic equipment, and provide corresponding power at different stages of fast charging to ensure stable and high-speed fast charging.
  • the electronic device when a group of pins is used for charging, can transmit the fast charging protocol through the channel corresponding to the group of pins, and use the fast charging protocol to quickly charge, that is, perform fast charging.
  • This fast charging protocol is a private fast charging protocol.
  • the private fast charging protocol is VFCP protocol, UFCP protocol, etc.
  • the switch chip is switched between three conduction states, so that the electronic device can achieve at least the following through the two sets of pins in the female socket One function: data transfer, fast charging.
  • the switch chip controls the switches in the switch chip to be in different conduction states, the electronic device has different capabilities, thereby improving the operational convenience of the switching capability of the electronic device.
  • the above-mentioned set of pins may include a first pin and a second pin
  • the above-mentioned another set of pins may include a third pin and a fourth pin
  • the application processor may include a fifth pin and a sixth pin.
  • Pin; the protocol chip includes the seventh pin and the eighth pin.
  • the first end a1 of the first switch group 14 is connected to the first pin 18, the second end b1 of the first switch group 14 is connected to the second pin 19; the first end a2 of the second switch group 15 is connected to the third pin 18.
  • the pin 20 is connected, and the second terminal b2 of the second switch group 15 is connected to the fourth pin 21 .
  • the third terminal c1 of the first switch group 14 and the third terminal c2 of the second switch group 15 are both connected to the fifth pin 24
  • the fourth terminal e1 of the first switch group 14 and the fourth terminal of the second switch group 15 e2 are both connected to the seventh pin 26
  • the fifth terminal f1 of the first switch group 14 and the fifth terminal f2 of the second switch group 15 are both connected to the sixth pin 25
  • the sixth terminal g1 of the first switch group 14 and the sixth terminal g2 of the second switch group 15 are both connected to the eighth pin 27 .
  • the first pin 18 is the D+ pin
  • the second pin 19 is the D- pin
  • the third pin 20 is the D+ pin
  • the fourth pin 21 is the D- pin
  • the fifth pin 24 and the sixth pin 25 are the D+ pin and the D- pin of the application processor 16 respectively
  • the seventh pin 26 and the eighth pin 27 are the D+ pin and the D- pin of the protocol chip 17 respectively. foot.
  • the pin 24 and the sixth pin 25 are the D- pin and the D+ pin of the application processor 16 respectively
  • the seventh pin 26 and the eighth pin 27 are the D- pin and the D+ pin of the protocol chip 17 respectively.
  • the switch chip 12 when the switch chip 12 is in the first conductive state, the first terminal a1 of the first switch group 14 and the third terminal c1 of the first switch group 14 are connected, so that the first pin 18 is connected to the fifth pin 24 of the application processor 16, and the second terminal b1 of the first switch group 14 and the first
  • the fifth terminal f1 of the switch group 14 is connected to connect the second pin 19 with the sixth pin 25 of the application processor 16; the first terminal a2 of the second switch group 15 and the second terminal a2 of the second switch group 15 are connected.
  • the fourth terminal e2 is connected to connect the third pin 20 to the seventh pin 26 of the protocol chip 17, and the second terminal b2 of the second switch group 15 and the sixth terminal g2 of the second switch group 15 between them, so that the fourth pin 21 is connected to the eighth pin 27 of the protocol chip 17 .
  • the electronic device 10 uses a private fast charging protocol for charging, the electronic device can realize data transmission through one set of pins in the two sets of pins, and realize fast charging through one set of pins in the two sets of pins. .
  • the switch chip 12 When the switch chip 12 is in the second conductive state, the first terminal a1 of the first switch group 14 and the fourth terminal e1 of the first switch group 14 are connected, so that the first pin 18 is connected to the protocol chip.
  • the seventh pin 26 of 17 is connected, and the second terminal b1 of the first switch group 14 and the sixth terminal g1 of the first switch group 14 are connected, so that the second pin 19 and the eighth terminal of the protocol chip 17 are connected.
  • Pin 27 is connected; there is conduction between the first terminal a2 of the second switch group 15 and the fourth terminal e2 of the second switch group 15, so that the third pin 20 is connected to the seventh pin 26 of the protocol chip 17, And the second terminal b2 of the second switch group 15 is connected to the sixth terminal g2 of the second switch group 15 , so that the fourth pin 21 is connected to the eighth pin 27 of the protocol chip 17 .
  • the switch chip 12 When the switch chip 12 is in the third conductive state, the first terminal a1 of the first switch group 14 and the third terminal c1 of the first switch group 14 are connected, so that the first pin 18 is connected to the application process.
  • the fifth pin 24 of the processor 16 is connected, and the second terminal b1 of the first switch group 14 and the fifth terminal f1 of the first switch group 14 are connected, so that the second pin 19 and the application processor 16
  • the sixth pin 25 is connected; the first terminal a2 of the second switch group 15 and the third terminal c2 of the second switch group 15 are connected, so that the third pin 20 and the fifth pin 24 are connected, and the third pin 20 is connected to the fifth pin 24.
  • the second terminal b2 of the second switch group 15 is connected to the fifth terminal f2 of the second switch group 15 so that the fourth pin 21 is connected to the sixth pin 25 of the application processor 16 .
  • the first switch group can be used to control one group of pins in the two groups of pins to be connected to the application processor or protocol chip
  • the second group of switches can be used to control the other group of pins in the two groups of pins to be connected to the application processor.
  • the device or protocol chip is connected, so that the different functions of the two sets of pins can be realized.
  • each switch group in the first switch group and the second switch group may include one of the following: 1 double pole double throw switch (Double Pole Double Throw, DPDT) (mode 1); 2 Single pole double throw switch (Single Pole Double Throw, SPDT) (mode 2); 4 single pole single throw switches (mode 3).
  • DPDT Double Pole Double Throw
  • SPDT Single Pole Double Throw
  • mode 3 4 single pole single throw switches
  • mode 1 as shown in Figure 4, take the first switch group 14 including a first switch, the second switch group 15 including a second switch, and both the first switch and the second switch being DPDT switches.
  • the two moving ends of the first switch are the first end a1 of the first switch group 14 and the second end b1 of the first switch group 14
  • the two fixed ends corresponding to one moving end of the first switch are the first switch group 14
  • the third terminal c1 and the fourth terminal e1 and the two fixed terminals corresponding to the other moving terminal of the first switch are the fifth terminal f1 and the sixth terminal f2 of the first switch group 14.
  • the two moving ends of the second switch are the first end a2 and the second end b2 of the second switch group 15, and the two fixed ends corresponding to one moving end of the second switch are the third end of the second switch group 15.
  • the terminal c2 and the fourth terminal e2, and the two fixed terminals corresponding to the other moving terminal of the second switch are the fifth terminal f2 and the sixth terminal g2 of the second switch group 15.
  • Each fixed end of the DPDT switch can alternately conduct (contact) with its corresponding two moving ends; for example, assuming that the two moving ends of the DPDT switch are moving end 1 and moving end 2, then at any time, the DPDT
  • the fixed terminal of the switch can be connected to the moving terminal 1, or the fixed terminal of the DPDT switch can be connected to the moving terminal 2.
  • the first switch is connected to the first pin, the second pin, the fifth pin, the sixth pin, the seventh pin and the eighth pin respectively, and the second switch is connected to the third pin
  • the fourth pin, the fifth pin, the sixth pin, the seventh pin and the eighth pin are connected, so that one group of pins in the two groups of pins can be controlled with the application processor or protocol chip through the first switch connection, and control the other set of pins of the two sets of pins to be connected to the application processor or protocol chip through the second switch, so that different functions of the two sets of pins can be realized.
  • the first pin 18 is the D1+ pin
  • the second pin 19 is the D1- pin
  • the third pin 20 is the D2+ pin
  • the fourth pin Pin 21 is the D2- pin
  • the fifth pin 24 and the sixth pin 25 are the D+ pin and D- pin of the application processor 16 respectively
  • the seventh pin 26 and the eighth pin 27 are the protocol chip respectively.
  • the cable L3 is connected to the sixth pin 25, the cable L4 is connected between the fourth fixed terminal of the first switch (i.e., the sixth terminal g1 of the first switch group 14) and the eighth pin 27;
  • a cable L5 is connected between a certain end (ie, the third end c2 of the second switch group 15) and the fifth pin 24, and the second fixed end of the second switch (ie, the fourth end e2 of the second switch group 15) is connected to the fifth pin 24.
  • the seventh pin 26 is connected to the cable L6, the third fixed end of the first switch (i.e. the fifth end f2 of the second switch group 15) and the sixth pin 25 are connected to the cable L7, and the fourth end of the first switch is connected to the cable L6.
  • a cable L8 is connected between the fixed end (ie, the sixth end g2 of the second switch group 15) and the eighth pin 27. So:
  • the default switch chip of the electronic device is in the third conduction state, that is, both sets of pins in the default female socket of the electronic device are used to transmit data; specifically, refer to Figure 4, as shown in Table 1 below:
  • the default conduction state of the switch chip is the third conduction state.
  • the electronic device can control the switch chip to be in a third conductive state for data transmission.
  • the electronic device can control the switch chip to be in the third conduction state for data transmission.
  • the electronic device may not switch the switch function, that is, keep the switch chip in the third conduction state, so that the electronic device can reversely power the target device.
  • Device that is, the electronic device can be used as a power supply device at this time, and the target device can be used as a charging device.
  • the electronic device can control the switch chip to be in the second conduction state, so that the electronic device can perform fast charging through the two sets of pins in the female socket.
  • the electronic device After the electronic device is disconnected from the target device (for example, unplugging the data cable), the electronic device can switch the switch chip to the third conductive state, that is, restore the default state.
  • the target device connected to the electronic device does not support OTG.
  • the target device is a power adapter that does not support OTG but supports the VFCP protocol or UFCP protocol (that is, the fast charging protocol data between the electronic device and the target device needs to go through D+, D- pin)
  • the electronic device can first determine whether the target device is a device that supports DCP when the switch chip is in the third conduction state. If the electronic device determines that the target device is a device that supports DCP, the electronic device can switch the switch chip from the third conduction state to the second conduction state, so that the electronic device can quickly charge or perform other operations through the target device, for example Get device capability information of the target device.
  • the electronic device can control the switch chip to be in the first conduction state, so that one set of pins in the female socket is used to transmit data, and the other set of pins for charging.
  • Figure 4 As shown in Table 3:
  • the D1+ pin is connected to the D+ pin of the protocol chip 17 through the connecting cable L2
  • the D1- pin is connected to the D- pin of the protocol chip 17 through the connecting cable L4
  • the D2+ pin pin is connected to the D+ pin of the application processor through the connecting cable L5
  • the D2- pin is connected to the D- pin of the application processor 16 through the connecting cable L7; that is, when the data line is reversely connected to the female socket, the D1+ pin
  • the pin group of D2+ pin and D1- pin is used for fast charging, and the group of pins of D2+ pin and D2- pin is used for data transmission.
  • the data cable and the female socket can be connected either directly or in reverse. Both of these connection methods can ensure that one set of pins is used for data transmission and the other set of pins is used for fast charging, so both methods belong to the first conduction state.
  • Figure 5 is a schematic structural diagram of the female base 11 connected to the target device 29 through the fast charging data cable 28.
  • Figure 5 shows a schematic diagram of the fast charging data line 28 and the female base 11 being connected properly.
  • Figure 5 shows a schematic diagram of the data line 28 and the female socket 11 being connected in reverse.
  • the first switch group 14 includes a third switch 30 and a fourth switch 31; the second switch group 15 includes a fifth switch 32 and a sixth switch 33.
  • the third switch 30, the fourth switch 31, the fifth switch 32 and the sixth switch 33 are all SPDT switches.
  • the moving end of the third switch 30 is the first end a1 of the first switch group 14, one fixed end of the third switch 30 is the third end c1 of the first switch group 14, and the other fixed end of the third switch 30 is The terminal is the fourth terminal e1 of the first switch group 14; the moving terminal of the fourth switch 31 is the second terminal b1 of the first switch group 14; a fixed terminal of the fourth switch 31 is the fifth terminal of the first switch group 14 f1, the other fixed terminal of the fourth switch 31 is the sixth terminal g1 of the first switch group 14; the moving terminal of the fifth switch 32 is the first terminal a2 of the second switch group 15, and one fixed terminal of the fifth switch 32 is the third end c2 of the second switch group 15, the other fixed end of the fifth switch 32 is the fourth end e2 of the second switch group 15; the moving end of the sixth switch 33 is the second end of the second switch group 15 b2; one fixed terminal of the sixth switch 33 is the fifth terminal f2 of the second switch group 15, and the other fixed terminal of the third switch
  • the first pin is the D1+ pin
  • the second pin 19 is the D1- pin
  • the third pin is the D2+ pin
  • the fourth pin is the D2- pin
  • the fifth and sixth pins are the D+ pin and D- pin of the application processor respectively
  • the seventh and eighth pins are the D+ and D- pins of the protocol chip respectively
  • the first switch The group 14 includes a third switch 30 and a fourth switch 31
  • the second switch group 15 includes a fifth switch 32 and a sixth switch 33 . So:
  • the switch chip 12 is in the first conductive state specifically as follows: the moving end of the third switch 30 (ie, the first end a1 of the first switch group 14) and a fixed end of the third switch 30 (ie, the first end a1 of the first switch group 14).
  • the switch chip is in the second conductive state specifically as follows: the moving end of the third switch 30 (ie, the first end a1 of the first switch group 14) and the other fixed end of the third switch 30 (ie, the first end a1 of the first switch group 14).
  • the four terminals e1) are connected, so that the first pin 18 is connected to the seventh pin 26 of the protocol chip 17; the moving end of the fourth switch 31 (ie, the second end b1 of the first switch group 14) and the fourth The other fixed end of the switch 31 (ie, the sixth end g1 of the first switch group 14) is connected, so that the second pin 19 is connected to the eighth pin 27 of the protocol chip 17; the moving end of the fifth switch 32 (i.e., the first terminal a2 of the second switch group 15) is connected to the other fixed terminal of the fifth switch 32 (i.e., the fourth terminal e2 of the second switch group 15), so that the third pin 20 is connected to the protocol chip
  • the seventh pin 26 of 17 is connected; the moving end of the sixth switch 33 (i.e., the second end b2 of the second switch group 15) and the other fixed end of the sixth switch 33 (i.e., the sixth end of the second switch group 15 g2) are turned on, so that the fourth pin 21 is connected to the
  • the switch chip is in the third conductive state specifically as follows: the moving end of the third switch 30 (the first end a1 of the first switch group 14) and a fixed end of the third switch 30 (that is, the third end of the first switch group 14). c1) are connected, so that the first pin 18 is connected to the fifth pin 24 of the application processor 16; the moving end of the fourth switch 31 (ie, the second end b1 of the first switch group 14) and the fourth switch 31 (i.e., the fifth terminal f1 of the first switch group 14) is connected, so that the second pin 19 is connected to the sixth pin 25 of the application processor 16; the moving terminal ( i.e.
  • the first terminal a2) of the switch group 15 is connected to a fixed terminal of the fifth switch 32 (ie, the third terminal c2 of the second switch group 15), so that the third pin 20 is connected to the fifth terminal of the application processor 16.
  • Pin 24 is connected; there is conduction between the moving end of the sixth switch 33 (i.e., the second end b2 of the second switch group 15) and a fixed end of the sixth switch 33 (the fifth end f2 of the second switch group 15). , so that the fourth pin 21 is connected to the sixth pin 25 of the application processor 16 .
  • one set of the above two sets of pins 13 can be used for data transmission and the other set of pins can be used for charging.
  • each of the two sets of pins of the female socket can be connected to the application processor or protocol chip through an SPDT switch in the switch chip, the two sets of pins in the female socket can be realized. Different functions of pins.
  • one of the above two sets of pins 13 includes a first pin 18 and a second pin 19, and the above two sets of pins 13
  • Another group of pins in may include a third pin 20 and a fourth pin 21
  • the first switch group 14 may include a seventh switch 34, an eighth switch 35, a ninth switch 36 and a tenth switch 37
  • the switch group 15 may include an eleventh switch 38, a twelfth switch 39, a thirteenth switch 40, and a fourteenth switch 41
  • the application processor 16 includes a fifth pin 24 and a sixth pin 25
  • the protocol chip 17 includes The seventh pin 26 and the eighth pin 27.
  • the moving ends of the seventh switch 34 and the eighth switch 35 are both connected to the first pin 18, and the moving ends of the ninth switch 36 and the tenth switch 37 are both connected to the second pin 19.
  • the moving ends of the eleventh switch 38 and the twelfth switch 39 are both connected to the third pin 20, and the moving ends of the thirteenth switch 40 and the fourteenth switch 41 are both connected to the fourth pin 21;
  • the fixed terminals of the seventh switch 34 and the eleventh switch 38 are connected to the fifth pin 24
  • the fixed terminals of the ninth switch 36 and the thirteenth switch 40 are both connected to the sixth pin 25 .
  • the fixed end of the eighth switch 35 and the fixed end of the twelfth switch 39 are both connected to the seventh pin 26; the fixed end of the tenth switch 37 and the fixed end of the fourteenth switch 41 are both connected to the eighth pin 27.
  • the moving ends of the seventh switch 34 and the eighth switch 35 constitute the first end of the first switch group 14, and the fixed ends of the ninth switch 36 and the tenth switch 37 constitute the second end of the first switch group 14.
  • the fixed end of the seventh switch 34 is the third end of the first switch group 14
  • the fixed end of the eighth switch 35 is the fourth end of the first switch group 14
  • the fixed end of the ninth switch 36 is the first end of the first switch group 14 .
  • the fifth terminal, the fixed terminal of the tenth switch 37 is the sixth terminal of the first switch group 14; the moving terminals of the eleventh switch 38 and the twelfth switch 39 constitute the first terminal of the second switch group 15, and the thirteenth terminal
  • the fixed terminals of the switch 40 and the fourteenth switch 41 constitute the second terminal of the second switch group 15, the fixed terminal of the eleventh switch 38 is the third terminal of the second switch group 15, and the fixed terminal of the twelfth switch 39 is
  • the fourth terminal of the second switch group 15 , the fixed terminal of the thirteenth switch 40 is the fifth terminal of the second switch group 15 , and the fixed terminal of the fourteenth switch 41 is the sixth terminal of the second switch group 15 .
  • the switch chip 12 is in the first conduction state specifically: the seventh switch 34 is closed, the eighth switch 35 is open; and the ninth switch 36 is closed, and the tenth switch 37 is open. open, so that the first pin 18 is connected to the fifth pin 24 of the application processor 16 through the seventh switch 34, and the second pin 19 is connected to the sixth pin 25 of the application processor 16 through the ninth switch 36;
  • the eleventh switch 38 is open, the twelfth switch 39 is closed, the thirteenth switch 40 is open, and the fourteenth switch 41 is closed, so that the third pin 20 passes through the twelfth switch 39 and the seventh pin of the protocol chip 17
  • the fourth pin 21 is connected to the eighth pin 27 of the protocol chip 17 through the fourteenth switch 41 . In this way, data can be transmitted through the first pin 18 and the second pin 19, and fast charging can be performed through the third pin 20 and the fourth pin 21.
  • the switch chip 12 is in the second conductive state specifically as follows: the seventh switch 34 is open and the eighth switch 35 is closed; and the ninth switch 36 is open and the tenth switch 37 is closed, so that the first pin 18 passes through the eighth switch 35 Connected to the seventh pin 26 of the protocol chip 17, the second pin 19 is connected to the eighth pin 27 of the protocol chip 17 through the tenth switch 37; the eleventh switch 38 is disconnected, the twelfth switch 39 is closed, and The thirteenth switch 40 is opened, and the fourteenth switch 41 is closed, so that the third pin 20 is connected to the seventh pin 26 of the protocol chip 17 through the twelfth switch 39 , and the fourth pin 21 is connected through the fourteenth switch 41 Connected to the eighth pin 27 of the protocol chip 17 . In this way, two groups of Pin 13 for fast charging.
  • the switch chip 12 is in the third conductive state specifically: the seventh switch 34 is closed, the eighth switch 35 is open; and the ninth switch 36 is closed, and the tenth switch 37 is open, so that the first pin 18 passes through the seventh switch.
  • 34 is connected to the fifth pin 24 of the application processor 16, the second pin 19 is connected to the sixth pin 25 of the application processor 16 through the ninth switch 36; the eleventh switch 38 is closed, and the twelfth switch 39 is open open, and the thirteenth switch 40 is closed, and the fourteenth switch 41 is opened, so that the third pin 20 is connected to the fifth pin 24 of the application processor 16 through the eleventh switch 38, and the fourth pin 21 is connected through the eleventh switch 38.
  • the thirteenth switch 40 is connected to the sixth pin 25 of the application processor 16 . This allows data transmission through two sets of pins 13.
  • Mode 2 and Mode 3 please refer to the relevant description in Mode 1 above.
  • each of the two sets of pins in the female socket can be connected to the application processor or protocol chip through two switches in the switch chip, the two sets of pins in the female socket can be realized. Different functions of pins.
  • the switch chip in the electronic device when the switch chip in the electronic device is in the first conductive state, one set of the two sets of pins of the female socket in the electronic device is used for data transmission.
  • the other set of pins in the two sets of pins can be used for data transmission; when the switch chip is in the second conduction state, both sets of pins are used for charging; when the switch chip is in the third conduction state In this case, both sets of pins are used for data transmission; that is, the switch chip is in a different conduction state, and the two sets of pins in the female socket can be used for data transmission or charging respectively. Therefore, when electronic devices use private fast charging When the protocol is used for fast charging, electronic devices can not only realize fast charging, but also perform data transmission.
  • FIG. 8 shows a flow chart of a fast charging method provided by an embodiment of the present application.
  • the fast charging method provided by the embodiment of the present application may include the following step 101. The following takes an electronic device as an example to illustrate the method.
  • Step 101 When the electronic device is connected to the target device through the fast charging data line, if the target device meets the first condition and the fast charging data line meets the second condition, the electronic device controls the switch chip in the electronic device to be in the first conductor. communication status.
  • the target device meeting the first condition includes: the target device is a device that supports DCP and the target device is a device with data transmission capabilities;
  • the fast charging data line meeting the second condition includes: the two sets of target pins in the fast charging data line are respectively Connect with the two sets of cables in the fast charging data cable.
  • the two sets of target pins are pins in the fast charging data line that correspond to the two sets of pins in the electronic device.
  • one set of pins in the two sets of pins in the female base is used for charging, and the other set of pins in the two sets of pins is used for data transmission.
  • the two sets of pins of the electronic device are the two sets of pins of the female socket in the above embodiment of the electronic device, specifically the two sets of D+ pins and D- pins in the female socket.
  • Each of the two sets of target pins consists of a D+ pin and a D- pin.
  • the correspondence between the two sets of target pins and the two sets of pins in the electronic device can be understood as: the D+ pin in the two sets of target pins corresponds to the D+ pin in the two sets of pins.
  • the D-pin corresponds one-to-one with the D-pin in the two sets of pins.
  • the above target device may be a device with at least one of the following capabilities: a fast charging function and a data transmission function.
  • the target device can be: power adapter, USB docking station, etc.
  • the electronic device and the target device can be charged through the target device, and the electronic device and the target device can Perform data transmission, such as text transmission, audio transmission, video transmission, etc.
  • the fast charging method provided by the embodiment of the present application may also include: when the switch chip is in the first conduction state, the electronic device enters the charging mode; between the electronic device and the fast charging data line After disconnecting, the electronic device can control the switch chip to be in the third conductive state.
  • the switch chip When the switch chip is in the third conductive state, both sets of pins in the electronic device are used for data transmission.
  • the fast charging device when the electronic device is connected to the target device through the fast charging data line, the fast charging device can control when the target device meets the first condition and the fast charging data line meets the second condition.
  • the switch chip in the electronic device is in the first conductive state, so that the electronic device can perform data transmission and fast charging respectively through the two sets of pins in the female socket.
  • step 101 can be specifically implemented through the following steps 101a to 101c.
  • Step 101a When the electronic device is connected to the target device through a fast charging data line, and when the target device is a device supporting DCP, the electronic device controls the switch chip to be in the second conductive state.
  • both sets of pins are used for charging.
  • the electronic device when the electronic device is connected to the target device through a fast charging data cable, the electronic device can first obtain the port type information of the target device, and determine whether the target device is a DCP-capable device through the port type information.
  • the port type information may include the port identifier of the target device, the maximum current supported by the port of the target device, and other information.
  • the default switch chip is in the third conduction state.
  • the electronic device can obtain the port type information of the target device based on the BC1.2 protocol, and obtain Get the port type information to determine whether the target device is a device that supports DCP.
  • the electronic device can switch the switch chip from the third conduction state to the second conduction state, so that the electronic device can obtain the device capability information of the target device in the second conduction state. ;
  • the electronic device can end the judgment or perform other processing.
  • the electronic device can be a device that supports any of the following: SDP, CDP.
  • SDP and CDP please refer to the relevant descriptions in the above noun explanation section.
  • the purpose of the electronic device switching the switch state to the second conduction state is: on the one hand, in the second conduction state, the electronic device can obtain the device capability information of the target device; on the other hand, the electronic device can obtain the device capability information of the target device.
  • the target device is a device that supports DCP
  • the electronic device can be fast charged through the target device.
  • the electronic device when the switch chip is in the second conductive state, the electronic device can initiate fast charging protocol handshake detection, so that the electronic device can establish a communication connection with the target device through the fast charging protocol, and thereby obtain the device capability information of the target device.
  • Step 101b The electronic device obtains the device capability information of the target device and the parameter information of the fast charging data line.
  • the above device capability information indicates the data transmission capability of the target device.
  • Step 101c When the device capability information indicates that the target device has data transmission capabilities and the fast charging data line is determined to meet the second condition based on the parameter information, the electronic device controls the switch chip to switch from the second conduction state to the first conduction state. .
  • the electronic device can continue to determine whether the fast charging data line satisfies the second condition. If it is determined that the fast charging data line satisfies the second condition, the electronic device can control The switch chip switches from the second conduction state to the first conduction state; if the device capability information indicates that the target device does not have the data transmission capability, the electronic device can enter the fast charging function.
  • the electronic device when the electronic device is connected to the target device through a fast charging data line, the electronic device can control the switch chip to switch to the second conduction state when determining that the target device is a device that supports DCP. status, so that the electronic device can continue to determine whether the target device has data transmission capabilities, and determine whether the fast charging cable meets the second condition, so that the ability of the target device and the ability of the fast charging data cable can be accurately judged.
  • the fast charging method provided by the embodiment of the present application may further include the following step 102.
  • Step 102 When the device capability information indicates that the target device does not have the data transmission capability, the electronic device controls the switch chip to maintain the second conductive state. In this way, electronic devices can be quickly charged through the target device.
  • the fast charging method provided by the embodiment of the present application may further include the following step 103.
  • Step 103 When the target device meets the third condition, the electronic device controls the switch chip to be in the third conduction state.
  • the target device meeting the third condition includes: the target device is a device that has data transmission capabilities but does not have power supply capabilities.
  • both sets of pins in the electronic device are used for data transmission.
  • the fast charging method provided by the embodiment of the present application can be compatible with the PD protocol. That is, for a target device that supports the PD protocol, if the target device has data transmission capabilities, the electronic device can also control the switch chip to be in the third conduction state. .
  • the electronic device can default the switch chip to be in the third conductive state. Then when the target device has the data transmission capability, the electronic device can keep the switch chip in the third conductive state and perform the high-speed data transmission function. .
  • the electronic device can output prompt information to prompt the user to select the conduction state of the switch chip. For example, if “data transmission only” is selected, the electronic device controls the switch chip to be in the third conduction state. ; If “Charging and data transmission” is selected, the electronic device can perform the above step 101. If “Charging only” is selected, the electronic device can determine whether the target device is a device that supports DCP, and perform operations corresponding to the determination result.
  • the electronic device can control the switch chip to be in the third conduction state, thereby enabling fast data transmission between the electronic device and the target device.
  • the fast charging system 100 in Figure 9 may include a target device 29, a fast charging data cable 28 and the electronic device 10 as in the above electronic device embodiment.
  • the fast charging data cable 28 is connected to the mother base 11 of the electronic device 10 and the target device 29 respectively.
  • the fast charging data line 28 may include two sets of target pins 45 and two sets of cables 46.
  • the two sets of cables 46 are respectively connected to the two sets of target pins 45.
  • the two sets of target pins 45 are connected to two sets of the female base 11. Group pin 13 is connected.
  • each group of target pins includes a D+ pin and a D- pin.
  • each group of cables may include 2 cables, and different cables in each group of cables are connected to different pins in a group of target pins, that is, each cable is connected to a group of target pins. One of the pins is connected.
  • the two sets of target pins in the fast charging data cable correspond one to one with the two sets of pins in the female socket of the electronic device.
  • one of the two sets of D+ and D- pins in the fast charging data cable is connected to the cable, and the other set of D+ and D- pins are not connected to the cable; or in the related art
  • the two sets of D+ and D- pins in the fast charging data cable are short-circuited, that is, connected to the same cable.
  • embodiments of the present application may also provide a fast charging data cable 28.
  • the fast charging data cable 28 includes two sets of target pins 45 and two sets of cables 46.
  • the two sets of cables 46 are respectively connected to the two sets of target pins. Pin 45 connection.
  • the fast charging cable provided by the embodiment of the present application has two sets of target pins connected to different cables.
  • the above two sets of target pins can be set in the male header of the fast charging data cable.
  • FIG. 10 is a schematic structural diagram of the male head of the fast charging data line.
  • the male header includes 24 pins A1 to A12 and B1 to B12.
  • One of the two sets of target pins includes the D1+ pin set at the A6 position, The D1- pin is set at the A7 position.
  • the other set of pins in the two sets of target pins includes the D2+ pin set at the B6 position and the D2- pin set at the B7 position.
  • the fast charging data line when the fast charging data line is connected to the female socket in the electronic device, one of the two sets of target pins is connected to a group of pins in the female socket, and the path formed can be used for charging or data. transmission; the path formed by connecting the other set of target pins in the two sets of target pins to the other set of pins in the female socket can be used for data transmission or charging, so that the fast charging system can achieve fast charging and/or data transmission.
  • the above-mentioned fast charging system 100 may also include a power adapter 42 and an adapter cable 43 ; the fast charging data cable 28 is connected to the USB expansion dock respectively.
  • One port of the USB dock is connected to the female base 11 in the electronic device 10 , and the other port of the USB dock is connected to the power adapter 42 through an adapter cable 43 .
  • the power adapter can be connected to AC power.
  • the AC power supply can provide 110 ⁇ 220V alternating current (Alternating Current, AC).
  • the fast charging data line when the fast charging data line is connected to the female socket of the electronic device and the port of the target device respectively, the fast charging data line includes two sets of target pins and two sets of cables, and Each group of cables in the two groups of cables is connected to two groups of target pins respectively, and the two groups of target pins are connected to the two groups of pins in the female base. Therefore, one group of target pins in the two groups of target pins is connected to The path formed by connecting a set of pins in the female socket can be used for charging or data transmission; the path formed by connecting another set of target pins in the two sets of target pins to another set of pins in the female socket can be used for charging or data transmission. For data transfer or charging. In this way, the fast charging system can realize at least one of fast charging and data transmission at the same time.
  • the execution subject may be a fast charging device (for example, the fast charging device is an electronic device or an external device on the electronic device).
  • the method of performing fast charging by the fast charging device is taken as an example to illustrate the fast charging device provided by the embodiment of the present application.
  • FIG. 12 shows a schematic structural diagram of a fast charging device provided by an embodiment of the present application. As shown in Figure 12, this embodiment of the present application provides a fast charging device.
  • the fast charging device 120 may include: a control module 121;
  • the control module 121 is used to control the switch chip in the electronic device to be in the first state if the target device meets the first condition and the fast charging data line meets the second condition when the electronic device is connected to the target device through a fast charging data line. conduction state;
  • the target device meeting the first condition includes: the target device is a device that supports DCP and has data transmission capabilities;
  • the fast charging data line that meets the second condition includes: two sets of target pins in the fast charging data line are respectively connected to two sets of cables in the fast charging data line;
  • the two sets of target pins are the pins in the fast charging data cable that correspond to the two sets of pins in the electronic device;
  • one set of pins in the two sets of pins is used for charging, and the other set of pins in the two sets of pins is used for data transmission.
  • the fast charging device further includes: an acquisition module.
  • the control module 121 is specifically used to control the switch chip to be in the second conductive state when the target device is a device that supports DCP. When the switch chip is in the second conductive state, both sets of pins are used for charging;
  • the acquisition module is used to obtain the device capability information of the target device and the parameter information of the fast charging data cable;
  • the control module 121 is specifically used to control the switch chip to switch from the second conduction state when the device capability information obtained by the acquisition module indicates that the target device has data transmission capabilities, and it is determined according to the parameter information that the fast charging data line meets the second condition. to the first conductive state.
  • control module 121 is also configured to control the switch chip to maintain the second conductive state when the device capability information indicates that the target device does not have the data transmission capability.
  • control module 121 is also used to control the switch chip to be in the third conduction state when the electronic device is connected to the target device through a fast charging data line and the target device meets the third condition. state;
  • the target device meeting the third condition includes: the target device is a device with data transmission capabilities but without power supply capabilities;
  • both sets of pins are used for data transmission.
  • the electronic device when the electronic device is connected to the target device through the fast charging data line, if the electronic device determines that the target device satisfies the first condition and the fast charging data line satisfies the second condition, then the electronic device The switch chip in the electronic device can be controlled to be in the first conductive state, so that the electronic device can perform data transmission and fast charging respectively through two sets of pins in the female socket.
  • the fast charging device in the embodiment of the present application may be an electronic device or a component of the electronic device, such as an integrated circuit or chip.
  • the electronic device may be a terminal or other devices other than the terminal.
  • the electronic device can be a mobile phone, a tablet computer, a notebook computer, a handheld computer, a vehicle-mounted electronic device, a mobile internet device (Mobile Internet Device, MID), or augmented reality (AR)/virtual reality (VR).
  • the fast charging device in the embodiment of the present application may be a device with an operating system.
  • the operating system can be an Android operating system, an ios operating system, or other possible operating systems, which are not specifically limited in the embodiments of this application.
  • the fast charging device provided by the embodiment of the present application can implement each process implemented by the method embodiment in Figure 8. To avoid repetition, details will not be described here.
  • this embodiment of the present application also provides an electronic device 300, including a processor 301 and a memory 302.
  • the memory 302 stores programs or instructions that can be run on the processor 301.
  • the electronic devices in the embodiments of the present application include the above-mentioned mobile electronic devices and non-mobile electronic devices.
  • Figure 14 is a schematic diagram of the hardware structure of an electronic device that implements an embodiment of the present application.
  • the electronic device 400 includes but is not limited to: radio frequency unit 401, network module 402, audio output unit 403, input unit 404, sensor 405, display unit 406, user input unit 407, interface unit 408, memory 409, processor 410, etc. part.
  • the electronic device 400 may also include a power supply (such as a battery) that supplies power to various components.
  • the power supply may be logically connected to the processor 410 through a power management system, thereby managing charging, discharging, and function through the power management system. Consumption management and other functions.
  • the structure of the electronic device shown in Figure 13 does not constitute a limitation of the electronic device.
  • the electronic device may include more or less components than shown in the figure, or combine certain components, or arrange different components, which will not be described again here. .
  • the processor 410 is used to determine whether the target device meets the first condition when the electronic device is connected to the target device through a fast charging data line, and determines whether the fast charging data line meets the second condition;
  • the processor 410 is configured to control the switch chip in the electronic device to be in the first state when the electronic device is connected to the target device through a fast charging data line and if the target device meets the first condition and the fast charging data line meets the second condition. conduction state;
  • the target device meeting the first condition includes: the target device supports DCP and has data transmission capabilities. equipment;
  • the fast charging data line that meets the second condition includes: two sets of target pins in the fast charging data line are respectively connected to two sets of cables in the fast charging data line;
  • the two sets of target pins are the pins in the fast charging data cable that correspond to the two sets of pins in the electronic device;
  • one set of pins in the two sets of pins is used for charging, and the other set of pins in the two sets of pins is used for data transmission.
  • the processor 410 is specifically configured to control the switch chip to be in the second conductive state when the target device is a device that supports DCP.
  • the switch chip is in the second conductive state, the two The group pins are all used for charging;
  • the acquisition module is used to obtain the device capability information of the target device and the parameter information of the fast charging data cable;
  • the processor 410 is specifically configured to control the switch chip to switch from the second conduction state when the device capability information obtained by the acquisition module indicates that the target device has data transmission capabilities, and it is determined according to the parameter information that the fast charging data line meets the second condition. to the first conductive state.
  • the processor 410 is also configured to control the switch chip to maintain the second conductive state when the device capability information indicates that the target device does not have the data transmission capability.
  • the processor 410 is also used to control the switch chip to be in the third conduction state when the electronic device is connected to the target device through a fast charging data line and the target device meets the third condition. state;
  • the target device meeting the third condition includes: the target device is a device with data transmission capabilities but without power supply capabilities;
  • both sets of pins are used for data transmission.
  • the electronic device 400 when the electronic device is connected to the target device through a fast charging data line, if the electronic device determines that the target device satisfies the first condition and the fast charging data line satisfies the second condition, then the electronic device The switch chip in the electronic device can be controlled to be in the first conductive state, so that the electronic device can perform data transmission and fast charging respectively through two sets of pins in the female socket.
  • the input unit 404 may include a graphics processing unit (GPU) 4041 and a microphone 4042.
  • the graphics processor 4041 is responsible for the image capture device (GPU) in the video capture mode or the image capture mode. Process the image data of still pictures or videos obtained by cameras (such as cameras).
  • the display unit 406 may include a display panel 4061, which may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like.
  • the user input unit 407 includes a touch panel 4071 and at least one of other input devices 4072 . Touch panel 4071, also called touch screen.
  • the touch panel 4071 may include two parts: a touch detection device and a touch controller.
  • Other input devices 4072 may include but are not limited to physical keyboards, function keys (such as volume control keys, switch keys, etc.), trackballs, mice, and joysticks, which will not be described again here.
  • Memory 409 may be used to store software programs as well as various data.
  • the memory 409 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, Image playback function, etc.) etc.
  • memory 409 may include volatile memory or nonvolatile memory, or memory 409 may include both volatile and nonvolatile memory.
  • non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), electrically removable memory. Erase programmable read-only memory (Electrically EPROM, EEPROM) or flash memory.
  • Volatile memory can be random access memory (Random Access Memory,
  • RAM random access memory
  • DRAM synchronous dynamic random access memory
  • SDRAM double data rate synchronous dynamic random access memory
  • DDRSDRAM double data rate synchronous dynamic random access memory
  • Enhanced SDRAM Enhanced SDRAM, ESDRAM
  • Synch link DRAM SLDRAM
  • Direct Rambus RAM Direct Rambus RAM, DRRAM
  • Memory 109 in embodiments of the present application includes, but is not limited to, these and any other suitable types of memory.
  • the processor 410 may include one or more processing units; optionally, the processor 410 integrates an application processor and a modem processor, where the application processor mainly handles operations related to the operating system, user interface, application programs, etc., Modem processors mainly process wireless communication signals, such as baseband processors. It can be understood that the above modem processor may not be integrated into the processor 410.
  • Embodiments of the present application also provide a readable storage medium.
  • Programs or instructions are stored on the readable storage medium.
  • the program or instructions are executed by a processor, each process of the above fast charging method embodiment is implemented, and the same can be achieved. The technical effects will not be repeated here to avoid repetition.
  • the processor is the processor in the electronic device described in the above embodiment.
  • the readable storage medium includes computer readable storage media, such as computer read-only memory ROM, random access memory RAM, magnetic disk or optical disk, etc.
  • An embodiment of the present application further provides a chip.
  • the chip includes a processor and a communication interface.
  • the communication interface is coupled to the processor.
  • the processor is used to run programs or instructions to implement the above fast charging method embodiment. Each process can achieve the same technical effect. To avoid duplication, it will not be described again here.
  • chips mentioned in the embodiments of this application may also be called system-on-chip, system-on-a-chip, system-on-a-chip or system-on-chip, etc.
  • Embodiments of the present application provide a computer program product.
  • the program product is stored in a storage medium.
  • the program product is executed by at least one processor to implement each process of the above fast charging method embodiment, and can achieve the same technical effect. , to avoid repetition, will not be repeated here.
  • the methods of the above embodiments can be implemented by means of software plus the necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is better. implementation.
  • the technical solution of the present application can be embodied in the form of a computer software product that is essentially or contributes to the existing technology.
  • the computer software product is stored in a storage medium (such as ROM/RAM, disk , optical disk), including several instructions to cause a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in various embodiments of this application.

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Abstract

一种电子设备（10）、快充方法、装置（120）、系统（100）及可读存储介质，属于通信技术领域。电子设备（10）包括：母座（11）和开关芯片（12），母座（11）包括两组引脚（13），开关芯片（12）分别与两组引脚（13）连接；在开关芯片（12）处于第一导通状态的情况下，两组引脚（13）中的一组引脚用于充电，两组引脚（13）中的另一组引脚用于数据传输；在开关芯片（12）处于第二导通状态的情况下，两组引脚（13）均用于充电；在开关芯片（12）处于第三导通状态的情况下，两组引脚（13）均用于数据传输。

Description

电子设备、快充方法、装置、系统及可读存储介质
相关申请的交叉引用
本申请主张在2022年07月25日在中国提交的申请号为202210878430.8的中国专利的优先权，其全部内容通过引用包含于此。
技术领域
本申请属于通信技术领域，具体涉及一种电子设备、快充方法、装置、系统及可读存储介质。
背景技术
目前，随着通信技术的发展，配置有通用串行总线(Universal Serial Bus，usb)type-c接口的电子设备已经可以实现快充。
然而，在电子设备使用私有快充协议的情况下，当电子设备进行快充时，电子设备需要占用用于数据传输的引脚进行快充，因此使得电子设备在进行快充时，无法进行数据传输。
发明内容
本申请实施例的目的是提供一种电子设备、快充方法、装置、系统及可读存储介质，能够解决电子设备在使用私有快充协议进行快充时，无法进行数据传输的问题。
第一方面，本申请实施例提供了一种电子设备，包括：母座和开关芯片，母座包括两组引脚，开关芯片分别与两组引脚连接；在开关芯片处于第一导通状态的情况下，两组引脚中的一组引脚用于充电，两组引脚中的另一组引脚用于数据传输；在开关芯片处于第二导通状态的情况下，两组引脚均用于充电；在开关芯片处于第三导通状态的情况下，两组引脚均用于数据传输。
第二方面，本申请实施例提供了一种快充方法，应用于如第一方面的电子设备，该方法包括：在电子设备通过快充数据线与目标设备连接的情况下，若目标设备满足第一条件且快充数据线满足第二条件，则控制电子设备中的开关芯片处于第一导通状态；其中，目标设备满足第一条件包括：目标设备为支持专用充电端口(Dedicated Charging Port，DCP)且具备数据传输能力的设备；快充数据线满足第二条件包括：快充数据线中的两组目标引脚分别与快充数据线中的两组线缆连接。其中，两组目标引脚为快充数据线中与电子设备中的两组引脚相对应的引脚；其中，开关芯片处于第一导通状态时，两组引脚中的一组引脚用于充电，两组引脚中的另一组引脚用于数据传输。
第三方面，本申请实施例提供了一种快充装置，快充装置包括控制模块；控制模块，用于在电子设备通过快充数据线与目标设备连接的情况下，若目标设备满足第一条件且快充数据线满足第二条件，则控制电子设备中的开关芯片处于第一导通状态。其中，目标设备满足第一条件包括：目标设备为支持DCP且具备数据传输能力的设备；快充数据线满足第二条件包括：快充数据线中的两组目标引脚分别与快充数据线中的两组线缆连接；其中，两组目标引脚为快充数据线中与电子设备中的两组引脚相对应的引脚；其中，开关芯片处于第一导通状态时，两组引脚中的一组引脚用于充电，两组引脚中的另一组引脚用于数据传输。
第四方面，本申请实施例提供了一种快充系统，该快充系统包括目标设备、快充数据线和上述第一方面的电子设备，快充数据线分别与电子设备中的母座和目标设备 的端口连接；其中，快充数据线包括两组目标引脚和两组线缆，两组目标引脚分别与两组线缆连接，且两组目标引脚分别与母座中的两组引脚连接。
第五方面，本申请实施例提供了一种电子设备，该电子设备包括处理器和存储器，所述存储器存储可在所述处理器上运行的程序或指令，所述程序或指令被所述处理器执行时实现如第二方面所述的方法的步骤。
第六方面，本申请实施例提供了一种可读存储介质，所述可读存储介质上存储程序或指令，所述程序或指令被处理器执行时实现如第二方面所述的方法的步骤。
第七方面，本申请实施例提供了一种芯片，所述芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器用于运行程序或指令，实现如第二方面所述的方法。
第八方面，本申请实施例提供一种计算机程序产品，该程序产品被存储在存储介质中，该程序产品被至少一个处理器执行以实现如第二方面所述的方法。
在本申请实施例中，由于在电子设备中的开关芯片处于第一导通状态的情况下，电子设备中的母座的两组引脚中的一组引脚用于数据传输，该两组引脚中的另一组引脚可以用于数据传输；在开关芯片处于第二导通状态的情况下，两组引脚均用于充电；在开关芯片处于第三导通状态的情况下，两组引脚均用于数据传输；即开关芯片所处的导通状态不同，母座中的两组引脚可以分别用于数据传输或充电，因此当电子设备使用私有快充协议进行快充时，电子设备既可以实现快充，也可以进行数据传输。
附图说明
图1是本申请实施例提供的一种电子设备的结构示意图之一；
图2是本申请实施例提供的电子设备中的母座的结构示意图；
图3是本申请实施例提供的一种电子设备的结构示意图之二；
图4是本申请实施例提供的一种电子设备的结构示意图之三；
图5是本申请实施例提供的电子设备通过数据线与目标设备连接的示意图；
图6是本申请实施例提供的一种电子设备的结构示意图之四；
图7是本申请实施例提供的一种电子设备的结构示意图之五；
图8是本申请实施例提供的一种快充方法的流程图；
图9是本申请实施例提供的一种快充系统的结构示意图之一；
图10是本申请实施例提供的一种快充数据线的公头的结构图；
图11是本申请实施例提供的一种快充系统的结构示意图之二；
图12是本申请实施例提供的一种快充装置的结构示意图；
图13是本申请实施例提供的一种电子设备的结构示意图；
图14是本申请实施例提供的一种电子设备的硬件示意图；
其中，图1至图11中的附图标记如下：
10、电子设备；11、母座；12、开关芯片；13、两组引脚；14、第一开关组；15、
第二开关组；16、应用处理器；17、协议芯片；18、第一引脚；19、第二引脚；20、第三引脚；21、第四引脚；24、第五引脚；25、第六引脚；26、第七引脚；27、第八引脚；28、快充数据线；29、目标设备；30、第三开关；31、第四开关；32、第五开关；33、第六开关；34、第七开关；35、第八开关；36、第九开关；37、第十开关；38、第十一开关；39、第十二开关；40、第十三开关；41、第十四开关；42、供电适配器；43、转接线；44、目标设备的端口；45、两组目标引脚；46、两组线缆；100、快充系统；
a1、第一开关组的第一端；b1、第一开关组的第二端；c1、第一开关组的第三端；
e1、第一开关组的第四端；f1、第一开关组的第五端；g1、第一开关组的第六端；
a2、第二开关组的第一端；b2、第二开关组的第二端；c2、第二开关组的第三端；
e2、第二开关组的第四端；f2、第二开关组的第五端；g2、第二开关组的第六端。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书中的术语“第一”、“第二”等是用于区别类似的对象，而不用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施，且“第一”、“第二”等所区分的对象通常为一类，并不限定对象的个数，例如第一对象可以是一个，也可以是多个。此外，说明书以及权利要求中“和/或”表示所连接对象的至少其中之一，字符“/”，一般表示前后关联对象是一种“或”的关系。
下面对本申请实施例中涉及的一些术语/名词进行解释说明。
BC1.2(Battery Charging v1.2)协议定义：
BC1.2是USB标准化组织(USB-IF(Implementers Forum))下属的BC小组制定的协议，主要用于规范电池充电的需求，该协议最早基于USB2.0协议来实现。
BC1.2充电端口：
USB2.0协议规定外设从USB充电器抽取电流的最大值为500mA，500mA的电流限制无法满足日益增长的快充需求。因此，BC1.2协议引入了充电端口识别机制，主要包括以下几个USB端口类型：
1)标准下行端口(Standard Downstream Port，SDP)：SDP支持USB协议，支持的最大电流为500mA，能够理解，SDP与USB 2.0规范定义的端口相同，即SDP就是台式机和笔记本电脑常见的典型端口。
2)专用充电端口(Dedicated Charging Port，DCP)：DCP不支持数据协议，仅支持快充，可以提供大电流。例如，DCP主要用于墙充等专用充电器。
3)充电下行端口(Charging Downstream Port，CDP)：CDP既支持数据协议也支持快充，CDP可以提供1.5A的电流。
供电设备：提供电能，并通过线缆与充电设备连接，如电源适配器。
充电设备：通过电缆接收电能的设备，如移动终端、笔记本电脑等。
线缆电子标签：可以读取该线缆的属性，电源传输能力、数据传输能力、身份标识(Identity Document，ID)等信息的芯片。
USB-功率传输(Power Delivery，PD)协议：支持USB-PD协议的供电设备，例如充电器的输出接口为Type-C接口。
USB Type-C接口：USB Type-C接口是可以正反接使用的USB接口，任一方向插入均可；无论USB Type-C接口怎样插入，电源的连接都是正确的。由于插座上含有两组连在一起的数据线D+/D-，所以Type-C接口以任意方向插入时数据线都是连接的。USB Type-C接口的用于高速通讯的TX/RX不能被连接在一起，所以USB Type-C接口的CC引脚被用于对Type-C接口的插入方向进行标识，并经由硬件线路对TX/RX进行路由，确保配置正确。
进一步地，Type-C接口支持：最大功率达100W的电力传输和最高速度为10Gbps的传输速度。
Type-C接口的数据角色(Data Role)：
在USB2.0接口中，USB根据数据传输的方向定义了：主设备(Host)端口、从设备(Device)端口和(On-The-Go，OTG)端口，三种角色。其中，支持OTG的设备可以作为Host，也可以作为Device，OTG技术允许在没有主机(Host)的情况下，实 现设备间的数据传输，在Type-C接口中，修改了该定义，修改后的定义如下表a所示：
表a
目前，在没有USB-PD协议参与的情况下，USB Type-C接口的数据角色必须和电源角色保持一致。因为Type-C协议没有提供多余的机制去单独的协商数据角色，也就是供电方同时作为数据的主设备，充电方(受电方)同时作为数据的从设备。
下面结合附图，通过具体的实施例及其应用场景对本申请实施例提供的电子设备、快充方法、快充装置、快充系统及可读存储介质进行详细地说明。
在相关技术中，对于原有基于BC1.2快充协议及衍生的私有快充协议，当电子设备进行快充时，电子设备需要占用原本用于数据传输的通道进行快充(传输私有协议)，因此使得电子设备在进行快充时，无法进行数据传输。
基于上述问题，本申请实施例提供了一种电子设备，母座和开关芯片，母座包括两组引脚，开关芯片分别与两组引脚连接。该开关芯片处于不同导通状态时，这两组引脚的作用可以不同。具体的，在开关芯片处于第一导通状态的情况下，两组引脚中的一组引脚用于充电，两组引脚中的另一组引脚用于数据传输；在开关芯片处于第二导通状态的情况下，两组引脚均用于充电；在开关芯片处于第三导通状态的情况下，两组引脚均用于数据传输。如此，当电子设备使用私有快充协议进行快充时，可以通过控制开关芯片处于第一导通状态，从而可以使得电子设备同时实现快充(私有协议)和数据传输。
本申请实施例提供一种电子设备，图1示出了本申请实施例提供的一种电子设备的结构示意图。如图1所示，本申请实施例提供的电子设备10可以包括：母座11和开关芯片12，该母座11包括两组引脚13，开关芯片12分别与两组引脚13连接。
本申请实施例中，在开关芯片处于第一导通状态的情况下，该两组引脚中的一组引脚用于充电，该两组引脚中的另一组引脚用于数据传输；在开关芯片处于第二导通状态的情况下，该两组引脚均用于充电；在所述开关芯片处于第三导通状态的情况下，该两组引脚均用于数据传输。
本申请实施例中，当电子设备需求同时进行快充和数据传输时，电子设备可以控制开关芯片处于第一导通状态。具体而言，电子设备可以在电子设备与目标设备连接，且该目标设备为支持DCP且具备数据传输能力的设备时，控制开关芯片处于第一导通状态。
当电子设备仅需求充电时，电子设备可以控制开关芯片处于第二导通状态。具体而言，可以在电子设备与目标设备连接，且该目标设备为支持DCP的设备时，控制开关芯片处于第二导通状态，以增大充电功率。需要说明的是，此时目标设备可以是具备数据传输能力的设备，也可以是不具备数据传输能力的设备。也就是说，即使该目标设备是支持数据传输的，电子设备仍然将开关芯片调整至第二导通状态。
当电子设备仅需求数据传输时，电子设备可以控制开关芯片处于第三导通状态。 具体而言，可以在电子设备与目标设备连接，且该目标设备为具备数据传输能力的设备时，可以控制开关芯片处于第三导通状态，以提高数据传输功率。需要说明的是，此时目标设备可以是支持DCP的设备，也可以是不支持DCP的设备。也就是说，即使该目标设备是支持DCP，电子设备仍然将开关芯片调整至第三导通状态。
可选地，母座可以包括母座本体和两组引脚，其中，这两组引脚对称设置在母座本体的相同表面上。
示例性地，图2为母座11的结构示意图，如图2所示，母座本体的一个表面上对称设置有两排引脚位，分别为A排引脚位和B排引脚位，每排引脚位中包括12个引脚位；具体的，A排引脚位包括引脚位A1至引脚位A12，B排引脚位包括引脚位B1至引脚位B12。每个引脚位上设置一个引脚。若上述两组引脚13中的一组引脚包括D1+引脚和D1-引脚，另一组引脚包括D2+引脚和D2-引脚，则：D1+引脚可以设置在引脚位A6上，D1-引脚可以设置在引脚位A7上；D2+引脚可以设置在引脚位B6上，D2-引脚可以设置在引脚位B7上。从图2可以看出，D1+引脚与D2-引脚相对，D1-引脚与D2引脚+相对。
需要说明的是，在相关技术的母座中，D1+引脚与D2+引脚短接，D1-引脚与D2-引脚短接。即相关技术中的母座中有且只有一组D+，D-引脚。而在本申请实施例中，D1+，D1-引脚与D2+、D2-引脚相互独立，从而确保本申请实施例的母座中可以包括两组D+，D-引脚。
可选地，由于开关芯片处于第一导通状态时，两组引脚中的一组引脚用于充电，两组引脚中的另一组引脚用于数据传输。因此，当两组引脚中的一组引脚包括D1+引脚、D1-引脚，两组引脚中的另一组引脚包括D2+引脚、D2-引脚时，一种可能的情况，D1+引脚和D1-引脚用于充电，D2+引脚和D2-引脚用于数据传输；另一种可能的情况，D1+引脚和D1-引脚用于数据传输，D2+引脚和D2-引脚用于充电。
可选地，母座11除包括上述两组引脚13之外，还可以包括其他的引脚。具体的，如图2所示，母座还可以包括：
4个地引脚，分别设置在引脚位A1，引脚位B1，引脚位A12和引脚位B12；
2组发射引脚，其中，一组发射引脚包括：TX1+引脚，TX1-引脚，分别设置在引脚位A2和引脚位A3；另一组发射引脚包括：TX2+引脚，TX2-引脚，分别设置在引脚位B2、引脚位B3；
2组接收引脚，一组接收引脚包括：RX1+引脚，RX1-引脚，分别设置在引脚位B11、引脚位B10；另一组接收引脚包括：RX2+引脚，RX2-引脚，分别设置在引脚位A11，引脚位A12；
4个电缆总线电源Vbus引脚，分别设置在引脚位A4，引脚位B4，引脚位A9和引脚位B9；
2个通道设置CC引脚，分别为设置在引脚位A5和引脚位B5的CC1引脚和CC2引脚；其中，CC引脚用于传输方向确认和正反插确认，以及USB-PD通信。
2个SBU引脚，分别为设置在引脚位A8和引脚位B8；SBU引脚用于边带使用。
需要说明的是，对于母座包括的除上述2组引脚之外的其他引脚的其他作用与功能的描述具体可以参见相关技术中的相关描述。
可选地，上述母座为支持USB Type-C接口的母座。例如，母座可以为既支持USB2.0接口，又支持USB Type-C接口的母座。
可选地，结合图1，如图3所示，电子设备10还可以包括：应用处理器16和协议芯片17；开关芯片12可以包括第一开关组14和第二开关组15。快充协议芯片17用于快速充电，应用处理器16用于传输并处理数据。
在开关芯片12处于第一导通状态的情况下：上述两组引脚13中的一组引脚通过 第一开关组14与应用处理器16连接，以实现数据传输；上述两组引脚13中的另一组引脚通过第二开关组15与协议芯片17连接，以实现充电。如此，在电子设备10使用私有快充协议进行充电的情况下，由于一组引脚可以支持电子设备10进行快速充电，另一组引脚支持数据传输，因此当电子设备10采用私有协议进行快充时，电子设备10仍可以传输数据。
或者，
在开关芯片12处于第二导通状态的情况下：上述两组引脚13中的一组引脚通过第一开关组14与协议芯片17连接，以实现充电；上述两组引脚13中的另一组引脚通过第二开关组15与协议芯片17连接，以实现充电。
或者，
在开关芯片12处于第三导通状态的情况下：上述两组引脚13中的一组引脚通过第一开关组14与应用处理器16连接，以实现数据传输；上述两组引脚13中的另一组引脚通过第二开关组15与应用处理器16连接，以实现数据传输。
可以理解的是，当开关芯片处于不同的导通状态时，两组引脚对应不同的功能。
需要说明的是，上述协议芯片为电子设备中的快充协议芯片。快充协议芯片为电子设备与目标设备之间连接的桥梁，协议芯片的稳定性，对快充的体验和可靠性起到决定性的作用。一颗稳定可靠的协议芯片，可以根据电子设备的要求，实时的调节输出电压，在快充的不同阶段，提供相应的功率，保证快充稳定高速的进行。
本申请实施例中，当一组引脚用于充电时，电子设备具体可以通过该一组引脚对应的通路传输快充协议，并采用该快充协议快速充电，即进行快充。该快充协议为私有快充协议。例如，该私有快充协议为VFCP协议、UFCP协议等。
本申请实施例中，通过第一开关组和第二开关组的配合，实现开关芯片在3个导通状态之间的切换，从而使得电子设备可以通过母座中的2组引脚实现以下至少一项功能：数据传输、快速充电。如此，通过控制开关芯片中的开关处于不同的导通状态，以使电子设备具备不同的能力，进而可以提高电子设备切换能力的操作便捷性。
可选地，假设上述一组引脚可以包括第一引脚和第二引脚，上述另一组引脚包括第三引脚和第四引脚，应用处理器包括第五引脚和第六引脚；协议芯片包括第七引脚和第八引脚。那么：结合图3，如图4所示：
第一开关组14的第一端a1与第一引脚18连接，第一开关组14的第二端b1与第二引脚19连接；第二开关组15的第一端a2与第三引脚20连接，第二开关组15的第二端b2与第四引脚21连接。第一开关组14的第三端c1和第二开关组15的第三端c2均与第五引脚24连接，第一开关组14的第四端e1和第二开关组15的第四端e2均与第七引脚26连接，第一开关组14的第五端f1和第二开关组15的第五端f2均与第六引脚25连接，第一开关组14的第六端g1和第二开关组15的第六端g2均与第八引脚27连接。
可选地，假设第一引脚18为D+引脚，第二引脚19为D-引脚，第三引脚20为D+引脚，第四引脚21为D-引脚，那么：第五引脚24和第六引脚25分别为应用处理器16的D+引脚和D-引脚，第七引脚26和第八引脚27分别为协议芯片17的D+引脚和D-引脚。或者，假设第一引脚18为D-引脚，第二引脚19为D+引脚，第三引脚20为D-引脚，第四引脚21为D+引脚，那么：第五引脚24和第六引脚25分别为应用处理器16的D-引脚和D+引脚，第七引脚26和第八引脚27分别为协议芯片17的D-引脚和D+引脚。
下面结合图4对开关芯片处于不同导通状态时，两组引脚与应用处理器和快充协议芯片的连接情况进行详细说明。
可选地，在开关芯片12处于第一导通状态的情况下，第一开关组14的第一端a1 和第一开关组14的第三端c1之间导通，以使第一引脚18与应用处理器16的第五引脚24连接，且第一开关组14的第二端b1和第一开关组14的第五端f1之间导通，以使第二引脚19与应用处理器16的第六引脚25连接；第二开关组15的第一端a2与第二开关组15的第四端e2之间导通，以使第三引脚20与协议芯片17的第七引脚26连接，且第二开关组15的第二端b2与第二开关组15的第六端g2之间导通，以使第四引脚21与协议芯片17的第八引脚27连接。如此，在电子设备10使用私有快充协议进行充电的情况下，电子设备可以通过两组引脚中的一组引脚实现数据传输，并通过两组引脚中的一组引脚实现快充。
在开关芯片12处于第二导通状态的情况下，第一开关组14的第一端a1与第一开关组14的第四端e1之间导通，以使第一引脚18与协议芯片17的第七引脚26连接，且第一开关组14的第二端b1与第一开关组14的第六端g1之间导通，以使第二引脚19与协议芯片17的第八引脚27连接；第二开关组15的第一端a2与第二开关组15的第四端e2之间导通，以使第三引脚20与协议芯片17的第七引脚26连接，且第二开关组15的第二端b2与第二开关组15的第六端g2之间导通，以使第四引脚21与协议芯片17的第八引脚27连接。
在开关芯片12处于第三导通状态的情况下，第一开关组14的第一端a1与第一开关组14的第三端c1之间导通，以使第一引脚18与应用处理器16的第五引脚24连接，且第一开关组14的第二端b1与第一开关组14的第五端f1之间导通，以使第二引脚19与应用处理器16的第六引脚25连接；第二开关组15的第一端a2与第二开关组15的第三端c2之间导通，以使第三引脚20与第五引脚24连接，且第二开关组15的第二端b2与第二开关组15的第五端f2之间导通，以使第四引脚21与应用处理器16的第六引脚25连接。
如此，由于可以通过第一开关组控制两组引脚中的一组引脚与应用处理器或协议芯片连接，并通过第二开关组控制两组引脚中的另一组引脚与应用处理器或协议芯片连接，从而可以实现两组引脚的不同功能。
在可选的实施例中，第一开关组和第二开关组中的每个开关组可以包括以下之一：1个双刀双掷开关(Double Pole Double Throw，DPDT)(方式1)；2个单刀双掷开关(Single Pole Double Throw，SPDT)(方式2)；4个单刀单掷开关(方式3)。
可选地，在方式1中，如图4所示，以第一开关组14包括第一开关，第二开关组15包括第二开关，且第一开关和第二开关均为DPDT开关为例。第一开关的2个动端为第一开关组14的第一端a1和第一开关组14的第二端b1，第一开关的一个动端对应的2个定端为第一开关组14的第三端c1和第四端e1，第一开关的另一个动端对应的2个定端为第一开关组14的第五端f1和第六端f2。对应地，第二开关的2个动端为第二开关组15的第一端a2和第二端b2，第二开关的一个动端对应的2个定端为第二开关组15的第三端c2和第四端e2，第二开关的另一个动端对应的2个定端为第二开关组15的第五端f2和第六端g2。DPDT开关的每个定端可以交替与其所对应的2个动端之间导通(接触)；例如，假设DPDT开关的2个动端为动端1和动端2，则在任意时刻，DPDT开关的定端可以与动端1之间导通，或者DPDT开关的定端可以与动端2之间导通。
如此，由于第一开关分别与第一引脚、第二引脚、第五引脚、第六引脚、第七引脚和第八引脚连接，且第二开关分别与第三引脚、第四引脚、第五引脚、第六引脚、第七引脚和第八引脚连接，因此可以通过第一开关控制两组引脚中的一组引脚与应用处理器或协议芯片连接，并通过第二开关控制两组引脚中的另一组引脚与应用处理器或协议芯片连接，从而可以实现两组引脚的不同功能。
下面结合具体示例对方式1进行示例性说明。
可选地，在方式1中，如图4所示，假设第一引脚18为D1+引脚，第二引脚19为D1-引脚，第三引脚20为D2+引脚，第四引脚21为D2-引脚，第五引脚24和第六引脚25分别为应用处理器16的D+引脚和D-引脚，第七引脚26和第八引脚27分别为协议芯片17的D+引脚和D-引脚；又假设第一开关的第一定端(即第一开关组14的第三端c1)与第五引脚24间连接线缆L1，第一开关的第二定端(即第一开关组14的第四端e1)与第七引脚26间连接线缆L2，第一开关的第三定端(即第一开关组14的第五端f1)与第六引脚25间连接线缆L3，第一开关的第四定端(即第一开关组14的第六端g1)与第八引脚27间连接线缆L4；第二开关的第一定端(即第二开关组15的第三端c2)与第五引脚24间连接线缆L5，第二开关的第二定端(即第二开关组15的第四端e2)与第七引脚26间连接线缆L6，第一开关的第三定端(即第二开关组15的第五端f2)与第六引脚25间连接线缆L7，第一开关的第四定端(即第二开关组15的第六端g2)与第八引脚27间连接线缆L8。那么：
(1)当电子设备不连接设备(例如目标设备)时，电子设备默认开关芯片处于第三导通状态，即电子设备默认母座中的两组引脚均用于传输数据；具体的，参照图4，如下表1所示：
表1：开关芯片处于第三导通状态
结合表1和图4可以看出：当开关芯片处于第三导通状态时，D1+引脚通过连接线缆L1与应用处理器16的D+引脚连接，D1-引脚通过连接线缆L3与应用处理器16的D-引脚连接；D2+引脚通过连接线缆L5与应用处理器16的D+引脚连接，D2-引脚通过连接线缆L7与应用处理器16的D-引脚连接。可见，当开关芯片处于第三导通状态时，母座中的D1+引脚与D2+引脚短接，母座中的D1-引脚与D2-引脚短接，此时该母座与现有的支持私有快充协议的Type-C接口没有区别。
可选地，电子设备的母座例如Type-C接口，在没接入目标设备(例如供电设备)情况下，开关芯片的默认导通状态是第三导通状态。
可选地，电子设备通过数据线连接的目标设备支持PD协议的充电器时，电子设备可以控制开关芯片可以处于第三导通状态，以进行数据传输。
可选地，电子设备通过数据线连接的目标设备支持PD协议且支持OTG时，电子设备可以控制开关芯片可以处于第三导通状态，以进行数据传输。
可选地，电子设备通过数据线连接的目标设备为不具备供电功能的OTG设备时，电子设备可以不切换开关功能，即保持开关芯片处于第三导通状态，以使电子设备反向供电目标设备，即此时电子设备可以作为供电设备，目标设备作为充电设备。
(2)当电子设备连接的目标设备支持私有协议且支持DCP时，电子设备可以控制开关芯片处于第二导通状态，以使电子设备通过母座中的两组引脚进行快充。
表2：开关芯片处于第二导通状态
结合表2和图4可以看出，当开关芯片处于第二导通状态时，D1+引脚通过连接线缆L2与协议芯片17的D+引脚连接，D1-引脚通过连接线缆L4与协议芯片17的 D-引脚连接，D2+引脚通过连接线缆L6与协议芯片17的D+引脚连接，D2-引脚通过连接线缆L8与协议芯片17的D-引脚连接。可见，当开关芯片处于第二导通状态时，母座中的D1+引脚与D2+引脚短接，母座中的D1-引脚与D2-引脚短接，此时，母座与现有的支持私有快充协议的Type-C接口没有区别。在电子设备与目标设备断开连接(例如拔掉数据线)后，电子设备可以将开关芯片切换至第三导通状态，即恢复默认状态。
可选地，在电子设备连接的目标设备不支持OTG，例如，目标设备为不支持OTG但支持VFCP协议或UFCP协议的电源适配器(也就是电子设备与目标设备之间的快充协议数据需要走D+，D-引脚)时，电子设备可以在开关芯片处于第三导通状态的情况下，先判断目标设备是否为支持DCP的设备。若电子设备判断目标设备为支持DCP的设备，则电子设备可以将开关芯片由第三导通状态切换至第二导通状态，以使电子设备可以通过目标设备进行快速充电或执行其他操作，例如获取目标设备的设备能力信息。
对于电子设备判断目标设备是否为支持DCP的设备的具体方法参见下述快充方法实施例中的相关描述。
(3)当母座连接的目标设备支持私有协议且支持OTG时，电子设备可以控制开关芯片处于第一导通状态，使得母座中的一组引脚用于传输数据，另一组引脚用于充电。具体的，参照图4，如表3所示：
表3：开关芯片处于第一导通状态
结合表3和图4可以看出，当数据线与母座正接时，D1+引脚通过连接线缆L1与应用处理器16的D+引脚连接，D1-引脚通过连接线缆L3与应用处理器16的D-引脚连接，D2+引脚通过连接线缆L6与协议芯片17的D+引脚连接，D2-引脚通过连接线缆L8与协议芯片17的D-引脚连接；即当数据线与母座正接时，D1+引脚和D1-引脚这一组引脚用于数据传输，D2+引脚与D2-引脚这一组引脚用于快充。
当数据线与母座反接时，D1+引脚通过连接线缆L2与协议芯片17的D+引脚连接，D1-引脚通过连接线缆L4与协议芯片17的D-引脚连接，D2+引脚通过连接线缆L5与应用处理器的D+引脚连接，D2-引脚通过连接线缆L7与应用处理器16的D-引脚连接；即当数据线与母座反接时，D1+引脚和D1-引脚这一组引脚用于快充，D2+引脚与D2-引脚这一组引脚用于数据传输。
可以理解，当母座支持Type-C接口时，数据线与母座既可以正接，也可以反接。这两种接通方式均能保证一组引脚用于数据传输，另一组引脚用于快充，因此这两种方式均属于第一导通状态。
可选地，本申请实施例中，当电子设备的母座通过数据线与目标设备，具体为USB扩展坞连接时，电子设备可以通过数据线的CC引脚确定数据线与母座间连接的正反 方向。例如，图5为母座11通过快充数据线28与目标设备29连接的结构示意图，图5中的(a)所示为快充数据线28与母座11正接的示意图，图5中的(b)所示为数据线28与母座11反接的示意图。
可选地，在方式2中，结合图4，如图6所示，第一开关组14包括第三开关30、第四开关31；第二开关组15包括第五开关32和第六开关33，且第三开关30、第四开关31、第五开关32和第六开关33均为SPDT开关。
具体的，第三开关30的动端为第一开关组14的第一端a1，第三开关30的一个定端为第一开关组14的第三端c1，第三开关30的另一个定端为第一开关组14的第四端e1；第四开关31的动端为第一开关组14的第二端b1；第四开关31的一个定端为第一开关组14的第五端f1，第四开关31的另一个定端为第一开关组14的第六端g1；第五开关32的动端为第二开关组15的第一端a2，第五开关32的一个定端为第二开关组15的第三端c2，第五开关32的另一个定端为第二开关组15的第四端e2；第六开关33的动端为第二开关组15的第二端b2；第六开关33的一个定端为第二开关组15的第五端f2，第六开关33的另一个定端为第二开关组15的第六端g2。
下面结合具体示例对方式2进行详细说明。
示例性地，如图6所示，假设第一引脚为D1+引脚，第二引脚19为D1-引脚，第三引脚为D2+引脚，第四引脚为D2-引脚，第五引脚和第六引脚分别为应用处理器的D+引脚和D-引脚，第七引脚和第八引脚分别为协议芯片的D+引脚和D-引脚；第一开关组14包括第三开关30、第四开关31；第二开关组15包括第五开关32和第六开关33。那么：
开关芯片12处于第一导通状态具体为：第三开关30的动端(即第一开关组14的第一端a1)与第三开关30的一个定端(即第一开关组14的第三端c1)之间导通，使得第一引脚18与应用处理器16的第五引脚24连接；第四开关31的动端(即第一开关组14的第二端b1)与第四开关31的一个定端(即第一开关组14的第五端f1)之间导通，使得第二引脚19与应用处理器16的第六引脚25连接；第五开关32的动端(即第二开关组15的第一端a2)与第五开关32的一个定端(即第二开关组15的第四端e2)之间导通，使得第三引脚20与协议芯片17的第七引脚26连接；第六开关33的定端(即第二开关组15的第二端b2)与第六开关33的另一个定端(即第二开关组15的第六端g2)之间导通，使得第四引脚21与协议芯片17的第八引脚27连接。如此可以实现上述两组引脚13中的一组引脚用于数据传输，另一组引脚用于充电。
开关芯片处于第二导通状态具体为：第三开关30的动端(即第一开关组14的第一端a1)与第三开关30的另一个定端(即第一开关组14的第四端e1)之间导通，使得第一引脚18与协议芯片17的第七引脚26连接；第四开关31的动端(即第一开关组14的第二端b1)与第四开关31的另一个定端(即第一开关组14的第六端g1)之间导通，使得第二引脚19与协议芯片17的第八引脚27连接；第五开关32的动端(即第二开关组15的第一端a2)与第五开关32的另一个定端(即第二开关组15的第四端e2)之间导通，使得第三引脚20与协议芯片17的第七引脚26连接；第六开关33的动端(即第二开关组15的第二端b2)与第六开关33的另一个定端(即第二开关组15的第六端g2)之间导通，使得第四引脚21与协议芯片17的第八引脚27连接。如此可以实现上述两组引脚13中的均用于充电。
开关芯片处于第三导通状态具体为：第三开关30的动端(第一开关组14的第一端a1)与第三开关30的一个定端(即第一开关组14的第三端c1)之间导通，使得第一引脚18与应用处理器16的第五引脚24连接；第四开关31的动端(即第一开关组14的第二端b1)与第四开关31的一个定端(即第一开关组14的第五端f1)之间导通，使得第二引脚19与应用处理器16的第六引脚25连接；第五开关32的动端(即第二 开关组15的第一端a2)与第五开关32的一个定端(即第二开关组15的第三端c2)之间导通，使得第三引脚20与应用处理器16的第五引脚24连接；第六开关33的动端(即第二开关组15的第二端b2)与第六开关33的一个定端(第二开关组15的第五端f2)之间导通，使得第四引脚21与应用处理器16的第六引脚25连接。如此可以实现上述两组引脚13中的一组引脚用于数据传输，另一组引脚用于充电。
如此，在方式2中，由于母座的两组引脚中的每个引脚可以通过开关芯片中的一个SPDT开关实现与应用处理器或协议芯片的连接，因此可以实现母座中的两组引脚的不同功能。
可选地，在方式3中，结合图4，如图7所示，上述两组引脚13中的一组引脚包括第一引脚18和第二引脚19，上述两组引脚13中的另一组引脚可以包括第三引脚20和第四引脚21；第一开关组14可以包括第七开关34、第八开关35、第九开关36和第十开关37，第二开关组15可以包括第十一开关38、第十二开关39、第十三开关40和第十四开关41；应用处理器16包括第五引脚24和第六引脚25，协议芯片17包括第七引脚26和第八引脚27。
其中，第七开关34的动端和第八开关35的动端均与第一引脚18连接，第九开关36的动端和第十开关37的动端均与第二引脚19连接，第十一开关38和第十二开关39的动端均与第三引脚20连接，第十三开关40的动端和第十四开关41的动端均与第四引脚21连接；第七开关34的定端和第十一开关38的定端与第五引脚24连接，第九开关36和第十三开关40的定端均与第六引脚25连接。第八开关35的定端和第十二开关39的定端均与第七引脚26连接；第十开关37的定端和第十四开关41的定端均与第八引脚27连接。
可以看出，第七开关34和第八开关35的动端构成第一开关组14的第一端，第九开关36和第十开关37的定端构成第一开关组14的第二端，第七开关34的定端为第一开关组14的第三端，第八开关35的定端为第一开关组14的第四端，第九开关36的定端为第一开关组14的第五端，第十开关37的定端为第一开关组14的第六端；第十一开关38和第十二开关39的动端构成第二开关组15的第一端，第十三开关40和第十四开关41的定端构成第二开关组15的第二端，第十一开关38的定端为第二开关组15的第三端，第十二开关39的定端为第二开关组15的第四端，第十三开关40的定端为第二开关组15的第五端，第十四开关41的定端为第二开关组15的第六端。
需要说明的是，在方式3中开关的“动端”和“定端”仅用于区分开关的两个端子，并不对开关的种类构成限定。
可选地，在方式3中，参照图7，开关芯片12处于第一导通状态具体为：第七开关34闭合，第八开关35断开；且第九开关36闭合，第十开关37断开，使得第一引脚18通过第七开关34与应用处理器16的第五引脚24连接，第二引脚19通过第九开关36与应用处理器16的第六引脚25连接；第十一开关38断开，第十二开关39闭合，且第十三开关40断开，第十四开关41闭合，使得第三引脚20通过第十二开关39与协议芯片17的第七引脚26连接，第四引脚21通过第十四开关41与协议芯片17的第八引脚27连接。如此可以通过第一引脚18和第二引脚19进行数据传输，并通过第三引脚20和第四引脚21进行快充。
开关芯片12处于第二导通状态具体为：第七开关34断开，第八开关35闭合；且第九开关36断开，第十开关37闭合，使得第一引脚18通过第八开关35与协议芯片17的第七引脚26连接，第二引脚19通过第十开关37与协议芯片17的第八引脚27连接；第十一开关38断开，第十二开关39闭合，且第十三开关40断开，第十四开关41闭合，使得第三引脚20通过第十二开关39与协议芯片17的第七引脚26连接，第四引脚21通过第十四开关41与协议芯片17的第八引脚27连接。如此可以通过两组 引脚13进行快充。
开关芯片12处于第三导通状态具体为：第七开关34闭合，第八开关35断开；且第九开关36闭合，第十开关37断开，以使得第一引脚18通过第七开关34与应用处理器16的第五引脚24连接，第二引脚19通过第九开关36与应用处理器16的第六引脚25连接；第十一开关38闭合，第十二开关39断开，且第十三开关40闭合，第十四开关41断开，使得第三引脚20通过第十一开关38与应用处理器16的第五引脚24连接，第四引脚21通过第十三开关40与应用处理器16的第六引脚25连接。如此可以通过两组引脚13进行数据传输。
对于方式2和方式3的其他描述，具体可以参见上述方式1中的相关描述。
如此，在方式3中，由于母座的两组引脚中的每个引脚可以通过开关芯片中的2个开关实现与应用处理器或协议芯片的连接，因此可以实现母座中的两组引脚的不同功能。
在本申请实施例提供的电子设备中，由于在电子设备中的开关芯片处于第一导通状态的情况下，电子设备中的母座的两组引脚中的一组引脚用于数据传输，该两组引脚中的另一组引脚可以用于数据传输；在开关芯片处于第二导通状态的情况下，两组引脚均用于充电；在开关芯片处于第三导通状态的情况下，两组引脚均用于数据传输；即开关芯片所处的导通状态不同，母座中的两组引脚可以分别用于数据传输或充电，因此当电子设备使用私有快充协议进行快充时，电子设备既可以实现快充，也可以进行数据传输。
如图8所示，本申请实施例还提供一种快充方法，应用于上述实施例中的电子设备，图8示出了本申请实施例提供的一种快充方法的流程图。如图8所示，本申请实施例提供的快充方法可以包括下述的步骤101。下面以电子设备执行该方法为例进行示例性地说明。
步骤101、在电子设备通过快充数据线与目标设备连接的情况下，若目标设备满足第一条件且快充数据线满足第二条件，则电子设备控制电子设备中的开关芯片处于第一导通状态。
其中，目标设备满足第一条件包括：目标设备为支持DCP的设备且目标设备为具备数据传输能力的设备；快充数据线满足第二条件包括：快充数据线中的两组目标引脚分别与快充数据线中的两组线缆连接。其中，两组目标引脚为快充数据线中与电子设备中的两组引脚相对应的引脚。
其中，开关芯片处于第一导通状态时，母座中的两组引脚中的一组引脚用于充电，两组引脚中的另一组引脚用于数据传输。
可以理解，电子设备的两组引脚为上述电子设备实施例中母座的两组引脚，具体为母座中的两组D+引脚、D-引脚。两组目标引脚中的每组目标引脚均包括一个D+引脚和一个D-引脚。
两组目标引脚与电子设备中的两组引脚相对应可以理解为：两组目标引脚中的D+引脚与两组引脚中的D+引脚一一对应，两组目标引脚中的D-引脚与两组引脚中的D-引脚一一对应。
可选地，上述目标设备可以为具备以下至少一种能力的设备：具备快充功能、具备数据传输功能。
可选地，目标设备可以为：电源适配器、USB扩展坞等。
对于电子设备、第一导通状态的详细描述，可以参照上述电子设备实施例中的相关描述，本申请实施例对此不再赘述。
可选地，在上述步骤101之后，如果电子设备和目标设备开始进入快充功能和数据传输功能，那么：可以通过目标设备向电子设备充电，且电子设备和目标设备可以 进行数据传输，例如，进行文本传输、音频传输和视频传输等。
可选地，在上述步骤101之后，本申请实施例提供的快充方法还可以包括：在开关芯片处于第一导通状态的情况下，电子设备进入充电模式；在电子设备与快充数据线断开连接之后，电子设备可以控制开关芯片处于第三导通状态。其中，开关芯片处于第三导通状态时，电子设备中的两组引脚均用于数据传输。
本申请实施例提供的快充方法，在电子设备通过快充数据线与目标设备连接的情况下，由于快充装置可以在目标设备满足第一条件且快充数据线满足第二条件时，控制电子设备中的开关芯片处于第一导通状态，使得电子设备可以通过母座中的两组引脚分别进行数据传输和快充。
可选地，上述步骤101具体可以通过下述的步骤101a至步骤101c实现。
步骤101a、在电子设备通过快充数据线与目标设备连接的情况下，且在目标设备为支持DCP的设备的情况下，电子设备控制开关芯片处于第二导通状态。
其中，开关芯片处于所述第二导通状态时，两组引脚均用于充电。
可以理解，在电子设备通过快充数据线与目标设备连接的情况下，电子设备可以先获取目标设备的端口类型信息，并通过该端口类型信息判断目标设备是否为支持DCP的设备。该端口类型信息可以包括目标设备的端口标识、目标设备的端口支持的最大电流等信息。
具体地，在电子设备与目标设备连接之后，默认开关芯片处于第三导通状态，在第三导通状态下，电子设备可以基于BC1.2协议，获取目标设备的端口类型信息，并通过获取到的端口类型信息，判断目标设备是否为支持DCP的设备。在判断目标设备为支持DCP的设备后，电子设备可以将开关芯片由第三导通状态切换至第二导通状态，使得电子设备可以在第二导通状态下，获取目标设备的设备能力信息；当然，如果目标设备不支持DCP，则电子设备可以结束判断或执行其他处理。
例如，若目标设备为不支持DCP的设备，则电子设备可以为支持以下任一项的设备：SDP、CDP。对于SDP和CDP的描述参见上述名词解释部分的相关描述。
可以理解，本申请实施例中，电子设备将开关状态切换至第二导通状态的目的是：一方面，在第二导通状态下，电子设备可以获取目标设备的设备能力信息；另一方面，当目标设备为支持DCP的设备时，电子设备可以通过目标设备进行快充。
其中，在开关芯片处于第二导通状态的情况下，电子设备可以启动快充协议握手检测，从而电子设备可以通过快充协议与目标设备建立通信连接，从而可以获取目标设备的设备能力信息。
步骤101b、电子设备获取目标设备的设备能力信息，以及快充数据线的参数信息。
其中，上述设备能力信息指示目标设备的数据传输能力。
步骤101c、电子设备在设备能力信息指示目标设备具备数据传输能力，以及根据参数信息确定快充数据线满足第二条件的情况下，控制开关芯片由第二导通状态切换至第一导通状态。
本申请实施例中，若设备能力信息指示目标设备具备数据传输能力，则电子设备可以继续判断快充数据线是否满足第二条件，若判断快充数据线满足第二条件，则电子设备可以控制开关芯片由第二导通状态切换至第一导通状态；若设备能力信息指示目标设备不具备数据传输能力，则电子设备可以进入快充功能。
本申请实施例提供的快充方法，在电子设备通过快充数据线与目标设备连接的情况下电子设备可以在判断目标设备为支持DCP的设备的情况下，控制开关芯片切换至第二导通状态，使得电子设备可以继续判断目标设备是否具备数据传输能力，以及判断快充线缆是否满足第二条件，从而可以实现对目标设备的能力和快充数据线的能力的准确判断。
可选地，本申请实施例中，在上述步骤101b之后，本申请实施例提供的快充方法还可以包括下述的步骤102。
步骤102、电子设备在设备能力信息指示目标设备不具备数据传输能力的情况下，控制开关芯片保持第二导通状态。如此，电子设备可以通过目标设备进行快充。
可选地，在上述步骤100之后，本申请实施例提供的快充方法还可以包括下述的步骤103。
步骤103、在目标设备满足第三条件的情况下，电子设备控制开关芯片处于第三导通状态。
其中，目标设备满足第三条件包括：目标设备为具备数据传输能力且不具备供电能力的设备。
本申请实施例中，开关芯片处于第三导通状态时，电子设备中的两组引脚均用于数据传输。
可选地，本申请实施例提供的快充方法可以兼容PD协议，即对于支持PD协议的目标设备，若该目标设备具备数据传输能力，则电子设备也可以控制开关芯片处于第三导通状态。
可以理解，实际实现中，电子设备可以默认开关芯片处于第三导通状态，那么当目标设备具备数据传输能力时，电子设备即可以保持开关芯片处于第三导通状态，并执行高速数据传输功能。
当然，若该目标设备具备供电能力，则电子设备可以输出提示信息，以提示用户选择开关芯片的导通状态，例如，选择“仅数据传输”，则电子设备控制开关芯片处于第三导通状态；若选择“充电并数据传输”，则电子设备可以执行上述步骤101，若选择“仅充电”，则电子设备可以判断目标设备是否为支持DCP的设备，并执行与判断结果对应的操作。
如此，由于当目标设备具备数据传输能力且不具备供电能力时，电子设备可以控制开关芯片处于第三导通状态，因此开使得电子设备可以与目标设备间进行快速数据传输。
如图9所示，本申请实施例提供一种快充系统。图9中的快充系统100可以包括目标设备29、快充数据线28和如上述电子设备实施例中的电子设备10，快充数据线28分别与电子设备10的母座11和目标设备29的端口44连接。其中，快充数据线28可以包括两组目标引脚45和两组线缆46，两组线缆46分别与两组目标引脚45连接，两组目标引脚45与母座11中的两组引脚13连接。
本申请实施例中，每组目标引脚均包括一个D+引脚和一个D-引脚。
本申请实施例中，每组线缆中可以包括2根线缆，且每组线缆中的不同线缆与一组目标引脚中的不同引脚连接，即每根线缆与一组目标引脚中的一个引脚连接。
需要说明是，快充数据线中两组目标引脚与电子设备的母座中的两组引脚一一对应。
相关技术中的快充数据线中的两组D+、D-引脚中的一组D+、D-引脚连接线缆，另一组D+、D-引脚不连接线缆；或者相关技术中的快充数据线中的两组D+、D-引脚短接，即连接相同线缆。参照图9，本申请实施例还可以提供一种快充数据线28，该快充数据线28包括两组目标引脚45和两组线缆46，两组线缆46分别与两组目标引脚45连接。相比与相关技术，本申请实施例提供的快充线缆中两组目标引脚与不同线缆连接。
可选地，上述两组目标引脚可以设置在快充数据线的公头中。
示例性地，图10为快充数据线的公头的结构示意图。该公头包括A1至A12、B1至B12这24个引脚。两组目标引脚中的一组目标引脚包括设置在A6位置的D1+引脚、 设置在A7位置的D1-引脚，两组目标引脚中的另一组引脚包括设置在B6位置的D2+引脚、设置在B7位置的D2-引脚。对于公头的其他引脚的描述，具体可以参见相关技术中的相关描述。
如此，当快充数据线与电子设备中的母座连接时，两组目标引脚中的一组目标引脚与母座中的一组引脚连接，所形成的通路可以用于充电或数据传输；两组目标引脚中的另一组目标引脚与母座中的另一组引脚连接所形成的通路可以用于数据传输或充电，使得该快充系统可以实现快充和/或数据传输。
可选地，结合图9，如图11所示，当目标设备29为USB扩展坞时，上述快充系统100中还可以包括供电适配器42和转接线43；快充数据线28分别与USB扩展坞的一个端口和电子设备10中的母座11连接，USB扩展坞的另一个端口通过转接线43与供电适配器42连接。
可选地，电源适配器可以与交流电源连接。例如，交流电源可以提供110～220V的交流电(Alternating Current，AC)。
本申请实施例提供的快充系统，在快充数据线分别与电子设备的母座和目标设备的端口连接的情况下，由于快充数据线包括两组目标引脚和两组线缆，且该两组线缆中的每组线缆分别与两组目标引脚连接，两组目标引脚与母座中的两组引脚连接，因此两组目标引脚中的一组目标引脚与母座中的一组引脚连接所形成的通路可以用于充电或数据传输；两组目标引脚中的另一组目标引脚与母座中的另一组引脚连接所形成的通路可以用于数据传输或充电。如此，该快充系统可以同时实现快充和数据传输中的至少一项。
本申请实施例提供的快充方法，执行主体可以为快充装置(例如，快充装置为电子设备或为电子设备上的外接设备)。本申请实施例中以快充装置执行快充的方法为例，说明本申请实施例提供的快充装置。
本申请实施例还提供一种快充装置，图12示出了本申请实施例提供的一种快充装置的结构示意图。如图12所示，本申请实施例提供一种快充装置，该快充装置120可以包括：控制模块121；
控制模块121，用于在电子设备通过快充数据线与目标设备连接的情况下，若目标设备满足第一条件且快充数据线满足第二条件，则控制电子设备中的开关芯片处于第一导通状态；
其中，目标设备满足第一条件包括：目标设备为支持DCP且具备数据传输能力的设备；
快充数据线满足第二条件包括：快充数据线中的两组目标引脚分别与快充数据线中的两组线缆连接；
其中，两组目标引脚为快充数据线中与电子设备中的两组引脚相对应的引脚；
其中，开关芯片处于第一导通状态时，两组引脚中的一组引脚用于充电，两组引脚中的另一组引脚用于数据传输。
一种可能的实现方式中，快充装置还包括：获取模块。控制模块121，具体用于在目标设备为支持DCP的设备的情况下，控制开关芯片处于第二导通状态，其中，开关芯片处于第二导通状态时，两组引脚均用于充电；
获取模块，用于获取目标设备的设备能力信息，以及快充数据线的参数信息；
控制模块121，具体用于在获取模块获取的设备能力信息指示目标设备具备数据传输能力，以及根据参数信息确定快充数据线满足第二条件的情况下，控制开关芯片由第二导通状态切换至第一导通状态。
一种可能的实现方式中，控制模块121，还用于在设备能力信息指示目标设备不具备数据传输能力的情况下，控制开关芯片保持第二导通状态。
一种可能的实现方式中，控制模块121，还用于在电子设备通过快充数据线与目标设备连接的情况下，在目标设备满足第三条件的情况下，控制开关芯片处于第三导通状态；
其中，目标设备满足第三条件包括：目标设备为具备数据传输能力且不具备供电能力的设备；
其中，开关芯片处于第三导通状态时，两组引脚均用于数据传输。
本申请实施例提供的快充装置，在电子设备通过快充数据线与目标设备连接的情况下，由于若电子设备判断目标设备满足第一条件且快充数据线满足第二条件，则电子设备可以控制电子设备中的开关芯片处于第一导通状态，使得电子设备可以通过母座中的两组引脚分别进行数据传输和快充。
本申请实施例中的快充装置可以是电子设备，也可以是电子设备中的部件，例如集成电路或芯片。该电子设备可以是终端，也可以为除终端之外的其他设备。示例性的，电子设备可以为手机、平板电脑、笔记本电脑、掌上电脑、车载电子设备、移动上网装置(Mobile Internet Device，MID)、增强现实(augmented reality，AR)/虚拟现实(virtual reality，VR)设备、机器人、可穿戴设备、超级移动个人计算机(ultra-mobile personal computer，UMPC)、上网本或者个人数字助理(personal digital assistant，PDA)等，还可以为服务器、网络附属存储器(Network Attached Storage，NAS)、个人计算机(personal computer，PC)、电视机(television，TV)、柜员机或者自助机等，本申请实施例不作具体限定。
本申请实施例中的快充装置可以为具有操作系统的装置。该操作系统可以为安卓(Android)操作系统，可以为ios操作系统，还可以为其他可能的操作系统，本申请实施例不作具体限定。
本申请实施例提供的快充装置能够实现图8的方法实施例实现的各个过程，为避免重复，这里不再赘述。
可选地，如图13所示，本申请实施例还提供一种电子设备300，包括处理器301和存储器302，存储器302上存储有可在处理器301上运行的程序或指令，该程序或指令被处理器301执行时实现上述快充方法实施例的各个步骤，且能达到相同的技术效果，为避免重复，这里不再赘述。
需要说明的是，本申请实施例中的电子设备包括上述的移动电子设备和非移动电子设备。
图14为实现本申请实施例的一种电子设备的硬件结构示意图。
该电子设备400包括但不限于：射频单元401、网络模块402、音频输出单元403、输入单元404、传感器405、显示单元406、用户输入单元407、接口单元408、存储器409、以及处理器410等部件。
本领域技术人员可以理解，电子设备400还可以包括给各个部件供电的电源(比如电池)，电源可以通过电源管理系统与处理器410逻辑相连，从而通过电源管理系统实现管理充电、放电、以及功耗管理等功能。图13中示出的电子设备结构并不构成对电子设备的限定，电子设备可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置，在此不再赘述。
其中，处理器410，用于在电子设备通过快充数据线与目标设备连接的情况下，判断目标设备是否满足第一条件，且判断快充数据线是否满足第二条件；
处理器410，用于在电子设备通过快充数据线与目标设备连接的情况下，若目标设备满足第一条件且快充数据线满足第二条件，则控制电子设备中的开关芯片处于第一导通状态；
其中，目标设备满足第一条件包括：目标设备为支持DCP且具备数据传输能力的 设备；
快充数据线满足第二条件包括：快充数据线中的两组目标引脚分别与快充数据线中的两组线缆连接；
其中，两组目标引脚为快充数据线中与电子设备中的两组引脚相对应的引脚；
其中，开关芯片处于第一导通状态时，两组引脚中的一组引脚用于充电，两组引脚中的另一组引脚用于数据传输。
一种可能的实现方式中，处理器410，具体用于在目标设备为支持DCP的设备的情况下，控制开关芯片处于第二导通状态，其中，开关芯片处于第二导通状态时，两组引脚均用于充电；
获取模块，用于获取目标设备的设备能力信息，以及快充数据线的参数信息；
处理器410，具体用于在获取模块获取的设备能力信息指示目标设备具备数据传输能力，以及根据参数信息确定快充数据线满足第二条件的情况下，控制开关芯片由第二导通状态切换至第一导通状态。
一种可能的实现方式中，处理器410，还用于在设备能力信息指示目标设备不具备数据传输能力的情况下，控制开关芯片保持第二导通状态。
一种可能的实现方式中，处理器410，还用于在电子设备通过快充数据线与目标设备连接的情况下，在目标设备满足第三条件的情况下，控制开关芯片处于第三导通状态；
其中，目标设备满足第三条件包括：目标设备为具备数据传输能力且不具备供电能力的设备；
其中，开关芯片处于第三导通状态时，两组引脚均用于数据传输。
本申请实施例提供的电子设备400，在电子设备通过快充数据线与目标设备连接的情况下，由于若电子设备判断目标设备满足第一条件且快充数据线满足第二条件，则电子设备可以控制电子设备中的开关芯片处于第一导通状态，使得电子设备可以通过母座中的两组引脚分别进行数据传输和快充。
应理解的是，本申请实施例中，输入单元404可以包括图形处理器(graphics processing unit，GPU)4041和麦克风4042，图形处理器4041对在视频捕获模式或图像捕获模式中由图像捕获装置(如摄像头)获得的静态图片或视频的图像数据进行处理。显示单元406可包括显示面板4061，可以采用液晶显示器、有机发光二极管等形式来配置显示面板4061。用户输入单元407包括触控面板4071以及其他输入设备4072中的至少一种。触控面板4071，也称为触摸屏。触控面板4071可包括触摸检测装置和触摸控制器两个部分。其他输入设备4072可以包括但不限于物理键盘、功能键(比如音量控制按键、开关按键等)、轨迹球、鼠标、操作杆，在此不再赘述。
存储器409可用于存储软件程序以及各种数据。存储器409可主要包括存储程序或指令的第一存储区和存储数据的第二存储区，其中，第一存储区可存储操作系统、至少一个功能所需的应用程序或指令(比如声音播放功能、图像播放功能等)等。此外，存储器409可以包括易失性存储器或非易失性存储器，或者，存储器409可以包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，
RAM)，静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic
RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDRSDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器 (Synch link DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DRRAM)。本申请实施例中的存储器109包括但不限于这些和任意其它适合类型的存储器。
处理器410可包括一个或多个处理单元；可选的，处理器410集成应用处理器和调制解调处理器，其中，应用处理器主要处理涉及操作系统、用户界面和应用程序等的操作，调制解调处理器主要处理无线通信信号，如基带处理器。可以理解的是，上述调制解调处理器也可以不集成到处理器410中。
本申请实施例还提供一种可读存储介质，所述可读存储介质上存储有程序或指令，该程序或指令被处理器执行时实现上述快充方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
其中，所述处理器为上述实施例中所述的电子设备中的处理器。所述可读存储介质，包括计算机可读存储介质，如计算机只读存储器ROM、随机存取存储器RAM、磁碟或者光盘等。
本申请实施例另提供了一种芯片，所述芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器用于运行程序或指令，实现上述快充方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
应理解，本申请实施例提到的芯片还可以称为系统级芯片、系统芯片、芯片系统或片上系统芯片等。
本申请实施例提供一种计算机程序产品，该程序产品被存储在存储介质中，该程序产品被至少一个处理器执行以实现如上述快充方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。此外，需要指出的是，本申请实施方式中的方法和装置的范围不限按示出或讨论的顺序来执行功能，还可包括根据所涉及的功能按基本同时的方式或按相反的顺序来执行功能，例如，可以按不同于所描述的次序来执行所描述的方法，并且还可以添加、省去、或组合各种步骤。另外，参照某些示例所描述的特征可在其他示例中被组合。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以计算机软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端(可以是手机，计算机，服务器，或者网络设备等)执行本申请各个实施例所述的方法。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。

Claims (19)

  1. 一种电子设备，包括：母座和开关芯片，所述母座包括两组引脚，所述开关芯片分别与所述两组引脚连接；
    在所述开关芯片处于第一导通状态的情况下，所述两组引脚中的一组引脚用于充电，所述两组引脚中的另一组引脚用于数据传输；
    在所述开关芯片处于第二导通状态的情况下，所述两组引脚均用于充电；
    在所述开关芯片处于第三导通状态的情况下，所述两组引脚均用于数据传输。
  2. 根据权利要求1所述的电子设备，其中，所述电子设备还包括：协议芯片和应用处理器；
    所述开关芯片包括第一开关组和第二开关组；
    在所述开关芯片处于所述第一导通状态的情况下，所述一组引脚通过所述第一开关组与所述应用处理器连接，以实现数据传输；所述另一组引脚通过所述第二开关组与所述协议芯片连接，以实现充电；
    在所述开关芯片处于所述第二导通状态的情况下，所述一组引脚通过所述第一开关组与所述协议芯片连接，以实现数据传输；所述另一组引脚通过所述第二开关组与所述协议芯片连接，以实现数据传输；
    在所述开关芯片处于第三导通状态的情况下，所述一组引脚通过所述第一开关组与所述应用处理器连接，以实现充电；所述另一组引脚通过所述第二开关组与所述应用处理器连接，以实现充电。
  3. 根据权利要求2所述的电子设备，其中，所述一组引脚包括第一引脚和第二引脚，所述另一组引脚包括第三引脚和第四引脚，所述应用处理器包括第五引脚和第六引脚；所述协议芯片包括第七引脚和第八引脚；
    所述第一开关组的第一端与所述第一引脚连接，所述第一开关组的第二端与所述第二引脚连接；
    所述第二开关组的第一端与所述第三引脚连接，所述第二开关组的第二端与所述第四引脚连接；
    所述第一开关组的第三端和所述第二开关组的第三端均与所述第五引脚连接，所述第一开关组的第四端和所述第二开关组的第四端均与所述第七引脚连接，所述第一开关组的第五端和所述第二开关组的第五端均与所述第六引脚连接，所述第一开关组的第六端和所述第二开关组的第六端均与所述第八引脚连接。
  4. 根据权利要求3所述的电子设备，其中，
    在所述开关芯片处于所述第一导通状态的情况下，所述第一开关组的第一端和所述第一开关组的第三端之间导通，以使所述第一引脚与所述应用处理器的所述第五引脚连接，且所述第一开关组的第二端和所述第一开关组的第五端之间导通，以使所述第二引脚与所述应用处理器的第六引脚连接；所述第二开关组的第一端与第二开关组的第四端之间导通，以使所述第三引脚与所述协议芯片的所述第七引脚连接，且所述第二开关组的第二端与所述第二开关组的第六端之间导通，以使所述第四引脚与所述协议芯片的所述第八引脚连接；
    在所述开关芯片处于所述第二导通状态的情况下，所述第一开关组的第一端与所述第一开关组的第四端之间导通，以使所述第一引脚与所述协议芯片的所述第七引脚连接，且所述第一开关组的第二端与所述第一开关组的第六端之间导通，以使所述第二引脚与所述协议芯片的所述第八引脚连接；所述第二开关组的第一端与所述第二开关组的第四端之间导通，以使所述第三引脚与所述协议芯片的所述第七引脚连接，且所述第二开关组的第二端与所述第二开关组的第六端之间导通，以使所述第四引脚与所述协议芯片的所述第八引脚连接；
    在所述开关芯片处于所述第三导通状态的情况下，所述第一开关组的第一端与所述第一开关组的第三端之间导通，以使所述第一引脚与所述应用处理器的所述第五引脚连接，且所述第一开关组的第二端与所述第一开关组的第五端之间导通，以使所述第二引脚与所述应用处理器的所述第六引脚连接；所述第二开关组的第一端与所述第二开关组的第三端之间导通，以使所述第三引脚与应用处理器的所述第五引脚连接，且所述第二开关组的第二端与所述第二开关组的第五定端之间导通，以使所述第四引脚与所述应用处理器的所述第六引脚连接。
  5. 根据权利要1至4中任一项所述的电子设备，其中，所述两组引脚中的每组引脚包括一个D+引脚和一个D-引脚。
  6. 一种快充方法，应用于如权利要求1至5中任一项所述的电子设备，所述方法包括：
    在所述电子设备通过快充数据线与目标设备连接的情况下，若所述目标设备满足第一条件且所述快充数据线满足第二条件，则控制所述电子设备中的开关芯片处于第一导通状态；
    其中，所述目标设备满足第一条件包括：所述目标设备为支持专用充电端口DCP且具备数据传输能力的设备；
    所述快充数据线满足第二条件包括：所述快充数据线中的两组目标引脚分别与所述快充数据线中的两组线缆连接；
    其中，所述两组目标引脚为所述快充数据线中与所述电子设备中的两组引脚相对应的引脚；
    其中，所述开关芯片处于所述第一导通状态时，所述两组引脚中的一组引脚用于充电，所述两组引脚中的另一组引脚用于数据传输。
  7. 根据权利要求6所述的方法，其中，所述若所述目标设备满足第一条件且所述快充数据线满足第二条件，则控制所述电子设备中的开关芯片处于第一导通状态，包括：
    在所述目标设备为支持DCP的设备的情况下，控制所述开关芯片处于第二导通状态，其中，所述开关芯片处于所述第二导通状态时，所述两组引脚均用于充电；
    获取所述目标设备的设备能力信息，以及所述快充数据线的参数信息；
    在所述设备能力信息指示所述目标设备具备数据传输能力，以及根据参数信息确定所述快充数据线满足所述第二条件的情况下，控制所述开关芯片由所述第二导通状态切换至所述第一导通状态。
  8. 根据权利要求7所述的方法，其中，所述获取所述目标设备的设备能力信息之后，所述方法还包括：
    在所述设备能力信息指示所述目标设备不具备数据传输能力的情况下，控制所述开关芯片保持所述第二导通状态。
  9. 根据权利要求6所述的方法，其中，所述方法还包括：
    在所述电子设备通过所述快充数据线与所述目标设备连接的情况下，在所述目标设备满足第三条件的情况下，控制所述开关芯片处于第三导通状态；
    其中，所述目标设备满足第三条件：所述目标设备为具备数据传输能力且不具备供电能力的设备；
    其中，所述开关芯片处于所述第三导通状态时，所述两组引脚均用于数据传输。
  10. 一种快充装置，所述快充装置包括控制模块；
    所述控制模块，用于在电子设备通过快充数据线与目标设备连接的情况下，若所述目标设备满足第一条件且所述快充数据线满足第二条件，则控制所述电子设备中的开关芯片处于第一导通状态；
    其中，所述目标设备满足第一条件包括：所述目标设备为支持DCP且具备数据传输能力的设备；
    所述快充数据线满足第二条件包括：所述快充数据线中的两组目标引脚分别与所述快充数据线中的两组线缆连接；
    其中，所述两组目标引脚为所述快充数据线中与所述电子设备中的两组引脚相对应的引脚；
    其中，所述开关芯片处于所述第一导通状态时，所述两组引脚中的一组引脚用于充电，所述两组引脚中的另一组引脚用于数据传输。
  11. 根据权利要求10所述的装置，其中，所述快充装置还包括：获取模块；
    所述控制模块，具体用于在所述目标设备为支持DCP的设备的情况下，控制所述开关芯片处于第二导通状态，其中，所述开关芯片处于所述第二导通状态时，所述两组引脚均用于充电；
    所述获取模块，用于获取所述目标设备的设备能力信息，以及所述快充数据线的参数信息；
    所述控制模块，具体用于在所述获取模块获取的所述设备能力信息指示所述目标设备具备数据传输能力，以及根据参数信息确定所述快充数据线满足所述第二条件的情况下，控制所述开关芯片由所述第二导通状态切换至所述第一导通状态。
  12. 根据权利要求11所述的装置，其中，所述控制模块，还用于在所述设备能力信息指示所述目标设备不具备数据传输能力的情况下，控制所述开关芯片保持所述第二导通状态。
  13. 根据权利要求10所述的装置，其中，所述控制模块，还用于在所述电子设备通过所述快充数据线与所述目标设备连接的情况下，在所述目标设备满足第三条件的情况下，控制所述开关芯片处于第三导通状态；
    其中，所述目标设备满足第三条件包括：所述目标设备为具备数据传输能力且不具备供电能力的设备；
    其中，所述开关芯片处于所述第三导通状态时，所述两组引脚均用于数据传输。
  14. 一种快充系统，包括目标设备、快充数据线和如权利要求1至5中任一项所述的电子设备，所述快充数据线分别与所述电子设备的母座和所述目标设备的端口连接；
    其中，所述快充数据线包括两组目标引脚和两组线缆，所述两组目标引脚分别与所述两组线缆连接，且所述两组目标引脚分别与所述母座中的两组引脚连接。
  15. 一种电子设备，包括处理器和存储器，所述存储器存储可在所述处理器上运行的程序或指令，所述程序或指令被所述处理器执行时实现如权利要求6至9中任一项所述的快充方法的步骤。
  16. 一种可读存储介质，所述可读存储介质上存储程序或指令，所述程序或指令被处理器执行时实现如权利要求6至9中任一项所述的快充方法的步骤。
  17. 一种计算机软件产品，所述计算机软件产品被至少一个处理器执行以实现如权利要求6至9中任一项所述的快充方法。
  18. 一种芯片，所述芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器用于运行程序或指令，实现如权利要求6至9中任一项所述的快充方法。
  19. 一种电子设备，其特征在于，包括所述电子设备用于执行如权利要求6至9中任一项所述的快充方法。
PCT/CN2023/108155 2022-07-25 2023-07-19 电子设备、快充方法、装置、系统及可读存储介质 WO2024022195A1 (zh)

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