WO2024021819A1 - 量子电路优化方法、装置、电子设备、计算机可读存储介质及计算机程序产品 - Google Patents

量子电路优化方法、装置、电子设备、计算机可读存储介质及计算机程序产品 Download PDF

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WO2024021819A1
WO2024021819A1 PCT/CN2023/096212 CN2023096212W WO2024021819A1 WO 2024021819 A1 WO2024021819 A1 WO 2024021819A1 CN 2023096212 W CN2023096212 W CN 2023096212W WO 2024021819 A1 WO2024021819 A1 WO 2024021819A1
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qubit
quantum
unitary matrix
quantum circuit
node
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PCT/CN2023/096212
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English (en)
French (fr)
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袁佩
张胜誉
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腾讯科技（深圳）有限公司
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Priority to EP23845033.2A priority Critical patent/EP4401012A1/en
Publication of WO2024021819A1 publication Critical patent/WO2024021819A1/zh
Priority to US18/610,133 priority patent/US20240281694A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/60—Quantum algorithms, e.g. based on quantum optimisation, quantum Fourier or Hadamard transforms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/20—Models of quantum computing, e.g. quantum circuits or universal quantum computers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N5/00—Computing arrangements using knowledge-based models
    • G06N5/01—Dynamic search techniques; Heuristics; Dynamic trees; Branch-and-bound

Definitions

  • the present application relates to quantum computing technology, and in particular, to a quantum circuit optimization method, device, electronic equipment, computer-readable storage medium and computer program product.
  • the number of quantum gates in a quantum circuit is related to the running time of the quantum algorithm.
  • the quantum circuit can also be optimized to further reduce the running time of the quantum algorithm.
  • quantum circuits in superconducting quantum devices have various constraints, such as no restrictions, path restrictions, tree restrictions, and connected graph restrictions. Therefore, for the circuit implementation of arbitrary unitary matrices, if it is based on existing circuit restrictions, The promotion of quantum circuits will make the optimization effect of quantum circuits poor.
  • Embodiments of the present application provide a quantum circuit optimization method, device, electronic equipment, computer-readable storage medium, and computer program product, which can improve the optimization effect of quantum circuits.
  • Embodiments of the present application provide a quantum circuit optimization method, which is applied to electronic devices.
  • the method includes:
  • each of the qubit uniform control gates into a second number of qubit diagonal unitary matrices and a third number of single qubit gates;
  • Embodiments of the present application provide a quantum circuit optimization device, including:
  • a matrix decomposition module configured to convert the quantum circuit to be optimized into a unitary matrix to be processed, and iteratively decompose the unitary matrix to be processed to obtain a first number of qubit uniform control gates;
  • control gate decomposition module configured to decompose each qubit uniform control gate into a second number of qubit diagonal unitary matrices and a third number of single qubit gates
  • a circuit implementation module configured to determine a matching quantum circuit corresponding to each of the qubit diagonal unitary matrices under the constraints of a connected graph
  • an integration module configured to integrate a second number of the matching quantum circuits and a third number of the single qubit gates to obtain a target quantum circuit with uniform control gates for each qubit; described
  • the target quantum circuits are connected to obtain the optimized quantum circuit corresponding to the quantum circuit to be optimized.
  • Embodiments of the present application provide a quantum computer device.
  • the quantum computing device includes an optimized quantum circuit.
  • the optimized quantum circuit is implemented by the quantum circuit optimization method provided by the embodiment of the present application.
  • An embodiment of the present application provides an electronic device, including:
  • Memory used to store executable instructions
  • the processor is configured to implement the quantum circuit optimization method provided by the embodiment of the present application when executing executable instructions stored in the memory.
  • Embodiments of the present application provide a computer-readable storage medium that stores executable instructions for causing the processor to implement the quantum circuit optimization method provided by the embodiments of the present application.
  • Embodiments of the present application provide a computer program product, which includes a computer program or instructions.
  • the computer program or instructions are executed by a processor, the quantum circuit optimization method provided by the embodiments of the present application is implemented.
  • the electronic device first iteratively decomposes the unitary matrix to be processed obtained by converting the quantum circuit to be optimized, and then decomposes the qubit uniform control gate obtained by decomposition, and obtains the qubit diagonal unitary matrix and
  • the electronic device first iteratively decomposes the unitary matrix to be processed obtained by converting the quantum circuit to be optimized, and then decomposes the qubit uniform control gate obtained by decomposition, and obtains the qubit diagonal unitary matrix and
  • the quantum circuit implementation process of the qubit diagonal unitary matrix is relatively complex.
  • the optimized quantum circuit is obtained by integrating the matching quantum circuit and the single qubit gate, thereby obtaining the optimal quantum circuit under the constraints of the connected graph, that is, the optimized quantum circuit with faster computing speed, which also improves the effect of quantum circuit optimization. , improving quantum computing efficiency by optimizing quantum circuits.
  • Figure 1 is a schematic diagram of graph constraints
  • Figure 2 is a schematic architectural diagram of the quantum circuit optimization system provided by the embodiment of the present application.
  • FIG 3 is a schematic structural diagram of the server in Figure 2 provided by an embodiment of the present application.
  • Figure 4 is a schematic flow chart of the quantum circuit optimization method provided by the embodiment of the present application.
  • Figure 5 is a schematic diagram of an n-qubit uniform control gate provided by an embodiment of the present application.
  • Figure 6 is a schematic diagram of decomposing a qubit uniform control gate provided by an embodiment of the present application.
  • Figure 7 is a schematic diagram of a connected graph provided by an embodiment of the present application.
  • Figure 8 is a schematic diagram of the decomposition results of the unitary matrix to be processed provided by the embodiment of the present application.
  • Figure 9 is another schematic flow chart of the quantum circuit optimization method provided by the embodiment of the present application.
  • Figure 10 is another schematic flow chart of the quantum circuit optimization method provided by the embodiment of the present application.
  • Figure 11 is a schematic diagram of a matching quantum circuit provided by an embodiment of the present application.
  • Figure 12 is a schematic diagram of numbering qubits provided by the embodiment of the present application.
  • Figure 13 is a schematic diagram of the circuit implementation of the controlled reverse gate (CNOT) gate under path restrictions provided by the embodiment of the present application.
  • CNOT controlled reverse gate
  • first ⁇ second ⁇ third are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understandable that “first ⁇ second ⁇ third” is used in Where appropriate, the specific order or sequence may be interchanged so that the embodiments of the application described herein can be implemented in an order other than that illustrated or described herein.
  • Quantum Computation is a computing method that uses the superposition and entanglement of quantum states to quickly complete computing tasks.
  • Quantum Circuit a description model of quantum computing, including qubits and quantum operations on qubits.
  • a quantum circuit includes a series of quantum gates and a measurement sequence. The quantum gates are used to complete calculations, and the measurement sequence is used to measure the calculation results.
  • Qubit is the carrying form of quantum information.
  • the unit of quantum information is a qubit, which is similar to a classical bit but adds the quantum properties of physical atoms.
  • Quantum Gate is a basic quantum circuit that operates a small number of qubits. Quantum gates are the basis of quantum circuits, just like the relationship between logic gates and digital circuits. Quantum gates operate on one or two qubits. Quantum gates that operate on one qubit are single-qubit gates. Quantum gates that operate on two qubits are double-qubit gates. Below, some quantum gates and their definitions are shown through Table 1 below.
  • Unitary Matrix also known as unitary matrix, is used to represent quantum gates. That is, any quantum gate can be expressed as a unitary matrix.
  • the unitary matrix is used to represent the Hermitian conjugate matrix equal to the inverse matrix.
  • the Hermitian conjugate is the transpose, so the real orthogonal representation is that the transposed matrix is equal to the inverse matrix.
  • Quantum computing can help solve some problems that are difficult for classical computers to solve due to its ability to quickly complete computing tasks. For example, for large number decomposition problems, the use of quantum computing can improve computing efficiency exponentially.
  • the quantum circuit can also be optimized to further reduce the running time of the quantum algorithm.
  • Figure 1 is a schematic diagram of a graph restriction.
  • the graph constraints in Figure 1 include path constraints 1-1, tree constraints 1-2, and brick wall shape constraints 1-3.
  • the nodes in Figure 1 represent qubits, and the edges represent the connection relationships of qubits.
  • the limitation of the graph is that a two-qubit gate can only be applied to two connected qubits.
  • CNOT gate can be applied to 0 and 1, 0 and 4 are not connected, CNOT gate cannot be applied to 0 and 4; 1 and 3 in tree restriction 1-2 are connected, 1 and 3 can be applied with CNOT gate, 2 and 6 are not connected, 2 and 6 cannot be applied with CNOT gate; brick wall shape limit 1-3 in 4 and 15 are connected, 4 and 15 can be applied with CNOT gate, 15 and 16 are not connected, 15 and 16 CNOT gate cannot be applied.
  • Embodiments of the present application provide a quantum circuit optimization method, device, electronic equipment, computer-readable storage medium and computer program product, which can improve the effect of quantum circuit optimization.
  • the following describes an exemplary application of the electronic device for quantum circuit optimization provided by the embodiment of the present application.
  • the electronic device provided by the embodiment of the present application can be implemented as various types of terminals or as a server. Below, an exemplary application when the electronic device is implemented as a server will be described.
  • Figure 2 is a schematic architectural diagram of a quantum circuit optimization system provided by an embodiment of the present application.
  • the terminal 400 and the quantum computing device 500 are connected to the server through the network 300.
  • the network 300 can be a wide area network or a local area network, or a combination of the two.
  • the terminal 400 is used to generate a quantum circuit to be optimized based on the problem to be solved, and send the quantum circuit to be optimized to the server 200 .
  • the server 200 is used to convert the quantum circuit to be optimized into a unitary matrix to be processed, and iteratively decompose the unitary matrix to be processed to obtain a first number of qubit uniform control gates; decompose each qubit uniform control gate into a second number qubit diagonal unitary matrix and the third number of single qubit gates; under the constraints of the connected graph, determine the matching quantum circuit corresponding to each qubit diagonal unitary matrix; based on the second number of matching quantum circuits and the third number Three quantities of single qubit gates are integrated to obtain the target quantum circuit that controls the gate uniformly for each qubit; based on the first number of target quantum circuits, the optimized quantum circuit corresponding to the quantum circuit to be optimized is connected to obtain the process of quantum circuit optimization.
  • the server 200 is also used to apply the optimized quantum circuit to the quantum computing device 500 (for example, transmit the optimized quantum circuit to a quantum chip manufacturing instrument, manufacture a quantum chip corresponding to the optimized quantum circuit, and obtain a quantum computing device based on the quantum chip configuration), to Improve the computing efficiency of the quantum computing device 500 by optimizing the quantum circuit.
  • the optimized quantum circuit for example, transmit the optimized quantum circuit to a quantum chip manufacturing instrument, manufacture a quantum chip corresponding to the optimized quantum circuit, and obtain a quantum computing device based on the quantum chip configuration
  • the server 200 may be an independent physical server, a server cluster or a distributed system composed of multiple physical servers, or may provide cloud services, cloud databases, cloud computing, cloud functions, cloud storage, Cloud servers for basic cloud computing services such as network services, cloud communications, middleware services, domain name services, security services, content delivery networks (CDN, Content Delivery Network), and big data and artificial intelligence platforms.
  • the terminal 400 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, etc., but is not limited thereto.
  • FIG. 3 is a schematic structural diagram of the server (an implementation of an electronic device) in Figure 2 provided by an embodiment of the present application.
  • the server 200 shown in Figure 3 includes: at least one processor 210, a memory 250, at least one Network interface 220.
  • the various components in server 200 are coupled together by bus system 240 .
  • bus system 240 is used to implement connection communication between these components.
  • the bus system 240 also includes a power bus, a control bus and a status signal bus.
  • the various buses are labeled bus system 240 in FIG. 3 .
  • the processor 210 may be an integrated circuit chip with signal processing capabilities, such as a general-purpose processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware Components, etc., wherein the general processor can be a microprocessor or any conventional processor, etc.
  • DSP Digital Signal Processor
  • Memory 250 may be removable, non-removable, or a combination thereof.
  • Exemplary hardware devices include solid state memory, hard disk drives, optical disk drives, etc.
  • Memory 250 optionally includes one or more storage devices physically located remotely from processor 210 .
  • Memory 250 includes volatile memory or non-volatile memory, and may include both volatile and non-volatile memory.
  • Non-volatile memory can be read-only memory (ROM, Read Only Memory), and volatile memory can be random access memory (RAM, Random Access Memory).
  • RAM Random Access Memory
  • the memory 250 described in the embodiments of this application is intended to include any suitable type of memory.
  • the memory 250 is capable of storing data to support various operations, examples of which include programs, modules, and data structures, or subsets or supersets thereof, as exemplarily described below.
  • the operating system 251 includes system programs used to process various basic system services and perform hardware-related tasks, such as the framework layer, core library layer, driver layer, etc., which are used to implement various basic services and process hardware-based tasks;
  • Network communication module 252 for reaching other electronic devices via one or more (wired or wireless) network interfaces 220.
  • Example network interfaces 220 include: Bluetooth, Wireless Compliance Certification (Wi-Fi), and Universal Serial Bus (USB, Universal Serial Bus), etc.;
  • the quantum circuit optimization device provided by the embodiments of the present application can be implemented in software.
  • Figure 3 shows the quantum circuit optimization device 255 stored in the memory 250, which can be software in the form of programs, plug-ins, etc., It includes the following software modules: matrix decomposition module 2551, control gate decomposition module 2552, circuit implementation module 2553 and connection integration module 2554. These modules are logical, so they can be arbitrarily combined or further split according to the functions implemented. The functions of each module are explained below.
  • the quantum circuit optimization device provided by the embodiments of the present application can be implemented in hardware.
  • the quantum circuit optimization device provided by the embodiments of the present application can be a processor in the form of a hardware decoding processor, which Programmed to execute the quantum circuit optimization method provided by the embodiments of the present application, for example, a processor in the form of a hardware decoding processor can use one or more Application Specific Integrated Circuits (ASIC, Application Specific Integrated Circuit), DSP, programmable logic Device (PLD, Programmable Logic Device), Complex Programmable Logic Device (CPLD, Complex Programmable Logic Device), Field Programmable Gate Array (FPGA, Field-Programmable Gate Array) or other electronic components.
  • ASIC Application Specific Integrated Circuit
  • DSP digital signal processor
  • PLD programmable logic Device
  • CPLD Complex Programmable Logic Device
  • FPGA Field-Programmable Gate Array
  • a terminal or server can implement the quantum circuit optimization method provided by the embodiments of this application by running a computer program.
  • a computer program can be a native program or software module in the operating system; it can be a native (Native) application (APP, Application), which needs to be installed in the operating system to run. It can be a running program, such as a circuit optimization APP; it can also be a small program, that is, a program that only needs to be downloaded to the browser environment to run; it can also be a small program that can be embedded in any APP.
  • the computer program described above can be any form of application, module or plug-in.
  • Embodiments of the present application provide a quantum computing device.
  • the quantum computing device includes an optimized quantum circuit.
  • the optimized quantum circuit is implemented by the quantum circuit optimization method provided by the embodiment of the present application.
  • ⁇ > is composed of qubits in the set S. If S ⁇ q ⁇ , then
  • Figure 4 is a schematic flow chart of a quantum circuit optimization method provided by an embodiment of the present application, which will be described in conjunction with the steps shown in Figure 4.
  • the embodiments of this application are implemented under the limitation of connected graphs and in the scenario of optimizing the quantum circuit to be optimized.
  • optimizing the quantum circuit to be optimized the same functions as the quantum circuit to be optimized can be achieved, but with fewer quantum gates. (that is, require less computational time) optimized quantum circuits.
  • Each quantum circuit has a corresponding unitary matrix.
  • the electronic device first performs unitary matrix conversion on the quantum circuit to be processed, and the resulting unitary matrix is the unitary matrix to be processed. Since the structure of the quantum circuit to be optimized is relatively complex, it is difficult to optimize the quantum circuit to be optimized without changing the function and being restricted by the connected graph. However, the implementation process of the unitary matrix quantum circuit is relatively simple. Therefore, in the embodiments of the present application, , is the problem of converting the size of an optimized quantum circuit into a quantum circuit implementation of an arbitrary unitary matrix.
  • the number of qubits acted upon by the quantum circuit to be optimized can be set according to the actual situation, for example, set to n (n is a positive integer).
  • the application of the quantum circuit to be optimized on n qubits is taken as an example to illustrate the optimization process of the quantum circuit to be optimized.
  • the unitary matrix to be processed is the n-qubit unitary matrix. Therefore, the optimization problem of the quantum circuit to be optimized is to realize the n-qubit unitary matrix under the constraints of the connected graph. The corresponding quantum circuit.
  • the number of qubits corresponding to the qubit uniform control gate obtained from the iterative decomposition of the unitary matrix to be processed is the same as the number of qubits corresponding to the unitary matrix to be processed, that is, when the unitary matrix to be processed is When processing a unitary matrix that is an n-qubit unitary matrix, the electronic device will perform n iterative decomposition of the n-qubit unitary matrix.
  • Each iterative decomposition will result in one or more n-qubit uniform control gates (UCG, n-qubit Uniformly Controlled Gate), and the qubit unitary matrix that needs to continue to be decomposed, the electronic device continues to decompose the obtained qubit unitary matrix, and so on, until n times of iterative decomposition are completed, the first number of n-qubit uniformly controlled gates.
  • UCG n-qubit Uniformly Controlled Gate
  • FIG. 5 is a schematic diagram of an n-qubit uniform control gate provided by an embodiment of the present application.
  • the set S ⁇ s 1 , s 2 ,..., s n-1 ⁇ represents the number of the control bit qubit, and t represents Target qubit number,
  • n-qubit uniform control gate Contains a series of single qubit gates When a single qubit gate When is the revolving door R z ( ⁇ ), then is the n-qubit diagonal unitary matrix, denoted as
  • the iterative decomposition of the unitary matrix to be processed in step S101 can be implemented through the following process: let i be a positive integer that increases sequentially, and 1 ⁇ i ⁇ n, n is the number of qubits, and iterate i Perform the following processing: perform matrix decomposition on the initial unitary matrix of the i-th iteration to obtain the decomposition result of the i-th iteration, in which the initial unitary matrix of the first iteration is the unitary matrix to be processed; from the decomposition result of the i-th iteration Extract the qubit uniform control gate of the i-th iteration and the generating unitary matrix of the i-th iteration; determine the generating unitary matrix of the i-th iteration as the initial unitary matrix of the i+1 iteration; The obtained 2 n-1 qubit uniform control gates are determined as the first number of qubit uniform control gates.
  • i is a positive integer that increases sequentially, and 1 ⁇ i ⁇ n, and n is the number of qubits.
  • the i-th bit in the qubit uniform control gate of the i-th iteration is the target bit, and the remaining n-1 bits are all control bits.
  • the qubits corresponding to the generating unitary matrix of the i-th iteration will be larger than the initial ones of the i-th iteration.
  • the number of qubits corresponding to the unitary matrix is reduced by one.
  • the electronic device can cosine- sine decomposition (i.e. matrix decomposition), the decomposition result is obtained in the following form:
  • V n-1,1 , V n-1,2 , V′ n-1,1 , V′ n-1,2 are (n-1)-qubit unitary matrices. Since V n-1,1 , V n-1,2 , V′ n-1,1 , V′ n-1,2 are (n-1)-qubit unitary matrices, we can continue to perform cosine-sine decomposition ( That is, matrix decomposition), the following form is obtained:
  • L n-2,1 (i), L n-2,2 (i), L′ n-2,1 (i), L′ n-2,1 (i), R n -2,1 (i), R n-2,2 (i), R′ n-2,1 (i), R′ n-2,1 (i) is the (n-2) qubit unitary matrix ( Generating unitary matrix of the second iteration), C n-2 (i), S n-2 (i), C′ n-2 (i), is a diagonal matrix, and the diagonal elements are respectively and Therefore, the matrix U can be expanded into the following form:
  • the second matrix (i.e. ) and the 6th matrix (i.e. ) is an n-qubit uniform control gate whose target bit is the second qubit.
  • the remaining matrix (i.e., the generating unitary matrix of the second iteration) is the diagonal matrix that needs to continue cosine-sine decomposition (i.e., the initial unitary matrix of the third iteration).
  • ⁇ (i) is calculated from the scale function, which is defined as: ( means not divisible,
  • Figure 8 is a schematic diagram of the decomposition result of the unitary matrix to be processed provided by the embodiment of the present application.
  • the unitary matrix to be processed corresponds to 3 qubits (denoted as 1, 2 and 3), that is, the unitary matrix to be processed is 3-qubits.
  • Bit unitary matrix electronic equipment decomposes the 3-qubit unitary matrix, and can obtain seven 3-qubit uniform control gates, namely (The target bit is the 3rd qubit, the control bit is the 1st qubit and the 2nd qubit), (The target bit is the 2nd qubit, the control bit is the 1st qubit and the 3rd qubit), (The target bit is the 1st qubit, the control bit is the 2nd qubit and the 3rd qubit), and
  • each qubit uniform control gate into a second number of qubit diagonal unitary matrices and a third number of single qubit gates.
  • any diagonal matrix (a matrix with all elements outside the main diagonal being 0) in the qubit uniform control gate can be decomposed into a rotation gate R z ( ⁇ ), a Hadmard gate H, a phase gate S and an inverse phase gate
  • the electronic device realizes the decomposition of qubit uniform control gates by decomposing each diagonal matrix to obtain qubit diagonal unitary matrices and single qubit gates.
  • the implementation problem of the unitary matrix to be processed is further transformed into the circuit implementation problem of the diagonal unitary matrix of qubits (the diagonal unitary matrix is easier to deal with than the unitary matrix). accomplish).
  • Each diagonal element of any n-qubit uniform control gate is a diagonal matrix, as shown in formula (1):
  • V n represents an n-qubit uniform control gate
  • U k represents a diagonal matrix, where k ⁇ [2 n-1 ].
  • R z represents the revolving door
  • S represents the phase gate
  • H represents the Hadmard gate. Represents an inverse phase gate.
  • any n-qubit uniform control gate can be decomposed into the form shown in formula (3):
  • a 1 , A 2 , A 4 and A 6 are all diagonal unitary matrices of n-qubits, Hadmard gate H, phase gate S and inverse phase gate Both are single qubit gates.
  • a 1 and A 2 can be combined into a diagonal unitary matrix of n-qubits. Therefore, the electronic device can decompose the gate uniformly for any n-qubit to obtain 3 (second number) n-qubit diagonal Unitary matrices (i.e. A 1 ⁇ A 2 , A 4 and A 6 ) and 4 (third number) single qubit gates (i.e. Hadmard gate H and phase gate S in A 3 , Hadmard gate H and inverse phase gate ).
  • FIG. 6 is a schematic diagram of decomposing a qubit uniform control gate provided by an embodiment of the present application.
  • the n-qubit uniform control gate can be obtained Control the target quantum circuit of the gate, and then obtain the quantum circuit of the unitary matrix to be processed under the constraints of the connected graph.
  • the electronic device needs to implement a circuit of a diagonal unitary matrix of qubits under the constraints of a connected graph, and the resulting circuit is recorded as a matched quantum circuit.
  • the electronic device determines the numbering information for n qubits based on the connected graph, determines the qubit pair based on the numbering information, and recurses through the double qubit gate applied to the qubit pair. Realizing the matching quantum circuit of the diagonal unitary matrix of qubits.
  • any two nodes included in the connected graph are connected, that is, there are edges connecting any two nodes.
  • the nodes in the connected graph correspond to qubits one-to-one, that is, the nodes in the connected graph represent quantum bits. bits.
  • the limitation of the connected graph means that the two-qubit gate in the quantum circuit is only allowed to act on two qubits connected by edges in the connected graph.
  • the set of nodes, E represents the set of edges in the connected graph.
  • the nodes of the connected graph G represent the qubits in the quantum circuit. Then under the constraints of the connected graph G, the qubit pairs (q 1 , q 2 ), (q 2 , q 3 ), (q 2 , q 4 ), ( q 4 , q 5 ) are connected by an edge. Therefore, a two-qubit gate (such as a CNOT gate) is only allowed to act on the qubit pair (q 1 , q 2 ), (q 2 , q 3 ), (q 2 , q 4 ), (q 4 , q 5 ) on.
  • a two-qubit gate such as a CNOT gate
  • the numbering information obtained based on the connected graph has an advantage, that is, the distance between the qubit with the numbering information k ⁇ [n] ([n] is a set of numbering information of n qubits) and the qubit with the numbering information n is not It will exceed n-k. In this way, it can limit the circuit size of the two-qubit gate when the circuit is implemented under path restriction, thus limiting the size of the matching quantum circuit.
  • Figure 9 is another schematic flow chart of the quantum circuit optimization method provided by the embodiment of the present application.
  • the control bits and target bits of different n-qubit uniform control gates may be different
  • the target of the n-qubit diagonal unitary matrix decomposed from different n-qubit uniform control gates is Bits and control bits may be different.
  • step S1031 can be implemented through the following solution two: extract the target tree from the connected graph; number each node in the target tree to obtain the node number corresponding to each node; The node number is determined as the number information of the qubit corresponding to each node.
  • the target tree is any spanning tree in the connected graph, and each qubit corresponds to a node in the target tree.
  • G′ represents a spanning tree, and at the same time, all edges in the edge set E(G′) can connect all nodes without forming a loop.
  • each node in the target tree is numbered to obtain the node number corresponding to each node.
  • This can be achieved through the following steps: generate an initialization number for each node in the target tree; when the node number When the n-k+2th node does not have a child node or a child node with an initialization number, query the target node that meets the query conditions from the node numbered node, and add the leftmost child node of the target node
  • the node code is determined to be the n-k+1th node; when the node coded as the n-k+2th node has a child node, and the number of the child node is the initialization number, the child node numbered as the initialization number will be The node code of the leftmost child node is determined to be the n-k+1th.
  • the query condition is the node with the largest number and the existence of a child node with the initialization number, 3 ⁇ k ⁇ n
  • the node with node code n is the root node of the target tree (that is, the nth node is the root node of the target tree )
  • the node with node code n-1 is the leftmost node of the root node (that is, the n-1th node is the leftmost node of the root node). That is to say, the electronic device will first access the root node of the spanning tree, number the root node as n, and then access the leftmost child node of the root node, and number the node as n-1.
  • node n-k+2 3 ⁇ k ⁇ n
  • node n-k+2 has no leaf node or no leaf node numbered 0 (0 is the initialization number)
  • find the node collection ⁇ n-k+2,n-k+ 3,...,n ⁇ (that is, the node with the node number) is the node with the largest number and a child node numbered 0.
  • FIG. 12 is a schematic diagram of numbering qubits provided by the embodiment of the present application.
  • Node 3 has a child node numbered 0, and The node number of this child node is determined to be 2.
  • node 2 Since node 2 has no child nodes, return to node 3, and node 3 has no remaining child nodes numbered 0. Continue to return to node 5, and then access the leftmost child node among the remaining child nodes numbered 0 of node 5. Its node number is determined to be 1. From this, the numbering information of the 5 qubits is obtained, and the numbering information indicates the access sequence of the 5 qubits.
  • n qubits can be marked as [n].
  • One advantage of this numbering method is that the distance between the node with numbering information k ⁇ [n] and the node with numbering information n will not exceed n-k, and ⁇ k,k+1,k+2,...,n ⁇
  • the generated subgraph is a connected graph.
  • the reference diagonal unitary matrix Based on the numbering information of n qubits, extract the reference diagonal unitary matrix from the qubit diagonal unitary matrix.
  • the target bits of the reference diagonal unitary matrix are the qubits whose encoding information is n
  • the control bits are the qubits whose encoding information is the first n-1.
  • FIG 10 is another schematic flow chart of the quantum circuit optimization method provided by the embodiment of the present application.
  • the specific implementation process of S1033 may include: S1033a-S1033e, as follows:
  • the electronic device will construct 2 n-1 qubit sequences of length n-1:
  • generating multiple qubit sequences for the reference diagonal unitary matrix can be achieved by the following processing: determining the qubit to be flipped in the jth qubit sequence, and flipping the elements on the qubit to be flipped, The j+1th qubit sequence is obtained; when the value of iteration j is 2 n-1 , the 2 n-1 qubit sequence is determined as multiple qubit sequences of the reference diagonal unitary matrix.
  • the first qubit sequence is arranged using n-1 second elements.
  • the first qubit sequence is composed of It is composed of n-1 zeros arranged.
  • the qubit to be flipped is obtained by subtracting the scale function values of n and j.
  • the qubit sequence c 1 0 n-1
  • the qubit sequence c j is obtained by flipping the n- ⁇ (j-1)th bit from c j-1 .
  • the first element can be 1 and the second element can be 0.
  • the electronic device expands each qubit sequence of length n-1 into 2 qubit sequences of length n.
  • the plurality of qubit sequences are 00, 01, 10, and 11 respectively
  • the plurality of first qubit sequences can be 001, 011, 101, 111
  • the plurality of second qubit sequences can be 000, 010, 100 ,110.
  • the electronic device determines to implement the transformation Quantum circuit, where c refers to the collective name of multiple qubit sequences, c1 is the collective name of the first qubit sequence obtained by adding 1 to the tail of each qubit sequence, ⁇ c1 is the first qubit sequence composed of set of real numbers.
  • S1033c can be implemented through the following processing: based on the numbering information of n qubits, determine the matching CNOT gate of the j-th first qubit sequence; based on the j+1-th first qubit sequence, construct the application in the Matching R quantum gates after matching CNOT gates of j first qubit sequences; when j reaches 2 n-1 -1, 2 n-1 -1 matching CNOT gates and matching R quantum gates are alternately connected to get Candidate subcircuit; determine the supplementary R quantum gate and the supplementary CNOT gate, and connect the supplementary R quantum gate and the supplementary CNOT gate to obtain the supplementary subcircuit; based on the candidate subcircuit and the supplementary subcircuit, determine the first quantum circuit.
  • j is a positive integer that increases sequentially, and 1 ⁇ j ⁇ 2 n-1 -1, 2 n-1 is the number of the first qubit sequence.
  • the target bit matching the CNOT gate is a qubit with number information n
  • the control bit is a qubit with number information n- ⁇ (j)
  • the electronic device is equipped with a qubit with number information n and number information n-
  • a CNOT gate is applied to the qubit of ⁇ (j) ( ⁇ (j) is calculated from the definition of the scale function above), and the CNOT gate is used to process the first qubit sequence.
  • the numbering information corresponding to the control bit of the matching CNOT gate of the j-th first qubit sequence is calculated from n and j
  • the target bit is the qubit with numbering information n.
  • the supplementary R quantum gate is determined by the first qubit sequence
  • the control bit of the supplementary CNOT gate is the qubit with number information 1
  • the target bit of the supplementary CNOT gate is the qubit with number information n.
  • formula (2) is the formula of the first quantum circuit:
  • ⁇ c1 is the set of real numbers composed of the first qubit sequence, Indicates matching CNOT gate, represents matching R quantum gate, Represents the supplementary CNOT gate, represents the complementary R quantum gate.
  • Formula (2) can be realized by the following process:
  • step S1033d can be implemented through the following solution 1: determine the diagonal unitary matrix to be implemented corresponding to the reference diagonal unitary matrix, where the diagonal unitary matrix to be implemented corresponds to n-1 qubits; through the transformation circuit, Decompose the unitary matrix to be realized to obtain a permuted diagonal unitary matrix, in which the transformation circuit is used to replace the quantum state in the first qubit set corresponding to the unitary matrix to be realized to the quantum state in the second qubit set; according to The numbering information of n qubits determines the permutation quantum circuit corresponding to the permutation diagonal unitary matrix; the connection result of the transformation circuit, the permutation quantum circuit, and the inverse transformation circuit corresponding to the transformation circuit is determined as the second quantum circuit; where, the inverse transformation The circuit is used to replace the quantum state in the second set of qubits with the quantum state in the first set of qubits (for example, the inverse transformation circuit converts the qubits to the initial position, that is, the original quantum state).
  • the quantum circuit is a second quantum circuit, where c0 is the second qubit sequence obtained by adding 0 to the end of the bit sequence, and ⁇ c0 is the set of real numbers composed of the second qubit sequence.
  • the graph generated by the qubit set [n-1] (i.e., the first qubit set) is not necessarily a connected graph, but the graph generated by the qubit set [n]- ⁇ 1 ⁇ (i.e., the second qubit set) is connected graph, therefore, in order to achieve In the embodiment of this application, you can first determine a qubit set [n-1] that can realize the diagonal unitary matrix.
  • a switching circuit that replaces the quantum state in the qubit set [n]- ⁇ 1 ⁇ , that is, the interactive circuit is used to replace the quantum state in the first qubit set corresponding to the diagonal unitary matrix to be implemented to the second qubit set.
  • the quantum state in x 2 >,...,x n-1 > at this time, the quantum state of the qubit numbered n is x n >, and the qubit set [n]- ⁇ 1 ⁇ is numbered 2, 3,...,n
  • the replacement process of replacing the quantum states in the qubit set [n-1] to the qubit set is: replacing the quantum states of these qubits numbered 2, 3,..., n, Replace them with x 1 >, x 2 >,..., x n-1 > respectively.
  • the quantum state of the qubit numbered n is x n-1 >.
  • the diagonal unitary matrix can be permuted based on the numbering information of n qubits. Decompose and connect the quantum circuits corresponding to the finally decomposed quantum gates to obtain the replacement quantum circuit. For example, As the new reference diagonal unitary matrix to perform steps S1033a-S1033e, we get replacement quantum circuit, that is, through step S1033 for Construct a qubit sequence and add 0 and 1 to the end of the qubit sequence through step S1033b.
  • the first qubit sequence and the second qubit sequence are then determined in a manner similar to the process of S1033c.
  • the corresponding first quantum circuit is determined according to the method of step S1033d.
  • the second quantum circuit is determined according to step S1033e permutation quantum circuits. Confirming After the quantum circuit (replacement quantum circuit), on the basis of the replacement quantum circuit, the transformation circuit and the corresponding inverse transformation circuit of the transformation circuit are connected to obtain the second quantum circuit.
  • the electronic device first applies the first quantum circuit to n qubits, and then applies the second quantum circuit to n qubits.
  • the resulting overall circuit is the reference quantum circuit. It can also be said that the electronic device connects the first quantum circuit and the second quantum circuit to obtain a reference quantum circuit.
  • FIG. 11 is a schematic diagram of a reference quantum circuit provided by an embodiment of the present application.
  • the first quantum circuit and the second quantum circuit are applied to the qubits whose number information is 1, 2,..., n-1, n respectively.
  • the second quantum circuit includes a conversion circuit P, a permutation quantum circuit and an inverse conversion. circuit
  • the remaining diagonal unitary matrix is the diagonal unitary matrix other than the reference diagonal unitary matrix among the qubit diagonal unitary matrices.
  • step S104 can be implemented in the following manner: connecting the matching quantum circuit and the single qubit gate in sequence to obtain a target quantum circuit with uniform control gates for each qubit, where the sequence The qubit diagonal unitary matrix obtained by decomposing the qubit uniform control gate and the decomposition sequence of the single qubit gate are shown in Figure 6.
  • the electronic device will obtain multiple target quantum circuits that correspond one-to-one to multiple qubit uniform control gates.
  • H, H, and S are known quantum circuits.
  • the order of H, R 2 , H, S, R 3 that is, the decomposition order of qubit uniform control gate into qubit diagonal unitary matrix and single qubit gate, connects the known quantum circuit (that is, single qubit Door H, H, S) and matching quantum circuits (i.e. matching quantum circuits corresponding to R 1 , R 2 and R 3 respectively), to obtain an n-qubit uniform control gate Target quantum circuits.
  • the electronic device After the electronic device obtains the first number of target quantum circuits based on the above step S104, it connects the first number of target quantum circuits according to the iterative decomposition sequence of the qubit uniform control gate to obtain the optimized quantum circuit (i.e., to be optimized).
  • the optimized quantum circuit corresponding to the quantum circuit where the iterative decomposition order is the order of the qubit uniform control gates obtained by iteratively decomposing the unitary matrix to be processed. It can be seen from the above that the computing time required to optimize a quantum circuit is less than the computing time of the quantum circuit to be optimized.
  • the embodiments of this application are implemented under the constraints of connected graphs and in the scenario of optimizing the quantum circuit to be optimized.
  • the quantum Optimized quantum circuits with fewer gates (that is, less computation time required).
  • Each quantum circuit has a corresponding unitary matrix.
  • the electronic device first performs unitary matrix conversion on the quantum circuit to be processed, and the resulting unitary matrix is the unitary matrix to be processed. Since the structure of the quantum circuit to be optimized is relatively complex, it is difficult to optimize the quantum circuit to be optimized without changing the function and being restricted by the connected graph. However, the implementation process of the unitary matrix quantum circuit is relatively simple.
  • the embodiments of this application first Iteratively decompose the unitary matrix to be processed obtained from the conversion of the quantum circuit to be optimized, and then decompose the qubit uniform control gate obtained from the decomposition to obtain the qubit diagonal unitary matrix and single qubit gate to achieve recursive decomposition of the quantum circuit.
  • the optimization problem is converted into a quantum circuit implementation problem of the qubit diagonal unitary matrix, and under the constraints of the connected graph, the matching quantum circuit is determined for the qubit diagonal unitary matrix.
  • the optimized quantum circuit is obtained based on the integration of the matching quantum circuit and the single qubit gate.
  • the obtained optimized quantum circuit when applied to a quantum computing device, it will speed up the computing speed of the quantum computing device, thereby improving the computing efficiency of the quantum computing device.
  • Figure 13 is a schematic diagram of the circuit implementation of the CNOT gate under path restrictions provided by the embodiment of the present application. Referring to Figure 13, it can be seen that in the path i-(i+1)-...-( Under the restriction of j-1)-j, Can be implemented by a CNOT circuit with O(ji) depth and size.
  • the quantum optimization method provided by the embodiments of the present application can obtain an asymptotically optimal quantum circuit, that is, an optimized quantum circuit with faster operation speed, and when the optimized quantum circuit is applied to a quantum computing device, it can make The computing speed of quantum computing equipment is accelerated and the computing efficiency of quantum computing equipment is improved.
  • the embodiment of the present application uses an O(2 n ) circuit with a size of 2 n to realize an arbitrary n-qubit uniform control gate under the constraints of the connected graph, the quantum state preparation circuit can be decomposed into n circuits with sizes 1, 2, respectively. ..., n qubits uniformly control the gate. Therefore, the embodiment of the present application can realize a quantum state preparation circuit with a circuit size of O(2 n ) under the limitation of connected graph, so that the size of the quantum state preparation circuit under the limitation of connected graph is also optimal.
  • the quantum circuit optimization device 255 provided by the embodiment of the present application is implemented as a software module.
  • the software module is stored in the quantum circuit optimization device 255 of the memory 250 Can include:
  • the matrix decomposition module 2551 is configured to convert the quantum circuit to be optimized into a unitary matrix to be processed, and iteratively decompose the unitary matrix to be processed to obtain a first number of qubit uniform control gates;
  • the control gate decomposition module 2552 is configured as Each of the qubit uniform control gates is decomposed into a second number of qubit diagonal unitary matrices and a third number of single qubit gates;
  • the circuit implementation module 2553 is configured to determine the relationship between each qubit and each qubit under the constraints of the connected graph.
  • Matching quantum circuits corresponding to the diagonal unitary matrices of qubits connect the integration module 2554, configured to integrate the second number of the matching quantum circuits and the third number of the single qubit gates to obtain each of the matching quantum circuits.
  • the target quantum circuit of the qubit uniform control gate connect a first number of the target quantum circuits to obtain an optimized quantum circuit.
  • the matrix decomposition module 2551 is also configured to perform the following processing for the i-th iteration:
  • the initial unitary matrix of the i-th iteration is the unitary matrix to be processed, i is a positive integer that increases sequentially, and 1 ⁇ i ⁇ n, n is the number of qubits; extract the qubit uniform control gate of the i-th iteration and the generating unitary matrix of the i-th iteration from the decomposition result of the i-th iteration; convert the i-th iteration
  • the generated unitary matrix is determined as the initial unitary matrix of the i+1th iteration; the 2 ⁇ (n-1) qubit uniform control gates obtained by n iterations are determined as the first number of the qubit uniform control gates Door.
  • the circuit implementation module 2553 is also configured to determine the numbering information corresponding to the n qubits under the constraints of the connected graph; based on the numbering information of the n qubits, from Extract a reference diagonal unitary matrix from the qubit diagonal unitary matrix, wherein the target bit of the reference diagonal unitary matrix is a qubit whose coded information is n, and the control bit is a qubit whose coded information is the first n-1 ; Based on the numbering information of the n qubits, determine the reference quantum circuit corresponding to the reference diagonal unitary matrix; convert the reference quantum circuit through a controlled back-gate CNOT gate to obtain the remaining diagonal unitary matrix corresponding A conversion quantum circuit, wherein the remaining diagonal unitary matrix is the diagonal unitary matrix other than the reference diagonal unitary matrix in the qubit diagonal unitary matrix; the reference diagonal unitary matrix corresponding to The reference quantum circuit and the conversion quantum circuit corresponding to the remaining diagonal unitary matrix are determined to be the matching quantum circuits of the qubit diagonal unitary matrix.
  • the circuit implementation module 2553 is also configured to generate multiple qubit sequences for the reference diagonal unitary matrix; add a first element to the tail of each qubit sequence to obtain multiple A first qubit sequence, and adding a second element to the end of each qubit sequence to obtain multiple second qubit sequences; determining the reference diagonal unitary based on the numbering information of the n qubits
  • the first quantum circuit corresponding to the matrix wherein the first quantum circuit is used to load the phases corresponding to a plurality of the first qubit sequences into the standard basis; based on the number information of the n qubits, determine the The second quantum circuit corresponding to the reference diagonal unitary matrix, the second quantum circuit is used to load the phases corresponding to a plurality of the second qubit sequence into the standard basis; based on the first quantum circuit and The second quantum circuit determines the reference quantum circuit corresponding to the reference diagonal unitary matrix.
  • the circuit implementation module 2553 is also configured to determine the matching CNOT gate of the jth first qubit sequence based on the numbering information of the n qubits, where j is a sequentially increasing positive integer. , and 1 ⁇ j ⁇ 2 n-1 -1; based on the j+1 first qubit sequence, construct a matching R quantum gate applied after the matching CNOT gate of the jth first qubit sequence ; When j reaches 2 n-1 -1, alternately connect 2 n-1 -1 matching CNOT gates and matching R quantum gates to obtain candidate subcircuits; determine the supplementary R quantum gate and supplementary CNOT gate, and compare all The supplementary R quantum gate and the supplementary CNOT gate are connected to obtain a supplementary subcircuit; based on the candidate subcircuit and the supplementary subcircuit, the first quantum circuit is determined.
  • the supplementary R quantum gate is determined based on the first qubit sequence, the control bit of the supplementary CNOT gate is a qubit with number information 1, and the target bit of the supplementary CNOT gate is the number information is the n qubit; the number information corresponding to the control bit of the matching CNOT gate of the jth first qubit sequence is calculated by n and j, and the target of the matching CNOT gate of the jth first qubit sequence A bit is a qubit of numbered information n.
  • the circuit implementation module 2553 also determines the diagonal unitary matrix to be implemented corresponding to the reference diagonal unitary matrix, wherein the diagonal unitary matrix to be implemented corresponds to n-1 qubits; by A conversion circuit that replaces the quantum state in the first set of qubits corresponding to the unitary matrix to be realized with the quantum state in the second set of qubits, and determines the replaced unitary matrix to be realized as a permuted diagonal unitary matrix; determine the permutation quantum circuit corresponding to the permutation diagonal unitary matrix according to the number information of the n qubits; combine the transformation circuit, the permutation quantum circuit and the inverse transformation circuit corresponding to the transformation circuit The connection result is determined as the second quantum circuit, wherein the inverse transformation circuit is used to replace the quantum state in the second qubit set with the quantum state in the first qubit set.
  • the circuit implementation module 2553 is also configured to determine the qubit to be flipped in the jth qubit sequence, and flip the elements on the qubit to be flipped to obtain the j+1th qubit.
  • Bit sequence among them, 2 ⁇ j ⁇ 2 n-1 , the first qubit sequence is obtained by arranging n-1 second elements; when the value of iteration j reaches 2 n-1 , 2 n-1
  • a qubit sequence is determined as a plurality of the qubit sequences of the reference diagonal unitary matrix.
  • the circuit implementation module 2553 is also configured to extract a target tree from the connected graph, wherein, the target tree is any spanning tree in the connected graph, and each qubit corresponds to a node in the target tree; each node in the target tree is numbered to obtain each The node number corresponding to the node; the node number corresponding to each node is determined as the number information of the qubit corresponding to each node.
  • the circuit implementation module 2553 is also configured to generate an initialization number for each node in the target tree; when the node numbered n-k+2 does not have a child node or is numbered When initializing the numbered child nodes, query the target node that meets the query conditions from the node numbered nodes, and determine the node code of the leftmost child node of the target node as n-k+1; where, the query The condition is that the node with the largest number and the child node with the initialization number exists; 3 ⁇ k ⁇ n, the node coded as n is the root node of the target tree, and the node coded as n-1 is the leftmost node of the root node; when the node coded as n-k+2 has a child node, and the number of the child node is the initialization number, the child node numbered as the initialization number The node code of the leftmost child node in is determined to be n-k+1.
  • Embodiments of the present application provide a computer program product or computer program.
  • the computer program product or computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium.
  • the processor of the electronic device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the electronic device executes the quantum circuit optimization method described above in the embodiment of the present application.
  • Embodiments of the present application provide a computer-readable storage medium storing executable instructions.
  • the executable instructions are stored therein.
  • the executable instructions When executed by a processor, they will cause the processor to perform the quantum circuit optimization provided by the embodiments of the present application.
  • Method for example, the quantum circuit optimization method shown in Figure 4.
  • the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; it may also include one or any combination of the above memories.
  • Various equipment may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; it may also include one or any combination of the above memories.
  • Various equipment may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; it may also include one or any combination of the above memories.
  • executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and their May be deployed in any form, including deployed as a stand-alone program or deployed as a module, component, subroutine, or other unit suitable for use in a computing environment.
  • executable instructions may be deployed to execute on one electronic device, or on multiple electronic devices located at one location, or on multiple electronic devices distributed across multiple locations and interconnected by a communications network. execute on.
  • the electronic device first iteratively decomposes the unitary matrix to be processed obtained by converting the quantum circuit to be optimized, and then decomposes the decomposed qubit uniform control gate to obtain the qubit diagonal unitary matrix.
  • Matrix and single qubit gates to recursively convert the quantum circuit optimization problem into the quantum circuit implementation problem of the qubit diagonal unitary matrix, and determine the matching quantum circuit for the qubit diagonal unitary matrix under the constraints of the connected graph,
  • an optimized quantum circuit is obtained based on the integration of matching quantum circuits and single qubit gates, thereby obtaining the optimal quantum circuit under the constraints of the connected graph, that is, an optimized quantum circuit with faster computing speed, which also improves the effect of quantum circuit optimization.
  • the optimized quantum circuit when applied to quantum computing equipment, it can speed up the computing speed of quantum computing equipment, that is, improve the computing efficiency of quantum computing equipment; it can realize a quantum state with a circuit size of O(2 n ) under the limitation of connected graphs.
  • the circuit is prepared so that the size of the quantum state preparation circuit is also optimal under the constraints of the connected graph.

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Abstract

本申请提供了一种量子电路优化方法、装置、电子设备、计算机可读存储介质及计算机程序产品，涉及量子计算技术；该方法包括：将待优化量子电路转换为待处理酉矩阵，并对待处理酉矩阵进行迭代分解，得到第一数量的量子比特均匀控制门；将每个量子比特均匀控制门，分解为第二数量的量子比特对角酉矩阵和第三数量的单量子比特门；在连通图的限制下，确定与每个量子比特对角酉矩阵对应的匹配量子电路；对第二数量的匹配量子电路和第三数量的单量子比特门进行整合，得到每个量子比特均匀控制门的目标量子电路；对第一数量的目标量子电路进行连接，得到优化后的量子电路。

Description

量子电路优化方法、装置、电子设备、计算机可读存储介质及计算机程序产品
相关申请的交叉引用
本申请实施例基于申请号为202210885994.4、申请日为2022年07月26日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请实施例作为参考。
技术领域
本申请涉及量子计算技术，尤其涉及一种量子电路优化方法、装置、电子设备、计算机可读存储介质及计算机程序产品。
背景技术
量子电路中的量子门个数与量子算法的运行时间关联，为了继续提升运算效率，还可以通过对量子电路进行优化，以进一步减少量子算法的运行时间。
然而，超导量子设备中的量子电路存在各种各样的约束，例如无限制、路径限制、树限制、连通图的限制，从而对于任意酉矩阵的电路实现，若基于已有无电路限制的量子电路进行推广，会使得量子电路的优化效果较差。
发明内容
本申请实施例提供一种量子电路优化方法、装置、电子设备、计算机可读存储介质及计算机程序产品，能够提升量子电路的优化效果。
本申请实施例的技术方案是这样实现的：
本申请实施例提供一种量子电路优化方法，应用于电子设备，所述方法包括：
将待优化量子电路转换为待处理酉矩阵，并对所述待处理酉矩阵进行迭代分解，得到第一数量的量子比特均匀控制门；
将每个所述量子比特均匀控制门，分解为第二数量的量子比特对角酉矩阵和第三数量的单量子比特门；
在连通图的限制下，确定与每个所述量子比特对角酉矩阵对应的匹配量子电路；
对第二数量的所述匹配量子电路和第三数量的所述单量子比特门进行整合，得到每个所述量子比特均匀控制门的目标量子电路；
对第一数量的所述目标量子电路进行连接，得到所述待优化量子电路对应的优化量子电路。
本申请实施例提供一种量子电路优化装置，包括：
矩阵分解模块，配置为将待优化量子电路转换为待处理酉矩阵，并对所述待处理酉矩阵进行迭代分解，得到第一数量的量子比特均匀控制门；
控制门分解模块，配置为将每个所述量子比特均匀控制门，分解为第二数量的量子比特对角酉矩阵和第三数量的单量子比特门；
电路实现模块，配置为在连通图的限制下，确定与每个所述量子比特对角酉矩阵对应的匹配量子电路；
连接整合模块，配置为对第二数量的所述匹配量子电路和第三数量的所述单量子比特门进行整合，得到每个所述量子比特均匀控制门的目标量子电路；对第一数量的所述 目标量子电路进行连接，得到所述待优化量子电路对应的优化量子电路。
本申请实施例提供一种量子计算机设备，所述量子计算设备包括优化量子电路，所述优化量子电路通过本申请实施例提供的量子电路优化方法实现。
本申请实施例提供一种电子设备，包括：
存储器，用于存储可执行指令；
处理器，用于执行所述存储器中存储的可执行指令时，实现本申请实施例提供的量子电路优化方法。
本申请实施例提供一种计算机可读存储介质，存储有可执行指令，用于引起处理器执行时，实现本申请实施例提供的量子电路优化方法。
本申请实施例提供一种计算机程序产品，包括计算机程序或指令，所述计算机程序或指令被处理器执行时实现本申请实施例提供的量子电路优化方法。
本申请实施例具有以下有益效果：电子设备先针对待优化量子电路转换所得到的待处理酉矩阵进行迭代分解，再对分解得到的量子比特均匀控制门进行分解，得到量子比特对角酉矩阵和单量子比特门，由于待优化量子电路结构较为复杂，在不改变功能、且受到连通图限制的前提下是无法对待优化量子电路进行优化的，而量子比特对角酉矩阵的量子电路实现过程较为简单，从而将量子电路优化问题转换为量子比特对角酉矩阵的量子电路实现问题，能够高效的实现量子电路的优化；在连通图的限制下，针对量子比特对角酉矩阵确定匹配量子电路，最终对匹配量子电路和单量子比特门整合得到优化量子电路，从而得到在连通图的限制下的最优的量子电路，即运算速度更快的优化量子电路，也就提升了量子电路优化的效果，通过优化量子电路提高量子计算效率。
附图说明
图1是图限制的示意图；
图2是本申请实施例提供的量子电路优化系统的架构示意图；
图3是本申请实施例提供的图2中的服务器的结构示意图；
图4是本申请实施例提供的量子电路优化方法的一个流程示意图；
图5是本申请实施例提供的n-量子比特均匀控制门的示意图；
图6是本申请实施例提供的对量子比特均匀控制门进行分解的示意图；
图7是本申请实施例提供的连通图的示意图；
图8是本申请实施例提供的对待处理酉矩阵的分解结果示意图；
图9是本申请实施例提供的量子电路优化方法的另一个流程示意图；
图10是本申请实施例提供的量子电路优化方法的又一个流程示意图；
图11是本申请实施例提供的匹配量子电路的示意图；
图12是本申请实施例提供的对量子比特进行编号的示意图；
图13是本申请实施例提供的受控反闸(CNOT)门在路径限制下的电路实现的示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述，所描述的实施例不应视为对本申请的限制，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本申请保护的范围。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲 突的情况下相互结合。
在以下的描述中，所涉及的术语“第一\第二\第三”仅仅是区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本申请实施例能够以除了在这里图示或描述的以外的顺序实施。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本申请实施例的目的，不是旨在限制本申请。
对本申请实施例进行进一步详细说明之前，对本申请实施例中涉及的名词和术语进行说明，本申请实施例中涉及的名词和术语适用于如下的解释。
1)量子计算(Quantum Computation)，利用量子态的叠加和纠缠等性质快速完成计算任务的一种计算方式。
2)量子电路(Quantum Circuit)，量子计算的一种描述模型，包括量子比特以及在量子比特上的量子操作。量子电路包括一系列的量子门和测量序列，量子门用于完成计算，测量序列用于测量计算结果。
3)量子比特(Qubit)，是量子信息的承载形式。在量子计算中，作为量子信息单位的是量子比特，量子比特与经典比特相似，但是增加了物理原子的量子特性。
4)量子门(Quantum Gate)，是一个基本的、操作一个小数量的量子比特的量子线路。量子门是量子线路的基础，就像逻辑门跟数字线路之间的关系。量子门针对一个或两个量子比特进行操作，针对一个量子比特进行操作的量子门为单量子比特门，针对两个量子比特进行操作的量子门为双量子比特门。下面，通过下表1示出一些量子门及其定义。
表1量子门
5)酉矩阵(Unitray Matrix)，也称为幺正矩阵，用于表示量子门。也即，任意一个量子门都能表示为一个酉矩阵。酉矩阵用于表示厄米共轭矩阵等于逆矩阵。对于实矩阵，厄米共轭就是转置，所以实正交表示就是转置矩阵等于逆矩阵。
6)连通图，在一个无向图中，若从节点i到节点j有路径相连，则称节点i和节点j是连通的。如果无向图中任意两节点都是连通的，那么无向图被称作连通图。
量子计算由于其具有快速完成计算任务的特点，能够帮助解决一些经典计算机难以解决解决的问题。例如，针对大数分解问题，使用量子计算能够使得计算效率得到指数级的提升。
由于量子电路中的量子门个数对应了量子算法的运行时间，为了继续提升运算效率，还可以通过对量子电路进行优化，以进一步减少量子算法的运行时间。
在嘈杂的中尺度量子时代(NISQ era，Noisy intermediate-scale quantum Era)，超导量子设备中的双量子比特门(例如CNOT门)的实现会受到限制，例如，仅仅允许作用在特定的量子比特对上，这种限制在本申请实施例中被称为图限制。
示例性的，图1是图限制的示意图。图1中的图限制包括路径限制1-1、树限制1-2和砖墙形状限制1-3。图1中的节点代表量子比特，边表示量子比特的连接关系，图限制即为只能在相连的两个量子比特上应用双量子比特门。例如，路径限制1-1中的0和1相连，0和1可以应用CNOT门，0和4不相连，0和4不能应用CNOT门；树限制1-2中的1和3相连，1和3可以应用CNOT门，2和6不相连，2和6不能应用CNOT门；砖墙形状限制1-3中4和15相连，4和15可以应用CNOT门，15和16不相连，15和16不能应用CNOT门。
由于任意量子电路可以转化为一个酉矩阵，因此优化量子电路的大小可以转换为任意酉矩阵的量子电路的实现问题。因此，在图限制G＝(V,E)下量子态制备的问题可以定义为：给定任意酉矩阵n-量子比特电路CUS满足：
其中，|ψ>表示量子态，n-量子比特电路CUS包括单量子比特门和CNOT门，且CNOT门的摆放受到G＝(V,E)的限制，也即在量子电路的设计中，仅允许使用单量子比特门和CNOT门，且CNOT仅允许作用在两个相邻的量子比特上。
相关技术中，针对量子电路的优化问题，解决了在无电路限制下的任意酉矩阵的量子电路的实现，以及在路径限制下的特殊问题的量子电路的实现，然后由这无电路限制的量子电路推广得到最优的量子电路。然而，超导量子设备中的量子电路存在各种各样的约束，例如无限制、路径限制、树限制、连通图的限制等图限制，从而对于任意酉矩阵的电路实现，若基于已有无电路限制的量子电路进行推广，是难以得到渐进意义下的最优的量子电路的，最终使得量子电路的优化效果较差。
本申请实施例提供一种量子电路优化方法、装置、电子设备、计算机可读存储介质及计算机程序产品，能够提高量子电路优化的效果。下面说明本申请实施例提供的用于量子电路优化的电子设备的示例性应用，本申请实施例提供的电子设备可以实施为各种类型的终端，也可以实施为服务器。下面，将说明电子设备实施为服务器时的示例性应用。
参见图2，图2是本申请实施例提供的量子电路优化系统的架构示意图，为实现支撑一个量子电路优化应用，在量子电路优化系统100中，终端400和量子计算设备500通过网络300连接服务器200，网络300可以是广域网或者局域网，又或者是二者的组合。
终端400用于依据所要解决的问题，生成待优化量子电路，并将待优化量子电路发送给服务器200。
服务器200用于将待优化量子电路转换为待处理酉矩阵，并对待处理酉矩阵进行迭代分解，得到第一数量的量子比特均匀控制门；将每个量子比特均匀控制门，分解为第二数量的量子比特对角酉矩阵和第三数量的单量子比特门；在连通图的限制下，确定与每个量子比特对角酉矩阵对应的匹配量子电路；基于第二数量的匹配量子电路和第三数量的单量子比特门，整合得到每个量子比特均匀控制门的目标量子电路；基于第一数量的目标量子电路，连接得到待优化量子电路对应的优化量子电路，实现量子电路优化的过程。
服务器200还用于将优化量子电路应用到量子计算设备500中(例如将优化量子电路传输至量子芯片制造仪器，制造优化量子电路对应的量子芯片，并基于量子芯片配置得到量子计算设备)，以通过优化量子电路提升量子计算设备500的运算效率。
在一些实施例中，服务器200可以是独立的物理服务器，也可以是多个物理服务器构成的服务器集群或者分布式系统，还可以是提供云服务、云数据库、云计算、云函数、云存储、网络服务、云通信、中间件服务、域名服务、安全服务、内容分发网络(CDN，Content Delivery Network)、以及大数据和人工智能平台等基础云计算服务的云服务器。终端400可以是智能手机、平板电脑、笔记本电脑、台式计算机等，但并不局限于此。
参见图3，图3是本申请实施例提供的图2中的服务器(电子设备的一种实施)的结构示意图，图3所示的服务器200包括：至少一个处理器210、存储器250、至少一个网络接口220。服务器200中的各个组件通过总线系统240耦合在一起。可理解，总线系统240用于实现这些组件之间的连接通信。总线系统240除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。但是为了清楚说明起见，在图3中将各种总线都标为总线系统240。
处理器210可以是一种集成电路芯片，具有信号的处理能力，例如通用处理器、数字信号处理器(DSP，Digital Signal Processor)，或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等，其中，通用处理器可以是微处理器或者任何常规的处理器等。
存储器250可以是可移除的，不可移除的或其组合。示例性的硬件设备包括固态存储器，硬盘驱动器，光盘驱动器等。存储器250可选地包括在物理位置上远离处理器210的一个或多个存储设备。
存储器250包括易失性存储器或非易失性存储器，也可包括易失性和非易失性存储器两者。非易失性存储器可以是只读存储器(ROM，Read Only Memory)，易失性存储器可以是随机存取存储器(RAM，Random Access Memory)。本申请实施例描述的存储器250旨在包括任意适合类型的存储器。
在一些实施例中，存储器250能够存储数据以支持各种操作，这些数据的示例包括程序、模块和数据结构或者其子集或超集，下面示例性说明。
操作系统251，包括用于处理各种基本系统服务和执行硬件相关任务的系统程序，例如框架层、核心库层、驱动层等，用于实现各种基础业务以及处理基于硬件的任务；
网络通信模块252，用于经由一个或多个(有线或无线)网络接口220到达其他电子设备，示例性的网络接口220包括：蓝牙、无线相容性认证(Wi-Fi)、和通用串行总线(USB，Universal Serial Bus)等；
在一些实施例中，本申请实施例提供的量子电路优化装置可以采用软件方式实现，图3示出了存储在存储器250中的量子电路优化装置255，其可以是程序和插件等形式的软件，包括以下软件模块：矩阵分解模块2551、控制门分解模块2552、电路实现模块2553和连接整合模块2554，这些模块是逻辑上的，因此根据所实现的功能可以进行任意的组合或进一步拆分。将在下文中说明各个模块的功能。
在另一些实施例中，本申请实施例提供的量子电路优化装置可以采用硬件方式实现，作为示例，本申请实施例提供的量子电路优化装置可以是采用硬件译码处理器形式的处理器，其被编程以执行本申请实施例提供的量子电路优化方法，例如，硬件译码处理器形式的处理器可以采用一个或多个应用专用集成电路(ASIC，Application Specific Integrated Circuit)、DSP、可编程逻辑器件(PLD，Programmable Logic Device)、复杂可编程逻辑器件(CPLD，Complex Programmable Logic Device)、现场可编程门阵列(FPGA，Field-Programmable Gate Array)或其他电子元件。
在一些实施例中，终端或服务器可以通过运行计算机程序来实现本申请实施例提供的量子电路优化方法。举例来说，计算机程序可以是操作系统中的原生程序或软件模块；可以是本地(Native)应用程序(APP，Application)，即需要在操作系统中安装才能运 行的程序，如电路优化APP；也可以是小程序，即只需要下载到浏览器环境中就可以运行的程序；还可以是能够嵌入至任意APP中的小程序。总而言之，上述计算机程序可以是任意形式的应用程序、模块或插件。
本申请实施例提供一种量子计算设备，该量子计算设备包括优化量子电路，该优化量子电路通过本申请实施例提供的量子电路优化方法实现。
在说明本申请实施例提供的量子优化方法之前，首先对本申请实施例所涉及到的基本符号进行说明：[n]表示集合{1,2,…,n}；表示二元域、且表示二元域下的加法；对于任意x＝(x1,…,xn)T,y＝(y1,…,yn)T∈{0,1}n，内积其中，加法和乘法均定义在二元域上；0n表示长度为n且元素为全0的向量，1n表示长度为n且元素为全1的向量；集合S是量子比特的编号信息的集合，|ψ>S表示量子态|ψ>由集合S中的量子比特组成，如果S＝{q}，则将|ψ>S简单记为|ψ>q；如果集合S、T满足定义
下面，将结合本申请实施例提供的电子设备的示例性应用和实施，以及涉及到的基本符号，说明本申请实施例提供的量子电路优化方法。参见图4，图4是本申请实施例提供的量子电路优化方法的一个流程示意图，将结合图4示出的步骤进行说明。
S101、将待优化量子电路转换为待处理酉矩阵，并对待处理酉矩阵进行迭代分解，得到第一数量的量子比特均匀控制门。
本申请实施例是在连通图的限制下，对待优化量子电路进行优化的场景下实现的，以通过对待优化量子电路进行优化，得到能够实现与待优化量子电路相同的功能，但是量子门更少(也就是所需的计算时间更少)的优化量子电路。每个量子电路都有对应的酉矩阵，本申请实施例中，电子设备先针对待处理量子电路进行酉矩阵的转换，所得到的酉矩阵就是待处理酉矩阵。由于待优化量子电路结构较为复杂，在不改变功能、且受到连通图限制的前提下是难以对待优化量子电路进行优化的，而酉矩阵的量子电路实现过程较为简单，因此，本申请实施例中，是将优化量子电路的大小转换为任意酉矩阵的量子电路实现的问题。
可以理解的是，待优化量子电路所作用的量子比特的数量，可以根据实际情况进行设置，例如设置为n(n为正整数)。本申请实施例中，以待优化量子电路应用在n个量子比特上为例，对待优化量子电路优化的过程进行说明。
当待优化量子电路作用在n个量子比特上时，待处理酉矩阵就是n-量子比特酉矩阵，从而，针对待优化量子电路的优化问题，就是在连通图限制下实现n-量子比特酉矩阵的所对应的量子电路。
需要说明的是，从待处理酉矩阵中迭代分解所得到的量子比特均匀控制门所对应的量子比特的数量，与待处理酉矩阵所对应的量子比特的数量是相同的，也即，当待处理酉矩阵是n-量子比特酉矩阵时，电子设备会将n-量子比特酉矩阵进行n次的迭代分解，每次迭代分解时都会得到一个或多个n-量子比特均匀控制门(UCG，n-qubit Uniformly Controlled Gate)，以及需要继续进行分解的量子比特酉矩阵，电子设备继续对所得到的量子比特酉矩阵进行分解，如此迭代，直至完成n次的迭代分解时，得到第一数量的n-量子比特均匀控制门。
需要说明的是，n-量子比特均匀控制门的作用是在2n-1种不同的控制下，在目标位上采用不同的单量子比特门。示例性的，图5是本申请实施例提供的n-量子比特均匀控制门的示意图，集合S＝{s1,s2,…,sn-1}表示控制位量子比特的编号，t表示目标位量子比特的编号，n-量子比特均匀控制门包含了一系列的单量子比特门当单量子比特门为旋转门Rz(θ)时，那么为n-量子比特对角酉矩阵，记为
在一些实施例中，步骤S101中的对待处理酉矩阵进行迭代分解，可以通过如下处理过程实现：令i为依次递增的正整数，且1≤i≤n，n是量子比特的数量，迭代i执行以下处理：对第i次迭代的初始酉矩阵进行矩阵分解，得到第i次迭代的分解结果，其中，第1次迭代的初始酉矩阵为待处理酉矩阵；从第i次迭代的分解结果中提取第i次迭代的量子比特均匀控制门，以及第i次迭代的生成酉矩阵；将第i次迭代的生成酉矩阵，确定为第i+1次迭代的初始酉矩阵；将n次迭代得到的2n-1个个量子比特均匀控制门，确定为第一数量的量子比特均匀控制门。
需要说明的是，i为依次递增的正整数，且1≤i≤n，n是量子比特的数量。第i次迭代的量子比特均匀控制门中的第i位是目标位，剩余的n-1位均为控制位，第i次迭代的生成酉矩阵对应的量子比特会比第i次迭代的初始酉矩阵对应的量子比特减少一个。
例如，当任意n-量子比特酉矩阵(即待处理酉矩阵)对应的n个量子比特分别标记为{1,2,…,n}时，电子设备可对n-量子比特酉矩阵进行cosine-sine分解(即矩阵分解)，得到如下形式的分解结果：
其中，为(n-1)-量子比特酉矩阵(即第1轮迭代的生成酉矩阵)，均为对角矩阵，且对角元素分别为和 是目标位为第1个量子比特的n-量子比特均匀控制门(即第1次迭代的量子比特均匀控制门)，记为从而第1次迭代的cosine-sine分解可以写为：
由于Vn-1,1,Vn-1,2,V′n-1,1,V′n-1,2为(n-1)-量子比特酉矩阵，可以继续进行cosine-sine分解(即矩阵分解)，得到如下形式：

其中，i∈[2]，Ln-2,1(i)，Ln-2,2(i)，L′n-2,1(i)，L′n-2,1(i)，Rn-2,1(i)，Rn-2,2(i)，R′n-2,1(i)，R′n-2,1(i)为(n-2)量子比特酉矩阵(第2次迭代的生成酉矩阵)，Cn-2(i),Sn-2(i),C′n-2(i),为对角矩阵，对角元素分别为 和因此，矩阵U可以展开为如下形式：

其中，第2个矩阵(即)和第6个矩阵(即)是目标位为第2个量子比特的n-量子比特均匀控制门剩余的矩阵(即第2次迭代的生成酉矩阵)是需要继续进行cosine-sine分解的对角矩阵(即第3轮迭代的初始酉矩阵)。
如此反复迭代，直至将i迭代至n，可以得到U的最终展开式，其由2n-1个n-量子比特均匀控制门的累乘得到。从而，U可以写为：
其中，ζ(i)是由标尺函数计算得到，标尺函数的定义为： (表示不能整除，|表示可以整除)。
示例性的，图8是本申请实施例提供的对待处理酉矩阵的分解结果示意图，待处理酉矩阵对应3个量子比特(记为1、2和3)，即待处理酉矩阵为3-量子比特酉矩阵，电子设备对3-量子比特酉矩阵进行分解，可以得到7个3-量子比特均匀控制门，即(目标位是第3个量子比特，控制位是第1个量子比特和第2个量子比特)、(目标位是第2个量子比特，控制位是第1个量子比特和第3个量子比特)、(目标位是第1个量子比特，控制位是第2个量子比特和第3个量子比特)、和
由上述内容可见，电子设备只需要实现n-量子比特均匀控制门在连通图的限制下的电路，就能够实现待处理酉矩阵在连通图的限制下的量子电路。
S102、将每个量子比特均匀控制门，分解为第二数量的量子比特对角酉矩阵和第三数量的单量子比特门。
由于量子比特均匀控制门中的任意的对角矩阵(主对角线之外的元素皆为0的矩阵)，都可以分解为旋转门Rz(θ)、Hadmard门H、相位门S和逆相位门电子设备通过对每个对角矩阵进行分解，实现对量子比特均匀控制门的分解，得到量子比特对角酉矩阵和单量子比特门。而由于单量子比特门的量子电路是已知的，因此，本申请实施例中是 基于对待处理酉矩阵的迭代分解，以及对量子比特均匀控制门的分解，将待处理酉矩阵的实现问题进一步转化为量子比特对角酉矩阵的电路实现问题(对角酉矩阵相对应酉矩阵更易实现)。
下面结合公式(1)-(3)具体说明量子比特均匀控制门的分解过程.
任意n-量子比特均匀控制门的每个对角元素均为对角矩阵，如公式(1)所示：
其中，Vn表示n-量子比特均匀控制门，Uk表示对角矩阵，其中，k∈[2n-1]。
针对任意的对角矩阵Uk，可以进行如公式(2)的分解：
其中，Rz表示旋转门、S表示相位门，H表示Hadmard门，表示逆相位门。
那么，任意的n-量子比特均匀控制门可以分解为如公式(3)所示的形式：
其中，表示n-1量子比特的单位算子(表示规模为(2n-1)×(2n-1)的单位矩阵，(2n-1)×(2n-1)规模的算子可以应用在n-1量子比特上实现)。A1、A2、A4和A6均为n-量子比特的对角酉矩阵，Hadmard门H、相位门S和逆相位门均为单量子比特门。A1和A2可以合并为一个n-量子比特的对角酉矩阵，因此，电子设备针对任意一个n-量子比特均匀控制门，可以分解得到3个(第二数量)n-量子比特对角酉矩阵(即A1·A2、A4和A6)和4个(第三数量)单量子比特门(即A3中的Hadmard门H和相位门S，A3中的Hadmard门H和逆相位门)。
示例性的，图6是本申请实施例提供的对量子比特均匀控制门进行分解的示意图。电子设备对从待处理酉矩阵中分解得到的n-量子比特均匀控制门进行分解(集合S＝{s1,s2,…,sn-1}表示控制位量子比特的编号，t表示目标位量子比特的编号)，得到3个n-量子比特对角酉矩阵，即和(其中，对应公式(3)中的A6，对应公式(3)中的A4，是公式(3)中A1和A2的合并(即A1·A2))，以及4个单量子比特门(公式(3)从左至右分别为H、H和S)。可见，电子设备只需要实现n-量子比特对角酉矩阵和的电路，即R1、R2和R3，就能够实现n-量子比特均匀控制门的电路U。
综上，结合S102中将n-量子比特均匀控制门分解为n-量子比特对角酉矩阵可知，只需要实现n-量子比特对角酉矩阵的匹配量子电路，就能够得到n-量子比特均匀控制门的目标量子电路，进而得到待处理酉矩阵在连通图的限制下的量子电路。
S103、在连通图的限制下，确定与每个量子比特对角酉矩阵对应的匹配量子电路。
本申请实施例中，电子设备需要在连通图的限制下，实现量子比特对角酉矩阵的电路，将所得到的电路记为匹配量子电路。电子设备基于连通图对n个量子比特确定编号信息，依据编号信息确定量子比特对，并通过在量子比特对应用的双量子比特门，递归 实现量子比特对角酉矩阵的匹配量子电路。
需要说明的是，连通图中包括的任意两节点都是连通的，即任意两节点之间有边相连，其中，连通图中的节点与量子比特一一对应，即连通图中的节点表示量子比特。连通图的限制是指量子电路中的双量子比特门仅允许作用在连通图中有边相连的两个量子比特下。示例性的，图7是本申请实施例提供的连通图的示意图，连通图G＝(V,E)中的V＝{q1,q2,…,qn}是指连通图中n个节点的集合，E表示连通图中边的集合。连通图G的节点表示量子电路中的量子比特，那么在连通图G的限制下，量子比特对(q1,q2),(q2,q3),(q2,q4),(q4,q5)之间有边相连，因此，双量子比特门(例如CNOT门)仅仅允许作用在量子比特对(q1,q2),(q2,q3),(q2,q4),(q4,q5)上。
基于连通图所得到的编号信息存在一个优点，即编号信息为k∈[n]([n]是n个量子比特的编号信息的集合)的量子比特到编号信息为n的量子比特的距离不会超过n-k，如此，能够限制双量子比特门在路径限制下电路实现时的电路大小，从而限制匹配量子电路的大小。
下面，对连通图限制下实现量子比特对角酉矩阵对应的匹配量子电路的过程进行说明。
参见图9，图9是本申请实施例提供的量子电路优化方法的另一个流程示意图。在一些实施例中，由于不同的n-量子比特均匀控制门的控制位、目标位可能存在不同，从不同的n-量子比特均匀控制门所分解得到的n-量子比特对角酉矩阵的目标位、控制位可能存在不同。而对于对角酉矩阵和对角酉矩阵可以通过电路大小不超过O(n)的CNOT电路进行相互转换，因此，电子设备可以选择作为基准对角酉矩阵，确定匹配量子电路(即基准量子电路)，然后再通过CNOT门转换得到剩余对角酉矩阵的转换量子电路，从而就能够得到任意n-量子比特对角酉矩阵的匹配量子电路。即S103的具体实现过程，可以包括：S1031-S1035，如下：
S1031、在连通图的限制下，确定n个量子比特分别对应的编号信息。
在一些实施例中，步骤S1031可以通过以下方案二实现：从连通图中抽取目标树；对目标树中的每个节点进行编号，得到每个节点所对应的节点编号；将每个节点所对应的节点编号，确定为每个节点所对应的量子比特的编号信息。其中，目标树是连通图中的任意一个生成树，每个量子比特对应目标树中的一个节点。
例如，电子设备从连通图G＝(V,E)中任意抽取一个生成树，通过该生成树对n个量子比特进行编号。其中，生成树的节点是连通图G＝(V,E)中的全部节点，边是连通图G＝(V,E)中的边的一部分，即V(G′)＝V(G)，其中，G′表示生成树，且同时满足边集E(G′)中的所有边既能够使得全部节点连通，而又不形成回路。
更详细的，方案二中的对目标树中的每个节点进行编号，得到每个节点所对应的节点编号，可以通过以下步骤实现：针对目标树中的每个节点生成初始化编号；当节点编号为第n-k+2的个节点不存在子节点或者编号为初始化编号的子节点时，从已节点编号的节点中查询符合查询条件的目标节点，并将目标节点最左侧的子节点的节点编码确定为第n-k+1个节点；当节点编码为第n-k+2的个节点存在子节点、，且子节点的编号为初始化编号时，将编号为初始化编号的子节点中最左侧的子节点的节点编码，确定为第n-k+1。
其中，查询条件为编号最大、且存在编号为初始化编号的子节点的节点，3≤k≤n，节点编码为n的节点是目标树的根节点(即第n个节点是目标树的根节点)，节点编码为n-1的节点是根节点最左侧的节点(即第n-1个节点是根节点最左侧的节点)。也就是说，电子设备会先访问生成树的根节点，将根节点编号为n，然后访问根节点的最左边的子节点，将该节点编号为n-1。接着继续向下访问，当访问到的节点标号为n-k+2 (3≤k≤n)时，若节点n-k+2没有叶子节点或者没有被编号为0(0为初始化编号)的叶子节点，则找到节点合集{n-k+2,n-k+3,…,n}(即已节点编号的节点)中编号最大且拥有编号为0的子节点的节点，访问该节点最左边的标号为0的节点，将其编号为n-k+1，若节点n-k+2存在标号为0的子节点，则访问其最左边的标号为0的子节点，将其编号为n-k+1。
示例性的，图12是本申请实施例提供的对量子比特进行编号的示意图。对于连通图G，首先抽取一个生成树T，将生成树T中的所有节点编号为0(即初始化编号)。首先，访问T的根节点，将其的节点编号确定为5，然后访问节点5最左边编号为0的子节点，将其的节点编号确定为4。由于节点4没有子节点，则退回到节点5，并访问剩余的编号为0的子节点中最左边的子节点，将其的节点编号确定为3，节点3存在编号为0的子节点，将该子节点的节点编号确定为2。由于节点2没有子节点，退回到节点3，且节点3没有其余编号为0的子节点，继续退回到节点5，然后访问节点5的剩余编号为0的子节点中最左边的子节点，将其的节点编号确定为1。由此，就得到了5个量子比特的编号信息，该编号信息表示了这5个量子比特的访问次序。
通过上述的编号方式，将n个量子比特可以标记为[n]。这种编号方式存在一个优点，就是编号信息为k∈[n]的节点到编号信息为n的节点的距离不会超过n-k，且{k,k+1,k+2,…,n}所生成的子图为连通图。
S1032、依据n个量子比特的编号信息，从量子比特对角酉矩阵中提取基准对角酉矩阵。其中，基准对角酉矩阵的目标位是编码信息为n的量子比特，控制位是编码信息为前n-1的量子比特。
S1033、依据n个量子比特的编号信息，确定基准对角酉矩阵对应的基准量子电路。
在对基准对角酉矩阵(即)确定基准量子电路之前，首先引入基准对角酉矩阵在标准基下的变换的定义：
其中，|x>是标准基，是实数集。针对实数集，可以进行如下的定义：{αs:s∈{0,1}n-{0n}}：
为了方便，可以定义接下来，对的基准量子电路的实现进行说明。
参见图10，图10是本申请实施例提供的量子电路优化方法的又一个流程示意图。在一些实施例中，S1033的具体实现过程，可以包括：S1033a-S1033e，如下：
S1033a、针对基准对角酉矩阵生成多个量子比特序列。
例如，当基准对角酉矩阵为时，电子设备会构造2n-1个长度为n-1的量子比特序列：
在一些实施例中，针对基准对角酉矩阵生成多个量子比特序列，可以通过以下处理实现：确定第j个量子比特序列的待翻转量子比特，并将待翻转量子比特上的元素进行翻转，得到第j+1个量子比特序列；当迭代j的取值2n-1时，将2n-1个量子比特序列确定为基准对角酉矩阵的多个量子比特序列。
需要说明的是，2≤j≤2n-1，第1个量子比特序列是利用n-1个第二元素排列而成，例如当第二元素为0时，第1个量子比特序列是由n-1个0排列而成的。待翻转量子比特是由n和j的标尺函数值相减得到的。
也即，第1个量子比特序列c1＝0n-1，当时，量子比特序列cj由cj-1翻转第n-ζ(j-1)位得到。结合标尺函数的性质，可知，由c1翻转第1位得到，并且
S1033b、在每个量子比特序列的尾部分别增加第一元素，得到多个第一量子比特序 列，并在每个量子比特序列的尾部分别增加第二元素，得到多个第二量子比特序列。
例如，第一元素可以取1，第二元素可以取0，这样，电子设备就是将每个长度为n-1的量子比特序列，扩展为2个长度为n的量子比特序列。例如，当多个量子比特序列分别为00，01，10，11时，多个第一量子比特序列可以为001，011，101，111，多个第二量子比特序列可以为000，010，100，110。
S1033c、依据n个量子比特的编号信息，确定基准对角酉矩阵对应的第一量子电路；其中，第一量子电路用于将多个第一量子比特序列对应的相位加载到标准基中。
例如，当第一元素为1时，将第一量子比特序列所对应的相位加载到标准基的量子电路，得到基准对角酉矩阵对应的第一量子电路。结合上述定义的基准对角酉矩阵在标准基下的变换和实数集，步骤S1033c中，电子设备就是要确定实现变换量子电路，其中，c是指多个量子比特序列的统称，c1是在每个量子比特序列的尾部分别补1所得到的第一量子比特序列的统称，αc1是第一量子比特序列所构成的实数集。
更详细的，S1033c可以通过以下处理实现：依据n个量子比特的编号信息，确定第j个第一量子比特序列的匹配CNOT门；基于第j+1个第一量子比特序列，构造应用在第j个第一量子比特序列的匹配CNOT门之后的匹配R量子门；当j达到2n-1-1时，对2n-1-1个匹配CNOT门和匹配R量子门进行交替连接，得到候选子电路；确定补充R量子门和补充CNOT门，并对补充R量子门和补充CNOT门连接，得到补充子电路；基于候选子电路以及补充子电路，确定第一量子电路。其中，j为依次递增的正整数，且1≤j≤2n-1-1，2n-1是第一量子比特序列的数量。
其中，匹配CNOT门的目标位为编号信息为n的量子比特，控制位为编号信息为n-ζ(j)的量子比特，即电子设备在编号信息为n的量子比特和编号信息为n-ζ(j)(ζ(j)由上述标尺函数的定义计算得到)的量子比特上应用CNOT门，该CNOT门用于对第一量子比特序列进行处理。换句话说，第j个第一量子比特序列的匹配CNOT门的控制位对应的编号信息由n与j计算得到，目标位是编号信息为n的量子比特。
还需要说明的是，补充R量子门是第1个量子比特序列确定得到，补充CNOT门的控制位是编号信息为1的量子比特，补充CNOT门的目标位是编号信息为n的量子比特。
示例性的，式(2)是第一量子电路的公式示意：
其中，αc1是第一量子比特序列所构成的实数集，表示匹配CNOT门，表示匹配R量子门，表示补充CNOT门，表示补充R量子门。
公式(2)可以由以下过程实现：
S1033d、依据n个量子比特的编号信息，确定基准对角酉矩阵对应的第二量子电路；第二量子电路用于将多个第二量子比特序列对应的相位加载到标准基中。
在一些实施例中，步骤S1033d可以通过如下方案一实现：确定基准对角酉矩阵对应的待实现对角酉矩阵，其中，待实现对角酉矩阵对应n-1个量子比特；通过变换电路，对待实现酉矩阵进行分解，得到置换对角酉矩阵，其中，变换电路用于将待实现酉矩阵对应的第一量子比特集合中的量子态，置换到第二量子比特集合中的量子态；依据n个量子比特的编号信息，确定置换对角酉矩阵对应的置换量子电路；将变换电路、置换量子电路以及变换电路对应的逆变换电路的连接结果，确定为第二量子电路；其中，逆变换电路用于将第二量子比特集合中的量子态，置换到第一量子比特集合中的量子态(例如逆变换电路将量子比特转换为初始位置，即原先的量子态)。
下面对上述方案一进行示例说明，当第二元素为0时，将第二比特序列所对应的相位加载到标准基的量子电路，从而得到第二量子电路。结合上述定义的基准对角酉矩阵在标准基下的变换和实数集，电子设备是要实现 的量子电路，作为第二量子电路，其中，c0是在比特序列的末尾补0所得到的第二量子比特序列，αc0是第二量子比特序列所构成的实数集。
实现其实就是实现在量子比特集合[n-1]上的(n-1)-量子比特对角酉矩阵(待实现对角酉矩阵)，即
而由于量子比特集合[n-1](即第一量子比特集合)生成的图不一定是连通图，但是量子比特集合[n]-{1}(即第二量子比特集合)生成的图是连通图，因此，为了实现本申请实施例可以先确定一个能够将待实现对角酉矩阵的量子比特集合[n-1] 中的量子态置换到量子比特集合[n]-{1}的交换电路，即交互电路用于将待实现对角酉矩阵对应的第一量子比特集合中的量子态置换到第二量子比特集合中的量子态，例如，量子比特集合[n-1]是编号为1、2、3、……、n-1这些量子比特所构成的集合，这些量子比特各自量子态表示为x1>、x2>、……、xn-1>，此时编号为n的量子比特的量子态为xn>，量子比特集合[n]-{1}是编号为2、3、……、n这些量子比特所构成的集合，则将量子比特集合[n-1]中的量子态置换到量子比特集合的置换过程为：将编号为2、3、……、n这些量子比特的量子态，分别替换为x1>、x2>、……、xn-1>，此时编号为n的量子比特的量子态为xn-1>。然后，通过以下方式对待实现酉矩阵进行分解：基于变换电路对应的酉矩阵、逆变换电路对应的酉矩阵，对待实现酉矩阵进行分解，得到一个在量子比特集合[n]-{1}上的(置换对角酉矩阵)，其中，分解原理如下：由于与之间满足Y＝PXP-1的关系(Y表示待实现酉矩阵，P表示变换电路对应的酉矩阵，P-1表示逆变换电路对应的酉矩阵，X表示置换对角酉矩阵)，当确定交换电路后，交互电路的酉矩阵以及逆交换电路的酉矩阵均为已知量，据此通过矩阵变换(即通过对Y左乘P-1、右乘P，对Y进行分解)，得到然后，通过以下方式确定的量子电路(置换量子电路)：由于受到连通图的限制，因此可以依据n个量子比特的编号信息对置换对角酉矩阵进行分解，将最后分解得到的量子门所对应的量子电路进行连接，得到置换量子电路，例如，将作为新的基准对角酉矩阵以执行步骤S1033a-S1033e，得到的置换量子电路，即通过步骤S1033针对构造量子比特序列，通过步骤S1033b在量子比特序列的尾部分别补0和补1得到的第一量子比特序列和第二量子比特序列，然后按照与S1033c的过程类似的方式，确定对应的第一量子电路，按照步骤S1033d的方法，确定的第二量子电路，按照步骤S1033e确定的置换量子电路。在确定的量子电路(置换量子电路)后，在置换量子电路的基础上，连接变换电路以及变换电路对应的逆变换电路，得到第二量子电路。
S1033e、基于第一量子电路和第二量子电路，确定基准对角酉矩阵的基准量子电路。
电子设备先将第一量子电路作用在n个量子比特上，然后再将第二量子电路也作用在n个量子比特上，所得到的整体电路就是基准量子电路。也可以说，电子设备将第一量子电路和第二量子电路进行连接，得到了基准量子电路。
示例性的，图11是本申请实施例提供的基准量子电路的示意图。在编号信息分别为1、2、……、n-1、n的量子比特上，应用第一量子电路和第二量子电路，其中，第二量子电路包括转换电路P、置换量子电路和逆转换电路
S1034、通过CNOT门，对基准量子电路进行转换，得到剩余对角酉矩阵对应的转换量子电路。
需要说明的是，剩余对角酉矩阵是量子比特对角酉矩阵中除去基准对角酉矩阵之外的对角酉矩阵。
S1035、将基准对角酉矩阵对应的基准量子电路、以及剩余对角酉矩阵对应的转换量子电路，确定为量子比特对角酉矩阵的匹配量子电路。
S104、对第二数量的匹配量子电路和第三数量的单量子比特门进行整合，得到每个量子比特均匀控制门的目标量子电路。
其中，单量子比特门是已知的量子电路，电子设备基于上述步骤S103中所求得的 受到连通图限制的匹配量子电路之后，步骤S104可以通过以下方式实现：按照顺序，将匹配量子电路和单量子比特门进行连接，得到每个量子比特均匀控制门的目标量子电路，其中，该顺序为将量子比特均匀控制门进行分解所得到的量子比特对角酉矩阵和单量子比特门的分解顺序，例如图6的顺序。最终，电子设备会得到与多个量子比特均匀控制门一一对应的多个的目标量子电路。
例如，如图6所示，H、H、S是已知的量子电路，当通过步骤S103得到R1、R2和R3分别对应的匹配量子电路后，按照R1、H、R2、H、S、R3的顺序(也就是量子比特均匀控制门分解成量子比特对角酉矩阵和单量子比特门的分解顺序)，连接已知的量子电路(即单量子比特门H、H、S)以及匹配量子电路(即R1、R2和R3分别对应的匹配量子电路)，得到n-量子比特均匀控制门的目标量子电路。
S105、对第一数量的目标量子电路进行连接，得到优化后的量子电路。
这里，电子设备基于上述步骤S104得到第一数量的目标量子电路后，按照量子比特均匀控制门的迭代分解顺序，将第一数量的目标量子电路进行连接，得到优化后的量子电路(即待优化量子电路对应的优化量子电路)，其中，迭代分解顺序为对待处理酉矩阵进行迭代分解所得到的量子比特均匀控制门的顺序。由上述内容可知，优化量子电路所需要的运算时间，少于待优化量子电路的运算时间。
综上，本申请实施例是在连通图的限制下，对待优化量子电路进行优化的场景下实现的，以通过对待优化量子电路进行优化，得到能够实现与待优化量子电路相同的功能，但是量子门更少(也就是所需的计算时间更少)的优化量子电路。每个量子电路都有对应的酉矩阵，本申请实施例中，电子设备先针对待处理量子电路进行酉矩阵的转换，所得到的酉矩阵就是待处理酉矩阵。由于待优化量子电路结构较为复杂，在不改变功能、且受到连通图限制的前提下是难以对待优化量子电路进行优化的，而酉矩阵的量子电路实现过程较为简单，因此，本申请实施例先针对待优化量子电路转换所得到的待处理酉矩阵进行迭代分解，再对分解得到的量子比特均匀控制门进行分解，得到量子比特对角酉矩阵和单量子比特门，以实现递归地将量子电路优化问题转换为量子比特对角酉矩阵的量子电路实现问题，并在连通图的限制下，针对量子比特对角酉矩阵确定匹配量子电路，最终基于匹配量子电路和单量子比特门整合得到优化量子电路，从而得到在连通图的限制下的最优的量子电路，即运算速度更快的优化量子电路，也就提升了量子电路优化的效果。并且，当所得到的优化量子电路应用到量子计算设备中，会使得量子计算设备的运算速度加快，也就提高了量子计算设备的运算效率。
综上，对本申请实施例提供的量子优化方法的优化效果进行说明。
首先，引入CNOT门和交换门在路径限制下的电路实现：
1、CNOT门在路径下的电路实现：示例性的，图13是本申请实施例提供的CNOT门在路径限制下的电路实现的示意图，参见图13，可见在路径i-(i+1)-…-(j-1)-j限制下，可以被深度和大小均为O(j-i)的CNOT电路实现。
2、交换门的电路实现：由于在路径i-(i+1)-…-(j-1)-j的限制下，可以被深度和大小均为(j-i)的CNOT电路实现。
3、在任意连通图限制下CNOT电路的压缩：在连通图的限制下，任意CNOT门组成的n-量子比特电路的大小可以被压缩至O(n2)。
下面分析n-量子比特对角酉矩阵在连通图G的限制下递归实现的电路大小。设S[n]-[k]表示作用在量子比特集合[n]-[k]上的对角酉矩阵的电路大小，其中，定义在确定第一量子电路时，由连通图下量子比特的编号信息可知， 中控制位n-ζ(j)和目标位n的距离不超过ζ(j)，结合CNOT门在路径限制下的实现可知，可被大小为O(ζ(j))的电路实现。再由于标尺函数存在如下性质：在集合中，元素k出现2n-1-k次，从而第一量子电路大小为：
在第二量子电路的构造过程中，两次置换的电路大小为O((n-0)2)＝O(n2)。从而，S[n]-[0]满足以下递推式：
综上，n-量子比特对角酉矩阵在连通图限制下的电路大小为O(2n)，从而n-量子比特均匀控制门的电路大小为3·O(2n)+4＝O(2n)。再结合对n-量子比特酉矩阵分解得到2n-1个n-量子比特均匀控制门，可见，在连通图限制下，n-量子比特酉矩阵可以被大小为O(2n)·(2n-1)＝O(4n)的电路实现。从而，本申请实施例提供的量子优化方法，能够得到渐进意义上最优的量子电路，即得到运算速度更快的优化量子电路，并且当该优化量子电路应用到量子计算设备中时，能够使得量子计算设备的运算速度加快，提高量子计算设备的运算效率。
此外，由于本申请实施例用大小为的O(2n)电路在连通图限制下实现了任意n-量子比特均匀控制门，而量子态制备电路可以分解为n个大小分别为1,2,…,n量子比特均匀控制门，因此，本申请实施例可以实现连通图限制下的电路大小为O(2n)的量子态制备电路，从而使得在连通图限制下量子态制备电路的大小也是最优的。
下面继续说明本申请实施例提供的量子电路优化装置255的实施为软件模块的示例性结构，在一些实施例中，如图3所示，存储在存储器250的量子电路优化装置255中的软件模块可以包括：
矩阵分解模块2551，配置为将待优化量子电路转换为待处理酉矩阵，并对所述待处理酉矩阵进行迭代分解，得到第一数量的量子比特均匀控制门；控制门分解模块2552，配置为将每个所述量子比特均匀控制门，分解为第二数量的量子比特对角酉矩阵和第三数量的单量子比特门；电路实现模块2553，配置为在连通图的限制下，确定与每个所述量子比特对角酉矩阵对应的匹配量子电路；连接整合模块2554，配置为对第二数量的所述匹配量子电路和第三数量的所述单量子比特门进行整合，得到每个所述量子比特均匀控制门的目标量子电路；对第一数量的所述目标量子电路进行连接，得到优化后的量子电路。
在一些实施例中，所述矩阵分解模块2551，还配置为针对第i次迭代执行以下处理：
对第i次迭代的初始酉矩阵进行矩阵分解，得到第i次迭代的分解结果，其中，第1次迭代的初始酉矩阵为所述待处理酉矩阵，i为依次递增的正整数，且1≤i≤n，n是量子比特的数量；从第i次迭代的分解结果中提取第i次迭代的量子比特均匀控制门，以及第i次迭代的生成酉矩阵；将所述第i次迭代的生成酉矩阵，确定为第i+1次迭代的初始酉矩阵；将n次迭代得到的2^(n-1)个量子比特均匀控制门，确定为第一数量的所述量子比特均匀控制门。
在一些实施例中，所述电路实现模块2553，还配置为在所述连通图的限制下，确定所述n个量子比特分别对应的编号信息；依据所述n个量子比特的编号信息，从所述量子比特对角酉矩阵中提取基准对角酉矩阵，其中，所述基准对角酉矩阵的目标位是编码信息为n的量子比特，控制位是编码信息为前n-1的量子比特；依据所述n个量子比特的编号信息，确定所述基准对角酉矩阵对应的基准量子电路；通过受控反闸CNOT门，对所述基准量子电路进行转换，得到剩余对角酉矩阵对应的转换量子电路，其中，所述剩余对角酉矩阵是所述量子比特对角酉矩阵中除去所述基准对角酉矩阵之外的对角酉矩阵；将所述基准对角酉矩阵对应的基准量子电路、以及所述剩余对角酉矩阵对应的转换量子电路，确定为所述量子比特对角酉矩阵的所述匹配量子电路。
在一些实施例中，所述电路实现模块2553，还配置为针对所述基准对角酉矩阵生成多个量子比特序列；在每个所述量子比特序列的尾部分别增加第一元素，得到多个第一量子比特序列，并在每个所述量子比特序列的尾部分别增加第二元素，得到多个第二量子比特序列；依据所述n个量子比特的编号信息，确定所述基准对角酉矩阵对应的第一量子电路，其中，所述第一量子电路用于将多个所述第一量子比特序列对应的相位加载到标准基中；依据所述n个量子比特的编号信息，确定所述基准对角酉矩阵对应的第二量子电路，所述第二量子电路用于将多个所述第二量子比特序列对应的相位加载到所述标准基中；基于所述第一量子电路和所述第二量子电路，确定所述基准对角酉矩阵对应的所述基准量子电路。
在一些实施例中，所述电路实现模块2553，还配置为依据所述n个量子比特的编号信息，确定第j个所述第一量子比特序列的匹配CNOT门，j为依次递增的正整数，且1≤j≤2n-1-1；基于第j+1个所述第一量子比特序列，构造应用在第j个所述第一量子比特序列的匹配CNOT门之后的匹配R量子门；当j达到2n-1-1时，对2n-1-1个匹配CNOT门和匹配R量子门进行交替连接，得到候选子电路；确定补充R量子门和补充CNOT门，并对所述补充R量子门和所述补充CNOT门进行连接，得到补充子电路；基于所述候选子电路以及所述补充子电路，确定所述第一量子电路。
在一些实施例中，所述补充R量子门基于第1个量子比特序列确定得到，所述补充CNOT门的控制位是编号信息为1的量子比特，所述补充CNOT门的目标位是编号信息为n的量子比特；第j个所述第一量子比特序列的匹配CNOT门的控制位对应的编号信息由n与j计算得到，第j个所述第一量子比特序列的匹配CNOT门的目标位是编号信息为n的量子比特。
在一些实施例中，所述电路实现模块2553，还确定所述基准对角酉矩阵对应的待实现对角酉矩阵，其中，所述待实现对角酉矩阵对应n-1个量子比特；通过变换电路，将所述待实现酉矩阵对应的第一量子比特集合中的量子态，置换为第二量子比特集合中的量子态，将置换后的所述待实现酉矩阵确定为置换对角酉矩阵；依据所述n个量子比特的所述编号信息，确定所述置换对角酉矩阵对应的置换量子电路；将所述变换电路、所述置换量子电路以及所述变换电路对应的逆变换电路的连接结果，确定为所述第二量子电路，其中，所述逆变换电路用于将第二量子比特集合中的量子态，置换为所述第一量子比特集合中的量子态。
在一些实施例中，所述电路实现模块2553，还配置为确定第j个量子比特序列的待翻转量子比特，并将所述待翻转量子比特上的元素进行翻转，得到第j+1个量子比特序列；其中，2≤j≤2n-1，第1个量子比特序列是通过n-1个第二元素排列得到；当迭代j的取值达到2n-1时，将2n-1个量子比特序列确定为所述基准对角酉矩阵的多个所述量子比特序列。
在一些实施例中，所述电路实现模块2553，还配置为从所述连通图中抽取目标树， 其中，所述目标树是所述连通图中的任意一个生成树，每个量子比特对应所述目标树中的一个节点；对所述目标树中的每个节点进行编号，得到所述每个节点所对应的节点编号；将所述每个节点所对应的节点编号，确定为每个节点所对应的量子比特的编号信息。
在一些实施例中，所述电路实现模块2553，还配置为针对所述目标树中的每个节点生成初始化编号；当所述节点编号为n-k+2的节点不存在子节点或者编号为初始化编号的子节点时，从已节点编号的节点中查询符合查询条件的目标节点，并将所述目标节点最左侧的子节点的节点编码确定为n-k+1；其中，所述查询条件为编号最大、且存在编号为初始化编号的子节点的节点；3≤k≤n，所述节点编码为n的节点是所述目标树的根节点，所述节点编码为n-1的节点是所述根节点最左侧的节点；当所述节点编码为n-k+2的节点存在子节点、且所述子节点的编号为初始化编号时，将所述编号为初始化编号的子节点中最左侧的子节点的节点编码，确定为n-k+1。
本申请实施例提供了一种计算机程序产品或计算机程序，该计算机程序产品或计算机程序包括计算机指令，该计算机指令存储在计算机可读存储介质中。电子设备的处理器从计算机可读存储介质读取该计算机指令，处理器执行该计算机指令，使得该电子设备执行本申请实施例上述的量子电路优化方法。
本申请实施例提供一种存储有可执行指令的计算机可读存储介质，其中存储有可执行指令，当可执行指令被处理器执行时，将引起处理器执行本申请实施例提供的量子电路优化方法，例如，如图4示出的量子电路优化方法。
在一些实施例中，计算机可读存储介质可以是FRAM、ROM、PROM、EPROM、EEPROM、闪存、磁表面存储器、光盘、或CD-ROM等存储器；也可以是包括上述存储器之一或任意组合的各种设备。
在一些实施例中，可执行指令可以采用程序、软件、软件模块、脚本或代码的形式，按任意形式的编程语言(包括编译或解释语言，或者声明性或过程性语言)来编写，并且其可按任意形式部署，包括被部署为独立的程序或者被部署为模块、组件、子例程或者适合在计算环境中使用的其它单元。
作为示例，可执行指令可被部署为在一个电子设备上执行，或者在位于一个地点的多个电子设备上执行，又或者，在分布在多个地点且通过通信网络互连的多个电子设备上执行。
综上所述，通过本申请实施例，电子设备先针对待优化量子电路转换所得到的待处理酉矩阵进行迭代分解，再对分解得到的量子比特均匀控制门进行分解，得到量子比特对角酉矩阵和单量子比特门，以实现递归地将量子电路优化问题转换为量子比特对角酉矩阵的量子电路实现问题，并在连通图的限制下，针对量子比特对角酉矩阵确定匹配量子电路，最终基于匹配量子电路和单量子比特门整合得到优化量子电路，从而得到在连通图的限制下的最优的量子电路，即运算速度更快的优化量子电路，也就提升了量子电路优化的效果；且该优化量子电路应用到量子计算设备中时，能够加快量子计算设备的运算速度，即提高量子计算设备的运算效率；可以实现连通图限制下的电路大小为O(2n)的量子态制备电路，从而使得在连通图限制下量子态制备电路的大小也是最优的。
以上所述，仅为本申请的实施例而已，并非用于限定本申请的保护范围。凡在本申请的精神和范围之内所作的任何修改、等同替换和改进等，均包含在本申请的保护范围之内。

Claims (15)

  1. 一种量子电路优化方法，应用于电子设备，所述方法包括：
    将待优化量子电路转换为待处理酉矩阵，并对所述待处理酉矩阵进行迭代分解，得到第一数量的量子比特均匀控制门；
    将每个所述量子比特均匀控制门，分解为第二数量的量子比特对角酉矩阵和第三数量的单量子比特门；
    在连通图的限制下，确定与每个所述量子比特对角酉矩阵对应的匹配量子电路；
    对第二数量的所述匹配量子电路和第三数量的所述单量子比特门进行整合，得到每个所述量子比特均匀控制门的目标量子电路；
    对第一数量的所述目标量子电路进行连接，得到优化后的量子电路。
  2. 根据权利要求1所述的方法，其中，所述对所述待处理酉矩阵进行迭代分解，得到第一数量的量子比特均匀控制门，包括：
    令i为依次递增的正整数，且1≤i≤n，n是量子比特的数量，迭代i执行以下处理：
    对第i次迭代的初始酉矩阵进行矩阵分解，得到第i次迭代的分解结果，其中，第1次迭代的初始酉矩阵为所述待处理酉矩阵；
    从第i次迭代的分解结果中提取第i次迭代的量子比特均匀控制门，以及第i次迭代的生成酉矩阵；
    将所述第i次迭代的生成酉矩阵，确定为第i+1次迭代的初始酉矩阵；
    将n次迭代得到的2n-1个量子比特均匀控制门，确定为第一数量的所述量子比特均匀控制门。
  3. 根据权利要求1或2所述的方法，其中，
    所述量子比特对角酉矩阵对应n个量子比特；
    所述在连通图的限制下，确定与每个所述量子比特对角酉矩阵对应的匹配量子电路，包括：
    在所述连通图的限制下，确定所述n个量子比特分别对应的编号信息；
    依据所述n个量子比特的编号信息，从所述量子比特对角酉矩阵中提取基准对角酉矩阵，其中，所述基准对角酉矩阵的目标位是编码信息为n的量子比特，控制位是编码信息为前n-1的量子比特；
    依据所述n个量子比特的编号信息，确定所述基准对角酉矩阵对应的基准量子电路；
    通过受控反闸CNOT门，对所述基准量子电路进行转换，得到剩余对角酉矩阵对应的转换量子电路，其中，所述剩余对角酉矩阵是所述量子比特对角酉矩阵中除去所述基准对角酉矩阵之外的对角酉矩阵；
    将所述基准对角酉矩阵对应的基准量子电路、以及所述剩余对角酉矩阵对应的转换量子电路，确定为所述量子比特对角酉矩阵的所述匹配量子电路。
  4. 根据权利要求3所述的方法，其中，所述依据所述n个量子比特的编号信息，确定所述基准对角酉矩阵对应的基准量子电路，包括：
    针对所述基准对角酉矩阵生成多个量子比特序列；
    在每个所述量子比特序列的尾部分别增加第一元素，得到多个第一量子比特序列，并在每个所述量子比特序列的尾部分别增加第二元素，得到多个第二量子比特序列；
    依据所述n个量子比特的编号信息，确定所述基准对角酉矩阵对应的第一量子电路，其中，所述第一量子电路用于将多个所述第一量子比特序列对应的相位加载到标准基中；
    依据所述n个量子比特的编号信息，确定所述基准对角酉矩阵对应的第二量子电路，所述第二量子电路用于将多个所述第二量子比特序列对应的相位加载到所述标准基中；
    基于所述第一量子电路和所述第二量子电路，确定所述基准对角酉矩阵对应的所述基准量子电路。
  5. 根据权利要求4所述的方法，其中，所述依照所述n个量子比特的编号信息，确定所述基准对角酉矩阵对应的第一量子电路，包括：
    依据所述n个量子比特的编号信息，确定第j个所述第一量子比特序列的匹配CNOT门，j为依次递增的正整数，且1≤j≤2n-1-1；
    基于第j+1个所述第一量子比特序列，构造应用在第j个所述第一量子比特序列的匹配CNOT门之后的匹配R量子门；
    当j达到2n-1-1时，对2n-1-1个匹配CNOT门和匹配R量子门进行交替连接，得到候选子电路；
    确定补充R量子门和补充CNOT门，并对所述补充R量子门和所述补充CNOT门进行连接，得到补充子电路；
    基于所述候选子电路以及所述补充子电路，确定所述第一量子电路。
  6. 根据权利要求5所述的方法，其中，
    所述补充R量子门基于第1个量子比特序列确定得到，所述补充CNOT门的控制位是编号信息为1的量子比特，所述补充CNOT门的目标位是编号信息为n的量子比特；
    第j个所述第一量子比特序列的匹配CNOT门的控制位对应的编号信息由n与j计算得到，第j个所述第一量子比特序列的匹配CNOT门的目标位是编号信息为n的量子比特。
  7. 根据权利要求4所述的方法，其中，所述依据所述n个量子比特的编号信息，确定所述基准对角酉矩阵对应的第二量子电路，包括：
    确定所述基准对角酉矩阵对应的待实现对角酉矩阵，其中，所述待实现对角酉矩阵对应n-1个量子比特；
    通过变换电路，对所述待实现酉矩阵进行分解，得到置换对角酉矩阵，其中，所述变换电路用于将所述待实现酉矩阵对应的第一量子比特集合中的量子态，置换到第二量子比特集合中的量子态；
    依据所述n个量子比特的所述编号信息，确定所述置换对角酉矩阵对应的置换量子电路；
    将所述变换电路、所述置换量子电路以及所述变换电路对应的逆变换电路的连接结果，确定为所述第二量子电路，其中，所述逆变换电路用于将第二量子比特集合中的量子态，置换到所述第一量子比特集合中的量子态。
  8. 根据权利要求4所述的方法，其中，所述针对所述基准对角酉矩阵生成多个量子比特序列，包括：
    确定第j个量子比特序列的待翻转量子比特，并将所述待翻转量子比特上的元素进行翻转，得到第j+1个量子比特序列，其中，2≤j≤2n-1，第1个量子比特序列是通过n-1个第二元素排列得到；
    当迭代j的取值达到2n-1时，将2n-1个量子比特序列确定为所述基准对角酉矩阵的多个所述量子比特序列。
  9. 根据权利要求3所述的方法，其中，所述在所述连通图的限制下，确定所述n个量子比特分别对应的编号信息，包括：
    从所述连通图中抽取目标树，其中，所述目标树是所述连通图中的任意一个生成树，每个量子比特对应所述目标树中的一个节点；
    对所述目标树中的每个节点进行编号，得到所述每个节点所对应的节点编号；
    将所述每个节点所对应的节点编号，确定为每个节点所对应的量子比特的编号信息。
  10. 根据权利要求9所述的方法，其中，所述对所述目标树中的每个节点进行编号，得到所述每个节点所对应的节点编号，包括：
    针对所述目标树中的每个节点生成初始化编号；
    当所述节点编号为n-k+2的节点不存在子节点或者编号为初始化编号的子节点时，从已节点编号的节点中查询符合查询条件的目标节点，并将所述目标节点最左侧的子节点的节点编码确定为n-k+1；
    其中，所述查询条件为编号最大、且存在编号为初始化编号的子节点的节点；3≤k≤n，所述节点编码为n的节点是所述目标树的根节点，所述节点编码为n-1的节点是所述根节点最左侧的节点；
    当所述节点编码为n-k+2的节点存在子节点、且所述子节点的编号为初始化编号时，将所述编号为初始化编号的子节点中最左侧的子节点的节点编码，确定为n-k+1。
  11. 一种量子电路优化装置，所述装置包括：
    矩阵分解模块，配置为将待优化量子电路转换为待处理酉矩阵，并对所述待处理酉矩阵进行迭代分解，得到第一数量的量子比特均匀控制门；
    控制门分解模块，配置为将每个所述量子比特均匀控制门，分解为第二数量的量子比特对角酉矩阵和第三数量的单量子比特门；
    电路实现模块，配置为在连通图的限制下，确定与每个所述量子比特对角酉矩阵对应的匹配量子电路；
    连接整合模块，配置为对第二数量的所述匹配量子电路和第三数量的所述单量子比特门进行整合，得到每个所述量子比特均匀控制门的目标量子电路；对第一数量的所述目标量子电路进行连接，得到优化后的量子电路。
  12. 一种量子计算设备，所述量子计算设备包括优化量子电路，所述优化量子电路通过权利要求1至10任一项所述的量子电路优化方法实现。
  13. 一种电子设备，所述电子设备包括：
    存储器，用于存储可执行指令；
    处理器，用于执行所述存储器中存储的可执行指令时，实现权利要求1至10任一项所述的量子电路优化方法。
  14. 一种计算机可读存储介质，存储有可执行指令，所述可执行指令被处理器执行时实现权利要求1至10任一项所述的量子电路优化方法。
  15. 一种计算机程序产品，包括计算机程序或指令，所述计算机程序或指令被处理器执行时实现权利要求1至10任一项所述的量子电路优化方法。
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