WO2024021762A1 - 驱动电路、控制方法、电源模块及电子设备 - Google Patents

驱动电路、控制方法、电源模块及电子设备 Download PDF

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Publication number
WO2024021762A1
WO2024021762A1 PCT/CN2023/093221 CN2023093221W WO2024021762A1 WO 2024021762 A1 WO2024021762 A1 WO 2024021762A1 CN 2023093221 W CN2023093221 W CN 2023093221W WO 2024021762 A1 WO2024021762 A1 WO 2024021762A1
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Prior art keywords
control
transistor
electrode
voltage
circuit
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PCT/CN2023/093221
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English (en)
French (fr)
Inventor
刘顺攀
麦瑞坤
周玮
朱勇发
曾智强
张敬阳
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华为技术有限公司
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Publication of WO2024021762A1 publication Critical patent/WO2024021762A1/zh

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33571—Half-bridge at primary side of an isolation transformer
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer

Definitions

  • This application is applied in the field of power electronics technology, especially involving drive circuits, control methods, power modules and electronic equipment.
  • the method of increasing the switching frequency of the switching tube is usually used to reduce the size of magnetic components such as capacitors, inductors, and transformers in the DC (Direct Current, DC)-DC converter.
  • the switching frequency of the switching tube can be controlled by designing the specific structure of the drive circuit.
  • the drive circuit can adopt a structure such as a non-isolated inductor-type resonant driver or an isolated transformer-type resonant driver.
  • the current inductive resonant driver is not suitable for applications with multiple switching tubes such as multi-level converters or full-bridge converters. It occupies a lot of input/output (IO) interface resources and is not conducive to saving drive circuits. cost and volume.
  • the loss of the transformer winding of the current transformer-type resonant driver is relatively large.
  • This application provides a drive circuit, a control method, a power module and an electronic device, which are used to reduce the cost and volume of the drive circuit and reduce drive losses.
  • embodiments of the present application provide a driving circuit that can drive N main transistors.
  • N is 1, 2, 3, 4 or more, so that the driving circuit provided in the embodiment of the present application can drive one or more main transistors.
  • the drive circuit mainly includes: voltage control circuit, coupling circuit and N charge and discharge control circuits.
  • the coupling circuit includes a primary winding and N first secondary windings. The primary winding and each of the N first secondary windings are coupled to each other and are in a tightly coupled state.
  • the driving circuit provided by the embodiment of the present application can be a transformer-type resonant driver, which improves the simplicity of the driving circuit.
  • the voltage control circuit is connected to the primary winding, the N first secondary windings are connected to the N charge and discharge control circuits in a one-to-one correspondence, and the N charge and discharge control circuits are connected to the control electrodes of the N main transistors in a one-to-one correspondence.
  • the voltage control circuit is used to drive the primary winding to generate a periodic first voltage and a second voltage in response to a plurality of control pulse signals; wherein any one of the N first secondary windings is configured according to The first voltage coupling generates a first induced electromotive force, and the second voltage coupling generates a second induced electromotive force.
  • Any one of the N charge and discharge control circuits is used to control the control electrode of the corresponding connected main transistor to charge and discharge according to the first induced electromotive force and the second induced electromotive force generated by the coupling of the corresponding connected first secondary winding. , to control the corresponding connected main transistor to turn on and off.
  • the control pulse signal can achieve a short pulse (that is, the maintenance duration of the effective level Shorter) form, so that the control transistor in the control voltage control circuit can quickly turn on and off, thereby quickly driving the control electrode of the main transistor to charge and discharge, and after quickly driving the control electrode of the main transistor to charge and discharge, the primary side
  • the current-cutting effect of the winding and secondary winding minimizes the conduction loss on the primary winding and reduces the driving loss.
  • the voltage control circuit can be implemented by combining a control transistor and a capacitor, and each control transistor is correspondingly loaded with a control pulse signal.
  • the control transistors in the voltage control circuit respond to the loaded control pulse signal and work in combination with each other to generate periodic first voltages and second voltages according to the driving voltage of the driving voltage source.
  • the control pulse signal is a signal with an effective level appearing periodically, and an inactive level is between two adjacent effective levels. The effective level of the control pulse signal can control the control transistor in the voltage control circuit to turn on, and the invalid level can control the control transistor in the voltage control circuit to turn off.
  • one cycle of the control pulse signal is the sum of the maintenance time of an effective level and the maintenance time of an inactive level.
  • the duty cycle of the effective level of the control pulse signal in one cycle is: the ratio of the duration of the effective level to the duration of one cycle.
  • the duty cycle of the effective level of the control pulse signal in one cycle ranges from 4% to 30%.
  • the duty cycle of the control signal of the transformer-type resonant driver is usually between 45% and 60%, so that the transformer-type resonant driver usually uses long pulses (that is, the effective level is maintained for a long time).
  • the driving circuit provided by the embodiment of the present application can make the control pulse signal realize a short pulse (that is, the effective level) by setting the duty cycle range of the effective level of the control pulse signal in one cycle to 4% to 30%. (shorter maintenance time) form, so that the control transistor in the control voltage control circuit can quickly turn on and off, thereby quickly driving the control electrode of the main transistor to charge and discharge, and after quickly driving the control electrode of the main transistor to charge and discharge , achieve the current-cutting effect of the primary winding and the secondary winding, minimize the conduction loss on the primary winding, and reduce the driving loss.
  • a short pulse that is, the effective level
  • the control transistor in the control voltage control circuit can quickly turn on and off, thereby quickly driving the control electrode of the main transistor to charge and discharge, and after quickly driving the control electrode of the main transistor to charge and discharge , achieve the current-cutting effect of the primary winding and the secondary winding, minimize the conduction loss on the primary winding, and reduce the driving loss.
  • the duty cycle of the effective level of the control pulse signal in one cycle can be set according to the switching frequency of the main transistor Qs.
  • the switching frequency of the main transistor Qs is set to 1 MHz
  • the duty cycle of the effective level of the control pulse signal in one cycle ranges from 1/21 to 1/6.
  • the effective level of the control pulse signal appears once every 1000 ns
  • the maintenance time of the effective level is 50 ns to 200 ns.
  • the maintenance time of the effective level is one of 50ns, 80ns, 100ns, 130ns, 150ns, 180ns, and 200ns.
  • the maintenance time of the effective level can be determined according to the needs of the actual application, and is not limited here.
  • the switching frequency of the main transistor Qs can also be set to 2 MHz, and the duty cycle of the effective level of the control pulse signal in one cycle ranges from 1/11 to 2/7.
  • the effective level of the control pulse signal appears once every 500 ns, and the maintenance time of the effective level is 50 ns to 200 ns.
  • the maintenance time of the effective level is one of 50ns, 80ns, 100ns, 130ns, 150ns, 180ns, and 200ns.
  • the maintenance time of the effective level can be determined according to the needs of the actual application, and is not limited here.
  • the corresponding effective level has the same maintenance time as the corresponding effective level when the switching frequency is 2 MHz.
  • the maintenance time of the effective level corresponding to the switching frequency of the main transistor Qs when it is 1 MHz and the effective level corresponding to the switching frequency of 2 MHz can be one of 50ns, 80ns, 100ns, 130ns, 150ns, 180ns, and 200ns. This can unify the maintenance time of the effective level under different switching frequencies and reduce the difficulty of control.
  • the voltage control circuit can be implemented by combining a control transistor and a capacitor, and each control transistor is correspondingly loaded with a control pulse signal.
  • the voltage control circuit includes: a plurality of control transistors and a first capacitor, the first capacitor is connected in series with the primary winding and then connected in parallel with at least one control transistor among the plurality of control transistors, and the plurality of control transistors is connected in series with Between the positive and negative poles of the driving voltage source.
  • control pulse signal There are multiple numbers, and the multiple control transistors correspond to the multiple control pulse signals one-to-one.
  • the control electrode of each control transistor in the multiple control transistors is used to receive the corresponding control pulse signal.
  • the plurality of control transistors respond to corresponding control pulse signals and drive the primary winding to generate periodic first voltages and second voltages according to the driving voltage of the driving voltage source. In this way, by combining the control transistor and the capacitor, the primary winding can generate periodic first voltage and second voltage.
  • the voltage control circuit includes two control transistors and a first capacitor, and the two control transistors are a first control transistor and a second control transistor respectively. Then the required control pulse signals are also two, and the two control pulse signals are the first control pulse signal and the second control pulse signal respectively.
  • the control electrode of the first control transistor is used to receive the first control pulse signal
  • the first electrode of the first control transistor is connected to the positive electrode of the driving voltage source
  • the second electrode of the first control transistor is connected to the first electrode of the second control transistor.
  • the control electrode of the second control transistor is used to receive the second control pulse signal
  • the second electrode of the second control transistor is connected to the negative electrode of the driving voltage source.
  • the first electrode of the first capacitor is connected to the first stage of the first control transistor and the positive electrode of the driving voltage source respectively, and the second electrode of the first capacitor is connected to the first end of the primary winding, so that the first capacitor is connected to the primary winding.
  • the windings are connected in series.
  • the second end of the primary winding is connected to the second electrode of the first control transistor and the first stage of the second control transistor respectively.
  • the charge and discharge control circuit can also be implemented by combining an auxiliary transistor and a capacitor.
  • the charge and discharge control circuit includes a plurality of auxiliary transistors and a second capacitor.
  • the plurality of auxiliary transistors, the second capacitor, the first secondary winding and the control electrode of the main transistor are connected in series.
  • a microcontroller unit can be used to load a corresponding control signal to the control electrode of the auxiliary transistor, or an additional gate drive circuit can be used to load a corresponding control signal to the control electrode of the auxiliary transistor.
  • MCU microcontroller unit
  • an additional gate drive circuit can be used to load a corresponding control signal to the control electrode of the auxiliary transistor.
  • these will increase the complexity of the driving circuit and increase the problem of IO interface resource occupation.
  • the embodiment of the present application sets a self-driving circuit in the charge and discharge control circuit.
  • the self-driving circuit is connected to the first end and the second end of the first secondary winding respectively.
  • the control electrodes of the plurality of auxiliary transistors are coupled.
  • the self-driving circuit is used to control some of the auxiliary transistors to be turned on and the other auxiliary transistors to be turned off according to the first induced electromotive force and the second induced electromotive force generated by the coupling of the corresponding connected first secondary windings. Break.
  • the self-driving circuit is used to control some of the auxiliary transistors to be turned on and the other auxiliary transistors to be turned off according to the first induced electromotive force and the second induced electromotive force generated by the coupling of the corresponding connected first secondary windings. Break.
  • the voltage between the two electrode plates of the second capacitor is a second voltage
  • the second voltage in the second capacitor can be combined with the first induced electromotive force generated by the coupling of the first secondary winding and the second voltage. 2.
  • the induced electromotive force controls the rapid charging and discharging of the control electrode of the main transistor.
  • the charge and discharge control circuit includes two auxiliary transistors, a second capacitor and a self-driving circuit.
  • the two auxiliary transistors are respectively a first auxiliary transistor and a second auxiliary transistor.
  • the first auxiliary transistor, the second auxiliary transistor, the second capacitor, the first secondary winding and the control electrode of the main transistor are connected in series.
  • the first electrode of the second capacitor is connected to the first electrode of the main transistor
  • the second electrode of the second capacitor is connected to the first electrode of the first auxiliary transistor
  • the second electrode of the first auxiliary transistor is connected to the first secondary side.
  • the first end of the winding is connected to the first electrode of the second auxiliary transistor and the first secondary winding
  • the second terminal is connected, and the second electrode of the second auxiliary transistor is connected to the control electrode of the main transistor.
  • the self-driving circuit is coupled to the control electrodes of the first auxiliary transistor and the second auxiliary transistor.
  • the self-driving circuit includes: a first sub-driving circuit and a second sub-driving circuit. The first sub-driving circuit is connected to the control electrode of the first auxiliary transistor, and the second sub-driving circuit is connected to the control electrode of the second auxiliary transistor.
  • the first end of the first sub-driving circuit is connected to the control electrode of the first auxiliary transistor
  • the second end of the first sub-driving circuit is connected to the first end of the corresponding first secondary winding
  • the first end of the first sub-driving circuit is connected to the control electrode of the first auxiliary transistor.
  • the third terminal is connected to the corresponding second terminal of the first secondary winding.
  • the first end of the second sub-driving circuit is connected to the control electrode of the second auxiliary transistor
  • the second end of the second sub-driving circuit is connected to the second end of the corresponding first secondary winding
  • the third end of the second sub-driving circuit is connected to the control electrode of the second auxiliary transistor.
  • the terminal is connected to the first terminal of the corresponding first secondary winding.
  • the first sub-driving circuit is used to control the first auxiliary transistor to turn on and off according to the first induced electromotive force and the second induced electromotive force generated by the coupling of the connected first secondary winding.
  • the second sub-drive circuit is used to control the second auxiliary transistor to turn on and off according to the first induced electromotive force and the second induced electromotive force generated by the coupling of the connected first secondary winding.
  • the first sub-driving circuit includes: a first diode, a first resistor and a second resistor.
  • the first end of the first resistor is the first end of the first sub-driving circuit
  • the first end of the second resistor is the second end of the first sub-driving circuit
  • the anode of the first diode is the first end of the first sub-driving circuit.
  • the third terminal of the circuit and the cathode of the first diode are respectively connected to the second terminal of the first resistor and the second terminal of the second resistor.
  • the second sub-driving circuit includes: a second diode, a third resistor and a fourth resistor.
  • the first end of the third resistor is the first end of the second sub-driving circuit
  • the first end of the fourth resistor is the second end of the second sub-driving circuit
  • the anode of the second diode is the second end of the second sub-driving circuit.
  • the third terminal of the circuit and the cathode of the second diode are respectively connected to the second terminal of the third resistor and the second terminal of the fourth resistor.
  • the tube voltage drops of the first diode and the second diode are the same.
  • the first diode and the second diode are diodes with low tube voltage drop.
  • the tube voltage drop of the first diode and the second diode ranges from 0.2V to 0.4V.
  • the tube voltage drop of the first diode and the second diode is one of 0.2V, 0.3V, and 0.4V.
  • the tube voltage drops of the first diode and the second diode can be determined according to the actual application environment, and are not limited here.
  • the first to fourth resistors are resistors used to adjust the charging and discharging speeds of the first auxiliary transistor and the second auxiliary transistor.
  • the resistance values of the first to fourth resistors may be made the same.
  • the resistance values of the first resistor to the fourth resistor can be determined according to the actual application environment, and are not limited here.
  • the drive circuit provided by the embodiments of the present application can be set as a non-isolated drive circuit, which can reduce the number of components used in the drive circuit and improve the simplicity of the drive circuit.
  • the M main transistors are defined as the 1st main transistor to the Mth main transistor connected in series; wherein, the 1st main transistor is directly connected to the ground. terminal is connected, and the second electrode of the second capacitor corresponding to the first main transistor is also connected to the first terminal of the primary winding.
  • the first electrode of the main transistor is connected to the ground terminal, and the second electrode of the second capacitor of the main transistor is also connected to the first end of the primary winding.
  • This can provide the second voltage to the second capacitor through the primary winding, so that the second voltage can be used as the reference voltage of the charge and discharge control circuit, so that it can be combined with the first inductance generated by the coupling of the first secondary winding.
  • the control electrode of the main transistor is quickly charged and discharged.
  • the drive circuit provided by the embodiments of the present application can be set as a non-isolated drive circuit, which can reduce the number of components used in the drive circuit and improve the simplicity of the drive circuit.
  • the charge and discharge control circuit corresponding to the Mth main transistor further includes a first bootstrap diode; wherein, in the charge and discharge control circuit corresponding to the Mth main transistor, the cathode of the first bootstrap diode is connected to the second terminal of the second capacitor.
  • the electrodes are connected; and, the anode of the first bootstrap diode in the charge and discharge control circuit corresponding to the Mth main transistor is connected to the second electrode of the second capacitor in the charge and discharge control circuit corresponding to the m-1th main transistor; 2 ⁇ m ⁇ M, 2 ⁇ M ⁇ N, m and M are both integers.
  • the second electrode of the second capacitor corresponding to the first main transistor is also connected to the first end of the primary winding.
  • the charge and discharge control circuit connected to the second main transistor further includes a first bootstrap diode, the cathode of the first bootstrap diode is connected to the second electrode of the second capacitor corresponding to the second main transistor, and the first bootstrap diode The anode is connected to the second electrode of the second capacitor corresponding to the first main transistor.
  • a simple bootstrap circuit is formed by the first bootstrap diode and the second capacitor corresponding to the second main transistor, so that the reference voltage is supplied to the high-order main transistor, that is, the second main transistor through the bootstrap circuit.
  • the drive circuit 204 provided by the embodiment of the present application can also be configured as an isolation type drive circuit.
  • a second secondary winding may be provided in the coupling circuit, and a storage capacitor and a second bootstrap diode may be provided in the driving circuit.
  • the primary winding and the second secondary winding are coupled to each other and in a tightly coupled state, and the first end of the second secondary winding and the first end of the primary winding have the same end. This enables the second secondary winding to generate the first induced electromotive force according to the first voltage coupling and the second induced electromotive force according to the second voltage coupling.
  • the anode of the second bootstrap diode is connected to the first end of the second secondary winding, and the cathode of the second bootstrap diode is connected to the first electrode of the energy storage capacitor.
  • the second electrode of the energy storage capacitor is connected to the second terminal of the second secondary winding and the ground terminal respectively.
  • the second electrode of the second capacitor is also connected to the first electrode of the energy storage capacitor.
  • K main transistors are connected in series to the ground terminal, and the K main transistors are defined as the 1st main transistor to the Kth main transistor connected in series.
  • Transistor wherein, the first main transistor is directly connected to the ground terminal, and the second electrode of the second capacitor corresponding to the first main transistor is also connected to the first electrode of the energy storage capacitor.
  • the charge and discharge control circuit corresponding to the kth main transistor also includes a third bootstrap diode; wherein, in the charge and discharge control circuit corresponding to the kth main transistor, the cathode of the third bootstrap diode is connected to the second electrode of the second capacitor.
  • the anode of the third bootstrap diode in the charge and discharge control circuit corresponding to the k-th main transistor is connected to the second electrode of the second capacitor in the charge and discharge control circuit corresponding to the k-1th main transistor; 2 ⁇ k ⁇ K, 2 ⁇ K ⁇ N, k and K are both integers.
  • the second electrode of the second capacitor corresponding to the first main transistor is also connected to the first electrode of the energy storage capacitor.
  • the charge and discharge control circuit connected to the second main transistor further includes a third bootstrap diode, the cathode of the third bootstrap diode is connected to the second electrode of the second capacitor corresponding to the second main transistor, and the third bootstrap diode The anode is connected to the second electrode of the second capacitor corresponding to the first main transistor.
  • a simple bootstrap circuit is formed by the third bootstrap diode and the second capacitor corresponding to the second main transistor, so that the reference voltage is supplied to the high-order main transistor, that is, the second main transistor through the bootstrap circuit.
  • the driving circuit of these main transistors can be If the dynamic logic is the same, that is, these main transistors are controlled to be turned on and off at the same time, then the first end of the primary winding and the first end of the first secondary winding corresponding to these main transistors are the same ends.
  • the driving logic of the first part of the main transistors can be the same, the driving logic of the second part of the main transistors can be the same, and the driving logic of the first part of the main transistors is the same as that of the second part of the main transistors.
  • the driving logic of some main transistors is opposite, that is, the first part of the main transistor is controlled to be turned on and off at the same time, the second part of the main transistor is turned on and off at the same time, and the first part of the main transistor and the second part of the main transistor are turned on and off at the same time. Break.
  • first end of the primary winding and the first end of the first secondary winding corresponding to the first part of the main transistor are the same ends, and the first end of the primary winding and the first end of the first secondary winding corresponding to the second part of the main transistor are the same ends.
  • One end is the heteronymous end.
  • control transistor in the voltage control circuit and the auxiliary transistor in the charge and discharge control circuit are metal-oxide semiconductor field-effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET). Then its control electrode is the gate electrode.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • the first electrode can be a source electrode and the second electrode can be a drain electrode, or the first electrode can be a drain electrode and the second electrode can be source electrode.
  • embodiments of the present application further provide a power module, which may include a conversion circuit and a drive circuit as provided in any one of the above first aspects.
  • the driving circuit is used to drive the main transistor in the conversion circuit.
  • the power module can be either a DC-DC power module or an AC-DC power module.
  • the above power module can be used in different types of electronic devices, such as smart phones, smart TVs, laptops, handheld computers (personal digital assistant, PDA), wearable devices with wireless communication functions (such as smart watches, smart glasses, smart wristband), vehicle equipment or data center, etc.
  • PDA personal digital assistant
  • wearable devices with wireless communication functions such as smart watches, smart glasses, smart wristband
  • vehicle equipment or data center etc.
  • the technical effects of the corresponding solution in the second aspect can be referred to the technical effects that can be obtained by the corresponding solution in the first aspect, and the repeated points will not be described in detail.
  • embodiments of the present application further provide an electronic device, which may include a power module and a load module as provided in any one of the above second aspects.
  • the power module is electrically connected to the load module to provide DC voltage to the load module.
  • embodiments of the present application also provide a control method for a driving circuit, which can be used to control the driving circuit provided in any one of the first aspects.
  • the control method can be applied to the driving circuit in the power module provided in any one of the second aspects.
  • the technical effects of the corresponding solution in the fourth aspect can be referred to the technical effects that can be obtained by the corresponding solution in the first aspect or the second aspect, and repeated details will not be described in detail.
  • control method provided by the embodiments of the present application includes:
  • multiple control pulse signals are loaded on the voltage control circuit, and the first part of the control pulse signal among the multiple control pulse signals is at an inactive level, and the second part of the control pulse signal is at an effective level, and the voltage control circuit controls the flow through
  • the current of the primary winding increases forward to the maximum forward current value and drives the primary winding to generate a second voltage.
  • At least one first secondary winding among the N first secondary windings generates a second induction according to the second voltage coupling.
  • Electromotive force at least one charge and discharge control circuit among the N charge and discharge control circuits controls the control electrode of the corresponding connected main transistor to charge or discharge according to the second induced electromotive force generated by the coupling of the corresponding connected first secondary winding.
  • the driving circuit drives a main transistor and the voltage of the driving voltage source is +VCC
  • the first control pulse signal is loaded with an invalid level and the first control transistor is turned off.
  • the second control pulse signal is loaded with an effective level, and the second control transistor is turned on.
  • the current direction of the primary winding is from the first end to the second end to the negative pole of the driving voltage source (that is, the ground end), and linearly increases in the forward direction to the maximum forward current, and the voltage at both ends of the primary winding is + VCC/2, and the voltage causing the second induced electromotive force of the first secondary winding to be synchronously coupled to +VCC/2.
  • the second auxiliary transistor Since the first sub-drive circuit The interaction of the first diode, the first resistor and the second resistor controls the first auxiliary transistor to turn off. And due to the interaction of the second diode, the third resistor and the fourth resistor in the second sub-driving circuit, the second auxiliary transistor is controlled to be turned on, thereby causing the discharge path of the main transistor (the discharge path is: control of the main transistor Electrode ⁇ the second auxiliary transistor that is turned on ⁇ the first secondary winding ⁇ the body diode of the first auxiliary transistor ⁇ the second capacitor ⁇ the negative electrode of the driving voltage source (that is, the ground terminal)) is turned on, and the voltage on the control electrode of the main transistor Discharge so that the voltage on the control electrode of the main transistor drops to 0V.
  • the voltage control circuit is loaded with multiple control pulse signals, and the multiple control pulse signals are all at invalid levels.
  • the control voltage control circuit controls the current flowing through the primary winding to change from the maximum forward current to zero, and drives The primary winding generates a first voltage, at least one of the N first secondary windings generates a first induced electromotive force according to the first voltage coupling, and at least one of the N charge and discharge control circuits generates a first induced electromotive force according to The first induced electromotive force generated by the coupling of the corresponding connected first secondary winding controls the control electrode of the corresponding connected main transistor to charge or discharge.
  • the driving circuit drives a main transistor and the voltage of the driving voltage source is +VCC
  • the first control pulse signal is loaded with an invalid level and the first control transistor is turned off.
  • the second control pulse signal is loaded with an inactive level, and the second control transistor is turned off.
  • the body diode of the first control transistor is turned on, and the current direction of the primary winding current flows from the first end to the second end to the positive electrode of the driving voltage source, and the current of the primary winding can be regarded as a constant value.
  • the voltage across the primary winding becomes -VCC/2, and the voltage of the first induced electromotive force of the first secondary winding is synchronously coupled to -VCC/2.
  • the second auxiliary transistor Due to the interaction of the second diode, the third resistor and the fourth resistor in the second sub-driving circuit, the second auxiliary transistor is controlled to be turned off. And due to the interaction of the first diode, the first resistor and the second resistor in the first sub-driving circuit, the first auxiliary transistor is controlled to be turned on, so that the charging path of the main transistor (the charging path is: the second capacitor ⁇ The first auxiliary transistor that is turned on ⁇ the first secondary winding ⁇ the body diode of the second auxiliary transistor ⁇ the control electrode of the main transistor) is turned on, so that both -VCC/2 and the second capacitor coupled through the first secondary winding can be The voltage at the terminal +VCC/2 quickly charges the voltage on the control electrode of the main transistor to the point where the main transistor can be controlled to turn on.
  • the body diode of the first control transistor conducts freewheeling, and the current direction of the primary winding is from the first end to the second end to the anode of the driving voltage source, so as to charge the energy in the primary winding into the driving voltage. source and linearly decrease the current from the maximum forward current to 0. In this way, current interruption of the primary winding can be achieved.
  • the voltage across the primary winding is still -VCC/2, and the voltage of the first induced electromotive force of the first secondary winding is synchronously coupled to -VCC/2. Due to the interaction of the second diode, the third resistor and the fourth resistor in the second sub-driving circuit, the second auxiliary transistor is controlled to be turned off.
  • the first auxiliary transistor is controlled to be turned on, so that the charging path of the main transistor continues to be turned on, so that the control electrode of the main transistor By keeping the voltage at +VCC, the main transistor can be controlled to remain on.
  • a plurality of control pulse signals are loaded into the voltage control circuit, and the first part of the control pulse signal among the plurality of control pulse signals is at an effective level, and the second part of the control pulse signal is at an inactive level, and the voltage control circuit controls the flow through
  • the current of the primary winding increases in the reverse direction to the maximum reverse current value and drives the primary winding to generate a first voltage.
  • At least one first secondary winding among the N first secondary windings generates a first induction according to the first voltage coupling.
  • Electromotive force at least one charge and discharge control circuit among the N charge and discharge control circuits controls the control electrode of the corresponding connected main transistor to charge or discharge according to the first induced electromotive force generated by the coupling of the corresponding connected first secondary winding.
  • the driving circuit drives a main transistor and the voltage of the driving voltage source is +VCC
  • the first control pulse signal is loaded with an effective level and the first control transistor is turned on.
  • the second control pulse signal is loaded with an inactive level, and the second control transistor is turned off.
  • the current direction of the primary winding is from the positive pole of the driving voltage source to the second terminal to the first terminal, and linearly increases in the reverse direction to the maximum reverse current value, and the voltage at both ends of the primary winding is -VCC/2, and Make the first secondary winding
  • the voltage of the first induced electromotive force is synchronously coupled to -VCC/2.
  • the second auxiliary transistor Due to the interaction of the second diode, the third resistor and the fourth resistor in the second sub-driving circuit, the second auxiliary transistor is controlled to be turned off. And due to the interaction of the first diode, the first resistor and the second resistor in the first sub-driving circuit, the first auxiliary transistor is controlled to be turned on, so that the charging path of the main transistor continues to be turned on, which can make the main transistor
  • the control electrode is charged with a small amount of voltage so that the control electrode of the main transistor is slightly above +VCC. This is done to achieve charge balance. Moreover, in practical applications, these small amounts of voltage charged will not adversely affect the turn-on and turn-off of the main transistor.
  • the voltage control circuit is loaded with multiple control pulse signals, and the multiple control pulse signals are all at invalid levels.
  • the control voltage control circuit controls the current flowing through the primary winding to change from the maximum reverse current to zero, and drives The primary winding generates a second voltage, at least one of the N first secondary windings generates a second induced electromotive force according to the second voltage coupling, and at least one of the N charge and discharge control circuits generates a second induced electromotive force according to The second induced electromotive force generated by the coupling of the corresponding connected first secondary winding controls the control electrode of the corresponding connected main transistor to charge or discharge.
  • the driving circuit drives a main transistor and the voltage of the driving voltage source is +VCC
  • the first control pulse signal is loaded with an invalid level and the first control transistor is turned off.
  • the second control pulse signal is loaded with an inactive level, and the second control transistor is turned off.
  • the body diode of the second control transistor is turned on, and the current direction of the primary winding current is from the negative electrode of the driving voltage source to the second end to the first end, and the current of the primary winding can be regarded as a constant value.
  • the voltage across the primary winding becomes +VCC/2
  • the voltage of the second induced electromotive force of the first secondary winding is synchronously coupled to +VCC/2.
  • the first auxiliary transistor Due to the interaction of the first diode, the first resistor and the second resistor in the first sub-driving circuit, the first auxiliary transistor is controlled to be turned off. And due to the interaction of the second diode, the third resistor and the fourth resistor in the second sub-driving circuit, the second auxiliary transistor is controlled to be turned on, thereby causing the discharge path of the main transistor (the discharge path is: control of the main transistor Electrode ⁇ the second auxiliary transistor that is turned on ⁇ the first secondary winding ⁇ the body diode of the first auxiliary transistor ⁇ the second capacitor ⁇ the negative electrode of the driving voltage source (that is, the ground terminal)) is turned on, and the voltage on the control electrode of the main transistor Discharge, so that the voltage on the control electrode of the main transistor quickly drops to 0V, and the main transistor can be controlled to turn off.
  • the discharge path is: control of the main transistor Electrode ⁇ the second auxiliary transistor that is turned on ⁇ the first secondary winding ⁇ the body di
  • the body diode of the second control transistor conducts freewheeling, and the current direction of the primary winding is from the second end to the first end to the first capacitor, so that the energy in the primary winding is charged into the first capacitor, And the current rises linearly from the maximum reverse current to 0. In this way, current interruption of the primary winding can be achieved. And, the voltage across the primary winding becomes +VCC/2, and the voltage of the second induced electromotive force of the first secondary winding is synchronously coupled to +VCC/2. Due to the interaction of the first diode, the first resistor and the second resistor in the first sub-driving circuit, the first auxiliary transistor is controlled to be turned off.
  • the second auxiliary transistor is controlled to be turned on, so that the discharge path of the main transistor continues to be turned on, so that the control electrode of the main transistor The voltage on is kept at 0V.
  • Figure 1 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • Figure 2 is a schematic structural diagram of an inductive resonant driver in the related art
  • Figure 3 is a signal timing diagram of the inductive resonant driver shown in Figure 2;
  • Figure 4 is a schematic structural diagram of a transformer-type resonant driver in the related art
  • Figure 5 is a signal timing diagram of the transformer-type resonant driver shown in Figure 4.
  • Figure 6 is a schematic structural diagram of a driving circuit provided by an embodiment of the present application.
  • Figure 7 is a schematic structural diagram of a driving circuit provided by an embodiment of the present application.
  • Figure 8 is a schematic structural diagram of a driving circuit provided by another embodiment of the present application.
  • Figure 9 is a signal timing diagram corresponding to the drive circuit shown in Figure 8.
  • Figure 10 is a schematic structural diagram of a driving circuit provided by another embodiment of the present application.
  • Figure 11 is a signal timing diagram corresponding to the drive circuit shown in Figure 10;
  • Figure 12 is a schematic structural diagram of a driving circuit provided by another embodiment of the present application.
  • Figure 13 is a signal timing diagram corresponding to the drive circuit shown in Figure 12;
  • Figure 14 is a schematic structural diagram of a driving circuit provided by another embodiment of the present application.
  • Figure 15 is a schematic structural diagram of a driving circuit provided by another embodiment of the present application.
  • Figure 16 is a signal timing diagram corresponding to the drive circuit shown in Figure 15;
  • Figure 17 is a schematic structural diagram of a driving circuit provided by another embodiment of the present application.
  • Figure 18 is a signal timing diagram corresponding to the drive circuit shown in Figure 17;
  • Figure 19 is a schematic structural diagram of an LLC resonant converter provided by an embodiment of the present application.
  • Figure 20 is a schematic structural diagram of an LLC resonant converter provided by another embodiment of the present application.
  • Figure 21 is a schematic diagram of the waveform of the simulation provided by the embodiment of the present application.
  • connection in the embodiments of this application refers to electrical connection, and the connection between two electrical components may be a direct or indirect connection between two electrical components.
  • a and B can be connected directly, or A and B can be connected indirectly through one or more other electrical components.
  • a and B can be connected, or A and C can be connected directly.
  • C and B are directly connected, and A and B are connected through C.
  • coupling may refer to coupling between two windings through electromagnetic fields, that is, electric energy can be transmitted between two windings through electromagnetic fields, which mainly includes the energy conversion process of electric energy - magnetic field potential energy - electric energy.
  • FIG. 1 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • an electronic device 01 provided by an embodiment of the present application includes a power module 011 and a load module 012 .
  • the power module 011 and the load module 012 are electrically connected.
  • the electronic device 01 may be any electrical device.
  • the power module 011 may be a DC-DC power module, used to step up or step down the DC power and then output the DC power.
  • the power module 011 can convert the DC power (eg 48V) output by the power supply 02 into DC power for all types of load modules 012 and output it to the load module 012 for use by the load module 012 Work.
  • the power supply 02 can be any device or component that can output direct current.
  • the power supply 02 can be a battery, and the power supply module 011 can receive the battery voltage provided by the battery and convert the battery voltage to After being converted into the operating voltage of the load module 012, it is output to the load module 012.
  • the load module 012 can be any functional module that uses direct current.
  • the load module 012 can be a processor, a chip, etc.
  • the power module can also be an alternating current (AC)-DC power module, which is used to step up or step down the alternating current and then output direct current.
  • AC alternating current
  • the power module 011 includes a conversion circuit 0111 and a driving circuit 0112 .
  • the drive circuit 0112 is used to drive the switching tube in the conversion circuit 0111 to work at a certain switching frequency, so that the conversion circuit 0111 boosts or steps down the voltage of the power supply 02, and then outputs it to the load module 012 Provides DC power at operating voltage.
  • the conversion circuit 0111 can be a DC-DC converter, such as a Buck converter, a Boost converter, a half-bridge converter, Full-bridge converters and inductor-inductor-capacitor (inductor-inductor-capacitor, LLC) resonant converters, etc.
  • the switch tube in the conversion circuit 0111 can be a MOSFET, and the drive circuit 0112 is connected to the control electrode of the MOSFET, so that the conversion circuit 0111 can realize voltage conversion by controlling the on and off of the MOSFET.
  • the method of increasing the switching frequency of the switching tube is usually used to reduce the size of magnetic components such as capacitors, inductors, and transformers in the DC-DC converter.
  • the switching frequency of the switching tube can be controlled by designing the specific structure of the drive circuit.
  • the drive circuit can adopt a structure such as a non-isolated inductor-type resonant driver or an isolated transformer-type resonant driver.
  • FIG. 2 is a schematic structural diagram of an inductive resonant driver in the related art.
  • the inductive resonant driver 0101 includes: four auxiliary control transistors S011 ⁇ S014, an inductor Lr011 and an energy storage capacitor Cs011.
  • VD is the driving voltage source, which provides the driving voltage for the control electrode of the switching tube Q011.
  • the control electrodes of the four auxiliary control transistors S011 to S014 are loaded with corresponding control signals to realize the charging and discharging processes of the control electrode of the switching tube Q011.
  • the inductor type resonant driver 0101 realizes the current cut-off of the inductor Lr011 and reduces the effective value of the current in the inductor type resonant driver 0101, which will add Drive losses are reduced to low levels. It should be noted that the specific connection relationship of each device in the inductive resonant driver 0101 can be referred to Figure 2 and will not be described again here.
  • FIG. 3 is a signal timing diagram of the inductive resonant driver shown in Figure 2.
  • S S011 represents the control signal loaded on the control electrode of the auxiliary control transistor S011
  • S S012 represents the control signal loaded on the control electrode of the auxiliary control transistor S012
  • S S013 represents the control signal loaded on the control electrode of the auxiliary control transistor S013
  • S S014 represents the control signal loaded on the control electrode of the auxiliary control transistor S014
  • I Lr011 represents the current flowing through the inductor Lr011
  • I GQ011 represents the control electrode current of the switching tube Q011
  • V GQ011 represents the control electrode voltage of the switching tube Q011.
  • the specific working process can be basically the same as that in the related art, and will not be described again here.
  • control signals S S011 and S S012 are logically complementary and leave a certain dead time.
  • the dead time is the charging time of the control electrode of the switch Q011.
  • the current I Lr011 of the inductor Lr011 is an intermittent current, which can minimize the conduction loss on the inductor Lr011.
  • the inductive resonant driver 0101 can minimize the conduction loss on the inductor Lr011, it also has the following significant shortcomings:
  • control signals and driving voltage sources required for driving a single switch tube are non-isolated connections, and cannot be directly applied to situations that require isolation of driving signals and power supply.
  • transformer-type resonant drivers For control electrode driving situations that require isolation, transformer-type resonant drivers have outstanding advantages in system simplicity.
  • FIG. 4 is a schematic structural diagram of a transformer-type resonant driver in the related art.
  • the Buck converter 0102 also includes a capacitor C0 and an inductor Lf0.
  • Q021 is the control switch tube in Buck converter 0102
  • Q022 is the synchronous switch tube in Buck converter 0102.
  • Transformer type resonant driver 0103 includes: auxiliary control transistors S021 ⁇ S024, transformer primary winding Lr021, transformer secondary winding Lr022, DC blocking capacitors Cb021 ⁇ Cb022, bootstrap capacitor Cf021, and bootstrap diode Df021.
  • the transformer primary winding Lr021 and the transformer secondary winding Lr022 are tightly coupled.
  • VD2 and VD3 are driving voltage sources. It should be noted that the specific connection relationship of each device in the Buck converter 0102 and the specific connection relationship of each device in the transformer-type resonant driver 0103 can be referred to Figure 4 and will not be described again here.
  • FIG. 5 is a signal timing diagram of the transformer-type resonant driver shown in FIG. 4 .
  • S S021 represents the control signal loaded on the control electrode of the auxiliary control transistor S021
  • S S022 represents the control signal loaded on the control electrode of the auxiliary control transistor S022
  • S S023 represents the control signal loaded on the control electrode of the auxiliary control transistor S023
  • S S024 represents the control signal loaded on the control electrode of the auxiliary control transistor S024
  • I Lr021 represents the current flowing through the primary winding Lr021 of the transformer
  • I Lr022 represents the current flowing through the secondary winding Lr022 of the transformer
  • I GQ021 represents the control electrode of the control switch Q021 Current
  • I GQ022 represents the control electrode current of synchronous switch tube Q022
  • V GQ021 represents the control electrode voltage of control switch tube Q021
  • V GQ022 represents the control electrode voltage of synchronous switch tube Q022.
  • control signals S S021 and S S022 are logically complementary and leave a certain dead time.
  • the control signals S S023 and S S024 are logically complementary and leave a certain dead time.
  • the bootstrap capacitor Cf021 and the bootstrap diode Df021 form a bootstrap circuit, which, combined with the drive voltage source VD2, provides the drive voltage for the high-level control switch Q021.
  • the above-mentioned transformer-type resonant driver 0103 reduces the number and control difficulty of auxiliary control transistors when driving two switching tubes.
  • it also has the following significant shortcomings:
  • the transformer has large inductance:
  • the transformer formed by the primary winding of the transformer and the secondary winding of the transformer has an inductance of 1.2uH under 1MHz, which limits the further reduction of the transformer volume.
  • embodiments of the present application provide a driving circuit.
  • the driving circuit is a transformer-type resonant driver, and the current of the primary winding in the driving circuit is an intermittent current, which can minimize the conduction loss on the primary winding. , reduce driving loss.
  • the function of the transformer-type resonant driver can be realized, so that the driving circuit provided by the embodiment of the present application can not only have the advantages of the intermittent current of the inductive type resonant driver, but also can A simple model with a transformer-type resonant driver.
  • the driving circuit provided by the embodiment of the present application can also recycle the excess energy stored in the primary winding into the driving voltage source, thereby achieving lossless driving.
  • the main transistor driven by the driving circuit provided by the present application is the switching transistor in the above-mentioned conversion circuit.
  • the main transistor driven by the driving circuit provided in this application is a buck converter, a boost converter, a half-bridge converter, a full-bridge converter or an inductor-inductor-capacitor (inductor). -Inductor-capacitor, LLC) switching transistor in at least one converter of the resonant converter.
  • a driving circuit can drive a conversion circuit.
  • one driving circuit can drive two, three or more conversion circuits. In actual applications, the driving correspondence relationship between the driving circuit and the conversion circuit can be determined according to the needs of the actual application, and is not limited here.
  • FIG. 6 is a schematic structural diagram of a driving circuit provided by an embodiment of the present application. Moreover, FIG. 6 takes driving a main transistor Qs as an example for illustration. Referring to Figure 6, the control electrode of the main transistor Qs is connected to the drive circuit 201, the first electrode of the main transistor Qs is connected to the ground terminal, and the second electrode of the main transistor Qs can be connected to other devices in the conversion circuit (not shown in Figure 6 The specific connection method of the second electrode of the main transistor Qs is shown).
  • the driving circuit 201 includes: a voltage control circuit 2011, a coupling circuit 2012 and a charge and discharge control circuit 2013; wherein the coupling circuit 2012 includes a primary winding LP and a first secondary winding LS1, the primary winding LP and a first secondary winding LS1.
  • the secondary windings LS1 are coupled to each other and are in a tightly coupled state.
  • the first end of the primary winding LP and the first end of the first secondary winding LS1 have the same name.
  • the voltage control circuit 2011 is connected to the primary winding LP
  • the first secondary winding LS1 is connected to the charge and discharge control circuit 2013, and the charge and discharge control circuit 2013 is connected to the control electrode of the main transistor Qs.
  • the voltage control circuit 2011 is used to drive the primary winding LP to generate a periodic first voltage and a second voltage in response to a plurality of control pulse signals, and the first secondary winding LS1 generates a first induction according to the first voltage coupling. Electromotive force, according to the second voltage coupling, a second induced electromotive force is generated. Furthermore, the charge and discharge control circuit 2013 is used to control the control electrode of the main transistor Qs to charge and discharge according to the first induced electromotive force and the second induced electromotive force coupled to the first secondary winding LS1, so as to control the main transistor Qs to turn on and off. .
  • the voltage control circuit 2011 can be implemented by combining a control transistor and a capacitor, and one control transistor is correspondingly loaded with a control pulse signal.
  • the control transistors in the voltage control circuit 2011 respond to the loaded control pulse signal and work in conjunction with each other to generate periodic first voltages and second voltages according to the driving voltage of the driving voltage source.
  • the control pulse signal is a signal with an effective level appearing periodically, and an inactive level is between two adjacent effective levels. The effective level of the control pulse signal can control the control transistor in the voltage control circuit 2011 to be turned on, and the inactive level can control the control transistor in the voltage control circuit 2011 to be turned off.
  • one cycle of the control pulse signal is the sum of the maintenance time of an effective level and the maintenance time of an inactive level.
  • the duty cycle of the effective level of the control pulse signal in one cycle is: the ratio of the duration of the effective level to the duration of one cycle. In the embodiment of the present application, the duty cycle of the effective level of the control pulse signal in one cycle ranges from 4% to 30%.
  • the duty cycle of the control signals S S021 ⁇ S S022 in the related art is usually 45% ⁇ 60%
  • the transformer-type resonant driver 0103 is usually driven by long pulses (that is, the effective level is maintained for a long time), resulting in the current of the primary winding and secondary winding of the transformer in the transformer-type resonant driver 0103 being long.
  • the driving circuit provided by the embodiment of the present application can make the control pulse signal realize a short pulse (that is, the effective level) by setting the duty cycle range of the effective level of the control pulse signal in one cycle to 4% to 30%.
  • control transistor in the control voltage control circuit 2011 can be quickly turned on and off, thereby realizing fast charging and discharging of the control electrode of the main transistor, and fast driving of the control electrode of the main transistor for charging and discharging.
  • the current-cutting effect of the primary winding and the secondary winding is achieved, minimizing the conduction loss on the primary winding and reducing the driving loss.
  • the duty cycle of the effective level of the control pulse signal in one cycle can be set according to the switching frequency of the main transistor Qs.
  • the switching frequency of the main transistor Qs is set to 1 MHz
  • the duty cycle of the effective level of the control pulse signal in one cycle ranges from 1/21 to 1/6.
  • the effective level of the control pulse signal appears once every 1000 ns
  • the maintenance time of the effective level is 50 ns to 200 ns.
  • the maintenance time of the effective level is one of 50ns, 80ns, 100ns, 130ns, 150ns, 180ns, and 200ns.
  • the maintenance time of the effective level can be determined according to the needs of the actual application, and is not limited here.
  • the switching frequency of the main transistor Qs can also be set to 2 MHz, and the duty cycle of the effective level of the control pulse signal in one cycle ranges from 1/11 to 2/7.
  • the effective level of the control pulse signal appears once every 500 ns, and the maintenance time of the effective level is 50 ns to 200 ns.
  • the maintenance time of the effective level is one of 50ns, 80ns, 100ns, 130ns, 150ns, 180ns, and 200ns.
  • the maintenance time of the effective level can be determined according to the needs of the actual application, and is not limited here.
  • the corresponding effective level has the same maintenance time as the corresponding effective level when the switching frequency is 2 MHz.
  • the maintenance time of the effective level corresponding to the switching frequency of the main transistor Qs when it is 1 MHz and the effective level corresponding to the switching frequency of 2 MHz can be one of 50ns, 80ns, 100ns, 130ns, 150ns, 180ns, and 200ns. This can unify the maintenance time of the effective level under different switching frequencies and reduce the difficulty of control.
  • FIG. 7 is a schematic structural diagram of a driving circuit provided by an embodiment of the present application.
  • the voltage control circuit 2011 includes two control transistors and a first capacitor Cr.
  • the two control transistors are a first control transistor P1 and a second control transistor P2 respectively.
  • the required control pulse signals are also two, and the two control pulse signals are the first control pulse signal PP1 and the second control pulse signal PP2 respectively.
  • control electrode of the first control transistor P1 is used to receive the first control pulse signal P P1
  • first electrode of the first control transistor P1 is connected to the positive electrode of the driving voltage source VDC
  • second electrode of the first control transistor P1 is connected to the positive electrode of the driving voltage source VDC.
  • the first electrode of the two control transistors P2 is connected
  • the control electrode of the second control transistor P2 is used to receive the second control pulse signal P P2
  • the second electrode of the second control transistor P2 is connected to the negative electrode of the driving voltage source VDC.
  • the first electrode of the first capacitor Cr is connected to the positive electrode of the driving voltage source VDC, and the second electrode of the first capacitor Cr is connected to the first end of the primary winding LP, so that the first capacitor Cr and the primary winding LP are connected in series.
  • the second end of the primary winding LP is connected to the second electrode of the first control transistor P1. This can simplify the structure of the voltage control circuit as much as possible.
  • FIG. 7 only illustrates the voltage control circuit 2011 including two control transistors and a first capacitor Cr as an example.
  • the number of control transistors and the number of first capacitors Cr in the voltage control circuit 2011 can be determined according to the needs of the actual application, and are not limited here.
  • the charge and discharge control circuit can also be implemented by combining an auxiliary transistor and a capacitor.
  • the charge and discharge control circuit includes a plurality of auxiliary transistors and a second capacitor.
  • the plurality of auxiliary transistors, the second capacitor, the first secondary winding and the control electrode of the main transistor are connected in series.
  • assistance is also needed
  • the control electrodes of the transistors are loaded with corresponding control signals to control these auxiliary transistors to work in coordination with each other, thereby controlling the control electrodes of the main transistors to charge and discharge.
  • an MCU may be used to load a corresponding control signal to the control electrode of the auxiliary transistor, or an additional gate drive circuit may be used to load a corresponding control signal to the control electrode of the auxiliary transistor.
  • these will increase the complexity of the driving circuit and increase the occupation of IO interface resources.
  • the embodiment of the present application sets a self-driving circuit AC in the charge and discharge control circuit.
  • the self-driving circuit AC is connected to the first terminal of the first secondary winding LS1.
  • the terminal is coupled to the second terminal and the control electrodes of the auxiliary transistors S1 ⁇ S2.
  • the self-driving circuit is used to control some of the auxiliary transistors to be turned on and the other auxiliary transistors to be turned off according to the first induced electromotive force and the second induced electromotive force generated by the coupling of the corresponding connected first secondary windings. Break.
  • the self-driving circuit is used to control some of the auxiliary transistors to be turned on and the other auxiliary transistors to be turned off according to the first induced electromotive force and the second induced electromotive force generated by the coupling of the corresponding connected first secondary windings. Break.
  • the voltage between the two electrode plates of the second capacitor is the second voltage.
  • the second voltage in the second capacitor can be combined with the first induced electromotive force generated by the coupling of the first secondary winding LS1 and the second voltage.
  • the second induced electromotive force controls the rapid charge and discharge of the control electrode of the main transistor Qs.
  • FIG. 8 is a schematic structural diagram of a driving circuit provided by another embodiment of the present application.
  • the charge and discharge control circuit 2013 includes two auxiliary transistors S1 ⁇ S2, a second capacitor Ct, and a self-driving circuit AC.
  • the two auxiliary transistors are respectively a first auxiliary transistor S1 and a second auxiliary transistor S2.
  • the first auxiliary transistor S1, the second auxiliary transistor S2, the second capacitor Ct, the first secondary winding LS1 and the control electrode of the main transistor Qs are connected in series.
  • the first electrode of the second capacitor Ct is connected to the first electrode of the main transistor Qs
  • the second electrode of the second capacitor Ct is connected to the first electrode of the first auxiliary transistor S1
  • the second electrode of the first auxiliary transistor S1 The first terminal of the first secondary winding LS1 is connected
  • the first electrode of the second auxiliary transistor S2 is connected to the second terminal of the first secondary winding LS1
  • the second electrode of the second auxiliary transistor S2 is connected to the control of the main transistor Qs. Electrode connections.
  • the self-driving circuit is coupled to the control electrodes of the first auxiliary transistor S1 and the second auxiliary transistor S2.
  • the self-driving circuit AC includes: a first sub-driving circuit AC1 and a second sub-driving circuit AC2.
  • the first sub-driving circuit AC1 is connected to the control electrode of the first auxiliary transistor S1
  • the second sub-driving circuit AC2 is connected to the control electrode of the second auxiliary transistor S2.
  • the first end of the first sub-driving circuit AC1 is connected to the control electrode of the first auxiliary transistor S1
  • the second end of the first sub-driving circuit AC1 is connected to the first end of the first secondary winding LS1
  • the first sub-driving circuit AC1 is connected to the control electrode of the first auxiliary transistor S1.
  • the third terminal of the circuit AC1 is connected to the second terminal of the first secondary winding LS1.
  • the first terminal of the second sub-driving circuit AC2 is connected to the control electrode of the second auxiliary transistor S2.
  • the second terminal of the second sub-driving circuit AC2 is connected to the second terminal of the first secondary winding LS1.
  • the second sub-driving circuit AC2 The third end of is connected to the first end of the first secondary winding LS1.
  • the first sub-driving circuit AC1 is used to control the first auxiliary transistor S1 to turn on and off according to the first induced electromotive force and the second induced electromotive force generated by the coupling of the connected first secondary winding LS1.
  • the second sub-drive circuit AC2 is used to control the second auxiliary transistor S2 to turn on and off according to the first induced electromotive force and the second induced electromotive force generated by the coupling of the connected first secondary winding LS1.
  • the first sub-driving circuit AC1 includes: a first diode D1, a first resistor R1, and a second resistor R2.
  • the first terminal of the first resistor R1 is the first terminal of the first sub-driving circuit AC1, and the second terminal of the first resistor R1 is connected to the cathode of the first diode D1.
  • the first terminal of the second resistor R2 is the second terminal of the first sub-driving circuit AC1, and the second terminal of the second resistor R2 is connected to the cathode of the first diode D1.
  • the anode of the first diode D1 is the third terminal of the first sub-driving circuit AC1. In this way, only the first diode, the first resistor and the second resistor can be used to realize the function of the first sub-driving circuit, reducing the complexity of the first sub-driving circuit and reducing the complexity of the driving circuit.
  • the second sub-driving circuit AC2 includes: a second diode D2, a third resistor R3, and a fourth resistor R4.
  • the first terminal of the third resistor R3 is the first terminal of the second sub-driving circuit AC2, and the second terminal of the third resistor R3 is connected to the cathode of the second diode D2.
  • the first terminal of the fourth resistor R4 is the second terminal of the second sub-driving circuit AC2, and the second terminal of the fourth resistor R4 is connected to the cathode of the second diode D2.
  • the anode of the second diode D2 is the third terminal of the second sub-driving circuit AC2. In this way, only the second diode, the third resistor and the fourth resistor can be used to realize the function of the second sub-driving circuit, reducing the complexity of the second sub-driving circuit and reducing the complexity of the driving circuit.
  • the tube voltage drops of the first diode D1 and the second diode D2 are the same.
  • the first diode D1 and the second diode D2 are diodes with low voltage drop.
  • the tube voltage drop of the first diode D1 and the second diode D2 ranges from 0.2V to 0.4V.
  • the tube voltage drop of the first diode D1 and the second diode D2 is one of 0.2V, 0.3V, and 0.4V.
  • the tube voltage drops of the first diode D1 and the second diode D2 can be determined according to the actual application environment, and are not limited here.
  • the first to fourth resistors R1 to R4 are resistors used to adjust the charging and discharging speeds of the first auxiliary transistor S1 and the second auxiliary transistor S2.
  • the resistance values of the first to fourth resistors R1 to R4 may be made the same.
  • the resistance values of the first to fourth resistors R1 to R4 can be determined according to the actual application environment, and are not limited here.
  • the driving circuit provided by embodiments of the present application can be configured as a non-isolated driving circuit, which can reduce the number of components used in the driving circuit and improve the simplicity of the driving circuit.
  • the first electrode of the main transistor Qs is connected to the ground terminal, and the second electrode of the second capacitor Ct is also connected to the first end of the primary winding LP.
  • This can provide the second voltage to the second capacitor Ct through the primary winding LP, so that the second voltage can be used as the reference voltage of the charge and discharge control circuit, so that the first induced electromotive force and the second induction generated by the coupling of the first secondary winding LS1 can be combined.
  • the electromotive force achieves the effect of rapid charging and discharging of the control electrode of the main transistor Qs.
  • control transistor in the voltage control circuit and the auxiliary transistor in the charge and discharge control circuit are MOSFETs, and their control electrodes are gate electrodes.
  • the first electrode can be a source electrode and the second electrode can be a drain electrode, or the first electrode can be a drain electrode and the second electrode can be source electrode.
  • FIG. 9 is a signal timing diagram corresponding to the driving circuit shown in FIG. 8 .
  • P P1 represents the first control pulse signal loaded on the control electrode of the first control transistor P1
  • P P2 represents the second control pulse signal loaded on the control electrode of the second control transistor P2
  • U LP represents the primary winding.
  • the voltage across LP I LP represents the current of the primary winding LP
  • U LS1 represents the voltage corresponding to the induced electromotive force at both ends of the first secondary winding LS1
  • U GS1 represents the voltage of the control electrode of the first auxiliary transistor S1
  • U GS2 represents the voltage of the control electrode of the first auxiliary transistor S1.
  • the voltage of the control electrode of the second auxiliary transistor S2, I GQs represents the current of the control electrode of the main transistor Qs, and U GQs represents the voltage of the control electrode of the main transistor Qs.
  • the high-level pulse is the effective level of the control pulse signal, and the driving voltage of the driving voltage source is +VCC as an example.
  • the sustaining duration of the high-level pulses of the first control pulse signal P P1 and the second control pulse signal P P2 is the same, and the high-level pulses of the first control pulse signal P P1 and the second control pulse signal P P2
  • a dead time between pulses that is, the time period when the first control pulse signal P P1 and the second control pulse signal P P2 appear low-level pulses at the same time as their dead time. zone time.
  • the following takes the structure of the driving circuit shown in FIG. 8 as an example and combines the signal timing diagram shown in FIG. 9 to describe the working process of the driving circuit provided by the embodiment of the present application.
  • the first voltage is -VCC/2 and the second voltage is +VCC/2 as an example.
  • the first control pulse signal P P1 is loaded with an inactive level (for example, low level), and the first control transistor P1 is turned off.
  • the second control pulse signal P P2 is loaded with an effective level (for example, a high level), and the second control transistor P2 is turned on.
  • the current direction of the current I LP of the primary winding LP is from the first end to the second end to the negative electrode of the driving voltage source (i.e., the ground end), and linearly increases in the forward direction to the maximum forward current value, and the two sides of the primary winding LP
  • the voltage at the terminal is +VCC/2, and the voltage of the second induced electromotive force of the first secondary winding LS1 is synchronously coupled to +VCC/2.
  • the first auxiliary transistor S1 Due to the interaction of the first diode D1, the first resistor R1 and the second resistor R2 in the first sub-driving circuit AC1, the first auxiliary transistor S1 is controlled to be turned off. And due to the interaction of the second diode D2, the third resistor R3 and the fourth resistor R4 in the second sub-driving circuit AC2, the second auxiliary transistor S2 is controlled to be turned on, thereby causing the discharge path of the main transistor Qs (the discharge path It is: the control electrode of the main transistor Qs ⁇ the second auxiliary transistor S2 that is turned on ⁇ the first secondary winding LS1 ⁇ the body diode of the first auxiliary transistor S1 ⁇ the second capacitor Ct ⁇ the negative electrode (i.e., the ground terminal) of the driving voltage source VDC ) is turned on, and the voltage on the control electrode of the main transistor Qs is discharged, so that the voltage on the control electrode of the main transistor Qs drops to 0V.
  • the first control pulse signal P P1 is loaded with an inactive level (for example, low level), and the first control transistor P1 is turned off.
  • the second control pulse signal P P2 is loaded with an inactive level (for example, a low level), and the second control transistor P2 is turned off. Then the body diode of the first control transistor P1 is turned on, the current I LP of the primary winding LP flows from the first end to the second end to the positive electrode of the driving voltage source, and the current I LP of the primary winding LP Can be regarded as a fixed value.
  • the voltage across the primary winding LP becomes -VCC/2
  • the voltage of the first induced electromotive force of the first secondary winding LS1 is synchronously coupled to -VCC/2. Due to the interaction of the second diode D2, the third resistor R3 and the fourth resistor R4 in the second sub-driving circuit AC2, the second auxiliary transistor S2 is controlled to be turned off.
  • the first auxiliary transistor S1 is controlled to be turned on, thereby making the charging path of the main transistor Qs (the charging path It is: the second capacitor Ct ⁇ the first auxiliary transistor S1 that is turned on ⁇ the first secondary winding LS1 ⁇ the body diode of the second auxiliary transistor S2 ⁇ the control electrode of the main transistor Qs) is turned on, so that the first secondary winding can be turned on
  • the -VCC/2 coupled by LS1 and the voltage +VCC/2 across the second capacitor quickly charge the voltage on the control electrode of the main transistor Qs to +VCC, thereby controlling the main transistor Qs to turn on.
  • the first control pulse signal P P1 is loaded with an inactive level (for example, low level), and the first control transistor P1 is turned off.
  • the second control pulse signal P P2 is loaded with an inactive level (for example, a low level), and the second control transistor P2 is turned off.
  • the body diode of the first control transistor P1 conducts freewheeling, and the current direction of the current I LP of the primary winding LP is from the first end to the second end to the anode of the driving voltage source, so as to transfer the energy in the primary winding LP.
  • the voltage across the primary winding LP is still -VCC/2
  • the voltage of the first induced electromotive force of the first secondary winding LS1 is synchronously coupled to -VCC/2. Due to the interaction of the second diode D2, the third resistor R3 and the fourth resistor R4 in the second sub-driving circuit AC2, the second auxiliary transistor S2 is controlled to be turned off.
  • the first auxiliary transistor S1 is controlled to be turned on, so that the charging path of the main transistor Qs continues to be turned on, By keeping the voltage on the control electrode of the main transistor Qs at +VCC, the main transistor Qs can be controlled to remain on.
  • the first control pulse signal P P1 is loaded with an effective level (for example, high level), and the first control transistor P1 is turned on.
  • the second control pulse signal P P2 is loaded with an inactive level (for example, a low level), and the second control transistor P2 is turned off.
  • the current direction of the current I LP of the primary winding LP is from the positive pole of the driving voltage source to the second terminal to the first terminal, and linearly increases in the reverse direction to the maximum reverse current value, and the voltage at both ends of the primary winding LP is -VCC /2, and the voltage of the first induced electromotive force of the first secondary winding LS1 is synchronously coupled to -VCC/2.
  • the second auxiliary transistor S2 is controlled to be turned off. And due to the interaction of the first diode D1, the first resistor R1 and the second resistor R2 in the first sub-driving circuit AC1, the first auxiliary transistor S1 is controlled to be turned on, so that the charging path of the main transistor Qs continues to be turned on, This allows the control electrode of the main transistor Qs to be charged with a small amount of voltage, so that the voltage of the control electrode of the main transistor Qs is slightly higher than +VCC. This is done to achieve charge balance. Moreover, in practical applications, these small amounts of voltage charged will not adversely affect the turn-on and turn-off of the main transistor Qs.
  • the first control pulse signal P P1 is loaded with an inactive level (for example, low level), and the first control transistor P1 is turned off.
  • the second control pulse signal P P2 is loaded with an inactive level (for example, a low level), and the second control transistor P2 is turned off. Then the body diode of the second control transistor P2 is turned on, the current direction of the current I LP of the primary winding LP is from the negative electrode of the driving voltage source to the second end to the first end, and the current I LP of the primary winding LP is Can be regarded as a fixed value.
  • the voltage across the primary winding LP becomes +VCC/2
  • the voltage of the second induced electromotive force of the first secondary winding LS1 is synchronously coupled to +VCC/2. Due to the interaction of the first diode D1, the first resistor R1 and the second resistor R2 in the first sub-driving circuit AC1, the first auxiliary transistor S1 is controlled to be turned off.
  • the second auxiliary transistor S2 is controlled to be turned on, thereby causing the discharge path of the main transistor Qs (the discharge path It is: the control electrode of the main transistor Qs ⁇ the second auxiliary transistor S2 that is turned on ⁇ the first secondary winding LS1 ⁇ the body diode of the first auxiliary transistor S1 ⁇ the second capacitor Ct ⁇ the negative electrode of the driving voltage source (ie, the ground terminal))
  • the voltage on the control electrode of the main transistor Qs is discharged, so that the voltage on the control electrode of the main transistor Qs quickly drops to 0V, and the main transistor Qs can be controlled to turn off.
  • the first control pulse signal P P1 is loaded with an inactive level (for example, low level), and the first control transistor P1 is turned off.
  • the second control pulse signal P P2 is loaded with an inactive level (for example, a low level), and the second control transistor P2 is turned off.
  • the body diode of the second control transistor P2 conducts freewheeling, and the current I LP of the primary winding LP flows from the second end to the first end to the first capacitor Cr to charge the energy in the primary winding LP.
  • the voltage across the primary winding LP becomes +VCC/2
  • the voltage of the second induced electromotive force of the first secondary winding LS1 is synchronously coupled to +VCC/2.
  • the first auxiliary transistor S1 Due to the interaction of the first diode D1, the first resistor R1 and the second resistor R2 in the first sub-driving circuit AC1, the first auxiliary transistor S1 is controlled to be turned off.
  • the second auxiliary transistor S2 is controlled to be turned on, so that the discharge path of the main transistor Qs continues to be turned on, The voltage on the control electrode of the main transistor Qs is maintained at 0V.
  • the drive circuit in the embodiment of the present application can achieve a current interruption effect on the basis of ensuring the charge and discharge current on the control electrode of the main transistor Qs, thereby minimizing the conduction loss on the primary winding LP and reducing the drive loss. .
  • the driving circuit provided by the embodiment of the present application can also recycle the excess energy stored in the primary winding LP into the driving voltage source, thereby achieving lossless driving.
  • FIG. 10 is a schematic structural diagram of a driving circuit provided by another embodiment of the present application. Moreover, in Figure 10, two main transistors Qs_1 (i.e., the first main transistor) and main transistor Qs_2 (i.e., the second main transistor) connected in series to the ground are driven. body tube) as an example. Referring to FIG.
  • the control electrodes of the main transistors Qs_1 and Qs_2 are connected to the drive circuit 202 , the first electrode of the main transistor Qs_1 is connected to the ground, the second electrode of the main transistor Qs_1 is connected to the first electrode of the main transistor Qs_2 , and the main transistor Qs_2
  • the second electrode of the main transistor Qs_2 may be connected to other devices in the conversion circuit (the specific connection method of the second electrode of the main transistor Qs_2 is not shown in Figure 10).
  • the driving circuit 202 includes: a voltage control circuit 2011, a coupling circuit 2012, and two charge and discharge control circuits 2013_1 and 2013_2.
  • the coupling circuit 2012 includes a primary winding LP and two first secondary windings LS1_1 and LS1_2.
  • the primary winding LP and the first secondary windings LS1_1 and LS1_2 are coupled to each other and in a tightly coupled state.
  • the driving logic of the main transistors Qs_1 and Qs_2 is the same, that is, the main transistors Qs_1 and Qs_2 are turned on and off at the same time, then the first end of the primary winding LP and the first end of the first secondary winding LS1_1 are the same ends.
  • the first end of the primary winding LP and the first end of the first secondary winding LS1_2 are the same ends.
  • the driving circuit provided in the embodiment of the present application is only an example of driving two main transistors with the same driving logic. In practical applications, the driving circuit provided by the embodiment of the present application can drive three, four or more main transistors with the same driving logic, which is not limited here.
  • the charge and discharge control circuit 2013_1 includes: a first auxiliary transistor S1_1, a second auxiliary transistor S2_1, a second capacitor Ct_1, a first diode D1_1, a first resistor R1_1 and a second resistor R2_1.
  • the driving circuit AC1_1 and the second sub-driving circuit AC2_1 are composed of the second diode D2_1, the third resistor R3_1 and the fourth resistor R4_1.
  • the second capacitor Ct_1, the first auxiliary transistor S1_1, the first secondary winding LS1_1, the second auxiliary transistor S2_1, and the control electrode of the main transistor Qs_1 are connected in series. It should be noted that the specific connection relationship may refer to the above embodiment, and will not be described again here.
  • the charge and discharge control circuit 2013_2 includes: a first auxiliary transistor S1_2, a second auxiliary transistor S2_2, a second capacitor Ct_2, a first diode D1_2, a first resistor R1_2 and a second resistor R2_2.
  • the driving circuit AC1_2 and the second sub-driving circuit AC2_2 are composed of the second diode D2_2, the third resistor R3_2 and the fourth resistor R4_2.
  • the second capacitor Ct_2, the first auxiliary transistor S1_2, the first secondary winding LS1_2, the second auxiliary transistor S2_2, and the control electrode of the main transistor Qs_2 are connected in series. It should be noted that the specific connection relationship may refer to the above embodiment, and will not be described again here.
  • the driving circuit provided by the embodiment of the present application can be configured as a non-isolated driving circuit.
  • the second electrode of the second capacitor Ct_1 is also connected to the first end of the primary winding LP.
  • the charge and discharge control circuit 2013_2 also includes a first bootstrap diode Df1, the cathode of the first bootstrap diode Df1 is connected to the second electrode of the second capacitor Ct_2, and the anode of the first bootstrap diode Df1 is connected to the second electrode of the second capacitor Ct_1. Two electrodes are connected.
  • a simple bootstrap circuit is formed by the first bootstrap diode Df1 and the second capacitor Ct_2, so that the reference voltage +VCC/2 is supplied to the high-order main transistor Qs_2 through the bootstrap circuit.
  • FIG. 11 is a signal timing diagram corresponding to the driving circuit shown in FIG. 10 .
  • P P1 represents the first control pulse signal loaded on the control electrode of the first control transistor P1
  • P P2 represents the second control pulse signal loaded on the control electrode of the second control transistor P2
  • U LP represents the primary winding.
  • the voltage across LP, I LP represents the current of the primary winding LP, U LS1_1 represents the voltage corresponding to the induced electromotive force at both ends of the first secondary winding LS1_1, U GS1_1 represents the voltage of the control electrode of the first auxiliary transistor S1_1, and U GS2_1 represents the The voltage of the control electrode of the second auxiliary transistor S2_1, I GQs_1 represents the current of the control electrode of the main transistor Qs_1, U GQs_1 represents the voltage of the control electrode of the main transistor Qs_1, U LS1_2 represents the voltage corresponding to the induced electromotive force at both ends of the first secondary winding LS1_2 , U GS1_2 represents the voltage of the control electrode of the first auxiliary transistor S1_2, U GS2_2 represents the voltage of the control electrode of the second auxiliary transistor S2_2, I GQs_2 represents the current of the control electrode of the main transistor Qs_2, U GQs_2 represents the control
  • the drive circuit shown in Figure 10 combined with the signal timing diagram shown in Figure 11 can control the control electrodes of the main transistors Qs_1 and Qs_2 to charge and discharge at the same time, thereby controlling the main transistors Qs_1 and Qs_2 to turn on and off at the same time. Turn off, thereby making the driving logic of the main transistors Qs_1 and Qs_2 the same.
  • the working process of this embodiment in stages t0 to t6 can be referred to the above embodiment, and will not be described in detail here.
  • FIG. 12 is a schematic structural diagram of a driving circuit provided by another embodiment of the present application. Moreover, FIG. 12 takes as an example an example of driving two main transistors Qs_1 (ie, the first main transistor) and the main transistor Qs_2 (ie, the second main transistor) connected to the ground in series. Referring to FIG. 10 , the control electrodes of main transistors Qs_1 and Qs_2 are connected to the driving circuit 203 .
  • This embodiment is modified from the implementation in the above embodiment. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • the driving circuit 203 includes: a voltage control circuit 2011, a coupling circuit 2012, and two charge and discharge control circuits 2013_1 and 2013_2.
  • the coupling circuit 2012 includes a primary winding LP and two first secondary windings LS1_1 and LS1_2.
  • the primary winding LP and the first secondary windings LS1_1 and LS1_2 are coupled to each other and in a tightly coupled state.
  • the driving logics of the main transistors Qs_1 and Qs_2 are opposite, that is, the logics of the main transistors Qs_1 and Qs_2 are complementary. Specifically, when the main transistor Qs_1 is turned on, the main transistor Qs_2 is turned off.
  • the driving circuit provided in the embodiment of the present application is only an example of driving two main transistors with opposite driving logic. In practical applications, the driving circuit provided by the embodiment of the present application can drive three, four or more main transistors with opposite driving logic, which is not limited here.
  • FIG. 13 is a signal timing diagram corresponding to the driving circuit shown in FIG. 12 .
  • P P1 represents the first control pulse signal loaded on the control electrode of the first control transistor P1
  • P P2 represents the second control pulse signal loaded on the control electrode of the second control transistor P2
  • U LP represents the primary winding.
  • the voltage across LP, I LP represents the current of the primary winding LP, U LS1_1 represents the voltage corresponding to the induced electromotive force at both ends of the first secondary winding LS1_1, U GS1_1 represents the voltage of the control electrode of the first auxiliary transistor S1_1, and U GS2_1 represents the The voltage of the control electrode of the second auxiliary transistor S2_1, I GQs_1 represents the current of the control electrode of the main transistor Qs_1, U GQs_1 represents the voltage of the control electrode of the main transistor Qs_1, U LS1_2 represents the voltage corresponding to the induced electromotive force at both ends of the first secondary winding LS1_2 , U GS1_2 represents the voltage of the control electrode of the first auxiliary transistor S1_2, U GS2_2 represents the voltage of the control electrode of the second auxiliary transistor S2_2, I GQs_2 represents the current of the control electrode of the main transistor Qs_2, U GQs_2 represents the control
  • the control electrodes that drive the main transistors Qs_1 and Qs_2 can be controlled to charge and discharge in a time-sharing manner, so that when the main transistor Qs_1 is turned on, the main transistor Qs_2 is turned off.
  • the main transistor Qs_2 is turned on, the main transistor Qs_1 is turned off.
  • this embodiment controls the discharge of the main transistor Qs_2 when controlling the charging of the main transistor Qs_1 in the t0 to t9 stage, and controls the charging of the main transistor Qs_2 when controlling the discharge of the main transistor Qs_1, thereby realizing driving the main transistor Qs_1 and the main transistor Qs_1.
  • the drive logic of transistor Qs_2 is opposite. Among them, this embodiment controls the charge and discharge process of the main transistor Qs_1 in stages t0 to t6. Reference may be made to the above-mentioned control of the charge and discharge process of the main transistor Qs_1, which will not be described in detail here. Furthermore, in this embodiment, the charging and discharging process of the main transistor Qs_2 is controlled in the stages t3 to t9. Reference may also be made to the charging and discharging process of controlling the main transistor Qs_1 described above, which will not be described in detail here.
  • FIG. 14 is a schematic structural diagram of a driving circuit provided by another embodiment of the present application. Moreover, FIG. 14 takes as an example an example of driving two main transistors Qs_1 (ie, the first main transistor) and the main transistor Qs_2 (ie, the second main transistor) connected to the ground in series. Referring to FIG. 14 , the control electrodes of main transistors Qs_1 and Qs_2 are connected to the drive circuit 204 .
  • This embodiment is modified from the implementation in the above embodiment. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • the driving circuit 204 includes: a voltage control circuit 2011, a coupling circuit 2012, and two charge and discharge control circuits 2013_1 and 2013_2.
  • the coupling circuit 2012 includes a primary winding LP and two first secondary windings LS1_1 and LS1_2.
  • the primary winding LP and the first secondary windings LS1_1 and LS1_2 are coupled to each other and in a tightly coupled state.
  • the driving logics of the main transistors Qs_1 and Qs_2 are opposite, that is, the logics of the main transistors Qs_1 and Qs_2 are complementary. Specifically, when the main transistor Qs_1 is turned on, the main transistor Qs_2 is turned off.
  • the driving circuit provided in the embodiment of the present application is only an example of driving two main transistors with opposite driving logic. In practical applications, the driving circuit provided by the embodiment of the present application can drive three, four or more main transistors with opposite driving logic, which is not limited here.
  • the driving logic of the main transistors Qs_1 and Qs_2 can also be made the same, that is, the main transistors Qs_1 and Qs_2 are turned on and off at the same time. Specifically, when the main transistor Qs_1 is turned on, the main transistor Qs_2 is turned on. When the main transistor Qs_1 is turned off, the main transistor Qs_2 is turned off. Then the first end of the primary winding LP and the first end of the first secondary winding LS1_1 are the same end, and the first end of the primary winding LP and the first end of the first secondary winding LS1_2 are the same end.
  • the charge and discharge control circuit 2013_1 includes: a first auxiliary transistor S1_1, a second auxiliary transistor S2_1, a second capacitor Ct_1, a first diode D1_1, a first resistor R1_1 and a second resistor R2_1.
  • the driving circuit AC1_1 and the second sub-driving circuit AC2_1 are composed of the second diode D2_1, the third resistor R3_1 and the fourth resistor R4_1.
  • the second capacitor Ct_1, the first auxiliary transistor S1_1, the first secondary winding LS1_1, the second auxiliary transistor S2_1, and the control electrode of the main transistor Qs_1 are connected in series. It should be noted that the specific connection relationship may refer to the above embodiment, and will not be described again here.
  • the charge and discharge control circuit 2013_2 includes: a first auxiliary transistor S1_2, a second auxiliary transistor S2_2, a second capacitor Ct_2, a first diode D1_2, a first resistor R1_2 and a second resistor R2_2.
  • the driving circuit AC1_2 and the second sub-driving circuit AC2_2 are composed of the second diode D2_2, the third resistor R3_2 and the fourth resistor R4_2.
  • the second capacitor Ct_2, the first auxiliary transistor S1_2, the first secondary winding LS1_2, the second auxiliary transistor S2_2, and the control electrode of the main transistor Qs_2 are connected in series. It should be noted that the specific connection relationship may refer to the above embodiment, and will not be described again here.
  • the drive circuit 204 provided in the embodiment of the present application can also be configured as an isolation drive circuit.
  • the second secondary winding LD in order to provide a reference voltage for the secondary side of the isolated driving circuit, the second secondary winding LD can be set in the coupling circuit 2012, and the energy storage capacitor CD and the second self-winding winding LD can be set in the driving circuit 204.
  • the primary winding LP and the second secondary winding LD are coupled to each other and are in a tightly coupled state. This enables the second secondary winding LD to generate the first induced electromotive force according to the first voltage coupling, and generate the second induced electromotive force according to the second voltage coupling.
  • the anode of the second bootstrap diode Df2 is connected to the first terminal of the second secondary winding LD, and the cathode of the second bootstrap diode Df2 is connected to the first electrode of the energy storage capacitor CD.
  • the second electrode of the energy storage capacitor CD is connected to the second terminal and the ground terminal of the second secondary winding LD respectively.
  • the second electrode of the second capacitor Ct_1 is also connected to the first electrode of the energy storage capacitor CD.
  • a peak holding circuit can be formed, thereby forming an isolated reference voltage DC voltage source on the secondary side of the isolated driver, so that The voltage across the second capacitor Ct_1 is the second voltage.
  • the first end of the second secondary winding LD and the first end of the primary winding LP have the same name.
  • the second electrode of the second capacitor Ct_1 is also connected to the first electrode of the energy storage capacitor CD.
  • the charge and discharge control circuit 2013_2 also includes a third bootstrap diode Df3, the cathode of the third bootstrap diode Df3 is connected to the second electrode of the second capacitor Ct_2, and the anode of the third bootstrap diode Df3 is connected to the second electrode of the second capacitor Ct_1. Two electrodes are connected. And the first end of the primary winding LP and the first end of the second secondary winding LD have the same name.
  • a simple bootstrap circuit is formed by the third bootstrap diode Df3 and the second capacitor Ct_2, so that the reference voltage +VCC/2 is supplied to the high-order main transistor Qs_2 through the bootstrap circuit.
  • the driving circuit shown in Figure 14 and the corresponding signal timing diagram are shown in Figure 13.
  • the control electrodes that drive the main transistors Qs_1 and Qs_2 can be controlled to charge and discharge in a time-sharing manner, so that when the main transistor Qs_1 is turned on, the main transistor Qs_2 is turned off. Break. When the main transistor Qs_2 is turned on, the main transistor Qs_1 is turned off.
  • this embodiment controls the discharge of the main transistor Qs_2 when controlling the charging of the main transistor Qs_1 in the t0 to t9 stage, and controls the charging of the main transistor Qs_2 when controlling the discharge of the main transistor Qs_1, thereby realizing driving the main transistor Qs_1 and the main transistor Qs_1.
  • the driving logic of transistor Qs_2 is opposite.
  • this embodiment controls the charge and discharge process of the main transistor Qs_1 in stages t0 to t6. Reference may be made to the above-mentioned control of the charge and discharge process of the main transistor Qs_1, which will not be described in detail here.
  • the charging and discharging process of the main transistor Qs_2 is controlled in the stages t3 to t9. Reference may also be made to the charging and discharging process of controlling the main transistor Qs_1 described above, which will not be described in detail here.
  • FIG. 15 is a schematic structural diagram of a driving circuit provided by another embodiment of the present application. Moreover, in FIG. 15 , four main transistors Qs_1 (ie, the first main transistor), main transistor Qs_2 (ie, the second main transistor), main transistor Qs_3 (ie, the third main transistor), and main transistor Qs_4 are driven in series and are connected to the ground. (i.e., the fourth main transistor) is shown as an example. Referring to FIG. 15 , the control electrodes of main transistors Qs_1 to Qs_4 are connected to the drive circuit 205 .
  • This embodiment is modified from the implementation in the above embodiment. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • the driving circuit 205 includes: a voltage control circuit 2011, a coupling circuit 2012, and four charge and discharge control circuits 2013_1 ⁇ 2013_4.
  • the coupling circuit 2012 includes a primary winding LP and four first secondary windings LS1_1 to LS1_4.
  • the primary winding LP and the first secondary windings LS1_1 to LS1_4 are coupled to each other and in a tightly coupled state.
  • the driving logic of the main transistors Qs_1 and Qs_2 is the same, that is, the main transistors Qs_1 and Qs_2 are turned on and off at the same time
  • the driving logic of the main transistors Qs_3 and Qs_4 is the same, that is, the main transistors Qs_3 and Qs_4 are turned on and off at the same time. Break.
  • the driving logic of the main transistors Qs_3 and Qs_1 is opposite, then the first end of the primary winding LP and the first end of the first secondary winding LS1_1 are the same ends, and the first end of the primary winding LP and the first secondary winding
  • the first end of LS1_2 is the end of the same name
  • the first end of the primary winding LP and the first end of the first secondary winding LS1_3 are the end of the same name
  • the first end of the primary winding LP and the first end of the first secondary winding LS1_4 are different ends.
  • One end is the heteronymous end.
  • the charge and discharge control circuit 2013_1 includes: a first auxiliary transistor S1_1, a second auxiliary transistor S2_1, a second capacitor Ct_1, a first diode D1_1, a first resistor R1_1 and a second resistor R2_1.
  • the driving circuit AC1_1 and the second sub-driving circuit AC2_1 are composed of the second diode D2_1, the third resistor R3_1 and the fourth resistor R4_1.
  • the second capacitor Ct_1, the first auxiliary transistor S1_1, the first secondary winding LS1_1, the second auxiliary transistor S2_1, and the control electrode of the main transistor Qs_1 are connected in series. It should be noted that the specific connection relationship may refer to the above embodiment, and will not be described again here.
  • the charge and discharge control circuit 2013_2 includes: a first auxiliary transistor S1_2, a second auxiliary transistor S2_2, a second capacitor Ct_2, a first diode D1_2, a first resistor R1_2 and a second resistor R2_2.
  • the driving circuit AC1_2 and the second sub-driving circuit AC2_2 are composed of the second diode D2_2, the third resistor R3_2 and the fourth resistor R4_2.
  • the second capacitor Ct_2, the first auxiliary transistor S1_2, the first secondary winding LS1_2 The control electrodes of the second auxiliary transistor S2_2 and the main transistor Qs_2 are connected in series. It should be noted that the specific connection relationship may refer to the above embodiment, and will not be described again here.
  • the charge and discharge control circuit 2013_3 includes: a first auxiliary transistor S1_3, a second auxiliary transistor S2_3, a second capacitor Ct_3, a first diode D1_3, a first resistor R1_3 and a second resistor R2_3.
  • the driving circuit AC1_3 and the second sub-driving circuit AC2_3 are composed of the second diode D2_3, the third resistor R3_3 and the fourth resistor R4_3.
  • the second capacitor Ct_3, the first auxiliary transistor S1_3, the first secondary winding LS1_3, the second auxiliary transistor S2_3, and the control electrode of the main transistor Qs_3 are connected in series. It should be noted that the specific connection relationship may refer to the above embodiment, and will not be described again here.
  • the charge and discharge control circuit 2013_4 includes: a first auxiliary transistor S1_4, a second auxiliary transistor S2_4, a second capacitor Ct_4, a first diode D1_4, a first resistor R1_4 and a second resistor R2_4.
  • the driving circuit AC1_4 and the second sub-driving circuit AC2_4 are composed of the second diode D2_4, the third resistor R3_4 and the fourth resistor R4_4.
  • the second capacitor Ct_4, the first auxiliary transistor S1_4, the first secondary winding LS1_4, the second auxiliary transistor S2_4, and the control electrode of the main transistor Qs_4 are connected in series. It should be noted that the specific connection relationship may refer to the above embodiment, and will not be described again here.
  • the drive circuit 205 provided in the embodiment of the present application can also be configured as an isolation drive circuit.
  • the second secondary winding LD in order to provide a reference voltage for the secondary side of the isolated driving circuit, the second secondary winding LD can be set in the coupling circuit 2012, and the energy storage capacitor CD and the second self-winding winding can be set in the driving circuit 204. Take diode Df2. Among them, the primary winding LP and the second secondary winding LD are coupled to each other and in a tightly coupled state. This enables the second secondary winding LD to generate the first induced electromotive force according to the first voltage coupling, and generate the second induced electromotive force according to the second voltage coupling.
  • the anode of the second bootstrap diode Df2 is connected to the first terminal of the second secondary winding LD, and the cathode of the second bootstrap diode Df2 is connected to the first electrode of the energy storage capacitor CD.
  • the second electrode of the energy storage capacitor CD is connected to the second terminal and the ground terminal of the second secondary winding LD respectively.
  • the second electrode of the second capacitor Ct_1 is also connected to the first electrode of the energy storage capacitor CD.
  • a peak holding circuit can be formed, thereby forming an isolated reference voltage DC voltage source on the secondary side of the isolated driver, so that The voltage across the second capacitor Ct_1 is the second voltage.
  • the first end of the second secondary winding LD and the first end of the primary winding LP have the same name.
  • the second electrode of the second capacitor Ct_1 is also connected to the first electrode of the energy storage capacitor CD.
  • the charge and discharge control circuit 2013_2 further includes a third bootstrap diode Df3_1
  • the charge and discharge control circuit 2013_3 further includes a third bootstrap diode Df3_2
  • the charge and discharge control circuit 2013_4 further includes a third bootstrap diode Df3_3.
  • the cathode of the third bootstrap diode Df3_1 is connected to the second electrode of the second capacitor Ct_2, and the anode of the third bootstrap diode Df3_1 is connected to the second electrode of the second capacitor Ct_1.
  • a simple bootstrap circuit is formed by the third bootstrap diode Df3_1 and the second capacitor Ct_2, so that the reference voltage +VCC/2 is supplied to the high-order main transistor Qs_2 through the bootstrap circuit.
  • the cathode of the third bootstrap diode Df3_2 is connected to the second electrode of the second capacitor Ct_3, and the anode of the third bootstrap diode Df3_2 is connected to the second electrode of the second capacitor Ct_2.
  • a simple bootstrap circuit is formed by the third bootstrap diode Df3_2 and the second capacitor Ct_3, so that the reference voltage +VCC/2 is supplied to the high-order main transistor Qs_3 through the bootstrap circuit.
  • the cathode of the third bootstrap diode Df3_3 is connected to the second electrode of the second capacitor Ct_4, and the anode of the third bootstrap diode Df3_3 is connected to the second electrode of the second capacitor Ct_3.
  • a simple bootstrap circuit is formed by the third bootstrap diode Df3_3 and the second capacitor Ct_4, so that the reference voltage +VCC/2 is supplied to the high-order main transistor Qs_4 through the bootstrap circuit.
  • FIG. 16 is a signal timing diagram corresponding to the driving circuit shown in FIG. 15 .
  • P P1 represents loading into The first control pulse signal on the control electrode of the first control transistor P1
  • P P2 represents the second control pulse signal loaded on the control electrode of the second control transistor P2
  • U LP represents the voltage across the primary winding LP
  • I LP represents the current of the primary winding LP
  • U LS1_1 represents the voltage corresponding to the induced electromotive force at both ends of the first secondary winding LS1_1
  • U GS1_1 represents the voltage of the control electrode of the first auxiliary transistor S1_1
  • U GS2_1 represents the control electrode of the second auxiliary transistor S2_1
  • the voltage of the control electrode of the transistor S1_2, U GS2_2 represents the voltage of the control electrode of the second auxiliary transistor S2_2,
  • I GQs_2 represents the current of the control electrode of the main transistor Qs_2, and
  • U LS1_3 represents the voltage corresponding to the induced electromotive force at both ends of the first secondary winding LS1_3
  • U GS1_3 represents the voltage of the control electrode of the first auxiliary transistor S1_3
  • U GS2_3 represents the voltage of the control electrode of the second auxiliary transistor S2_3
  • I GQs_3 represents the main transistor
  • the current of the control electrode of Qs_3, U GQs_3 represents the voltage of the control electrode of the main transistor Qs_3.
  • U LS1_4 represents the voltage corresponding to the induced electromotive force at both ends of the first secondary winding LS1_4, U GS1_4 represents the voltage of the control electrode of the first auxiliary transistor S1_4, U GS2_4 represents the voltage of the control electrode of the second auxiliary transistor S2_4, and I GQs_4 represents the main transistor The current of the control electrode of Qs_4, U GQs_4 represents the voltage of the control electrode of the main transistor Qs_4.
  • the control electrodes of the main transistors Qs_1 and Qs_2 can be controlled to charge and discharge at the same time, and the control electrodes of the main transistors Qs_3 and Qs_4 can be controlled to charge and discharge at the same time.
  • the control electrodes of Qs_1 and Qs_3 charge and discharge in a time-sharing manner, so that the driving logic of the main transistor Qs_1 and the main transistor Qs_2 is the same, the driving logic of the main transistor Qs_3 and the main transistor Qs_4 is the same, and the driving logic of the main transistor Qs_1 and the main transistor Qs_3 is opposite.
  • this embodiment controls the charging and discharging process of the main transistors Qs_1 and Qs_2 in the stages t0 to t6.
  • the charging and discharging process of the main transistors Qs_3 and Qs_4 is controlled in the stages t3 to t9.
  • FIG. 17 is a schematic structural diagram of a driving circuit provided by another embodiment of the present application.
  • driving two main transistors Qs_1a and Qs_1b, both of which are connected to the ground terminal is taken as an example.
  • the control electrodes of the main transistors Qs_1a and Qs_1b are connected to the drive circuit 206 .
  • This embodiment is modified from the implementation in the above embodiment. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • the driving circuit 206 includes: a voltage control circuit 2011, a coupling circuit 2012, and two charge and discharge control circuits 2013_1a and 2013_1b.
  • the coupling circuit 2012 includes a primary winding LP and two first secondary windings LS1_1a and LS1_1b.
  • the primary winding LP and the first secondary windings LS1_1a and LS1_1b are coupled to each other and in a tightly coupled state.
  • the driving logics of the main transistors Qs_1a and Qs_1b are opposite, that is, the logics of the main transistors Qs_1a and Qs_1b are complementary.
  • the driving circuit provided in the embodiment of the present application is only an example of driving two main transistors with opposite driving logic. In practical applications, the driving circuit provided by the embodiment of the present application can drive three, four or more main transistors with opposite driving logic, which is not limited here.
  • the driving logic of the main transistors Qs_1a and Qs_1b can also be made the same, that is, the main transistors Qs_1a and Qs_1b can be turned on and off at the same time. Specifically, when the main transistor Qs_1a is turned on, the main transistor Qs_1b is turned on. When the main transistor Qs_1a is turned off, the main transistor Qs_1b is turned off. Then the first end of the primary winding LP and the first end of the first secondary winding LS1_1 are the same end, and the first end of the primary winding LP and the first end of the first secondary winding LS1_2 are the same end.
  • the charge and discharge control circuit 2013_1a includes: a first auxiliary transistor S1_1a, a second auxiliary transistor S2_1a, a second capacitor Ct_1a, a first diode D1_1a, a first resistor R1_1a, and a second resistor R2_1a.
  • the driving circuit AC1_1a and the second sub-driving circuit AC2_1a are composed of the second diode D2_1a, the third resistor R3_1a and the fourth resistor R4_1a.
  • the second capacitor Ct_1a, the first auxiliary transistor S1_1a, the first secondary winding LS1_1a, the second auxiliary transistor S2_1a, and the control electrode of the main transistor Qs_1a are connected in series. It should be noted that the specific connection relationship may refer to the above embodiment, and will not be described again here.
  • the charge and discharge control circuit 2013_1b includes: a first auxiliary transistor S1_1b, a second auxiliary transistor S2_1b, a second capacitor Ct_1b, a first diode D1_1b, a first resistor R1_1b, and a second resistor R2_1b.
  • the driving circuit AC1_1b and the second sub-driving circuit AC2_1b are composed of the second diode D2_1b, the third resistor R3_1b and the fourth resistor R4_1b.
  • the second capacitor Ct_1b, the first auxiliary transistor S1_1b, the first secondary winding LS1_1b, the second auxiliary transistor S2_1b, and the control electrode of the main transistor Qs_1b are connected in series. It should be noted that the specific connection relationship may refer to the above embodiment, and will not be described again here.
  • the drive circuit 206 provided in the embodiment of the present application is configured as an isolation drive circuit.
  • the second secondary winding LD can be set in the coupling circuit 2012, and the energy storage capacitor CD and the second self-winding winding LD can be set in the driving circuit 205.
  • the second electrode of the second capacitor Ct_1 and the second electrode of the second capacitor Ct_1b are also connected to the first electrode of the energy storage capacitor CD.
  • the primary winding LP and the second secondary winding LD are coupled to each other and in a tightly coupled state.
  • the second secondary winding LD to generate the first induced electromotive force according to the first voltage coupling, and generate the second induced electromotive force according to the second voltage coupling.
  • the anode of the second bootstrap diode Df2 is connected to the first terminal of the second secondary winding LD, and the cathode of the second bootstrap diode Df2 is connected to the first electrode of the energy storage capacitor CD.
  • the second electrode of the energy storage capacitor Df2 is connected to the second terminal and the ground terminal of the second secondary winding LD respectively.
  • the second electrodes of the second capacitors Ct_1a and Ct_1b are also connected to the first electrode of the energy storage capacitor CD.
  • a peak holding circuit can be formed, thereby forming an isolated reference voltage DC voltage source on the secondary side of the isolated driver, so that The voltages across the second capacitors Ct_1a and Ct_1b are the second voltage.
  • the first end of the second secondary winding LD and the first end of the primary winding LP have the same name.
  • FIG. 18 is a signal timing diagram corresponding to the driving circuit shown in FIG. 17 .
  • P P1 represents the first control pulse signal loaded on the control electrode of the first control transistor P1
  • P P2 represents the second control pulse signal loaded on the control electrode of the second control transistor P2
  • U LP represents the primary winding.
  • the voltage across LP, I LP represents the current of the primary winding LP, U LS1_1a represents the voltage corresponding to the induced electromotive force at both ends of the first secondary winding LS1_1a, U GS1_1a represents the voltage of the control electrode of the first auxiliary transistor S1_1a, and U GS2_1a represents the The voltage of the control electrode of the second auxiliary transistor S2_1a, I GQs_1a represents the current of the control electrode of the main transistor Qs_1a, U GQs_1a represents the voltage of the control electrode of the main transistor Qs_1a, U LS1_1b represents the corresponding induced electromotive force at both ends of the first secondary winding LS1_1b voltage, U GS1_1b represents the voltage of the control electrode of the first auxiliary transistor S1_1b , U GS2_1b represents the voltage of the control electrode of the second auxiliary transistor S2_1b , I GQs_1b represents
  • the control electrodes that drive the main transistors Qs_1a and Qs_1b can be controlled to charge and discharge in a time-sharing manner, so that when the main transistor Qs_1a is turned on, the main transistor Qs_1b is turned off. Break. When the main transistor Qs_1b is turned on, the main transistor Qs_1a is turned off.
  • this embodiment controls the discharge of the main transistor Qs_1b when controlling the charging of the main transistor Qs_1a in the t0 to t9 stage, and controls the charging of the main transistor Qs_1b when controlling the discharge of the main transistor Qs_1a, thereby realizing driving the main transistor Qs_1a and the main transistor Qs_1a.
  • transistor The driving logic of Qs_1b is opposite.
  • this embodiment controls the charge and discharge process of the main transistor Qs_1a in the stages t0 to t6. Reference may be made to the above-mentioned control of the charge and discharge process of the main transistor Qs_1, which will not be described in detail here.
  • the charging and discharging process of the main transistor Qs_1b is controlled in the stages t3 to t9, and reference can also be made to the above-mentioned control of the charging and discharging process of the main transistor Qs_1, which will not be described in detail here.
  • the above are only examples to illustrate the working process of the driving circuit of the present application when controlling different main transistors in different driving logics.
  • the above driving circuits can be combined to be applied to specific conversion circuits.
  • the driving loss of the entire circuit can be reduced while controlling the conversion circuit to achieve voltage conversion.
  • the conversion circuit is an LLC resonant converter as an example. That is, the main transistor driven by the drive circuit in this application can be a switching tube in the LLC resonant converter.
  • FIG. 19 is a schematic structural diagram of an LLC resonant converter provided by an embodiment of the present application.
  • This conversion circuit takes a half-bridge LLC resonant converter as an example.
  • the conversion circuit 101 includes an inverter circuit, a resonant circuit, a transformer and a rectifier circuit.
  • the inverter circuit converts the input voltage Vi into an AC voltage, and transmits the converted AC voltage to the rectifier circuit through the resonant circuit and the transformer, and the rectifier circuit
  • the AC power output by the transformer is converted into DC voltage V O and then output.
  • the inverter circuit mainly includes: capacitors C1 and C2, and two switching transistors Q11 and Q12.
  • the resonant circuit mainly includes: resonant inductor Lr0 and resonant capacitor Cr0.
  • the primary winding of the transformer T is connected in series with the resonant inductor Lr0 and the resonant capacitor Cr0, and the secondary winding of the transformer T is connected to the rectifier circuit.
  • the rectifier circuit mainly includes switching tubes Q13 ⁇ Q16.
  • the resonant inductor Lr0 can be an independent inductor, or it can be the leakage inductance of the primary winding of the transformer, or the resonant inductor Lr0 is composed of part of the independent inductance and part of the leakage inductance of the primary winding of the transformer.
  • the switching transistors Q11 to Q16 in the conversion circuit 101 are MOSFETs, then the control electrodes of the switching transistors Q11 to Q16 are gate electrodes.
  • the first electrode of any of the switch tubes Q11 to Q16 can be the source electrode and the second electrode can be the drain electrode.
  • the first electrode of any one of the switching transistors Q11 to Q16 is the drain electrode, and the second electrode is the source electrode.
  • “+" represents the high voltage terminal
  • "-" represents the ground terminal.
  • the inverter circuit in the conversion circuit 101 shown in FIG. 19 may be provided with a corresponding drive circuit in the present application.
  • the main transistor Qs_1 connected to the driving circuits 203 and 204 in the embodiment of the present application may be the switching transistor Q11 in the conversion circuit 101
  • the main transistor Qs_2 may be the switching transistor Q12 in the conversion circuit 101.
  • the rectifier circuit in the conversion circuit 101 shown in FIG. 19 may be provided with a corresponding drive circuit in the present application.
  • a voltage control circuit, a coupling circuit and four charge and discharge control circuits can be provided. That is, a charging and discharging control circuit is connected to the switching tubes Q13 ⁇ Q16 respectively, and the driving logic of the switching tube Q13 and the switching tube Q16 is the same, the driving logic of the switching tube Q14 and the switching tube Q15 is the same, and the driving logic of the switching tube Q13 and the switching tube Q14 is the same. on the contrary.
  • the inverter circuit and the rectifier circuit in the conversion circuit 101 shown in FIG. 19 are correspondingly provided with a driving circuit in this application.
  • the driving circuits 203, 204 and 206 in the embodiment of the present application can be provided with a voltage control circuit, a coupling circuit and six charge and discharge control circuits.
  • Switch tubes Q11 to Q16 are connected to a charge and discharge control circuit in one-to-one correspondence.
  • FIG 20 is a schematic structural diagram of an LLC resonant converter provided by another embodiment of the present application.
  • the conversion circuit 102 takes a cascaded half-bridge LLC resonant converter as an example.
  • the LLC resonant converter provided by this embodiment is the same as shown in Figure 19 LLC resonant converters differ only in the inverter circuit. Only the differences will be explained below, and the similarities will not be repeated.
  • the inverter circuit mainly includes: capacitors C1 and C2, and four switching tubes Q21 ⁇ Q24. Among them, the switching tubes Q21 to Q24 are connected in series to the ground terminal.
  • the inverter circuit in the conversion circuit 102 shown in FIG. 20 may be provided with a corresponding drive circuit in the present application.
  • the main transistor Qs_1 connected to the driving circuit 205 in the embodiment of the present application can be the switch transistor Q21 in the conversion circuit 102
  • the main transistor Qs_2 can be the switch transistor Q22 in the conversion circuit 102
  • the main transistor Qs_3 can be the switch transistor Q22 in the conversion circuit 102.
  • the switch transistor Q23 and the main transistor Qs_4 can be the switch transistor Q24 in the conversion circuit 102.
  • the input voltage Vi of the inverter circuit is set to 40V
  • the effective value of the main circuit AC current is 1A
  • the output power of the inverter circuit is 40W
  • the driving voltage source VDC connected to the driving circuit 205 is set.
  • the driving voltage VCC is 5V
  • the switching frequency of the switching transistors Q21 ⁇ Q24 is 2MHz
  • the conduction time of the corresponding effective level of the control transistors P1 ⁇ P2 is 50ns.
  • the working process of the driving circuit 205 driving the switching transistors Q21 to Q24 in the conversion circuit 102 in the embodiment of the present application was simulated.
  • the waveform diagram of the simulation is shown in Figure 21.
  • L11 represents the simulated current of the primary winding LP
  • L12 represents the simulated current of a first primary winding
  • L21 represents the simulated control electrode voltage of the switch Q21
  • L22 represents the simulation of the switch Q22.
  • the voltage of the control electrode L23 represents the voltage of the simulated control electrode of the switch tube Q23
  • L24 represents the voltage of the simulated control electrode of the switch tube Q24.
  • the simulation results are basically consistent with the theoretical analysis.
  • the driving logic of switching tubes Q21 and Q22 and switching tubes Q23 and Q24 are complementary.
  • the current of the primary winding and the current of the first secondary winding are also basically consistent with the theoretical analysis.
  • the driving circuit 205 provided by the embodiment of the present application can effectively reduce the power loss by 396mW compared to 396mW in this application scenario. *46% or more.
  • the driving circuits 204 and 206 in the embodiment of the present application can be combined to determine the driving inverter circuit.
  • Drive circuit For example, a voltage control circuit, a coupling circuit, and four charge and discharge control circuits can be provided.
  • Each switching tube in the inverter circuit is connected to a charge and discharge control circuit, and the driving logic of the two switching tubes in the first group is the same, and the driving logic of the two switching tubes in the second group is the same, and the driving logic of the two switching tubes in the first group is the same.
  • the two switch tubes in the second group have opposite driving logic than the two switch tubes in the second group.
  • the driving circuit provided by the embodiment of the present application drives a large number of main transistors, it only needs to add a charge and discharge control circuit and a first secondary winding, which is beneficial to saving the cost and volume of the driving circuit.
  • the driving circuit provided by the embodiment of the present application has two modes: non-isolated type and isolation type. In this way, the driving circuit mode can be selectively adopted according to the non-isolated occasion and the isolated occasion, thereby improving the applicability of the driving circuit.
  • the drive circuit provided by the embodiment of the present application provides control pulse signals to the voltage control circuit and occupies less IO interface resources.
  • a power module which may include a conversion circuit and a driving circuit provided by any of the above.
  • the driving circuit is used to drive the main transistor in the conversion circuit.
  • the power module can be either a DC-DC power module or an AC-DC power module.
  • the above power module can be used in different types of electronic devices, such as smart phones, smart TVs, laptops, handheld computers (personal digital assistants, PDAs), and wearable devices with wireless communication functions (such as smart watches, smart glasses, smart wristband), vehicle equipment or data center, etc. Since the problem-solving principle of this power module is the same as that of the aforementioned driver The circuits are similar, so the implementation of the power module can be referred to the implementation of the aforementioned drive circuit, and repeated details will not be repeated.
  • an electronic device which may include the power module and the load module provided by any one of the above.
  • the power module is electrically connected to the load module to provide DC voltage to the load module.
  • the electronic device is: a smart phone, a smart TV, a notebook computer, a personal digital assistant (PDA), a wearable device with wireless communication functions (such as a smart watch, smart glasses, and a smart bracelet), Vehicle equipment or data center, etc. Since the problem-solving principle of this electronic device is similar to that of the foregoing power module, the implementation of this electronic device can refer to the implementation of the foregoing power module, and repeated details will not be repeated.

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Abstract

本申请提供驱动电路、控制方法、电源模块及电子设备，该驱动电路可以驱动N个主晶体管。其包括电压控制电路、耦合电路及N个充放电控制电路。耦合电路包括原边绕组和N个第一副边绕组。电压控制电路响应于多个控制脉冲信号，驱动原边绕组产生周期性的第一电压和第二电压。充放电控制电路用于根据对应连接的第一副边绕组耦合产生的第一感应电动势和第二感应电动势，控制对应连接的主晶体管的控制电极进行充放电，以控制对应连接的主晶体管导通和关断。控制脉冲信号的有效电平在一个周期中的占空比的范围设置为4％～30％，可使控制脉冲信号实现短脉冲形式，快速驱动主晶体管的控制电极充放电，实现原边绕组和副边绕组断流效果，降低驱动损耗。

Description

驱动电路、控制方法、电源模块及电子设备
相关申请的交叉引用
本申请要求在2022年07月27日提交中国专利局、申请号为202210896029.7、申请名称为“驱动电路、控制方法、电源模块及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请应用于电力电子技术领域，特别涉及驱动电路、控制方法、电源模块及电子设备。
背景技术
随着电力电子技术的不断发展，电力电子设备高频化、小型化已经是一个众所周知的大趋势。为了达到更高的功率密度，通常采用提高开关管的开关频率的方法，来减小直流(Direct Current，DC)-DC转换器中的电容、电感、变压器等磁性元件的体积。在实际应用中，通过设计驱动电路的具体结构可以实现控制开关管的开关频率。通常，驱动电路可以采用非隔离型的电感型谐振驱动器或隔离型的变压器型谐振驱动器等结构。然而，目前的电感型谐振驱动器，不适用于多级转换器或全桥转换器等多个开关管的应用场合，占用输入输出(Input/Output，IO)接口资源较多，不利于节约驱动电路的成本和体积。并且，目前的变压器型谐振驱动器的变压器绕组的损耗较大。
发明内容
本申请提供一种驱动电路、控制方法、电源模块及电子设备，用于降低驱动电路的成本和体积，以及降低驱动损耗。
第一方面，本申请实施例提供一种驱动电路，该驱动电路可以驱动N个主晶体管。其中，N为1、2、3、4或更多，以使本申请实施例提供的驱动电路能够驱动一个或多个主晶体管。该驱动电路主要包括：电压控制电路、耦合电路以及N个充放电控制电路。耦合电路包括原边绕组和N个第一副边绕组，原边绕组和N个第一副边绕组中的每一个第一副边绕组之间互相耦合，且处于紧耦合状态。这样可使本申请实施例提供的驱动电路为变压器型谐振驱动器，提高驱动电路的简洁性。并且，电压控制电路与原边绕组连接，N个第一副边绕组与N个充放电控制电路一一对应连接，N个充放电控制电路与N个主晶体管的控制电极一一对应连接。以及，电压控制电路用于响应于多个控制脉冲信号，驱动原边绕组产生周期性的第一电压和第二电压；其中，N个第一副边绕组中的任一个第一副边绕组根据第一电压耦合产生第一感应电动势，根据第二电压耦合产生第二感应电动势。N个充放电控制电路中的任一个充放电控制电路用于根据对应连接的第一副边绕组耦合产生的第一感应电动势和第二感应电动势，控制对应连接的主晶体管的控制电极进行充放电，以控制对应连接的主晶体管导通和关断。其中，通过将控制脉冲信号的有效电平在一个周期中的占空比的范围设置为4％～30％，可使控制脉冲信号实现短脉冲(即有效电平的维持时长 较短)形式，从而控制电压控制电路中的控制晶体管能够快速导通和关断，进而实现快速驱动主晶体管的控制电极充放电，并在快速驱动主晶体管的控制电极充放电后，实现原边绕组和副边绕组断流效果，使原边绕组上的导通损耗最小化，降低驱动损耗。
在本申请一些实施例中，电压控制电路可以采用控制晶体管和电容相结合的方式实现，且一个控制晶体管对应加载一个控制脉冲信号。在实际工作时，电压控制电路内的控制晶体管响应于加载的控制脉冲信号，相互结合工作，以根据驱动电压源的驱动电压产生周期性的第一电压和第二电压。示例性地，控制脉冲信号为周期性出现有效电平的信号，且相邻两个有效电平之间为无效电平。控制脉冲信号的有效电平可以控制电压控制电路内的控制晶体管导通，无效电平可以控制电压控制电路内的控制晶体管关断。并且，控制脉冲信号的一个周期为一个有效电平的维持时长与一个无效电平的维持时长之和。控制脉冲信号的有效电平在一个周期中的占空比为：有效电平的维持时长与一个周期的时长的比值。在本申请实施例中，控制脉冲信号的有效电平在一个周期中的占空比的范围为4％～30％。然而，相关技术中变压器型谐振驱动器的控制信号的占空比通常在45％～60％之间，这样使得变压器型谐振驱动器通常都是通过长脉冲(即有效电平的维持时长较长)进行驱动的，导致变压器型谐振驱动器中变压器原边绕组和副边绕组的电流是长时间存在的。而，本申请实施例提供的驱动电路，通过将控制脉冲信号的有效电平在一个周期中的占空比的范围设置为4％～30％，可使控制脉冲信号实现短脉冲(即有效电平的维持时长较短)形式，从而控制电压控制电路中的控制晶体管能够快速导通和关断，进而实现快速驱动主晶体管的控制电极充放电，并在快速驱动主晶体管的控制电极充放电后，实现原边绕组和副边绕组断流效果，使原边绕组上的导通损耗最小化，降低驱动损耗。
在一种可能的实现方式中，控制脉冲信号的有效电平在一个周期中的占空比可以根据主晶体管Qs的开关频率进行设置。示例性地，主晶体管Qs的开关频率设置为1MHz，控制脉冲信号的有效电平在一个周期中的占空比的范围为1/21～1/6。具体地，控制脉冲信号的有效电平每1000ns出现一次，且该有效电平的维持时长为50ns～200ns。例如，有效电平的维持时长为50ns、80ns、100ns、130ns、150ns、180ns、200ns中的一个。当然，在实际应用中，该有效电平的维持时长可以根据实际应用的需求进行确定，在此不作限定。
示例性地，主晶体管Qs的开关频率也可以设置为2MHz，控制脉冲信号的有效电平在一个周期中的占空比的范围为1/11～2/7。具体地，控制脉冲信号的有效电平每500ns出现一次，且该有效电平的维持时长为50ns～200ns。例如，有效电平的维持时长为50ns、80ns、100ns、130ns、150ns、180ns、200ns中的一个。当然，在实际应用中，该有效电平的维持时长可以根据实际应用的需求进行确定，在此不作限定。
示例性地，主晶体管Qs的开关频率为1MHz时对应的有效电平与其开关频率为2MHz时对应的有效电平的维持时长相同。例如，主晶体管Qs的开关频率为1MHz时对应的有效电平与其开关频率为2MHz时对应的有效电平的维持时长可以均为50ns、80ns、100ns、130ns、150ns、180ns、200ns中的一个。这样可以统一不同开关频率下的有效电平的维持时长，降低控制难度。
在一种可能的实现方式中，电压控制电路可以采用控制晶体管和电容相结合的方式实现，且一个控制晶体管对应加载一个控制脉冲信号。示例性地，电压控制电路包括：多个控制晶体管和第一电容，第一电容与原边绕组串联连接后与多个控制晶体管中的至少一个控制晶体管并联，且该多个控制晶体管串联连接于驱动电压源的正负极之间。控制脉冲信 号为多个，多个控制晶体管与多个控制脉冲信号一一对应，多个控制晶体管中的每一个控制晶体管的控制电极用于接收对应的控制脉冲信号。多个控制晶体管响应于对应的控制脉冲信号，根据驱动电压源的驱动电压驱动原边绕组产生周期性的第一电压和第二电压。这样在控制晶体管和电容相结合的方式下，可使原边绕组产生周期性的第一电压和第二电压。
在一种可能的实现方式中，作为电压控制电路的一个实施方式，电压控制电路包括两个控制晶体管和一个第一电容，这两个控制晶体管分别为第一控制晶体管和第二控制晶体管。则所需的控制脉冲信号也为两个，且这两个控制脉冲信号分别为第一控制脉冲信号和第二控制脉冲信号。其中，第一控制晶体管的控制电极用于接收第一控制脉冲信号，第一控制晶体管的第一电极与驱动电压源的正极连接，第一控制晶体管的第二电极与第二控制晶体管的第一电极连接，第二控制晶体管的控制电极用于接收第二控制脉冲信号，第二控制晶体管的第二电极与驱动电压源的负极连接。第一电容的第一电极分别与第一控制晶体管的第一级和驱动电压源的正极连接，第一电容的第二电极与原边绕组的第一端连接，以使第一电容与原边绕组串联连接。原边绕组的第二端分别与第一控制晶体管的第二电极和第二控制晶体管的第一级连接。这样可以尽可能的简化电压控制电路的结构。需要说明的是，上述仅是以电压控制电路包括两个控制晶体管和一个第一电容为例进行说明的。在实际应用中，电压控制电路内的控制晶体管的数量与第一电容的数量，可以根据实际应用的需求进行确定，在此不作限定。
在一种可能的实现方式中，充放电控制电路也可以采用辅助晶体管和电容相结合的方式实现。示例性地，充放电控制电路包括多个辅助晶体管和第二电容。多个辅助晶体管、第二电容、第一副边绕组以及主晶体管的控制电极串联连接。在实际工作时，也需要对辅助晶体管的控制电极加载相应的控制信号，控制这些辅助晶体管相互协调工作，从而实现控制主晶体管的控制电极实现充放电。示例性地，可以采用微控制单元(Microcontroller Unit，MCU)对辅助晶体管的控制电极加载相应的控制信号，或者也可以采用额外的栅极驱动电路对辅助晶体管的控制电极加载相应的控制信号。然而，这些均会提高驱动电路的复杂性并增加IO接口资源占用的问题。为了降低驱动电路的复杂性且减少IO接口资源占用，本申请实施例在充放电控制电路中设置了自驱动电路，该自驱动电路分别与第一副边绕组的第一端和第二端以及上述多个辅助晶体管的控制电极耦接。具体地，该自驱动电路用于根据对应连接的第一副边绕组耦合产生的第一感应电动势和第二感应电动势，控制多个辅助晶体管中的一部分辅助晶体管导通，另一部辅助晶体管关断。这样通过设置自驱动电路，控制辅助晶体管的导通和关断，可以不用额外的设置MCU或栅极驱动电路，从而降低驱动电路的复杂性且减少IO接口资源占用的问题。
在一种可能的实现方式中，第二电容的两个电极板之间的电压为第二电压，第二电容中的第二电压可以结合第一副边绕组耦合产生的第一感应电动势和第二感应电动势，控制主晶体管的控制电极快速充放电。
在一种可能的实现方式中，作为充放电控制电路的一个实施方式，充放电控制电路包括两个辅助晶体管、一个第二电容以及一个自驱动电路。这两个辅助晶体管分别为第一辅助晶体管和第二辅助晶体管。其中，第一辅助晶体管、第二辅助晶体管、第二电容、第一副边绕组以及主晶体管的控制电极串联连接。具体地，第二电容的第一电极与主晶体管的第一电极连接，第二电容的第二电极与第一辅助晶体管的第一电极连接，第一辅助晶体管的第二电极与第一副边绕组的第一端连接，第二辅助晶体管的第一电极与第一副边绕组的 第二端连接，第二辅助晶体管的第二电极与主晶体管的控制电极连接。并且，自驱动电路与第一辅助晶体管和第二辅助晶体管的控制电极耦接。并且，自驱动电路包括：第一子驱动电路和第二子驱动电路。第一子驱动电路与第一辅助晶体管的控制电极连接，第二子驱动电路与第二辅助晶体管的控制电极连接。其中，第一子驱动电路的第一端与第一辅助晶体管的控制电极连接，第一子驱动电路的第二端与对应的第一副边绕组的第一端连接，第一子驱动电路的第三端与对应的第一副边绕组的第二端连接。第二子驱动电路的第一端与第二辅助晶体管的控制电极连接，第二子驱动电路的第二端与对应的第一副边绕组的第二端连接，第二子驱动电路的第三端与对应的第一副边绕组的第一端连接。以及，第一子驱动电路用于根据连接的第一副边绕组耦合产生的第一感应电动势和第二感应电动势，控制第一辅助晶体管导通和关断。第二子驱动电路用于根据连接的第一副边绕组耦合产生的第一感应电动势和第二感应电动势，控制第二辅助晶体管导通和关断。
在一种可能的实现方式中，作为第一子驱动电路的一个实施方式，第一子驱动电路包括：第一二极管、第一电阻以及第二电阻。其中，第一电阻的第一端为第一子驱动电路的第一端，第二电阻的第一端为第一子驱动电路的第二端，第一二极管的正极为第一子驱动电路的第三端，且第一二极管的负极分别与第一电阻的第二端和第二电阻的第二端连接。这样可以仅需采用第一二极管、第一电阻以及第二电阻，即可实现第一子驱动电路的功能，降低第一子驱动电路的复杂性，降低驱动电路的复杂性。
在一种可能的实现方式中，作为第二子驱动电路的一个实施方式，第二子驱动电路包括：第二二极管、第三电阻以及第四电阻。其中，第三电阻的第一端为第二子驱动电路的第一端，第四电阻的第一端为第二子驱动电路的第二端，第二二极管的正极为第二子驱动电路的第三端，且第二二极管的负极分别与第三电阻的第二端和第四电阻的第二端连接。这样可以仅需采用第二二极管、第三电阻以及第四电阻，即可实现第二子驱动电路的功能，降低第二子驱动电路的复杂性，降低驱动电路的复杂性。
在本申请一些实施例中，为了保持对第一辅助晶体管和第二辅助晶体管的控制统一性，第一二极管和第二二极管的管压降相同。示例性地，第一二极管和第二二极管为低管压降的二极管。可选地，第一二极管和第二二极管的管压降的范围为0.2V～0.4V。例如，第一二极管和第二二极管的管压降为0.2V、0.3V以及0.4V中的一个。当然，在实际应用中，第一二极管和第二二极管的管压降，可以根据实际应用环境来确定，在此不作限定。
在本申请一些实施例中，第一电阻至第四电阻是用于调节第一辅助晶体管和第二辅助晶体管的充放电速度的电阻。示例性地，为了保持第一辅助晶体管和第二辅助晶体管的充放电速度统一，可以使第一电阻至第四电阻的电阻值相同。当然，在实际应用中，第一电阻至第四电阻的电阻值，可以根据实际应用环境来确定，在此不作限定。
在本申请一些实施例中，在无需隔离的应用场景中，本申请实施例提供的驱动电路可以设置为非隔离型驱动电路，这样可以降低驱动电路中所使用的器件，提高驱动电路的简洁性。示例性地，对于N个主晶体管中，串联连接于接地端的M个主晶体管，将M个主晶体管定义为依次串联的第1主晶体管至第M主晶体管；其中，第1主晶体管直接与接地端连接，第1主晶体管对应的第二电容的第二电极还与原边绕组的第一端连接。例如，对于一个主晶体管，该主晶体管的第一电极与接地端连接，则该主晶体管对于的第二电容的第二电极还与原边绕组的第一端连接。这可以通过原边绕组为第二电容提供第二电压，使第二电压作为充放电控制电路的基准电压，从而可以结合第一副边绕组耦合产生的第一感 应电动势和第二感应电动势，实现对该主晶体管的控制电极快速进行充放电的效果。
在本申请一些实施例中，在无需隔离的应用场景中，本申请实施例提供的驱动电路可以设置为非隔离型驱动电路，这样可以降低驱动电路中所使用的器件，提高驱动电路的简洁性。示例性地，第M主晶体管对应的充放电控制电路还包括第一自举二极管；其中，第M主晶体管对应的充放电控制电路中，第一自举二极管的负极与第二电容的第二电极连接；并且，第M主晶体管对应的充放电控制电路中的第一自举二极管的正极，与第m-1主晶体管对应的充放电控制电路中的第二电容的第二电极连接；2≤m≤M，2≤M≤N，m和M均为整数。示例性地，在对于串联连接于接地端的两个主晶体管：第1主晶体管和第2主晶体管，第1主晶体管对应的第二电容的第二电极还与原边绕组的第一端连接。并且，第2主晶体管连接的充放电控制电路还包括第一自举二极管，该第一自举二极管的负极与第2主晶体管对应的第二电容的第二电极连接，该第一自举二极管的正极与第1主晶体管对应的第二电容的第二电极连接。由此，通过第2主晶体管对应的第一自举二极管和第二电容形成简单的自举电路，以通过该自举电路将基准电压供给至高位主晶体管，即第2主晶体管。
在本申请一些实施例中，在需要隔离的应用场景中，本申请实施例提供的驱动电路204也可以设置为隔离型驱动电路。示例性地，为了给隔离型驱动电路的副边提供一个基准电压，可以在耦合电路中设置第二副边绕组，在驱动电路中设置储能电容和第二自举二极管。其中，原边绕组和第二副边绕组之间互相耦合，并处于紧耦合状态，且第二副边绕组的第一端和原边绕组的第一端为同名端。这样使得第二副边绕组能够根据第一电压耦合产生第一感应电动势，以及根据第二电压耦合产生第二感应电动势。并且，第二自举二极管的正极与第二副边绕组的第一端连接，第二自举二极管的负极与储能电容的第一电极连接。储能电容的第二电极分别与第二副边绕组的第二端以及接地端连接。第二电容的第二电极还与储能电容的第一电极连接。这样通过第二副边绕组、储能电容和第二自举二极管的相互配合，能够组成峰值保持电路，从而在隔离型驱动器的副边形成一个隔离的基准电压直流电压源，以使第二电容的两端电压为第二电压。
在本申请一些实施例中，在隔离型驱动电路中，对于N个主晶体管中，串联连接于接地端的K个主晶体管，将K个主晶体管定义为依次串联的第1主晶体管至第K主晶体管；其中，第1主晶体管直接与接地端连接，第1主晶体管对应的第二电容的第二电极还与储能电容的第一电极连接。并且，第k主晶体管对应的充放电控制电路还包括第三自举二极管；其中，第k主晶体管对应的充放电控制电路中，第三自举二极管的负极与第二电容的第二电极连接；并且，第k主晶体管对应的充放电控制电路中的第三自举二极管的正极，与第k-1主晶体管对应的充放电控制电路中的第二电容的第二电极连接；2≤k≤K，2≤K≤N，k和K均为整数。示例性地，在对于串联连接于接地端的两个主晶体管：第1主晶体管和第2主晶体管，第1主晶体管对应的第二电容的第二电极还与储能电容的第一电极连接。并且，第2主晶体管连接的充放电控制电路还包括第三自举二极管，该第三自举二极管的负极与第2主晶体管对应的第二电容的第二电极连接，该第三自举二极管的正极与第1主晶体管对应的第二电容的第二电极连接。由此，通过第2主晶体管对应的第三自举二极管和第二电容形成简单的自举电路，以通过该自举电路将基准电压供给至高位主晶体管，即第2主晶体管。
在本申请一些实施例中，在驱动电路驱动多个主晶体管时，可以使这些主晶体管的驱 动逻辑相同，即控制这些主晶体管同时导通和关断，则原边绕组的第一端和这些主晶体管对应的第一副边绕组的第一端为同名端。
在本申请一些实施例中，在驱动电路驱动多个主晶体管时，可以使第一部分主晶体管的驱动逻辑相同，第二部分主晶体管的驱动逻辑相同，且第一部分主晶体管的驱动逻辑和第二部分主晶体管的驱动逻辑相反，即控制第一部分主晶体管同时导通和关断，第二部分主晶体管同时导通和关断，且第一部分主晶体管和第二部分主晶体管分时导通和关断。则原边绕组的第一端和第一部分主晶体管对应的第一副边绕组的第一端为同名端，原边绕组的第一端和第二部分主晶体管对应的第一副边绕组的第一端为异名端。
需要说明的是，本申请实施例中，电压控制电路中的控制晶体管和充放电控制电路中的辅助晶体管为金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)，则其控制电极为栅电极。并且，可以根据在实际工作中，控制晶体管和辅助晶体管的电流的流向，将其第一电极为源电极，第二电极为漏电极，或者，将其第一电极为漏电极，第二电极为源电极。
第二方面，本申请实施例还提供一种电源模块，该电源模块可以包括转换电路以及如上述第一方面中任一项所提供的驱动电路。其中，驱动电路用于驱动转换电路中的主晶体管。示例性地，该电源模块既可以是直流-直流电源模块，也可以是交流-直流电源模块。上述电源模块可以应用于不同类型的电子设备中，如智能手机、智能电视、笔记本电脑、掌上电脑(personal digital assistant，PDA)、具备无线通讯功能的可穿戴设备(如智能手表、智能眼镜、智能手环)、车载设备或数据中心等。第二方面中相应方案的技术效果可以参照第一方面中对应方案可以得到的技术效果，重复之处不予详述。
第三方面，本申请实施例还提供一种电子设备，该电子设备可以包括如上述第二方面中任一项提供的电源模块及负载模块。其中，电源模块与负载模块电性连接，以为负载模块提供直流电压。第三方面中相应方案的技术效果可以参照第一方面中对应方案可以得到的技术效果，重复之处不予详述。
第四方面，本申请实施例还提供一种驱动电路的控制方法，该方法可以用于控制第一方面中任一项所提供的驱动电路。示例性的，该控制方法可以应用于第二方面中任一项所提供的电源模块中的驱动电路。第四方面中相应方案的技术效果可以参照第一方面或第二方面中对应方案可以得到的技术效果，重复之处不予详述。
在本申请一些实施例中，本申请实施例所提供的控制方法包括：
首先，对电压控制电路加载多个控制脉冲信号，且该多个控制脉冲信号中的第一部分控制脉冲信号为无效电平，第二部分控制脉冲信号为有效电平，控制电压控制电路控制流经原边绕组的电流正向增加至正向电流最大值，并驱动原边绕组产生第二电压，N个第一副边绕组中的至少一个第一副边绕组根据第二电压耦合产生第二感应电动势，N个充放电控制电路中的至少一个充放电控制电路根据对应连接的第一副边绕组耦合产生的第二感应电动势，控制对应连接的主晶体管的控制电极进行充电或放电。
示例性地，以驱动电路驱动一个主晶体管，驱动电压源的电压为+VCC为例，第一控制脉冲信号加载无效电平，第一控制晶体管关断。第二控制脉冲信号加载有效电平，第二控制晶体管导通。原边绕组的电流的电流方向为由第一端流向第二端至驱动电压源的负极(即接地端)，并正向线性增长至正向电流最大值，且原边绕组两端的电压为+VCC/2，以及使第一副边绕组的第二感应电动势的电压同步被耦合至+VCC/2。由于第一子驱动电路中 第一二极管、第一电阻以及第二电阻的相互作用，控制第一辅助晶体管关断。且由于第二子驱动电路中第二二极管、第三电阻以及第四电阻的相互作用，控制第二辅助晶体管导通，从而使主晶体管的放电路径(该放电路径为：主晶体管的控制电极→导通的第二辅助晶体管→第一副边绕组→第一辅助晶体管的本体二极管→第二电容→驱动电压源的负极(即接地端))导通，主晶体管的控制电极上的电压放电，以使主晶体管的控制电极上的电压降为0V。
之后，对电压控制电路加载多个控制脉冲信号，且该多个控制脉冲信号均为无效电平，控制电压控制电路控制流经原边绕组的电流由正向电流最大值变化为零，并驱动原边绕组产生第一电压，N个第一副边绕组中的至少一个第一副边绕组根据第一电压耦合产生第一感应电动势，N个充放电控制电路中的至少一个充放电控制电路根据对应连接的第一副边绕组耦合产生的第一感应电动势，控制对应连接的主晶体管的控制电极进行充电或放电。
示例性地，以驱动电路驱动一个主晶体管，驱动电压源的电压为+VCC为例，第一控制脉冲信号加载无效电平，第一控制晶体管关断。第二控制脉冲信号加载无效电平，第二控制晶体管关断。则第一控制晶体管的本体二极管导通，原边绕组的电流的电流方向为由第一端流向第二端至驱动电压源的正极，且原边绕组的电流的电流可以看作定值。以及，原边绕组两端的电压变为-VCC/2，并使第一副边绕组的第一感应电动势的电压同步被耦合至-VCC/2。由于第二子驱动电路中第二二极管、第三电阻以及第四电阻的相互作用，控制第二辅助晶体管关断。且由于第一子驱动电路中第一二极管、第一电阻以及第二电阻的相互作用，控制第一辅助晶体管导通，从而使主晶体管的充电路径(该充电路径为：第二电容→导通的第一辅助晶体管→第一副边绕组→第二辅助晶体管的本体二极管→主晶体管的控制电极)导通，这样可以通过第一副边绕组耦合的-VCC/2和第二电容两端的电压+VCC/2，使主晶体管的控制电极上的电压迅速充电至，即可控制主晶体管导通。
以及，第一控制晶体管的本体二极管导通续流，原边绕组的电流的电流方向为由第一端流向第二端至驱动电压源的正极，以将原边绕组中的能量充入驱动电压源，并使电流由正向电流最大值线性降低至0。这样即可实现原边绕组的断流。并且，原边绕组两端的电压仍为-VCC/2，并使第一副边绕组的第一感应电动势的电压同步被耦合至-VCC/2。由于第二子驱动电路中第二二极管、第三电阻以及第四电阻的相互作用，控制第二辅助晶体管关断。且由于第一子驱动电路中第一二极管、第一电阻以及第二电阻的相互作用，控制第一辅助晶体管导通，从而使主晶体管的充电路径继续导通，使主晶体管的控制电极上的电压保持在+VCC，即可控制主晶体管保持导通。
之后，对电压控制电路加载多个控制脉冲信号，且该多个控制脉冲信号中的第一部分控制脉冲信号为有效电平，第二部分控制脉冲信号为无效电平，控制电压控制电路控制流经原边绕组的电流反向增加至反向电流最大值，并驱动原边绕组产生第一电压，N个第一副边绕组中的至少一个第一副边绕组根据第一电压耦合产生第一感应电动势，N个充放电控制电路中的至少一个充放电控制电路根据对应连接的第一副边绕组耦合产生的第一感应电动势，控制对应连接的主晶体管的控制电极进行充电或放电。
示例性地，以驱动电路驱动一个主晶体管，驱动电压源的电压为+VCC为例，第一控制脉冲信号加载有效电平，第一控制晶体管导通。第二控制脉冲信号加载无效电平，第二控制晶体管关断。原边绕组的电流的电流方向为由驱动电压源的正极流向第二端至第一端，并反向线性增长至反向电流最大值，且原边绕组两端的电压为-VCC/2，并使第一副边绕组 的第一感应电动势的电压同步被耦合至-VCC/2。由于第二子驱动电路中第二二极管、第三电阻以及第四电阻的相互作用，控制第二辅助晶体管关断。且由于第一子驱动电路中第一二极管、第一电阻以及第二电阻的相互作用，控制第一辅助晶体管导通，从而使主晶体管的充电路径继续导通，这样可以使主晶体管的控制电极充入少量电压，以使主晶体管的控制电极的电压略微高于+VCC。这样是为了实现电荷平衡。并且，在实际应用中，充入的这些少量电压并不会对主晶体管的导通和关断造成不利影响。
之后，对电压控制电路加载多个控制脉冲信号，且该多个控制脉冲信号均为无效电平，控制电压控制电路控制流经原边绕组的电流由反向电流最大值变化为零，并驱动原边绕组产生第二电压，N个第一副边绕组中的至少一个第一副边绕组根据第二电压耦合产生第二感应电动势，N个充放电控制电路中的至少一个充放电控制电路根据对应连接的第一副边绕组耦合产生的第二感应电动势，控制对应连接的主晶体管的控制电极进行充电或放电。
示例性地，以驱动电路驱动一个主晶体管，驱动电压源的电压为+VCC为例，第一控制脉冲信号加载无效电平，第一控制晶体管关断。第二控制脉冲信号加载无效电平，第二控制晶体管关断。则第二控制晶体管的本体二极管导通，原边绕组的电流的电流方向为由驱动电压源的负极流向第二端至第一端，且原边绕组的电流的电流可以看作定值。以及，原边绕组两端的电压变为+VCC/2，并使第一副边绕组的第二感应电动势的电压同步被耦合至+VCC/2。由于第一子驱动电路中第一二极管、第一电阻以及第二电阻的相互作用，控制第一辅助晶体管关断。且由于第二子驱动电路中第二二极管、第三电阻以及第四电阻的相互作用，控制第二辅助晶体管导通，从而使主晶体管的放电路径(该放电路径为：主晶体管的控制电极→导通的第二辅助晶体管→第一副边绕组→第一辅助晶体管的本体二极管→第二电容→驱动电压源的负极(即接地端))导通，主晶体管的控制电极上的电压放电，以使主晶体管的控制电极上的电压迅速降为0V，即可控制主晶体管关断。
以及，第二控制晶体管的本体二极管导通续流，原边绕组的电流的电流方向为由第二端流向第一端至第一电容，以将原边绕组中的能量充入第一电容，并使电流由反向电流最大值线性升至0。这样即可实现原边绕组的断流。以及，原边绕组两端的电压变为+VCC/2，并使第一副边绕组的第二感应电动势的电压同步被耦合至+VCC/2。由于第一子驱动电路中第一二极管、第一电阻以及第二电阻的相互作用，控制第一辅助晶体管关断。且由于第二子驱动电路中第二二极管、第三电阻以及第四电阻的相互作用，控制第二辅助晶体管导通，从而使主晶体管的放电路径继续导通，使主晶体管的控制电极上的电压保持在0V。
附图说明
图1为本申请实施例提供的电子设备的结构示意图；
图2为相关技术中的电感型谐振驱动器的一些结构示意图；
图3为图2所示的电感型谐振驱动器的信号时序图；
图4为相关技术中的变压器型谐振驱动器的一些结构示意图；
图5为图4所示的变压器型谐振驱动器的信号时序图；
图6为本申请一种实施例提供的驱动电路的结构示意图；
图7为本申请一种实施例提供的驱动电路的具体结构示意图；
图8为本申请又一种实施例提供的驱动电路的具体结构示意图；
图9为图8所示的驱动电路对应的信号时序图；
图10为本申请另一种实施例提供的驱动电路的结构示意图；
图11为图10所示的驱动电路对应的信号时序图；
图12为本申请又一种实施例提供的驱动电路的结构示意图；
图13为图12所示的驱动电路对应的信号时序图；
图14为本申请又一种实施例提供的驱动电路的结构示意图；
图15为本申请又一种实施例提供的驱动电路的结构示意图；
图16为图15所示的驱动电路对应的信号时序图；
图17为本申请又一种实施例提供的驱动电路的结构示意图；
图18为图17所示的驱动电路对应的信号时序图；
图19为本申请一种实施例提供的LLC谐振转换器的结构示意图；
图20为本申请另一种实施例提供的LLC谐振转换器的结构示意图；
图21为本申请实施例提供的仿真模拟的波形示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。方法实施例中的具体操作方法也可以应用于装置实施例或系统实施例中。需要说明的是，在本申请的描述中“至少一个”是指一个或多个，其中，多个是指两个或两个以上。鉴于此，本申请实施例中也可以将“多个”理解为“至少两个”。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，字符“/”，如无特殊说明，一般表示前后关联对象是一种“或”的关系。另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
需要指出的是，本申请实施例中“连接”指的是电连接，两个电学元件连接可以是两个电学元件之间的直接或间接连接。例如，A与B连接，既可以是A与B直接连接，也可以是A与B之间通过一个或多个其它电学元件间接连接，例如A与B连接，也可以是A与C直接连接，C与B直接连接，A与B之间通过C实现了连接。本申请实施例中，“耦合”可以指两个绕组之间通过电磁场耦合，即两个绕组之间可以通过电磁场传输电能，主要包括了电能-磁场势能-电能的能量转化过程。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。
图1为本申请实施例提供的电子设备的结构示意图。参照图1，本申请实施例提供的电子设备01包括电源模块011及负载模块012，电源模块011与负载模块012电性连接。示例性地，电子设备01可以是任何用电设备。例如，智能手机、智能电视、笔记本电脑、掌上电脑(personal digital assistant，PDA)、具备无线通讯功能的可穿戴设备(如智能手表、智能眼镜、智能手环)、车载设备或数据中心等。应注意的是，本申请对电子设备的具体类型不作任何限定。
在一些实施例中，电源模块011可以为DC-DC电源模块，用于将直流电进行升压或降压变化处理后输出直流电。例如，电源模块011可将电源02输出的直流电(例如48V)变换为用于所有类型负载模块012的直流电，并输出至负载模块012，以供负载模块012 工作。本申请对电源02及负载模块012不作任何限制，电源02可以是任何能输出直流电的设备或元件，例如，电源02可以是电池，则电源模块011可以接收电池提供的电池电压，并将电池电压转换为负载模块012的工作电压后，输出给负载模块012。负载模块012可以是任何使用直流电的功能模块，例如负载模块012可以是处理器、芯片等。当然，电源模块也可以为交流(Alternating Current，AC)-DC电源模块，用于将交流电进行升压或降压变化处理后输出直流电。
参照图1，电源模块011包括转换电路0111和驱动电路0112。具体工作时，驱动电路0112用于驱动转换电路0111中的开关管工作在一定的开关频率下，使转换电路0111将电源02的电压，进行升压或降压变化处理后，输出为负载模块012提供工作电压的直流电。示例性地，电源模块011为DC-DC电源模块时，转换电路0111可以为DC-DC转换器，例如Buck(降压式)转换器、Boost(升压式)转换器、半桥转换器、全桥转换器和电感-电感-电容(inductor-inductor-capacitor，LLC)谐振转换器等。可选地，转换电路0111中的开关管可为MOSFET，驱动电路0112与MOSFET的控制电极连接，从而通过控制MOSFET的导通和关断，使转换电路0111实现电压转换。
随着电力电子技术的不断发展，电力电子设备高频化、小型化已经是一个众所周知的大趋势。为了达到更高的功率密度，通常采用提高开关管的开关频率的方法，来减小DC-DC转换器中的电容、电感、变压器等磁性元件的体积。在实际应用中，通过设计驱动电路的具体结构可以实现控制开关管的开关频率。通常，驱动电路可以采用非隔离型的电感型谐振驱动器或隔离型的变压器型谐振驱动器等结构。
图2为相关技术中的电感型谐振驱动器的一些结构示意图。参照图2，以DC-DC转换器中一个开关管Q011为例，电感型谐振驱动器0101包括：四个辅助控制晶体管S011～S014、电感Lr011以及储能电容Cs011。其中，VD为驱动电压源，为开关管Q011的控制电极提供驱动电压。在实际工作时，通过对四个辅助控制晶体管S011～S014的控制电极加载相应的控制信号，实现开关管Q011的控制电极充放电等过程。并且，电感型谐振驱动器0101在保证开关管Q011的控制电极充电电流(即开关管Q011导通速度)的前提下，实现电感Lr011电流断流，降低电感型谐振驱动器0101中电流有效值，将附加驱动损耗降至较低水平。需要说明的是，电感型谐振驱动器0101中的各器件的具体连接关系可以参照图2，在此不作赘述。
图3为图2所示的电感型谐振驱动器的信号时序图。参照图3，SS011代表辅助控制晶体管S011的控制电极加载的控制信号，SS012代表辅助控制晶体管S012的控制电极加载的控制信号，SS013代表辅助控制晶体管S013的控制电极加载的控制信号，SS014代表辅助控制晶体管S014的控制电极加载的控制信号，ILr011代表流经电感Lr011的电流，IGQ011代表开关管Q011的控制电极电流，VGQ011代表开关管Q011的控制电极电压。在图2所示的电感型谐振驱动器0101，结合图3所示的信号时序图，进行工作的具体工作过程，可以与相关技术中的基本相同，在此不作赘述。
在实际工作时，控制信号SS011和SS012逻辑互补，并留有一定的死区时间，死区时间为开关管Q011的控制电极的充电时间。电感Lr011的电流ILr011为断续型电流，可使电感Lr011上的导通损耗最小化。虽然，电感型谐振驱动器0101可以使电感Lr011上的导通损耗最小化，但是其还存在以下几个显著的缺点：
(1)所需元器件数量多：在该方案中，驱动1个开关管时，需要4个辅助控制晶体 管，对于多级转换器或全桥转换器等多个开关管的应用场合，则需要大量的辅助控制晶体管，不利于节约驱动电路成本和体积。
(2)占用IO接口资源多：在该方案中，需要严格控制该电感型谐振驱动器的充放电时间，这对辅助控制晶体管的IO接口资源和控制精度提出了较高的要求。同时，由于每个辅助控制晶体管的控制电极加载的控制信号的相位不相同，且控制信号SS011、SS012与控制信号SS013、SS014的占空比也不相同，在无MCU控制的场合，将难以提供精确的控制信号。
(3)不适用于隔离驱动场合：在该方案中，对单个开关管驱动所需的控制信号、驱动电压源等均为非隔离连接，不能直接应用于需要驱动信号和供电隔离的场合。
针对需要隔离的控制电极驱动场合，变压器型谐振驱动器则在系统简洁性上具备突出的优势。
图4为相关技术中的变压器型谐振驱动器的一些结构示意图。参照图4，以驱动Buck转换器0102中的控制开关管和同步开关管为例，Buck转换器0102还包括电容C0、电感Lf0。其中，Q021是Buck转换器0102中的控制开关管，Q022是buck转换器0102中的同步开关管。变压器型谐振驱动器0103包括：辅助控制晶体管S021～S024、变压器原边绕组Lr021、变压器副边绕组Lr022、隔直电容Cb021～Cb022、自举电容Cf021、自举二极管Df021。变压器原边绕组Lr021和变压器副边绕组Lr022为紧耦合状态。VD2和VD3为驱动电压源。需要说明的是，Buck转换器0102中的各器件的具体连接关系和变压器型谐振驱动器0103中的各器件的具体连接关系可以参照图4，在此不作赘述。
图5为图4所示的变压器型谐振驱动器的信号时序图。参照图5，SS021代表辅助控制晶体管S021的控制电极加载的控制信号，SS022代表辅助控制晶体管S022的控制电极加载的控制信号，SS023代表辅助控制晶体管S023的控制电极加载的控制信号，SS024代表辅助控制晶体管S024的控制电极加载的控制信号，ILr021代表流经变压器原边绕组Lr021的电流，ILr022代表流经变压器副边绕组Lr022的电流，IGQ021代表控制开关管Q021的控制电极电流，IGQ022代表同步开关管Q022的控制电极电流，VGQ021代表控制开关管Q021的控制电极电压，VGQ022代表同步开关管Q022的控制电极电压。在图4所示的变压器型谐振驱动器0103，结合图5所示的信号时序图，进行工作时的具体工作过程，可以与相关技术中的基本相同，在此不作赘述。
在实际工作时，控制信号SS021和SS022逻辑互补，并留有一定的死区时间。控制信号SS023和SS024逻辑互补，并留有一定的死区时间。该方案中，自举电容Cf021、自举二极管Df021构成了自举电路，结合驱动电压源VD2，为高位控制开关管Q021提供驱动电压。虽然，上述变压器型谐振驱动器0103在驱动两个开关管时，减少了辅助控制晶体管的数量和控制难度。但是其还存在以下几个显著的缺点：
(1)变压器感量大：在该方案中，所采用的由变压器原边绕组和变压器副边绕组形成的变压器，在1MHz条件下感量为1.2uH，限制了变压器体积的进一步减小。
(2)变压器损耗大：在该方案中，变压器原边绕组和变压器副边绕组中的电流均为连续型电流，与上述的电感器型谐振驱动器方案相比，该方案增加了变压器绕组的损耗。
(3)占用IO接口资源多：在该方案中，与上述的电感器型谐振驱动器方案相比，虽然使得IO接口资源占用量较少，但该方案中，驱动两个开关管，仍需要四个IO接口驱动信号。
基于此，本申请实施例提供了一种驱动电路，该驱动电路为变压器型谐振驱动器，且该驱动电路中原边绕组的电流为断续性电流，可以使原边绕组上的导通损耗最小化，降低驱动损耗。并且通过原边绕组和副边绕组的相互耦合，可以实现变压器型谐振驱动器的功能，从而使得本申请实施例提供的驱动电路，既可以具有电感型谐振驱动器的断续性电流的优点，又可以具有变压器型谐振驱动器的简洁型。以及，本申请实施例提供的驱动电路，还可以将原边绕组中储存的多余能量回收至驱动电压源中，从而实现无损驱动。
下文将详细阐述本申请的各个实施例。
本申请中的驱动电路可以驱动一个或多个主晶体管。即N＝1、2、3、4或更多。并且，N的具体数值，可以根据实际应用的需求进行确定，在此不作限定。
在本申请一些实施例中，本申请提供的驱动电路所驱动的主晶体管为上述转换电路中的开关管。示例性地，本申请提供的驱动电路驱动的主晶体管为降压式(Buck)转换器、升压式(Boost)转换器、半桥转换器、全桥转换器或电感-电感-电容(inductor-inductor-capacitor，LLC)谐振转换器中的至少一种转换器中的开关管。可选地，可使一个驱动电路驱动一个转换电路。或者，也可使一个驱动电路驱动两个、三个或多个转换电路。在实际应用中，驱动电路与转换电路之间的驱动对应关系，可以根据实际应用的需求确定，在此不作限定。
图6为本申请一种实施例提供的驱动电路的结构示意图。并且，图6中以驱动一个主晶体管Qs为例进行示意。参照图6，主晶体管Qs的控制电极与驱动电路201连接，主晶体管Qs的第一电极与接地端连接，主晶体管Qs的第二电极可以与转换电路中的其他器件连接(图6中未示出主晶体管Qs的第二电极的具体连接方式)。
参照图6，驱动电路201包括：电压控制电路2011、耦合电路2012以及一个充放电控制电路2013；其中，耦合电路2012包括原边绕组LP和一个第一副边绕组LS1，原边绕组LP和第一副边绕组LS1之间互相耦合，且处于紧耦合状态。以及，原边绕组LP的第一端和第一副边绕组LS1的第一端为同名端。以及，电压控制电路2011与原边绕组LP连接，第一副边绕组LS1与充放电控制电路2013对应连接，充放电控制电路2013与主晶体管Qs的控制电极对应连接。其中，电压控制电路2011用于响应于多个控制脉冲信号，驱动原边绕组LP产生周期性的第一电压和第二电压，并且，第一副边绕组LS1根据第一电压耦合产生第一感应电动势，根据第二电压耦合产生第二感应电动势。并且，充放电控制电路2013用于根据耦合到第一副边绕组LS1的第一感应电动势和第二感应电动势，控制主晶体管Qs的控制电极进行充放电，以控制主晶体管Qs导通和关断。
在本申请一些实施例中，电压控制电路2011可以采用控制晶体管和电容相结合的方式实现，且一个控制晶体管对应加载一个控制脉冲信号。在实际工作时，电压控制电路2011内的控制晶体管响应于加载的控制脉冲信号，相互结合工作，以根据驱动电压源的驱动电压产生周期性的第一电压和第二电压。示例性地，控制脉冲信号为周期性出现有效电平的信号，且相邻两个有效电平之间为无效电平。控制脉冲信号的有效电平可以控制电压控制电路2011内的控制晶体管导通，无效电平可以控制电压控制电路2011内的控制晶体管关断。并且，控制脉冲信号的一个周期为一个有效电平的维持时长与一个无效电平的维持时长之和。控制脉冲信号的有效电平在一个周期中的占空比为：有效电平的维持时长与一个周期的时长的比值。在本申请实施例中，控制脉冲信号的有效电平在一个周期中的占空比的范围为4％～30％。结合图5，相关技术中控制信号SS021～SS022的占空比通常在45％～60％ 之间，这样使得变压器型谐振驱动器0103通常都是通过长脉冲(即有效电平的维持时长较长)进行驱动的，导致变压器型谐振驱动器0103中变压器原边绕组和副边绕组的电流是长时间存在的。而，本申请实施例提供的驱动电路，通过将控制脉冲信号的有效电平在一个周期中的占空比的范围设置为4％～30％，可使控制脉冲信号实现短脉冲(即有效电平的维持时长较短)形式，从而控制电压控制电路2011中的控制晶体管能够快速导通和关断，进而实现快速驱动主晶体管的控制电极充放电，并在快速驱动主晶体管的控制电极充放电后，实现原边绕组和副边绕组断流效果，使原边绕组上的导通损耗最小化，降低驱动损耗。
在本申请实施例中，控制脉冲信号的有效电平在一个周期中的占空比可以根据主晶体管Qs的开关频率进行设置。示例性地，主晶体管Qs的开关频率设置为1MHz，控制脉冲信号的有效电平在一个周期中的占空比的范围为1/21～1/6。具体地，控制脉冲信号的有效电平每1000ns出现一次，且该有效电平的维持时长为50ns～200ns。例如，有效电平的维持时长为50ns、80ns、100ns、130ns、150ns、180ns、200ns中的一个。当然，在实际应用中，该有效电平的维持时长可以根据实际应用的需求进行确定，在此不作限定。
示例性地，主晶体管Qs的开关频率也可以设置为2MHz，控制脉冲信号的有效电平在一个周期中的占空比的范围为1/11～2/7。具体地，控制脉冲信号的有效电平每500ns出现一次，且该有效电平的维持时长为50ns～200ns。例如，有效电平的维持时长为50ns、80ns、100ns、130ns、150ns、180ns、200ns中的一个。当然，在实际应用中，该有效电平的维持时长可以根据实际应用的需求进行确定，在此不作限定。
示例性地，主晶体管Qs的开关频率为1MHz时对应的有效电平与其开关频率为2MHz时对应的有效电平的维持时长相同。例如，主晶体管Qs的开关频率为1MHz时对应的有效电平与其开关频率为2MHz时对应的有效电平的维持时长可以均为50ns、80ns、100ns、130ns、150ns、180ns、200ns中的一个。这样可以统一不同开关频率下的有效电平的维持时长，降低控制难度。
图7为本申请一种实施例提供的驱动电路的具体结构示意图。参照图7，在本申请一些实施例中，电压控制电路2011包括两个控制晶体管和一个第一电容Cr，这两个控制晶体管分别为第一控制晶体管P1和第二控制晶体管P2。则所需的控制脉冲信号也为两个，且这两个控制脉冲信号分别为第一控制脉冲信号PP1和第二控制脉冲信号PP2。其中，第一控制晶体管P1的控制电极用于接收第一控制脉冲信号PP1，第一控制晶体管P1的第一电极与驱动电压源VDC的正极连接，第一控制晶体管P1的第二电极与第二控制晶体管P2的第一电极连接，第二控制晶体管P2的控制电极用于接收第二控制脉冲信号PP2，第二控制晶体管P2的第二电极与驱动电压源VDC的负极连接。第一电容Cr的第一电极与驱动电压源VDC的正极连接，第一电容Cr的第二电极与原边绕组LP的第一端连接，以使第一电容Cr与原边绕组LP串联连接。原边绕组LP的第二端与第一控制晶体管P1的第二电极连接。这样可以尽可能的简化电压控制电路的结构。
需要说明的是，图7仅是以电压控制电路2011包括两个控制晶体管和一个第一电容Cr为例进行说明的。在实际应用中，电压控制电路2011内的控制晶体管的数量与第一电容Cr的数量，可以根据实际应用的需求进行确定，在此不作限定。
在本申请一些实施例中，充放电控制电路也可以采用辅助晶体管和电容相结合的方式实现。示例性地，充放电控制电路包括多个辅助晶体管和第二电容。多个辅助晶体管、第二电容、第一副边绕组以及主晶体管的控制电极串联连接。在实际工作时，也需要对辅助 晶体管的控制电极加载相应的控制信号，控制这些辅助晶体管相互协调工作，从而实现控制主晶体管的控制电极实现充放电。示例性地，可以采用MCU对辅助晶体管的控制电极加载相应的控制信号，或者也可以采用额外的栅极驱动电路对辅助晶体管的控制电极加载相应的控制信号。然而，这些均会提高驱动电路的复杂性并增加IO接口资源占用。为了降低驱动电路的复杂性且减少IO接口资源占用，参照图7，本申请实施例在充放电控制电路中设置了自驱动电路AC，该自驱动电路AC与第一副边绕组LS1的第一端和第二端以及辅助晶体管S1～S2的控制电极耦接。具体地，该自驱动电路用于根据对应连接的第一副边绕组耦合产生的第一感应电动势和第二感应电动势，控制多个辅助晶体管中的一部分辅助晶体管导通，另一部辅助晶体管关断。这样通过设置自驱动电路，控制辅助晶体管的导通和关断，可以不用额外的设置MCU或栅极驱动电路，从而降低驱动电路的复杂性且减少IO接口资源占用。
在本申请一些实施例中，第二电容的两个电极板之间的电压为第二电压，第二电容中的第二电压可以结合第一副边绕组LS1耦合产生的第一感应电动势和第二感应电动势，控制主晶体管Qs的控制电极快速充放电。
图8为本申请又一种实施例提供的驱动电路的具体结构示意图。参照图8，充放电控制电路2013包括两个辅助晶体管S1～S2、一个第二电容Ct以及一个自驱动电路AC。这两个辅助晶体管分别为第一辅助晶体管S1和第二辅助晶体管S2。其中，第一辅助晶体管S1、第二辅助晶体管S2、第二电容Ct、第一副边绕组LS1以及主晶体管Qs的控制电极串联连接。具体地，第二电容Ct的第一电极与主晶体管Qs的第一电极连接，第二电容Ct的第二电极与第一辅助晶体管S1的第一电极连接，第一辅助晶体管S1的第二电极与第一副边绕组LS1的第一端连接，第二辅助晶体管S2的第一电极与第一副边绕组LS1的第二端连接，第二辅助晶体管S2的第二电极与主晶体管Qs的控制电极连接。并且，自驱动电路与第一辅助晶体管S1和第二辅助晶体管S2的控制电极耦接。并且，自驱动电路AC包括：第一子驱动电路AC1和第二子驱动电路AC2。第一子驱动电路AC1与第一辅助晶体管S1的控制电极连接，第二子驱动电路AC2与第二辅助晶体管S2的控制电极连接。其中，第一子驱动电路AC1的第一端与第一辅助晶体管S1的控制电极连接，第一子驱动电路AC1的第二端与第一副边绕组LS1的第一端连接，第一子驱动电路AC1的第三端与第一副边绕组LS1的第二端连接。第二子驱动电路AC2的第一端与第二辅助晶体管S2的控制电极连接，第二子驱动电路AC2的第二端与第一副边绕组LS1的第二端连接，第二子驱动电路AC2的第三端与第一副边绕组LS1的第一端连接。以及，第一子驱动电路AC1用于根据连接的第一副边绕组LS1耦合产生的第一感应电动势和第二感应电动势，控制第一辅助晶体管S1导通和关断。第二子驱动电路AC2用于根据连接的第一副边绕组LS1耦合产生的第一感应电动势和第二感应电动势，控制第二辅助晶体管S2导通和关断。
参照图8，在本申请一些实施例中，第一子驱动电路AC1包括：第一二极管D1、第一电阻R1以及第二电阻R2。其中，第一电阻R1的第一端为第一子驱动电路AC1的第一端，第一电阻R1的第二端与第一二极管D1的负极连接。第二电阻R2的第一端为第一子驱动电路AC1的第二端，第二电阻R2的第二端与第一二极管D1的负极连接。第一二极管D1的正极为第一子驱动电路AC1的第三端。这样可以仅需采用第一二极管、第一电阻以及第二电阻，即可实现第一子驱动电路的功能，降低第一子驱动电路的复杂性，降低驱动电路的复杂性。
参照图8，在本申请一些实施例中，第二子驱动电路AC2包括：第二二极管D2、第三电阻R3以及第四电阻R4。其中，第三电阻R3的第一端为第二子驱动电路AC2的第一端，第三电阻R3的第二端与第二二极管D2的负极连接。第四电阻R4的第一端为第二子驱动电路AC2的第二端，第四电阻R4的第二端与第二二极管D2的负极连接。第二二极管D2的正极为第二子驱动电路AC2的第三端。这样可以仅需采用第二二极管、第三电阻以及第四电阻，即可实现第二子驱动电路的功能，降低第二子驱动电路的复杂性，降低驱动电路的复杂性。
在本申请一些实施例中，为了保持对第一辅助晶体管S1和第二辅助晶体管S2的控制统一性，第一二极管D1和第二二极管D2的管压降相同。示例性地，第一二极管D1和第二二极管D2为低管压降的二极管。可选地，第一二极管D1和第二二极管D2的管压降的范围为0.2V～0.4V。例如，第一二极管D1和第二二极管D2的管压降为0.2V、0.3V以及0.4V中的一个。当然，在实际应用中，第一二极管D1和第二二极管D2的管压降，可以根据实际应用环境来确定，在此不作限定。
在本申请一些实施例中，第一电阻至第四电阻R1～R4是用于调节第一辅助晶体管S1和第二辅助晶体管S2的充放电速度的电阻。示例性地，为了保持第一辅助晶体管S1和第二辅助晶体管S2的充放电速度统一，可以使第一电阻至第四电阻R1～R4的电阻值相同。当然，在实际应用中，第一电阻至第四电阻R1～R4的电阻值，可以根据实际应用环境来确定，在此不作限定。
在无需隔离的应用场景中，本申请实施例提供的驱动电路可以设置为非隔离型驱动电路，这样可以降低驱动电路中所使用的器件，提高驱动电路的简洁性。示例性地，参照图8，主晶体管Qs的第一电极与接地端连接，则第二电容Ct的第二电极还与原边绕组LP的第一端连接。这可以通过原边绕组LP为第二电容Ct提供第二电压，使第二电压作为充放电控制电路的基准电压，从而可以结合第一副边绕组LS1耦合产生的第一感应电动势和第二感应电动势，实现对主晶体管Qs的控制电极快速进行充放电的效果。
需要说明的是，本申请实施例中，电压控制电路中的控制晶体管和充放电控制电路中的辅助晶体管为MOSFET，则其控制电极为栅电极。并且，可以根据在实际工作中，控制晶体管和辅助晶体管的电流的流向，将其第一电极为源电极，第二电极为漏电极，或者，将其第一电极为漏电极，第二电极为源电极。
参照图9，图9为图8所示的驱动电路对应的信号时序图。其中，PP1代表加载到第一控制晶体管P1的控制电极上的第一控制脉冲信号，PP2代表加载到第二控制晶体管P2的控制电极上的第二控制脉冲信号，ULP代表原边绕组LP两端的电压，ILP代表原边绕组LP的电流，ULS1代表第一副边绕组LS1两端的感应电动势对应的电压，UGS1代表第一辅助晶体管S1的控制电极的电压，UGS2代表第二辅助晶体管S2的控制电极的电压，IGQs代表主晶体管Qs的控制电极的电流，UGQs代表主晶体管Qs的控制电极的电压。其中，以高电平脉冲为控制脉冲信号的有效电平，驱动电压源的驱动电压为+VCC为例。在第一控制脉冲信号PP1和第二控制脉冲信号PP2交替出现有效电平且占空比相等时，第二电容Ct两端的电压将稳定维持在+VCC/2。
参照图9，第一控制脉冲信号PP1和第二控制脉冲信号PP2的高电平脉冲的维持时长相同，并且，第一控制脉冲信号PP1和第二控制脉冲信号PP2的高电平脉冲之间具有死区时间，即第一控制脉冲信号PP1和第二控制脉冲信号PP2同时出现低电平脉冲时的时间段作为其死 区时间。
下面以图8所示的驱动电路的结构为例，结合图9所示的信号时序图，对本申请实施例提供的驱动电路的工作过程进行描述。其中，第一电压为-VCC/2，第二电压为+VCC/2为例。
在t0～t1阶段中，第一控制脉冲信号PP1加载无效电平(例如低电平)，第一控制晶体管P1关断。第二控制脉冲信号PP2加载有效电平(例如高电平)，第二控制晶体管P2导通。原边绕组LP的电流ILP的电流方向为由第一端流向第二端至驱动电压源的负极(即接地端)，并正向线性增长至正向电流最大值，且原边绕组LP两端的电压为+VCC/2，以及使第一副边绕组LS1的第二感应电动势的电压同步被耦合至+VCC/2。由于第一子驱动电路AC1中第一二极管D1、第一电阻R1以及第二电阻R2的相互作用，控制第一辅助晶体管S1关断。且由于第二子驱动电路AC2中第二二极管D2、第三电阻R3以及第四电阻R4的相互作用，控制第二辅助晶体管S2导通，从而使主晶体管Qs的放电路径(该放电路径为：主晶体管Qs的控制电极→导通的第二辅助晶体管S2→第一副边绕组LS1→第一辅助晶体管S1的本体二极管→第二电容Ct→驱动电压源VDC的负极(即接地端))导通，主晶体管Qs的控制电极上的电压放电，以使主晶体管Qs的控制电极上的电压降为0V。
在t1～t2阶段中，第一控制脉冲信号PP1加载无效电平(例如低电平)，第一控制晶体管P1关断。第二控制脉冲信号PP2加载无效电平(例如低电平)，第二控制晶体管P2关断。则第一控制晶体管P1的本体二极管导通，原边绕组LP的电流ILP的电流方向为由第一端流向第二端至驱动电压源的正极，且原边绕组LP的电流ILP的电流可以看作定值。以及，原边绕组LP两端的电压变为-VCC/2，并使第一副边绕组LS1的第一感应电动势的电压同步被耦合至-VCC/2。由于第二子驱动电路AC2中第二二极管D2、第三电阻R3以及第四电阻R4的相互作用，控制第二辅助晶体管S2关断。且由于第一子驱动电路AC1中第一二极管D1、第一电阻R1以及第二电阻R2的相互作用，控制第一辅助晶体管S1导通，从而使主晶体管Qs的充电路径(该充电路径为：第二电容Ct→导通的第一辅助晶体管S1→第一副边绕组LS1→第二辅助晶体管S2的本体二极管→主晶体管Qs的控制电极)导通，这样可以通过第一副边绕组LS1耦合的-VCC/2和第二电容两端的电压+VCC/2，使主晶体管Qs的控制电极上的电压迅速充电至+VCC，即可控制主晶体管Qs导通。
在t2～t3阶段中，第一控制脉冲信号PP1加载无效电平(例如低电平)，第一控制晶体管P1关断。第二控制脉冲信号PP2加载无效电平(例如低电平)，第二控制晶体管P2关断。则第一控制晶体管P1的本体二极管导通续流，原边绕组LP的电流ILP的电流方向为由第一端流向第二端至驱动电压源的正极，以将原边绕组LP中的能量充入驱动电压源，并使电流由正向电流最大值线性降低至0。这样即可实现原边绕组LP的断流。并且，原边绕组LP两端的电压仍为-VCC/2，并使第一副边绕组LS1的第一感应电动势的电压同步被耦合至-VCC/2。由于第二子驱动电路AC2中第二二极管D2、第三电阻R3以及第四电阻R4的相互作用，控制第二辅助晶体管S2关断。且由于第一子驱动电路AC1中第一二极管D1、第一电阻R1以及第二电阻R2的相互作用，控制第一辅助晶体管S1导通，从而使主晶体管Qs的充电路径继续导通，使主晶体管Qs的控制电极上的电压保持在+VCC，即可控制主晶体管Qs保持导通。
在t3～t4阶段中，第一控制脉冲信号PP1加载有效电平(例如高电平)，第一控制晶体管P1导通。第二控制脉冲信号PP2加载无效电平(例如低电平)，第二控制晶体管P2关断。 原边绕组LP的电流ILP的电流方向为由驱动电压源的正极流向第二端至第一端，并反向线性增长至反向电流最大值，且原边绕组LP两端的电压为-VCC/2，并使第一副边绕组LS1的第一感应电动势的电压同步被耦合至-VCC/2。由于第二子驱动电路AC2中第二二极管D2、第三电阻R3以及第四电阻R4的相互作用，控制第二辅助晶体管S2关断。且由于第一子驱动电路AC1中第一二极管D1、第一电阻R1以及第二电阻R2的相互作用，控制第一辅助晶体管S1导通，从而使主晶体管Qs的充电路径继续导通，这样可以使主晶体管Qs的控制电极充入少量电压，以使主晶体管Qs的控制电极的电压略微高于+VCC。这样是为了实现电荷平衡。并且，在实际应用中，充入的这些少量电压并不会对主晶体管Qs的导通和关断造成不利影响。
在t4～t5阶段中，第一控制脉冲信号PP1加载无效电平(例如低电平)，第一控制晶体管P1关断。第二控制脉冲信号PP2加载无效电平(例如低电平)，第二控制晶体管P2关断。则第二控制晶体管P2的本体二极管导通，原边绕组LP的电流ILP的电流方向为由驱动电压源的负极流向第二端至第一端，且原边绕组LP的电流ILP的电流可以看作定值。以及，原边绕组LP两端的电压变为+VCC/2，并使第一副边绕组LS1的第二感应电动势的电压同步被耦合至+VCC/2。由于第一子驱动电路AC1中第一二极管D1、第一电阻R1以及第二电阻R2的相互作用，控制第一辅助晶体管S1关断。且由于第二子驱动电路AC2中第二二极管D2、第三电阻R3以及第四电阻R4的相互作用，控制第二辅助晶体管S2导通，从而使主晶体管Qs的放电路径(该放电路径为：主晶体管Qs的控制电极→导通的第二辅助晶体管S2→第一副边绕组LS1→第一辅助晶体管S1的本体二极管→第二电容Ct→驱动电压源的负极(即接地端))导通，主晶体管Qs的控制电极上的电压放电，以使主晶体管Qs的控制电极上的电压迅速降为0V，即可控制主晶体管Qs关断。
在t5～t6阶段中，第一控制脉冲信号PP1加载无效电平(例如低电平)，第一控制晶体管P1关断。第二控制脉冲信号PP2加载无效电平(例如低电平)，第二控制晶体管P2关断。则第二控制晶体管P2的本体二极管导通续流，原边绕组LP的电流ILP的电流方向为由第二端流向第一端至第一电容Cr，以将原边绕组LP中的能量充入第一电容Cr，并使电流由反向电流最大值线性升至0。这样即可实现原边绕组LP的断流。以及，原边绕组LP两端的电压变为+VCC/2，并使第一副边绕组LS1的第二感应电动势的电压同步被耦合至+VCC/2。由于第一子驱动电路AC1中第一二极管D1、第一电阻R1以及第二电阻R2的相互作用，控制第一辅助晶体管S1关断。且由于第二子驱动电路AC2中第二二极管D2、第三电阻R3以及第四电阻R4的相互作用，控制第二辅助晶体管S2导通，从而使主晶体管Qs的放电路径继续导通，使主晶体管Qs的控制电极上的电压保持在0V。
综上，在主晶体管Qs的控制电极上的电压迅速充电至+VCC后，使主晶体管Qs导通，原边绕组LP的电流由正向电流最大值线性降低至0，实现断流的效果。以及在主晶体管Qs的控制电极上的电压迅速放电至0V后，使主晶体管Qs关断，原边绕组LP的电流由反向电流最大值线性升至0，实现断流的效果。因此，本申请实施例中的驱动电路，可以在保证主晶体管Qs的控制电极上充放电电流的基础上，实现断流效果，从而使原边绕组LP上的导通损耗最小化，降低驱动损耗。并且，本申请实施例提供的驱动电路，还可以将原边绕组LP中储存的多余能量回收至驱动电压源中，从而实现无损驱动。
图10为本申请另一种实施例提供的驱动电路的结构示意图。并且，图10中以驱动两个串联连接于接地端的主晶体管Qs_1(即第1主晶体管)和主晶体管Qs_2(即第2主晶 体管)为例进行示意。参照图10，主晶体管Qs_1和Qs_2的控制电极与驱动电路202连接，主晶体管Qs_1的第一电极与接地端连接，主晶体管Qs_1的第二电极与主晶体管Qs_2的第一电极连接，主晶体管Qs_2的第二电极可以与转换电路中的其他器件连接(图10中未示出主晶体管Qs_2的第二电极的具体连接方式)。本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
参照图10，驱动电路202包括：电压控制电路2011、耦合电路2012以及两个充放电控制电路2013_1、2013_2。耦合电路2012包括原边绕组LP和两个第一副边绕组LS1_1、LS1_2，原边绕组LP和第一副边绕组LS1_1、LS1_2之间互相耦合，且处于紧耦合状态。可选地，主晶体管Qs_1和Qs_2的驱动逻辑相同，即主晶体管Qs_1和Qs_2同时导通和关断，则原边绕组LP的第一端和第一副边绕组LS1_1的第一端为同名端，原边绕组LP的第一端和第一副边绕组LS1_2的第一端为同名端。需要说明的是，本申请实施例提供的驱动电路仅是以驱动两个驱动逻辑相同的主晶体管为例。在实际应用中，本申请实施例提供的驱动电路可以驱动三个、四个或更多个驱动逻辑相同的主晶体管，在此不作限定。
参照图10，充放电控制电路2013_1包括：第一辅助晶体管S1_1、第二辅助晶体管S2_1、第二电容Ct_1、由第一二极管D1_1、第一电阻R1_1以及第二电阻R2_1构成的第一子驱动电路AC1_1、以及由第二二极管D2_1、第三电阻R3_1以及第四电阻R4_1构成的第二子驱动电路AC2_1。其中，第二电容Ct_1、第一辅助晶体管S1_1、第一副边绕组LS1_1、第二辅助晶体管S2_1、以及主晶体管Qs_1的控制电极串联连接。需要说明的是，其具体连接关系可以参照上述实施例，在此不作赘述。
参照图10，充放电控制电路2013_2包括：第一辅助晶体管S1_2、第二辅助晶体管S2_2、第二电容Ct_2、由第一二极管D1_2、第一电阻R1_2以及第二电阻R2_2构成的第一子驱动电路AC1_2、以及由第二二极管D2_2、第三电阻R3_2以及第四电阻R4_2构成的第二子驱动电路AC2_2。其中，第二电容Ct_2、第一辅助晶体管S1_2、第一副边绕组LS1_2、第二辅助晶体管S2_2、以及主晶体管Qs_2的控制电极串联连接。需要说明的是，其具体连接关系可以参照上述实施例，在此不作赘述。
在无需隔离的应用场景中，本申请实施例提供的驱动电路可以设置为非隔离型驱动电路。示例性地，参照图10，第二电容Ct_1的第二电极还与原边绕组LP的第一端连接。并且，充放电控制电路2013_2还包括第一自举二极管Df1，第一自举二极管Df1的负极与第二电容Ct_2的第二电极连接，第一自举二极管Df1的正极与第二电容Ct_1的第二电极连接。由此，通过第一自举二极管Df1和第二电容Ct_2形成简单的自举电路，以通过该自举电路将基准电压+VCC/2供给至高位主晶体管Qs_2。
参照图11，图11为图10所示的驱动电路对应的信号时序图。其中，PP1代表加载到第一控制晶体管P1的控制电极上的第一控制脉冲信号，PP2代表加载到第二控制晶体管P2的控制电极上的第二控制脉冲信号，ULP代表原边绕组LP两端的电压，ILP代表原边绕组LP的电流，ULS1_1代表第一副边绕组LS1_1两端的感应电动势对应的电压，UGS1_1代表第一辅助晶体管S1_1的控制电极的电压，UGS2_1代表第二辅助晶体管S2_1的控制电极的电压，IGQs_1代表主晶体管Qs_1的控制电极的电流，UGQs_1代表主晶体管Qs_1的控制电极的电压,ULS1_2代表第一副边绕组LS1_2两端的感应电动势对应的电压，UGS1_2代表第一辅助晶体管S1_2的控制电极的电压，UGS2_2代表第二辅助晶体管S2_2的控制电极的电压，IGQs_2代表主晶体管Qs_2的控制电极的电流，UGQs_2代表主晶体管Qs_2的控制电极的电压。
需要说明的是，图10所示的驱动电路结合图11所示的信号时序图，可以控制驱动主晶体管Qs_1和Qs_2的控制电极同时充放电，从而控制主晶体管Qs_1和Qs_2同时导通和关断，进而使主晶体管Qs_1和Qs_2的驱动逻辑相同。并且，本实施例在t0～t6阶段的工作过程，可以参照上述实施例，在此不作赘述。
图12为本申请又一种实施例提供的驱动电路的结构示意图。并且，图12中以驱动两个串联连接于接地端的主晶体管Qs_1(即第1主晶体管)和主晶体管Qs_2(即第2主晶体管)为例进行示意。参照图10，主晶体管Qs_1和Qs_2的控制电极与驱动电路203连接。本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
参照图12，驱动电路203包括：电压控制电路2011、耦合电路2012以及两个充放电控制电路2013_1、2013_2。耦合电路2012包括原边绕组LP和两个第一副边绕组LS1_1、LS1_2，原边绕组LP和第一副边绕组LS1_1、LS1_2之间互相耦合，且处于紧耦合状态。可选地，主晶体管Qs_1和Qs_2的驱动逻辑相反，即主晶体管Qs_1和Qs_2的逻辑互补。具体地，在主晶体管Qs_1导通时，主晶体管Qs_2关断。在主晶体管Qs_2导通时，主晶体管Qs_1关断。则原边绕组LP的第一端和第一副边绕组LS1_1的第一端为同名端，原边绕组LP的第一端和第一副边绕组LS1_2的第一端为异名端。需要说明的是，本申请实施例提供的驱动电路仅是以驱动两个驱动逻辑相反的主晶体管为例。在实际应用中，本申请实施例提供的驱动电路可以驱动三个、四个或更多个驱动逻辑相反的主晶体管，在此不作限定。
参照图13，图13为图12所示的驱动电路对应的信号时序图。其中，PP1代表加载到第一控制晶体管P1的控制电极上的第一控制脉冲信号，PP2代表加载到第二控制晶体管P2的控制电极上的第二控制脉冲信号，ULP代表原边绕组LP两端的电压，ILP代表原边绕组LP的电流，ULS1_1代表第一副边绕组LS1_1两端的感应电动势对应的电压，UGS1_1代表第一辅助晶体管S1_1的控制电极的电压，UGS2_1代表第二辅助晶体管S2_1的控制电极的电压，IGQs_1代表主晶体管Qs_1的控制电极的电流，UGQs_1代表主晶体管Qs_1的控制电极的电压,ULS1_2代表第一副边绕组LS1_2两端的感应电动势对应的电压，UGS1_2代表第一辅助晶体管S1_2的控制电极的电压，UGS2_2代表第二辅助晶体管S2_2的控制电极的电压，IGQs_2代表主晶体管Qs_2的控制电极的电流，UGQs_2代表主晶体管Qs_2的控制电极的电压。
在图12所示的驱动电路结合图13所示的信号时序图进行工作时，可以控制驱动主晶体管Qs_1和Qs_2的控制电极分时充放电，从而在主晶体管Qs_1导通时，主晶体管Qs_2关断。在主晶体管Qs_2导通时，主晶体管Qs_1关断。并且，本实施例在t0～t9阶段中控制主晶体管Qs_1的充电时，控制主晶体管Qs_2的放电，以及控制主晶体管Qs_1的放电时，控制主晶体管Qs_2的充电，从而实现驱动主晶体管Qs_1和主晶体管Qs_2的驱动逻辑相反。其中，本实施例在t0～t6阶段中控制主晶体管Qs_1的充放电过程，可参照上述控制主晶体管Qs_1的充放电过程，具体在此不作赘述。以及，本实施例在t3～t9阶段中控制主晶体管Qs_2的充放电过程，也可参照上述控制主晶体管Qs_1的充放电过程，具体在此不作赘述。
图14为本申请又一种实施例提供的驱动电路的结构示意图。并且，图14中以驱动两个串联连接于接地端的主晶体管Qs_1(即第1主晶体管)和主晶体管Qs_2(即第2主晶体管)为例进行示意。参照图14，主晶体管Qs_1和Qs_2的控制电极与驱动电路204连接。 本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
参照图14，驱动电路204包括：电压控制电路2011、耦合电路2012以及两个充放电控制电路2013_1、2013_2。耦合电路2012包括原边绕组LP和两个第一副边绕组LS1_1、LS1_2，原边绕组LP和第一副边绕组LS1_1、LS1_2之间互相耦合且处于紧耦合状态。可选地，主晶体管Qs_1和Qs_2的驱动逻辑相反，即主晶体管Qs_1和Qs_2的逻辑互补。具体地，在主晶体管Qs_1导通时，主晶体管Qs_2关断。在主晶体管Qs_2导通时，主晶体管Qs_1关断。则原边绕组LP的第一端和第一副边绕组LS1_1的第一端为同名端，原边绕组LP的第一端和第一副边绕组LS1_2的第一端为异名端。需要说明的是，本申请实施例提供的驱动电路仅是以驱动两个驱动逻辑相反的主晶体管为例。在实际应用中，本申请实施例提供的驱动电路可以驱动三个、四个或更多个驱动逻辑相反的主晶体管，在此不作限定。
当然，也可以使主晶体管Qs_1和Qs_2的驱动逻辑相同，即主晶体管Qs_1和Qs_2同时导通和关断。具体地，在主晶体管Qs_1导通时，主晶体管Qs_2导通。在主晶体管Qs_1关断时，主晶体管Qs_2关断。则原边绕组LP的第一端和第一副边绕组LS1_1的第一端为同名端，原边绕组LP的第一端和第一副边绕组LS1_2的第一端为同名端。
参照图14，充放电控制电路2013_1包括：第一辅助晶体管S1_1、第二辅助晶体管S2_1、第二电容Ct_1、由第一二极管D1_1、第一电阻R1_1以及第二电阻R2_1构成的第一子驱动电路AC1_1、以及由第二二极管D2_1、第三电阻R3_1以及第四电阻R4_1构成的第二子驱动电路AC2_1。其中，第二电容Ct_1、第一辅助晶体管S1_1、第一副边绕组LS1_1、第二辅助晶体管S2_1、以及主晶体管Qs_1的控制电极串联连接。需要说明的是，其具体连接关系可以参照上述实施例，在此不作赘述。
参照图14，充放电控制电路2013_2包括：第一辅助晶体管S1_2、第二辅助晶体管S2_2、第二电容Ct_2、由第一二极管D1_2、第一电阻R1_2以及第二电阻R2_2构成的第一子驱动电路AC1_2、以及由第二二极管D2_2、第三电阻R3_2以及第四电阻R4_2构成的第二子驱动电路AC2_2。其中，第二电容Ct_2、第一辅助晶体管S1_2、第一副边绕组LS1_2、第二辅助晶体管S2_2、以及主晶体管Qs_2的控制电极串联连接。需要说明的是，其具体连接关系可以参照上述实施例，在此不作赘述。
在需要隔离的应用场景中，本申请实施例提供的驱动电路204也可以设置为隔离型驱动电路。示例性地，参照图14，为了给隔离型驱动电路的副边提供一个基准电压，可以在耦合电路2012中设置第二副边绕组LD，在驱动电路204中设置储能电容CD和第二自举二极管Df2。其中，原边绕组LP和第二副边绕组LD之间互相耦合，并处于紧耦合状态。这样使得第二副边绕组LD能够根据第一电压耦合产生第一感应电动势，以及根据第二电压耦合产生第二感应电动势。并且，第二自举二极管Df2的正极与第二副边绕组LD的第一端连接，第二自举二极管Df2的负极与储能电容CD的第一电极连接。储能电容CD的第二电极分别与第二副边绕组LD的第二端以及接地端连接。第二电容Ct_1的第二电极还与储能电容CD的第一电极连接。这样通过第二副边绕组LD、储能电容CD和第二自举二极管Df2的相互配合，能够组成峰值保持电路，从而在隔离型驱动器的副边形成一个隔离的基准电压直流电压源，以使第二电容Ct_1的两端电压为第二电压。以及，第二副边绕组LD的第一端和原边绕组LP的第一端为同名端。
参照图14，在隔离型驱动电路中，第二电容Ct_1的第二电极还与储能电容CD的第一电极连接。并且，充放电控制电路2013_2还包括第三自举二极管Df3，第三自举二极管Df3的负极与第二电容Ct_2的第二电极连接，第三自举二极管Df3的正极与第二电容Ct_1的第二电极连接。且原边绕组LP的第一端和第二副边绕组LD的第一端为同名端。由此，通过第三自举二极管Df3和第二电容Ct_2形成简单的自举电路，以通过该自举电路将基准电压+VCC/2供给至高位主晶体管Qs_2。
图14所示的驱动电路，对应的信号时序图，如图13所示。在图14所示的驱动电路结合图13所示的信号时序图进行工作时，可以控制驱动主晶体管Qs_1和Qs_2的控制电极分时充放电，从而在主晶体管Qs_1导通时，主晶体管Qs_2关断。在主晶体管Qs_2导通时，主晶体管Qs_1关断。并且，本实施例在t0～t9阶段中控制主晶体管Qs_1的充电时，控制主晶体管Qs_2的放电，以及控制主晶体管Qs_1的放电时，控制主晶体管Qs_2的充电，从而实现驱动主晶体管Qs_1和主晶体管Qs_2的驱动逻辑相反。其中，本实施例在t0～t6阶段中控制主晶体管Qs_1的充放电过程，可参照上述控制主晶体管Qs_1的充放电过程，具体在此不作赘述。以及，本实施例在t3～t9阶段中控制主晶体管Qs_2的充放电过程，也可参照上述控制主晶体管Qs_1的充放电过程，具体在此不作赘述。
图15为本申请又一种实施例提供的驱动电路的结构示意图。并且，图15中以驱动四个串联连接于接地端的主晶体管Qs_1(即第1主晶体管)、主晶体管Qs_2(即第2主晶体管)、主晶体管Qs_3(即第3主晶体管)、主晶体管Qs_4(即第4主晶体管)为例进行示意。参照图15，主晶体管Qs_1～Qs_4的控制电极与驱动电路205连接。本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
参照图15，驱动电路205包括：电压控制电路2011、耦合电路2012以及四个充放电控制电路2013_1～2013_4。耦合电路2012包括原边绕组LP和四个第一副边绕组LS1_1～LS1_4，原边绕组LP和第一副边绕组LS1_1～LS1_4之间互相耦合且处于紧耦合状态。可选地，主晶体管Qs_1和Qs_2的驱动逻辑相同，即主晶体管Qs_1和Qs_2同时导通和关断，并且，主晶体管Qs_3和Qs_4的驱动逻辑相同，即主晶体管Qs_3和Qs_4同时导通和关断。以及，主晶体管Qs_3和Qs_1的驱动逻辑相反，则原边绕组LP的第一端和第一副边绕组LS1_1的第一端为同名端，原边绕组LP的第一端和第一副边绕组LS1_2的第一端为同名端，原边绕组LP的第一端和第一副边绕组LS1_3的第一端为异名端，原边绕组LP的第一端和第一副边绕组LS1_4的第一端为异名端。
参照图15，充放电控制电路2013_1包括：第一辅助晶体管S1_1、第二辅助晶体管S2_1、第二电容Ct_1、由第一二极管D1_1、第一电阻R1_1以及第二电阻R2_1构成的第一子驱动电路AC1_1、以及由第二二极管D2_1、第三电阻R3_1以及第四电阻R4_1构成的第二子驱动电路AC2_1。其中，第二电容Ct_1、第一辅助晶体管S1_1、第一副边绕组LS1_1、第二辅助晶体管S2_1、以及主晶体管Qs_1的控制电极串联连接。需要说明的是，其具体连接关系可以参照上述实施例，在此不作赘述。
参照图15，充放电控制电路2013_2包括：第一辅助晶体管S1_2、第二辅助晶体管S2_2、第二电容Ct_2、由第一二极管D1_2、第一电阻R1_2以及第二电阻R2_2构成的第一子驱动电路AC1_2、以及由第二二极管D2_2、第三电阻R3_2以及第四电阻R4_2构成的第二子驱动电路AC2_2。其中，第二电容Ct_2、第一辅助晶体管S1_2、第一副边绕组LS1_2、 第二辅助晶体管S2_2、以及主晶体管Qs_2的控制电极串联连接。需要说明的是，其具体连接关系可以参照上述实施例，在此不作赘述。
参照图15，充放电控制电路2013_3包括：第一辅助晶体管S1_3、第二辅助晶体管S2_3、第二电容Ct_3、由第一二极管D1_3、第一电阻R1_3以及第二电阻R2_3构成的第一子驱动电路AC1_3、以及由第二二极管D2_3、第三电阻R3_3以及第四电阻R4_3构成的第二子驱动电路AC2_3。其中，第二电容Ct_3、第一辅助晶体管S1_3、第一副边绕组LS1_3、第二辅助晶体管S2_3、以及主晶体管Qs_3的控制电极串联连接。需要说明的是，其具体连接关系可以参照上述实施例，在此不作赘述。
参照图15，充放电控制电路2013_4包括：第一辅助晶体管S1_4、第二辅助晶体管S2_4、第二电容Ct_4、由第一二极管D1_4、第一电阻R1_4以及第二电阻R2_4构成的第一子驱动电路AC1_4、以及由第二二极管D2_4、第三电阻R3_4以及第四电阻R4_4构成的第二子驱动电路AC2_4。其中，第二电容Ct_4、第一辅助晶体管S1_4、第一副边绕组LS1_4、第二辅助晶体管S2_4、以及主晶体管Qs_4的控制电极串联连接。需要说明的是，其具体连接关系可以参照上述实施例，在此不作赘述。
在需要隔离的应用场景中，本申请实施例提供的驱动电路205也可以设置为隔离型驱动电路。示例性地，参照图15，为了给隔离型驱动电路的副边提供一个基准电压，可以在耦合电路2012中设置第二副边绕组LD，在驱动电路204中设置储能电容CD和第二自举二极管Df2。其中，原边绕组LP和第二副边绕组LD之间互相耦合并处于紧耦合状态。这样使得第二副边绕组LD能够根据第一电压耦合产生第一感应电动势，以及根据第二电压耦合产生第二感应电动势。并且，第二自举二极管Df2的正极与第二副边绕组LD的第一端连接，第二自举二极管Df2的负极与储能电容CD的第一电极连接。储能电容CD的第二电极分别与第二副边绕组LD的第二端以及接地端连接。第二电容Ct_1的第二电极还与储能电容CD的第一电极连接。这样通过第二副边绕组LD、储能电容CD和第二自举二极管Df2的相互配合，能够组成峰值保持电路，从而在隔离型驱动器的副边形成一个隔离的基准电压直流电压源，以使第二电容Ct_1的两端电压为第二电压。以及，第二副边绕组LD的第一端和原边绕组LP的第一端为同名端。
参照图15，在隔离型驱动电路中，第二电容Ct_1的第二电极还与储能电容CD的第一电极连接。并且，充放电控制电路2013_2还包括第三自举二极管Df3_1，充放电控制电路2013_3还包括第三自举二极管Df3_2，充放电控制电路2013_4还包括第三自举二极管Df3_3。第三自举二极管Df3_1的负极与第二电容Ct_2的第二电极连接，第三自举二极管Df3_1的正极与第二电容Ct_1的第二电极连接。由此，通过第三自举二极管Df3_1和第二电容Ct_2形成简单的自举电路，以通过该自举电路将基准电压+VCC/2供给至高位主晶体管Qs_2。第三自举二极管Df3_2的负极与第二电容Ct_3的第二电极连接，第三自举二极管Df3_2的正极与第二电容Ct_2的第二电极连接。由此，通过第三自举二极管Df3_2和第二电容Ct_3形成简单的自举电路，以通过该自举电路将基准电压+VCC/2供给至高位主晶体管Qs_3。第三自举二极管Df3_3的负极与第二电容Ct_4的第二电极连接，第三自举二极管Df3_3的正极与第二电容Ct_3的第二电极连接。由此，通过第三自举二极管Df3_3和第二电容Ct_4形成简单的自举电路，以通过该自举电路将基准电压+VCC/2供给至高位主晶体管Qs_4。
参照图16，图16为图15所示的驱动电路对应的信号时序图。其中，PP1代表加载到 第一控制晶体管P1的控制电极上的第一控制脉冲信号，PP2代表加载到第二控制晶体管P2的控制电极上的第二控制脉冲信号，ULP代表原边绕组LP两端的电压，ILP代表原边绕组LP的电流，ULS1_1代表第一副边绕组LS1_1两端的感应电动势对应的电压，UGS1_1代表第一辅助晶体管S1_1的控制电极的电压，UGS2_1代表第二辅助晶体管S2_1的控制电极的电压，IGQs_1代表主晶体管Qs_1的控制电极的电流，UGQs_1代表主晶体管Qs_1的控制电极的电压,ULS1_2代表第一副边绕组LS1_2两端的感应电动势对应的电压，UGS1_2代表第一辅助晶体管S1_2的控制电极的电压，UGS2_2代表第二辅助晶体管S2_2的控制电极的电压，IGQs_2代表主晶体管Qs_2的控制电极的电流，UGQs_2代表主晶体管Qs_2的控制电极的电压。ULS1_3代表第一副边绕组LS1_3两端的感应电动势对应的电压，UGS1_3代表第一辅助晶体管S1_3的控制电极的电压，UGS2_3代表第二辅助晶体管S2_3的控制电极的电压，IGQs_3代表主晶体管Qs_3的控制电极的电流，UGQs_3代表主晶体管Qs_3的控制电极的电压。ULS1_4代表第一副边绕组LS1_4两端的感应电动势对应的电压，UGS1_4代表第一辅助晶体管S1_4的控制电极的电压，UGS2_4代表第二辅助晶体管S2_4的控制电极的电压，IGQs_4代表主晶体管Qs_4的控制电极的电流，UGQs_4代表主晶体管Qs_4的控制电极的电压。
在图15所示的驱动电路结合图16所示的信号时序图进行工作时，可以控制驱动主晶体管Qs_1和Qs_2的控制电极同时充放电，主晶体管Qs_3和Qs_4的控制电极同时充放电，主晶体管Qs_1和Qs_3的控制电极分时充放电，从而实现驱动主晶体管Qs_1和主晶体管Qs_2的驱动逻辑相同，主晶体管Qs_3和主晶体管Qs_4的驱动逻辑相同，主晶体管Qs_1和主晶体管Qs_3的驱动逻辑相反。其中，本实施例在t0～t6阶段中控制主晶体管Qs_1和Qs_2的充放电过程，可参照上述控制主晶体管Qs_1的充放电过程，具体在此不作赘述。以及，本实施例在t3～t9阶段中控制主晶体管Qs_3和Qs_4的充放电过程，也可参照上述控制主晶体管Qs_1的充放电过程，具体在此不作赘述。
图17为本申请又一种实施例提供的驱动电路的结构示意图。图17中以驱动两个均连接于接地端的主晶体管Qs_1a和主晶体管Qs_1b为例进行示意。并且，主晶体管Qs_1a和Qs_1b的控制电极与驱动电路206连接。本实施例针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
参照图17，驱动电路206包括：电压控制电路2011、耦合电路2012以及两个充放电控制电路2013_1a、2013_1b。耦合电路2012包括原边绕组LP和两个第一副边绕组LS1_1a、LS1_1b，原边绕组LP和第一副边绕组LS1_1a、LS1_1b之间互相耦合且处于紧耦合状态。可选地，主晶体管Qs_1a和Qs_1b的驱动逻辑相反，即主晶体管Qs_1a和Qs_1b的逻辑互补。具体地，在主晶体管Qs_1a导通时，主晶体管Qs_1b关断。在主晶体管Qs_1b导通时，主晶体管Qs_1a关断。则原边绕组LP的第一端和第一副边绕组LS1_1a的第一端为同名端，原边绕组LP的第一端和第一副边绕组LS1_1b的第一端为异名端。需要说明的是，本申请实施例提供的驱动电路仅是以驱动两个驱动逻辑相反的主晶体管为例。在实际应用中，本申请实施例提供的驱动电路可以驱动三个、四个或更多个驱动逻辑相反的主晶体管，在此不作限定。
当然，也可以使主晶体管Qs_1a和Qs_1b的驱动逻辑相同，即主晶体管Qs_1a和Qs_1b同时导通和关断。具体地，在主晶体管Qs_1a导通时，主晶体管Qs_1b导通。在主晶体管Qs_1a关断时，主晶体管Qs_1b关断。则原边绕组LP的第一端和第一副边绕组LS1_1的第一端为同名端，原边绕组LP的第一端和第一副边绕组LS1_2的第一端为同名端。
参照图17，充放电控制电路2013_1a包括：第一辅助晶体管S1_1a、第二辅助晶体管S2_1a、第二电容Ct_1a、由第一二极管D1_1a、第一电阻R1_1a以及第二电阻R2_1a构成的第一子驱动电路AC1_1a、以及由第二二极管D2_1a、第三电阻R3_1a以及第四电阻R4_1a构成的第二子驱动电路AC2_1a。其中，第二电容Ct_1a、第一辅助晶体管S1_1a、第一副边绕组LS1_1a、第二辅助晶体管S2_1a、以及主晶体管Qs_1a的控制电极串联连接。需要说明的是，其具体连接关系可以参照上述实施例，在此不作赘述。
参照图17，充放电控制电路2013_1b包括：第一辅助晶体管S1_1b、第二辅助晶体管S2_1b、第二电容Ct_1b、由第一二极管D1_1b、第一电阻R1_1b以及第二电阻R2_1b构成的第一子驱动电路AC1_1b、以及由第二二极管D2_1b、第三电阻R3_1b以及第四电阻R4_1b构成的第二子驱动电路AC2_1b。其中，第二电容Ct_1b、第一辅助晶体管S1_1b、第一副边绕组LS1_1b、第二辅助晶体管S2_1b、以及主晶体管Qs_1b的控制电极串联连接。需要说明的是，其具体连接关系可以参照上述实施例，在此不作赘述。
在需要隔离的应用场景中，本申请实施例提供的驱动电路206设置为隔离型驱动电路。示例性地，参照图17，为了给隔离型驱动电路的副边提供一个基准电压，可以在耦合电路2012中设置第二副边绕组LD，在驱动电路205中设置储能电容CD和第二自举二极管Df2。其中，第二电容Ct_1的第二电极、第二电容Ct_1b的第二电极均还与储能电容CD的第一电极连接。原边绕组LP和第二副边绕组LD之间互相耦合并处于紧耦合状态。这样使得第二副边绕组LD能够根据第一电压耦合产生第一感应电动势，以及根据第二电压耦合产生第二感应电动势。并且，第二自举二极管Df2的正极与第二副边绕组LD的第一端连接，第二自举二极管Df2的负极与储能电容CD的第一电极连接。储能电容Df2的第二电极分别与第二副边绕组LD的第二端以及接地端连接。第二电容Ct_1a和Ct_1b的第二电极还与储能电容CD的第一电极连接。这样通过第二副边绕组LD、储能电容CD和第二自举二极管Df2的相互配合，能够组成峰值保持电路，从而在隔离型驱动器的副边形成一个隔离的基准电压直流电压源，以使第二电容Ct_1a和Ct_1b的两端电压为第二电压。以及，第二副边绕组LD的第一端和原边绕组LP的第一端为同名端。
参照图18，图18为图17所示的驱动电路对应的信号时序图。其中，PP1代表加载到第一控制晶体管P1的控制电极上的第一控制脉冲信号，PP2代表加载到第二控制晶体管P2的控制电极上的第二控制脉冲信号，ULP代表原边绕组LP两端的电压，ILP代表原边绕组LP的电流，ULS1_1a代表第一副边绕组LS1_1a两端的感应电动势对应的电压，UGS1_1a代表第一辅助晶体管S1_1a的控制电极的电压，UGS2_1a代表第二辅助晶体管S2_1a的控制电极的电压，IGQs_1a代表主晶体管Qs_1a的控制电极的电流，UGQs_1a代表主晶体管Qs_1a的控制电极的电压,ULS1_1b代表第一副边绕组LS1_1b两端的感应电动势对应的电压，UGS1_1b代表第一辅助晶体管S1_1b的控制电极的电压，UGS2_1b代表第二辅助晶体管S2_1b的控制电极的电压，IGQs_1b代表主晶体管Qs_1b的控制电极的电流，UGQs_1b代表主晶体管Qs_1b的控制电极的电压。
在图17所示的驱动电路结合图18所示的信号时序图进行工作时，可以控制驱动主晶体管Qs_1a和Qs_1b的控制电极分时充放电，从而在主晶体管Qs_1a导通时，主晶体管Qs_1b关断。在主晶体管Qs_1b导通时，主晶体管Qs_1a关断。并且，本实施例在t0～t9阶段中控制主晶体管Qs_1a的充电时，控制主晶体管Qs_1b的放电，以及控制主晶体管Qs_1a的放电时，控制主晶体管Qs_1b的充电，从而实现驱动主晶体管Qs_1a和主晶体管 Qs_1b的驱动逻辑相反。其中，本实施例在t0～t6阶段中控制主晶体管Qs_1a的充放电过程，可参照上述控制主晶体管Qs_1的充放电过程，具体在此不作赘述。以及，本实施例在t3～t9阶段中控制主晶体管Qs_1b的充放电过程，也可参照上述控制主晶体管Qs_1的充放电过程，具体在此不作赘述。
以上仅是举例说明本申请驱动电路控制不同主晶体管处于不同驱动逻辑时的工作过程。在具体实施时，可以将上述驱动电路进行结合，以应用到具体的转换电路中。并且，在具体实施时，将本申请实施例提供的驱动电路应用到上述转换电路中后，可以在控制转换电路实现电压转换的同时，降低整个电路的驱动损耗。
软开关技术是转换电路实现高转换效率的重要技术之一。其中，LLC谐振转换器被人们做了大量的研究和广泛的应用。本申请以转换电路为LLC谐振转换器为例，即，本申请的驱动电路驱动的主晶体管可以为LLC谐振转换器中的开关管。
图19为本申请一种实施例提供的LLC谐振转换器的结构示意图。该转换电路以半桥型LLC谐振转换器为例。参照图19，转换电路101中包括逆变电路、谐振电路、变压器和整流电路。在实际应用中，采用上述转换电路101对输入电压Vi进行转换时，逆变电路将输入电压Vi转换为交流电压，将转换出的交流电压通过谐振电路和变压器传输给整流电路，整流电路将变压器输出的交流电转换为直流电压VO后输出。示例性地，逆变电路主要包括：电容C1和C2，以及两个开关管Q11和Q12。谐振电路主要包括：谐振电感Lr0和谐振电容Cr0。变压器T的原边绕组与谐振电感Lr0和谐振电容Cr0串联，变压器T的副边绕组与整流电路连接。整流电路主要包括开关管Q13～Q16。其中，谐振电感Lr0可以是独立的电感，也可以是变压器原边绕组的漏感，或者谐振电感Lr0由一部分独立电感以及一部分变压器原边绕组的漏感组成。需要说明的是，若转换电路101中的开关管Q11～Q16为MOSFET，则开关管Q11～Q16的控制电极为栅电极。并且，可以根据在实际工作中，开关管Q11～Q16的电流的流向，可以将开关管Q11～Q16中的任一个开关管Q11～Q16的第一电极为源电极，第二电极为漏电极，或者，将开关管Q11～Q16中的任一个开关管Q11～Q16的第一电极为漏电极，第二电极为源电极。并且，图19中“+”代表高电压端，“-”代表接地端。
在一些示例中，图19所示的转换电路101中的逆变电路可以对应设置一个本申请中的驱动电路。例如，本申请实施例中的驱动电路203和204连接的主晶体管Qs_1可以为转换电路101中的开关管Q11，主晶体管Qs_2可以为转换电路101中的开关管Q12。
在另一些示例中，图19所示的转换电路101中的整流电路可以对应设置一个本申请中的驱动电路。例如，结合本申请实施例中的驱动电路204和206，可以设置一个电压控制电路、耦合电路以及四个充放电控制电路。即针对开关管Q13～Q16分别对应连接一个充放电控制电路，并使开关管Q13和开关管Q16驱动逻辑相同，使开关管Q14和开关管Q15驱动逻辑相同，开关管Q13和开关管Q14驱动逻辑相反。
在又一些示例中，图19所示的转换电路101中的逆变电路和整流电路对应设置一个本申请中的驱动电路。例如，本申请实施例中的驱动电路203、204和206，可以设置一个电压控制电路、耦合电路以及六个充放电控制电路。开关管Q11～Q16一一对应连接一个充放电控制电路。
图20为本申请另一种实施例提供的LLC谐振转换器的结构示意图。该转换电路102以级联半桥型LLC谐振转换器为例。并且，该实施例提供的LLC谐振转换器与图19所示 的LLC谐振转换器仅是逆变电路不同。下面仅说明其不同之处，其相同之处不在赘述。参照图20，逆变电路主要包括：电容C1和C2，以及四个开关管Q21～Q24。其中，开关管Q21～Q24串联于接地端。
在一些示例中，图20所示的转换电路102中的逆变电路可以对应设置一个本申请中的驱动电路。例如，本申请实施例中的驱动电路205连接的主晶体管Qs_1可以为转换电路102中的开关管Q21，主晶体管Qs_2可以为转换电路102中的开关管Q22，主晶体管Qs_3可以为转换电路102中的开关管Q23，主晶体管Qs_4可以为转换电路102中的开关管Q24。
并且，通过设定相关参数：设定逆变电路的输入电压Vi为40V，主回路交流电流有效值为1A，逆变电路输出功率为40W，并设定驱动电路205连接的驱动电压源VDC的驱动电压VCC为5V，开关管Q21～Q24的开关频率为2MHz，控制晶体管P1～P2对应的有效电平的导通时间为50ns。依据所设定的参数，对本申请实施例中，驱动电路205驱动转换电路102中的开关管Q21～Q24的工作过程进行了仿真模拟，仿真模拟的波形示意图，如图21所示。其中，L11代表原边绕组LP的仿真模拟的电流，L12代表一个第一原边绕组的仿真模拟的电流，L21代表开关管Q21的仿真模拟的控制电极的电压，L22代表开关管Q22的仿真模拟的控制电极的电压，L23代表开关管Q23的仿真模拟的控制电极的电压，L24代表开关管Q24的仿真模拟的控制电极的电压。从图21中可看出，仿真结果与理论分析基本吻合，开关管Q21、Q22与开关管Q23、Q24的驱动逻辑互补。原边绕组的电流和第一副边绕组的电流也与理论分析基本吻合。并且，开关管Q21～Q24的栅电极的电压上升和下降时间均约为28ns，栅电极电压变化量约为4.5V。相对于理论上四个开关管：4*4.5V*11nC*2MHz＝396mW的驱动损耗，本申请实施例提供的驱动电路205在该应用场合下，相对于396mW，可以有效将功率损耗降低了396mW*46％以上。
上述仅是以半桥型的LLC谐振转换器为例进行说明的是，在LLC谐振转换器为全桥型时，可以结合本申请实施例中的驱动电路204和206，确定驱动逆变电路的驱动电路。例如，可以设置一个电压控制电路、耦合电路以及四个充放电控制电路。逆变电路中的每一个开关管对应连接一个充放电控制电路，并使第一组中的两个开关管的驱动逻辑相同，第二组中的两个开关管驱动逻辑相同，且第一组中的两个开关管和第二组中的两个开关管驱动逻辑相反。
综上，本申请实施例提供的驱动电路，在驱动较多主晶体管时，仅需增加一个充放电控制电路和一个第一副边绕组即可，从而有利于节约驱动电路成本和体积。
并且，本申请实施例提供的驱动电路，具有非隔离型和隔离型两种模式，这样可以根据非隔离场合和隔离场合选择性的采用驱动电路的模式，提高驱动电路的适用性。
以及，本申请实施例提供的驱动电路，对电压控制电路提供控制脉冲信号，占用IO接口资源较少。
基于相同的构思，本申请实施例还提供一种电源模块，该电源模块可以包括转换电路以及上述任一项所提供的驱动电路。其中，驱动电路用于驱动转换电路中的主晶体管。示例性地，该电源模块既可以是直流-直流电源模块，也可以是交流-直流电源模块。上述电源模块可以应用于不同类型的电子设备中，如智能手机、智能电视、笔记本电脑、掌上电脑(personal digital assistant，PDA)、具备无线通讯功能的可穿戴设备(如智能手表、智能眼镜、智能手环)、车载设备或数据中心等。由于该电源模块解决问题的原理与前述驱动 电路相似，因此该电源模块的实施可以参见前述驱动电路的实施，重复之处不再赘述。
基于相同的构思，本申请实施例还提供一种电子设备，该电子设备可以包括上述任一项提供的电源模块及负载模块。其中，电源模块与负载模块电性连接，以为负载模块提供直流电压。示例性地，该电子设备例如为：智能手机、智能电视、笔记本电脑、掌上电脑(personal digital assistant，PDA)、具备无线通讯功能的可穿戴设备(如智能手表、智能眼镜、智能手环)、车载设备或数据中心等。由于该电子设备解决问题的原理与前述电源模块相似，因此该电子设备的实施可以参见前述电源模块的实施，重复之处不再赘述。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (15)

  1. 一种驱动电路，用于驱动N个主晶体管，其特征在于，所述驱动电路包括：电压控制电路、耦合电路以及N个充放电控制电路；其中，所述耦合电路包括原边绕组和N个第一副边绕组，所述原边绕组和所述N个第一副边绕组中的每一个第一副边绕组之间互相耦合，所述电压控制电路与所述原边绕组连接，所述N个第一副边绕组与所述N个充放电控制电路一一对应连接，所述N个充放电控制电路与所述N个主晶体管的控制电极一一对应连接；N为正整数；
    所述电压控制电路用于响应于多个控制脉冲信号，驱动所述原边绕组产生周期性的第一电压和第二电压；其中，所述N个第一副边绕组中的任一个第一副边绕组根据所述第一电压耦合产生第一感应电动势，根据所述第二电压耦合产生第二感应电动势；其中，所述控制脉冲信号的有效电平在一个所述周期中的占空比的范围为4％～30％；
    所述N个充放电控制电路中的任一个充放电控制电路用于根据对应连接的第一副边绕组耦合产生的所述第一感应电动势和所述第二感应电动势，控制对应连接的所述主晶体管的控制电极进行充放电，以控制对应连接的所述主晶体管导通和关断。
  2. 如权利要求1所述的驱动电路，其特征在于，所述N个主晶体管的开关频率为1MHz，所述控制脉冲信号的有效电平在一个周期中的占空比的范围为1/21～1/6；
    或者，所述N个主晶体管的开关频率为2MHz，所述控制脉冲信号的有效电平在一个周期中的占空比的范围为1/11～2/7。
  3. 如权利要求2所述的驱动电路，其特征在于，所述N个主晶体管的开关频率为1MHz时对应的有效电平与所述N个主晶体管的开关频率为2MHz时对应的有效电平的维持时长相同。
  4. 如权利要求1-3任一项所述的驱动电路，其特征在于，所述电压控制电路包括：多个控制晶体管和第一电容，所述第一电容与所述原边绕组串联连接后与所述多个控制晶体管中的至少一个控制晶体管并联，所述多个控制晶体管串联连接于驱动电压源的正负极之间；
    所述控制脉冲信号为多个，所述多个控制晶体管与所述多个控制脉冲信号一一对应，所述多个控制晶体管中的每一个控制晶体管的控制电极用于接收对应的控制脉冲信号；
    所述多个控制晶体管响应于对应的控制脉冲信号，根据所述驱动电压源的驱动电压驱动所述原边绕组产生周期性的所述第一电压和所述第二电压。
  5. 如权利要求4所述的驱动电路，其特征在于，所述多个控制晶体管为两个，所述两个控制晶体管分别为第一控制晶体管和第二控制晶体管，所述多个控制脉冲信号分别为第一控制脉冲信号和第二控制脉冲信号；其中，所述第一控制脉冲信号和所述第二控制脉冲信号的有效电平之间具有死区时间；
    所述第一控制晶体管的控制电极用于接收所述第一控制脉冲信号，所述第一控制晶体管的第一电极与所述驱动电压源的正极连接，所述第一控制晶体管的第二电极与所述第二控制晶体管的第一电极连接，所述第二控制晶体管的控制电极用于接收所述第二控制脉冲信号，所述第二控制晶体管的第二电极与所述驱动电压源的负极连接；
    所述第一电容的第一电极分别与所述第一控制晶体管的第一级和所述驱动电压源的正极连接，所述第一电容的第二电极与所述原边绕组的第一端连接，所述原边绕组的第二 端分别与所述第一控制晶体管的第二电极和所述第二控制晶体管的第一级连接。
  6. 如权利要求1-5任一项所述的驱动电路，其特征在于，所述N个充放电控制电路中的任一个充放电控制电路包括：多个辅助晶体管、第二电容以及自驱动电路；其中，所述第二电容的两个电极板之间的电压为所述第二电压，所述多个辅助晶体管、所述第二电容、对应的第一副边绕组以及对应的主晶体管的控制电极串联连接，所述自驱动电路分别与对应的所述第一副边绕组的第一端和第二端以及所述多个辅助晶体管的控制电极连接；
    所述自驱动电路用于根据对应连接的第一副边绕组耦合产生的所述第一感应电动势和所述第二感应电动势，控制所述多个辅助晶体管中的一部分辅助晶体管导通，另一部辅助晶体管关断。
  7. 如权利要求6所述的驱动电路，其特征在于，所述多个辅助晶体管为两个，所述两个辅助晶体管分别为第一辅助晶体管和第二辅助晶体管；其中，所述第二电容的第一电极与对应的所述主晶体管的第一电极连接，所述第二电容的第二电极与所述第一辅助晶体管的第一电极连接，所述第一辅助晶体管的第二电极与对应的所述第一副边绕组的第一端连接，所述第二辅助晶体管的第一电极与对应的所述第一副边绕组的第二端连接，所述第二辅助晶体管的第二电极与对应的所述主晶体管的控制电极连接；
    所述自驱动电路包括：第一子驱动电路和第二子驱动电路；
    所述第一子驱动电路的第一端与所述第一辅助晶体管的控制电极连接，所述第一子驱动电路的第二端与对应的所述第一副边绕组的第一端连接，所述第一子驱动电路的第三端与对应的所述第一副边绕组的第二端连接；所述第一子驱动电路用于根据对应连接的第一副边绕组耦合产生的所述第一感应电动势和所述第二感应电动势，控制所述第一辅助晶体管导通和关断；
    所述第二子驱动电路的第一端与所述第二辅助晶体管的控制电极连接，所述第二子驱动电路的第二端与对应的所述第一副边绕组的第二端连接，所述第二子驱动电路的第三端与对应的所述第一副边绕组的第一端连接；所述第二子驱动电路用于根据对应连接的第一副边绕组耦合产生的所述第一感应电动势和所述第二感应电动势，控制所述第二辅助晶体管导通和关断。
  8. 如权利要求7所述的驱动电路，其特征在于，所述第一子驱动电路包括：第一二极管、第一电阻以及第二电阻；
    所述第一电阻的第一端为所述第一子驱动电路的第一端，所述第二电阻的第一端为所述第一子驱动电路的第二端，所述第一二极管的正极为所述第一子驱动电路的第三端，所述第一二极管的负极分别与所述第一电阻的第二端和所述第二电阻的第二端连接。
  9. 如权利要求7所述的驱动电路，其特征在于，所述第二子驱动电路包括：第二二极管、第三电阻以及第四电阻；
    所述第三电阻的第一端为所述第二子驱动电路的第一端，所述第四电阻的第一端为所述第二子驱动电路的第二端，所述第二二极管的正极为所述第二子驱动电路的第三端，所述第二二极管的负极分别与所述第三电阻的第二端和所述第四电阻的第二端连接。
  10. 如权利要求7-9任一项所述的驱动电路，其特征在于，对于所述N个主晶体管中，串联连接于接地端的M个主晶体管，将所述M个主晶体管定义为依次串联的第1主晶体管至第M主晶体管；其中，所述第1主晶体管直接与所述接地端连接，所述第1主晶体管对应的第二电容的第二电极还与所述原边绕组的第一端连接；
    所述第m主晶体管对应的充放电控制电路还包括第一自举二极管；其中，所述第m主晶体管对应的充放电控制电路中，所述第一自举二极管的负极与所述第二电容的第二电极连接；并且，所述第m主晶体管对应的充放电控制电路中的所述第一自举二极管的正极，与所述第m-1主晶体管对应的充放电控制电路中的所述第二电容的第二电极连接；2≤m≤M，2≤M≤N，m和M均为整数。
  11. 如权利要求7-9任一项所述的驱动电路，其特征在于，所述耦合电路还包括第二副边绕组，所述原边绕组和所述第二副边绕组之间互相耦合，且所述第二副边绕组根据所述第一电压耦合产生第一感应电动势，根据所述第二电压耦合产生第二感应电动势；
    所述驱动电路还包括储能电容和第二自举二极管；其中，所述第二自举二极管的正极与所述第二副边绕组的第一端连接，所述第二自举二极管的负极与所述储能电容的第一电极连接，所述储能电容的第二电极分别与所述第二副边绕组的第二端以及接地端连接；
    所述第二电容的第二电极还与所述储能电容的第一电极连接。
  12. 如权利要求11所述的驱动电路，其特征在于，对于所述N个主晶体管中，串联连接于所述接地端的K个主晶体管，将所述K个主晶体管定义为依次串联的第1主晶体管至第K主晶体管；其中，所述第1主晶体管直接与所述接地端连接，所述第1主晶体管对应的第二电容的第二电极与所述储能电容的第一电极直接连接；
    所述第k主晶体管对应的充放电控制电路还包括第三自举二极管；其中，所述第k主晶体管对应的充放电控制电路中，所述第三自举二极管的负极与所述第二电容的第二电极连接；并且，所述第k主晶体管对应的充放电控制电路中的所述第三自举二极管的正极，与所述第k-1主晶体管对应的充放电控制电路中的所述第二电容的第二电极连接；2≤k≤K，2≤K≤N，k和K均为整数。
  13. 一种电源模块，其特征在于，包括转换电路和驱动电路；所述驱动电路为如权利要求1-12任一项所述的驱动电路；
    所述驱动电路用于驱动所述转换电路中的主晶体管。
  14. 一种电子设备，其特征在于，包括如权利要求13所述的电源模块及负载模块，所述电源模块与所述负载模块电性连接。
  15. 一种驱动电路的控制方法，应用于如权利要求1-12任一项所述的驱动电路，其特征在于，所述控制方法包括；
    对所述电压控制电路加载多个控制脉冲信号，且所述多个控制脉冲信号中的第一部分控制脉冲信号为无效电平，第二部分控制脉冲信号为有效电平，控制所述电压控制电路控制流经所述原边绕组的电流正向增加至正向电流最大值，并驱动所述原边绕组产生第二电压，所述N个第一副边绕组中的至少一个第一副边绕组根据所述第二电压耦合产生第二感应电动势，所述N个充放电控制电路中的至少一个充放电控制电路根据对应连接的第一副边绕组耦合产生的所述第二感应电动势，控制对应连接的所述主晶体管的控制电极进行充电或放电；
    对所述电压控制电路加载多个控制脉冲信号，且所述多个控制脉冲信号均为无效电平，控制所述电压控制电路控制流经所述原边绕组的电流由所述正向电流最大值变化为零，并驱动所述原边绕组产生第一电压，所述N个第一副边绕组中的至少一个第一副边绕组根据所述第一电压耦合产生第一感应电动势，所述N个充放电控制电路中的至少一个充放电控制电路根据对应连接的第一副边绕组耦合产生的所述第一感应电动势，控制对应连接的所 述主晶体管的控制电极进行充电或放电；
    对所述电压控制电路加载多个控制脉冲信号，且所述多个控制脉冲信号中的第一部分控制脉冲信号为有效电平，第二部分控制脉冲信号为无效电平，控制所述电压控制电路控制流经所述原边绕组的电流反向增加至反向电流最大值，并驱动所述原边绕组产生所述第一电压，所述N个第一副边绕组中的至少一个第一副边绕组根据所述第一电压耦合产生第一感应电动势，所述N个充放电控制电路中的至少一个充放电控制电路根据对应连接的第一副边绕组耦合产生的所述第一感应电动势，控制对应连接的所述主晶体管的控制电极进行充电或放电；
    对所述电压控制电路加载多个控制脉冲信号，且所述多个控制脉冲信号均为无效电平，控制所述电压控制电路控制流经所述原边绕组的电流由所述反向电流最大值变化为零，并驱动所述原边绕组产生所述第二电压，所述N个第一副边绕组中的至少一个第一副边绕组根据所述第二电压耦合产生第二感应电动势，所述N个充放电控制电路中的至少一个充放电控制电路根据对应连接的第一副边绕组耦合产生的所述第二感应电动势，控制对应连接的所述主晶体管的控制电极进行充电或放电。
PCT/CN2023/093221 2022-07-27 2023-05-10 驱动电路、控制方法、电源模块及电子设备 WO2024021762A1 (zh)

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