WO2024021212A1 - 一种具有前馈偏置校正电路的新型差分放大器及设备 - Google Patents

一种具有前馈偏置校正电路的新型差分放大器及设备 Download PDF

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Publication number
WO2024021212A1
WO2024021212A1 PCT/CN2022/114638 CN2022114638W WO2024021212A1 WO 2024021212 A1 WO2024021212 A1 WO 2024021212A1 CN 2022114638 W CN2022114638 W CN 2022114638W WO 2024021212 A1 WO2024021212 A1 WO 2024021212A1
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differential amplifier
resistor
circuit
amplifier
common
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PCT/CN2022/114638
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English (en)
French (fr)
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维拉亚历山大
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上海韦孜美电子科技有限公司
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Publication of WO2024021212A1 publication Critical patent/WO2024021212A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit

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  • the technical field of differential amplifiers in the embodiments of this application specifically relates to a new type of differential amplifier and equipment with a feedforward bias correction circuit.
  • a differential amplifier is a circuit that amplifies the difference between two input voltages. It is a direct-coupled amplifier with a small zero-point drift. It is often used for DC amplification. It can have balanced (the term "balanced” means differential) input and output , it can also be single-ended (unbalanced) input and output. It is often used to realize the mutual conversion of balanced and unbalanced circuits. It is a basic unit of various integrated circuits.
  • the effective bias voltage of the amplifier is related to the common-mode voltage output.
  • the common-mode voltage output produces an unacceptably large offset, resulting in low accuracy of the differential amplifier.
  • embodiments of the present application provide a new type of differential amplifier and equipment with a feedforward bias correction circuit to solve the problem that in the prior art, due to a very small input signal, the common-mode voltage output produces an unacceptably large offset. This leads to the technical problem of lower accuracy of the differential amplifier.
  • the embodiment of the present application provides a differential amplifier with a feedforward offset correction circuit, which is characterized in that it includes a differential amplifier and an offset correction circuit;
  • the differential amplifier includes an operational amplifier, the input terminal of the bias correction circuit is connected to the high-level input terminal and the low-level input terminal of the differential amplifier respectively, the output terminal of the bias correction circuit is connected to the operational amplifier, and the bias correction circuit output terminal is connected to the operational amplifier.
  • the setting correction circuit dynamically adjusts the common-mode voltage output of the differential amplifier according to the voltage at the input terminal of the differential amplifier.
  • the differential amplifier further includes a first resistor, a second resistor, a first feedback circuit and a second feedback circuit;
  • the first end of the first resistor is connected to the high-level input end of the differential amplifier, the second end of the first resistor is connected to the first input end of the operational amplifier, and the first end of the second resistor is connected to the low-level input end of the differential amplifier.
  • the flat input end is connected, the second end of the second resistor is connected to the second input end of the operational amplifier, the first end of the first feedback circuit is connected to the first input end of the operational amplifier, the first end of the second feedback circuit is connected to The second input end of the operational amplifier is connected, and the second end of the first feedback circuit and the second end of the second feedback circuit are respectively connected to the output end of the operational amplifier.
  • the bias correction circuit includes a clamp voltage setting circuit and a common mode voltage adjustment circuit
  • the first end of the clamp voltage setting circuit is connected to the reference voltage setting circuit
  • the second end of the clamp voltage setting circuit is connected to the first input end of the common mode voltage adjustment circuit
  • the first input end of the common mode voltage adjustment circuit is connected to The high-level input end of the differential amplifier is connected
  • the second input end of the common-mode voltage adjustment circuit is connected to the low-level input end of the differential amplifier
  • the output end of the common-mode voltage adjustment circuit is connected to the operational amplifier
  • the clamp voltage setting circuit is used to set the clamp voltage of the common mode voltage adjustment circuit.
  • the clamp voltage setting circuit includes a buffer amplifier and a third resistor.
  • the first input terminal of the buffer amplifier is connected to the reference voltage setting circuit.
  • the second input terminal of the buffer amplifier is connected to the buffer amplifier.
  • a common terminal is connected between the amplifier output terminal and the first terminal of the third resistor, and the second terminal of the third resistor is connected to the high-level input terminal of the common-mode voltage adjustment circuit.
  • the common mode voltage adjustment circuit includes a fourth resistor, a fifth resistor and a differential amplifier
  • the first end of the fourth resistor is connected to the high-level input end of the differential amplifier, the second end of the fourth resistor is connected to the first input end of the differential amplifier, and the first end of the fifth resistor is connected to the high-level input end of the differential amplifier.
  • the low-level input end of the differential amplifier is connected, and the second end of the fifth resistor is connected to the second input end of the differential amplifier; the output end of the differential amplifier is connected to the operational amplifier to set the reference common mode voltage set by the differential amplifier. Input to op amp.
  • the differential amplifier is an instrumentation amplifier.
  • the common-mode voltage adjustment circuit further includes a second feedback circuit, between the first end of the second feedback circuit and the second end of the fifth resistor and the second input end of the differential amplifier. Public connection.
  • embodiments of the present application provide a new type of differential amplifier and equipment with a feedforward bias correction circuit.
  • the bias correction circuit Through the bias correction circuit, the common mode voltage output of the differential amplifier is dynamically adjusted according to the input voltage, thereby greatly enabling Reduce the input voltage error of the differential amplifier caused by the common-mode voltage output offset, allowing high-precision detection of very small input signals, assisting the common-mode adjustment channel to track the common-mode voltage output, thereby reducing the common-mode voltage output offset. Improve the accuracy of differential amplifiers.
  • an embodiment of the present application further provides a device, including the differential amplifier described in the first aspect.
  • Figure 1 is a schematic structural diagram of a differential amplifier provided by the prior art
  • Figure 2 is a schematic structural diagram of a differential amplifier with a feedforward bias correction circuit provided by an embodiment of the present application
  • Figure 3 is a schematic structural diagram of a differential amplifier used in a battery charger according to an embodiment of the present application
  • FIG. 4 is a schematic structural diagram of a differential amplifier used in a battery charger according to an embodiment of the present application.
  • Figure 1 is a circuit diagram of a differential amplifier provided by the prior art.
  • the differential amplifier in the prior art includes an operational amplifier 105, a first resistor (R1) 101, a second resistor (R1) 102, a first feedback Circuit (R2) 103 and second feedback circuit (R2) 104;
  • the first end of the first resistor 101 is connected to the high-level V in+ input end of the differential amplifier, the second end of the first resistor 101 is connected to the first input end a1 of the operational amplifier 105, and the second resistor 102 is connected to the first input end a1 of the operational amplifier 105.
  • the terminal is connected to the low-level V in- input terminal of the differential amplifier, the second terminal of the second resistor 102 is connected to the second input terminal a2 of the operational amplifier 105, and the first terminal of the first feedback circuit 103 is connected to the second input terminal a2 of the operational amplifier 105.
  • An input terminal a1 is connected, the first terminal of the second feedback circuit 104 is connected to the second input terminal a2 of the operational amplifier 105, the second terminal of the first feedback circuit 103 and the second terminal of the second feedback circuit 104 are respectively connected to The output terminal b of the operational amplifier 105 is connected.
  • the existing differential amplifier has a common-mode voltage input V cmi , a common-mode voltage output V cmo , a high-level V in+ input terminal, a low-level V in- input terminal, a high-level V out + output terminal and a low-level V out -Output side, if the open-loop gain of the differential amplifier approaches infinity, the output voltage of the differential amplifier (V out+ -V out- ) is calculated by the following formula:
  • R1 is the resistance value of the first resistor 101 and the second resistor 102, and the resistance values of the first resistor 101 and the second resistor 102 are the same.
  • R2 is the resistance of the first feedback circuit 103 and the second feedback circuit 104, and the resistance of the first feedback circuit 103 and the second feedback circuit 104 is the same.
  • the first resistor (R1) 101, the second Resistor (R1) 102, first feedback circuit (R2) 103 and second feedback circuit (R2) 104 are used to set the gain of the differential amplifier.
  • the value of R2/R1 is used to set the gain ratio of the closed-loop differential amplifier.
  • the gain ratio can be from The gain can also be larger from 20 times to 100 times, and the embodiments of the present application do not limit this.
  • V cmo is the common mode voltage output
  • R1 is the resistance of the first resistor 101 and the second resistor 102
  • the resistance of the first resistor 101 and the second resistor 102 is the same
  • R2 is the first feedback circuit 103 and the second resistor 102.
  • the resistance of the feedback circuit 104 is the same, and the resistance of the first feedback circuit 103 and the second feedback circuit 104 is the same.
  • a resistor R2 is represented by the value of R2 and the value of (1+ ⁇ ) ⁇ R2, where ⁇ is the error change between the two R2s.
  • a similar analysis can be done for R1, but the results are very similar.
  • Common-mode voltage output V cmo is multiplied by the gain of the differential amplifier to obtain the output error V out, ⁇ ,cm of the differential amplifier.
  • the output error V out, ⁇ , cm of the differential amplifier is mainly composed of the first resistor (R1) 101, the second resistor (R1) 102, the first feedback circuit (R2) 103, the second feedback circuit Circuit (R2) 104 and the common mode voltage output V cmo are determined.
  • the embodiment of the present application provides a new differential amplifier with a feedforward offset correction circuit, including a differential amplifier 21 and an offset correction circuit 22;
  • the differential amplifier 21 includes an operational amplifier 205;
  • the input terminal c and the input terminal d of the offset correction circuit 22 are respectively connected to the high-level input terminal V in+ and the low-level input terminal V in- of the differential amplifier.
  • the output terminal m of the offset correction circuit 22 is connected to the operational amplifier. 205 is connected, the offset correction circuit 22 dynamically adjusts the common mode voltage output of the differential amplifier according to the voltage at the input terminal of the differential amplifier 21 .
  • the differential amplifier 21 also includes a first resistor (R1) 201, a second resistor (R1) 202, a first feedback circuit (R2) 203 and a second feedback circuit (R2) 204;
  • the first terminal of the first resistor (R1) 201 is connected to the high-level input terminal V in+ of the differential amplifier, and the second terminal of the first resistor (R1) 201 is connected to the first input terminal e of the operational amplifier 205.
  • the first terminal of the second resistor (R1) 202 is connected to the low-level input terminal V in- of the differential amplifier, and the second terminal of the second resistor (R1) 202 is connected to the second input terminal f of the operational amplifier 205.
  • the first end of a feedback circuit (R2) 203 is connected to the first input end e of the operational amplifier 205.
  • the first end of the second feedback circuit (R2) 204 is connected to the second input end f of the operational amplifier 205.
  • the first feedback circuit (R2) 204 has a first end connected to the second input end f of the operational amplifier 205.
  • the second terminal of the circuit (R2) 203 and the second terminal of the second feedback circuit (R2) 204 are respectively connected to the output terminal n of the operational amplifier 205.
  • the offset correction circuit 22 includes a clamp voltage setting circuit 22-1 and a common mode voltage adjustment circuit 22-2; the first end of the clamp voltage setting circuit 22-1 is connected to the reference voltage setting circuit 212.
  • the second end of the bit voltage setting circuit 22-1 is connected to the first input end k of the common mode voltage adjustment circuit 22-2, and the first input end k of the common mode voltage adjustment circuit 22-2 is connected to the high level input of the differential amplifier.
  • the terminal V in+ is connected, the second input terminal l of the common mode voltage adjustment circuit 22-2 is connected with the low-level input terminal V in- of the differential amplifier, and the output terminal m of the common mode voltage adjustment circuit 22-2 is connected with The operational amplifier 205 is connected, and the clamp voltage setting circuit 22-1 is used to set the clamp voltage of the common mode voltage adjustment circuit 22-2.
  • the clamp voltage setting circuit 22-1 includes a buffer amplifier 206 and a third resistor (r2) 207.
  • the first input terminal h of the buffer amplifier 206 is connected to the reference voltage setting circuit 212.
  • the second input terminal of the buffer amplifier 206 is i is connected to the common terminal between the output terminal j of the buffer amplifier 206 and the first terminal of the third resistor (r2) 207, and the second terminal of the third resistor (r2) 207 and the fourth resistor (r1) 208
  • the two terminals are connected to the common terminal between the first input terminal k of the differential amplifier 210 .
  • the buffer amplifier 206 is used to prevent the reference voltage setting circuit 212 from overloading.
  • the reference voltage setting circuit 212 overload usually occurs in the band gap circuit.
  • the reference voltage setting circuit 212 also has a high impedance. Any overload will affect the reference voltage setting circuit 212.
  • the accuracy of the reference voltage (VREF) of the reference voltage setting circuit 212 can be maintained by using the buffer amplifier 206, and the third resistor (r2) 207 can reduce the clamping voltage of the offset correction circuit 22.
  • the common mode voltage adjustment circuit 22-2 includes a fourth resistor (r1) 208, a fifth resistor (r1) 209 and a differential amplifier 210; the first end of the fourth resistor (r1) 208 is connected to the first end of the differential amplifier.
  • the high-level input terminal V in+ is connected, the second terminal of the fourth resistor (r1) 208 is connected to the first input terminal k of the differential amplifier 210; the first terminal of the fifth resistor (r1) 209 is connected to the differential amplifier 210
  • the low-level input terminal V in- is connected, the second terminal of the fifth resistor (r1) 209 is connected to the second input terminal i of the differential amplifier 210; the output terminal m of the differential amplifier 210 is connected to the operational amplifier 205,
  • the differential amplifier 210 is an instrumentation amplifier.
  • the differential amplifier 210 differs between the high-level input terminal V in+ and the low-level input terminal V in- of the differential amplifier and the reference voltage of the reference voltage setting circuit 212 (VREF), the reference common mode voltage VREF_VCM output by the differential amplifier 210 is calculated according to the following formula (III):
  • the reference common mode voltage VREF_VCM is set by the instrumentation amplifier 210.
  • the common mode reference voltage VREF_VCM set by the common mode voltage setting circuit is used to adjust the common mode voltage output of the differential amplifier.
  • the reference common mode voltage VREF_VCM is also the value of the differential amplifier.
  • the other input terminal is used to adjust the common-mode voltage output of the differential amplifier.
  • the reference common-mode voltage is set according to the input voltage V in (V in+ -V in- ) through the instrumentation amplifier 210 VREF_VCM.
  • the common mode voltage adjustment circuit 22-2 also includes a second feedback circuit (r2) 211.
  • the difference between the first terminal of the second feedback circuit (r2) 211 and the second terminal of the fourth resistor (r1) 209 is The common terminal between the second input terminal i of the dynamic amplifier 210 is connected.
  • the differential amplifier has a common-mode voltage input and output.
  • the common-mode voltage output will cause the accuracy of the differential amplifier to deteriorate.
  • This application implements The offset correction circuit 22 in the example differential amplifier adjusts the common-mode voltage output according to the input voltage to reduce the common-mode error.
  • Figure 3 shows that the differential amplifier provided by the embodiment of the present application is applied to a battery charger with a very low inductive resistance.
  • high-precision detection and current adjustment can be performed, so that the battery life can be extended. , charging with higher precision, preventing battery damage and reducing fire hazards.
  • the negative electrode of the battery 215 is connected to the fixed voltage node through the sensing resistor RSNS, which can measure the battery current more accurately.
  • the output terminal n of the operational amplifier 205 is connected to the analog-to-digital converter ADC 212, and the analog-to-digital converter ADC 212 is A type of device that converts continuous signals in analog form into discrete signals in digital form.
  • the analog-to-digital converter ADC 212 is connected to a digital controller 213.
  • the digital controller 213 has a program to complete the conversion of input signals to output signals.
  • the digital controller 213 uses computer software programming to complete a specific control algorithm.
  • the digital controller 213 is connected to the positive electrode of the battery 215 through a DC-DC converter 214.
  • the DC/DC converter 214 is used to convert the input voltage into an effective output fixed voltage.
  • the battery charger uses the differential amplifier provided by the embodiment of the present application to regulate the current of the battery to prevent damage to the battery.
  • the sensing resistor RSNS is directly connected in the current path, the sensing resistor RSNS is used to generate a voltage drop to maintain low impedance and reduce power loss. Therefore, a high-fidelity amplifier is needed to detect the low voltage passing through the sensing resistor RSNS, and amplify the voltage so that the analog-to-digital converter ADC 212 can read correctly.
  • the gain of the differential amplifier 21 can be from 20 times to 100 times. The specific gain multiple Depends on the battery current requirements, the analog-to-digital converter ADC212 input requirements and the selection of the sensing resistor RSNS.
  • Instrumentation amplifier 210 is configured to improve differential amplifier accuracy by sampling the input voltage while regulating the common-mode voltage output of differential amplifier 21 .
  • the differential amplifier provided by the embodiment of the present application is used in a battery charger.
  • the battery average current mode charger can have multiple high-precision differential amplifiers, and each differential amplifier has its own bias correction circuit.
  • the same structure can be used to accurately measure the battery voltage where the current is accurately measured.
  • a new differential amplifier 2 is used to detect the battery current
  • another new differential amplifier 1 is used to detect the inductor current.
  • the negative electrode of the battery 215 is connected to the fixed voltage node, and the positive electrode is connected to one of the new differential amplifiers 1 in this application.
  • the differential amplifier 1 includes a differential amplifier 21 and a bias correction circuit 22.
  • the new differential amplifier 1 and the periodic current detection module 3 To detect the current of the battery, the output terminal of the periodic current detection module 3 is connected to the current error amplifier 5, and the output terminal of the current error amplifier 5 is connected to the input terminal of the pulse width modulator 217 to modulate the pulse width. The output terminal of the pulse width modulator 217 is connected to the input terminal of the pulse width modulator 217.
  • the voltage conversion logic module 6 is connected, and the buck conversion logic module 6 is connected to the inductor 218 and the resistor 219 in turn.
  • the new differential amplifier 1 is connected to both ends of the resistor 219 for detecting the current at both ends of the resistor 219.
  • both the differential amplifier 1 and the differential amplifier 1 have an offset correction circuit 22 to enhance the regulation control of the DC-DC converter loop.
  • the average current mode loop can be improved. Adjustment accuracy.
  • an embodiment of the present application further provides a device, including the differential amplifier described in the first aspect.

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Abstract

一种具有前馈偏置校正电路的新型差分放大器及设备，通过偏置校正电路根据输入电压动态调整差分放大器的共模电压输出，进而可以大大减少共模电压输出偏移所带来的差分放大器的输入电压误差，使得可以高精度检测很小的输入信号，辅助共模调节通道以跟踪共模电压输出，从而减少共模电压输出偏移，提高差分放大器的精度。

Description

一种具有前馈偏置校正电路的新型差分放大器及设备 技术领域
本申请实施例差分放大器技术领域，具体涉及一种具有前馈偏置校正电路的新型差分放大器及设备。
背景技术
差分放大器能把两个输入电压的差值加以放大的电路，这是一种零点漂移很小的直接耦合放大器，常用于直流放大，它可以是平衡(术语"平衡"意味着差分)输入和输出，也可以是单端(非平衡)输入和输出，常用来实现平衡与不平衡电路的相互转换，是各种集成电路的一种基本单元。
在设计全差分放大器时，发现对放大器的有效偏置电压与共模电压输出有关，对于非常小的输入信号，共模电压输出产生一个不可接受大偏移量，从而导致差分放大器的精度较低。
发明内容
为此，本申请实施例提供一种具有前馈偏置校正电路的新型差分放大器及设备，以解决现有技术中由于非常小的输入信号，共模电压输出产生一个不可接受大偏移量，从而导致差分放大器的精度较低的技术问题。
为了实现上述目的，本申请实施例提供如下技术方案：
根据本申请实施例的第一方面，本申请实施例提供了一种具有前馈偏置校正电路的差分放大器，其特征在于，包括差分放大器和偏置校正电路；
所述差分放大器包括运算放大器，所述偏置校正电路输入端分别与差分放大器的高电平输入端和低电平输入端连接，所述偏置校正电路输出端与运算放大器连接，所述偏置校正电路根据差分放大器输入端电压动态调整差分放大器的共模电压输出。
作为本申请一优选实施例，所述差分放大器还包括第一电阻，第二电阻， 第一反馈电路和第二反馈电路；
所述第一电阻第一端与差分放大器的高电平输入端连接，所述第一电阻第二端与运算放大器第一输入端连接，所述第二电阻第一端与差分放大器的低电平输入端连接，所述第二电阻第二端与运算放大器第二输入端连接，所述第一反馈电路第一端与运算放大器第一输入端连接，所述第二反馈电路第一端与运算放大器第二输入端连接，所述第一反馈电路第二端和所述第二反馈电路第二端分别与运算放大器输出端连接。
作为本申请一优选实施例，所述偏置校正电路包括钳位电压设置电路和共模电压调节电路；
所述钳位电压设置电路第一端与参考电压设置电路连接，所述钳位电压设置电路第二端与共模电压调节电路第一输入端连接，所述共模电压调节电路第一输入端与所述差分放大器的高电平输入端连接，所述共模电压调节电路第二输入端与所述差分放大器的低电平输入端连接，所述共模电压调节电路输出端与运算放大器连接，所述钳位电压设置电路用于设置所述共模电压调节电路的钳位电压。
作为本申请一优选实施例，所述钳位电压设置电路包括缓冲放大器和第三电阻，所述缓冲放大器第一输入端与参考电压设置电路连接，所述缓冲放大器第二输入端与所述缓冲放大器输出端和第三电阻第一端之间公共端连接，所述第三电阻第二端与共模电压调节电路的高电平输入端连接。
作为本申请一优选实施例，所述共模电压调节电路包括第四电阻，第五电阻和差动放大器；
所述第四电阻第一端与所述差分放大器的高电平输入端连接，所述第四电阻第二端与差动放大器第一输入端连接，所述第五电阻第一端与所述差分放大器的低电平输入端连接，所述第五电阻第二端与差动放大器第二输入端连接；所述差动放大器输出端与运算放大器连接以便将差动放大器设置的参考共模电压输入至运算放大器。
作为本申请一优选实施例，所述差动放大器为仪表放大器。
作为本申请一优选实施例，所述共模电压调节电路还包括第二反馈电路，所述第二反馈电路第一端与第五个电阻第二端和差动放大器第二输入端之间的公共端连接。
与现有技术相比，本申请实施例提供了一种具有前馈偏置校正电路的新型差分放大器及设备，通过偏置校正电路根据输入电压动态调整差分放大器的共模电压输出，进而可以大大减少共模电压输出偏移所带来的差分放大器的输入电压误差，使得可以高精度检测很小的输入信号，辅助共模调节通道以跟踪共模电压输出，从而减少共模电压输出偏移，提高差分放大器的精度。
第二方面，本申请实施例还提供了一种设备，包括第一方面所述的差分放大器。
与现有技术相比，本申请实施例提供一种设备的有益效果与第一方面提供的差分放大器相同，在此不再赘述。
附图说明
为了更清楚地说明本申请的实施方式或现有技术中的技术方案，下面将对实施方式或现有技术描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是示例性的，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图引伸获得其它的实施附图。
本说明书所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技术的人士了解与阅读，并非用以限定本申请可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本申请所能产生的功效及所能达成的目的下，均应仍落在本申请所揭示的技术内容得能涵盖的范围内。
图1为现有技术提供的一种差分放大器结构示意图；
图2为本申请实施例提供的一种具有前馈偏置校正电路的差分放大器结构示意图；
图3为本申请实施例提供的差分放大器使用在电池充电器中的结构示意图；
图4为本申请实施例提供的差分放大器使用在电池充电器中的结构示意图。
具体实施方式
以下由特定的具体实施例说明本申请的实施方式，熟悉此技术的人士可由本说明书所揭露的内容轻易地了解本申请的其他优点及功效，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
如图1所示，图1为现有技术提供的差分放大器的电路图，现有技术中的差分放大器包括运算放大器105，第一电阻(R1)101，第二电阻(R1)102，第一反馈电路(R2)103和第二反馈电路(R2)104；
所述第一电阻101第一端与差分放大器的高电平V in+输入端连接，所述第一电阻101第二端与运算放大器105第一输入端a1连接，所述第二电阻102第一端与差分放大器的低电平V in-输入端连接，所述第二电阻102第二端与运算放大器105第二输入端a2连接，所述第一反馈电路103第一端与运算放大器105第一输入端a1连接，所述第二反馈电路104第一端与运算放大器105第二输入端a2连接，所述第一反馈电路103第二端和所述第二反馈电路104第二端分别与运算放大器105输出端b连接。
现有的差分放大器具有共模电压输入V cmi、共模电压输出V cmo、高电平V in+输入端、低电平V in-输入端、高电平V out+输出端和低电平V out-输出端，如果差分放大器的开环增益趋于无穷大，则差分放大器的输出电压(V out+-V out-)通过以下公式计算：
Figure PCTCN2022114638-appb-000001
其中，R1为第一电阻101和第二电阻102的阻值，且第一电阻101和第二电阻102的阻值相同。R2为第一反馈电路103和第二反馈电路104的阻值， 且第一反馈电路103和第二反馈电路104的阻值相同，在差分放大器电路中，第一电阻(R1)101，第二电阻(R1)102，第一反馈电路(R2)103和第二反馈电路(R2)104用来设置差分放大器的增益，R2/R1的值用于设置闭环差分放大器的增益比，增益比可以从20倍到100倍，增益也可以更大，本申请实施例对此不做限制。
假设差分放大器的开环增益趋于无穷大，而共模电压输出的偏移量可以忽略不计，由于单个电阻R2相互之间的失配而引起的差分放大器的输出误差V out,ε,cm通过以下公式计算：
Figure PCTCN2022114638-appb-000002
其中，V cmo为共模电压输出，R1为第一电阻101和第二电阻102的阻值，且第一电阻101和第二电阻102的阻值相同，R2为第一反馈电路103和第二反馈电路104的阻值，且第一反馈电路103和第二反馈电路104的阻值相同，在集成电路的实际应用中，由于制造过程中的细微变化，使两个器件不完全一样，所以两个电阻R2通过R2的值和(1+σ)×R2的值进行表示，其中，σ是两个R2之间误差变化，对于R1也可以做类似的分析，但结果非常相似，共模电压输出V cmo与差分放大器的增益相乘得到差分放大器的输出误差V out,ε,cm。
从上述公式(Ⅱ)可以得出差分放大器的输出误差V out,ε,cm主要由第一电阻(R1)101，第二电阻(R1)102，第一反馈电路(R2)103，第二反馈电路(R2)104及共模电压输出V cmo决定。
从现有技术可知，为了减小差分放大器的输出误差V out,ε,cm以提高差分放大器的精度需要降低共模电压输出V cmo来实现，本申请实施例提供了以下技术方案。
如图2所示，本申请实施例提供了一种具有前馈偏置校正电路的新型差分放大器，包括差分放大器21和偏置校正电路22；
所述差分放大器21包括运算放大器205；
所述偏置校正电路22输入端c和输入端d分别与差分放大器的高电平输入端 V in+和低电平输入端V in-连接，所述偏置校正电路22输出端m与运算放大器205连接，所述偏置校正电路22根据差分放大器21输入端电压动态调整差分放大器的共模电压输出。
所述差分放大器21还包括第一电阻(R1)201，第二电阻(R1)202，第一反馈电路(R2)203和第二反馈电路(R2)204；
所述第一电阻(R1)201第一端与差分放大器的高电平输入端V in+连接，所述第一电阻(R1)201第二端与运算放大器205第一输入端e连接，所述第二电阻(R1)202第一端与差分放大器的低电平输入端V in-连接，所述第二电阻(R1)202第二端与运算放大器205第二输入端f连接，所述第一反馈电路(R2)203第一端与运算放大器205第一输入端e连接，所述第二反馈电路(R2)204第一端与运算放大器205第二输入端f连接，所述第一反馈电路(R2)203第二端和所述第二反馈电路(R2)204第二端分别与运算放大器205输出端n连接。
所述偏置校正电路22包括钳位电压设置电路22-1和共模电压调节电路22-2；所述钳位电压设置电路22-1第一端与参考电压设置电路212连接，所述钳位电压设置电路22-1第二端与共模电压调节电路22-2第一输入端k连接，所述共模电压调节电路22-2第一输入端k与所述差分放大器的高电平输入端V in+连接，所述共模电压调节电路22-2第二输入端l与所述差分放大器的低电平输入端V in-连接，所述共模电压调节电路22-2输出端m与运算放大器205连接，所述钳位电压设置电路22-1用于设置所述共模电压调节电路22-2的钳位电压。
所述钳位电压设置电路22-1包括缓冲放大器206和第三电阻(r2)207，所述缓冲放大器206第一输入端h与参考电压设置电路212连接，所述缓冲放大器206第二输入端i与所述缓冲放大器206输出端j与第三电阻(r2)207第一端之间公共端连接，所述第三电阻(r2)207第二端与所述第四电阻(r1)208第二端与差动放大器210第一输入端k之间的公共端连接。
所述缓冲放大器206用于防止参考电压设置电路212过载，参考电压设置电路212过载通常产生于带隙电路，参考电压设置电路212过载也具有很高的阻抗， 任何过载都会影响参考电压设置电路212的基准电压(VREF)，通过使用缓冲放大器206可以保持参考电压设置电路212的基准电压(VREF)的精度，所述第三电阻(r2)207可以实现降低偏置校正电路22的钳位电压。
所述共模电压调节电路22-2包括第四电阻(r1)208，第五电阻(r1)209和差动放大器210；所述第四电阻(r1)208第一端与所述差分放大器的高电平输入端V in+连接，所述第四电阻(r1)208第二端与差动放大器210第一输入端k连接；所述第五电阻(r1)209第一端与所述差分放大器的低电平输入端V in-连接，所述第五电阻(r1)209第二端与差动放大器210第二输入端i连接；所述差动放大器210输出端m与运算放大器205连接，所述差动放大器210为仪表放大器，所述差动放大器210将差分放大器的高电平输入端V in+和低电平输入端V in-作差后与所述参考电压设置电路212的基准电压(VREF)求和，所述差动放大器210输出的参考共模电压VREF_VCM根据以下公式(Ⅲ)计算：
Figure PCTCN2022114638-appb-000003
所述参考共模电压VREF_VCM通过仪表放大器210进行设置，所述共模电压设置电路设置的共模参考电压VREF_VCM用于调节差分放大器共模电压输出，所述参考共模电压VREF_VCM也为差分放大器的另一输入端，以便调节差分放大器共模电压输出，为了减小共模电压输出对差分放大器的影响，通过仪表放大器210根据输入电压V in(V in+-V in-)进行设置参考共模电压VREF_VCM。
所述共模电压调节电路22-2还包括第二反馈电路(r2)211，所述第二反馈电路(r2)211第一端与所述第四个电阻(r1)209第二端与差动放大器210第二输入端i之间的公共端连接。
对于差分放大器都有一个共模电压输入和输出，当第一反馈电路(R2)203和第二反馈电路(R2)204失配时，共模电压输出将导致差分放大器精度变差，本申请实施例差分放大器中的偏置校正电路22根据输入电压进行调节 共模电压输出以减少共模误差。
如图3所示，图3为本申请实施例提供的差分放大器应用到具有很低感应电阻的电池充电器中，通过本申请实施例可以进行很高精度探测并调节电流，使得可以延长电池寿命，以更高精度充电，防止电池损坏和减少起火危险。
在具体的电池充电器中，电池215负极通过感应电阻RSNS与固定电压节点连接，能够更精确地测量电池电流，运算放大器205输出端n与模拟数字转换器ADC 212连接，模拟数字转换器ADC212用于将模拟形式的连续信号转换为数字形式的离散信号的一类设备，所述模拟数字转换器ADC 212与数字控制器213连接，通常数字控制器213具有完成输入信号到输出信号换算的程序，数字控制器213利用计算机软件编程完成特定的控制算法，数字控制器213通过DC-DC转换器214与电池215的正极连接，DC/DC转换器214用于将输入电压转换为有效输出固定电压，电池充电器利用本申请实施例提供的差分放大器调节电池的电流，防止损坏电池。
在电池充电应用中，因为感应电阻RSNS直接连接在电流通路中，所述感应电阻RSNS用于产生一个压降，用于保持低阻抗和减少功率损耗。所以，就需要一个高保真放大器，用来检测通过感应电阻RSNS的低电压，并将电压放大使得模数转换器ADC 212正确读数，差分放大器21的增益可以从20倍到100倍，具体增益倍数取决于电池电流需求、模数转换器ADC212输入需求及感应电阻RSNS的选择。仪表放大器210配置在于通过采样输入电压，同时调节差分放大器21的共模电压输出来提高差分放大器精度。
如图4所示，将本申请实施例提供的差分放大器用于电池充电器中，电池平均电流模式充电器可以具有多个高精度差分放大器，每一个差分放大器都具有各自的偏置校正电路，在图3的实施例中，在精确测量电流处，可以使用同样的结构来精确测量电池电压，在图4中，使用一个新型差分放大器2检测电池电流，另外一个新型差分放大器1检测电感电流，电池215的负极与所述固定电压节点连接，正极与其中一个本申请中的新型差分放大器1连接，差分放大器1包括差分放大器21和偏置校正电路22，新型差分放大器1与周期电流检测模块3进行检测电池的电流，周期电流检测模块3输出端与电流误差放大 器5连接，电流误差放大器5输出端与脉冲宽度调制器217输入端连接，以调制脉冲宽度，脉冲宽度调制器217输出端与降压转换逻辑模块,6连接，降压转换逻辑模块6依次与电感218和电阻219连接，其中，新型差分放大器1与电阻219两端连接用于检测电阻219两端的电流。
本申请实施例中，差分放大器1和差分放大器1都有偏置校正电路22，以加强直流-直流转换器环路的调节控制，通过更精确地检测电感电流，可以提高平均电流模式环路的调节精度。通过本申请实施例可以进行很高精度探测并调节电流，使得可以延长电池寿命，以更高精度充电，防止电池损坏和减少起火危险。
第二方面，本申请实施例还提供了一种设备，包括第一方面所述的差分放大器。
与现有技术相比，本申请实施例提供一种设备的有益效果与第一方面提供的差分放大器相同，在此不再赘述。
虽然，上文中已经用一般性说明及具体实施例对本申请作了详尽的描述，但在本申请基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本申请精神的基础上所做的这些修改或改进，均属于本申请要求保护的范围。
Figure PCTCN2022114638-appb-000004
Figure PCTCN2022114638-appb-000005
Figure PCTCN2022114638-appb-000006

Claims (8)

  1. 一种具有前馈偏置校正电路的新型差分放大器，其特征在于，包括差分放大器和偏置校正电路；
    所述差分放大器包括运算放大器，所述偏置校正电路输入端分别与差分放大器的高电平输入端和低电平输入端连接，所述偏置校正电路输出端与运算放大器连接，所述偏置校正电路根据差分放大器输入端电压动态调整差分放大器的共模电压输出。
  2. 如权利要求1所述的一种具有前馈偏置校正电路的新型差分放大器，其特征在于，所述差分放大器还包括第一电阻，第二电阻，第一反馈电路和第二反馈电路；
    所述第一电阻第一端与差分放大器的高电平输入端连接，所述第一电阻第二端与运算放大器第一输入端连接，所述第二电阻第一端与差分放大器的低电平输入端连接，所述第二电阻第二端与运算放大器第二输入端连接，所述第一反馈电路第一端与运算放大器第一输入端连接，所述第二反馈电路第一端与运算放大器第二输入端连接，所述第一反馈电路第二端和所述第二反馈电路第二端分别与运算放大器输出端连接。
  3. 如权利要求1或2所述的一种具有前馈偏置校正电路的新型差分放大器，其特征在于，所述偏置校正电路包括钳位电压设置电路和共模电压调节电路；
    所述钳位电压设置电路第一端与参考电压设置电路连接，所述钳位电压设置电路第二端与共模电压调节电路第一输入端连接，所述共模电压调节电路第一输入端还与所述差分放大器的高电平输入端连接，所述共模电压调节电路第二输入端与所述差分放大器的低电平输入端连接，所述共模电压调节电路输出端与运算放大器连接，所述钳位电压设置电路用于设置所述共模电压调节电路的钳位电压。
  4. 如权利要求3所述的一种具有前馈偏置校正电路的新型差分放大器，其特征在于，所述钳位电压设置电路包括缓冲放大器和第三电阻，所述缓冲放大器第一输入端与参考电压设置电路连接，所述缓冲放大器第二输入端与所述 缓冲放大器输出端和第三电阻第一端之间公共端连接，所述第三电阻第二端与共模电压调节电路的高电平输入端连接。
  5. 如权利要求3所述的一种具有前馈偏置校正电路的新型差分放大器，其特征在于，所述共模电压调节电路包括第四电阻，第五电阻和差动放大器；
    所述第四电阻第一端与所述差分放大器的高电平输入端连接，所述第四电阻第二端与差动放大器第一输入端连接，所述第五电阻第一端与所述差分放大器的低电平输入端连接，所述第五电阻第二端与差动放大器第二输入端连接；所述差动放大器输出端与运算放大器连接以便将差动放大器设置的参考共模电压输入至运算放大器。
  6. 如权利要求5述的一种具有前馈偏置校正电路的新型差分放大器，其特征在于，所述差动放大器为仪表放大器。
  7. 如权利要求4至6任一项所述的一种具有前馈偏置校正电路的差分放大器，其特征在于，所述共模电压调节电路还包括第二反馈电路，所述第二反馈电路第一端与第五个电阻第二端和差动放大器第二输入端之间的公共端连接。
  8. 一种设备，其特征在于，包括如权利要求1至7任一项所述的差分放大器。
PCT/CN2022/114638 2022-07-29 2022-08-24 一种具有前馈偏置校正电路的新型差分放大器及设备 WO2024021212A1 (zh)

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US9231542B1 (en) * 2014-11-24 2016-01-05 Dialog Semiconductor (Uk) Limited Amplifier common-mode control method
CN109004911A (zh) * 2017-06-07 2018-12-14 亚德诺半导体集团 具有调节的共模抑制的差分放大器和具有改进的共模抑制比率的电路
CN110086437A (zh) * 2018-01-26 2019-08-02 华为技术有限公司 运算放大器和芯片
CN114236221A (zh) * 2021-10-13 2022-03-25 北京华峰测控技术股份有限公司 差分电压测量电路、装置及方法
CN114337557A (zh) * 2021-12-28 2022-04-12 上海集成电路研发中心有限公司 一种差分信号放大电路

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* Cited by examiner, † Cited by third party
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US9231542B1 (en) * 2014-11-24 2016-01-05 Dialog Semiconductor (Uk) Limited Amplifier common-mode control method
CN109004911A (zh) * 2017-06-07 2018-12-14 亚德诺半导体集团 具有调节的共模抑制的差分放大器和具有改进的共模抑制比率的电路
CN110086437A (zh) * 2018-01-26 2019-08-02 华为技术有限公司 运算放大器和芯片
CN114236221A (zh) * 2021-10-13 2022-03-25 北京华峰测控技术股份有限公司 差分电压测量电路、装置及方法
CN114337557A (zh) * 2021-12-28 2022-04-12 上海集成电路研发中心有限公司 一种差分信号放大电路

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