WO2024021010A1 - 应用于车辆中的控制系统及车辆 - Google Patents

应用于车辆中的控制系统及车辆 Download PDF

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Publication number
WO2024021010A1
WO2024021010A1 PCT/CN2022/108904 CN2022108904W WO2024021010A1 WO 2024021010 A1 WO2024021010 A1 WO 2024021010A1 CN 2022108904 W CN2022108904 W CN 2022108904W WO 2024021010 A1 WO2024021010 A1 WO 2024021010A1
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Prior art keywords
memory
data
processor
control system
vehicle
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PCT/CN2022/108904
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English (en)
French (fr)
Inventor
吴泽亮
王兴武
金瑜辉
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华为技术有限公司
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Priority to PCT/CN2022/108904 priority Critical patent/WO2024021010A1/zh
Publication of WO2024021010A1 publication Critical patent/WO2024021010A1/zh

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60W—CONJOINT CONTROL OF VEHICLE SUB-UNITS OF DIFFERENT TYPE OR DIFFERENT FUNCTION; CONTROL SYSTEMS SPECIALLY ADAPTED FOR HYBRID VEHICLES; ROAD VEHICLE DRIVE CONTROL SYSTEMS FOR PURPOSES NOT RELATED TO THE CONTROL OF A PARTICULAR SUB-UNIT
    • B60W50/00—Details of control systems for road vehicle drive control not related to the control of a particular sub-unit, e.g. process diagnostic or vehicle driver interfaces

Definitions

  • the present application relates to the field of smart car technology, and in particular, to a control system and a vehicle used in a vehicle.
  • the embodiment of the present application discloses a control system and a vehicle applied in a vehicle, which can meet increasingly demanding storage requirements.
  • the present application provides a control system applied in a vehicle, characterized in that the control system includes at least one processor, a first memory and a second memory, the first memory being pluggable with the At least one processor is connected, and the second memory is fixedly connected to the at least one processor;
  • the first memory is used to store first data
  • the second memory is used to store second data.
  • the first data and the second data have different update degrees, and the update degrees include update frequency and/or importance.
  • the fixed connection can be made by welding or other methods.
  • the first memory is a solid-state drive SSD memory card
  • the second memory is a universal flash UFS memory.
  • the control system applied to the vehicle includes a memory connected in a pluggable manner.
  • the memory can be replaced quickly, conveniently and in a timely manner, so that there is no need to worry about the memory's erase and write times being used up, and the memory can be updated in a timely manner.
  • the data in the system meets the storage requirements for high data update frequency and provides guarantee for accurate driving control and safe driving of smart cars.
  • the pluggable memory solution in this application meets the requirements of vehicle regulations, such as the above-mentioned vehicle
  • vehicle regulations such as the above-mentioned vehicle
  • the pluggable memory interfaces and plugged memories included in the control system are in compliance with vehicle regulations.
  • the interface and the memory can also be connected structurally through bolts (bolt connection), buckles (buckle connection) or magnets (magnetic suction type). connection) and other fixed components to further secure the connection. This ensures that the pluggable memory will not fall off easily while the vehicle is driving, ensuring data and driving safety.
  • the first data includes map data and/or traffic data.
  • map data or traffic data with high update frequency can be stored in a pluggable memory, so that the data can be updated without worries to better meet the needs of intelligent driving.
  • the above-mentioned first memory may also be used to store operating system software and/or application programs of the vehicle. This can expand the application scope of pluggable memory.
  • the second data includes operating system software and/or application programs of the vehicle.
  • the first memory and the second memory satisfy at least one of the following:
  • the storage capacity of the first memory is greater than the storage capacity of the second memory
  • the update frequency of the first memory is higher than the update frequency of the second memory
  • the importance of the first data in the first memory is lower than the importance of the second data in the second memory.
  • the first memory is a pluggable memory with a larger capacity or a higher update frequency, which can provide necessary guarantee for rapid data update.
  • the second memory is a fixedly connected memory, which can ensure the stability and reliability of stored data. Therefore, it can be used to store data with a higher degree of importance to ensure the security of important data.
  • the data that needs to be stored in the vehicle can be stored reasonably and reliably. Especially for data such as map data and/or traffic data that are frequently updated, there is no need to consider the memory.
  • the problem of erasing and writing times can be updated and stored in time. This can better meet the storage needs of smart driving and provide guarantee for accurate driving control and safe driving of smart cars.
  • the at least one processor is used to perform intelligent driving or automatic driving control.
  • control system can be an intelligent driving control system or an automatic driving control system.
  • the system includes a memory connected in a pluggable manner.
  • the memory can be replaced conveniently, quickly and timely, without worrying about the number of erasing and writing of the memory.
  • the data in the memory can be updated in a timely manner to meet the storage requirements for high data update frequency and provide guarantee for accurate driving control and safe driving of smart cars.
  • the at least one processor is configured to send a first alarm signal when a bad block occurs in the first memory, and the first alarm signal is used to instruct replacement of the first memory.
  • bad blocks can be detected on the pluggable memory, and the user can be reminded to replace the memory in a timely manner through an alarm, so as to reduce the loss of data and ensure that the vehicle can be driven safely.
  • the pluggable memory of this application stores important data for assisting driving such as map data and/or road condition data, and the bad block detection of this application can detect it in time.
  • the pluggable memory problem allows timely replacement to reduce data loss. Therefore, the bad block detection alarm in this application is a powerful guarantee for safe driving control of the vehicle.
  • the at least one processor is configured to send a first alarm signal when a bad block occurs in the first memory, including: the at least one processor is configured to send a first warning signal through the first memory when a bad block occurs in the first memory.
  • the vehicle's central control screen sends out the first warning signal.
  • the solution of sending an alarm through the central control screen can more intuitively and clearly notify the user that the memory needs to be replaced in time. This reduces the loss of data used for assisted driving to ensure safe driving of the vehicle.
  • the at least one processor is configured to send a second alarm signal when the first memory fails to successfully connect to the at least one processor, and the second alarm signal is used to indicate that the first memory The connection to at least one processor failed.
  • the first memory and the at least one processor are connected through a connector, and the connector includes a first pin and a second pin to connect the first memory and the at least one processor; the at least one processor Specifically used for:
  • the second alarm signal is issued.
  • the pluggable memory of this application stores important data for assisting driving such as map data and/or road condition data.
  • the memory insertion detection in this application can promptly detect whether the pluggable memory is inserted securely. In order to ensure timely insertion and reduce data loss. Therefore, the memory insertion detection alarm in this application is a powerful guarantee for safe driving control of the vehicle.
  • this application provides a vehicle, which includes the control system described in any one of the first aspects.
  • the control system of the vehicle includes a memory connected in a pluggable manner.
  • the memory can be replaced conveniently, quickly and timely, so that there is no need to worry about the memory's erase and write times being used up, and the data in the memory can be updated in a timely manner to meet the needs of
  • the storage requirement with high data update frequency provides guarantee for accurate driving control and safe driving of smart cars.
  • FIG. 1 is a schematic structural diagram of the control system provided by this application.
  • FIG. 2 is a schematic diagram of the circuit connection of the connector provided by this application.
  • FIG. 3 is a schematic diagram of the memory insertion detection process provided by this application.
  • FIG. 4 is a schematic diagram of the flow of clock signals in the control system provided by this application.
  • FIG. 5 is a schematic structural diagram of the automatic driving system provided by this application.
  • FIG. 6 is a schematic diagram of the memory bad block detection process provided by this application.
  • FIG. 7 is a schematic structural diagram of the vehicle provided by this application.
  • multiple refers to two or more.
  • “and/or” is used to describe the association of associated objects, indicating three relationships that can exist independently.
  • a and/or B can mean: A exists alone, B exists alone, or both.
  • Descriptions such as "at least one (or at least one) of a1, a2, ... and an” used in the embodiments of this application include the situation where any one of a1, a2, ... and an exists alone. , also includes any combination of any more of a1, a2,...
  • each situation can exist alone; for example, the description of "at least one of a, b, and c" includes a single a , b alone, c alone, a and b combination, a and c combination, b and c combination, or a, b, c combination.
  • embodiments of the present application provide a control system applied in vehicles.
  • the above-mentioned data with high update frequency that appears with the development of smart cars can be stored through pluggable memory.
  • These data are mainly used to assist vehicle driving and are crucial to the accuracy of vehicle driving control and driving safety.
  • the current data storage solution in vehicles cannot meet the update and storage needs of these data. Therefore, this application innovatively proposes a storage solution that uses pluggable memory to store these data. Since the memory is pluggable, new memory can be replaced in a timely manner. Therefore, there is no need to worry about the number of erasing and writing of the memory, and the corresponding data can be updated and stored in a timely manner to meet the needs of intelligent and safe driving of vehicles.
  • pluggable memories also exist in other fields, such as USB flash drives, most of them are used to expand capacity or facilitate data transfer, and meet the data storage needs of small computing devices. And the requirements for security, performance, data classification, etc. are not high.
  • the data storage scheme of pluggable memory provided by this application is based on the vehicle specifications and other requirements, and is used to store specific categories of data (such as data with a high update frequency or data that requires a high number of erasing and writing times of the memory). . This ensures the timely updating and storage of these data, ensuring the accuracy of vehicle driving control and driving safety.
  • the following is an exemplary introduction to the embodiments of the present application with reference to the accompanying drawings.
  • FIG. 1 shows a schematic structural diagram of a control system 100 used in a vehicle provided by an embodiment of the present application.
  • the control system 100 includes a processor 101, a first memory 102 and a second memory 103.
  • the first memory 102 is connected to the processor 101 through a connector 104 .
  • the first memory 102 can be pluggable into the connector 104 to achieve connection with the processor 101 .
  • the second memory 103 is fixedly connected to the processor 101 .
  • the fixed connection may be a non-detachable connection such as welding.
  • the above-mentioned processor 101 may include one or more processors.
  • the processor has the ability to calculate and process objects such as data, signals or instructions.
  • the processor may be, for example, a central processing unit, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof.
  • the processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, and so on.
  • the processor may be a general purpose processor or the like.
  • the processor 101 may be embodied as one or more processing chips or system on chip (SOC). The embodiments of this application do not limit the specific type or implementation form of the processor.
  • the above-mentioned first memory 102 and second memory 103 may be the power-down storage unit of the control system 100 .
  • the first memory 102 may be a solid state drive (SSD) memory card, a pluggable universal flash storage (UFS) card, a mobile hard disk or a USB flash drive, etc.
  • the second memory 103 may be UFS or solid state disk (SSD), etc.
  • the embodiment of the present application does not limit the specific types of the first memory 102 and the second memory 103.
  • the first memory 102 can be pluggably connected to the processor 101, and the second memory 103 can be fixedly connected to the processor. 101-connected memories can be applied to the embodiments of this application.
  • the above-mentioned first memory 102 may be used to store the first data.
  • the above-mentioned second memory 103 can be used to store second data.
  • the first data and the second data have different update degrees.
  • the update level includes the update frequency of the data and/or the importance of the data. That is, the different update degrees of the first data and the second data may include any of the following situations:
  • the update frequencies of the first data and the second data are different.
  • the update frequency and importance of the first data and the second data are different.
  • the above-mentioned first data may include map data and/or traffic data, etc.
  • the map data may be map data downloaded to the vehicle or map data collected and recorded while the vehicle is driving, etc.
  • the road condition data may be road condition data downloaded to the vehicle or may be road condition data collected and recorded by the vehicle while driving.
  • the above-mentioned second data may include operating system software of the vehicle and/or application programs in the vehicle.
  • map data and/or road condition data need to be constantly updated so that the vehicle can perform driving control based on the latest data to ensure accurate and safe driving of the vehicle. That is, the map data and/or traffic data are updated more frequently.
  • the operating system software is more important and requires a more reliable and stable memory for storage, so it can be stored in the above-mentioned fixedly connected second memory 103 .
  • the above-mentioned first data may include the operating system and/or application program of the vehicle. That is, the operating system and/or application program may be stored in the above-mentioned first memory 102 .
  • the above-mentioned second data may include map data and/or traffic data, etc. That is, the map data and/or traffic data can be stored in the above-mentioned second memory 103 .
  • first data and second data do not constitute a limitation on the embodiments of the present application.
  • the above-mentioned first data and second data can be any data stored in the vehicle.
  • the embodiments of the present application use the first data and the specific scope included in the second data is not limited.
  • the above-mentioned first memory 102 and second memory 103 can satisfy at least one of the following conditions:
  • the storage capacity of the first memory 102 is greater than the storage capacity of the second memory 103 .
  • the update frequency of the first memory 102 is higher than the update frequency of the second memory 103;
  • the importance of the first data in the first memory 102 is lower than the importance of the second data in the second memory 103 .
  • the storage capacity of the first memory 102 can be designed to be relatively large, so that the first memory 102 can be used to store more data. .
  • the first memory 102 is connected to the processor in a pluggable manner, using the first memory 102 to store more data can also facilitate data transfer. That is, when data is needed, the first memory 102 can be disassembled and transferred quickly. Compared with transferring data through network transmission, the data transfer efficiency can be improved.
  • the update frequency of the first memory 102 is higher than the update frequency of the second memory 103, in a specific implementation, since the first memory 102 is connected to the processor 101 in a pluggable manner, when the first memory 102 When the storage space is full or bad blocks appear, new storage can be replaced in time. Moreover, since the first memory 102 can be replaced easily and quickly, there is no need to worry about the memory's erase and write times being used up, and the data in the memory can be updated in a timely manner to meet the storage requirements for high data update frequency. Provides guarantee for accurate driving control and safe driving of smart cars.
  • the important data is generally stored in a fixedly connected memory to avoid loss. Therefore, the importance of the data stored in the second memory 103 fixedly connected to the processor 101 may be higher than the data stored in the first memory 102 pluggably connected to the processor 101 .
  • the above-mentioned connector 104 may be a serial small computer system interface (serial attached SCSI, SAS) connector, a serial high-tech configuration (serial ATA, SATA) connector or a high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIE) connector and so on.
  • serial small computer system interface serial attached SCSI, SAS
  • serial high-tech configuration serial ATA, SATA
  • PCIE peripheral component interconnect express
  • the connector 104 includes multiple pins (PINs).
  • P1, P2, P3, etc. represent the first pin, the second pin, the third pin, etc. respectively.
  • the PCIE connector can be provided on the motherboard where the above-mentioned processor 101 is located.
  • the first memory 102 is connected to the motherboard through the PCIE connector.
  • the PCIE connector provides 4 ⁇ lane data channels (SOC_PCIE_RX[3:0]_P/N and SOC_PCIE_TX[3:0]_P/N), clock signal channel (SOC_CLK_100M_P/N), two The signal channel (SSD_CARD_IN_DET[1:0]) indicating whether the first memory 102 is inserted firmly, the status acquisition signal channel (SSD_SDA and SSD_SCL) of the first memory 102, the reset signal channel (SSD_PERST) of the first memory 102, and the clock request channel (SSD_CLKREQ) and wait signal channel (SSD_PEWAKE), etc.
  • PCIE is a full-duplex bus.
  • One lane consists of two pairs of differential signal lines, that is, 4 signal lines.
  • the number of lanes is called the bit width, that is, the bit width of the above PCIE connector is 4.
  • the four lanes can simultaneously receive and send 4 bits of information each.
  • SOC_PCIE_RX[3:0]_P/N and SOC_PCIE_TX[3:0]_P/N “[3:0]” indicates groups 0, 1, 2 and 3 of PCIE data channels.
  • the "P” in “P/N” indicates the data line connected to the positive pole, and the "N” indicates the data line connected to the negative pole.
  • the "RX” means sending, and the "TX” means receiving.
  • SOC_PCIE_RX[3:0]_P/N is used to receive data from the first memory 102 and send the received data to the processor 101 (when the processor 101 reads data from the first memory 102).
  • SOC_PCIE_TX[3:0]_P/N is used to send data to the first memory 102 (when the processor 101 writes data to the first memory 102).
  • the processor 101 can write data to the first memory 102 through the above-mentioned 4 ⁇ lane data channel, and read data from the first memory 102 .
  • capacitors on the above-mentioned 4 ⁇ lane data channel namely C1, C2, C3, C4, C5, C6, C7 and C8, can be used to filter out the DC component and play the role of AC coupling (AC Coupling).
  • bit width of the PCIE connector of 4 in Figure 2 is only an example.
  • the bit width of the PCIE connector may be 1 or 2, etc., and the embodiment of the present application does not limit this.
  • FIG. 2 takes a clock signal channel with a bandwidth of 100M as an example. This does not constitute a limitation on the embodiments of the present application. The embodiments of the present application do not limit the bandwidth of the clock signal channel.
  • the above two signal channels indicating whether the first memory 102 is inserted firmly can be used to detect whether the first memory 102 and the processor 101 are inserted firmly.
  • the two signals indicating whether the first memory 102 is inserted firmly may be simply called the insertion indication signal.
  • the two plug-in indication signals are respectively pulled up to high-level signals through resistors R1 and R2 on the motherboard side (for example, the pull-up is 3.3V, this is only an example).
  • the processor 101 can determine whether the first memory 102 is inserted firmly by detecting the two signals. For example, see the detection process shown in Figure 3 .
  • the processor 101 can read the above two insertion indication signals. And judge the high and low levels of the two signals. For example, a high-level signal may be represented as "1" and a low-level signal may be represented as "0". If both signals are low level, it indicates that the first memory 102 has been inserted firmly, that is, it has been successfully inserted into the PCIE connector. If at least one of the two signals is at a high level, it indicates that the first memory 102 is not inserted securely, and an alarm can be issued to remind the user.
  • the processor 101 can send a message to the central control screen of the vehicle, and the central control screen displays the prompt information that the device is not inserted securely. Or, for example, the processor 101 may instruct the unplugged indicator light to light to alert the user. Alternatively, the processor 101 may instruct the user to be notified via a voice broadcast.
  • the embodiment of this application does not limit the specific alarm method.
  • SSD_SDA is the data line
  • SSD_SCL is the control line.
  • the combination of the two can be used to read information such as the temperature of the first memory 102.
  • the above-mentioned reset signal channel of the first memory 102 can be used to control the reset of the first memory 102 .
  • the above clock request channel can be used by the first memory 102 to send a constant request signal to the processor 101 to achieve clock synchronization between the two.
  • the above-mentioned wait signal channel is used for the first memory 102 to send a wait signal to the processor 101 to indicate that it is not ready for further processing and the processor 101 needs to wait.
  • V_STB_3V3_SSD shown in Figure 2 above represents the supply voltage signal, which is used to power the connector.
  • the part connected to the pin P10 in Figure 2 is used to control the lighting of the LED.
  • the processor 101 can control the lighting of the LED.
  • R3 and R4 are used to control the LED lighting.
  • D1 is a transient voltage suppressor diode (TVS), which plays a role in circuit protection.
  • resistors R5, R6 and R7 in Figure 2 are optional and can be added to optimize signal integrity.
  • Resistor R8 is a pull-up resistor.
  • D2 to D6 are all transient voltage suppression diodes for circuit protection. GND in Figure 2 means ground.
  • PCIE connector is only an example and does not constitute a limitation on the embodiments of the present application.
  • the control system 100 may further include a clock module, which may be used to provide clock signals for the processor 101 and the first memory 102 .
  • the clock module 105 may include a crystal oscillator 1051 and a clock buffer 1052 .
  • crystal oscillator 1051 is used to output a single-ended clock signal.
  • the clock buffer 1052 is used to convert the single-ended clock signal into a differential clock signal.
  • a single-ended clock signal refers to a signal transmitted using a signal line and a ground wire.
  • the signal transmitted on the signal line is a single-ended signal.
  • Differential clock signals refer to the transmission of clock signals of equal size and opposite polarity on two lines, that is, the clock signals transmitted on these two lines are differential clock signals.
  • the clock buffer 1052 After the clock buffer 1052 converts the single-ended clock signal into a differential clock signal, it outputs the signal in two channels, one channel is output to the processor 101, and the other channel is output to the first memory 102.
  • the dotted arrow from the clock buffer 1052 pointing to the first memory 102 is only used to indicate that a clock signal is output to the first memory 102 , but does not mean that the clock buffer is directly connected to the first memory 102 .
  • the differential clock signal output to the first memory 102 may be sent to the first memory 102 through the connector 104 .
  • the PCIE connector shown in Figure 2 above For ease of understanding, reference can be made to the PCIE connector shown in Figure 2 above.
  • the PCIE connector includes a clock channel, so one output end of the clock buffer 1052 can be connected to two pins of the clock channel, namely pin P53 and pin P55. Then, when the first memory 102 is plugged into the PCIE connector, the pin P53 and the pin P55 are connected to the first memory 102, thereby realizing sending a differential clock signal of the clock buffer 1052 to the first memory 102.
  • a memory 102 A memory 102.
  • the above-mentioned processor 101 may be used to perform control operations of intelligent driving or automatic driving.
  • the above control system 100 may be an intelligent assisted driving system in a vehicle.
  • the processor 101 may be one or more control processors in the intelligent assisted driving system.
  • the intelligent assisted driving system may include, for example, a lane keeping assist system, an automatic parking assist system, a brake assist system, a reversing assist system, a driving assist system, etc.
  • the control system 100 may be an automatic driving system in a vehicle.
  • the processor 101 may be one or more control processors in the autonomous driving system.
  • the automatic driving system may be, for example, an advanced driving assistance system (ADAS).
  • ADAS advanced driving assistance system
  • the ADAS system can include a variety of different driving control technologies, such as intelligent adaptive cruise, automatic emergency braking, traffic sign recognition, blind spot detection, lane change assistance, lane departure warning, driver fatigue reminder, forward collision avoidance assistance, Navigation system, real-time traffic system, electronic police system, Internet of Vehicles system, downhill control system, etc.
  • driving control technologies such as intelligent adaptive cruise, automatic emergency braking, traffic sign recognition, blind spot detection, lane change assistance, lane departure warning, driver fatigue reminder, forward collision avoidance assistance, Navigation system, real-time traffic system, electronic police system, Internet of Vehicles system, downhill control system, etc.
  • FIG. 5 takes the above-mentioned control system 100 as an automatic driving system as an example, and illustrates a schematic structural diagram of an automatic driving system 500 .
  • the automatic driving system 500 includes a processor 501, and includes a first memory 502, a second memory 503, a switching module 505, a deserializer module 506, an ultrasonic access module 507, a positioning module 508, and a memory 509 connected to the processor 501. , basic input and output system memory 510, power module 511 and clock module 512.
  • the processor 501 is the control core of the automatic driving system 500 and is used to control the vehicle to implement automatic driving operations.
  • the specific form of the processor 501 can be exemplarily referred to the relevant description of the processor 101 shown in FIG. 1 , and will not be described again here.
  • the first memory 502 is connected to the processor 501 through a connector 504 .
  • the first memory 502 can be used to store data that is updated frequently, such as map data or traffic data.
  • the specific form of the first memory 502 can be exemplarily referred to the related description of the first memory 102 shown in FIG. 1 , and will not be described again here.
  • the second memory 503 can be connected to the processor 501 in a fixed manner.
  • the second memory 503 can be used to store data with high security and reliability requirements, such as vehicle system software or application programs.
  • the specific form of the second memory 503 can be exemplarily referred to the related description of the second memory 103 shown in FIG. 1 , and will not be described again here.
  • the exchange module 505 can be used to implement data exchange processing functions.
  • the switching module 505 may include, for example, a local area network switch chip (LAN switch, LSW).
  • the exchange module 505 can be connected to one or more lidars 513 to implement data exchange and transmission between the processor 501 and the lidars 513 .
  • the lidar 513 can be, for example, a laser detection and ranging (LIDAR) device, which can measure distance by emitting laser light to an object and then using a light sensor to receive the reflected light.
  • LIDAR laser detection and ranging
  • the deserializer module 506 can be connected to the camera 514 and is used to quickly transmit the data collected by the camera 514 to the processor 501 for processing.
  • the ultrasonic access module 507 can be connected to the ultrasonic sensor 515, and is used to receive data from the ultrasonic sensor 515 and send it to the processor 501 for processing.
  • the positioning module 508 can be used to locate the current location of the vehicle.
  • This memory 509 can be used to store data and computer programs run by the processor 501.
  • the basic input output system memory 510 can be used to store basic input output system (basic input output system, BIOS) programs and startup programs of the automatic driving system 500 , etc.
  • basic input output system basic input output system, BIOS
  • BIOS basic input output system
  • the power module 511 is used to provide power for the automatic driving system 500 .
  • the clock module 512 is used to manage the timing and operating frequency of the automatic driving system 500 so that the automatic driving system 500 can work in an orderly manner. Specifically, the clock module 512 is used to provide a clock signal for the automatic driving system 500 .
  • the clock module 512 reference may be made to the relevant description of the clock module 105 shown in FIG. 4 as an example, which will not be described again here.
  • the processor 101 may perform bad block detection on the first memory 102 .
  • the processor 101 After the processor 101 is powered on, it can perform bad block detection on the first memory 102 .
  • the status information of each storage block (block) in the first memory 102 can be read, and the quality of the storage block can be determined based on the status information of the storage block.
  • the method of bad block detection here is only an example and does not constitute a limitation on the embodiments of the present application.
  • the embodiments of the present application can implement the detection of bad blocks through existing bad block detection methods.
  • an alarm may be issued to instruct the user to replace the first memory 102 .
  • the bad block rate refers to the ratio of the number of bad blocks to the total number of storage blocks in the first memory 102.
  • the preset ratio may be, for example, 10% or 15%, which is not limited by the embodiment of the present application.
  • the processor 101 can send a message to the central control screen of the vehicle, and the central control screen displays the replacement prompt information.
  • the processor 101 may instruct the user to be notified via a voice broadcast.
  • the embodiment of this application does not limit the specific alarm method.
  • Vehicle 700 in Figure 7 includes a control system including a processor, a first memory, and a second memory.
  • the first memory is connected to the processor through a connector.
  • the first memory can be pluggable into a connector to be connected to the processor.
  • the second memory is fixedly connected to the processor.
  • control system applied to the vehicle includes a memory connected in a pluggable manner, which can be replaced conveniently, quickly and timely, so that there is no need to worry about the memory's erase and write times being used up, and it can be updated in a timely manner.
  • the data in the memory meets the storage requirements for high data update frequency and provides guarantee for accurate driving control and safe driving of smart cars.
  • first, second, etc. are used to distinguish the same or similar items with basically the same functions and functions. It should be understood that the terms “first”, “second” and “nth” There is no logical or sequential dependency, and there is no limit on the number or execution order. It should also be understood that, although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another.
  • the size of the sequence number of each process does not mean the order of execution.
  • the execution order of each process should be determined by its function and internal logic, and should not be determined by the execution order of the embodiments of the present application.
  • the implementation process constitutes no limitation.
  • references throughout this specification to "one embodiment,” “an embodiment,” and “a possible implementation” mean that specific features, structures, or characteristics related to the embodiment or implementation are included herein. In at least one embodiment of the application. Therefore, “in one embodiment” or “in an embodiment” or “a possible implementation” appearing in various places throughout this specification do not necessarily refer to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments.

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Abstract

一种应用于车辆中的控制系统及车辆。控制系统中包括至少一个处理器、第一存储器（102）和第二存储器（103），第一存储器（102）以可插拔的方式与至少一个处理器连接，第二存储器（103）与至少一个处理器固定连接；第一存储器（102）用于存储第一数据，第二存储器（103）用于存储第二数据，第一数据和第二数据的更新程度不同，更新程度包含更新频率和/或重要程度。能够满足车辆高要求的存储需求，为智能汽车的准确驾驶控制和安全驾驶提供保障。

Description

应用于车辆中的控制系统及车辆 技术领域
本申请涉及智能汽车技术领域，尤其涉及一种应用于车辆中的控制系统及车辆。
背景技术
随着智能汽车技术的发展，特别是随着无人驾驶技术的发展，车辆中需要存储的数据越来越多，并且数据更新的频率也越来越高，这对车辆中存储单元的要求也越来越高。车辆中现有的存储单元已无法满足要求越来越高的存储需求。
发明内容
本申请实施例公开了一种应用于车辆中的控制系统及车辆，能够满足要求越来越高的存储需求。
第一方面，本申请提供一种应用于车辆中的控制系统，其特征在于，该控制系统包括至少一个处理器、第一存储器和第二存储器，该第一存储器以可插拔的方式与该至少一个处理器连接，该第二存储器与该至少一个处理器固定连接；
该第一存储器用于存储第一数据，该第二存储器用于存储第二数据，该第一数据和该第二数据的更新程度不同，该更新程度包含更新频率和/或重要程度。
可选的，该固定连接可以是焊接等来接方式。可选的，该第一存储器为固态驱动器SSD存储卡，该第二存储器为通用闪存UFS存储器。
由于现有方案中，车辆控制系统中存储器无法更换，需要顾及到存储器的擦写次数的问题，影响到了地图数据或路况数据等数据的及时更新和存储，这会影响到智能汽车驾驶控制的准确性。本方案中，应用于车辆的控制系统包括以可插拔的方式连接的存储器，可以方便快捷并及时地更换存储器，从而无需顾虑存储器的擦写次数被用完的问题，进而可以及时地更新存储器中的数据，满足对数据更新频率高的存储需求，为智能汽车的准确驾驶控制和安全驾驶提供保障。
另一方面，相比于现有的可插拔存储器的方案(例如在电脑上可插拔U盘的方案等)，本申请中可插拔存储器的方案是符合车规要求的，例如上述车辆控制系统中包括的可插接存储器的接口以及插接的存储器都是符合车规的要求的。示例性地，该接口和存储器之间除了电路的插拔连接之外，在结构上该接口和存储器之间还可以通过螺栓(螺栓连接)、卡扣(卡扣连接)或磁铁(磁吸式连接)等固定部件进一步固定连接。由此，可以确保可插拔的存储器在车辆行驶的过程不易掉落，保障数据和行车安全。
可选的，该第一数据包括地图数据和/或路况数据。
本申请中，可以将更新频率高的地图数据或路况数据存储在可插拔的存储器中，使得可以无顾虑地更新数据，以更好地满足智能驾驶的需求。另外，可选的，上述第一存储器还可以用于存储该车辆的操作系统软件和/或应用程序。从而可以扩展可插拔存储器的应用范围。
可选的，该第二数据包括该车辆的操作系统软件和/或应用程序。
本申请中，将操作系统软件或应用程序等较重要的数据存储在固定连接的存储器中，可以提高系统软件或应用程序存储的稳定和可靠性。
一种可能的实施方式中，该第一存储器和该第二存储器满足以下中的至少一个：
该第一存储器的存储容量大于该第二存储器的存储容量；
该第一存储器的更新频率高于该第二存储器的更新频率；
该第一存储器中的第一数据的重要程度低于该第二存储器中的第二数据的重要程度。
本申请中，第一存储器为可插拔的存储器，其容量更大，或更新频率更高，可以为数据的快速更新提供了必要的保障。第二存储器为固定连接的存储器，其可以保障存储数据的稳定和可靠，因此可以用于存储重要程度较高的数据，以确保重要数据的安全。基于上述第一存储器和第二存储器满足的条件，可以使得车辆中需要存储的数据都能够得到合理可靠的存储，特别是对于更新频率高的地图数据和/或路况数据等数据，可以无需顾及存储器的擦写次数的问题，能够及时地更新并存储。从而更好地满足智能驾驶的存储需求，并为智能汽车的准确驾驶控制和安全驾驶提供保障。
一种可能的实施方式中，该至少一个处理器用于执行智能驾驶或者自动驾驶的控制。
本申请中，上述控制系统可以是智能驾驶控制系统或自动驾驶控制系统，该系统中包括以可插拔的方式连接的存储器，可以方便快捷并及时地更换存储器，从而无需顾虑存储器的擦写次数被用完的问题，进而可以及时地更新存储器中的数据，满足对数据更新频率高的存储需求，为智能汽车的准确驾驶控制和安全驾驶提供保障。
一种可能的实施方式中，该至少一个处理器用于在该第一存储器出现坏块的情况下，发出第一告警信号，该第一告警信号用于指示更换该第一存储器。
本申请中，可以对可插拔的存储器进行坏块检测，并通过告警的方式及时提醒用户及时更换存储器，以便减少数据的损失，以保障车辆可以安全驾驶。相比于现有的普通存储器的坏块检测，本申请的可插拔存储器中存储着地图数据和/或路况数据等重要的用于辅助驾驶的数据，本申请中的坏块检测能够及时发现该可插拔的存储器的问题，以便及时更换减少数据损失。因此本申请中的坏块检测告警是对车辆安全驾驶控制的一个有力的保障。
可选的，该至少一个处理器用于在该第一存储器出现坏块的情况下，发出第一告警信号，包括：该至少一个处理器用于在该第一存储器出现坏块的情况下，通过该车辆的中控屏发出该第一告警信号。
本申请中，通过中控屏发出告警的方案，可以更直观明了地通知用户需要及时更换存储器。因而减少了用于辅助驾驶的数据的丢失，以保障车辆的安全驾驶。
一种可能的实施方式中，该至少一个处理器用于在该第一存储器未成功与该至少一个处理器连接的情况下，发出第二告警信号，该第二告警信号用于指示该第一存储器与该至少一个处理器连接失败。
可选的，该第一存储器与该至少一个处理器通过连接器连接，该连接器包括的第一引脚和第二引脚连接该第一存储器与该至少一个处理器；该至少一个处理器具体用于：
检测该第一引脚和第二引脚的电平信号；
在该第一引脚和该第二引脚的电平信号中至少有一个为低电平信号的情况下，发出该第二告警信号。
本申请中，通过检测第一存储器是否插牢，以确保存储器与至少一个处理器的成功连接，进而确保数据可以成功存储，以免数据丢失。本申请的可插拔存储器中存储着地图数据和/或路况数据等重要的用于辅助驾驶的数据，本申请中的存储器插牢检测能够及时发现该可插拔的存储器是否插牢的问题，以便及时插牢，减少数据损失。因此本申请中的存储器插牢检测告警是对车辆安全驾驶控制的一个有力的保障。
第二方面，本申请提供一种车辆，该车辆包括第一方面任一项所述的控制系统。
该车辆的控制系统包括以可插拔的方式连接的存储器，可以方便快捷并及时地更换存储器，从而无需顾虑存储器的擦写次数被用完的问题，进而可以及时地更新存储器中的数据，满足对数据更新频率高的存储需求，为智能汽车的准确驾驶控制和安全驾驶提供保障。
附图说明
图1为本申请提供的控制系统的结构示意图；
图2为本申请提供的连接器的电路连接示意图；
图3为本申请提供的存储器插牢检测流程的示意图；
图4为本申请提供的控制系统中时钟信号的流向示意图；
图5为本申请提供的自动驾驶系统的结构示意图；
图6为本申请提供的存储器坏块检测流程的示意图；
图7为本申请提供的车辆的结构示意图。
具体实施方式
本申请实施例中，“多个”是指两个或两个以上。本申请实施例中，“和/或”用于描述关联对象的关联关系，表示可以独立存在的三种关系，例如，A和/或B，可以表示：单独存在A，单独存在B，或同时存在A和B。本申请实施例中采用的诸如“a1、a2、……和an中的至少一项(或至少一个)”等的描述方式，包括了a1、a2、……和an中任意一个单独存在的情况，也包括了a1、a2、……和an中任意多个的任意组合情况，每种情况可以单独存在；例如，“a、b和c中的至少一项”的描述方式，包括了单独a，单独b，单独c、a和b组合，a和c组合，b和c组合，或a、b、c三者组合的情况。
在本申请的各个实施例中，如果没有特殊说明以及逻辑冲突，各个实施例之间的术语和/或描述具有一致性、且可以相互引用，不同的实施例中的技术特征根据其内在的逻辑关系可以组合形成新的实施例。
下面将结合附图对本申请实施例作介绍。
随着智能汽车的不断发展，特别是在半自动驾驶或自动驾驶的场景，车辆需要采集和存储的数据越来越多，并且需要时常更新的数据也越来越多。数据的更新需要对存储器进行擦写操作，更新频率越高，擦写次数就越多。而存储器的擦写次数是有限制的，擦写次数超过存储器所能够提供的最大擦写次数则会导致存储器损害，进而造成数据的丢失等问题。现有的方案中为了保护存储器，会限制数据的更新，导致数据无法及时更新，导致车辆无法及时按照最新的数据来驾驶车辆，从而影响了车辆驾驶控制的准确性和驾驶安全。为了提高车辆驾驶控制的准确性和驾驶安全，本申请实施例提供了一种应用于车辆中的控制系统。
在本申请实施例中，可以通过可插拔的存储器来存储上述随着智能汽车的发展而出现的更新频率高的数据。这些数据主要是用于辅助车辆的驾驶，对车辆驾驶控制的准确性和驾驶安全至关重要。而当前车辆中的数据存储方案已满足不了这些数据的更新存储需求，因此，本申请创新性地提出了通过可插拔的存储器来存储这些数据的存储方案。由于存储器可插拔，可以及时地更换新的存储器，因而可以无需顾虑存储器的擦写次数的问题，进而可以及时完成对应数据的更新存储，以适应车辆智能安全驾驶的需求。虽然其它领域中也存在可插拔存储器，例如U盘等，但其大多数是为了扩容或方便数据转移，满足的是小型计算设备的数据存储需求。并且对安全、性能、数据分类等要求不高。而本申请提供的可插拔存储器存储数据的方案是基于车的车规等需求，用于对特定分类的数据(例如更新频率高的数据或对存储器的擦写次数要求高的数据)进行存储。保证了这些数据的及时更新和存储，可以保障车辆 驾驶控制的准确性和驾驶安全。下面结合附图对本申请实施例做示例性介绍。
图1所示为本申请实施例提供的一种应用于车辆中的控制系统100的结构示意图。该控制系统100包括处理器101、第一存储器102和第二存储器103。该第一存储器102通过连接器104与该处理器101连接。该第一存储器102可以可插拔地插接到连接器104上以实现与该处理器101连接。该第二存储器103与该处理器101固定连接。示例性地，该固定连接可以是通过焊接等不可拆卸的方式连接。
上述处理器101可以包括一个或多个处理器。处理器具备对数据、信号或指令等对象的计算处理能力。示例性地，处理器例如可以是中央处理器单元、数字信号处理器、专用集成电路、现场可编程门阵列或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。或者，处理器也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，数字信号处理器和微处理器的组合等等。或者，处理器可以是通用处理器等。一种可能的实施方式中，该处理器101可以表现为一个或多个处理芯片或系统芯片(system on chip，SOC)。本申请实施例对处理器的具体类型或实现形式不做限制。
上述第一存储器102和第二存储器103可以是控制系统100的掉电保存单元。示例性性地，该第一存储器102可以是固态驱动器(solid state drive,SSD)存储卡、可插拔的通用闪存(universal flash storage，UFS)卡、移动硬盘或U盘等。示例性地，该第二存储器103可以是UFS或固态硬盘(solid state disk，SSD)等。本申请实施例对该第一存储器102和第二存储器103的具体类型不做限制，可以实现第一存储器102可插拔地与处理器101连接，第二存储器103以固定连接的方式与处理器101连接的存储器均可以应用于本申请实施例。
在本申请实施例中，上述第一存储器102可以用于存储第一数据。上述第二存储器103可以用于存储第二数据。其中，该第一数据和第二数据的更新程度不同。该更新程度包括数据的更新频率和/或数据的重要程度。即第一数据和第二数据的更新程度不同可以包括如下的任一种情况：
第一种情况，该第一数据和该第二数据的更新频率不同。
第二种情况，该第一数据和该第二数据的重要程度不同。
第三中情况，该第一数据和该第二数据的更新频率和重要程度均不同。
为了便于理解，示例性地，上述第一数据可以包括地图数据和/或路况数据等。该地图数据可以是下载到车辆中的地图数据或者可以是车辆在行驶过程中采集并记录到的地图数据等。该路况数据可以是下载到车辆中的路况数据或者可以是车辆在行驶过程中采集并记录到的路况数据。上述第二数据可以包括车辆的操作系统软件和/或车辆中的应用程序。一般地，地图数据和/或路况数据等需要不断地更新以使得车辆可以基于最新的数据来进行驾驶控制，以确保车辆驾驶的准确和安全。即该地图数据和/或路况数据的更新频率较高。而对于操作系统软件和/或应用程序，其稳定性较高，更新频率较低甚至可能不更新。另外，在重要程度上，操作系统软件更加重要，需要更可靠稳定的存储器来存储，因此其可以存储在上述固定连接的第二存储器103中。
另一种可能的实施方式中，上述第一数据可以包括车辆的操作系统和/或应用程序。即该操作系统和/或应用程序可以存储在上述第一存储器102中。上述第二数据可以包括地图数据和/或路况数据等。即该地图数据和/或路况数据可以存储在上述第二存储器103中。
可以理解的是，上述第一数据和第二数据的示例不构成对本申请实施例的限制，上述第一数据和第二数据可以是车辆中保存的任意数据，本申请实施例对该第一数据和第二数据包括的具体范围不做限制。
一种可能的实施方式中，上述第一存储器102和第二存储器103可以满足以下中的至少一种情况：
第一种情况，第一存储器102的存储容量大于第二存储器103的存储容量。
第二种情况，第一存储器102的更新频率高于第二存储器103的更新频率；
第三种情况，第一存储器102中的第一数据的重要程度低于第二存储器103中的第二数据的重要程度。
第一存储器102的存储容量大于第二存储器103的存储容量的情况，在具体实现中，可以设计该第一存储器102的存储容量比较大，以使得第一存储器102可以用于存储较多的数据。另外，由于该第一存储器102是以可插拔的方式与处理器连接，因此，使用该第一存储器102存储更多的数据也可方便数据的转移。即在需要数据时，可以将该第一存储器102拆卸出来快速转移，相比于需要通过网络传输来转移数据，可以提高数据的转移效率。
第一存储器102的更新频率高于第二存储器103的更新频率的情况，在具体实现中，由于第一存储器102是以可插拔的方式与处理器101连接，因此当该第一存储器102的存储空间被存满或者出现坏块时，可以及时更换新的存储器。并且，由于该第一存储器102可以方便快速地进行更换，因此可以无需顾虑存储器的擦写次数被用完的问题，进而可以及时地更新存储器中的数据，满足对数据更新频率高的存储需求，为智能汽车的准确驾驶控制和安全驾驶提供保障。
第一存储器102中的第一数据的重要程度低于第二存储器103中的第二数据的重要程度的情况，在具体实现中，重要的数据一般存储在固定连接的存储器中以免丢失。因此，上述与处理器101固定连接的第二存储器103中存储数据的重要程度，可以高于以可插拔方式与处理器101连接的第一存储器102中存储的数据。
在可能的实施方式中，上述连接器104可以是串行小型计算机系统接口(serial attached SCSI，SAS)连接器、串行高技术配置(serial ATA，SATA)连接器或高速串行计算机扩展总线标准(peripheral component interconnect express，PCIE)连接器等等。
下面以该连接器104为PCIE连接器为例介绍第一存储器102与处理器101的具体连接。可以示例性地参见图2。可以看到，PCIE连接器上包括多个引脚(PIN)，图2中P1、P2、P3等分别表示第一个引脚、第二个引脚、第三个引脚等。在具体实现中，该PCIE连接器可以设置在上述处理器101所在的主板上。第一存储器102通过该PCIE连接器接入该主板。示例性地，该PCIE连接器上提供了4×lane的数据通道(SOC_PCIE_RX[3:0]_P/N和SOC_PCIE_TX[3:0]_P/N)、时钟信号通道(SOC_CLK_100M_P/N)、两个指示第一存储器102是否插牢的信号通道(SSD_CARD_IN_DET[1:0])、第一存储器102的状态获取信号通道(SSD_SDA和SSD_SCL)、第一存储器102的复位信号通道(SSD_PERST)、时钟请求通道(SSD_CLKREQ)和等待信号通道(SSD_PEWAKE)等。
PCIE是全双工的总线，一个lane由两对差分信号线，即4根信号线组成。lane的数量称为位宽，即上述PCIE连接器的位宽为4。在一个PCIE时钟周期内，该4个lane可同时接收和发送各4个比特信息。上述SOC_PCIE_RX[3:0]_P/N和SOC_PCIE_TX[3:0]_P/N中，“[3:0]”表示0、1、2和3组PCIE数据通道。该“P/N”中的“P”表示连接正极的数据线，“N”表示连接负极的数据线。该“RX”表示的是发送，“TX”表示的是接收。在图2中SOC_PCIE_RX[3:0]_P/N用于从第一存储器102接收数据，并将接收的数据发送给处理器101(处理器101从第一存储器102读取数据的情况)。SOC_PCIE_TX[3:0]_P/N用于向第一存储器102发送数据(处理器101向第一存储器102写入数据的情况)。
在具体实现中，处理器101可以通过上述4×lane的数据通道向第一存储器102写入数据，并从该第一存储器102中读取数据。
另外，上述4×lane的数据通道上的电容即C1、C2、C3、C4、C5、C6、C7和C8可以用于过滤掉直流分量，起到了交流耦合(AC Coupling)的作用。
可以理解的是，图2中PCIE连接器的位宽为4仅为示例，在具体实现中，该PCIE连接器的位宽可以是1或2等，本申请实施例对此不做限制。
上述时钟信号通道用于为第一存储器102提供时钟信号。可以理解，图2以100M带宽的时钟信号通道为例，这不构成对本申请实施例的限制，本申请实施例对时钟信号通道的带宽不作限制。
上述两个指示第一存储器102是否插牢的信号通道可以用于检测第一存储器102与处理器101之间是否插牢。该两个指示第一存储器102是否插牢的信号可以简称为插牢指示信号。具体的，该两个插牢指示信号在主板侧分别通过电阻R1和R2上拉为高电平信号(例如，上拉为3.3V，此处仅为示例)。当第一存储器102成功插接到该PCIE连接器中后，这两个信号将被接地，被下拉为低电平信号。若第一存储器102未成功插接到该PCIE连接器中，该两个信号至少有一个是高电平信号。因此，处理器101可以通过检测该两个信号来判断第一存储器102是否插牢。示例性地，可以参见图3所示的检测流程。
在图3中，处理器101在上电之后，可以读取上述两个插牢指示信号。并判断该两个信号的高低电平情况。示例性地，高电平的信号可以表示为“1”，低电平的信号可以表示为“0”。若该两个信号均为低电平，则表明上述第一存储器102已经插牢，即成功插接到PCIE连接器。若该两个信号中至少有一个信号为高电平，则表明上述第一存储器102未插牢，此时可以发出告警提醒用户。例如，处理器101可以发消息到车辆的中控屏，由中控屏显示该未插牢的提示信息。或者，例如，处理器101可以指示点亮未插牢的指示灯以提醒用户。或者，处理器101可以指示通过语音播报告知用户。本申请实施例对该具体的告警方式不做限制。
上述第一存储器102的状态获取信号通道中，SSD_SDA为数据线，SSD_SCL为控制线，该两者的结合可以用于读取第一存储器102的温度等信息。
上述第一存储器102的复位信号通道可以用于控制第一存储器102复位。
上述时钟请求通道可以用于第一存储器102向处理器101发送始终请求信号，以用于实现两者的时钟同步。
上述等待信号通道用于第一存储器102向处理器101发送等待信号，以用于表明还未准备好进行进一步的处理，需要处理器101等待。
上述图2中所示的V_STB_3V3_SSD表示供电电压信号，用于给连接器供电。
上述图2中引脚P10连接的部分用于控制LED的点亮，当上述第一存储器102成功插接到该连接器上后，处理器101可以控制该LED点亮。其中，R3和R4用于配合控制LED点亮。D1为瞬态电压抑制二极管(transient voltage suppressor，TVS)，起到电路保护的作用。另外，图2中电阻R5、R6和R7是可选的，增加后可以获得优化的信号完整性。电阻R8为上拉电阻。D2至D6均是瞬态电压抑制二极管，器电路保护作用。图2中的GND表示接地。
可以理解，上述PCIE连接器仅为一个示例，不构成对本申请实施例的限制。
在具体实现中，上述控制系统100还可以包括时钟模块，该时钟模块可以用于为上述处理器101和上述第一存储器102提供时钟信号。为了便于理解，可以示例性地参见图4。在图4中可以看到，时钟模块105可以包括晶振1051和时钟缓冲器(buffer)1052。其中，晶振 1051用于输出单端时钟信号。时钟缓冲器1052用于将单端时钟信号转为差分时钟信号。其中，单端时钟信号指的是用一根信号线和一根地线来传输的信号，信号线上传输的信号就是单端信号。差分时钟信号指的是在两根线上传输大小相等，极性相反的时钟信号，即这两根线上传输的时钟信号就是差分时钟信号。
上述时钟缓冲器1052将单端时钟信号转为差分时钟信号后，分两路输出，一路输出给处理器101，另一路输出给第一存储器102。图4中时钟缓冲器1052指向第一存储器102的虚线箭头只是用于表示有一路时钟信号输出给该第一存储器102，并不是表示该时钟缓冲器直接与该第一存储器102连接。在具体实现中，输出给第一存储器102的差分时钟信号可以是通过连接器104发送给该第一存储器102。为了便于理解，可以参考上述图2所示的PCIE连接器。该PCIE连接器中包括时钟通道，那么，上述时钟缓冲器1052的一路输出端可以与该时钟通道的两个引脚即引脚P53和引脚P55连接。然后，当第一存储器102插接到该PCIE连接器上后，该引脚P53和引脚P55与第一存储器102实现连接，从而实现了将时钟缓冲器1052的一路差分时钟信号发送到该第一存储器102。
一种可能的实施方式中，上述处理器101可以用于执行智能驾驶或自动驾驶的控制操作。示例性地，上述控制系统100可以是车辆中的智能辅助驾驶系统。该处理器101可以是该智能辅助驾驶系统中的一个或多个控制处理器。该智能辅助驾驶系统例如可以包括车道保持辅助系统、自动泊车辅助系统、刹车辅助系统、倒车辅助系统和行车辅助系统等。示例性地，该控制系统100可以是车辆中的自动驾驶系统。该处理器101可以是该自动驾驶系统中的一个或多个控制处理器。该自动驾驶系统例如可以是高级驾驶辅助系统(advanced driving assistance system，ADAS)。该ADAS系统可以包括多种不同的驾驶控制技术，例如包括智能自适应巡航、自动紧急制动、交通标志识别、盲点检测、变道辅助、车道偏离预警、驾驶员疲劳提醒、前方防撞辅助、导航系统、实时交通系统、电子警察系统、车联网系统、下坡控制系统等。
为了便于理解，可以参见图5。图5以上述控制系统100为自动驾驶系统为例，示例性示出了一种自动驾驶系统500的结构示意图。该自动驾驶系统500包括处理器501，以及包括与处理器501连接的第一存储器502、第二存储器503、交换模块505、解串器模块506、超声波接入模块507、定位模块508、内存509、基本输入输出系统存储器510、电源模块511和时钟模块512。
该处理器501为该自动驾驶系统500的控制核心，用于控制车辆实现自动驾驶操作。该处理器501的具体形态可以示例性地参见上述图1所示处理器101的相关描述，此处不赘述。
该第一存储器502通过连接器504与处理器501连接。该第一存储器502可以用于存储更新频率较高的数据，例如地图数据或路况数据等。该第一存储器502的具体形态可以示例性参考上述图1所示第一存储器102的相关描述，此处不赘述。
该第二存储器503可以以固定的方式与处理器501连接。该第二存储器503可以用于存储安全和可靠性要求较高的数据，例如车辆的系统软件或应用程序等。该第二存储器503的具体形态可以示例性参考上述图1所示第二存储器103的相关描述，此处不赘述。
该交换模块505可以用于实现数据的交换处理功能。该交换模块505例如可以包括局域网交换芯片(LAN switch，LSW)。示例性地，该交换模块505可以与一个或多个激光雷达513连接，以用于实现处理器501和激光雷达513之间数据的交换传输。该激光雷达513例如可以是激光探测及测距(light detection and ranging，LIDAR)装置，该装置可以通过向物体发射 激光，然后用光传感器接收反射回来的光来测量距离。
该解串器模块506可以与摄像头514连接，用于将摄像头514采集到的数据快速传输给处理器501进行处理。
该超声波接入模块507可以与超声波传感器515连接，用于接收超声波传感器515的数据，并发送给处理器501进行处理。
该定位模块508可以用于定位车辆当前所在的位置。
该内存509可以用于存储处理器501运行的数据和计算机程序。
该基本输入输出系统存储器510可以用于存储基本输入输出系统(basic input output system，BIOS)的程序和该自动驾驶系统500的启动程序等。
该电源模块511用于为该自动驾驶系统500提供电源。
该时钟模块512用于管理该自动驾驶系统500的时序和工作频率等，使得该自动驾驶系统500可以有序地工作。具体的，该时钟模块512用于为自动驾驶系统500提供时钟信号。该时钟模块512可以示例性参考上述图4所示时钟模块105的相关描述，此处不赘述。
可以理解，上述自动驾驶系统500仅为一个示例，不构成对本申请实施例的限制。
一种可能的实施方式中，上述处理器101可以对上述第一存储器102进行坏块检测。示例性地，可以参见图6。处理器101上电后，可以对第一存储器102进行坏块检测。示例性地，可以读取第一存储器102中各个存储块(block)的状态信息，通过存储块的状态信息来判断该存储块的好坏。可以理解的是，此处坏块检测的方式仅为示例，不构成对本申请实施例的限制，本申请实施例可以通过现有的坏块检测方法来实现坏块的检测。当处理器101判断第一存储器102中坏块率达到预设比例的情况下，可以发出告警，以指示用户对该第一存储器102进行更换。该坏块率指的是坏块的数量占该第一存储器102中全部存储块数量的比例，该预设比例如可以是10％或15％等，本申请实施例不做限制。示例性地，处理器101可以发消息到车辆的中控屏，由中控屏显示该更换的提示信息。或者，处理器101可以指示通过语音播报告知用户。本申请实施例对该具体的告警方式不做限制。
本申请实施例还提供一种车辆，可以示例性地参见图7。图7中车辆700包括控制系统，该控制系统包括处理器、第一存储器和第二存储器。该第一存储器通过连接器与该处理器连接。该第一存储器可以可插拔地插接到连接器上以实现与该处理器连接。该第二存储器与该处理器固定连接。关于该控制系统的描述可以参见前述的描述，此处不赘述。
综上所述，应用于车辆的控制系统包括以可插拔的方式连接的存储器，可以方便快捷并及时地更换存储器，从而无需顾虑存储器的擦写次数被用完的问题，进而可以及时地更新存储器中的数据，满足对数据更新频率高的存储需求，为智能汽车的准确驾驶控制和安全驾驶提供保障。
本申请中术语“第一”“第二”等字样用于对作用和功能基本相同的相同项或相似项进行区分，应理解，“第一”、“第二”、“第n”之间不具有逻辑或时序上的依赖关系，也不对数量和执行顺序进行限定。还应理解，尽管以下描述使用术语第一、第二等来描述各种元素，但这些元素不应受术语的限制。这些术语只是用于将一元素与另一元素区别分开。
还应理解，在本申请的各个实施例中，各个过程的序号的大小并不意味着执行顺序的先 后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
还应理解，术语“包括”(也称“includes”、“including”、“comprises”和/或“comprising”)当在本说明书中使用时指定存在所陈述的特征、整数、步骤、操作、元素、和/或部件，但是并不排除存在或添加一个或多个其他特征、整数、步骤、操作、元素、部件、和/或其分组。
还应理解，说明书通篇中提到的“一个实施例”、“一实施例”、“一种可能的实现方式”意味着与实施例或实现方式有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”、“一种可能的实现方式”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (12)

  1. 一种应用于车辆中的控制系统，其特征在于，所述控制系统包括至少一个处理器、第一存储器和第二存储器，所述第一存储器以可插拔的方式与所述至少一个处理器连接，所述第二存储器与所述至少一个处理器固定连接；
    所述第一存储器用于存储第一数据，所述第二存储器用于存储第二数据，所述第一数据和所述第二数据的更新程度不同，所述更新程度包含更新频率和/或重要程度。
  2. 根据权利要求1所述的控制系统，其特征在于，所述第一数据包括地图数据和/或路况数据。
  3. 根据权利要求2所述的控制系统，其特征在于，所述第一存储器还用于存储所述车辆的操作系统软件和/或应用程序。
  4. 根据权利要求1-3任一项所述的控制系统，其特征在于，所述第二数据包括所述车辆的操作系统软件和/或应用程序。
  5. 根据权利要求1-4任一项所述的控制系统，其特征在于，所述第一存储器和所述第二存储器满足以下中的至少一个：
    所述第一存储器的存储容量大于所述第二存储器的存储容量；
    所述第一存储器的更新频率高于所述第二存储器的更新频率；
    所述第一存储器中的第一数据的重要程度低于所述第二存储器中的第二数据的重要程度。
  6. 根据权利要求1-5任一项所述的控制系统，其特征在于，所述第一存储器为固态驱动器SSD存储卡，所述第二存储器为通用闪存UFS存储器。
  7. 根据权利要求1-6任一项所述的控制系统，其特征在于，所述至少一个处理器用于执行智能驾驶或者自动驾驶的控制。
  8. 根据权利要求1-7任一项所述的控制系统，其特征在于，所述至少一个处理器用于在所述第一存储器的坏块率达到预设比例的情况下，发出第一告警信号，所述第一告警信号用于指示更换所述第一存储器。
  9. 根据权利要求8所述的控制系统，其特征在于，所述至少一个处理器用于在所述第一存储器出现坏块的情况下，发出第一告警信号，包括：
    所述至少一个处理器用于在所述第一存储器出现坏块的情况下，通过所述车辆的中控屏发出所述第一告警信号。
  10. 根据权利要求1-9任一项所述的控制系统，其特征在于，所述至少一个处理器用于在所述第一存储器未成功与所述至少一个处理器连接的情况下，发出第二告警信号，所述第二告警信号用于指示所述第一存储器与所述至少一个处理器连接失败。
  11. 根据权利要求10所述的控制系统，其特征在于，所述第一存储器与所述至少一个处理器通过连接器连接，所述连接器包括的第一引脚和第二引脚连接所述第一存储器与所述至少一个处理器；所述至少一个处理器具体用于：
    检测所述第一引脚和第二引脚的电平信号；
    在所述第一引脚和所述第二引脚的电平信号中至少有一个为低电平信号的情况下，发出所述第二告警信号。
  12. 一种车辆，其特征在于，所述车辆包括权利要求1-11任一项所述的控制系统。
PCT/CN2022/108904 2022-07-29 2022-07-29 应用于车辆中的控制系统及车辆 WO2024021010A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10029401A1 (de) * 2000-06-15 2001-12-20 Pascal Munnix Verfahren zum ereignisbedingten Abspeichern von Fahrzeugsystemdaten
CN103064759A (zh) * 2012-12-18 2013-04-24 华为技术有限公司 数据修复的方法及装置
CN108162977A (zh) * 2017-11-25 2018-06-15 深圳市元征科技股份有限公司 驾驶辅助系统及控制方法
CN109910908A (zh) * 2019-02-20 2019-06-21 百度在线网络技术（北京）有限公司 一种驾驶参考线处理方法、装置、车辆及服务器
CN111210012A (zh) * 2018-11-21 2020-05-29 上海寒武纪信息科技有限公司 数据处理方法、装置及相关产品

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10029401A1 (de) * 2000-06-15 2001-12-20 Pascal Munnix Verfahren zum ereignisbedingten Abspeichern von Fahrzeugsystemdaten
CN103064759A (zh) * 2012-12-18 2013-04-24 华为技术有限公司 数据修复的方法及装置
CN108162977A (zh) * 2017-11-25 2018-06-15 深圳市元征科技股份有限公司 驾驶辅助系统及控制方法
CN111210012A (zh) * 2018-11-21 2020-05-29 上海寒武纪信息科技有限公司 数据处理方法、装置及相关产品
CN109910908A (zh) * 2019-02-20 2019-06-21 百度在线网络技术（北京）有限公司 一种驾驶参考线处理方法、装置、车辆及服务器

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