WO2024020768A1 - 滤波电路、滤波器及其制备方法、电子设备 - Google Patents

滤波电路、滤波器及其制备方法、电子设备 Download PDF

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Publication number
WO2024020768A1
WO2024020768A1 PCT/CN2022/107817 CN2022107817W WO2024020768A1 WO 2024020768 A1 WO2024020768 A1 WO 2024020768A1 CN 2022107817 W CN2022107817 W CN 2022107817W WO 2024020768 A1 WO2024020768 A1 WO 2024020768A1
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WIPO (PCT)
Prior art keywords
capacitor
inductor
filter
circuit
filter circuit
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PCT/CN2022/107817
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English (en)
French (fr)
Inventor
冯昱霖
李月
肖月磊
李慧颖
曹雪
韩基挏
任艳飞
吴艺凡
常文博
安齐昌
李必奇
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280002358.0A priority Critical patent/CN117813763A/zh
Priority to PCT/CN2022/107817 priority patent/WO2024020768A1/zh
Publication of WO2024020768A1 publication Critical patent/WO2024020768A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/12—Bandpass or bandstop filters with adjustable bandwidth and fixed centre frequency

Definitions

  • the present disclosure belongs to the field of communication technology, and specifically relates to a filter circuit, a filter and a preparation method thereof, and electronic equipment.
  • the present invention aims to solve at least one of the technical problems existing in the prior art and provide a filter circuit, a filter and a preparation method thereof, and electronic equipment.
  • an embodiment of the present disclosure provides a filter circuit, which includes a first resonator circuit, a second resonator circuit and an impedance matching network; the first resonator circuit and the second resonator circuit are respectively connected to the The above impedance matching network is connected in series;
  • the first resonator circuit is configured to allow signals higher than a first frequency to pass; the second resonator circuit is configured to allow signals lower than a second frequency to pass, and the second frequency is greater than the first frequency;
  • the impedance matching network allows signals between the first frequency and the second frequency to pass; wherein the impedance matching network includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, and a second capacitor. capacitor and first inductor;
  • the first end of the first capacitor is connected to the first end of the fourth capacitor, and the second end of the first capacitor is connected to the first end of the first inductor and the first end of the second capacitor;
  • the second end of the second capacitor is connected to the first end of the third capacitor and the second end of the fifth capacitor;
  • the second end of the fourth capacitor is connected to the first end of the fifth capacitor and the second end of the fifth capacitor.
  • the first resonant sub-circuit is connected to the first end of the first capacitor, and the second resonant sub-circuit is connected to the second end of the third capacitor;
  • the second resonant subcircuit is connected to the first end of the first capacitor, and the first resonant subcircuit is connected to the second end of the third capacitor.
  • the first resonant sub-circuit includes a sixth capacitor and a second inductor; the sixth capacitor and the second inductor are connected in parallel.
  • the value of the sixth capacitor is less than 20pF; and/or the value of the second inductor is less than 20nH.
  • the second resonant sub-circuit includes a seventh capacitor and a third inductor; the seventh capacitor and the third inductor are connected in parallel.
  • the value of the seventh capacitor is less than 20pF; and/or the value of the third inductor is less than 20nH.
  • the values of the first capacitor, the second capacitor, the third capacitor, the fourth capacitor and the fifth capacitor are all less than 20pF; and/or the value of the first inductor is less than 20nH. .
  • the impedance matching network further includes an eighth capacitor; a first end of the eighth capacitor is connected to the first resonant sub-circuit, and a second end of the third capacitor is connected to the second resonant sub-circuit; The second terminal of the eighth capacitor is connected to the first terminal of the first capacitor and the first terminal of the fourth capacitor.
  • the present disclosure provides a filter, including any one of the above filter circuits.
  • the filter further includes a first substrate, and the filter circuit is provided on the first substrate;
  • the first resonator circuit, the second resonator circuit and the impedance matching network all include Capacitance and inductance, the capacitance in the impedance matching network includes the first capacitance, the second capacitance, the third capacitance, the fourth capacitance, and the fifth capacitance;
  • the capacitor includes the first inductor;
  • the inductor includes a plurality of substructures arranged sequentially in a direction away from the first substrate, and an interlayer insulating layer is formed; the adjacent substructures pass through the The through-hole connection of the interlayer insulating layer forms the coil structure of the inductor;
  • the capacitor includes a first pole plate and a second pole plate arranged sequentially in a direction away from the first substrate substrate, and is arranged on the first pole A dielectric layer between the plate and the second plate.
  • At least one of the first pole plate and the second pole plate is arranged on the same layer as the substructure.
  • the orthographic projections of any two of the plurality of substructures on the first substrate overlap.
  • the filter further includes a protective layer located on a side of the inductor and the capacitor away from the first substrate.
  • the filter further includes a packaging substrate, the protective layer is provided with an opening at a position corresponding to a port of the filter circuit, and each port of the filter circuit is connected to the packaging substrate through the opening.
  • connection structure is provided in the opening, and each port of the filter circuit is connected to the packaging substrate through the corresponding connection structure.
  • an embodiment of the present disclosure provides a method for manufacturing a filter, which includes the step of forming a filter circuit on a first substrate, wherein the filter circuit includes any one of the above filter circuits.
  • the first resonant sub-circuit, the second resonant sub-circuit and the impedance matching network all include capacitors and inductors; the step of forming the inductors includes:
  • Substructures are formed sequentially on the first substrate, and an interlayer insulating layer is formed between the substructures.
  • the adjacent substructures are connected through the via holes of the interlayer insulating layer to form a coil structure of the inductor;
  • the steps of forming the capacitor include:
  • a first pole plate and a second pole plate are formed sequentially in a direction away from the first base substrate, and a dielectric layer is disposed between the first pole plate and the second pole plate.
  • At least one of the first pole plate and the second pole plate and the substructure are formed in one process.
  • the orthographic projections of any two of the plurality of substructures on the first substrate overlap.
  • the method of manufacturing the filter further includes forming a protective layer on a side of the inductor and the capacitor away from the first substrate.
  • an example of the present disclosure provides an electronic device, which includes any of the above filters.
  • Figure 1 is a circuit diagram of a filter circuit according to an embodiment of the present disclosure.
  • FIG. 2 is a simulation diagram of filtering performance of the filter circuit according to the embodiment of the present disclosure.
  • FIG. 3 is a circuit diagram of another filter circuit according to an embodiment of the present disclosure.
  • Figure 4 is a layout of a filter according to an embodiment of the present disclosure.
  • Figure 5 is a partial cross-sectional view of the filter according to an embodiment of the present disclosure.
  • Figure 6 is another partial cross-sectional view of a filter according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of an intermediate product formed in step S11 of the filter manufacturing method according to the embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of an intermediate product formed in step S12 of the filter manufacturing method according to the embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of an intermediate product formed in step S13 of the filter manufacturing method according to the embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of an intermediate product formed in step S14 of the filter manufacturing method according to the embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of an intermediate product formed in step S15 of the filter manufacturing method according to the embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of an intermediate product formed in step S16 of the filter manufacturing method according to the embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of an intermediate product formed in step S17 of the filter manufacturing method according to the embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of an intermediate product formed in step S18 of the filter manufacturing method according to the embodiment of the present disclosure.
  • FIG. 1 is a circuit diagram of a filter circuit according to an embodiment of the present disclosure; as shown in FIG. 1 , an embodiment of the present disclosure provides a filter circuit, which includes a first resonator circuit 11, a second resonator circuit 12 and an impedance. Matching network13.
  • the first resonator circuit 11 is configured to allow signals higher than the first frequency to pass
  • the second resonator circuit 12 is configured to allow signals lower than the second frequency to pass, and the second frequency is greater than the first frequency.
  • the impedance matching network 13 allows signals between the first frequency and the second frequency to pass.
  • the first resonator circuit 11 is a high-pass filter, used to adjust the left sideband of the signal
  • the second resonator circuit 12 is a low-pass filter, used to adjust the right sideband of the signal.
  • the impedance matching network 13 is equivalent to a band-pass filter, attenuating signals smaller than the first frequency and larger than the second frequency. The out-of-band attenuation and transmission zero point are adjusted through the first resonant sub-circuit 11, the second resonant sub-circuit 12 and the impedance matching network 13, so that it has the characteristics of large bandwidth, low loss, and fast out-of-band attenuation in the radio frequency range.
  • the electrical connection relationships between the first resonant sub-circuit 11, the second resonant sub-circuit 12 and the impedance matching network 13 can be interchanged.
  • the impedance matching network 13 is connected between the first resonant sub-circuit 11 and the second resonant sub-circuit 11.
  • the resonator circuits 12 that is, the first resonator circuit 11 and the second resonator circuit 12 are arranged symmetrically with respect to the impedance matching network 13 .
  • the first resonant sub-circuit 11 and the second resonant sub-circuit 12 are symmetrically arranged with respect to the impedance matching network 13 as an example, but this does not constitute a connection method for the filter circuit in the embodiment of the present disclosure. limit.
  • one end of the first resonant circuit 11 is connected to the impedance matching network 13, and the other end serves as the input port of the filter circuit.
  • One end of the second resonant circuit 12 is connected to the impedance matching network 13, and the other end is As the output port of the filter circuit.
  • the impedance matching network 13 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5 and a first inductor L1; the first capacitor C1
  • the first end of the fourth capacitor C4 is connected to the first end of the first resonant sub-circuit 11; the second end of the first capacitor C1 is connected to the first end of the first inductor L1 and the first end of the second capacitor C2;
  • the second end of the second capacitor C2 is connected to the first end of the third capacitor C3 and the second end of the fifth capacitor C5; the second end of the third capacitor C3 is connected to the second resonant subcircuit 12; the second end of the fourth capacitor C4 Connect the first terminal of the fifth capacitor C5, the second terminal of the first inductor L1 and the reference signal terminal.
  • the reference signal terminal includes but is not limited to the ground terminal GND.
  • the impedance matching network 13 in the embodiment of the present disclosure constitutes the main part of the filter circuit.
  • the first capacitor C1, the second capacitor C2 and the third capacitor C3 are connected in series on the main line.
  • the fourth capacitor C4, the fifth capacitor C5 and the first capacitor C5 are connected in series on the branch line.
  • the combined adjustment of inductor L1 can form a structure with wide bandwidth and low in-band fluctuation.
  • the embodiment of the present disclosure by combining the above-mentioned impedance matching network 13 with the first resonator circuit 11 and the second resonator circuit 12, a small and low-loss bandpass filter with low fluctuation within the bandpass can be effectively formed.
  • the first resonator circuit 11 may include a sixth capacitor and a second inductor L2 connected in parallel.
  • the second resonant circuit 12 may have a seventh capacitor and a third inductor L3 connected in parallel.
  • the inductor values in the filter circuit are less than 20nH. That is to say, the inductance values of the first inductor L1, the second inductor L2 and the third inductor L3 in the filter circuit are all small and less than 20 nH.
  • the capacitor values in the filter circuit are all less than 20pF. That is to say, the values of the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor and the seventh capacitor in the filter circuit are all less than 20pF.
  • the size of each component in the filter circuit is small, so the volume of the device can be effectively reduced, and at the same time, a high-performance filter circuit can be effectively formed in the high-frequency region.
  • Figure 2 is a simulation diagram of the filtering performance of the filter circuit according to the embodiment of the present disclosure. It can be seen from Figure 2 that the filter circuit has lower insertion loss in the bandpass area and a larger echo in the bandpass range. property, which is conducive to signal input and filtering. At the same time, it can be seen that the filter circuit has good out-of-band attenuation characteristics, which decreases rapidly outside the passband, which is conducive to effective signal filtering.
  • FIG. 3 is a circuit diagram of another filter circuit according to an embodiment of the present disclosure; as shown in FIG. 2 , an embodiment of the present disclosure also provides a filter circuit, which is the same as the filter circuit shown in FIG. 1
  • the matching impedance network in the filter circuit not only includes the above-mentioned first capacitor C1, second capacitor C2, third capacitor C3, fourth capacitor C4, fifth capacitor C5 and first inductor L1. It also includes an eighth capacitor C8.
  • the first terminal of the eighth capacitor C8 is connected to the first resonant subcircuit 11, and the second terminal of the eighth capacitor C8 is connected to the first terminal of the first capacitor C1 and the first terminal of the fourth capacitor C4.
  • FIG. 4 is a layout of a filter according to an embodiment of the present disclosure
  • FIG. 5 is a partial cross-sectional view of the filter according to an embodiment of the present disclosure
  • FIG. 6 is another partial cross-section of the filter according to an embodiment of the present disclosure. picture.
  • an embodiment of the present disclosure provides a filter, which includes the above filter circuit.
  • the filter in the implementation of the present disclosure also includes a first substrate 10 on which the filter circuit is disposed. That is, both the capacitor and the inductor in the filter circuit are arranged on the first base substrate 10 .
  • the capacitors and inductors in the filter circuit include capacitors and inductors in the first resonator circuit 11 , the second resonator circuit 12 and the impedance matching network 13 .
  • each capacitor in the first resonant sub-circuit 11, the second resonant sub-circuit 12 and the impedance matching network 13 is not distinguished, and they are all called capacitors.
  • each inductor is also not distinguished, and they are all called “capacitors”.
  • the inductor includes a plurality of substructures arranged sequentially in a direction away from the first substrate 10 , and an interlayer insulating layer is arranged between adjacent substructures. The adjacent substructures are passed through the interlayer insulating layer. The holes are connected to form the coil structure of the inductor.
  • each substructure has an open-loop structure, and the substructures located in adjacent layers are connected at the end to form the coil structure of the inductor.
  • the capacitor includes a first plate 201 and a second plate 202 arranged sequentially in a direction away from the first substrate 10 , and a dielectric layer 203 arranged between the first plate 201 and the second plate 202 .
  • the inductor includes three substructures arranged in a stack.
  • the three substructures are respectively called the first substructure 101 and the second substructure 102. and the third substructure 103.
  • the interlayer insulating layer between the first substructure 101 and the second substructure 102 is called the first interlayer insulating layer 301.
  • the interlayer insulating layer between the second substructure 102 and the third substructure 103 is called the first interlayer insulating layer 301.
  • the interlayer insulating layer is called the second interlayer insulating layer 302 .
  • the first substructure 101 of each inductor is placed on the same layer, the second substructure 102 is placed on the same layer, and the third substructure 103 is placed on the same layer.
  • the first plate 201 of each capacitor is placed on the same layer, and the second plate 202 is placed on the same layer. .
  • the capacitor and the inductor are connected through a first connection electrode 401, and the first connection electrode 401 is connected to the second connection electrode 402 for connecting external circuits.
  • first plate 201 and the second plate 202 of the capacitor is arranged on the same layer as the substructure of the inductor.
  • first plate 201 of the capacitor is placed on the same layer as a substructure, and the second plate 202 can be placed on a separate layer.
  • orthographic projections of any two of the layer substructures of the inductor on the first substrate 10 at least partially overlap. This arrangement method can effectively reduce the size of the device and help improve the integration of electronic equipment applying the filter circuit.
  • the filter not only includes the above structure, but may also include a protective layer disposed on the side of the capacitor and inductor away from the first substrate 10 to prevent components in the filter circuit from being corroded by water and oxygen.
  • openings are provided in the protective layer at positions corresponding to each port of the filter circuit.
  • openings penetrating the protective layer are formed at corresponding positions of the input port and the output port of the filter circuit, so as to facilitate the connection between the input port and the output port and the external circuit. connect.
  • the filter further includes a packaging substrate 20 , and each port of the filter circuit on the first substrate 10 communicates with the packaging substrate 20 through a connection structure 30 , which includes but is not limited to solder balls and copper pillars.
  • connection structure 30 uses solder balls
  • each port of the filter circuit and the packaging substrate 20 can be welded together.
  • connection structure 30 uses copper pillars
  • the copper pillars need to be connected to each port of the filter circuit through a conductive adhesive layer, and then the copper The pillars are then connected to the packaging substrate 20 . It should be understood that traces or other devices connected to the filter circuit are provided on the packaging substrate 20 .
  • first capacitors first capacitor C1, second capacitor C2, third capacitor C3, fourth capacitor C4 and fifth capacitor C5) and 3 inductors (the first inductor C5) in the filter circuit L1, the second inductor L2 and the third inductor L3)
  • the five capacitors are set together and placed below the three inductors to reduce the size of the device as much as possible and achieve the miniaturization of the filter.
  • the connection of the capacitor through the first plate 201 and the second plate 202 can be effectively connected to the inductor in the circuit through metal vias according to the circuit design.
  • embodiments of the present disclosure provide a method of manufacturing a filter, which method includes the step of forming the above-mentioned filter circuit on the first substrate 10 .
  • the preparation method of the filter according to the embodiment of the present disclosure will be described below in conjunction with specific methods.
  • each includes three substructures arranged in a stack.
  • the three substructures are respectively called the first substructure 101, the second substructure 102 and the third substructure 103.
  • the interlayer insulating layer between the first substructure 101 and the second substructure 102 is called the first interlayer insulating layer 301
  • the interlayer insulating layer between the second substructure 102 and the third substructure 103 is called the first interlayer insulating layer 301.
  • the second interlayer insulating layer 302. The first substructure 101 of each inductor is placed on the same layer, the second substructure 102 is placed on the same layer, and the third substructure 103 is placed on the same layer.
  • the first plate 201 of each capacitor is placed on the same layer, and the second plate 202 is placed on the same layer.
  • FIG. 7 is a schematic structural diagram of the intermediate product formed in step S11 of the filter manufacturing method according to the embodiment of the present disclosure
  • FIG. 8 is a schematic structural diagram of the intermediate product formed in step S12 of the filter manufacturing method according to the embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of an intermediate product formed in step S13 of the filter manufacturing method according to an embodiment of the present disclosure
  • FIG. 10 is a schematic structural diagram of an intermediate product formed in step S14 of the filter manufacturing method according to an embodiment of the present disclosure
  • FIG. 11 12 is a schematic structural diagram of the intermediate product formed in step S16 of the filter manufacturing method according to the embodiment of the present disclosure
  • FIG. 13 is a schematic structural diagram of the intermediate product formed in step S16 of the filter manufacturing method according to the embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of the intermediate product formed in step S18 of the filter manufacturing method according to the disclosed embodiment; combined with Figures 7-14,
  • the preparation method of the filter according to the embodiment of the present disclosure includes the following steps:
  • the material of the first base substrate 10 may be low conductivity materials such as glass, high resistance silicon, ceramics, etc., and the thickness of the first base substrate 10 is about 0.2 to 2 mm.
  • Step S11 may include cleaning the first base substrate 10, ultrasonic cleaning with deionized water and organic solvents, ultrasonic cleaning for more than 15 minutes, and finally drying in an oven at 70°C for 30 minutes.
  • step S12 may include forming a first conductive layer on the first base substrate 10 by a method including but not limited to sputtering, using the first conductive layer as a seed layer, spin-coating photoresist, exposure and development, Electroplating/chemical plating forms the first plate 201 of the capacitor and the first substructure 101 of the inductor.
  • the material of the first conductive layer includes, but is not limited to, Au, Al, Ag, Cu and other metal materials.
  • the thickness of the first plate 201 of the capacitor and the first substructure 101 of the inductor is about 1 to 20 ⁇ m.
  • the surface of the formed structure can be subjected to chemical mechanical polishing.
  • the material of the dielectric layer 203 may be an inorganic material, such as silicon nitride, silicon oxide, etc.; the thickness of the dielectric layer 203 is about 0.1-1 ⁇ m.
  • Step S13 may use materials including but not limited to physical vapor deposition (PVD) or chemical vapor deposition (CVD) to form the dielectric layer 203, and then spin-coating photoresist, exposure and development, and etching to form a substrate on the first plate 201 facing away from the first substrate. 10 side of the dielectric layer 203.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • the surface of the formed dielectric layer 203 can also be mechanically polished.
  • step S14 may adopt methods including but not limited to sputtering to form the second conductive layer, using the second conductive layer as a seed layer, spin coating photoresist, exposure and development, electroplating/chemical plating to form the second conductive layer of the capacitor.
  • Plate 202 The material of the second conductive layer includes, but is not limited to, Au, Al, Ag, Cu and other metal materials.
  • the second plate 202 of the capacitor is about 0.1 to 3 ⁇ m.
  • the material of the first interlayer insulating layer 301 may be an inorganic material, such as silicon nitride, silicon oxide, etc.; the thickness of the first interlayer insulating layer 301 is about 1-20 ⁇ m.
  • Step S15 may use, but is not limited to, PVD or CVD to form the first interlayer insulating layer 301 of inorganic materials, and then spin-coat photoresist, expose and develop, and etch to form the first via hole 501, the second via hole 502, and the like.
  • the material of the first interlayer insulating layer 301 may be an organic material, such as polyimide (PI) or other resin materials.
  • Step S15 may include a glue leveling process to pattern the first interlayer insulating layer 301 and also form the first via hole 501 , the second via hole 502 and the third via hole 503 .
  • first connection electrode 401 Form the first connection electrode 401 and the second substructure 102 of the inductor.
  • the first connection electrode 401 electrically connects the first substructure 101 of the inductor and the second plate 202 of the capacitor through the first via hole 501 and the second via hole 502, and the second substructure 102 is connected to the second substructure 102 through the third via hole 503.
  • the first substructure 101 is connected as shown in Figure 12 .
  • step S14 may include forming a second conductive layer by a method including but not limited to sputtering, using the second conductive layer as a seed layer, spin coating photoresist, exposure and development, electroplating/chemical plating to form the first connection.
  • Electrode 401 and second substructure 102 of the inductor The material of the first conductive layer includes, but is not limited to, Au, Al, Ag, Cu and other metal materials.
  • the thickness of the first plate 201 of the capacitor and the first substructure 101 of the inductor is about 1 to 20 ⁇ m.
  • the material of the second interlayer insulating layer 302 may be an inorganic material, such as silicon nitride, silicon oxide, etc.; the thickness of the second interlayer insulating layer 302 is about 1-20 ⁇ m.
  • Step S17 may use, but is not limited to, PVD or CVD to form the second interlayer insulating layer 302 of inorganic materials, followed by spin coating of photoresist, exposure and development, and etching to form the fourth via hole 601 and the fifth via hole 602.
  • the material of the second interlayer insulating layer 302 may be an organic material, such as polyimide (PI) or other resin materials.
  • Step S17 may include a glue leveling process to pattern the second interlayer insulating layer 302, and also form the fourth via hole 601 and the fifth via hole 602.
  • connection electrode 402 and the third substructure 103 of the inductor Form the second connection electrode 402 and the third substructure 103 of the inductor.
  • the third substructure 103 is connected to the second substructure 102 through the fourth via hole 601
  • the second connection electrode 402 is connected to the first connection electrode 401 through the fifth via hole 602 .
  • the second connection electrode 402 and the first connection electrode 401 can be connected as input ports of the filter circuit, as shown in FIG. 14 .
  • connection structure 30 is formed in the first opening and the second opening to connect the wiring on the packaging cover.
  • the line is electrically connected to the port on the filter circuit.
  • the connection structure 30 can be a solder ball or a copper pillar. When the connection structure 30 uses solder balls, each port of the filter circuit and the packaging substrate 20 can be welded together. When the connection structure 30 uses copper pillars, the copper pillars need to be connected to each port of the filter circuit through a conductive adhesive layer, and then the copper The pillars are then connected to the packaging substrate 20 .
  • the material of the protective layer can be inorganic materials, such as silicon nitride, silicon oxide, etc.; the thickness of the protective layer is about 1-20 ⁇ m.
  • Step S19 may use, but is not limited to, PVD or CVD to form the first interlayer insulating layer 301 of inorganic material, followed by spin coating of photoresist, exposure and development, and etching to form the first opening and the second opening.
  • the material of the protective layer may be organic materials, such as polyimide (PI) or other resin materials.
  • Step S19 may include a glue leveling process to pattern the protective layer and also form the first opening and the second opening.
  • the preparation method in the embodiment of the present disclosure may also include the step of connecting the lines on the packaging substrate 20 with the ports on the filter circuit. Specifically, welding can be used to connect.
  • an embodiment of the present disclosure further provides an electronic device, which includes the above-mentioned filter.

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Abstract

本公开提供一种滤波电路、滤波器及其制备方法、电子设备，属于通信技术领域。本公开的滤波电路，包括第一谐振子电路、第二谐振子电路和阻抗匹配网络；第一谐振子电路和第二谐振子电路分别与阻抗匹配网络串联；第一谐振子电路被配置为容许高于第一频率的信号通过；第二谐振子电路被配置为容许低于第二频率的信号通过，第二频率大于第一频率；阻抗匹配网络容许在第一频率和第二频率之间的信号通过；其中，阻抗匹配网络包括第一电容、第二电容、第三电容、第四电容、第五电容和第一电感。

Description

滤波电路、滤波器及其制备方法、电子设备 技术领域
本公开属于通信技术领域，具体涉及一种滤波电路、滤波器及其制备方法、电子设备。
背景技术
随着通讯信号技术的飞速发展，信号传输的方式和速度都得到了大幅提升。此外，半导体和微电子技术的进步，使得电子设备快速迭代，移动设备的数量不断增加，器件尺寸日益减小。尤其是在目前5G时代，移动通信技术产生了飞跃式的发展，高速率、低时延、大连接等特点都极大提升了通讯技术的进步。
通讯技术的发展也对于电子器件性能提出了更高的要求，高频信号的传输要求信号在大带宽的情况下进行高速信号的高功率传输，这要求电子设备具有良好的信号收发功能，同时可以有效的针对环境中无效的信号进行过滤。滤波器在射频前端设备中占据着至关重要的作用，滤波器通过对不同频率的信号进行通过和阻碍，实现了无用信号的过滤，以及有用信号的选频，因此，滤波器在射频前端中是必不可少的核心器件。滤波器有很多不同的种类，包括腔体滤波器、介质滤波器、LC滤波器等，其中LC滤波器通过不同数量的电感、电容和电阻根据电路设计进行不同的排列而实现滤波功能，其具有高性能、小体积、可集成制造等特点，是滤波器中常见的类型。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种滤波电路、滤波器及其制备方法、电子设备。
第一方面，本公开实施例提供一种滤波电路，其包括第一谐振子电路、第二谐振子电路和阻抗匹配网络；所述第一谐振子电路和所述第二谐振子电路分别与所述阻抗匹配网络串联；
所述第一谐振子电路被配置为容许高于第一频率的信号通过；第二谐振子电路被配置为容许低于第二频率的信号通过，所述第二频率大于所述第一 频率；所述阻抗匹配网络容许在所述第一频率和所述第二频率之间的信号通过；其中，所述阻抗匹配网络包括第一电容、第二电容、第三电容、第四电容、第五电容和第一电感；
所述第一电容的第一端和第四电容的第一端连接，所述第一电容的第二端与第一电感的第一端和所述第二电容的第一端连接；所述第二电容的第二端连接所述第三电容的第一端和所述第五电容的第二端；所述第四电容的第二端连接所述第五电容的第一端、所述第一电感的第二端以及参考信号端。
其中，所述第一谐振子电路与所述第一电容的第一端连接，所述第二谐振子电路与所述第三电容的第二端连接；或者，
所述第二谐振子电路与所述第一电容的第一端连接，所述第一谐振子电路与所述第三电容的第二端连接。
其中，所述第一谐振子电路包括第六电容和第二电感；所述第六电容和所述第二电感并联。
其中，所述第六电容的值小于20pF；和/或，所述第二电感的值小于20nH。
其中，所述第二谐振子电路包括第七电容和第三电感；所述第七电容和第三电感并联。
其中，所述第七电容的值小于20pF；和/或，所述第三电感的值小于20nH。
其中，所述第一电容、所述第二电容、所述第三电容、所述第四电容、所述第五电容的值均小于20pF；和/或，所述第一电感的值小于20nH。
其中，所述阻抗匹配网络还包括第八电容；所述第八电容的第一端连接所述第一谐振子电路，所述第三电容的第二端连接所述第二谐振子电路；所述第八电容的第二端连接所述第一电容的第一端和第四电容的第一端。
第二方面，本公开实施提供一种滤波器，包括上述任一所述的滤波电路。
其中，所述滤波器还包括第一衬底基板，所述滤波电路设置在所述第一 衬底基板上；所述第一谐振子电路、第二谐振子电路和所述阻抗匹配网络均包括电容和电感，所述阻抗匹配网络中的电容包括所述第一电容、所述第二电容、所述第三电容、所述第四电容、所述第五电容；所述阻抗匹配网络中的电容包括所述第一电感；所述电感包括沿背离所述第一衬底基板方向依次设置的多个子结构，且在形成设置的层间绝缘层；相邻设置的所述子结构通过所述层间绝缘层的过孔连接，形成电感的线圈结构；所述电容包括沿背离所述第一衬底基板方向依次设置的第一极板和第二极板，以及设置在所述第一极板和所述第二极板之间的介质层。
其中，所述第一极板和所述第二极板中的至少一者与所述子结构同层设置。
其中，多个所述子结构中的任意两个在所述第一衬底基板上的正投影存在交叠。
其中，所述滤波器还包括位于所述电感和所述电容背离所述第一衬底基板一侧的保护层。
其中，所述滤波器还包括封装基板，所述保护层与所述滤波电路的端口对应的位置设置有开口，所述滤波电路的各端口通过所述开口与所述封装基板连接。
其中，在所述开口中设置有连接结构，所述所述滤波电路的各端口分别通过对应的所述连接结构与所述封装基板连接。
第三方面，本公开实施例提供一种滤波器的制备方法，其包括：在第一衬底基板上形成滤波电路的步骤，其中，滤波电路包括上述任一所述的滤波电路。
其中，所述第一谐振子电路、第二谐振子电路和所述阻抗匹配网络均包括电容和电感；形成所述电感的步骤包括：
在第一衬底基板上依次形成子结构，并在子结构之间形成层间绝缘层，相邻设置的所述子结构通过所述层间绝缘层的过孔连接，形成电感的线圈结构；
形成所述电容的步骤包括：
沿背离所述第一衬底基板方向依次形成的第一极板和第二极板，以及设置在所述第一极板和所述第二极板之间的介质层。
其中，所述第一极板和所述第二极板中的至少一者与所述子结构在一次工艺中形成。
其中，多个所述子结构中的任意两个在所述第一衬底基板上的正投影存在交叠。
其中，所述滤波器的制备方法还包括在所述电感和所述电容背离所述第一衬底基板一侧形成保护层。
第四方面，本公开示例提供一种电子设备，其包括上述任一所述的滤波器。
附图说明
图1为本公开实施例的一种滤波电路的电路图。
图2为本公开实施例的滤波电路的滤波性能仿真图。
图3为本公开实施例的另一种滤波电路的电路图。
图4为本公开实施例的滤波器的版图。
图5为本公开实施例的滤波器的一种局部截面图。
图6为本公开实施例的滤波器的另一种局部截面图。
图7为本公开实施例的滤波器的制备方法的步骤S11所形成的中间产品结构示意图。
图8为本公开实施例的滤波器的制备方法的步骤S12所形成的中间产品结构示意图。
图9为本公开实施例的滤波器的制备方法的步骤S13所形成的中间产品结构示意图。
图10为本公开实施例的滤波器的制备方法的步骤S14所形成的中间产品结构示意图。
图11为本公开实施例的滤波器的制备方法的步骤S15所形成的中间产品结构示意图。
图12为本公开实施例的滤波器的制备方法的步骤S16所形成的中间产品结构示意图。
图13为本公开实施例的滤波器的制备方法的步骤S17所形成的中间产品结构示意图。
图14为本公开实施例的滤波器的制备方法的步骤S18所形成的中间产品结构示意图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
第一方面，图1为本公开实施例的滤波电路的电路图；如图1所示，本公开实施例提供一种滤波电路，其包括第一谐振子电路11、第二谐振子电路12和阻抗匹配网络13。第一谐振子电路11被配置为容许高于第一频率的信 号通过，第二谐振子电路12被配置为容许低于第二频率的信号通过，且第二频率大于第一频率。阻抗匹配网络13容许在第一频率和第二频率之间的信号通过。也就是说，第一谐振子电路11为高通滤波器，用于对信号的左侧边带进行调整；第二谐振子电路12为低通滤波器，用于对信号的右侧带边进行调整；阻抗匹配网络13相当于带通滤波器，对于小于第一频率和大于第二频率的信号进行衰减。通过第一谐振子电路11、第二谐振子电路12和阻抗匹配网络13调节带外衰减和传输零点，在射频范围内兼具大带宽、低损耗、快速带外衰减等特点。
其中，第一谐振子电路11、第二谐振子电路12和阻抗匹配网络13三者的电学连接关系可以互换，在一个示例中，阻抗匹配网络13连接在第一谐振子电路11和第二谐振子电路12之间，也即第一谐振子电路11和第二谐振子电路12相对于阻抗匹配网络13对称设置。当然，本公开实施例中也仅以第一谐振子电路11和第二谐振子电路12相对于阻抗匹配网络13对称设置为例，但这并不构成对本公开实施例的滤波电路的连接方式的限制。同时，还需要说明的是，第一谐振子电路11一端与阻抗匹配网络13连接，另一端则作为滤波电路的输入端口，第二谐振子电路12的一端与阻抗匹配网络13连接，另一端则作为滤波电路的输出端口。
在本公开实施例中，参照图1，阻抗匹配网络13包括第一电容C1、第二电容C2、第三电容C3、第四电容C4、第五电容C5和第一电感L1；第一电容C1的第一端连接第四电容C4的第一端和第一谐振子电路11；第一电容C1的第二端与第一电感L1的第一端和第二电容C2的第一端连接；第二电容C2的第二端连接第三电容C3的第一端和第五电容C5的第二端；第三电容C3的第二端连接第二谐振子电路12；第四电容C4的第二端连接第五电容C5的第一端、第一电感L1的第二端以及参考信号端。参考信号端包括但不限于接地端GND。
在本公开实施例中的阻抗匹配网络13构成滤波电路的主要部分，主线上第一电容C1、第二电容C2和第三电容C3串联，支线上第四电容C4、第五电容C5和第一电感L1组合调节，可以形成宽带宽且带内波动低的结构。 同时，在本公开实施例通过上述的阻抗匹配网络13和第一谐振子电路11、第二谐振子电路12组合，可以有效形成具有带通内低波动的小型低损耗的带通滤波器。
在一些示例中，第一谐振子电路11可以包括并联的第六电容和第二电感L2。第二谐振子电路12可以并联的第七电容和第三电感L3。
在一些示例中，滤波电路中的电感值均小于20nH。也就是说，滤波电路中的第一电感L1、第二电感L2和第三电感L3的电感值均较小，且小于20nH。滤波电路中的电容值均小于20pF。也就是说，滤波电路中的第一电容C1、第二电容C2、第三电容C3、第四电容C4、第五电容C5、第六电容和第七电容的值均小于20pF。在该种情况下，滤波电路中的各元件的尺寸均较小，故可以有效的减小器件的体积，同时可以有效在高频区域形成高性能的滤波电路。
图2为本公开实施例的滤波电路的滤波性能仿真图，从图2中可以看到滤波电路在带通区域内具有较低的插入损耗，同时在带通范围内具有较大的回波特性，有利于信号的输入及滤波。同时，可以看出该滤波电路具有较好的带外衰减特性，在通带外侧快速下降，有利于信号的有效滤波。
在一些示例中，图3为本公开实施例的另一种滤波电路的电路图；如图2所示，本公开实施例中还提供一种滤波电路，该滤波电路与图1所示的滤波电路结构大致相同，区别仅在于，该滤波电路中的匹配阻抗网络不仅包括上述的第一电容C1、第二电容C2、第三电容C3、第四电容C4、第五电容C5和第一电感L1，而且还包括第八电容C8。该第八电容C8的第一端连接第一谐振子电路11，第八电容C8的第二端连接第一电容C1的第一端和第四电容C4的第一端。第三电容C3的第二端连接第二谐振子电路12。由图3可以看出的是第一谐振子电路11和第二谐振子电路12相对于阻抗配网络13呈对称设置。该种设置结构具有较好的带外衰减特性，在通带外侧快速下降，有利于信号的有效滤波。第二方面，图4为本公开实施例的滤波器的版图；图5为本公开实施例的滤波器的一种局部截面图；图6为本公开实施例的滤波器的另一种局部截面图。结合图4-6所示，本公开实施例提供一种 滤波器，该滤波器包括上述的滤波电路。本公开实施中的滤波器还包括第一衬底基板10，滤波电路设置在第一衬底基板10上。也即，滤波电路中的电容和电感均设置在第一衬底基板10上。其中，滤波电路中的电容和电感包括第一谐振子电路11、第二谐振子电路12和阻抗匹配网络13中的各个电容和各个电感。以下为便于描述，对于第一谐振子电路11、第二谐振子电路12和阻抗匹配网络13中的各个电容不进行区分，均称之为电容，同理各个电感也不进行区分，均称之为电感。其中，电感包括沿背离第一衬底基板10方向依次设置的多个子结构，且相邻设置的子结构之间设置有层间绝缘层，相邻设置的子结构通过贯穿层间绝缘层的过孔连接，形成电感的线圈结构，例如：各个子结构呈开环结构，位于相邻层的子结构收尾连接，从而形成电感的线圈结构。电容包括沿背离第一衬底基板10方向依次设置的第一极板201和第二极板202，以及设置在第一极板201和第二极板202之间的介质层203。
需要说明的是，图中以一个电感与一个电容连接为例，电感包括叠层设置的三个子结构，为例便于描述将三个子结构分别称之为第一子结构101、第二子结构102和第三子结构103，第一子结构101和第二子结构102之间的层间绝缘层称之为第一层间绝缘层301，第二子结构102和第三子结构103之间的层间绝缘层称之为第二层间绝缘层302。各个电感的第一子结构101同层设置，第二子结构102同层设置，第三子结构103同层设置，各电容的第一极板201同层设置，第二极板202同层设置。电容和电感之间通过第一连接电极401连接，且第一连接电极401与第二连接电极402连接，用于连接外部线路。
进一步的，电容的第一极板201和第二极板202中的至少一者与电感的子结构同层设置。例如：电容的第一极板201与一子结构同层设置，第二极板202可以单独设置一层结构。
进一步的，电感的各层子结构中任意两者在第一衬底基板10上的正投影至少部分重叠。通过该种设置方式可以有效的缩小器件尺寸，有助于提高应用该滤波电路的电子设备的集成度。
在一些示例中，该滤波器不仅包括上述结构，还可以包括设置在电容和电感背离第一衬底基板10一侧的保护层，用以防止滤波电路中的器件被水氧侵蚀。
进一步的，在保护层与滤波电路的各端口对应的位置设置开口，例如在滤波电路的输入端口和输出端口的对应的位置分别形成贯穿保护层的开口，以便于输入端口和输出端口与外部线路连接。
在一些示例中，该滤波器还包括封装基板20，第一衬底基板10上的滤波电路的各端口与封装基板20通过连接结构30，该连接结构30包括但不限于锡球、铜柱。当连接结构30采用锡球时，滤波电路的各端口与封装基板20可以焊接在一起，当连接结构30采用铜柱时，铜柱需要通过导电粘结层和滤波电路的各端口连接，之后铜柱再与封装基板20连接。应当理解的是，在封装基板20上设置有滤波电路连接的走线或者其他器件。
在一些示例中，参照图3，滤波电路中的5个电容(第一电容C1、第二电容C2、第三电容C3、第四电容C4和第五电容C5)和3个电感(第一电感L1、第二电感L2和第三电感L3)可以按照图3中的方式设置，也即5个电容集中设置，设置在3个电感的下方，尽可能的缩小器件体积，实现滤波器的小型化。电容的连接通过第一极板201和第二极板202可以通过金属过孔的方式根据电路设计与电路中的电感有效连接。
对于滤波器中的各层结构的材质具体结合下述滤波器的制备方法进行说明。
第三方面，本公开实施例提供一种滤波器的制备方法，该方法包括第一衬底基板10上形成上述的滤波电路的步骤。以下结合具体方法对本公开实施例的滤波器的制备方法进行说明。其中，以滤波电路中的电感均包括叠层设置的三个子结构为例，为例便于描述将三个子结构分别称之为第一子结构101、第二子结构102和第三子结构103，第一子结构101和第二子结构102之间的层间绝缘层称之为第一层间绝缘层301，第二子结构102和第三子结构103之间的层间绝缘层称之为第二层间绝缘层302。各个电感的第一子结 构101同层设置，第二子结构102同层设置，第三子结构103同层设置，各电容的第一极板201同层设置，第二极板202同层设置，故在下述制备方法中仅以第一谐振子电路11中的电容和电感的制备流程进行说明。
其中，图7为本公开实施例的滤波器的制备方法的步骤S11所形成的中间产品结构示意图；图8为本公开实施例的滤波器的制备方法的步骤S12所形成的中间产品结构示意图；图9为本公开实施例的滤波器的制备方法的步骤S13所形成的中间产品结构示意图；图10为本公开实施例的滤波器的制备方法的步骤S14所形成的中间产品结构示意图；图11为本公开实施例的滤波器的制备方法的步骤S15所形成的中间产品结构示意图；图12为本公开实施例的滤波器的制备方法的步骤S16所形成的中间产品结构示意图；图13为本公开实施例的滤波器的制备方法的步骤S17所形成的中间产品结构示意图；图14为本公开实施例的滤波器的制备方法的步骤S18所形成的中间产品结构示意图；结合图7-14，本公开实施例的滤波器的制备方法包括如下步骤：
S11、提供一第一衬底基板10，如图7所示。
在一些示例中，第一衬底基板10的材料可以为玻璃、高阻硅、陶瓷等低电导率的材料，第一衬底基板10的厚度在0.2～2mm左右。在步骤S11中可以包括对第一衬底基板10进行清洗，通过去离子水和有机溶剂等进行超声清洗，分别进行15min以上超声，最后通过烘箱烘干，70℃下烘干30min。
S12、在第一衬底基板10上形成电容的第一极板201和电感的第一子结构101，如图8所示。
在一些示例中，步骤S12可以包括在第一衬底基板10上采用包括但不限于溅射的方式形成第一导电层，将第一导电层作为种子层，旋涂光刻胶、曝光显影、电镀/化学镀形成电容的第一极板201和电感的第一子结构101。其中，第一导电层的材料包括但不限于Au、Al、Ag、Cu等金属材料。电容的第一极板201和电感的第一子结构101的厚度在1～20μm左右。
进一步的，为了保证平整度还可以在电镀/化学镀形成电容的第一极板 201和电感的第一子结构101后，对所形成的结构进行化学机械研磨处理表面。
S13、形成电容的介质层203，如图9所示。
在一些示例中，介质层203的材料可以为无机材料，如氮化硅、氧化硅等；介质层203的厚度在0.1-1μm左右。其中，步骤S13可以采用包括但不限于物理气相沉积PVD或者化学气相沉积CVD形成介质层203材料，之后旋涂光刻胶、曝光显影、刻蚀形成位于第一极板201背离第一衬底基板10一侧的介质层203。当然，为例保证膜层的平整度，还可以对形成的介质层203进行学机械研磨处理表面。
S14、形成电容的第二极板202，如图10所示。
在一些示例中，步骤S14可以采用包括但不限于溅射的方式形成第二导电层，将第二导电层作为种子层，旋涂光刻胶、曝光显影、电镀/化学镀形成电容的第二极板202。其中，第二导电层的材料包括但不限于Au、Al、Ag、Cu等金属材料。电容的第二极板202在0.1～3μm左右。
S15、形成第一层间绝缘层301，并在对应电容的第二极板202的位置形成第一过孔501、对应电容的第一子结构101对应的位置形成第二过孔502和第三过孔503，如图11所示。
在一些示例中，第一层间绝缘层301的材料可以为无机材料，例如：氮化硅、氧化硅等；第一层间绝缘层301的厚度在1-20μm左右。其中，步骤S15可以采用包括但不限于PVD或者CVD形成无机材料的第一层间绝缘层301，之后旋涂光刻胶、曝光显影、刻蚀形成第一过孔501、第二过孔502和第三过孔503。
在一些示例中，第一层间绝缘层301的材料可以为有机材料，例如：聚酰亚胺(PI)或其他树脂材料。其中，步骤S15可以包括匀胶工艺实现第一层间绝缘层301的图案化，也形成第一过孔501、第二过孔502和第三过孔503。
S16、形成第一连接电极401和电感的第二子结构102。其中，第一连 接电极401通过第一过孔501和第二过孔502将电感的第一子结构101和电容的第二极板202电连接，第二子结构102通过第三过孔503与第一子结构101连接，如图12所示。
在一些示例中，步骤S14可以包括采用包括但不限于溅射的方式形成第二导电层，将第二导电层作为种子层，旋涂光刻胶、曝光显影、电镀/化学镀形成第一连接电极401和电感的第二子结构102。其中，第一导电层的材料包括但不限于Au、Al、Ag、Cu等金属材料。电容的第一极板201和电感的第一子结构101的厚度在1～20μm左右。
S17、形成第二层间绝缘层302，并在对应电感的第二子结构102的位置形成第四过孔601、对应第一连接对应的位置形成第五过孔602，如图13所示。
在一些示例中，第二层间绝缘层302的材料可以为无机材料，例如：氮化硅、氧化硅等；第二层间绝缘层302的厚度在1-20μm左右。其中，步骤S17可以采用包括但不限于PVD或者CVD形成无机材料的第二层间绝缘层302，之后旋涂光刻胶、曝光显影、刻蚀形成第四过孔601和第五过孔602。
在一些示例中，第二层间绝缘层302的材料可以为有机材料，例如：聚酰亚胺(PI)或其他树脂材料。其中，步骤S17可以包括匀胶工艺实现第二层间绝缘层302的图案化，也形成第四过孔601和第五过孔602。
S18、形成第二连接电极402和电感的第三子结构103。其中，第三子结构103通过第四过孔601与第二子结构102连接，第二连接电极402通过第五过孔602与第一连接电极401连接。第二连接电极402和第一连接电极401连可以作为滤波电路的输入端口，如图14所示。
S19、形成保护层，形成贯穿保护层的第一开口和第二开口。其中，第一开口和第二开口可以用于将封装基板20上的线路与滤波电路上的端口电连接所用，例如：在第一开口和第二开口中形成连接结构30将封装盖板上的线路与滤波电路上的端口电连接。连接结构30可以锡球或者铜柱。当连接结构30采用锡球时，滤波电路的各端口与封装基板20可以焊接在一起， 当连接结构30采用铜柱时，铜柱需要通过导电粘结层和滤波电路的各端口连接，之后铜柱再与封装基板20连接。
在一些示例中，保护层的材料可以为无机材料，例如：氮化硅、氧化硅等；保护层的厚度在1-20μm左右。其中，步骤S19可以采用包括但不限于PVD或者CVD形成无机材料的第一层间绝缘层301，之后旋涂光刻胶、曝光显影、刻蚀形成第一开口和第二开口。
在一些示例中，保护层的材料可以为有机材料，例如：聚酰亚胺(PI)或其他树脂材料。其中，步骤S19可以包括匀胶工艺实现保护层的图案化，也形成第一开口和第二开口。
当然，本公开实施例中的制备方法还可以包括将封装基板20上的线路与滤波电路上的端口连接的步骤。具体可以采用焊接的方式连接。
第四方面，本公开实施例还提供一种电子设备，其包括上述的滤波器。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (21)

  1. 一种滤波电路，其包括第一谐振子电路、第二谐振子电路和阻抗匹配网络；所述第一谐振子电路和所述第二谐振子电路分别与所述阻抗匹配网络串联；
    所述第一谐振子电路被配置为容许高于第一频率的信号通过；第二谐振子电路被配置为容许低于第二频率的信号通过，所述第二频率大于所述第一频率；所述阻抗匹配网络容许在所述第一频率和所述第二频率之间的信号通过；其中，所述阻抗匹配网络包括第一电容、第二电容、第三电容、第四电容、第五电容和第一电感；
    所述第一电容的第一端和第四电容的第一端连接，所述第一电容的第二端与第一电感的第一端和所述第二电容的第一端连接；所述第二电容的第二端连接所述第三电容的第一端和所述第五电容的第二端；所述第四电容的第二端连接所述第五电容的第一端、所述第一电感的第二端以及参考信号端。
  2. 根据权利要求1所述的滤波电路，其中，所述第一谐振子电路与所述第一电容的第一端连接，所述第二谐振子电路与所述第三电容的第二端连接；或者，
    所述第二谐振子电路与所述第一电容的第一端连接，所述第一谐振子电路与所述第三电容的第二端连接。
  3. 根据权利要求1所述的滤波电路，其中，所述第一谐振子电路包括第六电容和第二电感；所述第六电容和所述第二电感并联。
  4. 根据权利要求3所述的滤波电路，其中，所述第六电容的值小于20pF；和/或，所述第二电感的值小于20nH。
  5. 根据权利要求1所述的滤波电路，其中，所述第二谐振子电路包括第七电容和第三电感；所述第七电容和第三电感并联。
  6. 根据权利要求6所述的滤波电路，其中，所述第七电容的值小于20pF；和/或，所述第三电感的值小于20nH。
  7. 根据权利要求1所述的滤波电路，其中，所述第一电容、所述第二 电容、所述第三电容、所述第四电容、所述第五电容的值均小于5pF；和/或，所述第一电感的值小于20nH。
  8. 根据权利要求1-7中任一项所述的滤波电路，其中，所述阻抗匹配网络还包括第八电容；所述第八电容的第一端连接所述第一谐振子电路，所述第三电容的第二端连接所述第二谐振子电路；所述第八电容的第二端连接所述第一电容的第一端和第四电容的第一端。
  9. 一种滤波器，包括权利要求1-8中任一项所述的滤波电路。
  10. 根据权利要求9所述的滤波器，其中，还包括第一衬底基板，所述滤波电路设置在所述第一衬底基板上；所述第一谐振子电路、第二谐振子电路和所述阻抗匹配网络均包括电容和电感，所述阻抗匹配网络中的电容包括所述第一电容、所述第二电容、所述第三电容、所述第四电容、所述第五电容；所述阻抗匹配网络中的电容包括所述第一电感；所述电感包括沿背离所述第一衬底基板方向依次设置的多个子结构，且在形成设置的层间绝缘层；相邻设置的所述子结构通过所述层间绝缘层的过孔连接，形成电感的线圈结构；所述电容包括沿背离所述第一衬底基板方向依次设置的第一极板和第二极板，以及设置在所述第一极板和所述第二极板之间的介质层。
  11. 根据权利要求10所述的滤波器，其中，所述第一极板和所述第二极板中的至少一者与所述子结构同层设置。
  12. 根据权利要求10所述的滤波器，其中，多个所述子结构中的任意两个在所述第一衬底基板上的正投影存在交叠。
  13. 根据权利要求10所述的滤波器，其中，还包括位于所述电感和所述电容背离所述第一衬底基板一侧的保护层。
  14. 根据权利要求13所述的滤波器，其中，还包括封装基板，所述保护层与所述滤波电路的端口对应的位置设置有开口，所述滤波电路的各端口通过所述开口与所述封装基板连接。
  15. 根据权利要求14所述的滤波器，其中，在所述开口中设置有连接结构，所述所述滤波电路的各端口分别通过对应的所述连接结构与所述封装 基板连接。
  16. 一种滤波器的制备方法，其包括：在第一衬底基板上形成滤波电路的步骤，其中，滤波电路包括权利要求1-8中任一项所述的滤波电路。
  17. 根据权利要求16所述的滤波器的制备方法，其中，所述第一谐振子电路、第二谐振子电路和所述阻抗匹配网络均包括电容和电感；形成所述电感的步骤包括：
    在第一衬底基板上依次形成子结构，并在子结构之间形成层间绝缘层，相邻设置的所述子结构通过所述层间绝缘层的过孔连接，形成电感的线圈结构；
    形成所述电容的步骤包括：
    沿背离所述第一衬底基板方向依次形成的第一极板和第二极板，以及设置在所述第一极板和所述第二极板之间的介质层。
  18. 根据权利要求17所述的滤波器的制备方法，其中，所述第一极板和所述第二极板中的至少一者与所述子结构在一次工艺中形成。
  19. 根据权利要求17所述的滤波器的制备方法，其中，多个所述子结构中的任意两个在所述第一衬底基板上的正投影存在交叠。
  20. 根据权利要求17所述的滤波器的制备方法，其中，还包括在所述电感和所述电容背离所述第一衬底基板一侧形成保护层。
  21. 一种电子设备，其包括权利要求9-15中任一项所述的滤波器。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101640519A (zh) * 2009-09-02 2010-02-03 南京理工大学 高阻带抑制多零点2.4千兆赫微形滤波器
US20110241798A1 (en) * 2010-03-31 2011-10-06 Electronics And Telecommunications Research Institute Resonator for communication system and filter using the same
CN102340288A (zh) * 2010-07-21 2012-02-01 中国科学院微电子研究所 一种具有阻抗匹配的射频集成带通滤波器
US20130106532A1 (en) * 2011-10-27 2013-05-02 Taiwan Semiconductor Manufacturing Co., Ltd. Band-pass filter using lc resonators
CN103413994A (zh) * 2013-08-01 2013-11-27 南京理工大学 X波段高抑制微型带通滤波器
CN114448375A (zh) * 2022-01-22 2022-05-06 北京邮电大学 一种多零点高选择性ltcc带通滤波器芯片

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101640519A (zh) * 2009-09-02 2010-02-03 南京理工大学 高阻带抑制多零点2.4千兆赫微形滤波器
US20110241798A1 (en) * 2010-03-31 2011-10-06 Electronics And Telecommunications Research Institute Resonator for communication system and filter using the same
CN102340288A (zh) * 2010-07-21 2012-02-01 中国科学院微电子研究所 一种具有阻抗匹配的射频集成带通滤波器
US20130106532A1 (en) * 2011-10-27 2013-05-02 Taiwan Semiconductor Manufacturing Co., Ltd. Band-pass filter using lc resonators
CN103413994A (zh) * 2013-08-01 2013-11-27 南京理工大学 X波段高抑制微型带通滤波器
CN114448375A (zh) * 2022-01-22 2022-05-06 北京邮电大学 一种多零点高选择性ltcc带通滤波器芯片

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