WO2024013831A1 - タスクスケジューラ装置、計算システム、タスクスケジューリング方法およびプログラム - Google Patents

タスクスケジューラ装置、計算システム、タスクスケジューリング方法およびプログラム Download PDF

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WO2024013831A1
WO2024013831A1 PCT/JP2022/027327 JP2022027327W WO2024013831A1 WO 2024013831 A1 WO2024013831 A1 WO 2024013831A1 JP 2022027327 W JP2022027327 W JP 2022027327W WO 2024013831 A1 WO2024013831 A1 WO 2024013831A1
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Prior art keywords
processor
task
cpu
state
core
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English (en)
French (fr)
Japanese (ja)
Inventor
圭 藤本
奨悟 斎藤
育生 大谷
廣 名取
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NTT Inc
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Nippon Telegraph and Telephone Corp
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Priority to JP2023567089A priority Critical patent/JPWO2024013831A1/ja
Priority to EP22951047.4A priority patent/EP4557052A1/en
Priority to CN202280098015.9A priority patent/CN119522407A/zh
Priority to PCT/JP2022/027327 priority patent/WO2024013831A1/ja
Priority to JP2023187211A priority patent/JP7616321B2/ja
Publication of WO2024013831A1 publication Critical patent/WO2024013831A1/ja
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5094—Allocation of resources, e.g. of the central processing unit [CPU] where the allocation takes into account power or heat criteria
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3243—Power saving in microcontroller unit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/329—Power saving characterised by the action undertaken by task scheduling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G06F9/4893—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues taking into account power or heat criteria
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to a task scheduler device, a calculation system, a task scheduling method, and a program.
  • FIG. 19 is a diagram illustrating an overview of the wireless access system.
  • the radio access system includes a user terminal (UE: User Equipment), an antenna (base station antenna) 20, a base station (BBU: Base Band Unit) 30, and a core network 40 (not shown).
  • UE User Equipment
  • base station antenna base station antenna
  • BBU Base Band Unit
  • the antenna 20 is an antenna and a transmitting/receiving unit that wirelessly communicates with the UE 10 (hereinafter, “antenna” refers to the antenna, the transmitting/receiving unit, and its power supply unit collectively). Transmission and reception data is connected to the base station 30 by, for example, a dedicated cable.
  • the base station 30 is a stationary wireless station located on land that communicates with the UE 10.
  • a base station (BBU: Broad Band Unit) 30 that performs wireless signal processing is dedicated hardware (dedicated device) that performs wireless signal processing.
  • the base station 30 is a vRAN (virtual radio access network) in which a general-purpose server performs radio signal processing in an LTE (Long Term Evolution) or 5G (five generation) signal processing intensive system.
  • LTE Long Term Evolution
  • 5G five generation
  • general-purpose servers that are inexpensive and available in large quantities can be used as the hardware of the base station 30.
  • the base station 30 includes hardware (HW) 31, a CPU (Central Processing Unit) 32 on the hardware, an OS etc. 33, and L1, L2, L3 protocol wireless signal processing applications 1-1, 1-2, 1. -3 (generally referred to as APL1), and a task scheduler device 34.
  • HW hardware
  • CPU Central Processing Unit
  • the core network 40 is EPC (Evolved Packet Core)/(in the following description, "/" represents “or”), 5GC (5G Core Network), or the like.
  • EPC Evolved Packet Core
  • 5GC 5G Core Network
  • Non-Patent Document 1 An example of a system that requires real-time performance is a base station (BBU) in RAN.
  • BBU base station
  • the task scheduler device 34 often performs calculations by assigning wireless signal processing tasks to the CPU core (Non-Patent Document 1).
  • FIG. 20 is a diagram illustrating an example of task management for wireless access processing at a base station. Components that are the same as those in FIG. 19 are given the same reference numerals.
  • the base station (BBU) 30 includes a task scheduler device 34.
  • the task scheduler device 34 performs task management, prioritization, and task allocation.
  • the task scheduler device 34 allocates the wireless signal processing task of APL1 to the task queue 37, and from the task queue 37 to the CPU cores (CPUcore #0, CPUcore #1, . . . ) 32.
  • LPI Low Power Idle hardware control
  • the CPU 32 has a function of controlling the idle state of the CPU 32 through hardware control, and is called LPI.
  • LPI is often called CPUidle or C-state, and hereinafter LPI will be explained as C-state.
  • the C-state attempts to save power by turning off the power to part of the circuit of the CPU 32 when the CPU load decreases (Non-Patent Document 2).
  • FIG. 21 is a diagram showing an example of C-state states in a table. Note that since the state definition differs depending on the CPU hardware, FIG. 21 is just a reference example. As shown in FIG. 21, the CPUidle state has grades C0 to C6, and as the time when the CPU 32 is not loaded increases, the state transitions to a deep sleep state. A deep sleep state consumes less CPU power, but on the other hand, it lengthens the time it takes to return, which may pose a problem in terms of low latency.
  • C-state differs depending on the CPU hardware. For example, there are variations such as a model without C4 or C5, and a model in which the state following C1 is C1E. As the state becomes deeper, the power saving effect increases, but the time required to return from the idle state also increases.
  • the depth to which the CPUidle state transitions is controlled by the CPU hardware and depends on the CPU product (in many cases, it cannot be controlled from software such as the kernel).
  • FIG. 22 is a table showing an example of the maximum values of the time it takes to transition to a state (RESIDENCY) and the time it takes to return (WAKE-UP LATENCY).
  • FIG. 22 shows C-state information in Intel Xeon CPU E5-26X0 v4 (registered trademark).
  • Linux kernel 4 (registered trademark) provides two types of governors to manage CPU idle state (C-state).
  • FIG. 23 is a diagram illustrating the CPU Governor idle type. As shown in Figure 23, ladder is used for systems with ticks, and menu is used for systems with ticks. For example, the menu used in the tickless system is a method that estimates the depth of the idle state suitable for the next idle period from the results of the most recent idle period. menu can be effective for workloads with regular idle times, but has limited effectiveness for workloads with irregular idle times.
  • FIG. 24 is a diagram illustrating an overview of menu logic.
  • menu records the most recent idle time. Then, as shown in the middle diagram of FIG. 24, the next idle time is estimated. For example, based on the idle time shown in the left diagram of FIG. 24, if the deviation is small, the average value T_avr is adopted as the next idle time.
  • menu estimates the appropriate idle state depth based on the estimation of the next idle time. For example, if the next idle time estimate T_avr is equal to the return time exit latency from the idle state (Cx), it is determined that the state is too deep and a transition is made to the idle state of Cx-1.
  • the CPUidle state has grades, and as the time when the CPU is not loaded increases, the state transitions to a deep sleep state.
  • a deep sleep state consumes less CPU power, but on the other hand, the time required for recovery becomes longer, which may pose a problem in terms of low latency.
  • FIG. 25 and 26 are C-state transition image diagrams of the CPU core used in calculations.
  • FIG. 25 shows a case where the no-task time is short
  • FIG. 26 shows a case where the no-task time is long.
  • the CPU core is in a shallow sleep state, and the delay time from task generation to recovery is short.
  • the CPU core is in a deep sleep state (CPUidle state: grade C6), and the delay time from task generation to recovery becomes longer.
  • the CPU drops to a deep idle state, it takes a long time to recover, which impairs real-time performance.
  • the base station (BBU) 30 shown in FIGS. 19 and 20 the base station (BBU) takes measures such as disabling the C-state or introducing settings that limit the transition of the idle state to a limited depth such as C1. In other words, tuning may be performed in favor of real-time performance at the expense of power saving.
  • BBUs base stations
  • the present invention was made in view of this background, and an object of the present invention is to perform calculations with low delay while achieving power saving.
  • a task scheduler device that allocates tasks to a group of cores of the processor in a computing system that reduces power consumption by gradually reducing the operating state of the processor according to the processing load, Based on the processor usage rate acquisition unit that acquires the usage rate of the processor, and the usage rate of the processor acquired by the processor usage rate acquisition unit, continue processing is performed for the core or core group of the processor that is used more than a predetermined frequency.
  • the present invention provides a task scheduler device comprising: a task allocation unit that allocates tasks in a specific manner.
  • calculations can be performed with low delay while achieving power savings.
  • FIG. 1 is a schematic configuration diagram of a calculation system according to an embodiment of the present invention. This is an example of a configuration in which a task scheduler device of a computing system according to an embodiment of the present invention is placed in a user space. 1 is a configuration example in which a task scheduler device of a calculation system according to an embodiment of the present invention is arranged in an OS.
  • FIG. 3 is a table showing logic for estimating the required number of active CPU core groups of the task scheduler device of the arithmetic system according to the embodiment of the present invention.
  • FIG. 3 is a diagram illustrating the task amount threshold determination and CPU usage rate threshold determination operations of the task scheduler device of the arithmetic system according to the embodiment of the present invention.
  • FIG. 2 is a diagram showing an image of threshold value determination according to the amount of task inflow of the task scheduler device of the calculation system according to the embodiment of the present invention.
  • FIG. 2 is a diagram illustrating an image of threshold value determination according to the CPU usage rate of the task scheduler device of the arithmetic system according to the embodiment of the present invention.
  • FIG. 2 is a diagram illustrating the C-state upper limit setting of the task scheduler device of the arithmetic system according to the embodiment of the present invention.
  • FIG. 6 is a diagram illustrating a case where there is no C-state upper limit setting/a case where there is a C-state upper limit setting in the arithmetic system according to the embodiment of the present invention.
  • FIG. 2 is a diagram illustrating pooling of CPU cores with high usability in the task scheduler device of the arithmetic system according to the embodiment of the present invention.
  • FIG. 2 is a diagram illustrating advance wake-up of the task scheduler device of the computing system according to the embodiment of the present invention.
  • FIG. 2 is a diagram illustrating advance wake-up of the task scheduler device of the computing system according to the embodiment of the present invention.
  • 3 is a flowchart showing task scheduling processing of the task scheduler device of the computing system according to the embodiment of the present invention.
  • 1 is a hardware configuration diagram showing an example of a computer that implements the functions of a task scheduler device of a calculation system according to an embodiment of the present invention.
  • 1 is a diagram showing an example in which a calculation system according to an embodiment of the present invention is applied to an interrupt model in a server virtualization environment with a general-purpose Linux kernel (registered trademark) and a VM configuration.
  • 1 is a diagram showing an example in which a calculation system according to an embodiment of the present invention is applied to an interrupt model in a container-configured server virtualization environment.
  • 1 is a diagram showing an example in which a calculation system according to an embodiment of the present invention is applied to an interrupt model in a server virtualization environment with a general-purpose Linux kernel (registered trademark) and a VM configuration.
  • 1 is a diagram showing an example in which a calculation system according to an embodiment of the present invention is applied to an interrupt model in a container-configured server virtualization environment.
  • FIG. 1 is a diagram illustrating an overview of a wireless access system.
  • FIG. 2 is a diagram illustrating an example of task management for wireless access processing in a base station.
  • FIG. 3 is a diagram illustrating an example of C-state states in a table form.
  • FIG. 3 is a table showing an example of the maximum values of the time required to transition to a state (RESIDENCY) and the time required to return to a state (WAKE-UP LATENCY).
  • FIG. 3 is a diagram illustrating CPU idle governor types.
  • FIG. 2 is a diagram illustrating an overview of the logic of menu.
  • FIG. 2 is an image diagram of C-state transition of a CPU core used for calculations.
  • FIG. 2 is an image diagram of C-state transition of a CPU core used for calculations.
  • FIG. 1 is a schematic configuration diagram of a calculation system according to an embodiment of the present invention. Components that are the same as those in FIG. 20 are given the same reference numerals.
  • This embodiment is an example in which a CPU is used as a calculation system.
  • the present invention is also applicable to processors such as GPUs (Graphic Processing Units), FPGAs (Field Programmable Gate Arrays), and ASICs (Application Specific Integrated Circuits), if they have an idle state function.
  • GPUs Graphic Processing Units
  • FPGAs Field Programmable Gate Arrays
  • ASICs Application Specific Integrated Circuits
  • the computing system 1000 includes hardware (HW) 31, CPU cores (CPUcore #0, CPUcore #1,...) 32 (processors) on the hardware 31, an OS 33, L1, L2 , L3 protocol wireless signal processing applications 1-1, 1-2, and 1-3 (collectively referred to as APL1), and a task scheduler device 100.
  • the computing system 1000 is a computing system that reduces power consumption by gradually reducing the operating state of a processor depending on the processing load.
  • the computing system 1000 includes a processor having a plurality of core groups, and a task scheduler device 100 that allocates tasks to the core groups of the processor.
  • the task scheduler device 100 includes a management section 110, a task management section 120, and a CPU idle state control section 130.
  • the management section 110 includes an operator setting section 111.
  • an operator sets parameters regarding C-state.
  • the administrator inputs the C-state upper limit setting in advance, taking into account the time lag from the input of the C-state upper limit setting to its reflection.
  • the task management unit 120 includes a task priority assigning unit 121, a task amount/period prediction unit 122 (processor usage rate acquisition unit), and a task CPU allocation unit 123 (task assignment unit).
  • the task priority assigning unit 121 assigns a task priority to the task sent from APL1 as necessary.
  • the task management unit 120 executes priority control of allocation to CPU cores according to this priority.
  • the most accurate representation of the CPU state is considered to be the "CPU usage rate per unit time of the CPU core in use.”
  • the "CPU usage rate per unit time of the CPU core in use” can be estimated approximately based on the amount of tasks. How busy the CPU is can be estimated by the amount of tasks, but it cannot be measured by the amount of tasks alone; it also depends on how many processes the CPU is weak at. Furthermore, when the processor is a GPU, FPGA, or ASIC other than a CPU, the processing that the processor is good at/not good at also changes. In this embodiment, the amount of tasks is used as a physical quantity related to "CPU usage rate per unit time of the CPU core in use.”
  • the task amount/cycle prediction unit 122 obtains the usage rate of the processor. Specifically, the task amount/cycle prediction unit 122 measures the amount of tasks per unit time and the CPU usage rate according to the judgment logic shown in FIG. 4, and determines whether it is necessary to increase or decrease the number of CPU cores used for calculations. Determine if there is. The task amount/cycle prediction unit 122 wakes up the newly used CPU core in advance. In many CPU products, when some processing is executed by the CPU core, the C-state returns to C0. For this reason, there is a method in which the corresponding CPU core executes processing such as small calculations and outputting character strings to standard output.
  • the task CPU allocation unit 123 Based on the processor usage rate acquired by the task amount/cycle prediction unit 122 (processor usage rate acquisition unit), the task CPU allocation unit 123 continuously assigns processor cores or core groups that are used more than a predetermined frequency. Assign tasks to. For example, the task CPU allocation unit 123 reduces the number of CPU cores used. As a method of reducing the number of CPU cores, a CPU core that will no longer be used is determined, and tasks are no longer assigned to that CPU core. The task CPU allocation unit 123 allocates the arrived tasks to CPU cores (assignment to CPU cores may be done by round robin of the CPU cores in use, or by determining the remaining number of task queues prepared for each CPU core).
  • tasks may be assigned to a CPU core with a small number of CPU cores), and tasks are scheduled in a task queue prepared for each CPU core. At this time, a task with a high priority may be preferentially assigned to a vacant CPU core according to the assigned priority. Further, the task queue for each CPU core may be rearranged according to priority.
  • the CPU idle state control unit 130 includes a CPU pre-wake-up unit 131 (pre-wake-up unit) and a C-state setting unit 132 (operation state setting unit).
  • the CPU pre-wake-up unit 131 performs pre-wake-up to restore the operating state of the processor to its original state when assigning a task to a newly used core or a core that is to be used again after not being used for a predetermined period of time. (See reference numeral c in FIG. 1).
  • the C-state setting unit 132 sets an upper limit for a core or core group of a processor that is used more than a predetermined frequency so that the operating state of the processor cannot be transitioned to a deeper state. Specifically, the C-state setting unit 132 sets the C-state upper limit setting for the newly used CPU core.
  • the upper limit state is determined by setting by the operator (see reference numeral b in FIG. 1). Note that if tasks are constantly flowing in and tasks can be continuously assigned, the active CPU core group will not transition to a deep C-state, so there may be no need to set an upper limit.
  • a C-state upper limit may be set for a newly used CPU core before assigning a task to return it to a shallow state.
  • the C-state setting unit 132 cancels the upper limit setting.
  • the C-state setting unit 132 sets a core or core group to which the task CPU allocation unit 123 (task allocation unit) has not allocated a task so that the operating state of the processor can be transitioned to a deeper state.
  • FIG. 2 and 3 are diagrams illustrating the arrangement of the task scheduler device 100 of FIG. 1.
  • - Arrangement of task scheduler device in user space FIG. 2 is a configuration example in which the task scheduler device 100 of FIG. 1 is arranged in user space.
  • the computing system 1000 shown in FIG. 2 the task scheduler device 100 is arranged in the user space 60.
  • the computing system 1000 executes a packet processing APL1 located in the User space 60.
  • the computing system 1000 executes packet processing APL1 on a server equipped with an OS.
  • the present invention can be applied to a case where the user space 60 has a thread, such as Intel Data Plane Development Kit (DPDK) (registered trademark).
  • DPDK Intel Data Plane Development Kit
  • FIG. 3 is a configuration example in which the task scheduler device 100 of FIG. 1 is arranged in the OS 50.
  • a task scheduler device 100 is arranged in the OS 50.
  • the computing system 1000 executes packet processing APL1 on a server equipped with an OS 50.
  • the present invention can be applied to cases where there is a thread inside the kernel, such as New API (NAPI) (registered trademark) (non-patent document 1) and KBP (kernel-based virtual machine).
  • NAPI New API
  • KBP kernel-based virtual machine
  • FIG. 4 is a table showing the logic for estimating the required number of active CPU core groups.
  • the estimation logic judgment includes ⁇ 1. Judgment based on task arrival pattern'' and ⁇ 2. Judgment based on CPU usage rate'', which are based on threshold value judgment, periodicity, and machine learning, respectively. .
  • the applicable tasks are different for each determination logic, so logics are selected and used properly, taking into consideration the applicability listed in the right column of the table in FIG. Further, a plurality of determination logics may be used together.
  • a task scheduler that allocates tasks to CPU cores takes into account the state of the C-state of the CPU cores when allocating tasks.
  • Feature ⁇ 1> Continuous task allocation Securing frequently used CPU core groups and continuously assigning tasks prevents transitions to deep C-states ( Figures 5 to 7). As shown in the broken line box a in Fig. 5, depending on the amount of tasks, a frequently used CPU core group (active CPU core group) is secured using the judgment logic shown in Fig. 4, and the CPU core group is continuously assigned to the corresponding CPU core group. Assign tasks to. This prevents transitions to deep C-states and reduces the delay in returning from C-states. Except for the active CPU core, it is possible to transition to a deep C-state, thereby saving power.
  • C-state upper limit setting As a countermeasure for cases where tasks cannot be continuously assigned, an upper limit of C-states that can be transitioned to is set for frequently used CPU core groups ( Figures 8 to 8). 10). As a countermeasure for cases where tasks cannot be continuously assigned to active CPU cores, by setting an upper limit on the C-state that can be transitioned to the active CPU core group, it is possible to prevent transitions to deep C-states and reduce the return delay. Reduce.
  • Feature ⁇ 3> Wake-up in advance By waking up in advance before assigning a task to a CPU core that has transitioned to a deep state, the time to return from a deep state is reduced ( Figures 11 and 12). The time required to return from a deep C-state is reduced by pre-waking up a newly used CPU core (a CPU core that has not been used for a long time) before assigning a task to it.
  • a newly used CPU core a CPU core that has not been used for a long time
  • FIG. 5 is a diagram illustrating the task amount threshold determination and CPU usage rate threshold determination operations of the task scheduler device 100.
  • the task management unit 120 performs a task amount threshold determination operation. As shown by the broken line arrow d in FIG. 5, the task priority assigning unit 121 assigns a priority to a task as necessary.
  • the task amount/cycle prediction unit 122 measures the amount of tasks per unit time and CPU usage rate, and determines whether it is necessary to increase or decrease the number of CPU cores used for calculations, according to the judgment logic shown in FIG. 4. .
  • FIG. 6 is a diagram showing an image of threshold value determination according to the amount of task inflow.
  • the task management unit 120 manages the CPU cores according to the task inflow amount shown in FIG.
  • the amount of task inflow per unit time: W_input is associated with the number of CPU cores to be used. For example, when W_input is "dd ⁇ ee", the number of CPU cores used is "4", and the active CPU core group (see broken line box a in FIG. 5) is "4".
  • the task CPU allocation unit 123 allocates the arrived task to a CPU core, and schedules the task in a task queue prepared for each CPU core. At this time, tasks with high priority are preferentially allocated to vacant CPU cores according to the assigned priority. Further, the task queue for each CPU core is rearranged according to priority.
  • the task management unit 120 designs the number of CPU cores required to calculate the task inflow amount per unit time according to the threshold determination table of FIG. 6. Further, when the amount of task inflow exceeds the threshold (W_input threshold) in the threshold determination table of FIG. 6, it is possible to determine whether it is necessary to increase the number of CPU cores to be used. In FIG. 6, the state is dd ⁇ W_input ⁇ ee, and four CPU cores are used. When the amount of task inflow becomes W_input ⁇ ee, increase the number of CPU cores from 4 to 5.
  • the task management unit 120 calculates the required number of CPU cores. If the processing time of a task is fixed (or has small fluctuations), by defining the maximum waiting time Tw allowed by the service, we can use queuing theory to calculate the amount of time required to satisfy the maximum waiting time. It becomes possible to calculate the number N of CPU cores. Equation (3) of the calculation formula below does not include the time to return from the C-state into consideration, but if the time to return from the C-state can be made as close to zero as possible with this embodiment, consideration becomes unnecessary. .
  • FIG. 7 is a diagram illustrating an image of threshold value determination according to CPU usage rate.
  • the vertical axis represents the average CPU usage rate of the CPU cores in use, and the horizontal axis represents time.
  • Two thresholds, Threshold_upper (see broken line e in FIG. 7) and Threshold_base (lower limit) (see broken line f in FIG. 7), are set for the average CPU usage rate of 100%.
  • the task management unit 120 (FIG. 5) increases the number of CPU cores to be used when the average CPU usage rate exceeds the upper limit. Furthermore, when the average CPU usage rate falls below the lower limit, the CPU cores used are reduced.
  • Threshold_upper upper limit
  • Threshold_base lower limit
  • FIG. 8 is a diagram illustrating the C-state upper limit setting of the task scheduler device 100.
  • the C-state setting unit 132 of the CPU idle state control unit 130 sets an upper limit of C-states that can be transitioned to for frequently used CPU core groups (see reference numeral b in FIG. 8).
  • an upper limit of the CPU idle state that can be transitioned to (for example, see C1 and C1E in FIG. 22) is determined, and Set it so that it cannot transition to state. As a result, it is possible to return from a shallow state when assigning a task, and the return delay time can be reduced.
  • the number of CPU cores to be used for setting/cancelling the upper limit of the CPU idle state can be determined by using the determination logic shown in FIG. 4.
  • the C-state setting unit 132 dynamically sets the upper limit of the CPU idle state using the determination logic shown in FIG.
  • FIG. 9 is a diagram illustrating an image of C-state upper limit setting.
  • the upper diagram in FIG. 9 shows a case where there is no C-state upper limit setting
  • the lower diagram in FIG. 9 shows a case where there is a C-state upper limit setting.
  • the CPU drops to the idle state (grade C2) and the delay time until returning to C0 becomes longer.
  • the C-state upper limit for frequently used CPU core groups see symbol g in the lower diagram of Figure 9
  • FIG. 10 is a diagram illustrating pooling of CPU cores with high usability in the task scheduler device 100.
  • a CPU core group (broken line box h in FIG. 10) may be prepared that is set so that it will only fall into a shallow idle state.
  • the CPU cores (CPUcore #4, CPUcore #5) 32 shown in FIG. 10 are pooled as a CPU core group that can only transition up to C1.
  • the group of CPU cores that are likely to be used (h in the dashed line box in Figure 10) ) is set so that it can only transition to a shallow idle state (for example, up to C1). Then, active standby CPU cores are pooled and prepared so that they can be used immediately when needed. In this way, if future use is expected, prepare a group of CPU cores that are set to only fall into a shallow idle state (for example, pool a group of CPU cores that can only transition to C1). Take.
  • the C-state upper limit setting has been explained above.
  • FIG. 11 is a diagram illustrating how the task scheduler device 100 wakes up in advance.
  • the CPU pre-wake-up unit 131 pre-wakes up a CPU core when using a CPU core that has fallen into a deep CPU idle state (C-state) (see reference numeral c in FIG. 11).
  • FIG. 12 is a diagram illustrating how the task scheduler device 100 wakes up in advance.
  • the upper diagram in FIG. 12 shows a case using the existing technology
  • the lower diagram in FIG. 12 shows a case in which the task scheduler device 100 wakes up in advance.
  • the upper diagram of Figure 12 in the case of the existing technology (when there is no advance wake-up), there is a large delay from task assignment (symbol i in the upper diagram of Figure 12) to the start of the calculation (in the upper diagram of Figure 12). code j).
  • the delay from task assignment to the start of calculation is low (reference symbol k in the lower diagram of FIG. 12) due to the early wake-up (sign c in the lower diagram of FIG. ).
  • FIG. 13 is a flowchart showing the task scheduling process of the task scheduler device 100.
  • the APL 1 (FIG. 1) registers the task in the task management unit 120 (FIG. 1).
  • step S12 the task priority assigning unit 121 (FIG. 1) assigns a priority to the task as necessary.
  • the task CPU allocation unit 123 (FIG. 1) executes priority control of allocation to CPU cores according to this priority.
  • step S13 the task amount/period prediction unit 122 (FIG. 1) measures the amount of tasks per unit time and the CPU usage rate, and increases/decreases the number of CPU cores used for calculations, according to the judgment logic shown in FIG. It is determined whether it is necessary (branches after the determination are steps S14 and S15 below).
  • step S14 If it is necessary to reduce the number of CPU cores in step S14 (S14: Yes), the process proceeds to step S17, and if there is no need to reduce the number of CPU cores (S14: No), the process proceeds to step S15.
  • step S15: Yes If it is necessary to increase the number of CPU cores in step S15 (S15: Yes), proceed to step S19, and if there is no need to increase the number of CPU cores (S15: No), proceed to step S16.
  • step S16 the task CPU allocation unit 123 (FIG. 1) allocates the arrived task to the CPU core, schedules the task in a task queue prepared for each CPU core, and ends the processing of this flow.
  • the allocation to the CPU cores may be performed by round robin among the CPU cores in use, or may be allocated to a CPU core with a small number of remaining tasks in the task queue prepared for each CPU core.
  • the task CPU allocation unit 123 may preferentially allocate a task with a high priority to an empty CPU core according to the assigned priority, or may assign a task queue for each CPU core. , may be rearranged according to priority.
  • the task CPU allocation unit 123 reduces the number of CPU cores to be used in step S17. For example, as a method of reducing the number of CPU cores, a CPU core that will no longer be used is determined, and tasks are no longer assigned to that CPU core.
  • step S18 if the C-state upper limit setting is set for the CPU core that is determined not to be used, the C-state setting unit 132 (FIG. 1) cancels the C-state upper limit setting and restarts this flow. Finish the process.
  • the task amount/period prediction unit 122 (FIG. 1) performs pre-wake-up on the newly used CPU core in step S19.
  • the reason for pre-waking up a newly used CPU core is as follows. That is, in many CPU products, if some processing is executed in the CPU core, the C-state returns to C0. Therefore, by executing minor processing such as small calculations or outputting a character string to the standard output in the corresponding CPU core, the transition of the corresponding CPU core to a deep C-state is suppressed.
  • step S20 the C-state setting unit 132 sets the C-state upper limit setting for the newly used CPU core, and ends the processing of this flow.
  • the upper limit state is determined by setting it in advance by the operator.
  • FIG. 14 is a hardware configuration diagram showing an example of a computer 900 that implements the functions of the task scheduler devices 100 and 100A (FIGS. 1 and 10).
  • the computer 900 has a CPU 901, a ROM 902, a RAM 903, an HDD 904, a communication interface (I/F) 906, an input/output interface (I/F) 905, and a media interface (I/F) 907.
  • the CPU 901 operates based on a program stored in the ROM 902 or HDD 904, and controls each part of the task scheduler device 100, 100A (FIGS. 1 and 10).
  • the ROM 902 stores a boot program executed by the CPU 901 when the computer 900 is started, programs depending on the hardware of the computer 900, and the like.
  • the CPU 901 controls an input device 910 such as a mouse and a keyboard, and an output device 911 such as a display via an input/output I/F 905.
  • the CPU 901 acquires data from the input device 910 via the input/output I/F 905 and outputs the generated data to the output device 911.
  • a GPU Graphics Processing Unit
  • a GPU Graphics Processing Unit
  • the HDD 904 stores programs executed by the CPU 901 and data used by the programs.
  • the communication I/F 906 receives data from other devices via a communication network (for example, NW (Network) 920) and outputs it to the CPU 901, and also sends data generated by the CPU 901 to other devices via the communication network. Send to device.
  • NW Network
  • the media I/F 907 reads the program or data stored in the recording medium 912 and outputs it to the CPU 901 via the RAM 903.
  • the CPU 901 loads a program related to target processing from the recording medium 912 onto the RAM 903 via the media I/F 907, and executes the loaded program.
  • the recording medium 912 is an optical recording medium such as a DVD (Digital Versatile Disc) or a PD (Phase change rewritable disk), a magneto-optical recording medium such as an MO (Magneto Optical disk), a magnetic recording medium, a conductive memory tape medium, a semiconductor memory, or the like. It is.
  • the CPU 901 of the computer 900 executes a program loaded on the RAM 903. This realizes the functions of the task scheduler devices 100, 100A. Furthermore, data in the RAM 903 is stored in the HDD 904 .
  • the CPU 901 reads a program related to target processing from the recording medium 912 and executes it. In addition, the CPU 901 may read a program related to target processing from another device via a communication network (NW 920).
  • [Application example] (format in which the task scheduler device is placed in User space 60)
  • the present invention can be applied to a configuration example in which a task scheduler device 100 is arranged in a user space 60.
  • the OS is not limited.
  • it is not limited to being under a server virtualization environment. Therefore, the arithmetic system can be applied to each of the configurations shown in FIGS. 15 and 16.
  • VM configuration ⁇ Example of application to VM configuration>
  • NFV Network Functions Virtualization
  • SFC Service Function Chaining
  • a hypervisor environment composed of Linux (registered trademark) and KVM (kernel-based virtual machine) is known as a technology for configuring virtual machines.
  • a Host OS with a built-in KVM module OS installed on a physical server is called a Host OS
  • a hypervisor in a memory area called kernel space that is different from user space.
  • a virtual machine operates in the user space, and a Guest OS (the OS installed on the virtual machine is called a Guest OS) operates within the virtual machine.
  • a virtual machine running a Guest OS is different from a physical server running a Host OS; all HW (hardware) including network devices (typified by Ethernet card devices, etc.) are transferred from the HW to the Guest OS.
  • HW hardware
  • network devices typified by Ethernet card devices, etc.
  • FIG. 15 is a diagram showing an example in which the arithmetic system 1000A is applied to an interrupt model in a server virtualization environment with a general-purpose Linux kernel (registered trademark) and a VM configuration. Components that are the same as those in FIG. 1 are given the same reference numerals.
  • the computing system 1000A includes a Host OS 80 in which a virtual machine and an external process formed outside the virtual machine can operate, and the Host OS 80 includes a Kernel 81 and a Driver 82. Further, the computing system 1000A includes a CPU 71 of the HW 70 connected to the Host OS 80 and a KVM module 91 built into the hypervisor (HV) 90.
  • HV hypervisor
  • the computing system 1000A includes a Guest OS 95 that operates within a virtual machine, and the Guest OS 95 includes a Kernel 96 and a Driver 97.
  • the computing system 1000A includes a task scheduler device 100 connected to the Guest OS 95 and placed in the User space 60.
  • FIG. 16 is a diagram showing an example in which the calculation system 1000B is applied to an interrupt model in a container-configured server virtualization environment. Components that are the same as those in FIGS. 1 and 15 are designated by the same reference numerals.
  • the computing system 1000B has a container configuration in which the Guest OS 95 in FIG. 15 is replaced with a Container 98.
  • Container 98 has a vNIC (virtual NIC).
  • the present invention can be applied to a configuration example in which a task scheduler device 100 is arranged within an OS 50.
  • the OS is not limited.
  • it is not limited to being under a server virtualization environment. Therefore, the arithmetic system can be applied to each of the configurations shown in FIGS. 17 and 18.
  • FIG. 17 is a diagram showing an example in which the calculation system 1000C is applied to an interrupt model in a server virtualization environment with a general-purpose Linux kernel (registered trademark) and a VM configuration. Components that are the same as those in FIGS. 1 and 15 are designated by the same reference numerals.
  • a task scheduler device 100 is arranged in Kernel 81 of Host OS 80, and a task scheduler device 100 is arranged in Kernel 96 of Guest OS 95.
  • FIG. 18 is a diagram showing an example in which the calculation system 1000D is applied to an interrupt model in a server virtualization environment with a container configuration. Components that are the same as those in FIGS. 1 and 16 are given the same reference numerals.
  • a task scheduler device 100 is arranged in the Kernel 81 of the Host OS 80.
  • the present invention can be applied to a system with a non-virtualized configuration such as a bare metal configuration.
  • calculations can be performed with low latency while achieving power savings.
  • processors other than CPU ⁇ Application to processors other than CPU>
  • the present invention is similarly applicable to processors other than CPUs, such as GPUs, FPGAs, and ASICs, if they have an idle state function.
  • the present invention can also apply the advance wake-up according to the embodiment to a mechanism for restoring the frequency to the original level before task assignment when the processor operating frequency is low.
  • the present invention can also be applied to functions other than the CPU, such as memory and storage (eg, HDD, SSD). Furthermore, when a component of an externally connected peripheral device or the like is in a power saving mode, it can be applied to wake up in advance and prepare it before use.
  • functions other than the CPU such as memory and storage (eg, HDD, SSD).
  • a task scheduler device that allocates tasks to a group of cores of a processor is used.
  • 100, 100A which includes a processor usage rate acquisition unit (task amount/cycle prediction unit 122) that acquires the processor usage rate, and a processor usage rate acquisition unit that acquires the processor usage rate acquired by the processor usage rate acquisition unit.
  • a task allocation unit (task CPU allocation unit 123) that continuously allocates tasks to a processor core or core group used more than a predetermined frequency is provided.
  • a frequently used CPU core group (active CPU core group) is secured using the judgment logic shown in FIG.
  • CPU cores other than the active CPU core can transition to a deep C-state (for example, C6), it is possible to save power.
  • calculations can be performed with low delay while achieving power savings.
  • an operating state setting is performed to set an upper limit so that the operating state of the processor cannot be transitioned to a deeper state. (C-state setting unit 132).
  • the operating state setting unit selects a core or core group to which the task allocation unit (task CPU allocation unit 123) has not allocated a task. For example, the operating state of the processor is set so that it can transition to a deeper state.
  • the computer when assigning a task to a newly used core or a core to be used again after not using it for a predetermined period, the operating state of the processor is
  • the computer includes a pre-wake-up unit (CPU pre-wake-up unit 131) that performs pre-wake-up to return to the state.
  • the basic idea is that if it takes a long time from when a task is assigned until the process is finished and the system returns, the system should wake up in advance for the time it takes to return and prepare the CPU to be ready for use. It is something to keep. By doing this, the time required to return from a deep state can be reduced by waking up in advance before assigning a task to a CPU core that has transitioned to a deep state. It is assumed that a core to be newly used or a core to be used again after not being used for a predetermined period is in a deep C-state. By waking up before assigning tasks, you can reduce the time it takes to return from a deep C-state.
  • the computing system 1000 reduces power consumption by gradually reducing the operating state of a processor according to processing load, in which a processor (CPU) has a plurality of core groups (CPU cores (CPUcore #0, CPUcore #1, ...) 32), and includes task scheduler devices 100, 100A (Fig. 1, Fig. 10) that allocate tasks to core groups of processors. , a processor usage rate acquisition unit (task amount/period prediction unit 122) that acquires the processor usage rate, and a processor usage rate acquisition unit that calculates processor cores that are used more than a predetermined frequency based on the processor usage rate acquired by the processor usage rate acquisition unit.
  • a task allocation unit (task CPU allocation unit 123) that continuously allocates tasks is provided.
  • the calculation systems 1000 to 1000D are technologies that are extended not only to packet arrival/processing tasks but also to general tasks such as calculating ⁇ .
  • By continuously assigning tasks to frequently used CPU core groups (active CPU core groups) according to the processor usage rate transitions to deep C-states are prevented and return from C-states is delayed. can be reduced.
  • CPU cores other than the active CPU core can transition to a deep C-state, it is possible to save power. That is, pre-wake-up can maintain a deep LPI (C-state) for as long as possible while reducing the delay in returning from the C-state, thereby achieving both low latency and power saving.
  • C-state deep LPI
  • the above processor can be similarly applied to processors other than CPUs, such as GPUs, FPGAs, and ASICs, if they have an idle state function.
  • each of the above-mentioned configurations, functions, processing units, processing means, etc. may be partially or entirely realized by hardware, for example, by designing an integrated circuit.
  • each of the above-mentioned configurations, functions, etc. may be realized by software for a processor to interpret and execute a program for realizing each function.
  • Information such as programs, tables, files, etc. that realize each function is stored in memory, storage devices such as hard disks, SSDs (Solid State Drives), IC (Integrated Circuit) cards, SD (Secure Digital) cards, optical disks, etc. It can be held on a recording medium.
  • Hardware (HW) 32 CPU core (processor) 1, 1-1, 1-2, 1-3 Application (APL) 100, 100A Task scheduler device 110 Management unit 111 Setting unit for operator 120 Task management unit 121 Task priority assignment unit 122 Task amount/cycle prediction unit (processor usage rate acquisition unit) 123 Task CPU allocation unit (task allocation unit) 120 Task management unit 130 CPU idle state control unit 131 CPU pre-wake-up unit (pre-wake-up unit) 132 C-state setting section (operating state setting section) 1000, 1000A, 1000B, 1000C, 1000D Arithmetic system (calculation system) CPUcore #0, CPUcore #1,... CPU core

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