WO2024011508A1 - 驱动芯片、发光基板及其测试方法、显示装置 - Google Patents

驱动芯片、发光基板及其测试方法、显示装置 Download PDF

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Publication number
WO2024011508A1
WO2024011508A1 PCT/CN2022/105751 CN2022105751W WO2024011508A1 WO 2024011508 A1 WO2024011508 A1 WO 2024011508A1 CN 2022105751 W CN2022105751 W CN 2022105751W WO 2024011508 A1 WO2024011508 A1 WO 2024011508A1
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WIPO (PCT)
Prior art keywords
pin
address
driver chip
driver
signal
Prior art date
Application number
PCT/CN2022/105751
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English (en)
French (fr)
Inventor
郝卫
张峻玮
张笑语
时凌云
Original Assignee
京东方科技集团股份有限公司
京东方晶芯科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 京东方科技集团股份有限公司, 京东方晶芯科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/105751 priority Critical patent/WO2024011508A1/zh
Priority to CN202280002185.2A priority patent/CN117716413A/zh
Publication of WO2024011508A1 publication Critical patent/WO2024011508A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/50—Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDs; responsive to LED life; Protective circuits

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a driving chip, a light-emitting substrate and a testing method thereof, and a display device.
  • the display device can be used to display pictures.
  • display devices With the rapid development of display technology, display devices have gradually become ubiquitous in people's lives.
  • a driver chip is provided.
  • the driver chip includes a logic control module, at least one output pin and a first function pin. At least one output pin is electrically connected to the logic control module.
  • the first function pin is electrically connected to the logic control module.
  • the first functional pin can receive a test signal.
  • the logic control module is configured to generate a test current flowing through any of the output pins according to the test signal.
  • the test signal includes a switching signal.
  • the switch signal is used to control the logic control module to generate a test current flowing through any of the output pins respectively.
  • the driver chip also includes address pins and relay pins.
  • the address pin is electrically connected to the logic control module.
  • the address pin can receive driving data; the driving data includes address verification information and a plurality of driving information corresponding to a plurality of cascaded driving chips.
  • the logic control module is configured to: configure a driver information corresponding to the current driver chip according to the address verification information; and update the address verification information to generate an updated address verification information.
  • the relay pin is electrically connected to the logic control module. The relay pin can output the driving data including updated address verification information.
  • the test signal includes test data and universal address information, and the universal address information can match the initialization address information of any one of the driver chips.
  • the logic control module is configured to generate a test current flowing through any of the output pins according to the test data.
  • the driver chip also includes address pins and relay pins.
  • the address pin is electrically connected to the logic control module.
  • the address pin is capable of receiving address signals.
  • the logic control module is configured to configure the address information of the driver chip according to the address signal and generate a relay signal.
  • the relay pin is electrically connected to the logic control module.
  • the relay pin can output the relay signal.
  • the first functional pin is also capable of receiving driving data.
  • the driving data includes a plurality of address verification information and a plurality of driving information corresponding to the plurality of address verification information.
  • the logic control module is configured to: when the address verification information matches the address information of the driver chip, receive the corresponding driver information according to the address verification information, and generate the corresponding driver information based on the received driver information.
  • the drive current corresponding to at least one output pin.
  • the driver chip further includes a second functional pin and a first connection line.
  • the second functional pin is connected to the first functional pin through the first connecting line.
  • the second function pin can output a test signal.
  • the driver chip has a first edge and a second edge that are parallel to each other. One of the first functional pin and the second functional pin is close to the first edge, and the other is close to the second edge.
  • the driver chip further has a third edge located between a first end of the first edge and a first end of the second edge.
  • the driver chip includes an address pin and a relay pin: one of the address pin and the relay pin is close to the first edge, and the other is close to the second edge. The address pin and the relay pin are closer to the third edge than the first function pin and the second function pin.
  • the driver chip further includes at least one ground pin. At least one ground pin is electrically connected to the logic control module. The ground pin can receive a ground signal. The ground pin is located between the address pin and the relay pin.
  • the driver chip further includes a first power pin.
  • the first power pin is electrically connected to the logic control module.
  • the first power pin can receive a power signal.
  • a first power pin is close to the first edge or the second edge.
  • the driver chip further includes a second power pin and a second connection line.
  • the second power pin is connected to the first power pin through the second connection line.
  • the second power pin can output the power signal.
  • one of the first power pin and the second power pin is close to the first edge, and the other is close to the second edge.
  • the first power pin and the second power pin are farther away from the third edge than the address pin and the relay pin.
  • the driver chip further has a fourth edge located between a second end of the first edge and a second end of the second edge.
  • the number of the output pins is multiple, the multiple output pins are close to the fourth edge, and the multiple output pins are arranged along the extending direction of the fourth edge.
  • the light-emitting substrate includes a plurality of cascaded driver chips and a plurality of device groups.
  • the driver chip is the driver chip described in any of the above embodiments.
  • a first end of a device group is electrically connected to at least one output pin of a driver chip.
  • the relay pin of the driver chip located at the upper level The pin is electrically connected to the address pin of the driver chip located at the next level.
  • the light-emitting substrate also includes a conductive layer.
  • the conductive layer includes a second voltage line, an address signal line, a first voltage line, a test signal line and a ground line.
  • the second voltage line is electrically connected to the second end of each of the device groups.
  • the address signal line is electrically connected to the address pin of the first driver chip.
  • the first voltage line is electrically connected to the first power pin of the first driver chip.
  • the test signal line is electrically connected to the first functional pin of the first driver chip.
  • the ground wire is electrically connected to at least one ground pin of each driver chip. There is no overlap between the second voltage line, the address signal line, the first voltage line, the test signal line and the ground line.
  • the driver chip when the driver chip also includes a second functional pin: the second functional pin is respectively connected to the first functional pin of the driver chip of the current level, and the first functional pin of the next level.
  • the first functional pin of the driver chip is electrically connected.
  • the driver chip also includes a second power pin: the second power pin is connected to the first power pin of the driver chip of the current stage and the first power pin of the next stage.
  • the first power pin of the driver chip is electrically connected.
  • the address signal line is configured to transmit an address signal
  • the test signal line is configured to transmit a test signal and driving data in a time-sharing manner; or, the address signal line is configured to transmit driving data, so The test signal line is configured to transmit the test signal.
  • a method for testing a luminescent substrate is provided.
  • the light-emitting substrate is the light-emitting substrate described in any of the above embodiments.
  • the test method includes: inputting a test signal to the first function pin of each driver chip; so that each driver chip generates a test current flowing through any output pin according to the test signal. Determine the lighting status of the device group electrically connected to any of the driver chips; if it emits light normally, it is determined that the device group is connected to the corresponding driver chip normally; if it does not emit light or lights abnormally, it is determined that the device group is connected to the corresponding driver chip. The chip connection is abnormal.
  • inputting a test signal to the first functional pin of each driver chip includes: inputting a switch signal to the first functional pin of each driver chip, the switch signal being used to control the logic control module to generate The test current flowing through any output pin respectively.
  • the test method further includes: inputting drive data to an address pin of a first drive chip among multiple cascaded drive chips, where the drive data includes address verification information and information related to the multiple cascaded drive chips.
  • Multiple driver information corresponding to the driver chip the driver chip configures a driver information corresponding to the current driver chip according to the address verification information. And based on the driving information, the driving current corresponding to the device group connected to the driving chip is generated. And, the driver chip updates the address verification information, generates driver data including the updated address verification information, and outputs the driver data including the updated address verification information to the next-level driver chip. Determine whether there is a device group that does not emit light among the device groups connected to multiple cascaded driver chips. If so, according to the cascade sequence, it is determined that there is an abnormality in the driver chip connected to the first device group that does not emit light. If not, it is determined that there is no abnormality in the multiple cascaded driver chips.
  • inputting a test signal to the first functional pin of each driving chip includes: inputting a test signal including test data and first general address information to the first functional pin of each driving chip.
  • the first universal address information can match the initialization address information of any one of the driver chips.
  • the testing method further includes: inputting an address signal to an address pin of a first driver chip among the plurality of cascaded driver chips.
  • the driver chip configures the address information of the driver chip according to the address signal and generates a relay signal.
  • the relay signal is the same as the address signal.
  • the test method further includes: inputting a test signal including test data and second general address information to the first function pin of each driver chip.
  • the second universal address information can match the updated address information of any one of the driver chips. Determine whether there is a device group that does not emit light among the device groups connected to multiple cascaded driver chips. If yes, then according to the cascade sequence, it is determined that the driver chip connected to the first device group that does not emit light has an abnormality; if not, it is determined that there is no abnormality in the multiple cascaded driver chips.
  • the test method further includes: inputting an address signal to an address pin of a first driver chip among multiple cascaded driver chips, and the driver chip configuring the address information of the driver chip according to the address signal, and generate relay signals.
  • the logic control module receives the corresponding driver information based on the address verification information, and generates the corresponding driver information based on the received driver information.
  • the drive current corresponding to at least one output pin.
  • a display device in another aspect, includes: the light-emitting substrate as described in any of the above embodiments.
  • Figure 1 is a structural diagram of a display device provided by some embodiments of the present disclosure.
  • Figure 2 is a structural diagram of a light-emitting substrate provided by some embodiments of the present disclosure.
  • Figure 3 is a structural diagram of a driver chip provided by some embodiments of the present disclosure.
  • Figure 4 is a structural diagram of a driver chip in some implementations.
  • Figure 5 is a schematic diagram of two driver chips connected to each other according to some embodiments of the present disclosure.
  • Figure 6 is a schematic diagram of a data format of driving data provided by some embodiments of the present disclosure.
  • Figure 7 is a schematic diagram of another data format of driving data provided by some embodiments of the present disclosure.
  • Figure 8 is a structural diagram of a driver chip provided by some further embodiments of the present disclosure.
  • Figure 9 is a structural diagram of a driver chip provided by some embodiments of the present disclosure.
  • Figure 10 is a structural diagram of a driver chip provided by some embodiments of the present disclosure.
  • Figure 11 is a structural diagram of a light-emitting substrate provided by some further embodiments of the present disclosure.
  • Figure 12 is a partial enlarged view of the R position in Figure 11;
  • Figure 13 is a circuit block diagram of a light-emitting substrate provided by some embodiments of the present disclosure.
  • Figure 14 is a circuit block diagram of the driver chip in Figure 13;
  • Figure 15 is another circuit block diagram of the driver chip in Figure 13;
  • Figure 16 is a flow chart of a method for detecting a light-emitting substrate provided by some embodiments of the present disclosure
  • FIG. 17 is a flow chart of a method for detecting a light-emitting substrate according to further embodiments of the present disclosure.
  • Figure 18 is a flow chart of a method for detecting a light-emitting substrate according to yet another embodiment of the present disclosure.
  • Figure 19 is a flow chart of a method for detecting a light-emitting substrate according to yet another embodiment of the present disclosure.
  • Figure 20 is a flow chart of a method for detecting a light-emitting substrate according to yet another embodiment of the present disclosure
  • FIG. 21 is a flow chart of a method for detecting a light-emitting substrate according to yet another embodiment of the present disclosure.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • connection and “connect” and their derivatives may be used.
  • some embodiments may be described using the term “connected” to indicate that two or more components are in direct physical or electrical contact with each other.
  • parallel and perpendicular include the stated situation and situations that are approximate to the stated situation, and the range of the approximate situation is within an acceptable deviation range, where the acceptable deviation Ranges are as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (ie, the limitations of the measurement system).
  • the acceptable deviation Ranges are as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (ie, the limitations of the measurement system).
  • parallel includes absolutely parallel and approximately parallel, and the acceptable deviation range of approximately parallel may be, for example, a deviation within 5°
  • perpendicular includes absolutely vertical and approximately vertical, and the acceptable deviation range of approximately vertical may also be, for example, Deviation within 5°.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • FIG. 1 is a structural diagram of a display device provided by some embodiments of the present disclosure.
  • some embodiments of the present disclosure provide a display device 300 .
  • the display device 300 includes a light-emitting substrate 200 .
  • the display device 300 may be a liquid crystal display (Liquid Crystal Display, LCD for short), a Mini LED (Mini Light-Emitting Diode, Mini LED for short) display device, and a Micro LED (Micro Light-Emitting Diode, Micro LED for short). display device.
  • LCD Liquid Crystal Display
  • Mini LED Mini Light-Emitting Diode, Mini LED for short
  • Micro LED Micro Light-Emitting Diode, Micro LED for short
  • the display device 300 includes a cover glass, a liquid crystal display panel, and a backlight assembly.
  • Backlight components are used to provide light sources for LCD panels.
  • the backlight assembly includes a light-emitting substrate 200.
  • the light-emitting substrate 200 provides light for the liquid crystal display panel, so that the liquid crystal display panel can display images.
  • the backlight module in the display device 300 may further include an optical film, and the optical film is located on a side of the light-emitting substrate 200 close to the liquid crystal display panel.
  • Optical films can include reflective sheets, diffusion plates, brightness-enhancing films (prism sheets), diffusion sheets, etc., which can be used to improve the brightness and uniformity of light.
  • the display device 300 When the display device 300 is a Mini LED display device or a Micro LED display device, in some embodiments, the display device 300 includes a light-emitting substrate 200, and the light-emitting substrate 200 can realize picture display. In some examples, the display device 300 may further include an anti-reflective film layer and a protective cover, and the anti-reflective film layer is located between the light-emitting substrate 200 and the protective cover.
  • the anti-reflection film layer includes a polarizer, and the polarizer may be a circular polarizer.
  • the polarizer can reduce external light emission and prevent the light-emitting substrate 200 from reflecting ambient light to produce a dazzling effect.
  • the above-mentioned display device 300 may be any display device that displays images, whether moving (eg, video) or fixed (eg, still images), and whether text or text. More specifically, it is contemplated that the display devices of the embodiments may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants, etc.
  • PDA handheld or portable computer
  • GPS receiver/navigator camera
  • MP4 video player video player
  • video camera game console
  • watch clock
  • calculator TV monitor
  • flat panel display computer monitor
  • automotive monitor e.g., odometer display, etc.
  • navigator cockpit controller and/or display
  • display of camera view e.g., display of rear view camera in vehicle
  • electronic photo electronic billboard or sign
  • projector construction Structure
  • packaging and aesthetic structure for example, for the display of an image of a piece of jewelry
  • Figure 2 is a structural diagram of a light-emitting substrate provided by some embodiments of the present disclosure.
  • the light-emitting substrate 200 includes a plurality of cascaded driving chips 100 and a plurality of device groups O respectively connected to each driving chip.
  • one device group O includes at least one light emitting unit E.
  • a light-emitting unit E may include at least one light-emitting element.
  • one light-emitting unit E may include only one light-emitting element.
  • one light-emitting unit E may include two or more light-emitting elements that are electrically connected to each other.
  • the two or more light-emitting elements can be connected in series, in parallel, or in a mixed series-parallel connection.
  • the light-emitting element can be a light-emitting diode (Light-Emitting Diode, referred to as LED), a micro-light-emitting diode (Micro Light-Emitting Diode, referred to as Micro LED), a mini-light-emitting diode (Mini Light-Emitting Diode, referred to as Mini LED), Organic Electroluminescent Diode (Organic Light-Emitting Diode, OLED for short) Quantum Dot Light-Emitting Diode (QLED for short), etc.
  • the light-emitting unit E can emit light under the driving of the driver chip 100, and can be applied to equipment such as display devices and lighting devices.
  • the light-emitting substrate 200 is a backlight source of the display device 300 and is used to provide a light source for the liquid crystal display device.
  • Each device group O can be controlled by the driver chip 100, and each light-emitting unit E in the device group O can be independently controlled; in this way, the display device can implement local dimming (Local Dimming) and achieve high dynamic range images (High- Dynamic Range (HDR) effect to improve the display quality of the display device 300.
  • the number and electrical connection methods of the light-emitting units E are the same.
  • the number and electrical connection methods of light-emitting elements are the same.
  • the uniform distribution of the light-emitting units E on the light-emitting substrate can be ensured, which is beneficial to improving the uniformity of the light emitting of the light-emitting substrate and reducing the difficulty of debugging the backlight module.
  • the light emitting unit E (such as Micro LED, Mini LED, etc.) can emit light to directly display the pattern.
  • the light-emitting units E may be light-emitting elements capable of emitting light of the same color, for example, they may all be blue LEDs, red LEDs, green LEDs or yellow LEDs.
  • the display device can be a monochrome display device, which can be a display device such as an instrument dial, a signal indication screen, etc.
  • the light-emitting unit E may include a plurality of light-emitting elements of different colors, for example, it may include at least two of red LED, green LED, blue LED, yellow LED, etc., and the light-emitting units E of different colors may be independently configured. control. In this way, the display device can perform color display through light mixing.
  • a plurality of device groups O on the light-emitting substrate 200 are distributed in an array at equal intervals in the row direction and the column direction.
  • each device group O may be arranged into multiple device group rows, each device group row is equally spaced along the column direction, and each device group row includes a plurality of light emitting units E that are equally spaced along the row direction.
  • Each light-emitting unit E may also be arranged into multiple element columns, each element column is equally spaced along the row direction, and each element column includes a plurality of functional elements equally spaced along the column direction. In this way, the uniformity of distribution of the device group O on the light-emitting substrate 200 can be improved.
  • Figure 3 is a structural diagram of a driver chip provided by some embodiments of the present disclosure.
  • the driver chip 100 includes a logic control module CTR, at least one output pin OUT and a first function pin Q1.
  • At least one output pin OUT is electrically connected to the logic control module CTR.
  • FIG. 3 takes the driver chip 100 including four output pins OUT as an example for illustration. Since the driver chip 100 includes four output pins OUT, and each output pin OUT is connected to the light-emitting unit E (as shown in FIG. 2 ), one driver chip 100 can drive at least four light-emitting units E. Compared with the solution in which one driver chip drives one light-emitting unit E, the number of driver chips 100 can be reduced to 1/4, which greatly reduces the usage of the driver chips 100 and thereby reduces the cost of the light-emitting substrate 200 .
  • driver chip 100 in some embodiments of the present disclosure is slightly larger in size than a driver chip with only one output pin, this embodiment can significantly reduce the size of the driver chip 100 in the light-emitting substrate 200 . quantity, thereby reducing the area ratio of all driver chips 100 in the light-emitting substrate 200 . It can also help improve the binding efficiency of the driver chip 100 and improve the yield of the light-emitting substrate 200 .
  • the driver chip 100 in some embodiments of the present disclosure has four output pins OUT, and its area is twice that of a driver chip with only one output pin OUT; however, the light-emitting substrate 200 in this embodiment has The number of driver chips 100 can be reduced to 1/4, thereby reducing the area ratio of the driver chips 100 in the light-emitting substrate 200 in this embodiment to 1/2 (relative to a light-emitting substrate in which one driver chip drives one light-emitting unit E 200).
  • the driver chip 100 may include 3 output pins OUT, 5 output pins OUT, or 6 output pins OUT.
  • the solution in which one driver chip 100 includes four output pins OUT is more conducive to reducing the area ratio of the driver chip 100 and saving resources than the solution in which one driver chip 100 includes three output pins OUT.
  • a solution in which a driver chip 100 includes 4 output pins OUT is compared to a solution in which a driver chip 100 includes 5 output pins OUT or 6 output pins OUT.
  • the number of output pins OUT is relatively small, it can This prevents the driver chip 100 from generating a large amount of heat during operation, which is beneficial to extending the service life of the driver chip 100 .
  • the first function pin Q1 is electrically connected to the logic control module CTR.
  • the first functional pin Q1 can receive the test signal.
  • the logic control module CTR is configured to generate a test current flowing through any output pin OUT according to the test signal.
  • the driver chip 100 in this embodiment can use the first function pin Q1 to provide a test signal to the logic control module CTR.
  • the logic control module CTR generates a test current flowing through any output pin OUT according to the test signal.
  • the test current can drive the light-emitting unit E to emit light.
  • the lighting test of the light-emitting unit E electrically connected to each driver chip 100 can be implemented through a one-step detection operation. If the light-emitting unit E emits light normally, it can be determined that the light-emitting unit E is connected normally. If the light-emitting unit E does not emit light, it can be determined that there is a problem with the light-emitting unit E (such as short circuit, open circuit, etc.) and needs to be repaired to improve the driving chip 100 maintenance efficiency.
  • test current flowing through either output pin OUT can be the same. It can be understood that in other examples, the current flowing through each output pin OUT may be different. Or, partially the same. This disclosure does not limit this.
  • Figure 4 is a structural diagram of a driver chip in some implementations.
  • the driver chip includes the output pin OUT, the address pin Di, the relay pin Do, the data pin Data, the ground pin GND, and the power supply. pin V.
  • the address pin Di is used to receive the address signal, configure the address information of the driver chip according to the address signal, and generate a relay signal; the relay signal can be used as the address signal of the next-level driver chip.
  • the data pin Data is used to receive driving data.
  • the driving data includes driving information and address verification information. When the address verification information matches the address information, a driving current corresponding to at least one light-emitting unit connected to the driving chip is generated according to the driving information. And control an output pin of the driving chip to form an electrical path with the corresponding light-emitting unit, and the driving current flows in the electrical path.
  • the previous driver chip normally drives the light-emitting unit. If the light-emitting unit electrically connected to the driver chip does not emit light, , it can be determined that there is a problem with the light-emitting unit E and needs to be repaired. As for the driver chips with poor pin welding, subsequent cascaded driver chips cannot receive relay signals, that is, this part of the driver chips cannot provide driving current, and the corresponding electrically connected light-emitting units cannot emit light. However, this part cannot determine whether the light-emitting unit electrically connected to the driving chip of this part is connected normally. It requires continuous repeated testing and lighting at one level for judgment, resulting in low maintenance efficiency of the driver chip.
  • Some embodiments of the present disclosure provide a driver chip 100 that is provided with a first functional pin Q1 and a second functional pin Q2.
  • the first function pin Q1 can receive the test signal and send the test signal to the logic control module CTR.
  • the logic control module CTR generates test currents flowing through any output pin OUT respectively according to the test signal.
  • the test current can drive the light-emitting unit E to emit light.
  • the second functional pin Q2 is electrically connected to the first functional pin Q1.
  • the second function pin Q2 can output a test signal to the next-level driver chip 100 .
  • the lighting test of the light-emitting units E electrically connected to each driving chip 100 can be implemented through a one-step detection operation.
  • the light-emitting unit E does not emit light, it can be determined that there is a problem with the light-emitting unit E. There is no need to repeat the three stages of writing addresses, inputting drive data, and repairing until it is determined whether all the light-emitting units need maintenance, which effectively improves the efficiency of the driver chip 100 maintenance efficiency.
  • the driver chip 100 has a first edge W1 and a second edge W2 that are parallel to each other.
  • the driver chip 100 also has a fourth edge W4 located between the second end of the first edge W1 and the second end of the second edge W2.
  • the driver chip 100 includes a plurality of output pins OUT, the plurality of output pins OUT are close to the fourth edge, and the plurality of output pins OUT are arranged along the extending direction of the fourth edge W4. This facilitates the electrical connection between multiple output pins OUT and the same second voltage line outside the driver chip 100, avoids overlap between signal lines connected to the driver chip 100, and is conducive to the wiring layout of the light-emitting substrate.
  • FIG. 3 takes as an example that one end of the fourth edge W4 is directly connected to the first edge W1 and the other end of the fourth edge W4 is directly connected to the second edge W2. It can be understood that in other embodiments, the fourth edge W4 and the first edge W1 are connected through other edges. In still other embodiments, the fourth edge W4 and the second edge W2 are connected through other edges.
  • FIG. 5 is a schematic diagram of two driver chips connected to each other according to some embodiments of the present disclosure.
  • the driver chip 100 further includes a second functional pin Q2.
  • the second functional pin Q2 is electrically connected to the first functional pin Q1.
  • the second function pin Q2 can output a test signal to the next-level driver chip 100 .
  • the first functional pin Q1 is used to provide a test signal to the logic control module CTR.
  • the logic control module CTR generates a test current flowing through any output pin OUT according to the test signal.
  • the test current can drive the light-emitting unit E to emit light.
  • the second functional pin Q2 is then used to output a test signal to the first functional pin Q1 of the next-level driver chip 100. Therefore, the lighting test of the light-emitting unit E electrically connected to each driver chip 100 can be implemented through a one-step detection operation. . If the light-emitting unit E emits light normally, it can be determined that the light-emitting unit E is connected normally. If the light-emitting unit E does not emit light, it can be determined that there is a problem with the light-emitting unit E (such as short circuit, open circuit, etc.) and needs to be repaired to improve the driving chip 100 maintenance efficiency.
  • the second functional pin Q2 is electrically connected to the first functional pin Q1.
  • the second functional pin Q2 and the first functional pin Q1 receive the same signal.
  • the test signal can be output to the first functional pin Q1 of the lower-level driver chip 100 through the second functional pin Q2. It facilitates the wiring design between the driver chips 100 designed to be cascaded with each other.
  • the driver chip 100 includes a first functional pin Q1 and a second functional pin Q2.
  • the first functional pin Q1 and the second functional pin Q2 are respectively located on two relatively parallel sides of the driver chip 100, and the first functional pin Q1 and the second functional pin Q2 are electrically connected to each other.
  • the first function pin Q1 can receive the test signal and send the test signal to the logic control module CTR.
  • the logic control module CTR generates test currents flowing through any output pin OUT respectively according to the test signal.
  • the test current can drive the light-emitting unit E to emit light.
  • the second functional pin Q2 is electrically connected to the first functional pin Q1.
  • the second function pin Q2 can output a test signal to the next-level driver chip 100 . That is to say, the second functional pin Q2 of the upper-level driver chip 101 can output a test signal to the first functional pin Q1 of the lower-level driver chip 102.
  • the logic control module CTR in the lower-level driver chip 102 Generate test currents flowing through any output pin OUT respectively.
  • the next-level driver chip 102 can be used to continue outputting test signals to the next-level driver chip.
  • the driver chip 100 in this embodiment can use the first function pin Q1 to provide a test signal to the logic control module CTR.
  • the logic control module CTR generates a test current flowing through any output pin OUT according to the test signal. This test current can drive the light-emitting unit E (shown in Figure 2) to emit light.
  • the second functional pin Q2 is electrically connected to the first functional pin Q1.
  • the second function pin Q2 can output a test signal to the next-level driver chip 100 .
  • the light-emitting unit E does not emit light, it can be determined that there is a problem with the light-emitting unit E and needs to be repaired to improve the maintenance efficiency of the driver chip 100 .
  • Arranging the first functional pin Q1 and the second functional pin Q2 along the first direction X facilitates wiring design.
  • the driver chip 100 further includes a second functional pin Q2 and a first connection line L1.
  • the second function pin Q2 is connected to the first function pin Q1 through the first connection line L1.
  • the second function pin Q2 outputs a test signal to the next-level driver chip.
  • the driver chip 100 has a first edge W1 and a second edge W2 that are parallel to each other. Among the first functional pin Q1 and the second functional pin Q2, one is close to the first edge W1 and the other is close to the second edge W2.
  • the first edge W1 is the upper edge of the driver chip 100
  • the second edge W2 is the lower edge of the driver chip 100
  • the lower edge of the upper-level driver chip 101 is close to the upper edge of the lower-level driver chip 102 . Therefore, the first functional pin Q1 is set close to the first edge W1, and the second functional pin Q2 is set close to the second edge W2. That is, the second functional pin Q2 of the upper-level driver chip 101 is close to the first functional pin Q1 of the next-level driver chip 102 .
  • An external connection line K1 can be used to electrically connect the second functional pin Q2 of the upper-level driver chip 101 and the first functional pin Q1 of the lower-level driver chip 102 .
  • the first functional pin Q1 is close to the first edge W1 and the second functional pin Q2 is close to the second edge W2 .
  • the first connection line L1 may be provided inside the driving chip 100 ; in other examples, the first connection line L1 may be provided on the light-emitting substrate, that is, located outside the driving chip 100 .
  • the orthographic projection of the first connection line L1 on the light-emitting substrate is located between the orthographic projections of the first functional pin Q1 and the second functional pin Q2 on the light-emitting substrate.
  • the first connection line L1 is located between two adjacent drive chips 100 arranged in cascade, which can make full use of the space between adjacent drive chips 100 while reducing the space around the drive chips 100 (as shown in Figure 3 and Figure 5
  • the space occupied by the driver chip 100 (left and right) is dispersed among the signal lines electrically connected to the driver chip 100, which facilitates the wiring layout of each signal line.
  • the first connection line L1 may be a wiring inside the driver chip 100 , and the first connection line L1 is a straight line.
  • This disclosure does not specifically limit the shape of the first connection trace L1 and the position of the film layer, as long as it is between the first functional pin Q1 and the second functional pin Q2 and connects the first functional pin Q1 and the second functional pin Q2.
  • the driver chip 100 also includes a data pin Data (as shown in Figure 4).
  • the data pin Data is used to connect the data signal line to receive drive data.
  • the drive data includes drive information and address verification information.
  • the logic control module CTR is also configured to: when the address verification information matches the address information of the drive chip 100, determine the drive information corresponding to the address verification information, and generate at least one light-emitting unit connected to the drive chip 100 based on the drive information. E (as shown in FIG. 2 ), and controls at least one output pin OUT of the driver chip 100 to form an electrical path with the corresponding light-emitting unit E, and the driving current can flow in the electrical path.
  • the driver chip 100 also includes an address pin Di and a relay pin Do.
  • the address pin Di is electrically connected to the logic control module CTR; the address pin Di can receive drive data; the drive data includes address verification information and multiple drive information corresponding to multiple cascaded drive chips.
  • the logic control module CTR is configured to: obtain a driver information corresponding to the current driver chip according to the address verification information; and update the address verification information to generate driver data containing the updated address verification information.
  • the relay pin Do is electrically connected to the logic control module; the relay pin Do can output drive data including updated address verification information to the next-level driver chip 102 .
  • the address pin Di of the current-level driver chip 101 can receive drive data; the drive data includes the address verification information of the current-level driver chip 101 and multiple drive information corresponding to all cascaded driver chips.
  • the logic control module CTR of the current-level driver chip 101 receives the drive data and obtains the drive information corresponding to the address verification information of the current-level driver chip 101 according to the address verification information in the drive data.
  • the logic control module CTR generates a driving current corresponding to at least one light-emitting unit E (as shown in FIG. 2 ) connected to the driving chip 100 according to the driving information, and controls at least one output pin OUT of the driving chip 100 and the corresponding light-emitting unit.
  • the cells E form electrical paths in which drive current can flow.
  • the logic control module CTR of the current-level driver chip 101 updates the address verification information and generates updated address verification information.
  • the updated address verification information contains updated address verification information.
  • the relay pin Do can output updated address verification information to the next-level driver chip 102 .
  • the logic control module CTR will also update the received drive data, that is, update the address verification information in the drive data.
  • the address verification information in the drive data is the number of start identification bits and/or end identification bits. Decrease the number of start identification bits of the drive data by 1 and/or increase the number of end identification bits by 1, and output the re-edited drive data to the address pin Di of the next-level driver chip through its relay pin Do. .
  • the driver chip 100 can also use other different functions to generate new address verification information.
  • the address pin Di in the driver chip 100 can be used to receive driving data.
  • the drive data includes address verification information and multiple drive information corresponding to multiple cascaded drive chips.
  • the logic control module CTR of the current-level driver chip 101 updates the address verification information and generates updated address verification information.
  • the updated address verification information contains updated address verification information.
  • the relay pin Do can output updated address verification information to the next-level driver chip 102. That is to say, the driving data of the address pin Di simultaneously realizes the functions of writing the address and inputting the driving information.
  • the lead time of the driver chip 100 can be reduced.
  • the number of pins is conducive to reducing the area ratio of the driver chip 100 and saving resources. It is also beneficial to the subsequent layout design of each trace of the signal of the driver chip 100 .
  • an encoder may be provided on an external circuit (such as a circuit board), and a decoder may be provided on the logic control module CTR.
  • the encoder can encode according to the 4b/5b encoding protocol, 8b/10b encoding protocol or other encoding protocols to generate drive data and transmit it to the address pin Di.
  • the decoder of the logic control module CTR can decode the driving signal and obtain the driving information and address verification information in the driving data.
  • the description is given as an example in which the driver chip 100 does not set a data pin, but uses the address pin Di and the relay pin Do to respectively realize the reception and transmission of the driving data.
  • the address pin Di of the first-level driver chip among the N driver chips 100 cascaded in sequence on the light-emitting substrate 200 is connected to an address signal line, and the address signal line transmits driving data.
  • the driving data transmitted in the address signal line includes driving information corresponding to a plurality of driving chips connected in sequence.
  • the driving data transmitted in the address signal line includes driving information corresponding to a plurality of driving chips connected in sequence.
  • Figure 6 is a schematic diagram of a data format of driving data provided by some embodiments of the present disclosure.
  • the driving data is a digital signal, consisting of a start identification bit, address information, a register address, register byte length information, data information, and an end identification bit.
  • the start identification bit and the end identification bit can occupy n bits respectively, where n is 1 or 8; the driving data can include multiple start identification bits and multiple end identification bits, the number of start identification bits and the end identification bit The sum of the numbers is constant, for example, N+1, where N is the number of multiple cascaded driver chips.
  • the address information may include multiple groups, each group occupying 8 bits.
  • the address information includes 4 groups, namely:
  • the command address group (dev addr) implements different command controls by assigning values to the 8 bits of the command address respectively.
  • the problem address group (vled low dev addr) can feed back the location where the potential abnormality occurs on the second voltage line 10.
  • the fault address group (fault dev addr) can feed back the address information of the failed driver chip 100.
  • the fault status group (fault status) can feed back the specific status of the failed driver chip 100.
  • the address information may only include the command address.
  • the register address and register byte length information each occupy 8 bits.
  • the register address corresponds to the physical address (unique) of the register unit in a certain driver chip, and the register byte length represents the data byte length that needs to be reserved for the register unit, thereby facilitating the storage of configuration information.
  • the data information includes N pieces of 8-bit driver information, and the N pieces of driver information are arranged in the cascade sequence of N driver chips.
  • the assignment of any bit in the driving data can be achieved through pulse width modulation.
  • the duty cycle of a certain bit is 50%, which represents the starting point of the driving data; the duty cycle of a certain bit is 50%. If the duty cycle is 75%, it represents a logic "1"; if a certain bit has a duty cycle of 25%, it represents a logic "0".
  • FIG. 7 is a schematic diagram of another data format of driving data provided by some embodiments of the present disclosure.
  • the address pin Di of the first-level driver chip is connected to the address signal line 20 , and the address signal line transmits driving data.
  • the driving data corresponding to the current display frame transmitted in the address signal line 20 is the relay between the address pin Di of the n-th level driving chip (n is a positive integer greater than 1 and less than or equal to N) and the n-1th level driving chip.
  • Pin Do is connected, n is a positive integer greater than 1 and less than or equal to N.
  • Each driver chip among the N driver chips connected in sequence receives a fixed length of driver data, and the driver data received by each driver chip has a different number of start identification bits and/or end identification bits.
  • the first-level driver chip 100 receives the driver data provided by the address signal line 20, including 1 start identification bit, 3 consecutive The end flag bit;
  • the address pin Di of the second-level driver chip 100 receives the drive data output by the relay pin Do of the second-level driver chip 100, including 2 consecutive start flag bits, 2 consecutive End flag bit;
  • the address pin Di of the third-level driver chip 100 receives the drive data output by the relay pin Do of the second-level driver chip 100, including 3 consecutive start flag bits and 1 end flag bit. .
  • the rest of the data is exactly the same, which may specifically include address information and registers.
  • Address, register byte length information, and data information are the data format as shown in Figure 9; among them, the data information includes three 8-bit driver information, and the three driver information are in accordance with the cascading sequence of three sequentially cascaded driver chips. arrangement. It can be understood that after the address pin Di of each level of driver chip 100 receives the driver data, its logic control module CTR only obtains the driver information corresponding to the driver chip in the driver data, so that the driver chip can operate according to the driver information.
  • the logic control module CTR will also re-edit the received driving data, reducing the number of the start identification bits of the driving data by 1 and/or the number of the end identification bits. The number is incremented by 1, and the reedited driving data is output to the address pin Di of the next-level driver chip through its relay pin Do.
  • the address verification information in the driving data is the number of start identification bits and/or end identification bits.
  • the test signal includes a switching signal.
  • the switch line number is used to control the logic control module CTR to generate test current flowing through any output pin OUT respectively.
  • the logic control module CTR generates test currents flowing through any output pin OUT respectively according to the switch signal. That is, the light-emitting unit E (shown in FIG. 2 ) electrically connected to the driver chip 100 through the output pin OUT can be controlled to receive the test current. And the second function pin Q2 can output a test signal to the next-level driver chip 100 . Therefore, the light-emitting elements E connected to the plurality of driver chips 100 arranged in cascade can all receive the test current and emit light. Therefore, the lighting test of the light-emitting units E electrically connected to each driving chip 100 can be implemented through a one-step detection operation. If the light-emitting unit E does not emit light, it can be determined that there is a problem with the light-emitting unit E, which effectively improves the maintenance efficiency of the driving chip 100 .
  • the test signal may be a high level signal or a low level signal.
  • the logic control module CTR can be controlled by the test signal to generate test currents flowing through any output pin OUT respectively.
  • At least one output pin OUT in the driver chip 100 is electrically connected to one end of the light-emitting unit E, and the other end of the light-emitting unit E is electrically connected to the second voltage line (not shown in the figure).
  • the second voltage line is used to provide operating voltage to the light emitting unit E.
  • the ground pin GND can provide a ground voltage to the driver chip 100 .
  • the light-emitting unit E is equivalent to being connected between the second voltage line and the ground pin GND; the logic control module CTR controls the on or off of the current path of the light-emitting unit E according to the test signal, and then controls the current path through the light-emitting unit E and the output pin. pin OUT current.
  • the logic control module CTR uses the test signal to control the on or off of the light-emitting current path of the light-emitting unit E, thereby controlling the light-emitting Test current for unit E and output pin OUT.
  • the test signal includes a switch signal.
  • the switch line number is used to control the logic control module CTR to generate a test current flowing through any output pin OUT respectively
  • the address pin Di can be set to use to receive driver data.
  • the driver chip 100 can realize the lighting test of the light-emitting units E electrically connected to each driver chip 100 through a one-step detection operation, effectively improving the maintenance efficiency of the driver chip 100; at the same time, the pins in the driver chip 100 will not be increased.
  • the quantity is beneficial to the subsequent layout design of each trace of the driver chip 100 signals.
  • the test signal includes test data and first universal address information.
  • the first universal address information can match the initialization address information of any driver chip 100 .
  • the logic control module CTR is configured to generate a test current flowing through any output pin OUT according to the test data.
  • the driver chip 100 will be set with the same initialization address when it leaves the factory.
  • the initialization address can be a plurality of bits that are consecutive 0s or consecutive 1s.
  • the first general address information in the set test signal is the same as the initialization address of the driver chip 100 . That is to say, when the initialization address is consecutive 0, the general address setting is correspondingly set to consecutive 0.
  • the first general address information is used to match the initialization address information of all driver chips 100, so that the logic control module CTR of the driver chip 100 obtains the test data in the test signal and generates test currents flowing through any output pin OUT respectively.
  • the light-emitting element E receives the test current and emits light. Therefore, the lighting test of the light-emitting units E electrically connected to each drive chip 100 can be implemented through a one-step detection operation, thereby effectively improving the maintenance efficiency of the drive chips 100 .
  • At least one output pin OUT in the driver chip 100 is electrically connected to one end of the light-emitting unit E, and the other end of the light-emitting unit E is electrically connected to the second voltage line (not shown in the figure).
  • the second voltage line is used to provide operating voltage to the light emitting unit E.
  • the ground pin GND can provide a ground voltage to the driver chip 100 .
  • the light-emitting unit E is equivalent to being connected between the second voltage line and the ground pin GND; the logic control module CTR identifies the address information and obtains the test data in the test signal.
  • the logic control module CTR controls the on or off of the current path of the light-emitting unit E according to the test data, and then controls the current through the light-emitting unit E and the output pin OUTP.
  • the logic control module CTR recognizes the first general address information and obtains the test data in the test signal.
  • the logic control module CTR controls the on or off of the light-emitting current path of the light-emitting unit E according to the test data, and then controls the test current through the light-emitting unit E and the output pin OUTP.
  • the first functional pin Q1 receives the test signal and the driving data in a time-sharing manner. For example, during a period, the first functional pin Q1 receives a test signal. In another period, the first function pin Q1 receives driving data.
  • the test signal When the first function pin Q1 receives the test signal, the test signal includes test data and first universal address information.
  • the first universal address information can match the initialization address information of any driver chip 100 .
  • the logic control module CTR is configured to generate a test current flowing through any output pin OUT according to the test data.
  • each level driver chip 100 After the first function pin Q1 of each level driver chip 100 receives the test signal, its logic control module CTR can parse the first general address information and obtain the corresponding test data. Thereby, the driver chip provides a test current to the light-emitting unit E electrically connected to it according to the test data.
  • the second functional pin Q2 and the first functional pin Q1 are directly electrically connected through the first connection line L1, the test signal received by the first functional pin Q1 can be transmitted through the second functional pin Q2 through its third functional pin Q2.
  • the second function pin Q2 is output to the first function pin Q1 of the next-level driver chip.
  • the first function pin Q1 and the second function pin Q2 of each level of N driver chips in the cascade receive the same drive data.
  • the drive data includes N address verification information and N drive information.
  • an address verification information and a driver information form an array
  • N arrays are arranged in sequence. For example, they can be arranged in sequence according to the cascade sequence of N driver chips, or they can also be arranged in an irregular order.
  • the logic control module CTR is also configured to: when the address verification information matches the address information, receive the corresponding driving information according to the address verification information, and generate at least one light-emitting unit E connected to the driving chip 100 according to the driving information (as shown in the figure 2) corresponding to the driving current, and controls at least one output pin OUT of the driving chip 100 to form an electrical path with the corresponding light-emitting unit E, and the driving current flows in the electrical path.
  • each level of driving chip 100 receives the driving data
  • its logic control module CTR only obtains the driving information corresponding to the driving chip in the driving data, so that the driving chip is configured according to the driving information.
  • the electrically connected light-emitting unit E provides driving current.
  • its logic control module CTR will also output the received driving data to the first function pin Q1 of the next-level driver chip through its second function pin Q2.
  • the first functional pin Q1 of each level of driver chip 100 receives the driving data, its logic control module CTR only obtains the driving information corresponding to the driving chip in the driving data, so that the driving chip can The driving information provides a driving current for the light-emitting unit E electrically connected thereto.
  • the driving data received by the first functional pin Q1 can be output to the next device through the second functional pin Q2.
  • the first functional pin Q1 of the first-level driver chip since the second functional pin Q2 and the first functional pin Q1 are directly electrically connected through the first connection line L1, the driving data received by the first functional pin Q1 can be output to the next device through the second functional pin Q2.
  • the first functional pin Q1 of the first-level driver chip since the second functional pin Q2 and the first functional pin Q1 are directly electrically connected through the first connection line L1, the driving data received by the first functional pin Q1 can be output to the next device through the second functional pin Q2.
  • the first functional pin Q1 of the first-level driver chip since the second functional pin Q2 and the
  • the first function pin Q1 processes the test signal after receiving the test signal
  • the data pin Data processes the driving data after receiving the driving data. Therefore, the first functional pin Q1 can be used to receive the test signal and the driving data in a time-sharing manner.
  • the first functional pin Q1 is used to receive the test signal.
  • the first functional pin Q1 is used to receive driving data.
  • the data pin Data does not need to be set in the driver chip 100, which is beneficial to reducing the area ratio of the driver chip 100 and saving resources.
  • the driving data received by the first function pin Q1 can be output to the first function pin Q1 of the next-level driver chip through the second function pin Q2, it is also conducive to the layout of the driver chip 100 on the light-emitting substrate. Provide signal routing.
  • the driver chip 100 includes an address pin Di and a relay pin Do.
  • the address pin Di can receive the address signal.
  • the address information of the driver chip 100 is configured according to the address signal, and a relay signal is generated.
  • the relay pin Do can output the relay signal. That is, the initialization address information of each driver chip 100 is updated.
  • the initialization address information and the address signal may be the same type of digital signal. For example, initialize the address information to 0.
  • a driver chip 100 receives an address signal, it can parse, obtain, and store the address information in the address signal. It can also increment the address signal by 1 or another non-zero fixed amount and generate the incremented address signal (new address signal). ) is modulated into a relay signal, and the relay signal serves as the address signal of the next-level driver chip 100 .
  • the driver chip 100 can also use other different functions to update the address signal.
  • the first function pin Q1 is used to receive driving data.
  • the driving data includes a plurality of address verification information and a plurality of driving information corresponding to the plurality of address verification information.
  • a driving current corresponding to at least one output pin OUT is generated according to the received driving information. That is, a driving current corresponding to at least one light-emitting unit E connected to the driving chip 100 is generated, at least one output pin OUT of the driving chip 100 is controlled to form an electrical path with the corresponding light-emitting unit E, and the driving current flows in the electrical path. .
  • the light-emitting element E receives the drive current and emits light.
  • the second function pin Q2 can output the driving data to the next-level driving chip.
  • the updated address information of the first four driver chips 100 are 00000001, 00000010, 00000011, and 00000100 respectively.
  • the address information of the subsequent cascaded driver chips 100 is not updated, and is still the initialized address information 00000000.
  • the first four drive chips 100 can obtain the corresponding drive information from the drive data, that is, the first four drive chips 100 can obtain the corresponding drive information.
  • the electrically connected light-emitting element E can emit light normally. At this time, it is assumed that each light-emitting element E is welded normally.
  • the address verification information in the drive data cannot be matched with the subsequent cascaded driver chips 100 starting from the fifth driver chip.
  • the corresponding driver information cannot be obtained from the drive data, that is, all subsequent driver chips starting from the fifth driver chip cannot obtain the corresponding driver information.
  • the address information of 100 cannot obtain the driving current, causing the light-emitting element E electrically connected to it to be unable to emit light.
  • the driver chip 100 provided by some embodiments of the present disclosure does not need to set data pins, but uses the first functional pin Q1 and the second functional pin Q2 to respectively realize the reception and transmission of driving data. It is beneficial to reduce the area ratio of the driver chip 100 and save resources. It is also beneficial to the subsequent layout of various traces that provide signals for the driver chip 100 .
  • address pin Di may receive an address signal.
  • the address information of the driver chip 100 is configured according to the address signal, the logic control module CTR generates a relay signal according to the received address information, and the relay pin Do can output the relay signal. That is, the initialization address information of each driver chip 100 is updated.
  • the initialization address information and the address signal may be the same type of digital signal. For example, initialize the address information to 0.
  • a driver chip 100 receives an address signal, it can parse, obtain, and store the address signal in the address signal. It can also add a fixed amount to the address signal as a relay signal, and the relay signal serves as the address of the next-level driver chip 100. Signal. When the fixed quantity is 0, that is, the address signals of all driver chips 100 are the same. Of course, the driver chip 100 can also use other different functions to update the address signal.
  • the test signal includes test data and second general address information.
  • the second universal address information can match the address information of any driver chip 100 .
  • the logic control module CTR is configured to generate a test current flowing through any output pin OUT according to the test signal.
  • the address information of the driver chip and subsequent cascaded driver chips will be lost. Unable to update.
  • the updated address information of the first four driver chips 100 is all 11111111, and the address information of all subsequent driver chips 100 starting from the fifth driver chip is still the initialized address information 00000000.
  • the second general address information in the test signal is preset to 11111111, which can match the updated address information of the first four driver chips 100, that is, the light-emitting element E electrically connected to the first four driver chips 100 can emit light normally. At this time, it is assumed that each light-emitting element E is welded normally.
  • the second general address information in the test signal cannot match the address information of all subsequent driver chips 100 starting from the fifth one (the address information after updating the initialization information), that is, the address information of all subsequent driver chips 100 starting from the fifth one.
  • the logic control module cannot obtain the driving information from the driving data, causing the light-emitting elements E electrically connected to it to fail to emit light.
  • the driver chip 100 further has a third edge W3 located between the first end of the first edge W1 and the first end of the second edge W2.
  • the driver chip 100 includes an address pin Di and a relay pin Do: one of the address pin Di and the relay pin Do is close to the first edge W1 and the other is close to the second edge W2.
  • the address pin Di and the relay pin Do are closer to the third edge W3 than the first function pin Q1 and the second function pin Q2.
  • one of the address pin Di and the relay pin Do is set close to the first edge W1 and the other is set close to the second edge W2.
  • the first edge W1 is the upper edge of the driver chip 100
  • the second edge W2 is the lower edge of the driver chip 100
  • the lower edge of the upper-level driver chip 101 is close to the upper edge of the lower-level driver chip 102 .
  • the address pin Di is set close to the first edge W1
  • the relay pin Do is set close to the second edge W2. That is, the relay pin Do of the upper-level driver chip 101 is close to the address pin Di of the next-level driver chip 102 .
  • An external connection line K2 can be used to electrically connect the relay pin Do of the upper-level driver chip 101 and the address pin Di of the lower-level driver chip 102 .
  • the address pin Di of the upper-level driver chip 101 receives the address signal, and the logic control module CTR of the upper-level driver chip 101 configures the address information of the upper-level driver chip 101 according to the address signal, and generates a relay signal.
  • the relay signal can be used as an address signal of the next-level driver chip 102, and the relay pin Do of the upper-level driver chip 101 sends the relay signal to the address pin Di of the next-level driver chip 102. Then, dynamic addresses are allocated to the cascaded driver chips 100 .
  • the address pin Di is set close to the first edge W1
  • the relay pin Do is set close to the second edge W2. It is also beneficial to reduce the length of the external connection wire K2 and facilitate flexible setting of the position of the external connection wire K2, thereby facilitating subsequent wiring layout of the light-emitting substrate.
  • the address pin Di and the relay pin Do are set closer to the third edge W3 than the first function pin Q1 and the second function pin Q2. That is, the address pin Di and the relay pin Do are arranged on the upper and lower sides closest to the third edge W3, which facilitates connection to the address signal line outside the driver chip 100 and facilitates subsequent wiring layout of the light-emitting substrate.
  • Figure 5 takes the example of setting the address pin Di close to the first edge W1 and the relay pin Do close to the second edge W2. It can be understood that in other embodiments, the address pin Di can be set close to the second edge W2 and the relay pin Do can be set close to the first edge W1 for illustration. Some embodiments of the present disclosure can flexibly set the positions of the address pin Di and the relay pin Do in the driver chip 100, as long as the relay pin Do of the upper-level driver chip 101 is close to the address pin of the next-level driver chip 102. Just the bottom of your feet.
  • FIG. 5 takes as an example that one end of the third edge W3 is directly connected to the first edge W1 and the other end of the third edge W3 is directly connected to the second edge W2. It can be understood that in other embodiments, the third edge W3 and the first edge W1 are connected through other edges. In yet other embodiments, the third edge W3 and the second edge W2 are connected through other edges.
  • FIG. 8 is a structural diagram of another driver chip provided by some embodiments of the present disclosure.
  • the driver chip 100 further includes at least one ground pin GND.
  • At least one ground pin GND is electrically connected to the logic control module CTR.
  • the ground pin GND can receive the ground signal.
  • the ground pin GND is located between the address pin Di and the relay pin Do.
  • the driver chip 100 further includes at least one ground pin GND for receiving a ground signal.
  • FIG. 8 takes the driver chip 100 including two ground pins GND as an example for illustration. It can be understood that in other embodiments, the driver chip 100 may include 1, 3 or 4 ground pins, which may be selected as needed.
  • the ground pin GND is set close to the third edge W3, and the ground pin GND is located between the address pin Di and the relay pin Do.
  • the ground pin GND can be concentrated in the middle area of the third edge W3 of the driver chip 100, which facilitates the subsequent electrical connection of the ground pin GND with the ground lead and avoids overlapping design problems with other traces.
  • FIG. 9 is a structural diagram of a driver chip provided by some embodiments of the present disclosure.
  • Figure 10 is a structural diagram of a driver chip provided by yet another embodiment of the present disclosure.
  • the driver chip 100 further includes a first power pin V1.
  • the first power pin V1 is electrically connected to the logic control module CTR.
  • the first power pin V1 can receive a power signal.
  • the first power pin V1 is close to the first edge W1 or the second edge W2.
  • the first power pin V1 is farther away from the third edge W3 than the address pin Di and the relay pin Do.
  • the driver chip 100 uses the first power pin V1 to receive the power signal. Provide the power signal required for the operation of the driver chip 100 to ensure the normal operation of the driver chip 100.
  • the first power pin V1 is set close to the first edge W1 or the second edge W2. As shown in FIG. 9 and FIG. 10 , FIG. 9 and FIG. 10 take the first power pin V1 close to the first edge W1 as an example. It can be understood that in other embodiments, the first power pin V1 may also be provided.
  • the foot V1 is close to the second edge W2. Based on this, the first power pin V1 is close to the upper edge or the lower edge of the driver chip 100 .
  • the first power supply pin V1 is set further away from the third edge W3 relative to the address pin Di and the relay pin Do. This can include the following two situations:
  • Type 1 As shown in Figure 9, the first power pin V1 is located between the first function pin Q1 and the address pin Di.
  • the first function pin Q1 is located between the first power pin V1 and the address pin Di.
  • the address pin Di and the relay pin Do are set at the position closest to the third edge W3. It is convenient for the address pin Di to connect to the address signal line outside the driver chip 100, which is beneficial to the subsequent wiring layout of the light-emitting substrate.
  • the driver chip 100 further includes a second power pin V2 and a second connection line L2.
  • the second power pin V2 is connected to the first power pin V1 through the second connection line L2.
  • one of the first power pin V1 and the second power pin V2 is close to the first edge W1, and the other is close to the second edge W2.
  • the first power supply pin V1 and the second power supply pin V2 are farther away from the third edge W3 than the address pin Di and the relay pin Do.
  • the first power pin V1 and the second power pin V2 of the driver chip 100 of this stage are electrically connected through the second connection line L2.
  • the first power pin V1 and the second power pin V2 of the driver chip 100 of this stage receive the same signal.
  • the power signal can be output to the first power pin V1 of the next-level driver chip 100 through the second power pin V2. It facilitates the wiring design between the driver chips 100 designed to be cascaded with each other.
  • the first edge W1 is the upper edge of the driver chip 100
  • the second edge W2 is the lower edge of the driver chip 100
  • the lower edge of the upper-level driver chip 101 is close to the upper edge of the lower-level driver chip 102 .
  • the first power pin V1 is set close to the first edge W1
  • the second power pin V2 is set close to the second edge W2. That is, the first power pin V1 is close to the upper edge of the driver chip 100 , and the second power pin V2 is close to the lower edge of the driver chip 100 . It is convenient to connect the second power pin V2 and the first power pin V1 of two adjacent driver chips 100 so that the two power pins V2 can output power signals to the next-level driver chip 100 .
  • the second connection line L2 may be a wiring inside the driver chip 100 . In other examples, the second connection line L2 may be a trace outside the driver chip 100 but located on the light-emitting substrate. When the second connection line L2 is located on the light-emitting substrate, the orthographic projection of the second connection line L2 on the light-emitting substrate is located between the orthographic projections of the first power pin V1 and the second power pin V2 on the light-emitting substrate.
  • the second connection line L2 is located between two adjacent cascaded driver chips 100, which can fully utilize the space between adjacent driver chips 100 and reduce the space around the driver chips 100 (as shown in Figure 9 and Figure 10
  • the space occupied by the driver chip 100 (left and right) is dispersed among the signal lines electrically connected to the driver chip 100, which facilitates the wiring layout of each signal line.
  • the second connection line L2 may be a wiring inside the driver chip 100 , and the second connection line L2 is a straight line.
  • This disclosure does not specifically limit the shape of the second connection line L2 and the position of the film layer, as long as it is between the first power supply pin V1 and the second power supply pin V2 and connects the first power supply pin V1 and the second power supply pin. Just use pin V2.
  • FIG. 9 and FIG. 10 take the first power pin V1 close to the first edge W1 and the second power pin V2 close to the second edge W2 as an example. It can be understood that in other embodiments, the first power pin V1 can also be set close to the second edge W2, and the second power pin V2 can be set close to the first edge W1. Just make the second power pin V2 and the first power pin V1 of the two adjacent driver chips 100 close to each other.
  • the first power pin V1 and the second power pin V2 are farther away from the third edge W3 than the address pin Di and the relay pin Do.
  • the following two situations can be included:
  • Type 1 As shown in Figure 9, the first power pin V1 is located between the first function pin Q1 and the address pin Di.
  • the second power supply pin V2 is located between the second function pin Q2 and the relay pin Do.
  • the first function pin Q1 is located between the first power pin V1 and the address pin Di.
  • the second function pin Q2 is located between the second power supply pin V2 and the relay pin Do.
  • the address pin Di and the relay pin Do are set at the position closest to the third edge W3. It is convenient for the address pin Di to connect to the address signal line outside the driver chip 100, which is beneficial to the subsequent wiring layout of the light-emitting substrate.
  • FIG. 11 is a structural diagram of a light-emitting substrate according to further embodiments of the present disclosure.
  • Figure 12 is a partial enlarged view of the R position in Figure 11.
  • the light-emitting substrate 200 includes a plurality of cascaded driver chips 100 and a plurality of device groups O.
  • the driver chip 100 is the driver chip 100 of any of the above embodiments.
  • the first end Oa of a device group O is electrically connected to at least one output pin OUT of a driver chip 100 .
  • one device group O includes at least one light emitting unit E.
  • a light-emitting unit E may include at least one light-emitting element.
  • one light-emitting unit E may include only one light-emitting element.
  • one light-emitting unit E may include two or more light-emitting elements that are electrically connected to each other.
  • the two or more light-emitting elements can be connected in series, in parallel, or in a mixed series-parallel connection.
  • the first end Oa of a device group O is electrically connected to at least one output pin OUT of a driver chip 100. It can be the light-emitting unit E in a device group O and the output of a driver chip 100.
  • the pins OUT correspond one to one.
  • the embodiment of the present disclosure does not limit the number of light-emitting units E electrically connected to each output pin OUT, and can be adjusted according to actual needs.
  • a driver chip 100 includes four output pins OUT.
  • One device group O includes four light emitting units E.
  • An output pin OUT is electrically connected to a light-emitting unit E.
  • the first function pin Q1 in each driver chip 100 can be used to provide a test signal to its corresponding logic control module CTR, and the logic control module CTR generates a test current flowing through any output pin OUT respectively.
  • the test current can drive the light-emitting unit E to emit light. That is, all the light-emitting units E electrically connected to the driving chip 100 can receive the test current under normal circumstances. Therefore, the lighting test of the light-emitting units E electrically connected to each driving chip 100 can be implemented through a one-step detection operation. If the light-emitting unit E emits light normally, it can be determined that the light-emitting unit E is connected normally. If the light-emitting unit E does not emit light, it can be determined that there is a problem with the light-emitting unit E and needs to be repaired to improve the maintenance efficiency of the driver chip 100 .
  • the driver chip 100 also includes an address pin Di, a relay pin Do, a first power pin V1 and at least one ground pin GND.
  • the relay pin Do of the driver chip 100 at the upper level is electrically connected to the address pin Di of the driver chip 100 at the next level.
  • the light emitting substrate 200 further includes a conductive layer M.
  • the conductive layer M includes the second voltage line 10 , the address signal line 20 , the first voltage line 30 , the test signal line 40 and the ground line 50 .
  • the second voltage line 10 extends along the first direction X, and the plurality of light-emitting units E in one device group O are arranged along the first direction X.
  • the second voltage line 10 is provided to be electrically connected to the second end of each device group. That is, the second voltage line 10 is electrically connected to at least one light-emitting unit E in each device group O, and provides the driving voltage to the light-emitting unit E.
  • the conductive wire 11 extending in the direction Y is connected to the second voltage wire 10 .
  • the respective conductive lines 11 are parallel to each other.
  • the first direction X and the second direction Y intersect and are parallel to the light-emitting substrate 200 .
  • the first direction X and the second direction Y are perpendicular. It can be understood that in other embodiments, the angle between the first direction X and the second direction Y may be an obtuse angle or an acute angle.
  • multiple cascade-arranged driver chips 100 are arranged along the first direction Y.
  • multiple cascade-arranged driver chips 100 can be connected to the same second voltage line 10 , they can be arranged along the second direction Y.
  • the extended conductive wire 11 is connected to the second voltage wire 10 .
  • There is no overlap between the conductive lines 11 which is beneficial to realizing the single-layer wiring design of the light-emitting substrate 200 .
  • each conductive line 11 is parallel to each other.
  • Each device group O includes a plurality of light-emitting units E arranged in a row.
  • a second voltage line 10 may be provided to be electrically connected to all the light emitting units E in a device group O. It is also possible to arrange multiple device groups O forming a device group column to be connected to the same second voltage line 10 at the same time.
  • the second voltage line 10 provides at least one light emitting unit E with a first voltage.
  • the ground wire 50 is electrically connected to at least one ground pin GND of each driver chip 100 .
  • the ground wire 50 is electrically connected to each ground pin GND of each driver chip 100 to provide a ground signal for the ground pin.
  • the ground line 50 extends along the first direction X, the ground line 50 is located outside the driver chip 100, and the ground line 40 is close to the ground pin GND. Since the ground wire 50 needs to be electrically connected to at least one ground pin GND of each driver chip 100, setting the ground wire 40 closest to the ground pin GND can facilitate the electrical connection between the ground wire 40 and the ground pin GND and avoid intersection with other signal lines. Stack.
  • the address signal line 20 is electrically connected to the address pin Di.
  • the address pin Di of the first driver chip among the plurality of driver chips 100 arranged in cascade is electrically connected to the address signal line 20 .
  • the relay pin Do of the upper-level driver chip is electrically connected to the address pin Di of the lower-level driver chip through an external connection line K2.
  • the address pin Di is implemented to receive an address signal, configure the address information of the driver chip 100 according to the address signal, and the logic control module CTR generates a relay signal according to the received address information.
  • the relay signal can be used as an address signal for the next-level driver chip 100 .
  • the relay pin Do can output the relay signal.
  • the address signal line 20 extends along the first direction Y, and is located on a side of the ground line 40 away from the address pin Di. Since the address signal line 20 only needs to be electrically connected to the address pin Di of the first driver chip 100, arranging it on a side relatively far away from the driver chip 100 can facilitate the electrical connection between the ground wire 50 and the ground pin GND and avoid addressing the problem.
  • the signal line 20 and the ground line 50 overlap, which is beneficial to realizing a single-layer wiring design of the light-emitting substrate 200 .
  • the first voltage line 30 is electrically connected to the first power pin V1 of each driver chip 100 .
  • the first power pin V1 is located on the upper edge of the driver chip. That is, the first power pin V1 in the multiple cascade-arranged driver chips 100 is electrically connected to the first voltage line 30. It is used to provide voltage to each driver chip 100 so that it can operate normally.
  • the test signal line 40 is electrically connected to the first functional pin Q1 of each first driver chip 100 .
  • the test signal line 40 is located on the upper edge of the driver chip. That is, the first function pin Q1 in the multiple cascade-arranged driver chips 100 is electrically connected to the test signal line 40 . It is used to provide test signals for each driving chip 100 and to test whether there are abnormalities in the light-emitting units E electrically connected to all the driving chips 100 .
  • the second voltage line 10 is located on the side of the light-emitting unit E away from the driving chip 100 .
  • the address signal line 20 and the ground line 50 are located on a side close to the ground pin GND of the driver chip 100 , and the ground line 50 is located between the address signal line 20 and the driver chip 100 .
  • the first voltage line 30 , the test signal line 40 and the external connection line K2 are located between the second voltage line 10 and the ground line 50 .
  • the driver chip 100 also includes a second functional pin Q2, the second functional pin Q2 is respectively connected to the driver chip 100 of this level.
  • the first functional pin Q1 is electrically connected to the first functional pin Q1 of the next-level driver chip.
  • the second functional pin Q2 may be electrically connected to the first functional pin Q1 of the next-level driver chip through an external connection line K1.
  • the test signal line 40 is electrically connected to the first functional pin Q1 of the first driver chip 100 . Since the second functional pin Q2 is electrically connected to the first functional pin Q1 of the driver chip 100 of this stage, the second functional pin Q2 and the first functional pin Q1 receive the same signal. Furthermore, for other driver chips arranged in cascade, the second functional pin Q2 of the upper-level driver chip and the first functional pin Q1 of the lower-level driver chip are electrically connected through the external connection line K1. This facilitates wiring design between multiple cascade-designed driver chips 100 in the light-emitting substrate 200 .
  • the external connection line K1 is located between the second voltage line 10 and the ground line 50 . There can be no overlap between the second voltage line 10, the address signal line 20, the first voltage line 30, the test signal line 40 and the ground line 50, thereby realizing a single-layer wiring design of the light-emitting substrate 200 and reducing the process of the light-emitting substrate 200. Difficulty and cost reduction.
  • the driver chip 100 also includes a second power pin V2
  • the second power pin V2 is connected to the third pin of the driver chip 100 of the current level.
  • a power pin V1 is electrically connected to the first power pin V1 of the next-level driver chip 100 .
  • the second power pin V2 is electrically connected to the first power pin V1 of the next-stage driver chip 100 through an external connection line K3.
  • the first voltage line 30 is electrically connected to the first power pin V1 in the first driver chip 100 among the plurality of driver chips 100 arranged in cascade. Since the second power pin V2 is electrically connected to the first power pin V1 of the driver chip 100 of this level, the first power pin V1 and the second power pin V2 of the driver chip 100 of this level receive the same signal. Furthermore, for other driver chips arranged in cascade, it is convenient to realize that the second power pin V2 of the upper-level driver chip outputs the power signal to the first power pin V1 of the lower-level driver chip. This facilitates wiring design between multiple cascade-designed driver chips 100 in the light-emitting substrate 200 .
  • the external connection line K3 is located between the second voltage line 10 and the ground line 50 . There can be no overlap between the second voltage line 10, the address signal line 20, the first voltage line 30, the test signal line 40 and the ground line 50, thereby realizing a single-layer wiring design of the light-emitting substrate 200 and reducing the process of the light-emitting substrate 200. Difficulty and cost reduction.
  • the address signal line 20 is configured to transmit the address signal
  • the test signal line 40 is configured to transmit the test signal and the driving data in a time-sharing manner.
  • the address signal line 20 transmits the address signal to the address pin Di, and the address pin Di receives the address signal.
  • the logic control module CTR configures the address information of the driver chip 100 according to the address signal and generates a relay signal.
  • the relay signal can be used as an address signal for the next-level driver chip 100 .
  • the relay pin Do is electrically connected to the logic control module CTR. The relay pin Do can output the relay signal.
  • the address signal may be a digital signal.
  • a driver chip 100 receives an address signal, it can parse, obtain, and store the address signal in the address signal. It can also increment the address signal by 1 or another fixed amount and modulate the incremented address signal (new address signal). is a relay signal, which serves as the address signal of the next-level driver chip 100 .
  • the driver chip 100 can also use other different functions to generate new address signals.
  • the test signal line transmits the test signal and drive data in 40 time-sharing.
  • the test signal line 40 can provide different signals to the same pin (the first functional pin Q1) of the driver chip 100 in a time-sharing manner.
  • the test signal line 40 provides the test signal to the first function pin Q1
  • the first function pin Q1 receives the test signal
  • the test signal includes test data and first general address information.
  • the first general address information can match the initialization address information of any driver chip. Therefore, the logic control module of any driver chip 100 generates a test current flowing through any output pin OUT respectively according to the test data.
  • the light-emitting unit E receives the test current and emits light.
  • the lighting test of the light-emitting units E electrically connected to each drive chip 100 can be implemented through a one-step detection operation, thereby effectively improving the maintenance efficiency of the drive chips 100 .
  • the first functional pin Q1 can also be used to receive the driving data.
  • Driver data includes driver information and address verification information.
  • the driving data includes a plurality of address verification information and a plurality of driving information corresponding to the plurality of address verification information. For any of the driving chips: when the address verification information matches the address information, corresponding driving information is received according to the address verification information, and a driving current corresponding to at least one output pin OUT is generated according to the received driving information.
  • a driving current corresponding to at least one light-emitting unit E connected to the driving chip 100 is generated, and at least one output pin OUT of the driving chip 100 is controlled to form an electrical path with the corresponding light-emitting unit E, and the driving current is in the electrical path. flow. If starting from a certain driver chip 100, none of the light-emitting units E electrically connected to subsequent cascaded driver chips 100 emit light, it is determined that the address pin Di of the initial driver chip 100 is poorly welded and needs to be repaired.
  • the address signal line 20 is configured to transmit driving data
  • different signal lines are used for the address signal line 20 and the second voltage line 10 , which can simplify the driving chip 100
  • the internal circuit structure eliminates the need to install a power conditioning circuit in the driver chip 100 (the power conditioning circuit is used to generate a driving voltage based on the DC component in the power signal and generate driving data based on the modulation component in the power signal), thereby helping to reduce the drive cost.
  • the area of the chip is 100.
  • this setting method can also simplify the external circuit structure, avoid setting up a modulation circuit that modulates the driving voltage and driving data into power line carrier communication, and also reduce the quality requirements for the driving voltage.
  • the address signal line 20 is configured to transmit driving data
  • the test signal line 40 is configured to transmit a test signal
  • the test signal line 40 transmits the test signal to the first function pin Q1, and the test signal received by the first function pin Q1 in the driver chip 100 includes a switching signal.
  • the switching signal is used to control the logic control module CTR to generate test currents flowing through any output pin OUT respectively.
  • all the light-emitting units E electrically connected to the driving chip 100 can be controlled to receive the test current.
  • the second function pin Q2 can output a test signal to the next-level driver chip 100 .
  • the lighting test of the light-emitting units E electrically connected to each driving chip 100 can be implemented through a one-step detection operation. If the light-emitting unit E does not emit light, it can be determined that there is a problem with the light-emitting unit E, which effectively improves the maintenance efficiency of the driving chip 100 .
  • the test signal may be a high level signal or a low level signal. As long as the logic control module CTR can be controlled by the test signal to generate test currents flowing through any output pin OUT respectively.
  • the address signal line 20 transmits driving data to the address pin Di.
  • the address pin Di receives drive data, and the drive data includes address verification information and multiple drive information corresponding to multiple cascaded drive chips.
  • the logic control module CTR configures a driver information corresponding to the current driver chip according to the address verification information; and updates the address verification information to generate driver data containing the updated address verification information.
  • the relay pin Do is electrically connected to the logic control module; the relay pin Do can output drive data including updated address verification information to the next-level driver chip 102 .
  • the address pin Di of the upper-level driver chip 101 can receive drive data; the drive data includes address verification information of the upper-level driver chip 101 and multiple drive information corresponding to all cascaded driver chips.
  • the logic control module CTR of the upper-level driver chip 101 receives the drive data, and configures the drive information corresponding to the address verification information of the upper-level driver chip 101 according to the address verification information in the drive data.
  • the logic control module CTR generates a driving current corresponding to at least one light-emitting unit E connected to the driving chip 100 based on the driving information, and controls at least one output pin OUT of the driving chip 100 to form an electrical path with the corresponding light-emitting unit E to drive Electrical current can flow in this electrical path. If starting from a certain driver chip 100, none of the light-emitting units E electrically connected to subsequent cascaded driver chips 100 emit light, it is determined that the address pin Di of the initial driver chip 100 is poorly welded and needs to be repaired.
  • the logic control module CTR of the upper-level driver chip 101 updates the address verification information and generates updated address verification information.
  • the updated address verification information contains updated address verification information.
  • the relay pin Do can output updated address verification information to the next-level driver chip 102 .
  • the logic control module CTR will also update the received drive data, that is, update the address verification information in the drive data.
  • the address verification information in the drive data is the number of start identification bits and/or end identification bits. Decrease the number of start identification bits of the drive data by 1 and/or increase the number of end identification bits by 1, and output the re-edited drive data to the address pin Di of the next-level driver chip through its relay pin Do. .
  • the driver chip 100 can also use other different functions to generate new address verification information.
  • the light-emitting substrate 200 can transmit driving data through the address signal line 20.
  • the driving data includes address verification information and multiple driving information corresponding to multiple cascaded driving chips. That is to say, the driving data provided by the address signal line 20 can realize the functions of writing addresses and inputting driving information at the same time.
  • the number of signal lines connected to the driving chip 100 is reduced, which facilitates the single-layer wiring design of the light-emitting substrate 200 and reduces the emission of light.
  • the process difficulty of the substrate 200 is reduced and the cost is reduced.
  • the test signal line 40 is configured to transmit the test signal and the driving data in a time-sharing manner
  • the test signal line 40 and the second voltage line 10 respectively adopt different signal lines.
  • the internal circuit structure of the driver chip 100 can be simplified, and there is no need to provide a power conditioning circuit in the driver chip 100 (the power conditioning circuit is used to generate a driving voltage based on the DC component in the power signal and generate driving data based on the modulation component in the power signal), This further helps to reduce the area of the driver chip 100 .
  • this setting method can also simplify the external circuit structure, avoid setting up a modulation circuit that modulates the driving voltage and driving data into power line carrier communication, and also reduce the quality requirements for the driving voltage.
  • the light-emitting substrate 200 further includes a feedback signal line 70 , and the feedback signal line 70 is electrically connected to the relay pin Do of the last driver chip 100 arranged in the cascade.
  • the feedback signal line 70 is close to the ground line 50 and is located between the ground line 50 and the test signal line 40 , which can prevent the feedback signal line 70 from overlapping with other signal lines, such as the ground line 50 and the test signal line 40 . It is convenient to realize the single-layer wiring design of the light-emitting substrate 200, reduce the process difficulty of the light-emitting substrate 200, and reduce the cost.
  • FIG. 13 is a circuit block diagram of a light-emitting substrate according to yet another embodiment of the present disclosure.
  • the driver chip 100 includes an address pin Di, a relay pin Do, a first function pin Q1, a second function pin Q2, a ground pin GND, and a first power supply pin. pin V1 and the second power supply pin V2.
  • the driver chip 100 also includes four output pins OUT.
  • the four output pins OUT are respectively the first output pin OUT1, the second output pin OUT2, the third output pin OUT3 and the fourth output pin OUT4.
  • the logic control module CTR includes four modulation modules, namely the first modulation module PWMM1, the second modulation module PWMM2, the third modulation module PWMM3, and the fourth modulation module PWMM4.
  • the logic control module CTR also includes a control unit CLM.
  • the first to fourth output pins OUT1 to OUT4 are connected to the first to fourth modulation modules PWMM1 to PWMM4 in one-to-one correspondence.
  • the control unit CLM is used to generate the first drive control signal, the second drive control signal, the third drive control signal, and the fourth drive control signal according to the drive data, and transmit them to the first modulation module PWMM1, the second modulation module PWMM2, and the fourth drive control signal respectively.
  • the first modulation module PWMM1 is electrically connected to the first output pin OUT1, and can be turned on or off under the control of the first drive control signal, so that the first output pin OUT1 is electrically connected to the ground pin GND. connected or disconnected.
  • the ground wire 50 shown in Figure 11
  • the first output pin OUT1 When the first modulation module PWMM1 is turned on, the ground wire 50 (shown in Figure 11), the first output pin OUT1, the light-emitting unit E (shown in Figure 11) and the first output pin OUT1 are electrically connected.
  • the two voltage lines 10 (as shown in Figure 11) form a signal loop, and the light-emitting unit E works; when the first modulation module PWMM1 is turned off, the above-mentioned signal loop is disconnected, and the light-emitting unit E does not work.
  • the first modulation module PWMM1 can phase-modulate the driving current flowing through the light-emitting unit E under the control of the first driving control signal, which is a pulse width modulation signal.
  • the first modulation module PWMM1 can modulate the duration of the driving current flowing through the light-emitting unit E according to the first driving control signal, thereby controlling the working state of the light-emitting unit E.
  • the light-emitting unit E contains an LED
  • the duty cycle of the first drive control signal by increasing the duty cycle of the first drive control signal, the total lighting time of the LED within a display frame can be increased, thereby increasing the total lighting brightness of the LED within the display frame, so that the light-emitting substrate 200 The brightness in this area increases; conversely, by reducing the duty cycle of the pulse width modulation signal, the total lighting time of the LED in a display frame can be reduced, thereby reducing the total lighting brightness of the LED in the display frame, so that the light-emitting substrate The brightness in this area is reduced.
  • the second modulation module PWMM2 is electrically connected to the second output pin OUT2, and can be turned on or off under the control of the second drive control signal, which is a pulse width modulation signal.
  • the third modulation module PWMM3 is electrically connected to the third output pin OUT3, and can be turned on or off under the control of the third drive control signal, which is a pulse width modulation signal.
  • the fourth modulation module PWMM4 is electrically connected to the fourth output pin OUT4, and can be turned on or off under the control of a fourth drive control signal, which is a pulse width modulation signal.
  • the first modulation module PWMM1 to the fourth modulation module PWMM4 may be switching elements, such as MOS (metal-oxide semiconductor field effect transistor), TFT (thin film transistor) and other transistors; the first drive control signal ⁇
  • the fourth drive control signal may be a pulse width modulation signal, and the switching element is turned on or off under the control of the pulse width modulation signal.
  • the first modulation module PWMM1 to the fourth modulation module PWMM4 can pass the address signal.
  • the line 20 is electrically connected to the control unit CLM. It can also be electrically connected to the control unit CLM through the address signal line 20, or it can be electrically connected to the control module CLM in other ways.
  • the test signal line 40 is configured to transmit test signals and driving data in a time-sharing manner
  • the first to fourth modulation modules PWMM1 to PWMM4 can be electrically connected to the control unit CLM through the test signal line 40 , or can be tested respectively.
  • the signal line 40 is electrically connected to the control unit CLM, or is electrically connected to the control module CLM in other ways. This disclosure does not place special restrictions on this.
  • the logic control module CTR may also include a fifth modulation module PWMM5, and the fifth modulation module PWMM5 is electrically connected to the relay pin Do.
  • the control unit CLM can receive the address signal from the address pin Di, and generate and transmit the relay control signal to the fifth modulation module PWMM5 according to the address signal; the fifth modulation module PWMM5 can respond Relay the control signal to generate a relay signal and load it to the relay pin Do.
  • the fifth modulation module PWMM5 can be electrically connected to the control unit CLM through the test signal line 40 or the address signal line 20, or can be electrically connected to the control module through a dedicated data line, or can be electrically connected to the control module in other ways.
  • the control module implements electrical connection, and this disclosure does not place special restrictions on this.
  • the address signal line 20 is configured to transmit address signals and drive data in a time-sharing manner
  • the first modulation module PWMM1 to the fifth modulation module PWMM5 and the control unit CLM are all connected to the address signal line 20, so that the address signal line 20 interacts with the first to fifth modulation modules PWMM1 to PWMM5.
  • the test signal line 40 is configured to transmit test signals and driving data in a time-sharing manner
  • the first to fifth modulation modules PWMM1 to PWMM5 and the control unit CLM are all connected to the test signal line 40 , so that the test signal line 40 Interact with the first modulation module PWMM1 to the fifth modulation module PWMM5.
  • the fifth modulation module PWMM5 may include switching elements, such as MOS (Metal-Oxide Semiconductor Field Effect Transistor), TFT (Thin Film Transistor) and other transistors; the relay control signal may be a pulse width modulation signal, and the switch The components are turned on or off under the control of the pulse width modulation signal.
  • the switching element When the switching element is turned on, the fifth modulation module PWMM5 can output current or voltage.
  • the fifth modulation module PWMM5 generates a pulse width modulation signal as a relay signal and is output by the relay pin Do.
  • the fifth modulation module PWMM5 does not output any electrical signal (current or voltage).
  • the logic control module CTR may also include a power module PWRM.
  • the first power pin V1 may load a power signal to the power module PWRM.
  • the power module is configured to distribute power to various circuits of the driver chip 100 to The power supply of the driver chip 100 is guaranteed.
  • the second power pin V2 can also be electrically connected to the power module PWRM for outputting the power signal to the next-level driver chip 100 .
  • Figure 14 is a circuit block diagram of the driver chip in Figure 13. In some embodiments, only the first modulation module PWMM1 is shown and other modulation modules are not shown.
  • the driver chip 100 may include a voltage adjustment circuit 210, a low dropout regulator 230, an oscillator 240, a control unit CLM, an address driver 260, a dimming circuit 270, a transistor 275 and a brightness control circuit. 280. In various implementations, driver chip 100 may include additional, fewer, or different components.
  • the voltage adjustment circuit 210 will receive the power signal at the first power pin V1 and process it to obtain the DC component in the power signal to generate a supply voltage.
  • voltage regulation circuit 210 includes a first-order RC filter followed by an active follower.
  • the supply voltage is provided to low dropout regulator 230 .
  • the low dropout regulator 230 converts the supply voltage into a stable DC voltage (which can step down the voltage) for powering the oscillator 240, the control unit CLM and other components (not shown).
  • the stable DC voltage may be 1.8 volts.
  • the oscillator 240 provides a clock signal, and the maximum frequency of the clock signal may be about 10 MHz, for example.
  • the control unit CLM receives the test signal from the first function pin Q1.
  • the test signal includes test data and first general address information.
  • the first general address information can match the initialization address information of any driver chip 100. This generates test currents flowing through any output pin OUT respectively.
  • the light-emitting unit E receives the test current and emits light.
  • the control unit CLM receives the test signal via the first function pin Q1, and provides the first universal address information in the test signal to the address driver 260.
  • the address driver 260 caches the first universal address information into the second function pin Q2, Provide test signals to the next-level driver chip 100 .
  • the control unit CLM receives the driving data from the data pin (first function pin Q1 ), the DC voltage from the low dropout regulator 230 and the clock signal from the oscillator 240 . Depending on the working stage of the light-emitting substrate, the control unit CLM can also receive digital data from the address signal received at the address pin Di; the control unit CLM can output an enable signal 252, an incremental data signal 254, a PWM clock selection signal 256 and maximum current signal 258. The control unit CLM activates the enable signal 252 to enable the address driver 260 . The control unit CLM receives the address signal via address pin Di, stores the address and provides an incremented data signal 254 representing the outgoing address to the address driver 260 .
  • the address driver 260 buffers the incremented data signal 254 to the relay pin Do.
  • the control unit CLM may control the dimming circuit 270 to turn off the transistor 275 to effectively block the current path from the light-emitting unit.
  • the control unit CLM can also deactivate the enable signal 252 and tri-state the output of the address driver 260 to effectively decouple it from the relay pin Do.
  • PWM clock selection signal 256 specifies the duty cycle used to control PWM dimming by PWM dimming circuit 270 . Based on the selected duty cycle, PWM dimming circuit 270 controls the timing of the on-state and off-state of transistor 275 . During the on-state of the transistor 275, a current path is established through the transistor 275 from the output pin OUT (coupled to the device unit, OUT1 is used as an example in FIG. 14) to the ground pin GND, and the brightness control circuit 280 collects light emitted by The driver current of the unit.
  • the current path is interrupted to prevent current from flowing through the light emitting unit.
  • the brightness control circuit 280 receives the maximum current signal 258 from the control unit CLM and controls the amplitude of the current flowing through the light-emitting unit (from the output pin OUT to the ground pin GND).
  • the control unit CLM controls the duty cycle of the PWM dimming circuit 270 and the maximum current 258 of the brightness control circuit 280 to set the LED of the light-emitting unit to a desired brightness.
  • the driver chip 100 may also include a voltage-controlled constant current circuit (not shown in the figure), and the input reference voltage and input reference current of the voltage-controlled constant current circuit may receive power from the first power pin V1 Signal generation.
  • the voltage-controlled constant current circuit may be electrically connected to the brightness control circuit 280 .
  • a short circuit detector and an open circuit detector are provided in the modulation module.
  • the open circuit detector is composed of an operational amplifier connected in a virtual open mode and is used to detect the device unit and the driver chip 100. Whether there is a circuit break between them, the Vopen terminal can be a floating signal terminal.
  • the short circuit detector is composed of an operational amplifier connected in a virtual short manner to detect whether a short circuit occurs between the device unit and the driver chip 100 .
  • the potential of Vshort may be the same as the potential of the driving data transmitted by the second voltage line 10 .
  • the driver chip 100 further includes a data selector MUX and an analog-to-digital converter ADC.
  • the driver chip 100 forms a signal loop with the corresponding connected light-emitting unit and the second voltage line 10 through the multiple output pins OUT, it can transmit the electrical signals of the multiple signal loops to the data selector MUX, and sequentially pass the analog-to-digital signal in a time-sharing manner.
  • the converter ADC After processing by the converter ADC, it is passed to the control unit CLM, and then transmitted step by step through the relay pin Do of the driver chip 100 (for example, the electrical signals of multiple signal loops are appended to the back of the data signal 254 in accordance with the order and coding rules).
  • the external circuit can respond to the feedback information and adjust the signal level it outputs, thereby reducing the power consumption of the light-emitting substrate.
  • the driver chip 100 may also be provided with a thermal shutdown delay sensor TSD and a thermal shutdown delay (Thermal Shutdown) controller TS.
  • Thermal shutdown delay sensor TSD is used to detect the internal temperature of the driver chip 100 .
  • the thermal shutdown delay controller TS works to turn off the output of the driver chip 100 and reduce the power consumption of the driver chip 100 , thereby reducing the internal temperature of the driver chip 100 .
  • the driver chip 100 will output again.
  • the delay temperature is generally set in the range of 15 to 30°.
  • the thermal shutdown delay (Thermal Shutdown) controller TS can be connected to the data selector MUX, and can then feed back abnormal information to the control unit CLM through the data selector MUX to control the working status of the driver chip 100.
  • Figure 15 is another circuit block diagram of the driver chip in Figure 13.
  • the control unit CLM receives the test signal from the first function pin Q1, and the test signal includes the switch signal.
  • the switching signal is used to control the control unit CLM to generate test currents flowing through any output pin OUT respectively.
  • the light-emitting unit E receives the test current and emits light.
  • the control unit CLM receives the test signal through the first functional pin Q1 and sends the test signal to the second functional pin Q2.
  • the second functional pin Q2 can output the test signal to the next-level driver chip 100.
  • the control unit CLM receives the driving data from the data pin (or address pin Di), the DC voltage from the low dropout regulator 230 and the clock signal from the oscillator 240 . Depending on the working stage of the light-emitting substrate, the control unit CLM can also receive digital data from the address signal received at the address pin Di; the control unit CLM can output an enable signal 252, an incremental data signal 254, a PWM clock selection signal 256 and maximum current signal 258. The control unit CLM activates the enable signal 252 to enable the address driver 260 . The control unit CLM receives the address signal via address pin Di, stores the address and provides an incremented data signal 254 representing the outgoing address to the address driver 260 .
  • the address driver 260 buffers the incremented data signal 254 to the relay pin Do.
  • the control unit CLM may control the dimming circuit 270 to turn off the transistor 275 to effectively block the current path from the light-emitting unit.
  • Figure 16 is a flow chart of a method for detecting a light-emitting substrate according to some embodiments of the present disclosure. Some embodiments of the present disclosure provide a testing method for the light-emitting substrate 200 .
  • the light-emitting substrate 200 is the light-emitting substrate 200 of any of the above embodiments.
  • the device group O includes at least one light emitting unit E. As shown in Figure 16, the test methods include:
  • S1 Input a test signal to the first function pin of each driver chip, so that the logic control module of each driver chip generates a test current flowing through any output pin according to the test signal.
  • step S1
  • S1a Input a test signal to the first function pin Q1 of each driver chip 100, so that the logic control module of each driver chip generates a test current flowing through any output pin according to the test signal.
  • This test current can drive the light-emitting unit E in the device group O to emit light.
  • S1b Determine the light-emitting state of the device group O electrically connected to any driver chip 100.
  • the light-emitting state may include normal light-emitting, abnormal light-emitting, and no light-emitting.
  • step S1c confirm that the device group O and the corresponding driver chip 100 are connected normally. If the light-emitting unit E in the device group O emits light normally, the connection between the light-emitting unit E and the corresponding driving chip 100 is normal. It can be seen from this that the device group O/light-emitting unit E does not need to be repaired.
  • normal light emission means that the light emission brightness of the light emitting unit E reaches the threshold brightness.
  • the threshold brightness can be set specifically according to the actual situation.
  • step S1d is performed: determining that the connection between the device group O and the corresponding driver chip 100 is abnormal. If the light-emitting unit E in the device group O does not emit light or emit light abnormally, it is determined that the connection between the light-emitting unit E and the corresponding driving chip 100 is abnormal.
  • the device group O/light-emitting unit E does not emit light, it can be determined that the device group O/light-emitting unit E is disconnected from the driver chip connected to it, and the device group O/light-emitting unit E needs to be inspected and re-soldered so that it can It is connected to the driver chip normally and emits light normally.
  • device group O/light-emitting unit E emits abnormal light
  • the chip is connected normally and emits light normally.
  • abnormal light emission means that the light emission brightness of the light emitting unit E is lower than the threshold brightness.
  • the threshold brightness can be set specifically according to the actual situation.
  • a test signal is input to the first functional pin Q1 of each driver chip 100, so that the lighting test of the light-emitting unit E electrically connected to each driver chip 100 can be realized through a one-step detection operation, which is beneficial to improving the performance of the driver chip 100. Maintenance efficiency.
  • FIG. 17 is a flow chart of a method for detecting a light-emitting substrate according to further embodiments of the present disclosure.
  • S1Aa Input switching signals to the first function pins of each driver chip.
  • the switch signal is used to control the logic control module to generate a test current flowing through any output pin respectively, so that the logic control module of each driver chip generates a test current flowing through any output pin respectively according to the test signal.
  • S1Ab Determine the light-emitting state of the device group O electrically connected to any driver chip 100.
  • step S1Ac confirm that the device group O and the corresponding driver chip 100 are connected normally. If the light-emitting unit E in the device group O emits light normally, the connection between the light-emitting unit E and the corresponding driving chip 100 is normal. It can be seen from this that the device group O/light-emitting unit E does not need to be repaired.
  • step S1Ad is performed: it is determined that the connection between the device group O and the corresponding driver chip 100 is abnormal. If the light-emitting unit E in the device group O does not emit light or emit light abnormally, it is determined that the connection between the light-emitting unit E and the corresponding driving chip 100 is abnormal.
  • the test signal is input to the first function pin Q1 of each driver chip 100, so that the lighting test of the light-emitting unit E electrically connected to each driver chip 100 can be realized through a one-step detection operation, which is beneficial to improving the performance of the driver chip 100. Maintenance efficiency.
  • the test signal includes a switching signal.
  • the switch line number is used to control the logic control module CTR to generate test current flowing through any output pin OUT respectively. That is, all the light-emitting units E electrically connected to the driving chip 100 can be controlled to receive the test current. And because the second functional pin Q2 is directly connected to the first functional pin Q1 of this level of driver chip and the next level of driver chip, each level of driver chip 100 can receive the same test signal. Therefore, the lighting test of the light-emitting units E electrically connected to each driving chip 100 can be implemented through a one-step detection operation.
  • the test signal may be a high level signal or a low level signal. As long as the test signal can be used to control the logic control module CTR to generate test currents flowing through any output pin OUT respectively.
  • FIG. 18 is a flow chart of a method for detecting a light-emitting substrate according to further embodiments of the present disclosure.
  • test method also includes:
  • the drive data includes address verification information and multiple drive information corresponding to the multiple cascaded drive chips.
  • the driver chip configures a driver information corresponding to the current driver chip according to the address verification information. And based on the driving information, the driving current corresponding to the device group connected to the driving chip is generated. And, the driver chip updates the address verification information, generates driver data including the updated address verification information, and outputs the driver data including the updated address verification information to the next-level driver chip. Determine whether there is a device group that does not emit light among the device groups connected to multiple cascaded driver chips. If so, according to the cascade sequence, it is determined that there is an abnormality in the driver chip connected to the first device group that does not emit light. If not, it is determined that there is no abnormality in the multiple cascaded driver chips.
  • step S01
  • S01a Input drive data to the address pin Di of the first driver chip among the multiple cascaded drive chips 100.
  • the drive data includes address verification information and multiple drive information corresponding to the multiple cascaded drive chips.
  • the driver chip 100 configures a driver information corresponding to the current driver chip 100 according to the address verification information. And based on the driving information, a driving current corresponding to the device group O connected to the driving chip 100 is generated. And, the driver chip 100 updates the address verification information, generates driver data including the updated address verification information, and outputs the driver data including the updated address verification information to the next-level driver chip 100 .
  • S01b Determine whether there is a device group O that does not emit light among the device groups O connected to the plurality of cascaded driver chips 100.
  • step S01c determine that there is no abnormality in the multiple cascaded driver chips 100 . There is no need to overhaul the driver chip 100 .
  • step S01d is performed: according to the cascade sequence, it is determined that the driver chip 100 connected to the first device group O that does not emit light has an abnormality. It is necessary to inspect the address pin Di and the relay pin Do of the driver chip 100 to determine whether they are welded normally. After repair, the device group O connected to the driver chip 100 is allowed to emit light normally.
  • step S01 may be continued to determine whether there is an abnormality in the remaining driver chips 100 . Until all device groups O connected to the driver chip 100 can emit light normally.
  • step S01a can be used to drive the light-emitting substrate 200 to emit light normally.
  • the testing method may include the above-mentioned S1A step and S01 step.
  • the S1A step is used to test the light-emitting element O connected to the driver chip 100
  • the S01 step is used to detect the cascade status of multiple driver chips 100, which is beneficial to improving the maintenance efficiency of the light-emitting substrate 200.
  • step S01 may be performed first, followed by step S1A.
  • the test method can perform the SA1 step first and then the S01 step. This disclosure does not limit this.
  • FIG. 19 is a flow chart of a method for detecting a light-emitting substrate according to further embodiments of the present disclosure.
  • S1Ba Input test signals including test data and first general address information to the first function pins of each driver chip.
  • the first general address information can match the initialization address information of any driver chip. So that the logic control module of each driver chip generates a test current flowing through any output pin respectively according to the test signal.
  • S1Bb Determine the light-emitting state of the device group O electrically connected to any driver chip 100.
  • step S1Bc confirm that the device group O and the corresponding driver chip 100 are connected normally. If the light-emitting unit E in the device group O emits light normally, the connection between the light-emitting unit E and the corresponding driving chip 100 is normal. It can be seen from this that the device group O/light-emitting unit E does not need to be repaired.
  • step S1Bd is performed: determining that the connection between the device group O and the corresponding driver chip 100 is abnormal. If the light-emitting unit E in the device group O does not emit light or emit light abnormally, it is determined that the connection between the light-emitting unit E and the corresponding driving chip 100 is abnormal.
  • a test signal is input to the first functional pin Q1 of each driver chip 100, so that the lighting test of the light-emitting unit E electrically connected to each driver chip 100 can be realized through a one-step detection operation, which is beneficial to improving the performance of the driver chip 100. Maintenance efficiency.
  • the test signal includes test data and first universal address information.
  • the first universal address information can match the initialization address information of any driver chip 100 to generate a test current flowing through any output pin OUT respectively.
  • the light-emitting unit E receives the test current and emits light. Since the first universal address information can match the initialization address information of any driver chip, that is, the test signal can simultaneously drive the light-emitting units E electrically connected to each driver chip 100 to emit light. If the light-emitting unit E does not emit light, it can be determined that there is a problem with the light-emitting unit E. Therefore, the lighting test of the light-emitting units E electrically connected to each drive chip 100 can be implemented through a one-step detection operation, thereby effectively improving the maintenance efficiency of the drive chips 100 .
  • FIG. 20 is a flow chart of a method for detecting a light-emitting substrate according to further embodiments of the present disclosure.
  • test method also includes:
  • S10A Input an address signal to the address pin of the first driver chip among multiple cascaded driver chips.
  • the driver chip configures the address information of the driver chip according to the address signal and generates a relay signal.
  • the relay pin outputs the relay signal to the next-level driver chip.
  • the relay signal is the same as the address signal. That is, the updated address information is the same (the updated address information is the same as the initialization information).
  • the address signal may be a digital signal.
  • a driver chip 100 When a driver chip 100 receives an address signal, it can parse, obtain and store the address signal in the address signal, and can also modulate the address signal (new address signal) by incrementing the address signal by 0 into a relay signal.
  • the relay signal as the address signal of the next-level driver chip 100. Make the relay signal the same as the address signal.
  • the driver chip 100 can also use other different functions to generate new address signals.
  • Step S1B1 may also be included after step S10A.
  • step S1B1 is used to determine whether there is an abnormality in multiple driver chips 100 arranged in cascade.
  • S1B1 includes:
  • S1B1a Input a test signal including test data and second general address information to the first function pin of each driver chip.
  • the second general address information can match the updated address information of any driver chip (the updated address information of the initialization information). So that the logic control module of each driver chip generates a test current flowing through any output pin respectively according to the test signal.
  • S1B1b Determine whether there is a device group that does not emit light among the device groups connected to multiple cascaded driver chips.
  • step S1B1c confirm that there are no abnormalities in multiple cascaded driver chips. Then the address pin Di and the relay pin Do in the driver chip 100 connected to the light-emitting unit E are welded normally. It can be seen from this that the driver chip 100 does not need to be repaired.
  • step S1B1d according to the cascading sequence, determine that the driver chip connected to the first non-luminous device group is abnormal. That is, the address pin Di and the relay pin Do in the driver chip 100 are welded abnormally. It can be seen from this that the driver chip 100 needs to be repaired.
  • the testing method includes step S1B and steps S10A and S1B1.
  • Each driver chip 100 will have initialized address information set when it leaves the factory.
  • the first general address information in the test signal matches the initialization address information in any driver chip 100, so that the logic control module of each driver chip 100 generates a test current flowing through any output pin OUT respectively.
  • Device group O receives the test current and emits light. According to whether the light-emitting unit E in the device group O emits light, it is determined whether the light-emitting unit E is welded normally. Then use step S10A to update the initialized address information to obtain updated address information, which is the same.
  • the second universal address information in the test signal in step S1B1 can match the updated address information of any driver chip, so that the logic control module of each driver chip 100 generates signals that flow through any output respectively.
  • the test current of pin OUT, device group O receives the test current and emits light. If no light is emitted starting from a certain device group O, it can be known that the initialization address information in the driver chip 100 connected to the non-light device group O has not been updated to the address information matching the second general address information. Therefore, the driver There is an abnormality in the chip 100, that is, the address pin Di and the relay pin Do in the driver chip 100 for receiving the updated address information may have a welding abnormality problem. Recording the coordinates of the abnormal light-emitting unit E in step S1B and the coordinates of the abnormal driving chip 100 in step S1B1 are performed simultaneously for maintenance, which is beneficial to improving the maintenance efficiency of the light-emitting substrate 200 .
  • FIG. 21 is a flow chart of a method for detecting a light-emitting substrate according to yet another embodiment of the present disclosure.
  • the first functional pin Q1 of the driver chip 100 receives the test signal and the driver data in a time-sharing manner.
  • the test method also includes:
  • S10B Input an address signal to the address pin of the first driver chip among multiple cascaded driver chips.
  • the driver chip configures the address information of the driver chip according to the address signal and generates a relay signal.
  • the relay pin points downward.
  • the stage driver chip outputs the relay signal. Among them, the relay signal is different from the address signal.
  • step S10B address signals are input to the address pins Di of multiple cascaded driver chips 100.
  • the driver chip 100 configures the address information of the driver chip 100 according to the address signals and generates relay signals.
  • the relay pins Do can send signals to The next-level driver chip 100 outputs the relay signal.
  • step S01 addresses are written to each driver chip 100. Among them, the relay signal is different from the address signal.
  • the address signal may be a digital signal.
  • a driver chip 100 When a driver chip 100 receives an address signal, it can parse, obtain and store the address signal in the address signal, and can also increment the address signal by 1 or another non-zero fixed amount and generate the incremented address signal (new address signal). ) is modulated into a relay signal, and the relay signal serves as the address signal of the next-level driver chip 100. Make the relay signal different from the address signal.
  • the driver chip 100 can also use other different functions to generate new address signals.
  • S11 Input driving data to the first function pin of each driver chip in multiple cascaded driver chips.
  • the driver data includes multiple address verification information and multiple drive information corresponding to the multiple address verification information; for any Driver chip: When the address verification information matches the address information of the driver chip, the logic control module receives the corresponding drive information based on the address verification information, and generates a drive current corresponding to at least one output pin based on the received drive information. Determine whether there is a device group that does not emit light among the device groups connected to multiple cascaded driver chips. If so, according to the cascade sequence, it is determined that there is an abnormality in the driver chip connected to the first device group that does not emit light. If not, it is determined that there is no abnormality in the multiple cascaded driver chips.
  • step S11
  • S11a Input drive data to the first function pin of each drive chip in multiple cascaded drive chips.
  • the drive data includes multiple address verification information and multiple drive information corresponding to the multiple address verification information; for any Driver chip 100: When the address verification information matches the address information of the driver chip 100, the logic control module receives the corresponding driver information based on the address verification information, and generates a signal corresponding to at least one output pin OUT based on the received driver information. drive current.
  • S11b Determine whether there is a device group O that does not emit light among the device groups O connected to the plurality of cascaded driver chips 100 .
  • step S11c determine that there is no abnormality in the multiple cascaded driver chips 100. There is no need to overhaul the driver chip 100 .
  • step S11d according to the cascade sequence, determine that the driver chip 100 connected to the first device group O that does not emit light has an abnormality. It is necessary to inspect the address pin Di and the relay pin Do of the driver chip 100 to determine whether they are welded normally. After repair, the device group O connected to the driver chip 100 is allowed to emit light normally.
  • step S11 may be continued to determine whether there is an abnormality in the remaining driver chips 100 . Until all device groups O connected to the driver chip 100 can emit light normally.
  • steps S10B and S11a can be used to drive the light-emitting substrate 200 to emit light normally.
  • the testing method may include the above-mentioned steps S1B, S10B and S11. Using step S1B to test the light-emitting element O connected to the driver chip 100, and using steps S10B and S11 to detect the cascade status of multiple driver chips 100 will help further improve the maintenance efficiency of the light-emitting substrate 200.
  • test method can first perform step S1B, and then perform steps S10B and S11.
  • some embodiments of the present disclosure provide a driver chip 100, a light-emitting substrate 200 and a display device 300, and also provide a method for detecting a light-emitting substrate by optimizing the structure of the driver chip 100, including, for example, the first functional pin. Q1 and second function pin Q2.
  • a test signal is input to the first function pin Q1 of each driver chip 100 .
  • a test current is generated that flows through any output pin OUT respectively.
  • the first function pin Q1 and the second function pin Q2 are electrically connected.
  • the second function pin Q2 can output a test signal to the next-level driver chip 100 .
  • the lighting test of the light-emitting units E electrically connected to each driving chip 100 can be implemented through a one-step detection operation. If the light-emitting unit E does not emit light, it can be determined that there is a problem with the light-emitting unit E, which effectively improves the maintenance efficiency of the driving chip 100 .
  • the light-emitting substrate 200 with the driving chip 100, the display device 300 with the light-emitting substrate 200, and the detection method of the driving chip 100 all have the beneficial effects of the driving chip 100 in any of the above embodiments, and will not be described again here.

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Abstract

公开了一种驱动芯片。驱动芯片包括逻辑控制模块、至少一个输出引脚和第一功能引脚。至少一个输出引脚与逻辑控制模块电连接。第一功能引脚与逻辑控制模块电连接。第一功能引脚能够接收测试信号。逻辑控制模块被配置为：根据测试信号，产生分别流经任一输出引脚的测试电流。

Description

驱动芯片、发光基板及其测试方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种驱动芯片、发光基板及其测试方法、显示装置。
背景技术
显示装置可以用于显示画面。随着显示技术的飞速发展，显示装置已经逐渐遍及在人们的生活中。
发明内容
一方面，提供一种驱动芯片。所述驱动芯片包括逻辑控制模块、至少一个输出引脚和第一功能引脚。至少一个输出引脚与所述逻辑控制模块电连接。第一功能引脚与所述逻辑控制模块电连接。所述第一功能引脚能够接收测试信号。所述逻辑控制模块被配置为：根据所述测试信号，产生分别流经任一所述输出引脚的测试电流。
在一些实施例中，所述测试信号包括开关信号。所述开关信号用于控制所述逻辑控制模块，产生分别流经任一所述输出引脚的测试电流。
在一些实施例中，所述驱动芯片还包括地址引脚和中继引脚。所述地址引脚与所述逻辑控制模块电连接。所述地址引脚能够接收驱动数据；所述驱动数据包括地址校验信息以及与多个级联的驱动芯片对应的多个驱动信息。所述逻辑控制模块被配置为：根据所述地址校验信息，配置与当前的所述驱动芯片对应的一个驱动信息；以及，对所述地址校验信息进行更新，生成包含更新后的地址校验信息的驱动数据。所述中继引脚与所述逻辑控制模块电连接。所述中继引脚能够输出所述包含更新后的地址校验信息的驱动数据。
在一些实施例中，所述测试信号包括测试数据和通用地址信息，所述通用地址信息能够匹配任意一个所述驱动芯片的初始化地址信息。所述逻辑控制模块被配置为：根据所述测试数据，产生分别流经任一所述输出引脚的测试电流。
在一些实施例中，所述驱动芯片还包括地址引脚和中继引脚。所述地址引脚与所述逻辑控制模块电连接。所述地址引脚能够接收地址信号。所述逻辑控制模块被配置为：根据所述地址信号配置所述驱动芯片的地址信息，并生成中继信号。所述中继引脚与所述逻辑控制模块电连接。所述中继引脚能够输出所述中继信号。所述第一功能引脚还能够接收驱动数据。所述驱动数据包括多个地址验证信息以及与多个地址验证信息对应的多个驱动信息。所 述逻辑控制模块被配置为：当所述地址验证信息和所述驱动芯片的地址信息匹配时，根据所述地址验证信息，接收对应的驱动信息，并根据所接收的驱动信息，生成与所述至少一个输出引脚对应的驱动电流。
在一些实施例中，所述驱动芯片还包括第二功能引脚和第一连接线。所述第二功能引脚通过所述第一连接线与所述第一功能引脚相连。所述第二功能引脚能够输出测试信号。所述驱动芯片具有相互平行的第一边缘和第二边缘。所述第一功能引脚和所述第二功能引脚中，一个靠近所述第一边缘，另一个靠近所述第二边缘。
在一些实施例中，所述驱动芯片还具有位于所述第一边缘的第一端与所述第二边缘的第一端之间的第三边缘。在所述驱动芯片包括地址引脚和中继引脚的情形下：所述地址引脚和所述中继引脚中，一个靠近所述第一边缘，另一个靠近所述第二边缘。所述地址引脚和所述中继引脚，相对于所述第一功能引脚和所述第二功能引脚，更靠近所述第三边缘。
在一些实施例中，所述驱动芯片还包括至少一个接地引脚。至少一个接地引脚，与所述逻辑控制模块电连接。所述接地引脚能够接收接地信号。所述接地引脚位于地址引脚和所述中继引脚之间。
在一些实施例中，所述驱动芯片还包括第一电源引脚。第一电源引脚与所述逻辑控制模块电连接。所述第一电源引脚能够接收电源信号。第一电源引脚靠近所述第一边缘或所述第二边缘。
在一些实施例中，所述驱动芯片还包括第二电源引脚和第二连接线。所述第二电源引脚通过所述第二连接线与所述第一电源引脚相连。所述第二电源引脚能够输出所述电源信号。其中，所述第一电源引脚和所述第二电源引脚中，一个靠近所述第一边缘，另一个靠近所述第二边缘。所述第一电源引脚和所述第二电源引脚，相对于所述地址引脚和所述中继引脚，更远离所述第三边缘。
在一些实施例中，所述驱动芯片还具有位于所述第一边缘的第二端与所述第二边缘的第二端之间的第四边缘。所述输出引脚的数量为多个，多个所述输出引脚靠近所述第四边缘，且多个所述输出引脚沿所述第四边缘的延伸方向排列。
另一方面，提供一种发光基板。所述发光基板包括多个级联的驱动芯片和多个器件组。所述驱动芯片为上述任一实施例所述的驱动芯片。一个器件组的第一端与一个驱动芯片的至少一个输出引脚对应电连接。
在一些实施例中，在所述驱动芯片还包括地址引脚、中继引脚、第一电 源引脚和至少一个接地引脚的情形下：位于上一级的所述驱动芯片的中继引脚与位于下一级的驱动芯片的地址引脚电连接。所述发光基板还包括导电层。所述导电层中包括第二电压线、地址信号线、第一电压线、测试信号线和接地线。第二电压线与各个所述器件组的第二端电连接。地址信号线与第一个所述驱动芯片的地址引脚电连接。第一电压线与第一个所述驱动芯片的第一电源引脚电连接。测试信号线与第一个所述驱动芯片的第一功能引脚电连接。接地线与各个所述驱动芯片的至少一个接地引脚电连接。其中，所述第二电压线、所述地址信号线、所述第一电压线、所述测试信号线以及接地线之间无交叠。
在一些实施例中，在所述驱动芯片还包括第二功能引脚的情况下：所述第二功能引脚分别与本级的所述驱动芯片的第一功能引脚，和下一级的所述驱动芯片的第一功能引脚电连接。
在一些实施例中，在所述驱动芯片还包括第二电源引脚的情形下：所述第二电源引脚分别与本级的所述驱动芯片的第一电源引脚，和下一级的所述驱动芯片的第一电源引脚电连接。
在一些实施例中，所述地址信号线被配置为传输地址信号，所述测试信号线被配置为分时传输测试信号和驱动数据；或，所述地址信号线被配置为传输驱动数据，所述测试信号线被配置为传输测试信号。
又一方面，提供一种发光基板的测试方法。所述发光基板为上述任一实施例所述的发光基板。所述测试方法包括：向各个驱动芯片的第一功能引脚输入测试信号；以使各个所述驱动芯片根据所述测试信号，产生分别流经任一输出引脚的测试电流。判断与任一所述驱动芯片电连接的器件组的发光状态；若正常发光，则确定该器件组与对应的驱动芯片连接正常；若不发光或异常发光，则确定该器件组与对应的驱动芯片连接异常。
在一些实施例中，所述向各个驱动芯片的第一功能引脚输入测试信号包括：向各个驱动芯片的第一功能引脚输入开关信号，所述开关信号用于控制所述逻辑控制模块产生分别流经任一输出引脚的测试电流的。
在一些实施例中，所述测试方法还包括：向多个级联的驱动芯片中的第一个驱动芯片的地址引脚输入驱动数据，驱动数据包括地址校验信息以及与多个级联的驱动芯片对应的多个驱动信息。其中，驱动芯片根据地址校验信息，配置与当前的驱动芯片对应的一个驱动信息。并根据驱动信息，生成与驱动芯片连接的器件组所对应的驱动电流。以及，驱动芯片对所述地址校验信息进行更新，生成包含更新后的地址校验信息的驱动数据，并向下一级驱 动芯片输出所述包含更新后的地址校验信息的驱动数据。判断与多个级联的驱动芯片的连接的器件组中，是否存在不发光的器件组。若是，则按照级联顺序，确定与第一个不发光的器件组连接的驱动芯片存在异常。若否，则确定所述多个级联的驱动芯片不存在异常。
在一些实施例中，所述向各个驱动芯片的第一功能引脚输入测试信号，包括：向各个驱动芯片的第一功能引脚输入包括测试数据和第一通用地址信息的测试信号。所述第一通用地址信息能够匹配任意一个所述驱动芯片的初始化地址信息。
在一些实施例中，所述测试方法还包括：向多个级联的驱动芯片中的第一个驱动芯片的地址引脚输入地址信号。所述驱动芯片根据地址信号配置驱动芯片的地址信息，并生成中继信号。其中，所述中继信号与所述地址信号相同。所述测试方法还包括：向各个驱动芯片的第一功能引脚输入包括测试数据和第二通用地址信息的测试信号。所述第二通用地址信息能够匹配任意一个所述驱动芯片更新后的地址信息。判断与多个级联的驱动芯片的连接的器件组中，是否存在不发光的器件组。若是，则按照级联顺序，确定与第一个不发光的器件组连接的驱动芯片存在异常；若否，则确定所述多个级联的驱动芯片不存在异常。
在一些实施例中，所述测试方法还包括：向多个级联的驱动芯片中的第一个驱动芯片的地址引脚输入地址信号，所述驱动芯片根据地址信号配置驱动芯片的地址信息，并生成中继信号。向多个级联的驱动芯片中的各个驱动芯片的第一功能引脚输入驱动数据，驱动数据包括多个地址验证信息以及与多个地址验证信息对应的多个驱动信息；对于任一个所述驱动芯片：当所述地址验证信息和所述驱动芯片的地址信息匹配时，所述逻辑控制模块根据所述地址验证信息，接收对应的驱动信息，并根据所接收的驱动信息，生成与所述至少一个输出引脚对应的驱动电流。判断与多个级联的驱动芯片的连接的器件组中，是否存在不发光的器件组。若是，则按照级联顺序，确定与第一个不发光的器件组连接的驱动芯片存在异常。若否，则确定所述多个级联的驱动芯片不存在异常。
又一方面，提供一种显示装置。所述显示装置包括：如上述任一实施例所述的发光基板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图 仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为本公开的一些实施例提供的一种显示装置的结构图；
图2为本公开的一些实施例提供的一种发光基板的结构图；
图3为本公开的一些实施例提供的一种驱动芯片的结构图；
图4为一些实现方式中的一种驱动芯片的结构图；
图5为本公开的一些实施例提供的两个驱动芯片相互连接的示意图；
图6为本公开一些实施例提供的一种驱动数据的数据格式示意图；
图7为本公开一些实施例提供的又一种驱动数据的数据格式示意图；
图8为本公开的再一些实施例提供的一种驱动芯片的结构图；
图9为本公开的又一些实施例提供的一种驱动芯片的结构图；
图10为本公开又的一些实施例提供的一种驱动芯片的结构图；
图11为本公开的再一些实施例提供的一种发光基板的结构图；
图12为图11中R位置处的一种局部放大图；
图13为本公开的又一些实施例提供的一种发光基板的电路框图；
图14为图13中驱动芯片的一种电路框图；
图15为图13中驱动芯片的又一种电路框图；
图16为本公开的一些实施例提供的一种发光基板的检测方法的流程图；
图17为本公开的再一些实施例提供的一种发光基板的检测方法的流程图；
图18为本公开的又一些实施例提供的一种发光基板的检测方法的流程图；
图19为本公开的又一些实施例提供的一种发光基板的检测方法的流程图；
图20为本公开的又一些实施例提供的一种发光基板的检测方法的流程图；
图21为本公开的又一些实施例提供的一种发光基板的检测方法的流程图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实 施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。
本文中“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“平行”、“垂直”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间 存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
图1为本公开的一些实施例提供的一种显示装置的结构图。请参阅图1所示，本公开的一些实施例提供了一种显示装置300，该显示装置300包括发光基板200。
示例性的，显示装置300可以为液晶显示装置(Liquid Crystal Display，简称LCD)、Mini LED(Mini Light-Emitting Diode，简称Mini LED)显示装置和Micro LED(Micro Light-Emitting Diode，简称Micro LED)显示装置。
在显示装置300为液晶显示装置的情况下，在一些实施例中，显示装置300包括盖板玻璃、液晶显示面板以及背光组件。背光组件用于为液晶显示面板提供光源。其中，背光组件包括发光基板200，发光基板200为液晶显示面板提供光线，从而液晶显示面板可以进行画面显示。在一些示例中，显示装置300中的背光模组还可以包括光学膜片，光学膜片位于发光基板200靠近液晶显示面板的一侧。光学膜片可以包括反射片、扩散板、增亮膜(棱镜片)、扩散片等，可以用于提高光线的亮度和均匀性。
在显示装置300为Mini LED显示装置和Micro LED显示装置的情况下，在一些实施例中，显示装置300包括发光基板200，发光基板200可以实现画面显示。在一些示例中，显示装置300还可以包括减反射膜层和保护盖板，减反射膜层位于发光基板200和保护盖板之间。减反射膜层包括偏光片，偏光片可以为圆偏光片。此处，偏光片可以减少外界光发射，防止发光基板200反射环境光从而产生刺眼效果。
示例性的，上述显示装置300可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何显示装置。更明确地说，预期所述实施例的显示装置可实施应用在多种电子中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平 板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
图2为本公开的一些实施例提供的一种发光基板的结构图。
本公开一些实施例中提供了一种发光基板200。请参阅图2所示，发光基板200包括多个级联的驱动芯片100和与每个驱动芯片分别连接的多个器件组O。
在一些示例中，一个器件组O包括至少一个发光单元E。示例性的，一个发光单元E可以包括至少一个发光元件。其中，一个发光单元E可以仅包括一个发光元件。或者，一个发光单元E可以包括两个或两个以上相互电连接的发光元件。当一个发光单元E包括两个或两个以上发光元件时，两个或两个以上发光元件可以相互串联，也可以相互并联，还可以是串联并联混合的连接方式。
示例性的，发光元件可以为发光二极管(Light-Emitting Diode，简称LED)、微型发光二极管(Micro Light-Emitting Diode，简称Micro LED)、迷你发光二极管(Mini Light-Emitting Diode，简称Mini LED)、有机电致发光二极管(Organic Light-Emitting Diode，简称OLED)量子点发光二极管(Quantum Dot Light-Emitting Diode，简称QLED)等。在该实施例中，发光单元E可以在驱动芯片100的驱动下发光，进而可以应用于显示装置、照明装置等设备中。
在显示装置300为液晶显示装置的情况下，在一些示例中，发光基板200为显示装置300的背光源，用于为液晶显示装置提供光源。各个器件组O可以受驱动芯片100的控制，器件组O中的各个发光单元E可以被独立控制；如此，该显示装置可以实现局域调光(Local Dimming)，实现高动态范围图像(High-Dynamic Range，简称HDR)效果，提高显示装置300的显示质量。在任意一个器件组O中，发光单元E的数量和电连接方式均相同。在任意一个发光单元E中，发光元件的数量和电连接方式均相同。如此，可以保证发光单元E在发光基板上分布的均一性，利于提高发光基板发光的均一性，降低背光模组调试的难度。
在显示装置为Mini LED显示装置或Micro LED显示装置的情况下，在一些示例中，发光单元E(例如Micro LED、Mini LED等)可以发光以直接显示图案。示例性的，发光单元E可以为能够发出相同颜色光线的发光元件，例如可以均为蓝色LED、红色LED、绿色LED或者黄色LED。如此，该显 示装置可以为单色的显示装置，其可以为仪器表盘、信号指示屏等显示装置。示例性的，发光单元E可以包括多种不同颜色的发光元件，例如可以包括红色LED、绿色LED、蓝色LED、黄色LED等中的至少两种，且不同颜色的发光单元E可以被各自独立控制。如此，该显示装置可以通过混光而进行彩色显示。
在本公开的一种实施方式中，发光基板200上的多个器件组O按照行方向和列方向等间距阵列分布。示例的，各个器件组O可以排列成多个器件组行，各个器件组行沿列方向等间距排列，且每个器件组行包括沿行方向等间距排列的多个发光单元E。各个发光单元E还可以排列成多个元件列，各个元件列沿行方向等间距排列，且每个元件列包括沿列方向等间距排列的多个功能元件。如此，可以提高器件组O在发光基板200上分布的均一性。
图3为本公开的一些实施例提供的一种驱动芯片的结构图。
本公开一些实施例中提供了一种驱动芯片100。请参阅图3所示，驱动芯片100包括逻辑控制模块CTR、至少一个输出引脚OUT和第一功能引脚Q1。
至少一个输出引脚OUT与逻辑控制模块CTR电连接。本公开的一种实施方式中，请参阅图3所示，图3以驱动芯片100包括4个输出引脚OUT为例进行示意。由于驱动芯片100包括4个输出引脚OUT，每个输出引脚OUT连接发光单元E(如图2所示)，所以一个驱动芯片100可以驱动至少4个发光单元E。相较于一个驱动芯片驱动一个发光单元E的方案，可以使得驱动芯片100的数量减少至1/4，大大降驱动芯片100的用量，进而降低发光基板200的成本。
需要说明的是，尽管本公开一些实施例的驱动芯片100相较于仅设置一个输出引脚的驱动芯片的体积略大，但是由于本实施例可以大幅度减小发光基板200中驱动芯片100的数量，进而可以降低全部驱动芯片100在发光基板200中的面积占比。也可以有利于提高驱动芯片100的绑定效率，有利于提升发光基板200的良率。
示例性的，本公开一些实施例的驱动芯片100具有4个输出引脚OUT，其面积为仅具有1个输出引脚OUT的驱动芯片的两倍；然而，本实施例中的发光基板200中驱动芯片100的数量可以减少至1/4，进而使得本实施例中的发光基板200中驱动芯片100的面积占比降低至1/2(相对于1个驱动芯片驱动一个发光单元E的发光基板200)。
可以理解的是，在另一些实施例中，驱动芯片100可以包括3个输出引脚OUT、5个输出引脚OUT或6个输出引脚OUT。其中，一个驱动芯片100 包括4个输出引脚OUT的方案，相对于一个驱动芯片100包括3个输出引脚OUT的方案，更有利于降低驱动芯片100的面积占比，节约资源。一个驱动芯片100包括4个输出引脚OUT的方案，相对于一个驱动芯片100包括5个输出引脚OUT或6个输出引脚OUT的方案，虽然输出引脚OUT的数量相对较少，但是可以防止驱动芯片100工作时产生的热量较大，有利于提高驱动芯片100的使用寿命。
第一功能引脚Q1与逻辑控制模块CTR电连接。第一功能引脚Q1能够接收测试信号。逻辑控制模块CTR被配置为：根据测试信号，产生分别流经任一输出引脚OUT的测试电流。
本实施例中的驱动芯片100，可以利用第一功能引脚Q1提供测试信号至逻辑控制模块CTR，逻辑控制模块CTR根据测试信号，产生分别流经任一输出引脚OUT的测试电流。该测试电流可以驱动发光单元E发光。通过为各个驱动芯片100的第一功能引脚Q1提供测试信号，就可以实现通过一步检测操作对各个驱动芯片100电连接的发光单元E的点亮测试。如发光单元E正常发光，则可判定该发光单元E连接正常，如发光单元E未发光，则可判定该发光单元E存在问题(例如短路、断路等不良)，需进行返修，提高驱动芯片100的检修效率。
在一些示例中，流经任一输出引脚OUT的测试电流均可以相同。可以理解的是，在另一些示例中，各个输出引脚OUT流经的电流可以均不相同。或者，部分相同。本公开对此不做限定。
图4为一些实现方式中的一种驱动芯片的结构图。
值得指出的是：在一些可实现的方式中，请参阅图4所示，驱动芯片包括输出引脚OUT、地址引脚Di、中继引脚Do、数据引脚Data、接地引脚GND、电源引脚V。利用地址引脚Di接收地址信号，根据地址信号配置驱动芯片的地址信息，并生成中继信号；中继信号能够作为下一级驱动芯片的地址信号。数据引脚Data用于接收驱动数据，驱动数据包括驱动信息和地址验证信息，当地址验证信息与地址信息匹配时，根据驱动信息，生成与驱动芯片连接的至少一个发光单元所对应的驱动电流，并控制驱动芯片的一个输出引脚与对应的发光单元形成电气通路，驱动电流在该电气通路中流动。
由于地址信号需要转换为中继信号发送至下一级驱动芯片，当某个驱动芯片的引脚焊接不良，前部分的驱动芯片正常驱动发光单元，该部分驱动芯片电连接的发光单元如未发光，则可判定该发光单元E存在问题，需进行返修。而引脚焊接不良的驱动芯片后续级联的驱动芯片，由于均无法接收到中 继信号，也即该部分驱动芯片无法提供驱动电流，对应电连接的发光单元均无法实现发光。但是，该部分由此无法判定该部分的驱动芯片电连接的发光单元是否连接正常。需要一级一级不断的重复测试点亮进行判断，导致驱动芯片的检修效率较低。
而本公开的一些实施例提供的一种驱动芯片100，设有第一功能引脚Q1和第二功能引脚Q2。第一功能引脚Q1可以接收测试信号，并将测试信号发送至逻辑控制模块CTR。逻辑控制模块CTR根据测试信号，产生分别流经任一输出引脚OUT的测试电流。该测试电流可以驱动发光单元E发光。第二功能引脚Q2与第一功能引脚Q1电连接。第二功能引脚Q2能够向下一级驱动芯片100输出测试信号。可以通过一步检测操作实现对各个驱动芯片100电连接的发光单元E的点亮测试。如发光单元E未发光，则可判定该发光单元E存在问题，无需不断重复进行写入地址、输入驱动数据，返修这三个阶段直至判定出全部发光单元是否需要检修，有效的提高驱动芯片100的检修效率。
在一些实施例中，请继续参阅图3所示，驱动芯片100具有相互平行的第一边缘W1和第二边缘W2。驱动芯片100还具有位于第一边缘W1的第二端与第二边缘W2的第二端之间的第四边缘W4。输出引脚OUT的数量为多个，多个输出引脚OUT靠近第四边缘W4，且多个输出引脚OUT沿第四边缘W4的延伸方向排列。
本实施例中，驱动芯片100包括多个输出引脚OUT，多个输出引脚OUT靠近第四边缘，且多个输出引脚OUT沿第四边缘W4的延伸方向排列。便于多个输出引脚OUT与驱动芯片100外部的同一条第二电压线电连接，避免驱动芯片100连接的各个信号线之间交叠，有利于发光基板的走线布局。
示例性的，图3以第四边缘W4的一端与第一边缘W1直接相连接，第四边缘W4的另一端与第二边缘W2直接相连接为例进行示意。可以理解的是，在另一些实施例中，第四边缘W4和第一边缘W1通过其他边缘进行连接。在又一些实施例中，第四边缘W4和第二边缘W2通过其他边缘进行连接。
图5为本公开的一些实施例提供的两个驱动芯片相互连接的示意图。
在一些实施例中，请参阅图5所示，驱动芯片100还包括第二功能引脚Q2。第二功能引脚Q2与第一功能引脚Q1电连接。第二功能引脚Q2能够向下一级驱动芯片100输出测试信号。
如上结构，利用第一功能引脚Q1提供测试信号至逻辑控制模块CTR，逻辑控制模块CTR根据测试信号，产生分别流经任一输出引脚OUT的测试电流。该测试电流可以驱动发光单元E发光。再利用第二功能引脚Q2向下一 级驱动芯片100的第一功能引脚Q1输出测试信号，由此，可以通过一步检测操作实现对各个驱动芯片100电连接的发光单元E的点亮测试。如发光单元E正常发光，则可判定该发光单元E连接正常，如发光单元E未发光，则可判定该发光单元E存在问题(例如短路、断路等不良)，需进行返修，提高驱动芯片100的检修效率。
第二功能引脚Q2与第一功能引脚Q1电连接。第二功能引脚Q2与第一功能引脚Q1接收相同的信号。进而，可以通过第二功能引脚Q2向下一级驱动芯片100的第一功能引脚Q1输出测试信号。便于相互级联设计的驱动芯片100之间的布线设计。
此外，可以根据驱动芯片100中引脚的总数量，确实是否需要设置第二功能引脚Q2，以保证驱动芯片100中引脚的总数量为偶数。
在一些实施例中，继续参阅图5所示，驱动芯片100包括第一功能引脚Q1和第二功能引脚Q2。第一功能引脚Q1和第二功能引脚Q2分别位于驱动芯片100的两个相对平行的侧边，且第一功能引脚Q1和第二功能引脚Q2相互电连接。
第一功能引脚Q1可以接收测试信号，并将测试信号发送至逻辑控制模块CTR。逻辑控制模块CTR根据测试信号，产生分别流经任一输出引脚OUT的测试电流。该测试电流可以驱动发光单元E发光。
第二功能引脚Q2与第一功能引脚Q1电连接。第二功能引脚Q2能够向下一级驱动芯片100输出测试信号。也即上一级驱动芯片101的第二功能引脚Q2能够向下一级驱动芯片102的第一功能引脚Q1输出测试信号，下一级驱动芯片102中的逻辑控制模块CTR根据测试信号，产生分别流经任一输出引脚OUT的测试电流。如上，可以利用下一级驱动芯片102继续向再下一级的驱动芯片输出测试信号。
本实施例中的驱动芯片100，可以利用第一功能引脚Q1提供测试信号至逻辑控制模块CTR，逻辑控制模块CTR根据测试信号，产生分别流经任一输出引脚OUT的测试电流。该测试电流可以驱动发光单元E(如图2所示)发光。第二功能引脚Q2与第一功能引脚Q1电连接。第二功能引脚Q2能够向下一级驱动芯片100输出测试信号。如上结构，可以通过一步检测操作实现对各个驱动芯片100电连接的发光单元E的点亮测试。如发光单元E正常发光，则可判定该发光单元E连接正常，如发光单元E未发光，则可判定该发光单元E存在问题，需进行返修，提高驱动芯片100的检修效率。通过将第一功能引脚Q1和第二功能引脚Q2沿第一方向X排布，有利于布线设计。
在一些实施例中，请继续参阅图5所示，驱动芯片100还包括第二功能引脚Q2和第一连接线L1。第二功能引脚Q2通过第一连接线L1与第一功能引脚Q1相连。第二功能引脚Q2向下一级驱动芯片输出测试信号。驱动芯片100具有相互平行的第一边缘W1和第二边缘W2。第一功能引脚Q1和第二功能引脚Q2中，一个靠近第一边缘W1，另一个靠近第二边缘W2。
本实施例中，如图5所示，第一边缘W1为驱动芯片100的上边缘，第二边缘W2为驱动芯片100的下边缘。上一级驱动芯片101的下边缘靠近下一级驱动芯片102的上边缘。由此，设置第一功能引脚Q1靠近第一边缘W1，第二功能引脚Q2靠近第二边缘W2。也即上一级驱动芯片101的第二功能引脚Q2靠近下一级驱动芯片102的第一功能引脚Q1。可以利用一个外部连接线K1使上一级驱动芯片101的第二功能引脚Q2和下一级驱动芯片102的第一功能引脚Q1电连接。有利于充分利用相邻两个级联设置的驱动芯片100之间的空间，同时也有利于缩减外部连接线K1的长度，以及便于灵活的设置外部连接线K1的位置，从而便于后续发光基板的走线布局。
示例性的，图5中以第一功能引脚Q1靠近第一边缘W1，第二功能引脚Q2靠近第二边缘W2为例进行示意。
在一些示例中，第一连接线L1可以设置在驱动芯片100内部；在另一些示例中，第一连接线L1设置在发光基板上，即位于驱动芯片100的外部。当第一连接线L1位于发光基板上时，第一连接线L1在发光基板上的正投影位于第一功能引脚Q1和第二功能引脚Q2在发光基板上的正投影之间。也即第一连接线L1位于相邻两个级联设置的驱动芯片100之间，可以充分利用相邻驱动芯片100之间的空间，同时减少对驱动芯片100左右空间(如图3和图5所示的驱动芯片100左右空间)的占用，将于驱动芯片100电连接的各个信号线分散设置，利于各个信号线的走线布局。
示例性的，图5中以第一连接线L1可以为驱动芯片100内部的走线，且第一连接线L1为直线为例进行示意。本公开对第一连接走线L1的形状、以及膜层位置均不作具体限定，只要位于第一功能引脚Q1和第二功能引脚Q2之间，且连接第一功能引脚Q1和第二功能引脚Q2即可。
在一些实施例中，驱动芯片100还包括数据引脚Data(如图4所示)。数据引脚Data用于连接数据信号线，以接收驱动数据，驱动数据包括驱动信息和地址验证信息。逻辑控制模块CTR还被配置为：当地址验证信息与驱动芯片100的地址信息匹配时，确定与该地址验证信息对应的驱动信息，并根据驱动信息，生成与驱动芯片100连接的至少一个发光单元E(如图2所示) 所对应的驱动电流，并控制驱动芯片100的至少一个输出引脚OUT与对应的发光单元E形成电气通路，驱动电流可以在该电气通路中流动。
在一些实施例中，请继续参阅图5所示，驱动芯片100还包括地址引脚Di和中继引脚Do。地址引脚Di与逻辑控制模块CTR电连接；地址引脚Di能够接收驱动数据；驱动数据包括地址校验信息以及与多个级联的驱动芯片对应的多个驱动信息。逻辑控制模块CTR被配置为：根据地址校验信息，获取与当前的驱动芯片对应的一个驱动信息；以及，对地址校验信息进行更新，生成包含更新后的地址校验信息的驱动数据。中继引脚Do与逻辑控制模块电连接；中继引脚Do能够向下一级驱动芯片102输出包含更新后的地址校验信息的驱动数据。
可以理解的是，当前级驱动芯片101的地址引脚Di能够接收驱动数据；驱动数据包括当前级驱动芯片101的地址校验信息以及与全部级联的驱动芯片对应的多个驱动信息。当前级驱动芯片101的逻辑控制模块CTR接收驱动数据，根据驱动数据中的地址校验信息，获取与当前级驱动芯片101的地址校验信息相对应的驱动信息。逻辑控制模块CTR根据该驱动信息，生成与驱动芯片100连接的至少一个发光单元E(如图2所示)所对应的驱动电流，并控制驱动芯片100的至少一个输出引脚OUT与对应的发光单元E形成电气通路，驱动电流可以在该电气通路中流动。
以及，当前级驱动芯片101的逻辑控制模块CTR对地址校验信息进行更新，生成更新后的地址校验信息。更新后的地址校验信息包含更新后的地址校验信息。中继引脚Do能够向下一级驱动芯片102输出更新后的地址校验信息。
示例性的，逻辑控制模块CTR还会对接收到的驱动数据进行更新，也即对驱动数据中的地址校验信息进行更新。驱动数据中的地址校验信息即为起始标识位和/或结束标识位的个数。将驱动数据的起始标识位的数目减1和/或结束标识位的个数加1，并通过其中继引脚Do将重编辑后的驱动数据输出给下一级驱动芯片的地址引脚Di。当然地，驱动芯片100还可以采用其他不同的函数以生成新的地址校验信息。
需要说明的是，上述实施例提供的驱动芯片100中的地址引脚Di可以同于接收驱动数据。驱动数据包括地址校验信息以及与多个级联的驱动芯片对应的多个驱动信息。当前级驱动芯片101的逻辑控制模块CTR对地址校验信息进行更新，生成更新后的地址校验信息。更新后的地址校验信息包含更新后的地址校验信息。中继引脚Do能够向下一级驱动芯片102输出更新后的地 址校验信息。也即地址引脚Di的驱动数据同时实现写入地址和输入驱动信息的作用，相对于分别利用地址引脚Di接收地址信息，数据引脚Data接收驱动数据的方式，可以减少驱动芯片100中引脚的数量，有利于降低驱动芯片100的面积占比，节约资源。也有利于后续为驱动芯片100信号的各个走线的布图设计。
在一些示例中，外部电路(例如电路板)上可以设置有编码器，逻辑控制模块CTR可以设置有解码器。编码器可以按照4b/5b编码协议、8b/10b编码协议或者其他编码协议进行编码，以生成驱动数据并传输至地址引脚Di。逻辑控制模块CTR的解码器可以对驱动信号进行解码，进而获得驱动数据中的驱动信息和地址校验信息。
在一些实施例中，以驱动芯片100不设置数据引脚，而是由地址引脚Di和中继引脚Do分别实现驱动数据的接收和传输的情况为例，进行说明。
发光基板200上依次级联的N个驱动芯片100中的第一级驱动芯片的地址引脚Di，与地址信号线连接，该地址信号线传输驱动数据。该地址信号线中传输的驱动数据包括与依次级联的多个驱动芯片的一一对应的驱动信息。该地址信号线中传输的驱动数据包括与依次级联的多个驱动芯片的一一对应的驱动信息。
图6为本公开一些实施例提供的一种驱动数据的数据格式示意图。
在一些实施例中，请参阅图6所示，驱动数据为数字信号，由起始标识位、地址信息、寄存器地址、寄存器字节长度信息、数据信息、结束标识位组成。
起始标识位和结束标识位可分别占用n bit位，其中，n为1或8；驱动数据可以包括多个起始标识位和多个结束标识位，起始标识位的数目和结束标识位的数目的总和是不变的，例如为N+1，N为多个级联的驱动芯片的数目。
在一些示例中，地址信息可以包括多个组，每组均占用8bit位。
示例性的，地址信息包括4个组，分别为：
命令地址组(dev addr)，通过对命令地址的8个bit位分别进行赋值，以实现不同的命令控制。
问题地址组(vled low dev addr)，可以反馈第二电压线10出现电位异常的位置。
故障地址组(fault dev addr)，可以反馈出现故障的驱动芯片100的地址信息。
故障状态组(fault status)，可以反馈出现故障的驱动芯片100的具体状 态。
示例性的，地址信息可以仅包括命令地址。
寄存器地址和寄存器字节长度信息分别占用8bit位。寄存器地址对应某个驱动芯片中寄存器单元的物理地址(唯一)，寄存器字节长度代表该寄存器单元需要预留的数据字节长度，从而便于存储配置信息。
数据信息包括N个8bit位的驱动信息，N个驱动信息按照N个驱动芯片的级联顺序排列。
可以理解是，可以通过脉冲宽度调制的方式实现对驱动数据中任一bit位的赋值，例如某个bit位的占空比为50％，则其代表驱动数据的起点；某个bit位的占空比为75％，则其代表逻辑“1”；某个bit位的占空比为25％，则其代表逻辑“0”。
图7为本公开一些实施例提供的又一种驱动数据的数据格式示意图。
在一些示例中，依次级联的N个驱动芯片中，第一级驱动芯片的地址引脚Di，与地址信号线20连接，该地址信号线传输驱动数据。该地址信号线20中传输的当前显示帧对应的驱动数据，第n级驱动芯片(n为大于1且小于等于N的正整数)的地址引脚Di与第n-1级驱动芯片的中继引脚Do连接，n为大于1且小于等于N的正整数。依次级联的N个驱动芯片中的每个驱动芯片接收固定长度的驱动数据，而每个驱动芯片接收到的驱动数据中，起始标识位和/或结束标识位的数目不同。具体的，起始标识位的数目与该驱动芯片在级联序列中的顺序相对应。例如，以N＝3为例，一共有3个驱动芯片依次级联，其中第1级驱动芯片100接收到由地址信号线20提供的驱动数据中，包括1个起始标识位，3个连续的结束标识位；第2级驱动芯片100的地址引脚Di接收由第2级驱动芯片100的中继引脚Do输出的驱动数据中，包括2个连续的起始标识位，2个连续的结束标识位；第3级驱动芯片100的地址引脚Di接收由第2级驱动芯片100的中继引脚Do输出的驱动数据中，包括3个连续的起始标识位，1个结束标识位。依次级联的N个驱动芯片中的每个驱动芯片接收到的驱动数据中，除了起始标识位和/或结束标识位的数目不同以外，其余的数据完全相同，具体可以包括地址信息、寄存器地址、寄存器字节长度信息、数据信息，即如图9中的数据格式；其中，数据信息包括3个8bit位的驱动信息，3个驱动信息按照3个依次级联的驱动芯片的级联顺序排列。可以理解的是，每一级驱动芯片100的地址引脚Di在接收到驱动数据后，其逻辑控制模块CTR仅获取驱动数据中与该驱动芯片对应的驱动信息，从而使驱动芯片根据该驱动信息为与其电连接的发光单元E提供驱动电流； 此外，其逻辑控制模块CTR还会对接收到的驱动数据进行重编辑，将驱动数据的起始标识位的数目减1和/或结束标识位的个数加1，并通过其中继引脚Do将重编辑后的驱动数据输出给下一级驱动芯片的地址引脚Di。
可以理解的是，在上述情况下，驱动数据中的地址校验信息即为起始标识位和/或结束标识位的个数。
在一些实施例中，请继续参阅图5所示，测试信号包括开关信号。开关线号用于控制逻辑控制模块CTR，产生分别流经任一输出引脚OUT的测试电流。
此时，逻辑控制模块CTR根据该开关信号，产生分别流经任一输出引脚OUT的测试电流。也即，可以控制与该驱动芯片100通过输出引脚OUT电连接的发光单元E(如图2所示)可以接收测试电流。并且第二功能引脚Q2能够向下一级驱动芯片100输出测试信号。由此，可以使级联设置的多个驱动芯片100连接的发光元件E，均接收测试电流发光。从而可以通过一步检测操作实现对各个驱动芯片100电连接的发光单元E的点亮测试。如发光单元E未发光，则可判定该发光单元E存在问题，有效的提高驱动芯片100的检修效率。
在一些示例中，测试信号可以为高电平信号或低电平信号。只要可以通过该测试信号控制逻辑控制模块CTR，产生分别流经任一输出引脚OUT的测试电流即可。
需要说明的是，驱动芯片100中至少一个输出引脚OUT电连接发光单元E的一端，发光单元E的另一端和第二电压线(图中未示出)电连接。第二电压线用于为发光单元E提供工作电压。接地引脚GND可以向驱动芯片100的提供接地电压。如此，发光单元E相当于连接在第二电压线和接地引脚GND之间；逻辑控制模块CTR根据测试信号控制发光单元E的电流路径的导通或者截止，进而控制通过发光单元E和输出引脚OUT的电流。此时，当第一功能引脚Q1接收测试信号，并将测试信号发送至逻辑控制模块CTR，逻辑控制模块CTR通过测试信号控制发光单元E的发光电流路径的导通或者截止，进而控制通过发光单元E和输出引脚OUT的测试电流。
在一些实施例中，在“测试信号包括开关信号。开关线号用于控制逻辑控制模块CTR，产生分别流经任一输出引脚OUT的测试电流”的情况下，可以设置地址引脚Di用于接收驱动数据。
如上结构，驱动芯片100可以在通过一步检测操作实现对各个驱动芯片100电连接的发光单元E的点亮测试，有效的提高驱动芯片100的检修效率； 同时不会增加驱动芯片100中引脚的数量，有利于后续为驱动芯片100信号的各个走线的布图设计。
在另一些实施例中，请继续参阅图5所示，测试信号包括测试数据和第一通用地址信息，第一通用地址信息能够匹配任意一个驱动芯片100的初始化地址信息。逻辑控制模块CTR被配置为：根据测试数据，产生分别流经任一输出引脚OUT的测试电流。
其中，驱动芯片100在出厂时会设置同一的初始化地址。例如，初始化地址可以为多个比特位为连续的0或连续1。设置测试信号中的第一通用地址信息和驱动芯片100的初始化地址相同。也即可以为当初始化地址为连续的0时，通用地址设置对应设置为连续的0。从而实现利用第一通用地址信息与全部驱动芯片100的初始化地址信息匹配，使驱动芯片100的逻辑控制模块CTR获取测试信号中的测试数据，产生分别流经任一输出引脚OUT的测试电流。发光元件E接收测试电流发光。由此，可以通过一步检测操作实现对各个驱动芯片100电连接的发光单元E的点亮测试，从而有效的提高驱动芯片100的检修效率。
需要说明的是，驱动芯片100中至少一个输出引脚OUT电连接发光单元E的一端，发光单元E的另一端和第二电压线(图中未示出)电连接。第二电压线用于为发光单元E提供工作电压。接地引脚GND可以向驱动芯片100提供接地电压。如此，发光单元E相当于连接在第二电压线和接地引脚GND之间；逻辑控制模块CTR识别地址信息，获取测试信号中的测试数据。逻辑控制模块CTR根据测试数据控制发光单元E的电流路径的导通或者截止，进而控制通过发光单元E和输出引脚OUTP的电流。此时，当第一功能引脚Q1接收测试信号，并将测试信号发送至逻辑控制模块CTR，逻辑控制模块CTR识别第一通用地址信息，获取测试信号中的测试数据。逻辑控制模块CTR根据测试数据控制发光单元E的发光电流路径的导通或者截止，进而控制通过发光单元E和输出引脚OUTP的测试电流。
在一些实施例中，请继续参阅图5所示，第一功能引脚Q1分时接收测试信号和驱动数据。例如，在一个时段，第一功能引脚Q1接收测试信号。在另一个时段，第一功能引脚Q1接收驱动数据。
在第一功能引脚Q1接收测试信号的情况下，测试信号包括测试数据和第一通用地址信息，第一通用地址信息能够匹配任意一个驱动芯片100的初始化地址信息。逻辑控制模块CTR被配置为：根据测试数据，产生分别流经任一输出引脚OUT的测试电流。
其中，每一级驱动芯片100的第一功能引脚Q1接收测试信号后，其逻辑控制模块CTR可以解析第一通用地址信息，获得对应的测试数据。从而使驱动芯片根据该测试数据为与其电连接的发光单元E提供测试电流。此外，由于第二功能引脚Q2与第一功能引脚Q1通过第一连接线L1直接电连接，可以通过第二功能引脚Q2将第一功能引脚Q1接收到的测试信号，通过其第二功能引脚Q2输出给下一级驱动芯片的第一功能引脚Q1。
依次级联的N个驱动芯片中的每一级驱动芯片的第一功能引脚Q1和第二功能引脚Q2均接收相同的驱动数据，驱动数据中包括N个地址验证信息以及N个驱动信息，一个地址验证信息与一个驱动信息构成一个数组，N个数组依次排布，例如可以按照N个驱动芯片的级联顺序依次排布，或也可以为无规律的顺序依次排布。逻辑控制模块CTR还被配置为：当地址验证信息与地址信息匹配时，根据地址验证信息，接收对应的驱动信息，并根据驱动信息，生成与驱动芯片100连接的至少一个发光单元E(如图2所示)所对应的驱动电流，并控制驱动芯片100的至少一个输出引脚OUT与对应的发光单元E形成电气通路，驱动电流在该电气通路中流动。
其中，每一级驱动芯片100的第一功能引脚Q1在接收驱动数据后，其逻辑控制模块CTR仅获取驱动数据中与该驱动芯片对应的驱动信息，从而使驱动芯片根据该驱动信息为与其电连接的发光单元E提供驱动电流。此外，其逻辑控制模块CTR还会对接收到的驱动数据通过其第二功能引脚Q2输出给下一级驱动芯片的第一功能引脚Q1。
需要说明的是，每一级驱动芯片100的第一功能引脚Q1在接收到驱动数据后，其逻辑控制模块CTR仅获取驱动数据中与该驱动芯片对应的驱动信息，从而使驱动芯片根据该驱动信息为与其电连接的发光单元E提供驱动电流。此外，由于第二功能引脚Q2与第一功能引脚Q1通过第一连接线L1直接电连接，可以通过第二功能引脚Q2将第一功能引脚Q1接收到的驱动数据，输出给下一级驱动芯片的第一功能引脚Q1。
综上所述，一个驱动芯片100中，第一功能引脚Q1在接收测试信号后，对测试信号的处理，与数据引脚Data在接收驱动数据后，对驱动数据的处理相似。由此，可以利用第一功能引脚Q1分时接收测试信号和驱动数据。驱动芯片100在测试阶段，第一功能引脚Q1用于接收测试信号。驱动芯片100在正常工作阶段，第一功能引脚Q1用于接收驱动数据。在本实施例中，在第一功能引脚Q1分时接收测试信号和驱动数据时，驱动芯片100中可以无需设置数据引脚Data，有利于降低驱动芯片100的面积占比，节约资源。而且，由 于可以通过第二功能引脚Q2将第一功能引脚Q1接收到的驱动数据，输出给下一级驱动芯片的第一功能引脚Q1，也有利于布局发光基板上为驱动芯片100提供信号的走线。
在一些实施例中，请继续参阅图5所示，驱动芯片100包括地址引脚Di和中继引脚Do。地址引脚Di可以接收地址信号。根据地址信号配置驱动芯片100的地址信息，并生成中继信号，中继引脚Do能够输出中继信号。也即，对各个驱动芯片100的初始化地址信息进行更新。
在一些示例中，初始化地址信息和地址信号可以为同类型的数字信号。例如，初始化地址信息为0。当一个驱动芯片100接收地址信号后，可以解析并获得、存储该地址信号中的地址信息，还可以使地址信号递增1或另一非0固定量并将递增后的地址信号(新的地址信号)调制为中继信号，该中继信号作为下一级驱动芯片100的地址信号。当然地，驱动芯片100还可以采用其他不同的函数以更新地址信号。
在地址引脚Di接收地址信号后，第一功能引脚Q1用于接收驱动数据。驱动数据包括多个地址验证信息以及与多个地址验证信息对应的多个驱动信息。对于任一个所述驱动芯片：当地址验证信息与地址信息匹配时，根据地址验证信息，接收对应的驱动信息，并根据所接收的驱动信息，生成与至少一个输出引脚OUT对应的驱动电流。也即，生成与驱动芯片100连接的至少一个发光单元E所对应的驱动电流，控制驱动芯片100的至少一个输出引脚OUT与对应的发光单元E形成电气通路，驱动电流在该电气通路中流动。发光元件E接收该驱动电流发光。
此外，第二功能引脚Q2能够向下一级驱动芯片输出所述驱动数据。
可以理解的是，在地址配置阶段，如驱动芯片100的地址引脚Di和中继引脚Do焊接出现问题，会导致无法更新该驱动芯片100的地址信息，以及无法更新设置在该驱动芯片100下级的全部驱动芯片的地址信息。以地址信息占8bit位为例，前4个驱动芯片100更新后的地址信息分别为00000001、00000010、00000011、00000100，例如，第五个驱动芯片100内部或第五个驱动芯片与第六个驱动芯片的连接出现问题，而从第5个驱动芯片开始，后续级联的多个的驱动芯片100的地址信息没有更新，依旧为初始化地址信息00000000。由于驱动数据中的地址验证信息与各个驱动芯片更新后的地址信息一一匹配对应，因此前4个驱动芯片100可以从驱动数据中获取到对应的驱动信息，也即与前4个驱动芯片100电连接的发光元件E可以正常发光。此时，假设各个发光元件E均正常焊接。而驱动数据中的地址验证信息无法 与从第5个驱动芯片开始后续级联的多个驱动芯片100均无法从驱动数据中获取到对应的驱动信息，也即从第5个开始后续全部驱动芯片100的地址信息无法获取驱动电流，导致与其电连接的发光元件E均无法发光。
基于此，可以根据各个驱动芯片100电连接全部发光元件E是否发光进行判断。如从某一个驱动芯片100开始，后续驱动芯片100电连接的发光元件E均未发光，则可以判定该驱动芯片100内部或该驱动芯片与下一级驱动芯片100的连接出现问题，需要对其进行返修。
此外，本公开一些实施例提供的驱动芯片100，可以无需设置数据引脚，而是由第一功能引脚Q1和第二功能引脚Q2分别实现驱动数据的接收和传输。有利于降低驱动芯片100的面积占比，节约资源。也有利于后续布局为驱动芯片100提供信号的各个走线。
在又一些实施例中，地址引脚Di可以接收地址信号。根据地址信号配置驱动芯片100的地址信息，逻辑控制模块CTR根据接收到的地址信息生成中继信号，中继引脚Do能够输出中继信号。也即，对各个驱动芯片100的初始化地址信息进行更新。
在一些示例中，初始化地址信息和地址信号可以为同类型的数字信号。例如，初始化地址信息为0。当一个驱动芯片100接收地址信号后，可以解析并获得、存储该地址信号中的地址信号，还可以使地址信号加固定量的作为中继信号，该中继信号作为下一级驱动芯片100的地址信号。当固定量为0时，也即，所有驱动芯片100的地址信号均相同。当然地，驱动芯片100还可以采用其他不同的函数以更新地址信号。
在第一功能引脚Q1接收测试信号的情况下，测试信号包括测试数据和第二通用地址信息。第二通用地址信息能够匹配任意一个驱动芯片100的地址信息。逻辑控制模块CTR被配置为：根据测试信号，产生分别流经任一输出引脚OUT的测试电流。
可以理解的是，在地址配置阶段，如某驱动芯片内部或该驱动芯片与下一级驱动芯片100的连接出现问题，会导致该驱动芯片及其之后级联的多个驱动芯片的地址信息均无法更新。例如，前4个驱动芯片100更新后的地址信息均为11111111，而从第5个驱动芯片开始后续全部驱动芯片100的地址信息依旧为初始化地址信息00000000。而测试信号中的第二通用地址信息预设为11111111，可以与前4个驱动芯片100更新后的地址信息匹配，也即与前4个驱动芯片100电连接的发光元件E可以正常发光。此时，假设各个发光元件E均正常焊接。而测试信号中的第二通用地址信息无法与从第5个开 始后续全部驱动芯片100的地址信息(对初始化信息更新后的地址信息)匹配，也即从第5个开始后续全部驱动芯片100的逻辑控制模块无法从驱动数据中获取驱动信息，导致与其电连接的发光元件E均无法发光。
基于此，可以根据各个驱动芯片100电连接全部发光元件E是否发光进行判断。如从某一个驱动芯片100开始，后续驱动芯片100电连接的发光元件E均未发光，则可以判定该驱动芯片100的地址引脚Di和中继引脚Do焊接出现问题，需要对其进行返修。
在一些实施例中，请继续参阅图5所示，驱动芯片100还具有位于第一边缘W1的第一端与第二边缘W2的第一端之间的第三边缘W3。在驱动芯片100包括地址引脚Di和中继引脚Do的情形下：地址引脚Di和中继引脚Do中，一个靠近第一边缘W1，另一个靠近第二边缘W2。地址引脚Di和中继引脚Do，相对于第一功能引脚Q1和第二功能引脚Q2，更靠近第三边缘W3。
在本实施例中，设置地址引脚Di和中继引脚Do中，一个靠近第一边缘W1，另一个靠近第二边缘W2。如图5所示，第一边缘W1为驱动芯片100的上边缘，第二边缘W2为驱动芯片100的下边缘。上一级驱动芯片101的下边缘靠近下一级驱动芯片102的上边缘。
由此，设置地址引脚Di靠近第一边缘W1，中继引脚Do靠近第二边缘W2。也即上一级驱动芯片101的中继引脚Do靠近下一级驱动芯片102的地址引脚Di。可以利用一个外部连接线K2使上一级驱动芯片101的中继引脚Do和下一级驱动芯片102的地址引脚Di电连接。使上一级驱动芯片101的地址引脚Di接收地址信号，上一级驱动芯片101的逻辑控制模块CTR根据地址信号配置上一级驱动芯片101的地址信息，并生成中继信号。中继信号能够作为下一级驱动芯片102的地址信号，且上一级驱动芯片101的中继引脚Do将该中继信号发送至下一级驱动芯片102的地址引脚Di。进而实现为级联的驱动芯片100分配动态地址。
并且，设置地址引脚Di靠近第一边缘W1，中继引脚Do靠近第二边缘W2。还有利于缩减外部连接线K2的长度，以及便于灵活的设置外部连接线K2的位置，从而便于后续发光基板的走线布局。
此外，设置地址引脚Di和中继引脚Do，相对于第一功能引脚Q1和第二功能引脚Q2，更靠近第三边缘W3。也即地址引脚Di和中继引脚Do设置在最靠近第三边缘W3的上下两侧，便于连接驱动芯片100外部的地址信号线，有利于后续发光基板的走线布局。
示例性的，图5以设置地址引脚Di靠近第一边缘W1，中继引脚Do靠 近第二边缘W2为例进行示意。可以理解的是，在另一些实施例中，可以设置地址引脚Di靠近第二边缘W2，中继引脚Do靠近第一边缘W1为例进行示意。本公开一些实施例对于驱动芯片100中地址引脚Di和中继引脚Do的位置可以灵活设置，只要使上一级驱动芯片101的中继引脚Do靠近下一级驱动芯片102的地址引脚Di即可。
示例性的，图5以第三边缘W3的一端与第一边缘W1直接相连接，第三边缘W3的另一端与第二边缘W2直接相连接为例进行示意。可以理解的是，在另一些实施例中，第三边缘W3和第一边缘W1通过其他边缘进行连接。在又一些实施例中，第三边缘W3和第二边缘W2通过其他边缘进行连接。
图8为本公开的再一些实施例提供的又一种驱动芯片的结构图。
在一些实施例中，请参阅图8所示，驱动芯片100还包括至少一个接地引脚GND。至少一个接地引脚GND与逻辑控制模块CTR电连接。接地引脚GND能够接收接地信号。接地引脚GND位于地址引脚Di和中继引脚Do之间。
本实施例中，驱动芯片100还包括至少一个接地引脚GND，接收接地信号。图8以驱动芯片100包括2个接地引脚GND为例进行示意。可以理解的时，在另一些实施例中，驱动芯片100可以包括1个、3个或4个接地引脚，具体可以根据需要选择。设置接地引脚GND靠近第三边缘W3，且接地引脚GND位于地址引脚Di和中继引脚Do之间。可以将接地引脚GND集中在驱动芯片100的第三边缘W3的中间区域，有利于接地引脚GND后续与接地引线进行电连接，避免与其他走线出现交叠设计的问题。
图9为本公开的又一些实施例提供的一种驱动芯片的结构图。图10为本公开的又一些实施例提供的一种驱动芯片的结构图。
在一些实施例中，请参阅图9和图10所示，驱动芯片100还包括第一电源引脚V1。第一电源引脚V1与逻辑控制模块CTR电连接。第一电源引脚V1能够接收电源信号。第一电源引脚V1靠近第一边缘W1或第二边缘W2。第一电源引脚V1相对于地址引脚Di和中继引脚Do，更远离第三边缘W3。
在本实施例中，驱动芯片100利用第一电源引脚V1接收电源信号。提供驱动芯片100工作所需电源信号，保证驱动芯片100正常工作。
设置第一电源引脚V1靠近第一边缘W1或第二边缘W2。结合图9和图10所示，图9和图10以第一电源引脚V1靠近第一边缘W1为例进行示意，可以理解的是，在另一些实施例中，也可以设置第一电源引脚V1靠近第二边缘W2。基于此，第一电源引脚V1靠近驱动芯片100的上边缘或下边缘。将 多个驱动芯片100中的第一电源引脚V1均设置在对应驱动芯片100的上边缘或下边缘，可以充分利用相邻两个驱动芯片100之间的空间，有利于布线设计。
此外，设置第一电源引脚V1相对于地址引脚Di和中继引脚Do，更远离第三边缘W3。可以包括以下两种情况：
第一种：请参阅图9所示，第一电源引脚V1位于第一功能引脚Q1和地址引脚Di之间。
第二种：请参阅图10所示，第一功能引脚Q1位于第一电源引脚V1和地址引脚Di之间。
无论上述第一种还是第二种方式，均可以理解为将地址引脚Di和中继引脚Do设置在最靠近第三边缘W3的位置处。便于地址引脚Di连接驱动芯片100外部的地址信号线，有利于后续发光基板的走线布局。
在一些实施例中，请参阅图9和图10所示，驱动芯片100还包括第二电源引脚V2和第二连接线L2。第二电源引脚V2通过第二连接线L2与第一电源引脚V1相连。其中，第一电源引脚V1和第二电源引脚V2中，一个靠近第一边缘W1，另一个靠近第二边缘W2。第一电源引脚V1和第二电源引脚V2，相对于地址引脚Di和中继引脚Do，更远离第三边缘W3。
在本实施例中，第一电源引脚V1和本级的驱动芯片100的第二电源引脚V2通过第二连接线L2电连接。第一电源引脚V1和本级的驱动芯片100第二电源引脚V2接收相同的信号。进而，可以通过第二电源引脚V2向下一级驱动芯片100的第一电源引脚V1输出电源信号。便于相互级联设计的驱动芯片100之间的布线设计。
基于此，设置第一电源引脚V1和第二电源引脚V2中，一个靠近第一边缘W1，另一个靠近第二边缘W2。如图7和图8所示，第一边缘W1为驱动芯片100的上边缘，第二边缘W2为驱动芯片100的下边缘。上一级驱动芯片101的下边缘靠近下一级驱动芯片102的上边缘。
由此，设置第一电源引脚V1靠近第一边缘W1，第二电源引脚V2靠近第二边缘W2。也即第一电源引脚V1靠近驱动芯片100的上边缘，第二电源引脚V2靠近驱动芯片100的下边缘。便于使相邻两个驱动芯片100的第二电源引脚V2和第一电源引脚V1连接，使二电源引脚V2能够向下一级驱动芯片100输出电源信号。
此外，可以根据驱动芯片100中引脚的总数量，确实是否需要设置第二功能引脚Q2，以保证驱动芯片100中引脚的总数量为偶数。
在一些示例中，第二连接线L2可以为驱动芯片100内部的走线。在另一些示例中，第二连接线L2可以为驱动芯片100外部，但位于发光基板上的走线。当第二连接线L2位于发光基板上时，第二连接线L2在发光基板上的正投影位于第一电源引脚V1和第二电源引脚V2在发光基板上的正投影之间。
也即第二连接线L2位于相邻两个级联设置的驱动芯片100之间，可以充分利用相邻驱动芯片100之间的空间，同时减少对驱动芯片100左右空间(如图9和图10所示的驱动芯片100左右空间)的占用，将于驱动芯片100电连接的各个信号线分散设置，利于各个信号线的走线布局。
示例性的，图9和图10中以第二连接线L2可以为驱动芯片100内部的走线，且第二连接线L2为直线为例进行示意。本公开对第二连接线L2的形状、以及膜层位置均不作具体限定，只要位于第一电源引脚V1和第二电源引脚V2之间，且连接第一电源引脚V1和第二电源引脚V2即可。
示例性的，图9和图10以第一电源引脚V1靠近第一边缘W1，第二电源引脚V2靠近第二边缘W2为例进行示意。可以理解的是，在另一些实施例中，也可以设置第一电源引脚V1靠近第二边缘W2，第二电源引脚V2靠近第一边缘W1。只要使相邻两个驱动芯片100的第二电源引脚V2和第一电源引脚V1想靠近即可。
其中，“第一电源引脚V1和第二电源引脚V2，相对于地址引脚Di和中继引脚Do，更远离第三边缘W3。”可以包括以下两种情况：
第一种：请参阅图9所示，第一电源引脚V1位于第一功能引脚Q1和地址引脚Di之间。第二电源引脚V2位于第二功能引脚Q2和中继引脚Do之间。
第二种：请参阅图10所示，第一功能引脚Q1位于第一电源引脚V1和地址引脚Di之间。第二功能引脚Q2位于第二电源引脚V2和中继引脚Do之间。
无论上述第一种还是第二种方式，均可以理解为将地址引脚Di和中继引脚Do设置在最靠近第三边缘W3的位置处。便于地址引脚Di连接驱动芯片100外部的地址信号线，有利于后续发光基板的走线布局。
图11为本公开的再一些实施例提供的一种发光基板的结构图。图12为图11中R位置处的一种局部放大图。
本公开一些实施例提供了一种发光基板200。请参阅图11和图12所示，发光基板200包括多个级联的驱动芯片100和多个器件组O。驱动芯片100为上述任一实施例的驱动芯片100。一个器件组O的第一端Oa与一个驱动芯片100的至少一个输出引脚OUT对应电连接。
在一些示例中，一个器件组O包括至少一个发光单元E。示例性的，一个发光单元E可以包括至少一个发光元件。其中，一个发光单元E可以仅包括一个发光元件。或者，一个发光单元E可以包括两个或两个以上相互电连接发光元件。当一个发光单元E包括两个或两个以上发光元件时，两个或两个以上发光元件可以相互串联，也可以相互并联，还可以是串联并联混合的连接方式。
示例性的，“一个器件组O的第一端Oa与一个驱动芯片100的至少一个输出引脚OUT对应电连接。”可以为一个器件组O中的发光单元E与一个驱动芯片100中的输出引脚OUT一一对应。本公开实施例对每个输出引脚OUT电连接的发光单元E的数量不做限定，可以根据实际需求进行调节。例如，图12所示，一个驱动芯片100包括4个输出引脚OUT。一个器件组O包括4个发光单元E。一个输出引脚OUT电连接一个发光单元E。
本实施例中，可以利用各个驱动芯片100中的第一功能引脚Q1提供测试信号至其对应的逻辑控制模块CTR，逻辑控制模块CTR产生分别流经任一输出引脚OUT的测试电流。该测试电流可以驱动发光单元E发光。也即，全部驱动芯片100电连接的发光单元E正常情况下均可以接收到测试电流。由此，可以通过一步检测操作实现对各个驱动芯片100电连接的发光单元E的点亮测试。如发光单元E正常发光，则可判定该发光单元E连接正常，如发光单元E未发光，则可判定该发光单元E存在问题，需进行返修，提高驱动芯片100的检修效率。
在一些实施例中，请继续参阅图11和图12所示，在驱动芯片100还包括地址引脚Di、中继引脚Do、第一电源引脚V1和至少一个接地引脚GND的情形下：位于上一级的驱动芯片100的中继引脚Do与位于下一级的驱动芯片100的地址引脚Di电连接。发光基板200还包括导电层M。导电层M中包括第二电压线10、地址信号线20、第一电压线30、测试信号线40和接地线50。
第二电压线10沿第一方向X延伸，一个器件组O中的多个发光单元E沿第一方向X排布。设置第二电压线10与各个器件组的第二端电连接。也即第二电压线10与各个器件组O中的至少一个发光单元E电连接，为该发光单元E提供驱动电压。同时，由于多个一个器件组O中的多个发光单元E沿第一方向X排布，一个器件组O中的全部发光单元E与同一条第二电压线10连接时，可以利用沿第二方向Y延伸的导电线11与第二电压线10连接。各个导电线11之间无交叠，有利于实现发光基板200的单层走线设计。示例性 的，各个导电线11相互平行。其中，第一方向X和第二方向Y相交，且平行于发光基板200。如图11和图12所示，第一方向X和第二方向Y垂直。可以理解的是，在另一些实施例中，第一方向X和第二方向Y的夹角可以为钝角或锐角。
在一些示例中，多个级联设置的驱动芯片100沿第一方向Y排布，多个级联设置的驱动芯片100可以与同一条第二电压线10连接时，可以利用沿第二方向Y延伸的导电线11与第二电压线10连接。各个导电线11之间无交叠，有利于实现发光基板200的单层走线设计。示例性的，各个导电线11相互平行。
在任意一个器件组O包括一列设置的多个发光单元E。可以设置一个第二电压线10与一个器件组O中的全部发光单元E电连接。也可以设置形成器件组列的多个器件组O同时连接同一条第二电压线10。第二电压线10为至少一个发光单元E提供第一电压。
接地线50与各个驱动芯片100的至少一个接地引脚GND电连接。示例性的，接地线50与各个驱动芯片100的每个接地引脚GND电连接，为接地引脚提供接地信号。接地线50沿第一方向X延伸，接地线50位于驱动芯片100的外侧，且接地线40靠近接地引脚GND。由于接地线50需与各个驱动芯片100的至少一个接地引脚GND电连接，设置接地线40最靠近接地引脚GND，可以便于接地线40和接地引脚GND电连接，避免与其他信号线交叠。
地址信号线20与地址引脚Di电连接。多个级联设置的驱动芯片100中的第一个驱动芯片的地址引脚Di与地址信号线20电连接。其他级联设置的驱动芯片，上一级的驱动芯片的中继引脚Do与下一级的驱动芯片的地址引脚Di通过外部连接线K2电连接。实现地址引脚Di能够接收地址信号，根据地址信号配置驱动芯片100的地址信息，逻辑控制模块CTR根据接收到的地址信息生成中继信号。中继信号能够作为下一级驱动芯片100的地址信号。中继引脚Do能够输出中继信号。
地址信号线20沿第一方向Y延伸，且地址信号线20位于接地线40远离地址引脚Di的一侧。由于地址信号线20与第一个驱动芯片100的地址引脚Di电连接即可，将其设置在相对远离驱动芯片100的一侧，可以便于接地线50和接地引脚GND电连接，避免地址信号线20和接地线50交叠，有利于实现发光基板200的单层走线设计。
第一电压线30与各个驱动芯片100的第一电源引脚V1电连接。第一电源引脚V1位于驱动芯片的上边缘。也即，多个级联设置的驱动芯片100中的 第一电源引脚V1与第一电压线30电连接。用于为各个驱动芯片100提供电压使其可以正常工作。
测试信号线40与各个第一个驱动芯片100的第一功能引脚Q1电连接。测试信号线40位于驱动芯片的上边缘。也即，多个级联设置的驱动芯片100中的第一功能引脚Q1与测试信号线40电连接。用于为各个驱动芯片100提供测试信号，用于测试全部驱动芯片100电连接的发光单元E是否存在异常。
如上结构，第二电压线10位于发光单元E远离驱动芯片100的一侧。地址信号线20和接地线50位于靠近驱动芯片100的接地引脚GND的一侧，且接地线50位于地址信号线20和驱动芯片100之间。以及，第一电压线30和测试信号线40和外部连接线K2位于第二电压线10和接地线50之间。可以使得第二电压线10、地址信号线20、第一电压线30、测试信号线40和接地线50之间无交叠，实现发光基板200的单层走线设计，降低发光基板200的工艺难度，降低成本。
在一些实施例中，请继续参阅图11和图12所示，在驱动芯片100还包括第二功能引脚Q2的情况下，第二功能引脚Q2分别与本级的所述驱动芯片100的第一功能引脚Q1，和下一级的驱动芯片的第一功能引脚Q1电连接。示例性的，第二功能引脚Q2可以和下一级的驱动芯片的第一功能引脚Q1通过外部连接线K1电连接。
测试信号线40与第一个驱动芯片100的第一功能引脚Q1电连接。由于第二功能引脚Q2与本级的所述驱动芯片100的第一功能引脚Q1电连接，第二功能引脚Q2与第一功能引脚Q1接收相同的信号。进而，其他级联设置的驱动芯片，上一级的驱动芯片的第二功能引脚Q2与下一级的驱动芯片的第一功能引脚Q1通过外部连接线K1电连接。便于发光基板200中多个相互级联设计的驱动芯片100之间的布线设计。
外部连接线K1位于第二电压线10和接地线50之间。可以使得第二电压线10、地址信号线20、第一电压线30、测试信号线40和接地线50之间无交叠，实现发光基板200的单层走线设计，降低发光基板200的工艺难度，降低成本。
在一些实施例中，请继续参阅图11和图12所示，在驱动芯片100还包括第二电源引脚V2的情况下，第二电源引脚V2分别与，本级的驱动芯片100的第一电源引脚V1，和下一级的驱动芯片100的第一电源引脚V1电连接。
示例性的，第二电源引脚V2通过外部连接线K3和下一级的驱动芯片100的第一电源引脚V1电连接。
第一电压线30与多个级联设置的驱动芯片100中的第一个驱动芯片100中的第一电源引脚V1电连接。由于，第二电源引脚V2与本级的驱动芯片100的第一电源引脚V1电连接，第一电源引脚V1和本级的驱动芯片100第二电源引脚V2接收相同的信号。进而，对于其他级联设置的驱动芯片，可以便于实现上一级的驱动芯片的第二电源引脚V2，向下一级的驱动芯片的第一电源引脚V1输出电源信号。便于发光基板200中多个相互级联设计的驱动芯片100之间的布线设计。
外部连接线K3位于第二电压线10和接地线50之间。可以使得第二电压线10、地址信号线20、第一电压线30、测试信号线40和接地线50之间无交叠，实现发光基板200的单层走线设计，降低发光基板200的工艺难度，降低成本。
在一些实施例中，请继续参阅图11和图12所示，地址信号线20被配置为传输地址信号，测试信号线40被配置为分时传输测试信号和驱动数据。
本实施例中，地址信号线20传递地址信号至地址引脚Di，地址引脚Di接收地址信号。逻辑控制模块CTR根据地址信号配置驱动芯片100的地址信息，并生成中继信号。中继信号能够作为下一级驱动芯片100的地址信号。中继引脚Do与逻辑控制模块CTR电连接。中继引脚Do能够输出中继信号。
示例性的，地址信号可以为数字信号。当一个驱动芯片100接收地址信号后，可以解析并获得、存储该地址信号中的地址信号，还可以使地址信号递增1或另一固定量并将递增后的地址信号(新的地址信号)调制为中继信号，该中继信号作为下一级驱动芯片100的地址信号。当然地，驱动芯片100还可以采用其他不同的函数以生成新的地址信号。
测试信号线40分时传输测试信号和驱动数据。该测试信号线40可以分时提供不同的信号至驱动芯片100相同的引脚(第一功能引脚Q1)。
当测试信号线40提供测试信号至第一功能引脚Q1时，第一功能引脚Q1接收测试信号，该测试信号包括测试数据和第一通用地址信息。第一通用地址信息能够匹配任意一个驱动芯片的初始化地址信息。从而使任意一个驱动芯片100的逻辑控制模块根据测试数据，产生分别流经任一输出引脚OUT的测试电流。发光单元E接收测试电流发光。可以通过一步检测操作实现对各个驱动芯片100电连接的发光单元E的点亮测试，从而有效的提高驱动芯片100的检修效率。
当测试信号线40提供驱动数据至第一功能引脚Q1时，第一功能引脚Q1还可以用于接收驱动数据。驱动数据包括驱动信息和地址验证信息。驱动数 据包括多个地址验证信息以及与多个地址验证信息对应的多个驱动信息。对于任一个所述驱动芯片：当地址验证信息与地址信息匹配时，根据地址验证信息，接收对应的驱动信息，并根据所接收的驱动信息，生成与至少一个输出引脚OUT对应的驱动电流。也即，生成与驱动芯片100连接的至少一个发光单元E所对应的驱动电流，并控制驱动芯片100的至少一个输出引脚OUT与对应的发光单元E形成电气通路，驱动电流在该电气通路中流动。如从某个驱动芯片100开始，后续级联设置的驱动芯片100电连接的发光单元E均未发光，则判定该起始的驱动芯片100的地址引脚Di焊接不良，需对其进行返修。
如上结构，无需设置单独的信号线以及单独的数据引脚为驱动芯片100提供驱动数据，减少驱动芯片100连接的信号线，便于实现发光基板200的单层走线设计，降低发光基板200的工艺难度，降低成本。
在一些实施例中，请继续参阅图11，当地址信号线20被配置为能够传输驱动数据的情况下，地址信号线20与第二电压线10分别采用不同的信号线，可以简化驱动芯片100内部的电路结构，无需在驱动芯片100内设置电力调节电路(该电力调节电路用于基于电源信号中的直流分量生成驱动电压并基于电源信号中的调制分量生成驱动数据)，进而利于减小驱动芯片100的面积。另外，这种设置方式还可以简化外部电路结构，既可以避免设置将驱动电压和驱动数据调制成电力线载波通信的调制电路，还可以降低对驱动电压的品质要求。
在一些实施例中，请参阅图11和图12所示，地址信号线20被配置为传输驱动数据，测试信号线40被配置为传输测试信号。
本实施例中，测试信号线40传输测试信号至第一功能引脚Q1，该驱动芯片100中的第一功能引脚Q1接收的测试信号包括开关信号。开关信号用于控制逻辑控制模块CTR，产生分别流经任一输出引脚OUT的测试电流。此时，可以控制与该驱动芯片100电连接的发光单元E均可以接收测试电流。并且第二功能引脚Q2能够向下一级驱动芯片100输出测试信号。
由此，可以通过一步检测操作实现对各个驱动芯片100电连接的发光单元E的点亮测试。如发光单元E未发光，则可判定该发光单元E存在问题，有效的提高驱动芯片100的检修效率。在一些示例中，测试信号可以为高电平信号或低电平信号。只要可以通过该测试信号控制逻辑控制模块CTR，产生分别流经任一输出引脚OUT的测试电流即可。
地址信号线20传输驱动数据至地址引脚Di。地址引脚Di接收驱动数据， 驱动数据包括地址校验信息以及与多个级联的驱动芯片对应的多个驱动信息。逻辑控制模块CTR根据地址校验信息，配置与当前的驱动芯片对应的一个驱动信息；以及，对地址校验信息进行更新，生成包含更新后的地址校验信息的驱动数据。中继引脚Do与逻辑控制模块电连接；中继引脚Do能够向下一级驱动芯片102输出包含更新后的地址校验信息的驱动数据。
可以理解的是，上一级驱动芯片101的地址引脚Di能够接收驱动数据；驱动数据包括上一级驱动芯片101的地址校验信息以及与全部级联的驱动芯片对应的多个驱动信息。上一级驱动芯片101的逻辑控制模块CTR接收驱动数据，根据驱动数据中的地址校验信息，配置与上一级驱动芯片101的地址校验信息相对应的驱动信息。逻辑控制模块CTR根据该驱动信息，生成与驱动芯片100连接的至少一个发光单元E所对应的驱动电流，并控制驱动芯片100的至少一个输出引脚OUT与对应的发光单元E形成电气通路，驱动电流可以在该电气通路中流动。如从某个驱动芯片100开始，后续级联设置的驱动芯片100电连接的发光单元E均未发光，则判定该起始的驱动芯片100的地址引脚Di焊接不良，需对其进行返修。
以及，上一级驱动芯片101的逻辑控制模块CTR对地址校验信息进行更新，生成更新后的地址校验信息。更新后的地址校验信息包含更新后的地址校验信息。中继引脚Do能够向下一级驱动芯片102输出更新后的地址校验信息。
示例性的，逻辑控制模块CTR还会对接收到的驱动数据进行更新，也即对驱动数据中的地址校验信息进行更新。驱动数据中的地址校验信息即为起始标识位和/或结束标识位的个数。将驱动数据的起始标识位的数目减1和/或结束标识位的个数加1，并通过其中继引脚Do将重编辑后的驱动数据输出给下一级驱动芯片的地址引脚Di。当然地，驱动芯片100还可以采用其他不同的函数以生成新的地址校验信息。
如上结构，发光基板200可以通过地址信号线20传输驱动数据，驱动数据包括地址校验信息以及与多个级联的驱动芯片对应的多个驱动信息。也即地址信号线20提供的驱动数据可以同时实现写入地址和输入驱动信息的作用。相对于分别利用地址信号线20实现写入数据，利用数据信号线实现输入驱动信息的方式，减少与驱动芯片100连接的信号线的数量，便于实现发光基板200的单层走线设计，降低发光基板200的工艺难度，降低成本。
在一些实施例中，请继续参阅图11，在测试信号线40被配置为能够分时传输测试信号和驱动数据的情况下，测试信号线40和第二电压线10分别采 用不同的信号线，可以简化驱动芯片100内部的电路结构，无需在驱动芯片100内设置电力调节电路(该电力调节电路用于基于电源信号中的直流分量生成驱动电压并基于电源信号中的调制分量生成驱动数据)，进而利于减小驱动芯片100的面积。另外，这种设置方式还可以简化外部电路结构，既可以避免设置将驱动电压和驱动数据调制成电力线载波通信的调制电路，还可以降低对驱动电压的品质要求。
在一些实施例中，请参阅图11所示，发光基板200还包括反馈信号线70，反馈信号线70与级联设置的最后一个驱动芯片100的中继引脚Do电连接。反馈信号线70靠近接地线50，位于接地线50和测试信号线40之间，可以防止反馈信号线70与其他信号线交叠，例如接地线50和测试信号线40。便于实现发光基板200的单层走线设计，降低发光基板200的工艺难度，降低成本。
图13为本公开的又一些实施例提供的一种发光基板的电路框图。
在一些实施例中，请参阅图13所示，驱动芯片100包括地址引脚Di、中继引脚Do、第一功能引脚Q1、第二功能引脚Q2、接地引脚GND、第一电源引脚V1和第二电源引脚V2。
驱动芯片100还包括4个输出引脚OUT。4个输出引脚OUT分别为第一输出引脚OUT1、第二输出引脚OUT2、第三输出引脚OUT3和第四输出引脚OUT4。
逻辑控制模块CTR包括四个调制模块，即第一调制模块PWMM1、第二调制模块PWMM2、第三调制模块PWMM3、第四调制模块PWMM4。逻辑控制模块CTR还包括控制单元CLM。
第一输出引脚OUT1～第四输出引脚OUT4与第一调制模块PWMM1～第四调制模块PWMM4一一对应地连接。控制单元CLM用于根据驱动数据生成第一驱动控制信号、第二驱动控制信号、第三驱动控制信号、第四驱动控制信号，并分别传输至第一调制模块PWMM1、第二调制模块PWMM2、第三调制模块PWMM3和第四调制模块PWMM4。
第一调制模块PWMM1与第一输出引脚OUT1电连接，并能够在第一驱动控制信号的控制下导通或者截止，使得第一输出引脚OUT1与接地引脚GND电连接的接地线50之间导通或者断开。
当第一调制模块PWMM1导通时，接地线50(如图11所示)、第一输出引脚OUT1、与第一输出引脚OUT1电连接的发光单元E(如图11所示)和第二电压线10(如图11所示)构成信号回路，发光单元E工作；当第一调 制模块PWMM1截止时，上述信号回路断开，发光单元E不工作。
如此，第一调制模块PWMM1可以在第一驱动控制信号的控制下对流经发光单元E的驱动电流进行相位调制，第一驱动控制信号为一种脉冲宽度调制信号。第一调制模块PWMM1可以根据第一驱动控制信号对流经发光单元E的驱动电流的时长进行调制，进而控制发光单元E的工作状态。当发光单元E含有LED时，通过增加第一驱动控制信号的占空比，可以提高LED在一个显示帧内的发光总时长，进而提高LED在该显示帧内的总发光亮度，使得发光基板200在该区域的亮度增大；反之，通过降低脉冲宽度调制信号的占空比，可以降低LED在一个显示帧内的发光总时长，进而降低LED在该显示帧内的总发光亮度，使得发光基板在该区域的亮度减小。
相应的，第二调制模块PWMM2与第二输出引脚OUT2电连接，并能够在第二驱动控制信号的控制下导通或者截止，第二驱动控制信号为一种脉冲宽度调制信号。第三调制模块PWMM3与第三输出引脚OUT3电连接，并能够在第三驱动控制信号的控制下导通或者截止，第三驱动控制信号为一种脉冲宽度调制信号。第四调制模块PWMM4与第四输出引脚OUT4电连接，并能够在第四驱动控制信号的控制下导通或者截止，第四驱动控制信号为一种脉冲宽度调制信号。
在一些实施例中，第一调制模块PWMM1～第四调制模块PWMM4可以为开关元件，例如可以为MOS(金属-氧化物半导体场效应晶体管)、TFT(薄膜晶体管)等晶体管；第一驱动控制信号～第四驱动控制信号可以为脉冲宽度调制信号，开关元件在脉冲宽度调制信号的控制下导通或者截止。
在一些实施例中，请继续参阅图13所示，当地址信号线20被配置为能够分时传输地址信号和驱动数据的情况下，第一调制模块PWMM1～第四调制模块PWMM4可以通过地址信号线20与控制单元CLM电连接，也可以分别通过地址信号线20与控制单元CLM电连接，亦或通过其他方式与控制模块CLM实现电连接。在测试信号线40被配置为能够分时传输测试信号和驱动数据的情况下，第一调制模块PWMM1～第四调制模块PWMM4可以通过测试信号线40与控制单元CLM电连接，也可以分别通过测试信号线40与控制单元CLM电连接，亦或通过其他方式与控制模块CLM实现电连接。本公开对此不做特殊的限制。
在一些实施例中，请继续参阅图13所示，逻辑控制模块CTR还可以包括第五调制模块PWMM5，第五调制模块PWMM5与中继引脚Do电连接。在地址引脚Di接收地址信号的情况下：控制单元CLM可以从地址引脚Di接 收地址信号，并根据地址信号生成并传输中继控制信号至第五调制模块PWMM5；第五调制模块PWMM5可以响应中继控制信号而生成一中继信号并加载至中继引脚Do。
本实施例中，第五调制模块PWMM5可以通过测试信号线40或地址信号线20与控制单元CLM电连接，也可以通过专用的数据走线与控制模块电连接，亦或还可以通过其他方式与控制模块实现电连接，本公开对此不做特殊的限制。
在一些实施例中，请继续参阅图13所示，当地址信号线20被配置为能够分时传输地址信号和驱动数据的情况下，第一调制模块PWMM1～第五调制模块PWMM5、控制单元CLM均与地址信号线20连接，进而使得地址信号线20与第一调制模块PWMM1～第五调制模块PWMM5进行交互。在测试信号线40被配置为能够分时传输测试信号和驱动数据的情况下，第一调制模块PWMM1～第五调制模块PWMM5、控制单元CLM均与测试信号线40连接，进而使得测试信号线40与第一调制模块PWMM1～第五调制模块PWMM5进行交互。
在一些示例中，第五调制模块PWMM5可以包括开关元件，例如可以包括MOS(金属-氧化物半导体场效应晶体管)、TFT(薄膜晶体管)等晶体管；中继控制信号可以为脉冲宽度调制信号，开关元件在脉冲宽度调制信号的控制下导通或者截止。当开关元件导通时，第五调制模块PWMM5可以输出电流或者电压，例如第五调制模块PWMM5产生一个脉冲宽度调制信号作为中继信号由中继引脚Do输出。当开关元件截止时，第五调制模块PWMM5不输出任何电信号(电流或者电压)。
在一些实施例中，逻辑控制模块CTR还可以包括电源模块PWRM，第一电源引脚V1可以将电源信号加载至电源模块PWRM，电源模块被配置将电力分配至驱动芯片100的各个电路中，以保障驱动芯片100的电力供应。第二电源引脚V2也可以与电源模块PWRM电连接，用于将电源信号向下一级驱动芯片100输出。
图14为图13中驱动芯片的一种电路框图。在一些实施例中，仅仅示出了第一调制模块PWMM1而未示出其他的调制模块。请参阅图14，在该示例中，驱动芯片100可以包括电压调节电路210、低压差稳压器230、振荡器240、控制单元CLM、地址驱动器260、调光电路270、晶体管275和亮度控制电路280。在各种实施方式中，驱动芯片100可以包括附加的、更少的或不同的部件。
电压调节电路210将在第一电源引脚V1处接收电源信号进行处理，以获得电源信号中的直流分量，以生成供电电压。在示例实施方式中，电压调节电路210包括跟随有源跟随器的一阶RC滤波器。供电电压被提供给低压差稳压器230。低压差稳压器230将供电电压转换为用于为振荡器240、控制单元CLM和其他部件(未示出)供电的稳定的直流电压(其可以逐步降低电压)。在示例实施方式中，稳定直流电压可以是1.8伏。振荡器240提供时钟信号，时钟信号的最大频率例如可以为10MHz左右。
控制单元CLM接收来第一功能引脚Q1的测试信号，测试信号包括测试数据和第一通用地址信息，第一通用地址信息可以匹配任意一个驱动芯片100的初始化地址信息。从而产生分别流经任一输出引脚OUT的测试电流。发光单元E接收测试电流发光。控制单元CLM经由第一功能引脚Q1接收测试信号，将该测试信号内的第一通用地址信息提供到地址驱动器260，地址驱动器260将第一通用地址信息缓存到第二功能引脚Q2中，向下一级驱动芯片100提供测试信号。
控制单元CLM接收来自数据引脚(第一功能引脚Q1)的驱动数据、来自低压差稳压器230的直流电压和来自振荡器240的时钟信号。取决于发光基板的工作阶段，控制单元CLM还可以从在地址引脚Di处接收的地址信号中接收数字数据；控制单元CLM可以输出使能信号252、递增的数据信号254、PWM时钟选择信号256和最大电流信号258。控制单元CLM激活使能信号252以启用地址驱动器260。控制单元CLM经由地址引脚Di接收地址信号，储存该地址，并且将表示传出地址的递增后的数据信号254提供到地址驱动器260。当在地址配置阶段使能信号252被激活的情况下，地址驱动器260将递增后的数据信号254缓存到中继引脚Do。控制单元CLM可以控制调光电路270以关断晶体管275以有效地阻断来自发光单元的电流路径。
控制单元CLM还能将使能信号252去激活并且地址驱动器260的输出是三态以有效地将其从中继引脚Do解耦。PWM时钟选择信号256指定用于由PWM调光电路270控制PWM调光的占空比。基于所选择的占空比，PWM调光电路270控制晶体管275的导通状态和截止状态的定时。在晶体管275的导通状态期间，建立通过晶体管275从输出引脚OUT(耦接至器件单元，图14中以OUT1为示例)到接地引脚GND的电流路径，并且亮度控制电路280汇集经过发光单元的驱动器电流。在晶体管275的截止状态期间，电流路径被中断以阻止电流流过发光单元。当晶体管275处于导通状态时，亮度控制电路280从控制单元CLM接收最大电流信号258并且控制流过发光单元(从 输出引脚OUT至接地引脚GND)的电流幅值。控制单元CLM控制PWM调光电路270的占空比和亮度控制电路280的最大电流258以将发光单元的LED设置为期望亮度。
可以理解的是，驱动芯片100中还可以包括压控恒流电路(图中未示出)，压控恒流电路的输入参考电压和输入参考电流，可以由第一电源引脚V1处接收电源信号生成。压控恒流电路可以与亮度控制电路280电连接。
在一些实施例中，请继续参阅图14，在调制模块中设置有短路检测器和断路检测器，其中，断路检测器由虚断方式连接的运算放大器构成，用于检测器件单元与驱动芯片100之间是否发生断路，其中，Vopen端可以为悬空信号端。短路检测器由虚短方式连接的运算放大器构成，来检测器件单元与驱动芯片100之间是否发生短路，其中，Vshort的电位可以与第二电压线10传输的驱动数据的电位相同。
在一些实施例中，请继续参阅图14所示，驱动芯片100还包括与数据选择器MUX和模数转换器ADC。驱动芯片100通过多个输出引脚OUT在与对应连接发光单元和第二电压线10构成信号回路时，可以将多个信号回路的电信号传输给数据选择器MUX，并分时依次经由模数转换器ADC处理后传递给控制单元CLM，再通过该驱动芯片100的中继引脚Do(例如将多个信号回路的电信号按照顺序以及编码规则附加在数据信号254的后面)，逐级传输，直至由最后一级的驱动芯片100的中继引脚Do输出，并通过反馈信号线70连接到外部电路。外部电路可以对反馈信息进行响应，调节其所输出的信号电平，进而降低发光基板的功耗。
在一些实施例中，请继续参阅图14所示，驱动芯片100还可以设置有热关断延迟传感器TSD和热关断延迟(Thermal Shutdown)控制器TS。热关断延迟传感器TSD用于检测驱动芯片100的内部温度。当驱动芯片100的内部温度达到预设的保护温度(一般设置在150℃～170℃之间)时，热关断延迟控制器TS工作以关闭驱动芯片100的输出，降低驱动芯片100的功耗，进而降低驱动芯片100的内部温度。当驱动芯片100的内部温度降低至预设的重启温度(重启温度＝保护温度-延迟温度)时，驱动芯片100将重新输出。其中，延迟温度一般设置在15～30°范围内。热关断延迟(Thermal Shutdown)控制器TS可以与数据选择器MUX相连接，进而可以通过数据选择器MUX将异常信息反馈给控制单元CLM，以控制驱动芯片100的工作状态。
图15为图13中驱动芯片的又一种电路框图。在又一些实施例中，请参阅图15所示，控制单元CLM接收来第一功能引脚Q1的测试信号，测试信号 包括开关信号。开关信号用于控制控制单元CLM，产生分别流经任一输出引脚OUT的测试电流。发光单元E接收测试电流发光。并且，控制单元CLM经由第一功能引脚Q1接收测试信号，将该测试信号发送至第二功能引脚Q2，第二功能引脚Q2能够向下一级驱动芯片100输出测试信号。
控制单元CLM接收来自数据引脚(或地址引脚Di)的驱动数据、来自低压差稳压器230的直流电压和来自振荡器240的时钟信号。取决于发光基板的工作阶段，控制单元CLM还可以从在地址引脚Di处接收的地址信号中接收数字数据；控制单元CLM可以输出使能信号252、递增的数据信号254、PWM时钟选择信号256和最大电流信号258。控制单元CLM激活使能信号252以启用地址驱动器260。控制单元CLM经由地址引脚Di接收地址信号，储存该地址，并且将表示传出地址的递增后的数据信号254提供到地址驱动器260。当在地址配置阶段使能信号252被激活的情况下，地址驱动器260将递增后的数据信号254缓存到中继引脚Do。控制单元CLM可以控制调光电路270以关断晶体管275以有效地阻断来自发光单元的电流路径。
图16为本公开的一些实施例提供的一种发光基板的检测方法的流程图。本公开一些实施例提供一种发光基板200的测试方法。发光基板200为上述任一实施例的发光基板200。器件组O包括至少一个发光单元E。请参阅图16所示，测试方法包括：
S1：向各个驱动芯片的第一功能引脚输入测试信号，以使各个驱动芯片的逻辑控制模块根据测试信号产生分别流经任一输出引脚的测试电流。判断与任一驱动芯片电连接的器件组的发光状态。若正常发光，则确定该器件组与对应的驱动芯片连接正常。若不发光或异常发光，则确定该器件组与对应的驱动芯片连接异常。
在S1步骤中：
S1a：向各个驱动芯片100的第一功能引脚Q1输入测试信号，以使各个驱动芯片的逻辑控制模块根据测试信号产生分别流经任一输出引脚的测试电流。
该测试电流可以驱动器件组O中的发光单元E发光。
S1b：判断与任一驱动芯片100电连接的器件组O的发光状态。
根据器件组O中的发光单元E的发光状态，从而可以判断发光单元E的连接情况。其中，发光状态可以包括正常发光、异常发光和不发光。
若器件组O正常发光，则进行S1c步骤：确定该器件组O与对应的驱动芯片100连接正常。若器件组O中的发光单元E正常发光，则该发光单元E 与对应的驱动芯片100连接正常。由此可知，该器件组O/发光单元E无需进行返修。
其中，正常发光代表发光单元E的发光亮度达到阈值亮度。阈值亮度可以根据实际情况具体设置。
若器件组O不发光或异常发光，则进行S1d步骤：确定该器件组O与对应的驱动芯片100连接异常。若器件组O中的发光单元E不发光或异常发光，则确定发光单元E与对应的驱动芯片100连接异常。
例如，若器件组O/发光单元E不发光，则可以判定器件组O/发光单元E与其连接的驱动芯片断开，需对该器件组O/发光单元E进行检修，重新焊接，使其可以与驱动芯片正常导通连接，且正常发光。
例如，若器件组O/发光单元E异常发光，则可以判定器件组O/发光单元E可能发生虚焊的情况，需对器件组O/发光单元E进行检修，重新焊接，使其可以与驱动芯片正常导通连接，且正常发光。
其中，异常发光代表发光单元E的发光亮度低于阈值亮度。阈值亮度可以根据实际情况具体设置。
如上测试方法，向各个驱动芯片100的第一功能引脚Q1输入测试信号，从而可以通过一步检测操作实现对各个驱动芯片100电连接的发光单元E的点亮测试，有利于提高驱动芯片100的检修效率。
图17为本公开的再一些实施例提供的一种发光基板的检测方法的流程图。
在一些实施例中，请参阅图17，以及结合图12所示，在S1A中，包括：
S1Aa：向各个驱动芯片的第一功能引脚输入开关信号。开关信号用于控制逻辑控制模块产生分别流经任一输出引脚的测试电流，以使各个驱动芯片的逻辑控制模块根据测试信号产生分别流经任一输出引脚的测试电流。
S1Ab：判断与任一驱动芯片100电连接的器件组O的发光状态。
若器件组O正常发光，则进行S1Ac步骤：确定该器件组O与对应的驱动芯片100连接正常。若器件组O中的发光单元E正常发光，则该发光单元E与对应的驱动芯片100连接正常。由此可知，该器件组O/发光单元E无需进行返修。
若器件组O不发光或异常发光，则进行S1Ad步骤：确定该器件组O与对应的驱动芯片100连接异常。若器件组O中的发光单元E不发光或异常发光，则确定发光单元E与对应的驱动芯片100连接异常。
如上测试方法，向各个驱动芯片100的第一功能引脚Q1输入测试信号， 从而可以通过一步检测操作实现对各个驱动芯片100电连接的发光单元E的点亮测试，有利于提高驱动芯片100的检修效率。
本实施例中，测试信号包括开关信号。开关线号用于控制逻辑控制模块CTR，产生分别流经任一输出引脚OUT的测试电流。也即可以控制与该驱动芯片100电连接的发光单元E均可以接收测试电流。并且由于第二功能引脚Q2与该级驱动芯片和下一级驱动芯片的第一功能引脚Q1直接连接，从而每一级驱动芯片100都可以接收相同的测试信号。由此，可以通过一步检测操作实现对各个驱动芯片100电连接的发光单元E的点亮测试。如发光单元E未发光，则可判定该发光单元E存在问题，有效的提高驱动芯片100的检修效率。在一些示例中，测试信号可以为高电平信号或低电平信号。只要可以通过该测试信号控制逻辑控制模块CTR产生分别流经任一输出引脚OUT的测试电流即可。
图18为本公开的再一些实施例提供的一种发光基板的检测方法的流程图。
在一些实施例中，请参阅图18，以及结合图12所示，测试方法还包括：
S01：向多个级联的驱动芯片中的第一个驱动芯片的地址引脚输入驱动数据，驱动数据包括地址校验信息以及与多个级联的驱动芯片对应的多个驱动信息。其中，驱动芯片根据地址校验信息，配置与当前的驱动芯片对应的一个驱动信息。并根据驱动信息，生成与驱动芯片连接的器件组所对应的驱动电流。以及，驱动芯片对地址校验信息进行更新，生成包含更新后的地址校验信息的驱动数据，并向下一级驱动芯片输出包含更新后的地址校验信息的驱动数据。判断与多个级联的驱动芯片的连接的器件组中，是否存在不发光的器件组。若是，则按照级联顺序，确定与第一个不发光的器件组连接的驱动芯片存在异常。若否，则确定多个级联的驱动芯片不存在异常。
在S01步骤中：
S01a：向多个级联的驱动芯片100中的第一个驱动芯片的地址引脚Di输入驱动数据，驱动数据包括地址校验信息以及与多个级联的驱动芯片对应的多个驱动信息。其中，驱动芯片100根据地址校验信息，配置与当前的驱动芯片100对应的一个驱动信息。并根据驱动信息，生成与驱动芯片100连接的器件组O所对应的驱动电流。以及，驱动芯片100对地址校验信息进行更新，生成包含更新后的地址校验信息的驱动数据，并向下一级驱动芯片100输出包含更新后的地址校验信息的驱动数据。
S01b：判断与多个级联的驱动芯片100的连接的器件组O中，是否存在 不发光的器件组O。
若否，则进行S01c步骤：确定多个级联的驱动芯片100不存在异常。无需对该驱动芯片100进行检修。
若是，则进行S01d步骤：按照级联顺序，确定与第一个不发光的器件组O连接的驱动芯片100存在异常。需对该驱动芯片100的地址引脚Di和中继引脚Do进行检修，判断其是否焊接正常。修复后，使该驱动芯片100连接的器件组O正常发光。
在一些示例中，可以继续进行S01步骤，用于判定剩余驱动芯片100是否存在异常。直至所有驱动芯片100连接的器件组O均可以正常发光。
在上述一些实施例的基础上，可利用S01a步骤驱动发光基板200正常发光。
在一些实施例中，测试方法可以包括上述S1A步骤和S01步骤。利用S1A步骤对驱动芯片100连接的发光元件O进行测试，利用S01步骤对多个驱动芯片100的级联情况进行检测，有利于提高发光基板200的检修效率。
在一些示例中，可以先进行S01步骤，再进行S1A步骤。或者，测试方法可以先进行SA1步骤，再进行S01步骤。本公开对此不做限定。
图19为本公开的又一些实施例提供的一种发光基板的检测方法的流程图。
在一些实施例中，请结合图19，以及结合图12所示，在S1B中，包括：
S1Ba：向各个驱动芯片的第一功能引脚输入包括测试数据和第一通用地址信息的测试信号。第一通用地址信息能够匹配任意一个驱动芯片的初始化地址信息。以使各个驱动芯片的逻辑控制模块根据测试信号产生分别流经任一输出引脚的测试电流。
S1Bb：判断与任一驱动芯片100电连接的器件组O的发光状态。
若器件组O正常发光，则进行S1Bc步骤：确定该器件组O与对应的驱动芯片100连接正常。若器件组O中的发光单元E正常发光，则该发光单元E与对应的驱动芯片100连接正常。由此可知，该器件组O/发光单元E无需进行返修。
若器件组O不发光或异常发光，则进行S1Bd步骤：确定该器件组O与对应的驱动芯片100连接异常。若器件组O中的发光单元E不发光或异常发光，则确定发光单元E与对应的驱动芯片100连接异常。
如上测试方法，向各个驱动芯片100的第一功能引脚Q1输入测试信号，从而可以通过一步检测操作实现对各个驱动芯片100电连接的发光单元E的 点亮测试，有利于提高驱动芯片100的检修效率。
本实施例中，测试信号包括测试数据和第一通用地址信息，第一通用地址信息可以匹配任意一个驱动芯片100的初始化地址信息，产生分别流经任一输出引脚OUT的测试电流。发光单元E接收测试电流发光。由于第一通用地址信息可以匹配任意一个驱动芯片的初始化地址信息，也即该测试信号可以同时驱动各个驱动芯片100电连接的发光单元E发光。如发光单元E未发光，则可判定该发光单元E存在问题。由此，可以通过一步检测操作实现对各个驱动芯片100电连接的发光单元E的点亮测试，从而有效的提高驱动芯片100的检修效率。
图20为本公开的又一些实施例提供的一种发光基板的检测方法的流程图。
在一些实施例中，请参阅图20，以及结合图12所示，测试方法还包括：
S10A：向多个级联的驱动芯片中的第一个驱动芯片的地址引脚输入地址信号。驱动芯片根据地址信号配置驱动芯片的地址信息，并生成中继信号，中继引脚向下一级驱动芯片输出中继信号。其中，中继信号与地址信号相同。也即，更新后的地址信息相同(对初始化信息更新后的地址信息相同)。
在一些示例中，地址信号可以为数字信号。当一个驱动芯片100接收地址信号后，可以解析并获得、存储该地址信号中的地址信号，还可以使地址信号递增0的地址信号(新的地址信号)调制为中继信号，该中继信号作为下一级驱动芯片100的地址信号。使中继信号与地址信号相同。当然地，驱动芯片100还可以采用其他不同的函数以生成新的地址信号。
在S10A步骤之后还可以包括S1B1步骤，此时S1B1步骤用于判定多个级联设置的驱动芯片100是否存在异常。S1B1包括：
S1B1a：向各个驱动芯片的第一功能引脚输入包括测试数据和第二通用地址信息的测试信号。第二通用地址信息能够匹配任意一个驱动芯片的更新后的地址信息(对初始化信息更新后的地址信息)。以使各个驱动芯片的逻辑控制模块根据测试信号产生分别流经任一输出引脚的测试电流。
S1B1b：判断与多个级联的驱动芯片的连接的器件组中，是否存在不发光的器件组。
若否，则进行S1B1c步骤：确定多个级联的驱动芯片不存在异常。则该发光单元E连接的驱动芯片100中的地址引脚Di和中继引脚Do焊接正常。由此可知，该驱动芯片100无需进行返修。
若是，则进行S1B1d步骤：按照级联顺序，确定与第一个不发光的器件 组连接的驱动芯片存在异常。也即该驱动芯片100中的地址引脚Di和中继引脚Do焊接异常。由此可知，该驱动芯片100需进行返修。
基于此，可以根据各个驱动芯片100电连接全部发光元件E是否发光进行判断。如从某一个驱动芯片100开始，后续驱动芯片100电连接的发光元件E均未发光，则可以判定该驱动芯片100的地址引脚Di和中继引脚Do焊接出现问题，需要对其进行返修。
在一些实施例中，测试方法包括S1B步骤和S10A和S1B1步骤。由于每个驱动芯片100在出厂时均会设置初始化地址信息。先利用S1B步骤中，测试信号中第一通用地址信息匹配任意一个驱动芯片100中的初始化地址信息，使每个驱动芯片100的逻辑控制模块产生分别流经任一输出引脚OUT的测试电流，器件组O接收测试电流发光。根据器件组O中的发光单元E是否发光，判定发光单元E是否焊接正常。再利用S10A步骤，对初始化地址信息进行更新，得到更新后的地址信息，更新后的地址信息相同。再利用S1B1步骤中测试信号中的第二通用地址信息，第二通用地址信息能够匹配任意一个驱动芯片的更新后的地址信息，使每个驱动芯片100的逻辑控制模块产生分别流经任一输出引脚OUT的测试电流，器件组O接收测试电流发光。如从某一个器件组O开始均未发光，可以得知，未发光的器件组O连接的驱动芯片100中初始化地址信息未被更新为与第二通用地址信息匹配的地址信息，所以，该驱动芯片100存在异常，也即该驱动芯片100中用于接收更新后地址信息的地址引脚Di和中继引脚Do可能存在焊接异常的问题。记录，S1B步骤异常发光单元E的坐标和S1B1步骤中异常驱动芯片100的坐标，同步进行检修，有利于提高发光基板200的检修效率。
图21为本公开的又一些实施例提供的一种发光基板的检测方法的流程图。
在一些实施例中，驱动芯片100的第一功能引脚Q1分时接收测试信号和驱动数据。请参阅图21，以及结合图12所示，测试方法还包括：
S10B：向多个级联的驱动芯片中的第一个驱动芯片的地址引脚输入地址信号，驱动芯片根据地址信号配置驱动芯片的地址信息，并生成中继信号，中继引脚向下一级驱动芯片输出中继信号。其中，中继信号与地址信号不同。
在S10B步骤中，向多个级联的驱动芯片100的地址引脚Di输入地址信号，驱动芯片100根据地址信号配置驱动芯片100的地址信息，并生成中继信号，中继引脚Do能够向下一级驱动芯片100输出中继信号。在S01步骤中对各个驱动芯片100写入地址。其中，中继信号与地址信号不同。
在一些示例中，地址信号可以为数字信号。当一个驱动芯片100接收地址信号后，可以解析并获得、存储该地址信号中的地址信号，还可以使地址信号递增1或另一非0固定量并将递增后的地址信号(新的地址信号)调制为中继信号，该中继信号作为下一级驱动芯片100的地址信号。使得中继信号与地址信号不同。当然地，驱动芯片100还可以采用其他不同的函数以生成新的地址信号。
S11：向多个级联的驱动芯片中的各个驱动芯片的第一功能引脚输入驱动数据，驱动数据包括多个地址验证信息以及与多个地址验证信息对应的多个驱动信息；对于任一个驱动芯片：当地址验证信息和驱动芯片的地址信息匹配时，逻辑控制模块根据地址验证信息，接收对应的驱动信息，并根据所接收的驱动信息，生成与至少一个输出引脚对应的驱动电流。判断与多个级联的驱动芯片的连接的器件组中，是否存在不发光的器件组。若是，则按照级联顺序，确定与第一个不发光的器件组连接的驱动芯片存在异常。若否，则确定多个级联的驱动芯片不存在异常。
在S11步骤中：
S11a：向多个级联的驱动芯片中的各个驱动芯片的第一功能引脚输入驱动数据，驱动数据包括多个地址验证信息以及与多个地址验证信息对应的多个驱动信息；对于任一个驱动芯片100：当地址验证信息和驱动芯片100的地址信息匹配时，逻辑控制模块根据地址验证信息，接收对应的驱动信息，并根据所接收的驱动信息，生成与至少一个输出引脚OUT对应的驱动电流。
S11b：判断与多个级联的驱动芯片100的连接的器件组O中，是否存在不发光的器件组O。
若否，则进行S11c步骤：确定多个级联的驱动芯片100不存在异常。无需对该驱动芯片100进行检修。
若是，则进行S11d步骤：按照级联顺序，确定与第一个不发光的器件组O连接的驱动芯片100存在异常。需对该驱动芯片100的地址引脚Di和中继引脚Do进行检修，判断其是否焊接正常。修复后，使该驱动芯片100连接的器件组O正常发光。
在一些示例中，可以继续进行S11步骤，用于判定剩余驱动芯片100是否存在异常。直至所有驱动芯片100连接的器件组O均可以正常发光。
在上述一些实施例的基础上，可利用S10B和S11a步骤驱动发光基板200正常发光。
在一些实施例中，测试方法可以包括上述S1B步骤、S10B和S11步骤。 利用S1B步骤对驱动芯片100连接的发光元件O进行测试，利用S10B和S11步骤对多个驱动芯片100的级联情况进行检测，有利于进一步提高发光基板200的检修效率。
在一些示例中，测试方法可以先进行S1B步骤，再进行S10B、S11步骤。
综上所述，本公开一些实施例提供了驱动芯片100、发光基板200和显示装置300，还提供了一种发光基板的检测方法，通过优化驱动芯片100的结构，例如包括第一功能引脚Q1和第二功能引脚Q2。向各个驱动芯片100的第一功能引脚Q1输入测试信号。根据测试信号，产生分别流经任一输出引脚OUT的测试电流。第一功能引脚Q1和第二功能引脚Q2电连接。第二功能引脚Q2能够向下一级驱动芯片100输出测试信号。可以通过一步检测操作实现对各个驱动芯片100电连接的发光单元E的点亮测试。如发光单元E未发光，则可判定该发光单元E存在问题，有效的提高驱动芯片100的检修效率。具有该驱动芯片100的发光基板200，具有发光基板200的显示装置300，以及该驱动芯片100的检测方法，均具有上述任意实施例中驱动芯片100具有的有益效果，在此不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 一种驱动芯片，包括：
    逻辑控制模块；
    至少一个输出引脚，与所述逻辑控制模块电连接；
    第一功能引脚，与所述逻辑控制模块电连接；所述第一功能引脚能够接收测试信号；所述逻辑控制模块被配置为：根据所述测试信号，产生分别流经任一所述输出引脚的测试电流。
  2. 根据权利要求1所述的驱动芯片，其中，
    所述测试信号包括开关信号；所述开关信号用于控制所述逻辑控制模块产生分别流经任一所述输出引脚的测试电流。
  3. 根据权利要求1或2所述的驱动芯片，还包括地址引脚和中继引脚；
    所述地址引脚与所述逻辑控制模块电连接；所述地址引脚能够接收驱动数据；所述驱动数据包括地址校验信息以及与多个级联的驱动芯片对应的多个驱动信息；
    所述逻辑控制模块被配置为：根据所述地址校验信息，获取与当前的所述驱动芯片对应的一个驱动信息；以及，对所述地址校验信息进行更新，生成包含更新后的地址校验信息的驱动数据；
    所述中继引脚与所述逻辑控制模块电连接；所述中继引脚能够输出所述包含更新后的地址校验信息的驱动数据。
  4. 根据权利要求1所述的驱动芯片，其中，
    所述测试信号包括测试数据和通用地址信息，所述通用地址信息能够匹配任意一个所述驱动芯片的地址信息；
    所述逻辑控制模块被配置为：根据所述测试数据，产生分别流经任一所述输出引脚的测试电流。
  5. 根据权利要求1或4所述的驱动芯片，还包括：
    地址引脚，与所述逻辑控制模块电连接；所述地址引脚能够接收地址信号；所述逻辑控制模块被配置为：根据所述地址信号配置所述驱动芯片的地址信息，并生成中继信号；
    中继引脚，与所述逻辑控制模块电连接；所述中继引脚能够输出所述中继信号；
    所述第一功能引脚还能够接收驱动数据；所述驱动数据包括多个地址验证信息以及与多个地址验证信息对应的多个驱动信息；
    所述逻辑控制模块被配置为：当所述地址验证信息和所述驱动芯片的地 址信息匹配时，根据所述地址验证信息，接收对应的驱动信息，并根据所接收的驱动信息，生成与所述至少一个输出引脚对应的驱动电流。
  6. 根据权利要求1～5中任一项所述的驱动芯片，还包括：
    第二功能引脚和第一连接线；所述第二功能引脚通过所述第一连接线与所述第一功能引脚相连；所述第二功能引脚能够输出测试信号；
    所述驱动芯片具有相互平行的第一边缘和第二边缘；
    所述第一功能引脚和所述第二功能引脚中，一个靠近所述第一边缘，另一个靠近所述第二边缘。
  7. 根据权利要求6所述的驱动芯片，其中，所述驱动芯片还具有位于所述第一边缘的第一端与所述第二边缘的第一端之间的第三边缘；
    在所述驱动芯片包括地址引脚和中继引脚的情形下：
    所述地址引脚和所述中继引脚中，一个靠近所述第一边缘，另一个靠近所述第二边缘；
    所述地址引脚和所述中继引脚，相对于所述第一功能引脚和所述第二功能引脚，更靠近所述第三边缘。
  8. 根据权利要求7所述的驱动芯片，还包括：
    至少一个接地引脚，与所述逻辑控制模块电连接；所述接地引脚能够接收接地信号；所述接地引脚位于地址引脚和所述中继引脚之间。
  9. 根据权利要求7或8所述的驱动芯片，还包括：
    第一电源引脚，与所述逻辑控制模块电连接；所述第一电源引脚能够接收电源信号；所述第一电源引脚靠近所述第一边缘或所述第二边缘。
  10. 根据权利要求9所述的驱动芯片，还包括：
    第二电源引脚和第二连接线，所述第二电源引脚通过所述第二连接线与所述第一电源引脚相连；所述第二电源引脚能够输出所述电源信号；
    其中，所述第一电源引脚和所述第二电源引脚中，一个靠近所述第一边缘，另一个靠近所述第二边缘；
    所述第一电源引脚和所述第二电源引脚，相对于所述地址引脚和所述中继引脚，更远离所述第三边缘。
  11. 根据权利要求6～10中任一项所述的驱动芯片，其中，
    所述驱动芯片还具有位于所述第一边缘的第二端与所述第二边缘的第二端之间的第四边缘；
    所述输出引脚的数量为多个，多个所述输出引脚靠近所述第四边缘，且多个所述输出引脚沿所述第四边缘的延伸方向排列。
  12. 一种发光基板，包括：
    多个级联的驱动芯片，所述驱动芯片为权利要求1～11中任一项所述的驱动芯片；
    多个器件组，一个器件组的第一端与一个驱动芯片的至少一个输出引脚对应电连接。
  13. 根据权利要求12所述的发光基板，其中，在所述驱动芯片还包括地址引脚、中继引脚、第一电源引脚和至少一个接地引脚的情形下：
    位于上一级的所述驱动芯片的中继引脚与位于下一级的驱动芯片的地址引脚电连接；
    所述发光基板还包括：导电层；所述导电层中包括：
    第二电压线，与各个所述器件组的第二端电连接；
    地址信号线，与第一个所述驱动芯片的地址引脚电连接；
    第一电压线，与第一个所述驱动芯片的第一电源引脚电连接；
    测试信号线，与第一个所述驱动芯片的第一功能引脚电连接；以及
    接地线，与各个所述驱动芯片的至少一个接地引脚电连接；
    其中，所述第二电压线、所述地址信号线、所述第一电压线、所述测试信号线以及接地线之间无交叠。
  14. 根据权利要求12或13所述的发光基板，其中，在所述驱动芯片还包括第二功能引脚的情况下：
    所述第二功能引脚分别与本级的所述驱动芯片的第一功能引脚，和下一级的所述驱动芯片的第一功能引脚电连接。
  15. 根据权利要求12～14中任一项所述的发光基板，其中，在所述驱动芯片还包括第二电源引脚的情形下：
    所述第二电源引脚分别与本级的所述驱动芯片的第一电源引脚，和下一级的所述驱动芯片的第一电源引脚电连接。
  16. 根据权利要求13～15中任一项所述的发光基板，其中，
    所述地址信号线被配置为传输地址信号，所述测试信号线被配置为分时传输测试信号和驱动数据；或，所述地址信号线被配置为传输驱动数据，所述测试信号线被配置为传输测试信号。
  17. 一种发光基板的测试方法，其中，所述发光基板为权利要求12～16中任一项所述的发光基板；
    所述测试方法包括：
    向各个驱动芯片的第一功能引脚输入测试信号；以使各个所述驱动芯片 的逻辑控制模块根据所述测试信号，产生分别流经任一输出引脚的测试电流；
    判断与任一所述驱动芯片电连接的器件组的发光状态；若正常发光，则确定该器件组与对应的驱动芯片连接正常；若不发光或异常发光，则确定该器件组与对应的驱动芯片连接异常。
  18. 根据权利要求17所述的测试方法，其中，所述向各个驱动芯片的第一功能引脚输入测试信号，包括：
    向各个驱动芯片的第一功能引脚输入开关信号，所述开关信号用于控制所述逻辑控制模块产生分别流经任一输出引脚的测试电流。
  19. 根据权利要求17或18所述的测试方法，还包括：
    向多个级联的驱动芯片中的第一个驱动芯片的地址引脚输入驱动数据，驱动数据包括地址校验信息以及与多个级联的驱动芯片对应的多个驱动信息；其中，驱动芯片根据地址校验信息，配置与当前的驱动芯片对应的一个驱动信息；并根据驱动信息，生成与驱动芯片连接的器件组所对应的驱动电流；以及，驱动芯片对所述地址校验信息进行更新，生成包含更新后的地址校验信息的驱动数据，并向下一级驱动芯片输出所述包含更新后的地址校验信息的驱动数据；
    判断与多个级联的驱动芯片的连接的器件组中，是否存在不发光的器件组；若是，则按照级联顺序，确定与第一个不发光的器件组连接的驱动芯片存在异常；若否，则确定所述多个级联的驱动芯片不存在异常。
  20. 根据权利要求17所述的测试方法，其中，所述向各个驱动芯片的第一功能引脚输入测试信号，包括：
    向各个驱动芯片的第一功能引脚输入包括测试数据和第一通用地址信息的测试信号；所述第一通用地址信息能够匹配任意一个所述驱动芯片的初始化地址信息。
  21. 根据权利要求17或20所述的测试方法，还包括：
    向多个级联的驱动芯片中的第一个驱动芯片的地址引脚输入地址信号；所述驱动芯片根据地址信号配置驱动芯片的地址信息，并生成中继信号，中继引脚向下一级驱动芯片输出所述中继信号；其中，所述中继信号与所述地址信号相同；
    所述测试方法还包括：
    向各个驱动芯片的第一功能引脚输入包括测试数据和第二通用地址信息的测试信号；所述第二通用地址信息能够匹配任意一个所述驱动芯片更新后的地址信息；以使各个所述驱动芯片的逻辑控制模块根据所述测试信号，产 生分别流经任一输出引脚的测试电流；
    判断与多个级联的驱动芯片的连接的器件组中，是否存在不发光的器件组；若是，则按照级联顺序，确定与第一个不发光的器件组连接的驱动芯片存在异常；若否，则确定所述多个级联的驱动芯片不存在异常。
  22. 根据权利要求17或20所述的测试方法，还包括：
    向多个级联的驱动芯片中的第一个驱动芯片的地址引脚输入地址信号，所述驱动芯片根据地址信号配置驱动芯片的地址信息，并生成中继信号，中继引脚向下一级驱动芯片输出所述中继信号；其中，所述中继信号与所述地址信号不同；
    向多个级联的驱动芯片中的各个驱动芯片的第一功能引脚输入驱动数据，驱动数据包括多个地址验证信息以及与多个地址验证信息对应的多个驱动信息；对于任一个所述驱动芯片：当所述地址验证信息和所述驱动芯片的地址信息匹配时，所述逻辑控制模块根据所述地址验证信息，接收对应的驱动信息，并根据所接收的驱动信息，生成与所述至少一个输出引脚对应的驱动电流；
    判断与多个级联的驱动芯片的连接的器件组中，是否存在不发光的器件组；若是，则按照级联顺序，确定与第一个不发光的器件组连接的驱动芯片存在异常；若否，则确定所述多个级联的驱动芯片不存在异常。
  23. 一种显示装置，包括：如权利要求12～16中任一项所述的发光基板。
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