WO2024007356A1 - 一种半导体结构、封装器件及半导体结构的制造方法 - Google Patents

一种半导体结构、封装器件及半导体结构的制造方法 Download PDF

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Publication number
WO2024007356A1
WO2024007356A1 PCT/CN2022/105548 CN2022105548W WO2024007356A1 WO 2024007356 A1 WO2024007356 A1 WO 2024007356A1 CN 2022105548 W CN2022105548 W CN 2022105548W WO 2024007356 A1 WO2024007356 A1 WO 2024007356A1
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sub
bonding pad
semiconductor structure
dielectric layer
covering
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English (en)
French (fr)
Inventor
卢宗正
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US18/157,079 priority Critical patent/US20240006281A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure, a packaging device, and a manufacturing method of the semiconductor structure.
  • a semiconductor structure such as a packaging substrate, usually includes a substrate.
  • the surface of the substrate is provided with bonding pads and signal transmission lines located between the bonding pads.
  • the bonding pads are used for soldering solder balls.
  • solder pad and the solder ball occupy a larger area on the substrate surface, squeezing the area occupied by the signal transmission line on the substrate surface, making Signal transmission lines are designed to be thin and prone to breakage. In order to avoid soldering pads, signal transmission lines often have long windings, causing signal integrity problems.
  • Embodiments of the present disclosure provide a semiconductor structure, including:
  • the substrate including a first surface
  • a first bonding pad located on the first surface
  • a solder ball is located on the second sub-section.
  • the orthographic projection of the solder ball on the first surface completely overlaps the orthographic projection of the second sub-portion on the first surface, or the solder ball is on the first surface.
  • the orthographic projection on the surface falls within the orthographic projection of the second sub-portion on the first surface.
  • the orthographic projection of the first sub-portion on the first surface completely overlaps the orthographic projection of the first bonding pad on the first surface, or the first sub-portion is on The orthographic projection on the first surface falls within the orthographic projection of the first bonding pad on the first surface.
  • the width of the first sub-portion gradually increases in a direction perpendicular to the first surface and directed from the first bonding pad to the second sub-portion.
  • the semiconductor structure further includes a composite reinforcement layer located between the first sub-portion and the first bonding pad.
  • the semiconductor structure further includes a solderable layer located between the solder ball and the second sub-portion.
  • the semiconductor structure further includes: a transmission line located on the first surface; a dielectric layer covering the transmission line and filling between the first bonding pad and the transmission line a gap between; wherein, a first opening exposing the first bonding pad is formed in the dielectric layer, the first sub-portion is located in the first opening, and the second sub-portion covers the first A sub-section and part of the dielectric layer.
  • the semiconductor structure further includes: a plurality of second bonding pads located on a second surface of the substrate opposite to the first surface, and the dielectric layer further fills the plurality of second bonding pads. Gaps between bonding pads; wherein a plurality of second openings are formed in the dielectric layer, and the second openings expose the second bonding pads.
  • Embodiments of the present disclosure also provide a packaged device, which includes: at least one chip and any semiconductor structure as described above, and the at least one chip is bonded and connected to the semiconductor structure.
  • An embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, including:
  • the substrate including a first surface
  • a transition portion is formed on the first bonding pad, the transition portion includes a first sub-portion covering the first bonding pad and a second sub-portion covering the first sub-portion, wherein the first The orthographic projection of the sub-portion and the first bonding pad on the first surface falls within the orthographic projection of the second sub-portion on the first surface;
  • a solder ball is formed on the second sub-portion.
  • forming a first bonding pad on the first surface includes:
  • first conductive material layer Forming a first conductive material layer, the first conductive material layer covering at least the first surface
  • the first conductive material layer covering the first surface is etched to form the first bonding pad and transmission line on the first surface.
  • the method before forming the transition portion on the first bonding pad, the method further includes:
  • a dielectric layer is formed.
  • the dielectric layer at least covers the first bonding pad and the transmission line and fills the gap between the first bonding pad and the transmission line.
  • a transition portion is formed on the first bonding pad, the transition portion includes a first sub-portion covering the first bonding pad and a second sub-portion covering the first sub-portion, include:
  • the method before forming the second conductive material layer on the first surface, the method further includes: forming a composite reinforcement layer in the first opening, the composite reinforcement layer covering the first welding layer. pad.
  • the method before forming the solder ball, the method further includes forming a solderable layer covering a surface of the second sub-section to be electrically connected to the solder ball.
  • forming a first conductive material layer that covers at least the first surface includes: forming a first conductive material layer that covers the first surface and a second surface of the substrate opposite the first surface;
  • the method further includes: etching the first conductive material layer covering the first surface.
  • the first conductive material layer on the second surface to form a plurality of second bonding pads.
  • forming a dielectric layer that at least covers the first bonding pad and the transmission line and fills the gap between the first bonding pad and the transmission line includes:
  • the dielectric layer is formed on the first surface and the second surface, and the dielectric layer also covers the plurality of second bonding pads and fills gaps between the plurality of second bonding pads.
  • the method further includes:
  • the dielectric layer covering the second soldering pad is etched to form a second opening, and the second opening exposes the second soldering pad.
  • Embodiments of the present disclosure provide a semiconductor structure, a packaging device, and a method for manufacturing a semiconductor structure, wherein the semiconductor structure includes: a substrate including a first surface; and a first bonding pad located on the first surface. ; The transfer part is located on the first bonding pad; the transfer part includes a first sub-part covering the first welding pad and a second sub-part covering the first sub-part, wherein the third A sub-portion, the orthographic projection of the first soldering pad on the first surface falls within the orthographic projection of the second sub-portion on the first surface; a solder ball is located on the second sub-portion superior.
  • the solder ball is electrically connected to the first solder pad through the transfer part, and the solder ball is located on the second sub-part with a larger size.
  • the size of the first solder pad can be reduced by reducing the size of the first solder pad without changing the size of the solder ball. , reducing the area occupied by the first bonding pad on the substrate surface, thereby allowing the transmission line to occupy a larger area on the substrate surface.
  • the transmission line can be designed wider, reducing or eliminating the risk of transmission line breakage, and avoiding transmission lines caused by being too close. electromagnetic interference and signal crosstalk, and due to the smaller size of the first bonding pad, the problem of a long transmission path of the transmission line can be avoided or alleviated.
  • Figure 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2 is a schematic diagram of a semiconductor structure provided by another embodiment of the present disclosure.
  • Figure 3 is a schematic diagram of a semiconductor structure provided by yet another embodiment of the present disclosure.
  • Figure 4 is a schematic diagram of a packaged device provided by an embodiment of the present disclosure.
  • Figure 5 is a flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • 6 to 12 are process flow diagrams of a method for manufacturing a semiconductor structure provided by embodiments of the present disclosure.
  • 13 to 16 are process flow diagrams of a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.
  • FIG. 17 is a process flow diagram of a method for manufacturing a semiconductor structure provided by yet another embodiment of the present disclosure.
  • a semiconductor structure such as a packaging substrate, usually includes a substrate.
  • the surface of the substrate is provided with bonding pads and signal transmission lines located between the bonding pads.
  • the bonding pads are used for soldering solder balls.
  • the solder pad and the solder ball occupy a larger area on the substrate surface, squeezing the area occupied by the signal transmission line on the substrate surface,
  • the signal transmission line is designed to be thin and prone to breakage. In order to avoid the solder pads, the signal transmission line often has a long winding, causing signal integrity problems.
  • FIG. 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of a semiconductor structure provided by another embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a semiconductor structure provided by yet another embodiment of the present disclosure. The semiconductor structure provided by the embodiment of the present disclosure will be further described below with reference to FIGS. 1 to 3 .
  • the semiconductor structure includes: a substrate 10 including a first surface S1; a first bonding pad 12 located on the first surface S1; a transfer portion 18 located on the first bonding pad 12;
  • the portion 18 includes a first sub-portion 181 covering the first soldering pad 12 and a second sub-portion 182 covering the first sub-portion 181 , wherein the first sub-portion 181 and the first soldering pad 12 are located directly on the first surface S1
  • the projection falls into the orthographic projection of the second sub-portion 182 on the first surface S1; the solder ball 21 is located on the second sub-portion 182.
  • the semiconductor structure provided by embodiments of the present disclosure may be a packaging substrate, such as a ball grid array (BGA) packaging substrate. But it is not limited thereto, the semiconductor structure may also be any semiconductor structure including solder balls.
  • BGA ball grid array
  • the material of the substrate 10 may be an organic insulating material, a fiber-mixed organic insulating material or a mixed-particle organic insulating material, such as epoxy resin, polyimide, bismaleimide/triazine-based resin, cyanic acid Grease or its glass fiber composite materials, etc. But it is not limited thereto.
  • the material of the substrate 10 may also be a semiconductor material, such as silicon.
  • conductive vias (not shown) are formed in the substrate 10 .
  • the semiconductor structure further includes: a transmission line 13 located on the first surface S1 and disposed between the plurality of first bonding pads 12 for transmitting electrical signals.
  • the orthographic projection of the first sub-portion 181 and the first bonding pad 12 on the first surface S1 falls within the orthographic projection of the second sub-portion 182 on the first surface S1, and the solder ball 21 has The larger size of the second sub-portion 182 is soldered.
  • the size of the first bonding pad 12 can be reduced, thereby reducing the space occupied by the first bonding pad 12 on the first surface S1. area, thereby allowing the transmission line 13 to occupy a larger area on the first surface S1.
  • the transmission line 13 can be designed to be wider, reducing or eliminating the risk of breakage of the transmission line 13, and avoiding electromagnetic interference and signal crosstalk caused by too close a transmission line distance, and Since the size of the first bonding pad 12 is small, the problem of a long transmission path of the transmission line 13 can be avoided or alleviated.
  • the first sub-portion 181 has a uniform width in a direction perpendicular to the first surface S1 and directed from the first bonding pad 12 to the second sub-portion 182 .
  • the orthographic projection of the first sub-portion 181 on the first surface S1 completely overlaps the orthographic projection of the first bonding pad 12 on the first surface S1 , or the first sub-portion 181 is on the first surface S1 falls within the orthographic projection of the first bonding pad 12 on the first surface S1 , that is, the cross-sectional area of the first sub-portion 181 is less than or equal to the cross-sectional area of the first bonding pad 12 , thus avoiding
  • the first sub-section 181 is oversized and contacts the transmission line 13, causing a short circuit.
  • the width of the first sub-portion 181 gradually increases. Increase, in this way, increase the contact area of the first sub-portion 181 and the second sub-portion 182, reduce the contact resistance, achieve better signal transmission, and avoid the first sub-portion 181 due to the side close to the first bonding pad 12
  • the size is too large to contact the transmission line 13.
  • the shape of the first bonding pad 12 is a circular column, the diameter of the first bonding pad 12 is between 20 ⁇ m and 420 ⁇ m, and the thickness is between 15 ⁇ m and 30 ⁇ m.
  • the diameter of the first bonding pad 12 When the diameter of the first bonding pad 12 is smaller, , for example, when the diameter is less than 50 ⁇ m, it can be designed to gradually increase the width of the first sub-portion 181 in the direction perpendicular to the first surface S1 and directed from the first pad 12 to the second sub-portion 182 to achieve better signal transmission. , to avoid affecting signal transmission due to the small size of the first bonding pad 12 .
  • the ratio between the cross-sectional area of the second sub-portion 182 and the cross-sectional area of the first bonding pad 12 should not be too large or too small; if the ratio is too large, the cross-sectional area of the first bonding pad 12 will be too small and the first The contact area between the soldering pad 12 and the transfer part 18 is small, and increasing the contact resistance will lead to poor signal transmission effect of the first soldering pad 12; if the ratio is too small, the cross-sectional area of the first soldering pad 12 and the second sub-section will be If the difference in the cross-sectional area of the portion 182 is too small, the effect of reducing the size of the first bonding pad 12 is ineffective, and more wiring area cannot be reserved for the transmission line 13 .
  • the ratio of the cross-sectional area of the second sub-portion 182 to the cross-sectional area of the first bonding pad 12 is between 2 and 50, for example, between 2 and 16. But it is not limited thereto.
  • the ratio of the cross-sectional area of the second sub-portion 182 to the cross-sectional area of the first bonding pad 12 may be larger, for example, between 50 and 100.
  • the shapes of the second sub-portion 182 and the first bonding pad 12 are both circular cylinders, and the ratio of the diameter of the second sub-portion 182 to the diameter of the first bonding pad 12 ranges from 1.1 to 7, For example, between 1.4 and 4. But it is not limited thereto.
  • the ratio range of the diameter of the second sub-portion 182 to the diameter of the first bonding pad 12 can be larger, for example, between 7 and 10.
  • the orthographic projection of the solder ball 21 on the first surface S1 completely overlaps the orthographic projection of the second sub-portion 182 on the first surface S1, or the orthographic projection of the solder ball 21 on the first surface S1 falls into
  • the second sub-portion 182 is within the orthographic projection on the first surface S1, that is, the size of the cross-section of the second sub-portion 182 is greater than or equal to the size of the cross-section of the solder ball 21, allowing the solder ball 21 and the second sub-portion 182 to have
  • the larger contact area reduces the contact resistance and helps the solder ball 21 and the second sub-section 182 to be welded more firmly.
  • the shape of the second sub-portion 182 is a circular cylinder, and the ratio of the diameter of the second sub-portion 182 to the diameter of the solder ball 21 is between 1 and 1.2, such as 1.1.
  • the diameter of the second sub-portion 182 ranges from 40 ⁇ m to 510 ⁇ m, and the thickness ranges from 10 ⁇ m to 20 ⁇ m; the diameter of the solder ball 21 ranges from 40 ⁇ m to 420 ⁇ m.
  • the materials of the first sub-part 181 and the second sub-part 182 may be the same or different, and the materials of the first bonding pad 12 and the transmission line 13 may be the same or different.
  • the materials of the pad 12 and the transmission line 13 include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), gold (Au), silver (Ag), nitride Titanium (TiN), tantalum nitride (TaN), metal silicides, metal alloys or any combination thereof.
  • the first sub-portion 181 and the second sub-portion 182 are made of the same material, for example, copper; the first bonding pad 12 and the transmission line 13 are made of the same material, for example, copper.
  • the solder balls 21 may be lead-containing tin balls or lead-free tin balls.
  • the semiconductor structure further includes: a composite reinforcement layer 16 located between the first sub-section 181 and the first bonding pad 12 .
  • the material of the composite reinforcement layer 16 can be an alloy material, such as titanium. Titanium has the advantages of good conductivity, high strength, easy welding, etc., and plays a good connection role. But it is not limited thereto, and any material that meets the above requirements can be used as the composite reinforcement layer 16 in the embodiment of the present disclosure.
  • the semiconductor structure further includes: a solderable layer 19 located between the solder ball 21 and the second sub-portion 182 , the solderable layer 19 helps to connect the solder ball 21 and the second sub-portion 182 The welding is stronger.
  • the material of the side of the solderable layer 19 adjacent to the solder ball 21 may be tin (Sn), gold (Au), or silver (Ag).
  • the semiconductor structure further includes: a dielectric layer 15.
  • the dielectric layer 15 covers the transmission line 13 and fills the gap between the first bonding pad 12 and the transmission line 13 to protect the transmission line 13 and the first bonding pad 12 from being oxidized. or damaged.
  • the material of the dielectric layer 15 may be graphene, ink, green paint, epoxy resin, etc., for example, green oil.
  • a first opening T1 exposing the first bonding pad 12 is formed in the dielectric layer 15 .
  • the first sub-portion 181 is located in the first opening T1
  • the second sub-portion 182 covers the first sub-portion 181 and part of the dielectric layer 15 .
  • the height H1 of the first sub-portion 181 is equal to or less than the height H2 of the first opening T1. But it is not limited thereto. As shown in FIG. 1 or FIG. 2 , in a specific embodiment, the first sub-portion 181 is located in the first opening T1 , and the second sub-portion 182 covers the first sub-portion 181 and part of the dielectric layer 15 . More specifically, the height H1 of the first sub-portion 181 is equal to or less than the height H2 of the first opening T1. But it is not limited thereto. As shown in FIG.
  • the first sub-portion 181 is partially located within the first opening T1 , the height H1 of the first sub-portion 181 is greater than the height H2 of the first opening T1 , and the second sub-portion 181 is not limited to this.
  • the sub-section 182 is far away from the transmission line 13. In this way, when the semiconductor structure is operating, signal interference between the second sub-section 182 and the transmission line 13 can be reduced.
  • the semiconductor structure further includes: a plurality of second bonding pads 14, located on the second surface S2 of the substrate 10 opposite to the first surface S1, and the dielectric layer 15 also fills between the plurality of second bonding pads 14. gaps; wherein, a plurality of second openings T2 are formed in the dielectric layer 15, and the second openings T2 expose the second bonding pads 14.
  • the second bonding pads 14 can be used for subsequent connection to other structures. But it is not limited thereto.
  • the upper surface of the dielectric layer 15 can also be flush with the upper surface of the second bonding pads 14 , or the dielectric layer 15 located between the plurality of second bonding pads 14 can be removed. In this way, it is convenient to connect the second bonding pad 14 to other structures in actual operations, and the embodiment of the present disclosure is not too restrictive here.
  • first bonding pad 12 and the transmission line 13 located on the first surface S1 and the second bonding pad 14 located on the second surface S2 are electrically connected through conductive vias (not shown) located in the substrate 10 . connect.
  • the material of the second bonding pad 14 may be the same as or different from the material of the first bonding pad 12 .
  • the material of the second bonding pad 14 is the same as the material of the first bonding pad 12 , for example, copper.
  • Embodiments of the present disclosure also provide a packaged device. As shown in FIG. 4 , the packaged device includes: at least one chip 22 and any semiconductor structure 100 as described above. At least one chip 22 is bonded to the semiconductor structure 100 .
  • the semiconductor structure 100 includes: a substrate 10 including a first surface S1; a first bonding pad 12 located on the first surface S1; a transfer portion 18 located on the first bonding pad 12; the transfer portion 18 includes a first sub-portion 181 covering the first welding pad 12 and a second sub-portion 182 covering the first sub-portion 181, wherein the orthographic projection of the first sub-portion 181 and the first welding pad 12 on the first surface S1 Falling into the orthographic projection of the second sub-portion 182 on the first surface S1; the solder ball 21 is located on the second sub-portion 182.
  • the semiconductor structure 100 further includes: a plurality of second bonding pads 14 located on the second surface S2 of the substrate 10 opposite to the first surface S1.
  • the number of chips 22 may be one; the packaged device further includes: bumps 23 disposed between the chip 22 and the semiconductor structure 100 , a plurality of bumps 23 and a plurality of second bonding pads 14 are connected in a one-to-one correspondence, and the material of the bump 23 includes copper. But it is not limited to this. In other embodiments, the number of chips 22 is multiple, and the multiple chips 22 are stacked in the vertical direction and bonded to each other. The chip 22 may also be connected to the second bonding pad 14 through a bonding wire.
  • the packaged device further includes: an encapsulation layer 24 , and the encapsulation layer 24 at least covers the chip 22 and the second surface S2 of the substrate 10 .
  • the material of the encapsulation layer 24 includes epoxy resin molding compound.
  • An embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure. As shown in Figure 5, the method includes the following steps:
  • Step 501 Provide a substrate, the substrate including a first surface
  • Step 502 Form a first bonding pad on the first surface
  • Step 503 Form a transition portion on the first bonding pad.
  • the transition portion includes a first sub-portion covering the first bonding pad and a second sub-portion covering the first sub-portion, wherein the first sub-portion and the first bonding pad
  • the orthographic projection on the first surface falls within the orthographic projection of the second subpart on the first surface
  • Step 504 Form a solder ball on the second sub-part.
  • FIGS. Process flow chart FIG. 13 to FIG. 16 is a process flow chart of a manufacturing method of a semiconductor structure provided by another embodiment of the present disclosure
  • FIG. 17 is a process flow chart of a manufacturing method of a semiconductor structure provided by yet another embodiment of the present disclosure.
  • step 501 is performed.
  • a substrate 10 is provided.
  • the substrate 10 includes a first surface S1.
  • the substrate 10 also includes a second surface S2 opposite the first surface S1.
  • the material of the substrate 10 may be an organic insulating material, a fiber-mixed organic insulating material or a mixed-particle organic insulating material, such as epoxy resin, polyimide, bismaleimide/triazine-based resin, cyanic acid Grease or its glass fiber composite materials, etc. But it is not limited thereto.
  • the material of the substrate 10 may also be a semiconductor material, such as silicon.
  • conductive vias are formed in the substrate 10 .
  • step 502 is performed. As shown in FIGS. 7 to 8 , the first bonding pad 12 is formed on the first surface S1.
  • forming the first bonding pad 12 on the first surface S1 includes:
  • the first conductive material layer 11 at least covers the first surface S1;
  • the first conductive material layer 11 covering the first surface S1 is etched to form the first bonding pad 12 and the transmission line 13 on the first surface S1.
  • forming the first conductive material layer 11 which at least covers the first surface S1 , includes: forming the first conductive material layer 11 , the first conductive material layer 11 covers the first surface S1 and the second surface S2 of the substrate 10 opposite to the first surface S1;
  • the method further includes: etching the first conductive material layer 11 covering the second surface S2. Conductive material layer 11 to form a plurality of second bonding pads 14 .
  • Embodiments of the present disclosure simplify the process by forming the first bonding pad 12 and the second bonding pad 14 in the same process step. But it is not limited to this, the second bonding pad 14 and the first bonding pad 12 can also be formed in different process steps.
  • the first conductive material layer 11 can be formed on the liner using processes such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, chemical plating, sputtering, etc. on the first surface S1 and the second surface S2 of the bottom 10 .
  • the materials of the first conductive material layer 11 include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), gold (Au), silver (Ag), nitrogen Titanium nitride (TiN), tantalum nitride (TaN), metal suicide, metal alloy or any combination thereof, for example, copper.
  • first bonding pads 12 there are multiple first bonding pads 12 , and the transmission lines 13 are located between the multiple first bonding pads 12 .
  • first bonding pad 12 and the transmission line 13 located on the first surface S1 and the second bonding pad 14 located on the second surface S2 are electrically connected through conductive vias (not shown) located in the substrate 10 . connect.
  • the shape of the first bonding pad 12 is a circular column, the diameter of the first bonding pad 12 is between 20 ⁇ m and 420 ⁇ m, and the thickness is between 15 ⁇ m and 30 ⁇ m.
  • step 503 is performed.
  • an adapter portion 18 is formed on the first bonding pad 12 .
  • the adapter portion 18 includes a first sub-portion 181 covering the first bonding pad 12 and a first sub-portion 181 covering the first bonding pad 12 .
  • the second sub-portion 182 of the sub-portion 181 wherein the orthographic projection of the first sub-portion 181 and the first bonding pad 12 on the first surface S1 falls within the orthographic projection of the second sub-portion 182 on the first surface S1 .
  • the method before forming the transfer portion 18 on the first bonding pad 12 , the method further includes: forming a dielectric layer 15 , and the dielectric layer 15 at least covers the first bonding pad 12 and the transmission line 13 and fills it. The gap between the first bonding pad 12 and the transmission line 13 .
  • a dielectric layer 15 is formed.
  • the dielectric layer 15 at least covers the first bonding pad 12 and the transmission line 13 and fills the gap between the first bonding pad 12 and the transmission line 13 , including: on the first surface
  • a dielectric layer 15 is formed on S1 and the second surface S2.
  • the dielectric layer 15 also covers the plurality of second bonding pads 14 and fills the gaps between the plurality of second bonding pads 14.
  • the embodiment of the present disclosure simplifies the process by forming the dielectric layer 15 on the first surface S1 and the second surface S2 in the same process step. But it is not limited thereto.
  • the dielectric layer 15 located on the first surface S1 and the dielectric layer 15 located on the second surface S2 can also be formed in different process steps.
  • the dielectric layer 15 is used to protect the first bonding pad 12, the transmission line 13, and the second bonding pad 14 from being oxidized or damaged in subsequent process steps.
  • the material of the dielectric layer 15 may be graphene, ink, green paint, epoxy resin, etc., for example, green oil.
  • an adapter portion 18 is formed on the first bonding pad 12 .
  • the adapter portion 18 includes a first sub-portion 181 covering the first bonding pad 12 and a second sub-portion covering the first sub-portion 181 . 182, including:
  • the second conductive material layer 17 fills the first opening T1 and covers the dielectric layer 15;
  • a portion of the second conductive material layer 17 covering the dielectric layer 15 is etched to form the adapter portion 18 , wherein the portion of the adapter portion 18 located within the first opening T1 constitutes the first sub-portion 181 , covering the first sub-portion 181 and part of the second conductive material layer 17 .
  • Part of the dielectric layer 15 forms the second sub-portion 182 .
  • the second conductive material layer 17 can be formed on the lining using processes such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, chemical plating, sputtering, etc. on the first surface S1 of the bottom 10 .
  • the materials of the second conductive material layer 17 include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), gold (Au), silver (Ag), nitrogen Titanium nitride (TiN), tantalum nitride (TaN), metal suicide, metal alloy or any combination thereof, for example, copper.
  • the method further includes: The dielectric layer 15 covering the second bonding pad 14 is etched to form a second opening T2.
  • the second opening T2 exposes the second bonding pad 14.
  • the second bonding pad 14 can be used for subsequent connection to other structures.
  • Embodiments of the present disclosure simplify the process by forming T1 and T2 in the same step. But it is not limited to this, the first opening T1 and the second opening T2 can also be formed in different steps.
  • the dielectric layer 15 located on the second surface S2 may be subsequently etched so that the upper surface of the dielectric layer 15 is flush with the upper surface of the second bonding pad 14 , or the dielectric layer 15 located on the second surface S2 may be removed.
  • the dielectric layer 15 between the bonding pads 14 facilitates the connection of the second bonding pad 14 with other structures in actual operations, and the embodiment of the present disclosure is not too restrictive here.
  • the method before forming the second conductive material layer 17 on the first surface S1 , the method further includes: forming a composite reinforcement layer 16 in the first opening T1 , and the composite reinforcement layer 16 covers the first bonding pad 12 .
  • the material of the composite reinforcement layer 16 can be an alloy material, such as titanium. Titanium has the advantages of good conductivity, high strength, easy welding, etc., and plays a good connection role. But it is not limited thereto, and any material that meets the above requirements can be used as the composite reinforcement layer 16 in the embodiment of the present disclosure.
  • step 504 is performed to form the solder ball 21 on the second sub-section 182 to form a semiconductor structure as shown in FIG. 1 or 2 .
  • the solder balls 21 may be lead-containing tin balls or lead-free tin balls.
  • the orthographic projection of the solder ball 21 on the first surface S1 completely overlaps the orthographic projection of the second sub-portion 182 on the first surface S1, or the orthographic projection of the solder ball 21 on the first surface S1 falls into
  • the second sub-portion 182 is within the orthographic projection on the first surface S1, that is, the size of the cross-section of the second sub-portion 182 is greater than or equal to the size of the cross-section of the solder ball 21, allowing the solder ball 21 and the second sub-portion 182 to have
  • the larger contact area reduces the contact resistance and helps the solder ball 21 and the second sub-section 182 to be welded more firmly.
  • the shape of the second sub-portion 182 is a circular cylinder, and the ratio of the diameter of the second sub-portion 182 to the diameter of the solder ball 21 is between 1 and 1.2, such as 1.1.
  • the diameter of the second sub-portion 182 ranges from 40 ⁇ m to 510 ⁇ m, and the thickness ranges from 10 ⁇ m to 20 ⁇ m; the diameter of the solder ball 21 ranges from 40 ⁇ m to 420 ⁇ m.
  • the method before forming the solder ball 21, the method further includes: forming a solderable layer 19, the solderable layer 19 covering the surface of the second sub-portion 182 to be electrically connected to the solder ball 21 , the solderable layer 19 helps to solder the solder ball 21 and the second sub-section 182 more firmly.
  • the material of the side of the solderable layer 19 to be electrically connected to the solder ball 21 may be tin (Sn), gold (Au), or silver (Ag).
  • the first sub-portion 181 of the adapter portion 18 shown in FIGS. 12 and 1 to 2 is formed in the first opening T1, and the height H1 of the first sub-portion 181 is equal to or less than the height H2 of the first opening T1.
  • the first sub-portion 181 is only partially formed in the first opening T1, and the height H1 of the first sub-portion 181 is greater than the height H2 of the first opening T1, as shown in Figures 13 to 16 and Figure 3 shown.
  • the method also includes: forming an insulation Layer 25, the insulating layer 25 covers the dielectric layer 15 located on the first surface S1.
  • the insulating layer 25 will be removed. Therefore, under preset etching conditions, the etching rate of the insulating layer 25 is greater than the etching rate of the dielectric layer 15 .
  • the insulating layer 25 covering the dielectric layer 15 and the dielectric layer 15 covering the first bonding pad 12 are etched to form the third opening T3 and the first opening T1 respectively.
  • the opening T1 exposes the first bonding pad 12 .
  • a second conductive material layer 17 is formed on the first surface S1 .
  • the second conductive material layer 17 fills the first opening T1 and the third opening T3 and covers the insulating layer 25 .
  • a portion of the second conductive material layer 17 covering the insulating layer 25 is etched to form a connecting portion 18 , wherein the connecting portion 18 is formed by the portion located within the first opening T1 and the third opening T3
  • the first sub-part 181 covers the first sub-part 181 and part of the insulating layer 25 to form the second sub-part 182 .
  • the insulating layer 25 is removed and the solder ball 21 is formed on the second sub-portion 182 to form a semiconductor structure as shown in FIG. 3 .
  • the first sub-portion 181 is partially located within the first opening T1, the height H1 of the first sub-portion 181 is greater than the height H2 of the first opening T1, and the second sub-portion 182 is farther from the transmission line 13. In this way, when When the semiconductor structure is operating, signal interference between the second sub-section 182 and the transmission line 13 can be reduced.
  • the method of forming the transition portion 18 on the first bonding pad 12 is to first form the second conductive material layer 17 covering the first bonding pad 12 and then etch the second conductive material layer 17 to form the transition portion. Department 18. But it is not limited thereto. As shown in FIG.
  • forming the transfer portion 18 on the first bonding pad 12 includes: etching the dielectric layer 15 covering the first bonding pad 12 to form a third An opening T1, the first opening T1 exposes the first bonding pad 12; an adapter part 18 is provided, the adapter part 18 includes a first sub-part 181 and a second sub-part 182 covering the first sub-part 181; the adapter part 18 The first sub-portion 181 is welded to the first pad 12 .
  • the method before welding the first sub-part 181 of the transfer part 18 to the first pad 12 , the method further includes: forming a composite reinforcement layer 16 covering the first sub-part 181 , and the connection part 18 is reinforced by the composite The layer 16 is welded to the first welding pad 12, and the composite reinforcement layer 16 plays a good connection role.
  • the solder ball 21 is welded to the second sub-part 182, and the first solder pad 12 is connected to the first sub-part 181. Without changing the size of the solder ball 21, the size of the solder ball 21 can be reduced by reducing the size of the first sub-part 182.
  • the size of the first bonding pad 12 reduces the area occupied by the first bonding pad 12 on the first surface S1, thereby allowing the transmission line 13 to occupy a larger area on the first surface S1.
  • the transmission line 13 can be designed wider to reduce Or eliminate the risk of the transmission line 13 breaking, avoid electromagnetic interference and signal crosstalk caused by too close transmission lines, and because the size of the first bonding pad 12 is small, the problem of a long transmission path of the transmission line 13 can be avoided or alleviated.
  • Embodiments of the present disclosure provide a semiconductor structure, a packaging device, and a method for manufacturing a semiconductor structure, wherein the semiconductor structure includes: a substrate including a first surface; and a first bonding pad located on the first surface. ; The transfer part is located on the first bonding pad; the transfer part includes a first sub-part covering the first welding pad and a second sub-part covering the first sub-part, wherein the third A sub-portion, the orthographic projection of the first soldering pad on the first surface falls within the orthographic projection of the second sub-portion on the first surface; a solder ball is located on the second sub-portion superior.
  • the solder ball is electrically connected to the first solder pad through the transfer part, and the solder ball is located on the second sub-part with a larger size.
  • the size of the first solder pad can be reduced by reducing the size of the first solder pad without changing the size of the solder ball. , reducing the area occupied by the first bonding pad on the substrate surface, thereby allowing the transmission line to occupy a larger area on the substrate surface.
  • the transmission line can be designed wider, reducing or eliminating the risk of transmission line breakage, and avoiding transmission lines caused by being too close. electromagnetic interference and signal crosstalk, and due to the smaller size of the first bonding pad, the problem of a long transmission path of the transmission line can be avoided or alleviated.

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本公开实施例公开了一种半导体结构、封装器件及半导体结构的制造方法，所述半导体结构包括：衬底，所述衬底包括第一表面；第一焊垫，位于所述第一表面上；转接部，位于所述第一焊垫上；所述转接部包括覆盖所述第一焊垫的第一子部和覆盖所述第一子部的第二子部，其中，所述第一子部、所述第一焊垫在所述第一表面上的正投影落入所述第二子部在所述第一表面上的正投影内；焊球，位于所述第二子部上。

Description

一种半导体结构、封装器件及半导体结构的制造方法
相关申请的交叉引用
本公开基于申请号为202210787178.X、申请日为2022年07月04日、发明名称为“一种半导体结构、封装器件及半导体结构的制造方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体制造领域，尤其涉及一种半导体结构、封装器件及半导体结构的制造方法。
背景技术
半导体结构，例如封装基板，通常包括衬底，衬底表面设置有焊垫以及位于焊垫之间的信号传输线，焊垫用于焊接焊球。
然而，由于焊球的尺寸较大，且焊垫与焊球的尺寸相等或接近，焊垫与焊球在衬底表面占用的面积较大，挤压信号传输线在衬底表面占用的面积，使得信号传输线设计的较细，容易发生断裂，且为了避开焊垫，信号传输线往往具有较长的绕线，从而引起信号完整性问题。
发明内容
本公开实施例提供一种半导体结构，包括:
衬底，所述衬底包括第一表面；
第一焊垫，位于所述第一表面上；
转接部，位于所述第一焊垫上；所述转接部包括覆盖所述第一焊垫的第一子部和覆盖所述第一子部的第二子部，其中，所述第一子部、所述第一焊垫在所述第一表面上的正投影落入所述第二子部在所述第一表面上的正投影内；
焊球，位于所述第二子部上。
在一些实施例中，所述焊球在所述第一表面上的正投影与所述第二子部在所述第一表面上的正投影完全重叠，或者所述焊球在所述第一表面上的正投影落入所述第二子部在所述第一表面上的正投影内。
在一些实施例中，所述第一子部在所述第一表面上的正投影与所述第一焊垫在所述第一表面上的正投影完全重叠，或者所述第一子部在所述第 一表面上的正投影落入所述第一焊垫在所述第一表面上的正投影内。
在一些实施例中，在垂直于所述第一表面且由所述第一焊垫指向所述第二子部的方向上，所述第一子部的宽度逐渐增加。
在一些实施例中，所述半导体结构还包括：复合增强层，所述复合增强层位于所述第一子部和所述第一焊垫之间。
在一些实施例中，所述半导体结构还包括：可焊层，所述可焊层位于所述焊球和所述第二子部之间。
在一些实施例中，所述半导体结构还包括：传输线，所述传输线位于所述第一表面上；介质层，所述介质层覆盖所述传输线且填充所述第一焊垫和所述传输线之间的空隙；其中，所述介质层内形成有暴露出所述第一焊垫的第一开口，所述第一子部位于所述第一开口内，所述第二子部覆盖所述第一子部及部分所述介质层。
在一些实施例中，所述半导体结构还包括：多个第二焊垫，位于所述衬底与所述第一表面相对的第二表面上，所述介质层还填充所述多个第二焊垫之间的空隙；其中，所述介质层内形成有多个第二开口，所述第二开口暴露所述第二焊垫。
本公开实施例还提供了一种封装器件，所述封装器件包括：至少一个芯片以及如上所述的任一半导体结构，所述至少一个芯片与所述半导体结构键合连接。
本公开实施例还提供了一种半导体结构的制造方法，包括：
提供衬底，所述衬底包括第一表面；
在所述第一表面上形成第一焊垫；
在所述第一焊垫上形成转接部，所述转接部包括覆盖所述第一焊垫的第一子部和覆盖所述第一子部的第二子部，其中，所述第一子部、所述第一焊垫在所述第一表面上的正投影落入所述第二子部在所述第一表面上的正投影内；
在所述第二子部上形成焊球。
在一些实施例中，在所述第一表面上形成第一焊垫，包括：
形成第一导电材料层，所述第一导电材料层至少覆盖所述第一表面；
刻蚀覆盖所述第一表面的所述第一导电材料层以在所述第一表面上形成所述第一焊垫和传输线。
在一些实施例中，在所述第一焊垫上形成转接部之前，所述方法还包括：
形成介质层，所述介质层至少覆盖所述第一焊垫、所述传输线并填充所述第一焊垫、所述传输线之间的空隙。
在一些实施例中，在所述第一焊垫上形成转接部，所述转接部包括覆盖所述第一焊垫的第一子部和覆盖所述第一子部的第二子部，包括：
刻蚀覆盖所述第一焊垫的所述介质层以形成第一开口，所述第一开口 暴露所述第一焊垫；
在所述第一表面上形成第二导电材料层，所述第二导电材料层填充所述第一开口并覆盖所述介质层；
刻蚀覆盖所述介质层的部分所述第二导电材料层以形成所述转接部，其中，所述转接部位于所述第一开口内的部分构成所述第一子部，覆盖所述第一子部及部分所述介质层的部分构成所述第二子部。
在一些实施例中，在所述第一表面上形成第二导电材料层之前，所述方法还包括：在所述第一开口内形成复合增强层，所述复合增强层覆盖所述第一焊垫。
在一些实施例中，在形成焊球之前，所述方法还包括：形成可焊层，所述可焊层覆盖所述第二子部待与所述焊球电连接的表面。
在一些实施例中，形成第一导电材料层，所述第一导电材料层至少覆盖所述第一表面，包括：形成第一导电材料层，所述第一导电材料层覆盖所述第一表面及所述衬底的与所述第一表面相对的第二表面；
在刻蚀覆盖所述第一表面的所述第一导电材料层以在所述第一表面上形成所述第一焊垫和传输线的同一步骤中，所述方法还包括：刻蚀覆盖所述第二表面的所述第一导电材料层，以形成多个第二焊垫。
在一些实施例中，形成介质层，所述介质层至少覆盖所述第一焊垫、所述传输线并填充所述第一焊垫、所述传输线之间的空隙，包括：
在所述第一表面和所述第二表面上形成所述介质层，所述介质层还覆盖所述多个第二焊垫并填充位于所述多个第二焊垫之间的空隙。
在一些实施例中，在刻蚀覆盖所述第一焊垫的所述介质层以形成第一开口，所述第一开口暴露所述第一焊垫的同一步骤中，所述方法还包括：
刻蚀覆盖所述第二焊垫的介质层以形成第二开口，所述第二开口暴露所述第二焊垫。
本公开实施例提供的半导体结构、封装器件及半导体结构的制造方法，其中，所述半导体结构包括：衬底，所述衬底包括第一表面；第一焊垫，位于所述第一表面上；转接部，位于所述第一焊垫上；所述转接部包括覆盖所述第一焊垫的第一子部和覆盖所述第一子部的第二子部，其中，所述第一子部、所述第一焊垫在所述第一表面上的正投影落入所述第二子部在所述第一表面上的正投影内；焊球，位于所述第二子部上。焊球通过转接部与第一焊垫电连接，且焊球位于具有更大尺寸的第二子部上，如此，在不改变焊球尺寸的情况下，可以通过缩小第一焊垫的尺寸，减小第一焊垫在衬底表面占用的面积，从而允许传输线在衬底表面占用更大的面积，传输线可以设计的更宽，减小或消除传输线断裂的风险，避免传输线距离过近引起的电磁干扰、信号串扰，且由于第一焊垫的尺寸较小，能够避免或缓解传输线传输路径较长的问题。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公 开的其它特征和优点将从说明书附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的半导体结构的示意图；
图2为本公开另一实施例提供的半导体结构的示意图；
图3为本公开又一实施例提供的半导体结构的示意图；
图4为本公开实施例提供的封装器件的示意图；
图5为本公开实施例提供的半导体结构的制造方法的流程框图；
图6至图12为本公开实施例提供的半导体结构的制造方法的工艺流程图；
图13至图16为本公开另一实施例提供的半导体结构的制造方法的工艺流程图；
图17为本公开又一实施例提供的半导体结构的制造方法的工艺流程图。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管 可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
半导体结构，例如封装基板，通常包括衬底，衬底表面设置有焊垫以及位于焊垫之间的信号传输线，焊垫用于焊接焊球。
然而，由于焊球的尺寸较大，且焊垫与焊球的尺寸相等或接近，因此焊垫与焊球在衬底表面占用的面积较大，挤压信号传输线在衬底表面占用的面积，使得信号传输线设计的较细，容易发生断裂，且为了避开焊垫，信号传输线往往具有较长的绕线，从而引起信号完整性问题。
基于此，提出了本公开实施例的以下技术方案。下面结合附图对本公开的具体实施方式做详细的说明。在详述本公开实施例时，为便于说明，示意图会不依一般比例做局部放大，而且所述示意图只是示例，其在此不应限制本公开的保护范围。
图1为本公开实施例提供的半导体结构的示意图，图2为本公开另一实施例提供的半导体结构的示意图，图3为本公开又一实施例提供的半导体结构的示意图。以下结合图1至图3对本公开实施例提供的半导体结构再作进一步说明。
如图所示，半导体结构包括：衬底10，衬底10包括第一表面S1；第 一焊垫12，位于第一表面S1上；转接部18，位于第一焊垫12上；转接部18包括覆盖第一焊垫12的第一子部181和覆盖第一子部181的第二子部182，其中，第一子部181、第一焊垫12在第一表面S1上的正投影落入第二子部182在第一表面S1上的正投影内；焊球21，位于第二子部182上。
在实际操作中，本公开实施例提供的半导体结构可以是封装基板，例如球栅阵列(BGA)封装基板。但不限于此，半导体结构还可以是任何包括焊球的半导体结构。
衬底10的材料可以为有机绝缘材料、混纤维的有机绝缘材料或混颗粒的有机绝缘材料等，例如环氧树脂、聚酰亚胺、双马来酰亚胺/三嗪基树脂、氰酸脂或其玻璃纤维的复合材料等。但不限于此，衬底10的材料还可以为半导体材料，例如硅。在一些实施例中，衬底10内形成有导电通孔(未图示)。
第一焊垫12、转接部18、焊球21的数量均为多个，多个焊球21通过转接部18与多个第一焊垫12一一对应电连接。在一实施例中，半导体结构还包括：传输线13，传输线13位于第一表面S1上，且设置在多个第一焊垫12之间，用于传输电信号。本公开实施例中，第一子部181、第一焊垫12在第一表面S1上的正投影落入第二子部182在第一表面S1上的正投影内，且焊球21与具有更大尺寸的第二子部182焊接，如此，在不改变焊球21尺寸的情况下，可以通过缩小第一焊垫12的尺寸，减小第一焊垫12在第一表面S1上占用的面积，从而允许传输线13在第一表面S1上占用更大的面积，传输线13可以设计的更宽，减小或消除传输线13断裂的风险，避免传输线距离过近引起的电磁干扰、信号串扰，且由于第一焊垫12的尺寸较小，能够避免或缓解传输线13传输路径较长的问题。
如图1所示，在一实施例中，在垂直于第一表面S1且由第一焊垫12指向第二子部182的方向上，第一子部181具有均匀的宽度。在一些实施例中，第一子部181在第一表面S1上的正投影与第一焊垫12在第一表面S1上的正投影完全重叠，或者第一子部181在第一表面S1上的正投影落入第一焊垫12在第一表面S1上的正投影内，即，第一子部181的横截面的面积小于或等于第一焊垫12的横截面的面积，如此，避免了第一子部181由于尺寸过大与传输线13接触，造成短路。
但不限于此，如图2所示，在另一实施例中，在垂直于第一表面S1且由第一焊垫12指向第二子部182的方向上，第一子部181的宽度逐渐增加，如此，增加了第一子部181和第二子部182的接触面积，降低接触电阻，实现更好的信号传输，且避免了第一子部181由于靠近第一焊垫12的一侧的尺寸过大与传输线13接触。在一些实施例中，第一焊垫12的形状为圆形柱，第一焊垫12的直径在20μm至420μm之间，厚度在15μm至30μm之间，当第一焊垫12的直径较小时，例如直径小于50μm时，可以设计在垂直于第一表面S1且由第一焊垫12指向第二子部182的方向上，第 一子部181的宽度逐渐增加，以实现更好的信号传输，避免由于第一焊垫12的尺寸过小，影响信号传输。
第二子部182的横截面的面积和第一焊垫12的横截面的面积的比值不宜过大也不宜过小；比值过大，第一焊垫12的横截面的面积太小，第一焊垫12与转接部18的接触面积较小，增加接触电阻，会导致第一焊垫12传输信号的效果不佳；比值过小，第一焊垫12的横截面的面积和第二子部182的横截面的面积的差值过小，第一焊垫12尺寸缩小的效果不佳，无法为传输线13预留较多的布线面积。在一实施例中，第二子部182的横截面的面积和第一焊垫12的横截面的面积的比值在2至50之间，例如，在2至16之间。但不限于此，第二子部182的横截面的面积和第一焊垫12的横截面的面积的比值还可以更大，例如在50至100之间。在一些实施例中，第二子部182和第一焊垫12的形状均为圆形柱，第二子部182的直径和第一焊垫12的直径的比值范围在1.1至7之间，例如，在1.4至4之间。但不限于此，第二子部182的直径和第一焊垫12的直径的比值范围还可以更大，例如在7至10之间。
在一实施例，焊球21在第一表面S1上的正投影与第二子部182在第一表面S1上的正投影完全重叠，或者焊球21在第一表面S1上的正投影落入第二子部182在第一表面S1上的正投影内，即第二子部182的横截面的尺寸大于或等于焊球21的横截面的尺寸，允许焊球21和第二子部182具有更大的接触面积，降低接触电阻，且有助于焊球21与第二子部182焊接的更牢固。在一些实施例中，第二子部182的形状为圆形柱，第二子部182的直径与焊球21的直径的比值在1至1.2之间，例如1.1。在一具体实施例中，第二子部182的直径的范围在40μm至510μm之间，厚度在10μm至20μm之间；焊球21的直径的范围在40μm至420μm之间。
第一子部181的材料和第二子部182的材料可以相同或不同，第一焊垫12和传输线13的材料可以相同或不同，第一子部181、第二子部182、第一焊垫12、传输线13的材料包括钨(W)、铜(Cu)、钛(Ti)、钽(Ta)、镍(Ni)、铬(Cr)、金(Au)、银(Ag)、氮化钛(TiN)、氮化钽(TaN)、金属硅化物、金属合金或其任何组合。在一实施例中，第一子部181的材料和第二子部182的材料相同，例如，铜；第一焊垫12和传输线13的材料相同，例如，铜。焊球21可以为含铅锡球或不含铅锡球。
在一些实施例中，半导体结构还包括：复合增强层16，复合增强层16位于第一子部181和第一焊垫12之间。复合增强层16的材料可以为合金材料，例如钛，钛具有导电性好、强度高、易焊接等优点，起到良好的连接作用。但不限于此，任何符合上述要求的材料都可以作为本公开实施例中的复合增强层16使用。
在一实施例中，半导体结构还包括：可焊层19，可焊层19位于焊球21和第二子部182之间，可焊层19有助于使焊球21和第二子部182焊接 的更牢固。可焊层19邻近焊球21一面的材料可以是锡(Sn)、金(Au)、银(Ag)。
在一实施例中，半导体结构还包括：介质层15，介质层15覆盖传输线13且填充第一焊垫12和传输线13之间的空隙，用于保护传输线13和第一焊垫12不被氧化或损坏。介质层15的材料可以为石墨烯、油墨、绿漆、环氧树脂等，例如，绿油。
在一实施例中，介质层15内形成有暴露出第一焊垫12的第一开口T1。如图1或图2所示，在一具体的实施例中，第一子部181位于第一开口T1内，第二子部182覆盖第一子部181及部分介质层15。更具体的，第一子部181的高度H1等于或小于第一开口T1的高度H2。但不限于此，如图3所示，在另一些实施例中，第一子部181部分位于第一开口T1内，第一子部181的高度H1大于第一开口T1的高度H2，第二子部182距离传输线13较远，如此，当半导体结构在工作时，能够减小第二子部182与传输线13之间的信号干扰。
在一实施例中，半导体结构还包括：多个第二焊垫14，位于衬底10与第一表面S1相对的第二表面S2上，介质层15还填充多个第二焊垫14之间的空隙；其中，介质层15内形成有多个第二开口T2，第二开口T2暴露第二焊垫14，第二焊垫14可以用于后续连接其他结构。但不限于此，在另一些实施例中，介质层15的上表面还可以与第二焊垫14的上表面齐平，或者移除位于多个第二焊垫14之间的介质层15，如此，便于在实际操作中将第二焊垫14与其他结构连接，本公开实施例在此不做过多限制。
在一些实施例中，位于第一表面S1上的第一焊垫12、传输线13与位于第二表面S2上的第二焊垫14通过位于衬底10内的导电通孔(未图示)电连接。第二焊垫14的材料与第一焊垫12的材料可以相同或不同。在一具体实施例中，第二焊垫14的材料与第一焊垫12的材料相同，例如，铜。
本公开实施例还提供了一种封装器件，如图4所示，封装器件包括：至少一个芯片22以及如上所述的任一半导体结构100，至少一个芯片22与半导体结构100键合连接。
具体的，半导体结构100包括：衬底10，衬底10包括第一表面S1；第一焊垫12，位于第一表面S1上；转接部18，位于第一焊垫12上；转接部18包括覆盖第一焊垫12的第一子部181和覆盖第一子部181的第二子部182，其中，第一子部181、第一焊垫12在第一表面S1上的正投影落入第二子部182在第一表面S1上的正投影内；焊球21，位于第二子部182上。在一些实施例中，半导体结构100还包括：多个第二焊垫14，位于衬底10与第一表面S1相对的第二表面S2上。
在一实施例中，芯片22的数量可以为一个；封装器件还包括：凸块23，凸块23位于设置在芯片22和半导体结构100之间，多个凸块23与多个第二焊垫14一一对应连接，凸块23的材料包括铜。但不限于此，在其他实 施例中，芯片22的数量为多个，多个芯片22在竖直方向上堆叠设置且彼此键合连接。芯片22还可以通过键合线与第二焊垫14连接。
在一实施例中，封装器件还包括：封装层24，封装层24至少覆盖芯片22及衬底10的第二表面S2。封装层24的材料包括环氧树脂模塑料。
本公开实施例还提供了一种半导体结构的制造方法，如图5所示，方法包括以下步骤：
步骤501、提供衬底，衬底包括第一表面；
步骤502、在第一表面上形成第一焊垫；
步骤503、在第一焊垫上形成转接部，转接部包括覆盖第一焊垫的第一子部和覆盖第一子部的第二子部，其中，第一子部、第一焊垫在第一表面上的正投影落入第二子部在第一表面上的正投影内；
步骤504、在第二子部上形成焊球。
下面结合图6至图17、图1至图3对本公开实施例的半导体结构的制造方法再做进一步详细的说明，其中，图6至图12为本公开实施例提供的半导体结构的制造方法的工艺流程图，图13至图16为本公开另一实施例提供的半导体结构的制造方法的工艺流程图，图17为本公开又一实施例提供的半导体结构的制造方法的工艺流程图。
首先，执行步骤501，如图6所示，提供衬底10，衬底10包括第一表面S1。
衬底10还包括与第一表面S1相对的第二表面S2。衬底10的材料可以为有机绝缘材料、混纤维的有机绝缘材料或混颗粒的有机绝缘材料等，例如环氧树脂、聚酰亚胺、双马来酰亚胺/三嗪基树脂、氰酸脂或其玻璃纤维的复合材料等。但不限于此，衬底10的材料还可以为半导体材料，例如硅。在一实施例中，衬底10内形成有导电通孔(未图示)。
接着，执行步骤502，如图7至图8所示，在第一表面S1上形成第一焊垫12。
具体的，在第一表面S1上形成第一焊垫12，包括：
形成第一导电材料层11，第一导电材料层11至少覆盖第一表面S1；
刻蚀覆盖第一表面S1的第一导电材料层11以在第一表面S1上形成第一焊垫12和传输线13。
再次参见图7至图8，在一实施例中，形成第一导电材料层11，第一导电材料层11至少覆盖第一表面S1，包括：形成第一导电材料层11，第一导电材料层11覆盖第一表面S1及衬底10的与第一表面S1相对的第二表面S2；
在刻蚀覆盖第一表面S1的第一导电材料层11以在第一表面S1上形成第一焊垫12和传输线13的同一步骤中，方法还包括：刻蚀覆盖第二表面S2的第一导电材料层11，以形成多个第二焊垫14。
本公开实施例通过在相同的工艺步骤中形成第一焊垫12和第二焊垫 14，简化了工艺。但不限于此，第二焊垫14与第一焊垫12还可以在不同的工艺步骤中形成。
这里，第一导电材料层11可以使用化学气相沉积(CVD)、等离子增强CVD(PECVD)、物理气相沉积(PVD)、原子层沉积(ALD)、电镀、化学镀、溅射等工艺形成在衬底10的第一表面S1和第二表面S2上。第一导电材料层11的材料包括钨(W)、铜(Cu)、钛(Ti)、钽(Ta)、镍(Ni)、铬(Cr)、金(Au)、银(Ag)、氮化钛(TiN)、氮化钽(TaN)、金属硅化物、金属合金或其任何组合，例如，铜。
如图8所示，第一焊垫12的数量为多个，传输线13位于多个第一焊垫12之间。在一些实施例中，位于第一表面S1上的第一焊垫12、传输线13与位于第二表面S2上的第二焊垫14通过位于衬底10内的导电通孔(未图示)电连接。
在一实施例中，第一焊垫12的形状为圆形柱，第一焊垫12的直径在20μm至420μm之间，厚度在15μm至30μm之间。
接下来，执行步骤503，如图10至图12所示，在第一焊垫12上形成转接部18，转接部18包括覆盖第一焊垫12的第一子部181和覆盖第一子部181的第二子部182，其中，第一子部181、第一焊垫12在第一表面S1上的正投影落入第二子部182在第一表面S1上的正投影内。
如图9所示，在一实施例中，在第一焊垫12上形成转接部18之前，方法还包括：形成介质层15，介质层15至少覆盖第一焊垫12、传输线13并填充第一焊垫12、传输线13之间的空隙。
再次参见图9，在一实施例中，形成介质层15，介质层15至少覆盖第一焊垫12、传输线13并填充第一焊垫12、传输线13之间的空隙，包括：在第一表面S1和第二表面S2上形成介质层15，介质层15还覆盖多个第二焊垫14并填充位于多个第二焊垫14之间的空隙。本公开实施例通过在相同的工艺步骤中在第一表面S1和第二表面S2上形成介质层15，简化了工艺。但不限于此，位于第一表面S1上的介质层15和位于第二表面S2上的介质层15还可以在不同的工艺步骤中形成。介质层15用于保护第一焊垫12、传输线13、第二焊垫14在后续的工艺步骤中不被氧化或损坏。介质层15的材料可以为石墨烯、油墨、绿漆、环氧树脂等，例如，绿油。
再次参见图10至图12，在第一焊垫12上形成转接部18，转接部18包括覆盖第一焊垫12的第一子部181和覆盖第一子部181的第二子部182，包括：
刻蚀覆盖第一焊垫12的介质层15以形成第一开口T1，第一开口T1暴露第一焊垫12；
在第一表面S1上形成第二导电材料层17，第二导电材料层17填充第一开口T1并覆盖介质层15；
刻蚀覆盖介质层15的部分第二导电材料层17以形成转接部18，其中， 转接部18位于第一开口T1内的部分构成第一子部181，覆盖第一子部181及部分介质层15的部分构成第二子部182。
这里，第二导电材料层17可以使用化学气相沉积(CVD)、等离子增强CVD(PECVD)、物理气相沉积(PVD)、原子层沉积(ALD)、电镀、化学镀、溅射等工艺形成在衬底10的第一表面S1上。第二导电材料层17的材料包括钨(W)、铜(Cu)、钛(Ti)、钽(Ta)、镍(Ni)、铬(Cr)、金(Au)、银(Ag)、氮化钛(TiN)、氮化钽(TaN)、金属硅化物、金属合金或其任何组合，例如，铜。
继续参见图10，在一实施例中，在刻蚀覆盖第一焊垫12的介质层15以形成第一开口T1，第一开口T1暴露第一焊垫12的同一步骤中，方法还包括：刻蚀覆盖第二焊垫14的介质层15以形成第二开口T2，第二开口T2暴露第二焊垫14，第二焊垫14可以用于后续连接其他结构。本公开实施例通过在同一步骤中形成T1和T2，简化了工艺。但不限于此，第一开口T1和第二开口T2还可以在不同的步骤中形成。在一些实施例中，后续还可以继续刻蚀位于第二表面S2上的介质层15，使得介质层15的上表面与第二焊垫14的上表面齐平，或者移除位于多个第二焊垫14之间的介质层15，如此，便于在实际操作中将第二焊垫14与其他结构连接，本公开实施例在此不做过多限制。
继续参见图11，在第一表面S1上形成第二导电材料层17之前，方法还包括：在第一开口T1内形成复合增强层16，复合增强层16覆盖第一焊垫12。复合增强层16的材料可以为合金材料，例如钛，钛具有导电性好、强度高、易焊接等优点，起到良好的连接作用。但不限于此，任何符合上述要求的材料都可以作为本公开实施例中的复合增强层16使用。
接着，执行步骤504，在第二子部182上形成焊球21，形成如图1或图2所示的半导体结构。
焊球21可以为含铅锡球或不含铅锡球。在一实施例，焊球21在第一表面S1上的正投影与第二子部182在第一表面S1上的正投影完全重叠，或者焊球21在第一表面S1上的正投影落入第二子部182在第一表面S1上的正投影内，即第二子部182的横截面的尺寸大于或等于焊球21的横截面的尺寸，允许焊球21和第二子部182具有更大的接触面积，降低接触电阻，且有助于焊球21与第二子部182焊接的更牢固。在一些实施例中，第二子部182的形状为圆形柱，第二子部182的直径与焊球21的直径的比值在1至1.2之间，例如1.1。在一具体实施例中，第二子部182的直径的范围在40μm至510μm之间，厚度在10μm至20μm之间；焊球21的直径的范围在40μm至420μm之间。
再次参见图1或图2，在一实施例中，在形成焊球21之前，方法还包括：形成可焊层19，可焊层19覆盖第二子部182待与焊球21电连接的表面，可焊层19有助于使焊球21和第二子部182焊接的更牢固。可焊层19 待与焊球21电连接的一面的材料可以是锡(Sn)、金(Au)、银(Ag)。
图12、图1至图2示出的转接部18的第一子部181形成于第一开口T1内，第一子部181的高度H1等于或小于第一开口T1的高度H2。在本公开的另一实施例中，第一子部181仅部分形成于第一开口T1内，第一子部181的高度H1大于第一开口T1的高度H2，如图13至16、图3所示。
具体的，如图13所示，在形成介质层15，介质层15至少覆盖第一焊垫12、传输线13并填充第一焊垫12、传输线13之间的空隙之后，方法还包括：形成绝缘层25，绝缘层25覆盖位于第一表面S1上的介质层15。在后续工艺中，在形成转接部18之后，将去除绝缘层25，因此，在预设的刻蚀条件下，绝缘层25的刻蚀速率大于介质层15的刻蚀速率。
接下来，如图14所示，刻蚀覆盖介质层15的绝缘层25以及覆盖第一焊垫12的介质层15以分别形成第三开口T3、第一开口T1，第三开口T3和第一开口T1暴露第一焊垫12。
接下来，如图15所示，在第一表面S1上形成第二导电材料层17，第二导电材料层17填充第一开口T1、第三开口T3并覆盖绝缘层25。
接下来，如图16所示，刻蚀覆盖绝缘层25的部分第二导电材料层17以形成转接部18，其中，转接部18位于第一开口T1、第三开口T3内的部分构成第一子部181，覆盖第一子部181及部分绝缘层25的部分构成第二子部182。
接下来，去除绝缘层25并在第二子部182上形成焊球21，形成如图3所示的半导体结构。
在该实施例中，第一子部181部分位于第一开口T1内，第一子部181的高度H1大于第一开口T1的高度H2，第二子部182距离传输线13较远，如此，当半导体结构在工作时，能够减小第二子部182与传输线13之间的信号干扰。
在上述实施例中，在第一焊垫12上形成转接部18的方式均是先形成覆盖第一焊垫12的第二导电材料层17，接着刻蚀第二导电材料层17形成转接部18。但不限于此，如图17所示，在本公开又一实施例中，在第一焊垫12上形成转接部18，包括：刻蚀覆盖第一焊垫12的介质层15以形成第一开口T1，第一开口T1暴露第一焊垫12；提供转接部18，转接部18包括第一子部181和覆盖第一子部181的第二子部182；将转接部18的第一子部181与第一焊垫12进行焊接。
在一些实施例中，在将转接部18的第一子部181与第一焊垫12进行焊接之前，还包括：形成覆盖第一子部181的复合增强层16，连接部18通过复合增强层16与第一焊垫12焊接，复合增强层16起到良好的连接作用。
可以看出，本公开实施例中，焊球21与第二子部182进行焊接，第一焊垫12与第一子部181连接，在不改变焊球21尺寸的情况下，可以通过缩小第一焊垫12的尺寸，减小第一焊垫12在第一表面S1上占用的面积， 从而允许传输线13在第一表面S1上占用更大的面积，传输线13可以设计的更宽，减小或消除传输线13断裂的风险，避免传输线距离过近引起的电磁干扰、信号串扰，且由于第一焊垫12的尺寸较小，能够避免或缓解传输线13传输路径较长的问题。
应当说明的是，本领域技术人员能够对上述步骤顺序进行变换而并不离开本公开的保护范围，以上所述，仅为本公开的可选实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例提供的半导体结构、封装器件及半导体结构的制造方法，其中，所述半导体结构包括：衬底，所述衬底包括第一表面；第一焊垫，位于所述第一表面上；转接部，位于所述第一焊垫上；所述转接部包括覆盖所述第一焊垫的第一子部和覆盖所述第一子部的第二子部，其中，所述第一子部、所述第一焊垫在所述第一表面上的正投影落入所述第二子部在所述第一表面上的正投影内；焊球，位于所述第二子部上。焊球通过转接部与第一焊垫电连接，且焊球位于具有更大尺寸的第二子部上，如此，在不改变焊球尺寸的情况下，可以通过缩小第一焊垫的尺寸，减小第一焊垫在衬底表面占用的面积，从而允许传输线在衬底表面占用更大的面积，传输线可以设计的更宽，减小或消除传输线断裂的风险，避免传输线距离过近引起的电磁干扰、信号串扰，且由于第一焊垫的尺寸较小，能够避免或缓解传输线传输路径较长的问题。

Claims (18)

  1. 一种半导体结构，包括：
    衬底，所述衬底包括第一表面；
    第一焊垫，位于所述第一表面上；
    转接部，位于所述第一焊垫上；所述转接部包括覆盖所述第一焊垫的第一子部和覆盖所述第一子部的第二子部，其中，所述第一子部、所述第一焊垫在所述第一表面上的正投影落入所述第二子部在所述第一表面上的正投影内；
    焊球，位于所述第二子部上。
  2. 根据权利要求1所述的半导体结构，其中，所述焊球在所述第一表面上的正投影与所述第二子部在所述第一表面上的正投影完全重叠，或者所述焊球在所述第一表面上的正投影落入所述第二子部在所述第一表面上的正投影内。
  3. 根据权利要求1所述的半导体结构，其中，所述第一子部在所述第一表面上的正投影与所述第一焊垫在所述第一表面上的正投影完全重叠，或者所述第一子部在所述第一表面上的正投影落入所述第一焊垫在所述第一表面上的正投影内。
  4. 根据权利要求1所述的半导体结构，其中，在垂直于所述第一表面且由所述第一焊垫指向所述第二子部的方向上，所述第一子部的宽度逐渐增加。
  5. 根据权利要求1所述的半导体结构，其中，所述半导体结构还包括：复合增强层，所述复合增强层位于所述第一子部和所述第一焊垫之间。
  6. 根据权利要求1所述的半导体结构，其中，所述半导体结构还包括：可焊层，所述可焊层位于所述焊球和所述第二子部之间。
  7. 根据权利要求1所述的半导体结构，其中，所述半导体结构还包括：传输线，所述传输线位于所述第一表面上；介质层，所述介质层覆盖所述传输线且填充所述第一焊垫和所述传输线之间的空隙；其中，所述介质层内形成有暴露出所述第一焊垫的第一开口，所述第一子部位于所述第一开口内，所述第二子部覆盖所述第一子部及部分所述介质层。
  8. 根据权利要求7所述的半导体结构，其中，所述半导体结构还包括：多个第二焊垫，位于所述衬底与所述第一表面相对的第二表面上，所述介质层还填充所述多个第二焊垫之间的空隙；其中，所述介质层内形成有多个第二开口，所述第二开口暴露所述第二焊垫。
  9. 一种封装器件，所述封装器件包括：至少一个芯片以及如权利要求1至8所述的任一半导体结构，所述至少一个芯片与所述半导体结构键合连接。
  10. 一种半导体结构的制造方法，包括：
    提供衬底，所述衬底包括第一表面；
    在所述第一表面上形成第一焊垫；
    在所述第一焊垫上形成转接部，所述转接部包括覆盖所述第一焊垫的第一子部和覆盖所述第一子部的第二子部，其中，所述第一子部、所述第一焊垫在所述第一表面上的正投影落入所述第二子部在所述第一表面上的正投影内；
    在所述第二子部上形成焊球。
  11. 根据权利要求10所述的制造方法，其中，在所述第一表面上形成第一焊垫，包括：
    形成第一导电材料层，所述第一导电材料层至少覆盖所述第一表面；
    刻蚀覆盖所述第一表面的所述第一导电材料层以在所述第一表面上形成所述第一焊垫和传输线。
  12. 根据权利要求11所述的制造方法，其中，在所述第一焊垫上形成转接部之前，所述方法还包括：
    形成介质层，所述介质层至少覆盖所述第一焊垫、所述传输线并填充所述第一焊垫、所述传输线之间的空隙。
  13. 根据权利要求12所述的制造方法，其中，在所述第一焊垫上形成转接部，所述转接部包括覆盖所述第一焊垫的第一子部和覆盖所述第一子部的第二子部，包括：
    刻蚀覆盖所述第一焊垫的所述介质层以形成第一开口，所述第一开口暴露所述第一焊垫；
    在所述第一表面上形成第二导电材料层，所述第二导电材料层填充所述第一开口并覆盖所述介质层；
    刻蚀覆盖所述介质层的部分所述第二导电材料层以形成所述转接部，其中，所述转接部位于所述第一开口内的部分构成所述第一子部，覆盖所述第一子部及部分所述介质层的部分构成所述第二子部。
  14. 根据权利要求13所述的制造方法，其中，在所述第一表面上形成第二导电材料层之前，所述方法还包括：在所述第一开口内形成复合增强层，所述复合增强层覆盖所述第一焊垫。
  15. 根据权利要求14所述的制造方法，其中，在形成焊球之前，所述方法还包括：形成可焊层，所述可焊层覆盖所述第二子部待与所述焊球电连接的表面。
  16. 根据权利要求12所述的制造方法，其中，
    形成第一导电材料层，所述第一导电材料层至少覆盖所述第一表面，包括：形成第一导电材料层，所述第一导电材料层覆盖所述第一表面及所述衬底的与所述第一表面相对的第二表面；
    在刻蚀覆盖所述第一表面的所述第一导电材料层以在所述第一表面上 形成所述第一焊垫和传输线的同一步骤中，所述方法还包括：刻蚀覆盖所述第二表面的所述第一导电材料层，以形成多个第二焊垫。
  17. 根据权利要求16所述的制造方法，其中，形成介质层，所述介质层至少覆盖所述第一焊垫、所述传输线并填充所述第一焊垫、所述传输线之间的空隙，包括：
    在所述第一表面和所述第二表面上形成所述介质层，所述介质层还覆盖所述多个第二焊垫并填充位于所述多个第二焊垫之间的空隙。
  18. 根据权利要求17所述的制造方法，其中，在刻蚀覆盖所述第一焊垫的所述介质层以形成第一开口，所述第一开口暴露所述第一焊垫的同一步骤中，所述方法还包括：
    刻蚀覆盖所述第二焊垫的介质层以形成第二开口，所述第二开口暴露所述第二焊垫。
PCT/CN2022/105548 2022-07-04 2022-07-13 一种半导体结构、封装器件及半导体结构的制造方法 Ceased WO2024007356A1 (zh)

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