WO2024007315A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

Info

Publication number
WO2024007315A1
WO2024007315A1 PCT/CN2022/104677 CN2022104677W WO2024007315A1 WO 2024007315 A1 WO2024007315 A1 WO 2024007315A1 CN 2022104677 W CN2022104677 W CN 2022104677W WO 2024007315 A1 WO2024007315 A1 WO 2024007315A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
communication
signal lines
communication line
conductive layer
Prior art date
Application number
PCT/CN2022/104677
Other languages
English (en)
French (fr)
Inventor
马俊如
刘汉青
陈伟
魏玉轩
郭洪文
毛磊
李鑫
田鹏程
邹浩伟
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/104677 priority Critical patent/WO2024007315A1/zh
Priority to CN202280002162.1A priority patent/CN117694035A/zh
Publication of WO2024007315A1 publication Critical patent/WO2024007315A1/zh

Links

Images

Definitions

  • This article relates to but is not limited to the field of display technology, and specifically refers to a display substrate and a display device.
  • Electrophoretic electronic paper (EPD, Electrophoretic Display) is a paper-like display. Its working principle relies on the electrophoresis of black particles and white particles under the action of voltage to form black and white colors. Due to its own reflective and bistable display principles, it has the characteristics of eye protection and energy saving. It has gradually entered the education, medical and transportation fields from the price tag market, and has potential application value. However, traditional electrophoretic electronic paper products have poor interactive capabilities.
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • a display substrate including: a substrate, a circuit structure layer and an electronic paper film sequentially disposed on the substrate.
  • the circuit structure layer includes: a plurality of first signal lines extending along a first direction, a plurality of second signal lines extending along a second direction, a plurality of driving units, and at least one near field communication coil.
  • the first direction intersects the second direction.
  • a plurality of first signal lines and a plurality of second signal lines may intersect to form a plurality of sub-pixel regions.
  • the driving unit is located in the sub-pixel area and is electrically connected to the first signal line and the second signal line.
  • the driving unit is configured to control the display pattern of the electronic paper film corresponding to the sub-pixel area.
  • the near field communication coil may include: at least one first communication line extending along the first direction and at least one second communication line extending along the second direction. At least one first communication line and at least one second communication line are electrically connected.
  • At least one first signal line is adjacent to the first communication line in the second direction, and at least one second signal line is adjacent to the second communication line in the first direction.
  • Communication traces are adjacent.
  • At least one sub-pixel area is spaced between two adjacent first communication lines in the second direction, and between two adjacent second communication lines in the first direction separated by at least one sub-pixel area.
  • the at least one first communication trace is located on a side of the at least one second communication trace close to the substrate; the plurality of first signal lines are located on the plurality of first communication traces. Two signal lines are close to one side of the substrate.
  • the at least one second communication line and the plurality of second signal lines are in the same layer structure.
  • the at least one first communication line and the plurality of first signal lines are in the same layer structure.
  • the at least one first communication trace is located on a side of the plurality of first signal lines away from the substrate.
  • the at least one first communication line includes: a plurality of first sub-communication line segments extending along the first direction and arranged in sequence, and two adjacent first sub-communication line segments pass through the first sub-communication line segment.
  • a connection electrode is electrically connected, and the first connection electrode is located on a side of the first sub-communication line segment away from the substrate.
  • the substrate includes: at least one near field communication area and at least one non-near field communication area; the at least one near field communication coil is located in the at least one near field communication area, and the At least one non-near field communication area is provided with at least one first virtual communication line extending along the first direction and at least one second dummy coil extending along the second direction; the first communication line and the The first virtual communication line is disconnected, and the second communication line is disconnected from the second dummy communication line.
  • the circuit structure layer further includes: a plurality of touch signal lines and a plurality of touch electrodes; the plurality of touch signal lines extend along the second direction, and at least one touch signal The wires are electrically connected to a plurality of touch electrodes that are electrically connected to each other and spaced apart.
  • the at least one second communication line is arranged at intervals between the plurality of touch signal lines, and the distance between the adjacent second communication line and the touch signal line is separated by at least one sub-pixel area.
  • the driving unit at least includes: a transistor and a pixel electrode; the pixel electrode is located in the sub-pixel area; a gate electrode of the transistor is electrically connected to the first signal line, and the The first electrode of the transistor is electrically connected to the second signal line, and the second electrode of the transistor is electrically connected to the pixel electrode.
  • the circuit structure layer in a direction perpendicular to the display substrate, includes: a first conductive layer, a semiconductor layer, a first transparent conductive layer, and a two conductive layers and a second transparent conductive layer.
  • the first conductive layer at least includes: the plurality of first signal lines and gates of transistors of the driving unit.
  • the semiconductor layer includes at least an active layer of a transistor of the driving unit.
  • the first transparent conductive layer at least includes: the plurality of touch electrodes.
  • the second conductive layer at least includes: the plurality of second signal lines, the at least one second communication line, and the plurality of touch signal lines.
  • the second transparent conductive layer at least includes: the pixel electrode.
  • the at least one first communication trace is located on the first conductive layer or the first transparent conductive layer.
  • an inorganic insulating layer and an organic insulating layer are provided between the second conductive layer and the transparent conductive layer, and the organic insulating layer is located on a side of the inorganic insulating layer away from the substrate. side.
  • the electronic paper film is configured to display using light incident on one side of the substrate.
  • embodiments of the present disclosure provide a display device including the display substrate as described above.
  • embodiments of the present disclosure provide a method for preparing a display substrate, including: forming a circuit structure layer on the substrate.
  • the circuit structure layer includes: a plurality of first signal lines extending along a first direction, and a circuit structure layer extending along a first direction.
  • a plurality of second signal lines extending in two directions, a plurality of drive units, and at least one near field communication coil; the first direction intersects the second direction; the plurality of first signal lines and the plurality of second The signal lines intersect to form multiple sub-pixel areas; the driving unit is located in the sub-pixel area and is electrically connected to the first signal line and the second signal line; the near field communication coil includes: along the first direction At least one first communication line extending and at least one second communication line extending along the second direction, the at least one first communication line and the at least one second communication line being electrically connected;
  • the circuit structure layer is provided with an electronic paper film on a side away from the substrate; the driving unit of the circuit structure layer is configured to control the display pattern of the electronic paper film corresponding to the sub-pixel area.
  • forming the circuit structure layer on the substrate includes: sequentially forming a first conductive layer, a first insulating layer, a semiconductor layer, a first transparent conductive layer, and a second layer on the substrate. a conductive layer, a second insulating layer, a third insulating layer and a second transparent conductive layer.
  • the first conductive layer at least includes: the plurality of first signal lines and the gates of the transistors of the driving unit; the semiconductor layer at least includes: the active layer of the transistors of the driving unit; the first The transparent conductive layer at least includes: a plurality of touch electrodes; the second conductive layer at least includes: the plurality of second signal lines, the at least one second communication line and a plurality of touch signal lines, the driving The first pole and the second pole of the transistor of the unit; the second transparent conductive layer at least includes: a plurality of pixel electrodes.
  • the transistor of the driving unit and the first signal line are of an integrated structure
  • the first electrode of the transistor of the driving unit and the second signal line are of an integrated structure
  • the second electrode of the transistor is of an integrated structure.
  • the pole is electrically connected to the pixel electrode.
  • Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure
  • Figure 2 is a partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure
  • Figure 3 is a schematic diagram of a display area of a display substrate according to at least one embodiment of the present disclosure
  • Figure 4 is a partial schematic diagram of the circuit structure layer of the near field communication area according to at least one embodiment of the present disclosure
  • Figure 5 is a schematic diagram of the circuit structure layer after forming the second conductive layer in Figure 4.
  • Figure 6 is a partial schematic diagram of the circuit structure layer of the display area according to at least one embodiment of the present disclosure.
  • Figure 7 is a partial cross-sectional schematic diagram along the Q-Q’ direction in Figure 6;
  • Figure 8A is a partial schematic diagram of the circuit structure layer after forming the first conductive layer in Figure 6;
  • Figure 8B is a partial schematic diagram of the circuit structure layer after forming the semiconductor layer in Figure 6;
  • Figure 8C is a partial schematic diagram of the circuit structure layer after forming the first transparent conductive layer in Figure 6;
  • Figure 8D is a partial schematic diagram of the circuit structure layer after forming the second conductive layer in Figure 6;
  • Figure 8E is a partial schematic diagram of the circuit structure layer after forming the third insulating layer in Figure 6;
  • FIG. 9A is a partial schematic diagram of the circuit structure layer of the display area according to at least one embodiment of the present disclosure.
  • Figure 9B is a schematic diagram of the circuit structure layer after forming the second conductive layer in Figure 9A;
  • Figure 10 is a partial cross-sectional view along the R-R’ direction in Figure 9A;
  • FIG. 11A is a partial schematic diagram of the circuit structure layer of the display area according to at least one embodiment of the present disclosure.
  • Figure 11B is a schematic diagram of the circuit structure layer after forming the second conductive layer in Figure 11A;
  • FIG. 12A is another partial schematic diagram of the circuit structure layer of the display area according to at least one embodiment of the present disclosure.
  • Figure 12B is a schematic diagram of the circuit structure layer after forming the second conductive layer in Figure 12A;
  • FIG. 13A is another schematic diagram of the circuit structure layer of the display area according to at least one embodiment of the present disclosure.
  • Figure 13B is a schematic diagram of the circuit structure layer after forming the second conductive layer in Figure 13A;
  • Figure 14 is a partial enlarged schematic diagram along the U-U’ direction in Figure 13A;
  • Figure 15 is another schematic diagram of the circuit structure layer of the display area according to at least one embodiment of the present disclosure.
  • Figure 16 is a partial enlarged schematic diagram along the P-P’ direction in Figure 15;
  • FIG. 17 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • the terms “mounted,” “connected,” and “connected” are to be construed broadly unless otherwise expressly stated and limited. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • the meanings of the above terms in this disclosure can be understood according to the circumstances.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode .
  • the channel region refers to a region through which current mainly flows.
  • one of the electrodes is called the first electrode, and the other electrode is called the second electrode.
  • the first electrode can be the source electrode or the drain electrode
  • the second electrode can be is the drain electrode or the source electrode
  • the gate electrode of the transistor is called the control electrode.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • component having some electrical function There is no particular limitation on the “component having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • components with some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, a state in which the angle is -5° or more and 5° or less may be included.
  • vertical refers to a state in which the angle formed by two straight lines is 80° or more and 100° or less. Therefore, it may include a state in which the angle is 85° or more and 95° or less.
  • NFC Near Field Communication
  • This embodiment provides a display substrate that can integrate NFC functions, thereby improving the interactive capabilities of display products.
  • This embodiment provides a display substrate, including: a substrate, a circuit structure layer and an electronic paper film sequentially provided on the substrate.
  • the circuit structure layer includes: a plurality of first signal lines extending along a first direction, a plurality of second signal lines extending along a second direction, a plurality of driving units, and at least one near field communication coil.
  • the first direction intersects the second direction, for example, the first direction may be perpendicular to the second direction.
  • a plurality of first signal lines and a plurality of second signal lines may intersect to form a plurality of sub-pixel regions.
  • the driving unit may be located in the sub-pixel area and electrically connected to the first signal line and the second signal line.
  • the driving unit is configured to control the display pattern of the electronic paper film corresponding to the sub-pixel area.
  • the near field communication coil may include: at least one first communication line extending along the first direction and at least one second communication line extending along the second direction. At least one first communication line and at least one second communication line are electrically connected.
  • the first communication wires and the second communication wires can be arranged in a mesh structure and electrically connected to form a near field communication coil with a mesh structure to support implementation inside the display substrate.
  • Integrated NFC function Integrated NFC function.
  • At least one first signal line is adjacent to a first communication trace in the second direction
  • at least one second signal line is adjacent to a second communication trace in the first direction.
  • no other devices or traces are provided between the adjacent first signal line and the first communication line; in the first direction, the adjacent second signal line and the second There are no other devices or traces between communication traces.
  • the near field communication coils can be reasonably arranged in the display area.
  • At least one sub-pixel area may be spaced between two adjacent first communication traces in the second direction, and may be spaced between two adjacent second communication traces in the first direction. At least one sub-pixel area.
  • a second communication line may be arranged between at least two columns of adjacent sub-pixel regions in the first direction, and a second communication line may be arranged between at least two rows of adjacent sub-pixel regions in the second direction.
  • the at least one first communication trace may be located on a side of the at least one second communication trace close to the substrate.
  • the plurality of first signal lines may be located on a side of the plurality of second signal lines close to the substrate.
  • at least one second communication line and a plurality of second signal lines may be in the same layer structure.
  • the at least one first communication line and the plurality of first signal lines may be in the same layer structure, or the at least one first communication line may be located on a side of the plurality of first signal lines away from the substrate.
  • this embodiment is not limited to this.
  • the circuit structure layer may further include: a plurality of touch signal lines and a plurality of touch electrodes.
  • the plurality of touch signal lines may extend along the second direction, and at least one touch signal line may be electrically connected to a plurality of touch electrodes that are electrically connected to each other and spaced apart. Multiple touch electrodes are electrically connected to form a touch sensing area.
  • the display substrate of this example can integrate NFC function and touch function, thereby improving the interactive capabilities of the display product.
  • At least one second communication line can be arranged at intervals between a plurality of touch signal lines, and adjacent second communication lines and touch signal lines can be spaced apart by at least one sub-pixel. area.
  • FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate may include: a display area AA and a peripheral area BB located around the display area AA.
  • the display area AA may be provided with a plurality of first signal lines 21 extending in the first direction X and a plurality of second signal lines 22 extending in the second direction Y.
  • the first direction X intersects the second direction Y.
  • the first direction X may be perpendicular to the second direction Y.
  • the plurality of first signal lines 21 may be arranged in sequence along the second direction Y, and the plurality of second signal lines 22 may be arranged in sequence along the first direction X.
  • a plurality of first signal lines 21 and a plurality of second signal lines 22 may intersect to form multiple sub-pixel regions.
  • the plurality of first signal lines 21 may include a plurality of scan lines
  • the plurality of second signal lines 22 may include a plurality of data lines.
  • the peripheral area BB may include: an upper border located on the upper side of the display area AA, a lower border located on the lower side of the display area AA, a left border located on the left side of the display area AA, and a left border located on the left side of the display area AA.
  • the upper border can be connected to the left and right borders, and the lower border can be connected to the left and right borders.
  • the peripheral area BB may be provided with a plurality of first lead lines 23 and a plurality of second lead lines 24.
  • the plurality of first lead lines 23 may be located on the left and right borders, and the plurality of second lead lines 24 may be located on the lower frame.
  • first signal line 21 may be electrically connected to the first lead-out line 23 on the left frame, and the other end may be electrically connected to the first lead-out line 23 on the right frame, so as to receive signals through the first lead-out line 23 .
  • the first leading line 23 may extend from the left frame or the right frame to the lower frame.
  • the second lead-out line 24 may be electrically connected to an end of the second signal line 22 extending to the lower frame, so as to provide a signal to the second signal line 22 .
  • the lower frame may include: a first circuit area 101 and a first binding area 102 .
  • the first binding area 102 may be located on a side of the first circuit area 101 away from the display area AA.
  • the first circuit area 101 may be provided with a display control circuit.
  • the first lead-out line 23 and the second lead-out line 24 may extend to the first circuit area 101 and be electrically connected with the display control circuit.
  • the first binding area 102 may be provided with a plurality of first binding pins, and the plurality of first binding pins may be bonded and connected to a flexible circuit board (FPC) that provides display control.
  • FPC flexible circuit board
  • the display area AA may further include a plurality of driving units, and the plurality of driving units may be distributed in an array.
  • each driving unit may be located in a sub-pixel area.
  • Each driving unit can be in contact with the electronic paper film in the corresponding sub-pixel area and can control the display pattern of the electronic paper film in the corresponding sub-pixel area.
  • Each driving unit may include at least: a transistor and a pixel electrode.
  • the gate electrode of the transistor may be electrically connected to the first signal line, the first electrode may be electrically connected to the second signal line, and the second electrode may be electrically connected to the pixel electrode.
  • a first signal line may provide a scan signal
  • a second signal line may provide a data signal.
  • Each transistor may function as a switch, so that when a signal is supplied to a first signal line (eg, a scan line) and a second signal line (eg, a data line), the transistor may be in an on state. When in the on state, voltage can be applied to the pixel electrode.
  • a first signal line eg, a scan line
  • a second signal line eg, a data line
  • the display area AA may also include: a plurality of touch electrodes arranged in an array (as self-capacitance electrodes), and a touch signal line 25 electrically connected to the touch electrodes.
  • the orthographic projection of the touch electrode on the substrate may overlap with the orthographic projection of the pixel electrode on the substrate.
  • the plurality of touch signal lines 25 may be arranged sequentially along the first direction X and extend along the second direction Y.
  • a plurality of touch lead-out lines 26 may also be provided in the peripheral area BB. Multiple touch lead-out lines 26 may be located on the upper frame.
  • the upper frame may include: a second circuit area 103 and a second binding area 104 .
  • the second binding area 104 may be located on a side of the second circuit area 103 away from the display area AA.
  • the second circuit area 103 may be provided with a touch control circuit.
  • the touch lead-out wire 26 can extend to the second circuit area 103 and be electrically connected to the touch control circuit.
  • the second binding area 104 may be provided with a plurality of second binding pins, and the plurality of second binding pins may be bound and connected to a flexible circuit board that provides touch control.
  • the touch electrodes may be electrically connected to the touch control circuit through the touch signal lines 25 and the touch lead-out lines 26 .
  • the touch object for example, a human finger
  • touches the display device and the capacitance of the touch electrode located at the touch point will change.
  • the touch control circuit determines this by detecting the change in self-capacitance of the touch electrode. Touch location.
  • this embodiment is not limited to this.
  • the display control circuit and the touch control circuit can be integrated into one display touch control circuit, and the display touch control circuit can be disposed on the lower frame or the upper frame.
  • the display substrate of this embodiment may adopt self-capacitive touch technology.
  • the touch signal line detected by the touch electrode is used to transmit the touch signal to implement the touch function.
  • multiple touch electrodes may be electrically connected to form a touch sensing area.
  • a touch sensing area may include dozens by dozens of touch electrodes in sub-pixel areas.
  • the length of a touch sensing area may be approximately 4 millimeters (mm) and may include touch electrodes located in 25 to 40 sub-pixel areas.
  • Multiple touch electrodes in each touch sensing area may be electrically connected to one touch signal line.
  • the touch electrodes can also be reused as common electrodes.
  • a common voltage can be provided to the common electrodes through the touch signal lines to implement the display function.
  • FIG. 2 is a partial cross-sectional view of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate may include: a substrate 300, and a circuit structure layer 400 and an electronic paper film 500 sequentially disposed on the substrate 300.
  • the electronic paper film 500 may be disposed on the side of the circuit structure layer 400 away from the substrate 300 through an adhesive layer.
  • the electronic paper film 500 may include: an ink layer 501 , a control electrode 502 and a protective film 503 .
  • the ink layer 501 can express a color or black and white pattern through movement of particles according to an applied electric field (ie, an electrophoretic phenomenon), and display a pattern through reflection or absorption of external light incident on the pattern.
  • the ink layer 501 includes a plurality of microcapsules, which are transparent fluids containing white particles and black particles. Black or white patterns are created by applying an electric field to multiple microcapsules. For example, white particles are charged (+) and black particles are charged (-) so that they move in opposite directions by applying an electric field.
  • the image pattern of the ink layer can be maintained up to the point where the electric field changes.
  • color display can be achieved by stacking color filters on an ink layer, or using colored particles instead of black and white particles.
  • the control electrode 502 of the electronic paper film 500 can serve as a common electrode to provide a common voltage Vcom.
  • control electrode 502 may remain a constant electrode and may be connected to ground.
  • the electric field generated between the control electrode 502 and the pixel electrode of the circuit structure layer can promote the movement of charged particles.
  • the control electrode 502 may be electrically connected to a common electrode of the circuit structure layer.
  • the electronic paper film 500 may be configured to perform display using light incident from one side of the substrate 300 .
  • the display substrate can be used upside down. During use, the substrate faces the user, and the electronic paper film 500 uses the side close to the substrate 300 for display, so that the user can observe the display pattern of the electronic paper film 500 through the substrate 300 .
  • the display substrate may provide a near field communication coil in the display area to integrate NFC functionality.
  • a magnetic field will be generated. This magnetic field will electromagnetically couple with the induced magnetic field of the target terminal device to be connected.
  • the two devices will be paired and connected successfully, and data can be processed. exchange.
  • the touch control circuit provided in the second circuit area 103 can integrate an NFC control circuit, and the near field communication coil in the display area can be electrically connected to the touch control circuit in the second circuit area 103 through lead wires located on the upper frame. connect.
  • the NFC control circuit can be integrated with the display control circuit, or the NFC control circuit, the display control circuit, and the touch control circuit can be integrated and provided on the upper frame or the lower frame.
  • FIG. 3 is a schematic diagram of a display area according to at least one embodiment of the present disclosure.
  • the display area AA may include: two near field communication areas (for example, the first near field communication area A11 and the second near field communication area A12 ) and three non-near field communication areas ( For example, the first non-near field communication area A21, the second non-near field communication area A22, and the third non-near field communication area A23).
  • the orthographic projection of the first near field communication area A11 and the second near field communication area A12 on the substrate may be U-shaped, and the second near field communication area A12 may be located inside the first near field communication area A11.
  • the first non-near field communication area A21 may be located inside the first near field communication area A12
  • the second non-near field communication area A22 may be located between the first near field communication area A11 and the second near field communication area A12
  • the third non-near field communication area A21 may be located inside the first near field communication area A12.
  • the non-near field communication area A23 may be located on a side of the first near field communication area A11 away from the second near field communication area A12.
  • this embodiment is not limited to this. In this example, by setting multiple near field communication areas, communication quality can be improved.
  • FIG. 4 is a partial schematic diagram of a near field communication area according to at least one embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of the circuit structure layer after forming the second conductive layer in FIG. 4 .
  • Figure 4 shows a sub-pixel area arranged according to 4 ⁇ 4 in a near field communication area of the display area. In some examples, as shown in FIG.
  • the near field communication area may include: a plurality of first communication traces extending along the first direction X (for example, first communication traces ML(j) and ML(j+1 )), a plurality of second communication traces extending along the second direction Y (for example, second communication traces NL(i) to NL(i+2)), a plurality of first signals extending along the first direction X lines (for example, including scan lines GL(m-1) to GL(m+3)), a plurality of second signal lines extending along the second direction Y (for example, including data lines DL(n-1) to DL(n+) 2)), and the touch signal line Tx extending along the second direction Y.
  • i, j, m and n can all be positive integers.
  • multiple scan lines and multiple data lines intersect to form multiple sub-pixel regions.
  • At least one scan line may be adjacent to the first communication line in the second direction Y.
  • the scan line GL(m-1) may be adjacent to the first communication line ML(j)
  • the scan line GL(m+3) may be adjacent to the first communication line ML(j+1).
  • Four rows of sub-pixel areas may be spaced between two adjacent first communication lines (for example, ML(j) and ML(j+1)).
  • this embodiment is not limited to this.
  • one row of sub-pixel areas may be spaced between two adjacent first communication lines.
  • At least one data line may be adjacent to the second communication line or the touch signal line in the first direction X.
  • the data line DL(n) may be adjacent to the second communication line NL(i)
  • the data line DL(n+1) may be adjacent to the touch signal line Tx
  • the data line DL(n+2) may be adjacent to the touch signal line Tx.
  • the second communication line NL(i+1) is adjacent.
  • the touch signal line Tx may be electrically connected to 4 ⁇ 4 touch electrodes 430 . As shown in FIGS.
  • the touch electrodes 430 adjacent along the second direction Y among the 4 ⁇ 4 touch electrodes 430 may have an integrated structure, and the touch electrodes 430 adjacent along the first direction X may pass through the first direction X.
  • the two connecting electrodes 440 are electrically connected.
  • the second connection electrode 440 electrically connected to the touch electrode 430 in the fourth row and second column and the touch electrode 430 in the fourth row and third column can be electrically connected to the touch signal line Tx at the same time, thereby realizing the touch signal line Tx Electrical connection with multiple touch electrodes 430 .
  • At least one column of sub-pixel regions is spaced between adjacent second communication lines and touch signal lines Tx.
  • the second communication lines NL(i) and NL(j+1) are located on both sides of the touch signal line Tx in the first direction X, and are separated from the touch signal line Tx by one column of sub-pixel regions.
  • this embodiment is not limited to this.
  • a data line and a touch signal line can be provided between two adjacent columns of sub-pixel areas, or a data line and a second communication line can be provided.
  • a scan line may be set between two adjacent rows of sub-pixel areas, or a scan line and a first communication line may be set.
  • the wiring arrangement of this embodiment can save space and avoid wiring aggregation and signal interference.
  • the first communication line ML(j) may include a plurality of first sub-communications arranged sequentially along the first direction X. Line segments 451 and adjacent first sub-communication line segments 451 may be electrically connected through first connection electrodes 452 .
  • the first communication line ML(j+1) can be electrically connected to the second communication line NL(i+2) through a first connection electrode 452, thereby realizing a mesh of the first communication line and the second communication line. connect.
  • the near field communication coil of this example may be a mesh structure.
  • FIG. 6 is a partial schematic diagram of the circuit structure layer of the display area according to at least one embodiment of the present disclosure.
  • FIG. 6 may be a schematic diagram of two sub-pixel areas in the second row, second column and second row, third column in FIG. 4 .
  • Figure 7 is a partial cross-sectional view along the Q-Q’ direction in Figure 6.
  • the circuit structure layer of the display area may include: the first conductive layer 41 , the semiconductor layer 40 , which are sequentially disposed on the substrate 300 .
  • a first insulating layer 301 may be disposed between the first conductive layer 41 and the semiconductor layer 40
  • a second insulating layer 302 and a third insulating layer 303 may be disposed between the second conductive layer 43 and the second transparent conductive layer 44 .
  • the first insulating layer 301 and the second insulating layer 302 may be inorganic insulating layers
  • the third insulating layer 303 may be an organic insulating layer.
  • this embodiment is not limited to this.
  • FIG. 8A is a partial schematic diagram of the circuit structure layer after forming the first conductive layer in FIG. 6 .
  • the first conductive layer 41 may include: a gate 411 of the transistor T1 of the driving unit, and a plurality of first signal lines extending along the first direction Lines GL(m) and GL(m+1)).
  • the first signal line and the gate electrodes 411 of the plurality of transistors T1 connected in the same row may have an integrated structure.
  • FIG. 8B is a partial schematic diagram of the circuit structure layer after forming the semiconductor layer in FIG. 6 .
  • the semiconductor layer 40 may include an active layer 410 of the transistor T1 .
  • the orthographic projection of the active layer 410 of the transistor T1 on the substrate (for example, may be rectangular) may overlap with the orthographic projection of the gate electrode 411 on the substrate.
  • FIG. 8C is a partial schematic diagram of the circuit structure layer after forming the first transparent conductive layer in FIG. 6 .
  • the first transparent conductive layer 42 may include a plurality of touch electrodes 430 .
  • the orthographic projection of the touch electrode 430 in the sub-pixel area on the substrate may be T-shaped.
  • the plurality of touch electrodes 430 adjacent along the second direction Y may have an integrated structure.
  • FIG. 8D is a partial schematic diagram of the circuit structure layer after forming the second conductive layer in FIG. 6 .
  • the second conductive layer 43 may include: a first pole 412 , a second pole 413 and a third pole 414 of the transistor T1 , a plurality of second signal lines (eg, data lines DL(n) to DL(n+2)), the touch signal line Tx, and a plurality of second communication lines (for example, NL(i) and NL(i+1)).
  • the orthographic projection of the first pole 411, the second pole 413 and the third pole 414 of the transistor T1 on the substrate all overlap with the orthographic projection of the active layer 410 on the substrate.
  • the first pole 412 , the second pole 413 and the third pole 414 of the transistor T1 are all in direct contact with the active layer 410 .
  • the first electrode 412 of the transistor T1 and a data line (such as the data line DL(n)) that are electrically connected may be of an integrated structure.
  • the second electrode 413 of the transistor T1 may be electrically connected to the pixel electrode 420 later.
  • the third electrode of the transistor T1 The orthographic projection of the pole 414 on the substrate may be located on the same side of the first pole 412 and the second pole 413 in the second direction Y.
  • FIG. 8E is a partial schematic diagram of the circuit structure layer after forming the third insulating layer in FIG. 6 .
  • the third insulating layer 303 may be provided with a plurality of via holes, which may include, for example, first via holes V1 to third via holes V3.
  • the third insulating layer 303 and the second insulating layer 302 in the first via hole V1 may be removed, exposing the surface of the second electrode 413 of the transistor T1.
  • the third insulating layer 303 and the second insulating layer 302 in the second via hole V2 and the third via hole V3 can be removed to expose the surface of the touch electrode 430 .
  • Orthographic projections of the second via hole V2 and the third via hole V3 on the substrate may be located at both ends of the touch electrode 430 along the first direction X.
  • the second transparent conductive layer 44 may include: a plurality of pixel electrodes 420 and a plurality of second connection electrodes 440 .
  • the pixel electrode 420 may be located within the sub-pixel area.
  • the pixel electrode 420 may be electrically connected to the second electrode 413 of one transistor T1 through the first via hole V1.
  • the second connection electrode 440 may extend along the first direction X.
  • One end of the second connection electrode 440 can be electrically connected to the touch electrode 430 in one sub-pixel area through the second via hole V2, and can also be electrically connected to the touch electrode 430 in another sub-pixel area, thereby realizing the first Electrical connection between two adjacent touch electrodes 430 arranged in the direction X.
  • the front projection of a second connection electrode 440 on the substrate may overlap with the front projection of the touch signal line Tx and a data line on the substrate, or may overlap with a data line and a second communication line on the substrate. There is overlap in the orthographic projections of .
  • FIG. 9A is a partial schematic diagram of the circuit structure layer of the display area according to at least one embodiment of the present disclosure.
  • FIG. 9A is a schematic diagram of two sub-pixel areas in the first row, second column and first row, third column in FIG. 4 .
  • FIG. 9B is a schematic diagram of the circuit structure layer after forming the second conductive layer in FIG. 9A.
  • Figure 10 is a partial cross-sectional view along the R-R' direction in Figure 9A.
  • the first communication line ML(j) may include: a plurality of lines arranged sequentially along the first direction X.
  • a first sub-communication line segment 451 may be located within a sub-pixel area. Adjacent first sub-communication line segments 451 may be electrically connected through first connection electrodes 452.
  • the first sub-communication line segment 451 may be a strip line, and may be located on one side of the touch electrode 430 in the second direction Y in a sub-pixel area. As shown in FIG. 10 , the first sub-communication line segment 451 may be located on the first transparent conductive layer.
  • the first sub-communication line segment 451 may have the same layer structure as the touch electrode 430 .
  • the first connection electrode 452 may be located on the second transparent conductive layer.
  • the first connection electrode 452 may have the same layer structure as the pixel electrode 420 .
  • One end of the first connection electrode 452 can be electrically connected to a first sub-communication line segment 451 through a via hole opened in the third insulating layer 303 and the second insulating layer 302, and the other end can be connected to another first sub-communication line segment through another via hole.
  • Line segments 451 are electrically connected.
  • the front projection of a first connection electrode 452 on the substrate may overlap with the front projection of a touch signal line Tx and a data line on the substrate, or may overlap with a data line and a second communication line on the substrate. There is overlap in the orthographic projection of the bottom.
  • the first connection electrode 452 realizes the electrical connection between two adjacent first sub-communication line segments 451 by crossing two traces extending along the second direction Y on the second conductive layer.
  • the first communication trace is provided on the first transparent conductive layer and is electrically connected through the first connection electrode located on the second transparent conductive layer, thereby realizing signal transmission in the first direction X by the first communication trace.
  • the pixel electrode is located on the second transparent conductive layer, and a second insulating layer and a third insulating layer are provided between the pixel electrode and the near field communication coil, which can effectively reduce the interference between the pixel electrode and the near field communication coil under a heavy load screen. Capacitive coupling effect, thereby improving the adverse effects of near field communication on the display.
  • FIG. 11A is a partial schematic diagram of the circuit structure layer of the display area according to at least one embodiment of the present disclosure.
  • FIG. 11B is a schematic diagram of the circuit structure layer after forming the second conductive layer in FIG. 11A.
  • FIG. 11A is a schematic diagram of a circuit structure layer of a sub-pixel area adjacent to the near field communication area of the display area and the non-near field communication area.
  • the first sub-communication line segment in a sub-pixel area adjacent to the non-near field communication area in the near field communication area may include: a first line segment 451a and a second line segment 451b. .
  • the first line segment 451a and the second line segment 451b may be disconnected.
  • One end of the first line segment 451a may be electrically connected to another first sub-communication line segment in the near field communication area through the first connection electrode 452.
  • the second line segment 451b may be electrically connected to a first dummy communication line in the non-near field communication area through the first connection electrode 452.
  • the arrangement manner of the first dummy communication traces in the non-near field communication area can be substantially the same as the arrangement manner of the first communication traces in the near field communication area, so the details will not be described again.
  • disconnecting the first communication trace from the first dummy communication trace can be achieved by disconnecting part of the first communication trace, which can avoid affecting the display of the non-near field communication area.
  • this embodiment is not limited to this.
  • the first communication trace and the first dummy communication trace may not be electrically connected through the first connection electrode, thereby achieving disconnection between the two.
  • FIG. 12A is another partial schematic diagram of the circuit structure layer of the display area according to at least one embodiment of the present disclosure.
  • FIG. 12B is a schematic diagram of the circuit structure layer after forming the second conductive layer in FIG. 12A.
  • FIG. 12A is a schematic diagram of a circuit structure layer of a sub-pixel area adjacent to the near field communication area of the display area and the non-near field communication area.
  • the second communication trace NL in a sub-pixel area adjacent to the non-near field communication area in the near field communication area communicates with the second dummy line in the non-near field communication area.
  • Trace 460 can be disconnected.
  • the second dummy communication trace 460 may receive the common voltage Vcom.
  • the arrangement manner of the second dummy communication traces in the non-near field communication area can be substantially the same as the arrangement manner of the second communication traces in the near field communication area, so the details will not be described again.
  • the second communication trace is disconnected from the second dummy communication trace, which can avoid affecting the display of the non-near field communication area.
  • the "patterning process” or “patterning process” mentioned in this disclosure includes coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes,
  • For organic materials this includes processes such as coating organic materials, mask exposure, and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • E and F are arranged on the same layer means that E and F are formed at the same time through the same patterning process or the distance between the surfaces of E and F close to the substrate and the substrate is basically the same, or E and F The surface close to the substrate is in direct contact with the same film layer.
  • the "thickness" of a film is the dimension of the film in a plane perpendicular to the substrate.
  • the orthographic projection of E includes the orthographic projection of F means that the boundary of the orthographic projection of E falls within the boundary range of the orthographic projection of F, or that the boundary of the orthographic projection of E is consistent with the orthographic projection of F. The projected boundaries overlap.
  • the preparation process of the display substrate may include the following operations.
  • the substrate may be a transparent substrate, for example, a quartz substrate, a glass substrate, or an organic resin substrate.
  • a transparent substrate for example, a quartz substrate, a glass substrate, or an organic resin substrate.
  • this embodiment is not limited to this.
  • the first conductive layer may include at least: the gate electrode 411 of the transistor T1, and a plurality of first signal lines (such as scan lines).
  • a first insulating film and a semiconductor film are sequentially deposited on the substrate forming the aforementioned structure, and the semiconductor film is patterned through a patterning process to form a first insulating layer and a semiconductor layer disposed on the first insulating layer.
  • the semiconductor layer may include an active layer 410 of the transistor T1.
  • a first transparent conductive film is deposited on the substrate forming the foregoing structure, and the first transparent conductive film is patterned through a patterning process to form a first transparent conductive layer.
  • the first transparent conductive layer may include a plurality of touch electrodes 430 .
  • a second conductive film is deposited on the substrate forming the foregoing structure, and the second conductive film is patterned through a patterning process to form a second conductive layer.
  • the second conductive layer may include: a first pole 412 , a second pole 413 and a third pole 414 of the transistor T1 , a plurality of second signal lines (such as data lines), a touch signal line and a plurality of Second communication wiring.
  • a second insulating film is deposited on the substrate forming the foregoing structure, and subsequently, a third insulating film is coated, a third insulating layer is formed by patterning the third insulating film, and the second insulating film is patterned to form a second insulating layer.
  • the third insulating layer and the second insulating layer may have multiple via holes.
  • the second transparent conductive layer may include: a plurality of pixel electrodes 420 , a plurality of first connection electrodes 452 , and a plurality of second connection electrodes 440 .
  • the circuit structure layer can be prepared. Subsequently, the electronic paper film can be attached to the side of the circuit structure layer away from the substrate by pasting.
  • the first insulating layer 301 and the second insulating layer 302 may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). , can be single layer, multi-layer or composite layer.
  • the third insulating layer 303 may be made of organic materials.
  • the first conductive film and the second conductive film may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or
  • the alloy materials of the above metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can have a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, etc.
  • the first transparent conductive film and the second transparent conductive film may be made of transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, this embodiment is not limited to this.
  • the structure of the display substrate and its preparation process in the embodiments of the present disclosure are merely illustrative. In some exemplary embodiments, the corresponding structure may be changed and the patterning process may be increased or decreased according to actual needs.
  • the display substrate provided in this example can integrate touch and NFC functions into EPD display products by adding a near-field communication coil to the circuit structure layer, thereby enhancing product competitiveness.
  • this embodiment does not require additional film layers and preparation processes, and does not increase the cost of the mask, which is beneficial to reducing costs.
  • the display substrate of this embodiment can be used upside down during use, that is, one side of the substrate faces the user during use, touch operations are performed on one side of the substrate, and the electronic paper film is used for display through the substrate. It will not affect the light transmittance of display products.
  • FIG. 13A is another schematic diagram of the circuit structure layer of the display area according to at least one embodiment of the present disclosure.
  • FIG. 13B is a schematic diagram of the circuit structure layer after forming the second conductive layer in FIG. 13A.
  • Figure 14 is a partial enlarged schematic diagram along the U-U' direction in Figure 13A.
  • Figure 13A illustrates the structure of two adjacent sub-pixel areas within the near field communication area.
  • the orthographic projection of at least one second communication trace NL on the substrate may intersect with the orthographic projection of the first sub-communication line segment 451 of the first communication trace on the substrate.
  • the second communication line NL may directly contact the first sub-communication line segment 451 to achieve electrical connection.
  • One end of the first connection electrode 451 may be electrically connected to the second communication line NL, and the other end may be electrically connected to another first sub-communication line segment 451, thereby achieving electrical connection between adjacent first sub-communication sub-line segments.
  • one end of the first sub-communication line segment 451 may be electrically connected to the first connection electrode 451, and the other end may be directly electrically connected to the second communication line NL.
  • FIG. 15 is another schematic diagram of the circuit structure layer of the display area according to at least one embodiment of the present disclosure.
  • Figure 16 is a partial enlarged schematic diagram along the P-P' direction in Figure 15.
  • Figure 15 illustrates the structure of a sub-pixel area within the near field communication area.
  • the first communication trace ML may be located on the first conductive layer.
  • the second communication trace NL may be located on the second conductive layer.
  • the second communication line NL may be electrically connected to the first communication line ML through a via hole opened in the first insulation layer.
  • Embodiments of the present disclosure also provide a method for preparing a display substrate, which includes: forming a circuit structure layer on a substrate; and disposing an electronic paper film on a side of the circuit structure layer away from the substrate.
  • the circuit structure layer includes: a plurality of first signal lines extending along a first direction, a plurality of second signal lines extending along a second direction, a plurality of driving units, and at least one near field communication coil.
  • the first direction intersects the second direction.
  • a plurality of first signal lines and a plurality of second signal lines intersect to form a plurality of sub-pixel regions.
  • the driving unit is located in the sub-pixel area and is electrically connected to the first signal line and the second signal line.
  • the near field communication coil includes: at least one first communication line extending along the first direction and at least one second communication line extending along the second direction.
  • the at least one first communication line and the at least one second communication line are electrically connect.
  • the driving unit of the circuit structure layer is configured to control the display pattern of the electronic paper film corresponding to the sub-pixel area.
  • forming the circuit structure layer on the substrate may include: sequentially forming a first conductive layer, a first insulating layer, a semiconductor layer, a first transparent conductive layer, a second conductive layer, and a third conductive layer on the substrate. two insulating layers, a third insulating layer and a second transparent conductive layer.
  • the first conductive layer at least includes: the plurality of first signal lines and the gates of the transistors of the driving unit; the semiconductor layer at least includes: the active layer of the transistors of the driving unit; the first The transparent conductive layer at least includes: a plurality of touch electrodes; the second conductive layer at least includes: the plurality of second signal lines, the at least one second communication line and a plurality of touch signal lines, the driving The first pole and the second pole of the transistor of the unit; the second transparent conductive layer at least includes: a plurality of pixel electrodes.
  • the transistor of the driving unit and the first signal line are of an integral structure
  • the first electrode of the transistor of the driving unit and the second signal line are of an integral structure
  • the second electrode of the transistor is electrically connected to the pixel electrode.
  • An embodiment of the present disclosure also provides a display device, including the display substrate as described above.
  • FIG. 17 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • this embodiment provides a display device 900, including a display substrate 910.
  • the display substrate 910 may be the display substrate provided in the previous embodiment.
  • display substrate 910 may be an EPD panel.
  • the display device 900 may be: an EPD display device, an electronic label, or any other product or component with a display function. However, this embodiment is not limited to this.

Abstract

一种显示基板，包括：衬底(300)、依次设置在衬底(300)上的电路结构层(400)和电子纸膜(500)。电路结构层(400)包括：沿第一方向(X)延伸的多条第一信号线(21)、沿第二方向(Y)延伸的多条第二信号线(22)、多个驱动单元、以及至少一个近场通信线圈。多条第一信号线(21)和多条第二信号线(22)交叉形成多个子像素区域。驱动单元位于子像素区域，并与第一信号线(21)和第二信号线(22)电连接，配置为控制子像素区域对应的电子纸膜的显示图案。近场通信线圈包括：沿第一方向(X)延伸的至少一条第一通信走线(ML)以及沿第二方向(Y)延伸的至少一条第二通信走线(NL)。第一通信走线(ML)和第二通信走线(NL)电连接。

Description

显示基板及显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及显示装置。
背景技术
电泳电子纸(EPD，Electrophoretic Display)是一种类纸显示器，其工作原理是依靠黑色颗粒与白色颗粒在电压的作用下发生电泳，进而形成黑白色彩。由于其本身的反射式、双稳态显示原理，具有护眼、节能等特点，已逐渐从价签市场进入教育、医疗及交通等领域，具有潜在的应用价值。然而，传统的电泳电子纸产品交互能力较差。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板及显示装置。
一方面，本公开实施例提供一种显示基板，包括：衬底、以及依次设置在衬底上的电路结构层和电子纸膜。电路结构层包括：沿第一方向延伸的多条第一信号线、沿第二方向延伸的多条第二信号线、多个驱动单元以及至少一个近场通信线圈。第一方向与第二方向交叉。多条第一信号线和多条第二信号线可以交叉形成多个子像素区域。驱动单元位于子像素区域，并与第一信号线和第二信号线电连接。驱动单元配置为控制子像素区域对应的电子纸膜的显示图案。近场通信线圈可以包括：沿第一方向延伸的至少一条第一通信走线以及沿第二方向延伸的至少一条第二通信走线。至少一条第一通信走线和至少一条第二通信走线电连接。
在一些示例性实施方式中，至少一条第一信号线在所述第二方向上与所述第一通信走线相邻，至少一条第二信号线在所述第一方向上与所述第二通信走线相邻。
在一些示例性实施方式中，在所述第二方向上相邻两条第一通信走线之间间隔至少一个子像素区域，在所述第一方向上相邻两条第二通信走线之间间隔至少一个子像素区域。
在一些示例性实施方式中，所述至少一条第一通信走线位于所述至少一条第二通信走线靠近所述衬底的一侧；所述多条第一信号线位于所述多条第二信号线靠近所述衬底的一侧。
在一些示例性实施方式中，所述至少一条第二通信走线与所述多条第二信号线为同层结构。
在一些示例性实施方式中，所述至少一条第一通信走线与所述多条第一信号线为同层结构。
在一些示例性实施方式中，所述至少一条第一通信走线位于所述多条第一信号线远离所述衬底的一侧。
在一些示例性实施方式中，所述至少一条第一通信走线包括：沿所述第一方向延伸且依次排布的多个第一子通信线段，相邻两个第一子通信线段通过第一连接电极电连接，所述第一连接电极位于所述第一子通信线段远离所述衬底的一侧。
在一些示例性实施方式中，所述衬底包括：至少一个近场通信区域和至少一个非近场通信区域；所述至少一个近场通信线圈位于所述至少一个近场通信区域内，所述至少一个非近场通信区域设置有沿所述第一方向延伸的至少一条第一虚拟通信走线和沿所述第二方向延伸的至少一条第二虚设线圈；所述第一通信走线与所述第一虚拟通信走线断开，所述第二通信走线与所述第二虚设通信走线断开。
在一些示例性实施方式中，所述电路结构层还包括：多条触控信号线和多个触控电极；所述多条触控信号线沿所述第二方向延伸，至少一条触控信号线与彼此电连接且间隔开的多个触控电极电连接。
在一些示例性实施方式中，所述至少一条第二通信走线间隔排布在所述多条触控信号线之间，相邻的所述第二通信走线与所述触控信号线之间间隔至少一个子像素区域。
在一些示例性实施方式中，所述驱动单元至少包括：晶体管和像素电极；所述像素电极位于所述子像素区域内；所述晶体管的栅极与所述第一信号线电连接，所述晶体管的第一极与所述第二信号线电连接，所述晶体管的第二极与所述像素电极电连接。
在一些示例性实施方式中，在垂直于所述显示基板的方向上，所述电路结构层包括：依次设置在所述衬底上的第一导电层、半导体层、第一透明导电层、第二导电层和第二透明导电层。所述第一导电层至少包括：所述多条第一信号线、所述驱动单元的晶体管的栅极。所述半导体层至少包括：所述驱动单元的晶体管的有源层。所述第一透明导电层至少包括：所述多个触控电极。所述第二导电层至少包括：所述多条第二信号线、所述至少一条第二通信走线和所述多条触控信号线。所述第二透明导电层至少包括：所述像素电极。
在一些示例性实施方式中，所述至少一条第一通信走线位于所述第一导电层或所述第一透明导电层。
在一些示例性实施方式中，所述第二导电层与所述透明导电层之间设置有无机绝缘层和有机绝缘层，所述有机绝缘层位于所述无机绝缘层远离所述衬底的一侧。
在一些示例性实施方式中，所述电子纸膜被配置为利用所述衬底一侧入射的光线进行显示。
另一方面，本公开实施例提供一种显示装置，包括如上所述的显示基板。
另一方面，本公开实施例提供一种显示基板的制备方法，包括：在衬底上形成电路结构层，所述电路结构层包括：沿第一方向延伸的多条第一信号线、沿第二方向延伸的多条第二信号线、多个驱动单元、以及至少一个近场通信线圈；所述第一方向与所述第二方向交叉；所述多条第一信号线和多条第二信号线交叉形成多个子像素区域；所述驱动单元位于所述子像素区域，并与所述第一信号线和第二信号线电连接；所述近场通信线圈包括：沿所述第一方向延伸的至少一条第一通信走线以及沿所述第二方向延伸的至少一条第二通信走线，所述至少一条第一通信走线和所述至少一条第二通信走线电连接；在所述电路结构层远离所述衬底一侧设置电子纸膜；所述电路结构层 的驱动单元配置为控制所述子像素区域对应的电子纸膜的显示图案。
在一些示例性实施方式中，所述在衬底上形成电路结构层，包括：在所述衬底上依次形成第一导电层、第一绝缘层、半导体层、第一透明导电层、第二导电层、第二绝缘层、第三绝缘层和第二透明导电层。所述第一导电层至少包括：所述多条第一信号线、所述驱动单元的晶体管的栅极；所述半导体层至少包括：所述驱动单元的晶体管的有源层；所述第一透明导电层至少包括：多个触控电极；所述第二导电层至少包括：所述多条第二信号线、所述至少一条第二通信走线和多条触控信号线、所述驱动单元的晶体管的第一极和第二极；所述第二透明导电层至少包括：多个像素电极。
在一些示例性实施方式中，所述驱动单元的晶体管与所述第一信号线为一体结构，所述驱动单元的晶体管的第一极与第二信号线为一体结构，所述晶体管的第二极与像素电极电连接。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例的显示基板的示意图；
图2为本公开至少一实施例的显示基板的局部剖面示意图；
图3为本公开至少一实施例的显示基板的显示区域的示意图；
图4为本公开至少一实施例的近场通信区域的电路结构层的局部示意图；
图5为图4中形成第二导电层后的电路结构层的示意图；
图6为本公开至少一实施例的显示区域的电路结构层的局部示意图；
图7为图6中沿Q-Q’方向的局部剖面示意图；
图8A为图6中形成第一导电层后的电路结构层的局部示意图；
图8B为图6中形成半导体层后的电路结构层的局部示意图；
图8C为图6中形成第一透明导电层后的电路结构层的局部示意图；
图8D为图6中形成第二导电层后的电路结构层的局部示意图；
图8E为图6中形成第三绝缘层后的电路结构层的局部示意图；
图9A为本公开至少一实施例的显示区域的电路结构层的局部示意图；
图9B为图9A中形成第二导电层后的电路结构层的示意图；
图10为图9A中沿R-R’方向的局部剖面示意图；
图11A为本公开至少一实施例的显示区域的电路结构层的局部示意图；
图11B为图11A中形成第二导电层后的电路结构层的示意图；
图12A为本公开至少一实施例的显示区域的电路结构层的另一局部示意图；
图12B为图12A中形成第二导电层后的电路结构层的示意图；
图13A为本公开至少一实施例的显示区域的电路结构层的另一示意图；
图13B为图13A中形成第二导电层后的电路结构层的示意图；
图14为图13A中沿U-U’方向的局部放大示意图；
图15为本公开至少一实施例的显示区域的电路结构层的另一示意图；
图16为图15中沿P-P’方向的局部放大示意图；
图17为本公开至少一实施例的显示装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为一种或多种形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本公开中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个或两个以上的数量。
在本公开中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本公开中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏极)与源电极(源电极端子、源区域或源极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本公开中，沟道区域是指电流主要流过的区域。
在本公开中，为区分晶体管除栅电极之外的两极，将其中一个电极称为第一极，另一电极称为第二极，第一极可以为源电极或者漏电极，第二极可以为漏电极或源电极，另外，将晶体管的栅电极称为控制极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本公开中，“源电极”和“漏电极”可以互相调换。
在本公开中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有一种或多种功能的元件等。
在本公开中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，可以包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，可以包括85°以上且95°以下的角度的状态。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。
近场通信(NFC，Near Field Communication)技术，又称为近距离无线通信，是一种新兴的通信技术，该通信技术结合了非接触式感应技术和无线连接技术，可以在近距离内实现数据的传输交换，并具有传输安全性高、反应迅速等优点，正在被逐渐应用于移动支付、身份识别、防伪、门禁等方面。
本实施例提供一种显示基板，可以集成NFC功能，从而提高显示产品的交互能力。
本实施例提供一种显示基板，包括：衬底、以及依次设置在衬底上的电路结构层和电子纸膜。电路结构层包括：沿第一方向延伸的多条第一信号线、沿第二方向延伸的多条第二信号线、多个驱动单元以及至少一个近场通信线圈。第一方向与第二方向交叉，例如第一方向可以垂直于第二方向。多条第一信号线和多条第二信号线可以交叉形成多个子像素区域。驱动单元可以位于子像素区域，并与第一信号线和第二信号线电连接。驱动单元配置为控制子像素区域对应的电子纸膜的显示图案。近场通信线圈可以包括：沿第一方向延伸的至少一条第一通信走线以及沿第二方向延伸的至少一条第二通信走线。至少一条第一通信走线和至少一条第二通信走线电连接。
本实施例提供的显示基板中，第一通信走线和第二通信走线可以排布为网状结构，并电连接，从而形成网状结构的近场通信线圈，以支持实现在显示基板内部集成NFC功能。
在一些示例性实施方式中，至少一条第一信号线在第二方向上与一条第一通信走线相邻，至少一条第二信号线在第一方向上与一条第二通信走线相邻。在本示例中，在第二方向上，相邻的第一信号线与第一通信走线之间没有设置其他器件或走线；在第一方向上，相邻的第二信号线与第二通信走线之间没有设置其他器件或走线。本示例中，通过设置第一通信走线与第一信号线相邻，第二通信走线与第二信号线相邻，可以实现在显示区域合理排布近场通信线圈。
在一些示例性实施方式中，在第二方向上相邻两条第一通信走线之间可以间隔至少一个子像素区域，在第一方向上相邻两条第二通信走线之间可以间隔至少一个子像素区域。在一些示例中，在第一方向上至少两列相邻子像素区域之间可以排布一条第二通信走线，在第二方向上至少两行相邻子像素区域之间可以排布一条第一通信走线。
在一些示例性实施方式中，至少一条第一通信走线可以位于至少一条第二通信走线靠近衬底的一侧。多条第一信号线可以位于多条第二信号线靠近衬底的一侧。例如，至少一条第二通信走线与多条第二信号线可以为同层结构。在一些示例中，至少一条第一通信走线与多条第一信号线可以为同层结构，或者，至少一条第一通信走线可以位于多条第一信号线远离衬底的一侧。然而，本实施例对此并不限定。
在一些示例性实施方式中，电路结构层还可以包括：多条触控信号线和多个触控电极。多条触控信号线可以沿第二方向延伸，至少一条触控信号线可以与彼此电连接且间隔开的多个触控电极电连接。多条触控电极电连接可以形成一个触控感测区域。本示例的显示基板可以集成NFC功能和触控功能，从而提高显示产品的交互能力。
在一些示例性实施方式中，至少一条第二通信走线可以间隔排布在多条触控信号线之间，相邻的第二通信走线与触控信号线之间可以间隔至少一个子像素区域。
下面通过一些示例对本实施例的方案进行举例说明。
图1为本公开至少一实施例的显示基板的示意图。在一些示例中，如图1所示，显示基板可以包括：显示区域AA和位于显示区域AA四周的周边 区域BB。显示区域AA可以设置有沿第一方向X延伸的多条第一信号线21以及沿第二方向Y延伸的多条第二信号线22。第一方向X与第二方向Y交叉，例如，第一方向X可以垂直于第二方向Y。多条第一信号线21可以沿第二方向Y依次排布，多条第二信号线22可以沿第一方向X依次排布。多条第一信号线21和多条第二信号线22可以交叉形成多个子像素区域。在一些示例中，多条第一信号线21可以包括多条扫描线，多条第二信号线22可以包括多条数据线。
在一些示例中，如图1所示，周边区域BB可以包括：位于显示区域AA上侧的上边框、位于显示区域AA下侧的下边框、位于显示区域AA左侧的左边框和位于显示区域AA右侧的右边框。上边框可以与左边框和右边框连通，下边框可以与左边框和右边框连通。周边区域BB可以设置有多条第一引出线23以及多条第二引出线24。多条第一引出线23可以位于左边框和右边框，多条第二引出线24可以位于下边框。第一信号线21的一端可以与左边框的第一引出线23电连接，另一端可以与右边框的第一引出线23电连接，以便通过第一引出线23接收信号。第一引出线23可以从左边框或右边框延伸至下边框。第二引出线24可以与第二信号线22向下边框延伸的一端电连接，以便给第二信号线22提供信号。
在一些示例中，如图1所示，下边框可以包括：第一电路区101和第一绑定区域102。第一绑定区域102可以位于第一电路区101远离显示区域AA的一侧。第一电路区101可以设置显示控制电路。第一引出线23和第二引出线24可以延伸至第一电路区101，并与显示控制电路电连接。第一绑定区域102可以设置多个第一绑定引脚，多个第一绑定引脚可以与提供显示控制的柔性线路板(FPC)绑定连接。
在一些示例中，显示区域AA还可以包括多个驱动单元，多个驱动单元可以呈阵列分布。例如，每个驱动单元可以位于一个子像素区域。每个驱动单元可以与对应子像素区域的电子纸膜接触，能够控制对应子像素区域内的电子纸膜的显示图案。每个驱动单元可以至少包括：一个晶体管和像素电极。晶体管的栅极可以与第一信号线电连接，第一极可以与第二信号线电连接，第二极可以与像素电极电连接。例如，第一信号线可以提供扫描信号，第二 信号线可以提供数据信号。每个晶体管可以起到开关作用，以便当将信号供应给第一信号线(例如，扫描线)和第二信号线(例如，数据线)时，晶体管可以处于接通状态下，当晶体管处于接通状态下时可以将电压施加于像素电极。
在一些示例中，如图1所示，显示区域AA还可以包括：阵列排布的多个触控电极(作为自电容电极)、以及与触控电极电连接的触控信号线25。触控电极在衬底的正投影与像素电极在衬底的正投影可以存在交叠。多条触控信号线25可以沿第一方向X依次排布，并沿第二方向Y延伸。周边区域BB还可以设置多条触控引出线26。多条触控引出线26可以位于上边框。
在一些示例中，如图1所示，上边框可以包括：第二电路区103和第二绑定区域104。第二绑定区域104可以位于第二电路区103远离显示区域AA的一侧。第二电路区103可以设置触控控制电路。触控引出线26可以延伸至第二电路区103，并与触控控制电路电连接。第二绑定区域104可以设置多个第二绑定引脚，多个第二绑定引脚可以与提供触控控制的柔性线路板绑定连接。触控电极可以通过触控信号线25和触控引出线26与触控控制电路电连接。在进行触控时，触摸物(例如，人的手指)触碰显示装置，位于触摸点处的触控电极的电容会发生变化，触控控制电路通过检测触控电极的自电容变化情况来确定触摸位置。然而，本实施例对此并不限定。在另一些示例中，显示控制电路和触控控制电路可以集成为一个显示触控控制电路，所述显示触控控制电路可以设置在下边框或上边框。
本实施例的显示基板可以采用自电容式触控技术。在触控阶段，利用触控信号线传输触控电极检测到的触控信号，以实现触控功能。在一些示例中，多个触控电极可以电连接形成一个触控感测区域，例如一个触控感测区域可以包括几十乘以几十个子像素区域的触控电极。比如，一个触控感测区域的长度可以约为4毫米(mm)，可以包括位于25至40个子像素区域的触控电极。每个触控感测区域内的多个触控电极可以与一条触控信号线电连接。在一些示例中，触控电极还可以复用为公共电极，在显示阶段，可以通过触控信号线给公共电极提供公共电压，以实现显示功能。
图2为本公开至少一实施例的显示基板的局部剖面示意图。在一些示例 中，如图2所示，在垂直于显示基板的方向上，显示基板可以包括：衬底300、以及依次设置在衬底300上的电路结构层400和电子纸膜500。电子纸膜500可以通过粘贴层设置在电路结构层400远离衬底300的一侧。
在一些示例中，如图2所示，电子纸膜500可以包括：墨水层501、控制电极502和保护膜503。墨水层501可以通过颗粒根据所施加的电场进行的运动(即，电泳现象)表现彩色或黑白图案，并通过入射在图案上的外部光的反射或吸收显示图案。例如，墨水层501包括多个微囊(microcapsule)，微囊为包含白色颗粒和黑色颗粒的透明流体。通过将电场施加于多个微囊来表现黑色或白色图案。例如，使白色颗粒带(+)电，使黑色颗粒带(-)电，以便通过施加电场使它们沿着相反方向运动。墨水层的图像图案可以一直保持到电场变化点。在另一些示例中，可以通过将滤色片堆叠在墨水层上，或采用彩色颗粒取代黑白颗粒，可以实现彩色显示。电子纸膜500的控制电极502可以作为公共电极，提供公共电压Vcom。例如，控制电极502可以保持恒定电极，并可以与地连接。控制电极502和电路结构层的像素电极之间产生的电场，可以推动带电粒子的移动。在一些示例中，控制电极502可以与电路结构层的公共电极电连接。
在一些示例中，电子纸膜500可以被配置为利用衬底300一侧入射的光线进行显示。在本示例中，显示基板可以采用倒置使用方式。在使用过程中，将衬底面向使用者，电子纸膜500利用靠近衬底300一侧进行显示，以便使用者可以透过衬底300观察到电子纸膜500的显示图案。
在一些示例中，显示基板可以在显示区域设置近场通信线圈，以集成NFC功能。例如，当发起连接的终端设备的近场通信线圈中通过变化的电流时会产生磁场，该磁场与待连接的目标终端设备的感应磁场发生电磁耦合，两台设备即配对连接成功，可以进行数据交换。在一些示例中，设置在第二电路区103的触控控制电路可以集成NFC控制电路，显示区域的近场通信线圈可以通过位于上边框的引出线与第二电路区103的触控控制电路电连接。然而，本实施例对此并不限定。例如，NFC控制电路可以与显示控制电路集成，或者，NFC控制电路、显示控制电路和触控控制电路可以集成设置在上边框或下边框。
图3为本公开至少一实施例的显示区域的示意图。在一些示例中，如图3所示，显示区域AA可以包括：两个近场通信区域(例如第一近场通信区域A11和第二近场通信区域A12)以及三个非近场通信区域(例如，第一非近场通信区域A21、第二非近场通信区域A22和第三非近场通信区域A23)。第一近场通信区域A11和第二近场通信区域A12在衬底的正投影可以为U字形，第二近场通信区域A12可以位于第一近场通信区域A11的内侧。第一非近场通信区域A21可以位于第一近场通信区域A12的内侧，第二非近场通信区域A22可以位于第一近场通信区域A11和第二近场通信区域A12之间，第三非近场通信区域A23可以位于第一近场通信区域A11远离第二近场通信区域A12的一侧。然而，本实施例对此并不限定。在本示例中，通过设置多个近场通信区域，可以有利于提高通信质量。
图4为本公开至少一实施例的近场通信区域的局部示意图。图5为图4中形成第二导电层后的电路结构层的示意图。图4所示为显示区域的一个近场通信区域内按照4×4排布的子像素区域。在一些示例中，如图4所示，近场通信区域可以包括：沿第一方向X延伸的多条第一通信走线(例如，第一通信走线ML(j)和ML(j+1))、沿第二方向Y延伸的多条第二通信走线(例如，第二通信走线NL(i)至NL(i+2))、沿第一方向X延伸的多条第一信号线(例如包括扫描线GL(m-1)至GL(m+3))、沿第二方向Y延伸的多条第二信号线(例如包括数据线DL(n-1)至DL(n+2))、以及沿第二方向Y延伸的触控信号线Tx。其中，i、j、m和n可以均为正整数。
在一些示例中，如图4所示，多条扫描线和多条数据线交叉形成多个子像素区域。至少一条扫描线在第二方向Y可以与第一通信走线相邻。例如，扫描线GL(m-1)可以与第一通信走线ML(j)相邻，扫描线GL(m+3)可以与第一通信走线ML(j+1)相邻。相邻两条第一通信走线(例如ML(j)与ML(j+1))之间可以间隔四行子像素区域。然而，本实施例对此并不限定。例如，相邻两条第一通信走线之间可以间隔一行子像素区域。
在一些示例中，如图4所示，至少一条数据线在第一方向X可以与第二通信走线或触控信号线相邻。例如，数据线DL(n)可以与第二通信走线NL(i)相邻，数据线DL(n+1)可以与触控信号线Tx相邻，数据线DL(n+2)可以与第 二通信走线NL(i+1)相邻。例如，触控信号线Tx可以与4×4个触控电极430电连接。如图4和图5所示，4×4个触控电极430中沿第二方向Y相邻的触控电极430可以为一体结构，沿第一方向X相邻的触控电极430可以通过第二连接电极440电连接。与第四行第二列的触控电极430和第四行第三列的触控电极430电连接的第二连接电极440可以同时与触控信号线Tx电连接，从而实现触控信号线Tx与多个触控电极430的电连接。
在一些示例中，如图4和图5所示，相邻的第二通信走线与触控信号线Tx之间至少间隔一列子像素区域。例如，第二通信走线NL(i)和NL(j+1)在第一方向X上位于触控信号线Tx的两侧，并与触控信号线Tx之间均间隔一列子像素区域。然而，本实施例对此并不限定。
在一些示例中，如图4和图5所示，相邻两列子像素区域之间可以设置一条数据线和一条触控信号线，或者可以设置一条数据线和一条第二通信走线。相邻两行子像素区域之间可以设置一条扫描线，或者可以设置一条扫描线和一条第一通信走线。本实施例的走线排布可以节省空间，而且可以避免走线聚集，产生信号干扰。
在一些示例中，如图4所示，以第一通信走线ML(j)为例，第一通信走线ML(j)可以包括沿第一方向X依次排布的多个第一子通信线段451，相邻第一子通信线段451之间可以通过第一连接电极452电连接。第一通信走线ML(j+1)可以通过一个第一连接电极452与第二通信走线NL(i+2)电连接，从而实现第一通信走线和第二通信走线的网状连接。本示例的近场通信线圈可以为网状结构。
图6为本公开至少一实施例的显示区域的电路结构层的局部示意图。图6所示可以为图4中第二行第二列和第二行第三列的两个子像素区域的示意图。图7为图6中沿Q-Q’方向的局部剖面示意图。
在一些示例中，如图6和图7所示，在垂直于显示基板的方向上，显示区域的电路结构层可以包括：依次设置在衬底300上的第一导电层41、半导体层40、第一透明导电层42、第二导电层43和第二透明导电层44。第一导电层41和半导体层40之间可以设置第一绝缘层301，第二导电层43和第二透明导电层44之间可以设置第二绝缘层302和第三绝缘层303。例如，第一 绝缘层301和第二绝缘层302可以为无机绝缘层，第三绝缘层303可以为有机绝缘层。然而，本实施例对此并不限定。
图8A为图6中形成第一导电层后的电路结构层的局部示意图。在一些示例中，如图6至图8A所示，第一导电层41可以包括：驱动单元的晶体管T1的栅极411、以及沿第一方向X延伸的多条第一信号线(例如包括扫描线GL(m)和GL(m+1))。第一信号线与同一行连接的多个晶体管T1的栅极411可以为一体结构。
图8B为图6中形成半导体层后的电路结构层的局部示意图。在一些示例中，如图6至图8B所示，半导体层40可以包括：晶体管T1的有源层410。晶体管T1的有源层410在衬底的正投影(例如，可以为矩形)可以与栅极411在衬底的正投影存在交叠。
图8C为图6中形成第一透明导电层后的电路结构层的局部示意图。在一些示例中，如图6至图8C所示，第一透明导电层42可以包括：多个触控电极430。子像素区域内的触控电极430在衬底的正投影可以为T字型。沿第二方向Y相邻的多个触控电极430可以为一体结构。
图8D为图6中形成第二导电层后的电路结构层的局部示意图。在一些示例中，如图6至图8D所示，第二导电层43可以包括：晶体管T1的第一极412、第二极413和第三极414、多条第二信号线(例如，数据线DL(n)至DL(n+2))、触控信号线Tx以及多条第二通信走线(例如NL(i)和NL(i+1))。晶体管T1的第一极411、第二极413和第三极414在衬底的正投影均与有源层410在衬底的正投影存在交叠。晶体管T1的第一极412、第二极413和第三极414均与有源层410直接接触。晶体管T1的第一极412与电连接的一条数据线(例如数据线DL(n))可以为一体结构，晶体管T1的第二极413可以在后续与像素电极420电连接，晶体管T1的第三极414在衬底的正投影可以在第二方向Y上位于第一极412和第二极413的相同侧。通过设置第三极414，当晶体管T1在栅极411控制下导通时，有利于第一极412和第二极413之间的导通。
图8E为图6中形成第三绝缘层后的电路结构层的局部示意图。在一些示例中，如图6至图8E所示，第三绝缘层303可以开设有多个过孔，例如 可以包括第一过孔V1至第三过孔V3。第一过孔V1内的第三绝缘层303和第二绝缘层302可以被去掉，暴露出晶体管T1的第二极413的表面。第二过孔V2和第三过孔V3内的第三绝缘层303和第二绝缘层302可以被去掉，暴露出触控电极430的表面。第二过孔V2和第三过孔V3在衬底的正投影可以位于触控电极430沿第一方向X的两个端部。
在一些示例中，如图6至图8E所示，第二透明导电层44可以包括：多个像素电极420、以及多个第二连接电极440。像素电极420可以位于子像素区域内。像素电极420可以通过第一过孔V1与一个晶体管T1的第二极413电连接。第二连接电极440可以沿第一方向X延伸。第二连接电极440的一端可以通过第二过孔V2与一个子像素区域内的触控电极430电连接，还可以与另一个子像素区域内的触控电极430电连接，从而实现沿第一方向X排布的两个相邻触控电极430之间的电连接。一个第二连接电极440在衬底的正投影可以与触控信号线Tx和一条数据线在衬底的正投影存在交叠，或者，可以与一条数据线和一条第二通信走线在衬底的正投影存在交叠。
图9A为本公开至少一实施例的显示区域的电路结构层的局部示意图。图9A所示为图4中第一行第二列和第一行第三列的两个子像素区域的示意图。图9B为图9A中形成第二导电层后的电路结构层的示意图。图10为图9A中沿R-R’方向的局部剖面示意图。
在一些示例中，如图9A和图9B所示，以第一通信走线ML(j)为例，第一通信走线ML(j)可以包括：沿第一方向X依次排布的多个第一子通信线段451。一个第一子通信线段451可以位于一个子像素区域内。相邻第一子通信线段451可以通过第一连接电极452电连接。第一子通信线段451可以为条形走线，在一个子像素区域内可以位于触控电极430在第二方向Y上的一侧。如图10所示，第一子通信线段451可以位于第一透明导电层。第一子通信线段451可以与触控电极430为同层结构。
在一些示例中，如图9A至图10所示，第一连接电极452可以位于第二透明导电层。第一连接电极452可以与像素电极420为同层结构。第一连接电极452的一端可以通过第三绝缘层303和第二绝缘层302开设的过孔与一个第一子通信线段451电连接，另一端可以通过另一个过孔与另一个第一子 通信线段451电连接。一个第一连接电极452在衬底的正投影可以与一条触控信号线Tx和一条数据线在衬底的正投影存在交叠，或者，可以与一条数据线和一条第二通信走线在衬底的正投影存在交叠。第一连接电极452通过横跨位于第二导电层的两条沿第二方向Y延伸的走线，实现相邻两个第一子通信线段451的电连接。
本示例通过在第一透明导电层设置第一通信走线，并通过位于第二透明导电层的第一连接电极电连接，实现第一通信走线在第一方向X上的信号传输。本示例的像素电极位于第二透明导电层，像素电极与近场通信线圈之间设置有第二绝缘层和第三绝缘层，可以有效降低重载画面下像素电极与近场通信线圈之间的电容耦合作用，从而改善近场通信对显示的不良影响。
图11A为本公开至少一实施例的显示区域的电路结构层的局部示意图。图11B为图11A中形成第二导电层后的电路结构层的示意图。图11A所示为显示区域的近场通信区域邻近非近场通信区域的一个子像素区域的电路结构层的示意图。
在一些示例中，如图11A和图11B所示，近场通信区域内邻近非近场通信区域的一个子像素区域内的第一子通信线段可以包括：第一线段451a和第二线段451b。第一线段451a和第二线段451b可以断开。第一线段451a的一端可以通过第一连接电极452与近场通信区域内的另一个第一子通信线段电连接。第二线段451b可以通过第一连接电极452与非近场通信区域内的一个第一虚设通信走线电连接。非近场通信区域内的第一虚设通信走线的设置方式与近场通信区域内的第一通信走线的设置方式可以大致相同，故于此不再赘述。在本示例中，第一通信走线与第一虚设通信走线断开，可以通过断开第一通信走线的部分来实现，可以避免对非近场通信区域的显示产生影响。然而，本实施例对此并不限定。在另一些示例中，第一通信走线和第一虚设通信走线可以不通过第一连接电极电连接，从而实现两者的断开。
图12A为本公开至少一实施例的显示区域的电路结构层的另一局部示意图。图12B为图12A中形成第二导电层后的电路结构层的示意图。图12A所示为显示区域的近场通信区域邻近非近场通信区域的一个子像素区域的电路结构层的示意图。
在一些示例中，如图12A和图12B所示，近场通信区域内邻近非近场通信区域的一个子像素区域内的第二通信走线NL与非近场通信区域内的第二虚设通信走线460可以断开。第二虚设通信走线460可以接收公共电压Vcom。非近场通信区域内的第二虚设通信走线的设置方式与近场通信区域内的第二通信走线的设置方式可以大致相同，故于此不再赘述。在本示例中，第二通信走线与第二虚设通信走线断开，可以避免对非近场通信区域的显示产生影响。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“构图工艺”或“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。
本公开所说的“E和F同层设置”是指，E和F通过同一次图案化工艺同时形成或者E和F靠近衬底一侧的表面与衬底的距离基本相同，或者E和F靠近衬底一侧的表面与同一个膜层直接接触。膜层的“厚度”为膜层在垂直于衬底所在平面上的尺寸。本公开示例性实施例中，“E的正投影包含F的正投影”，是指E的正投影的边界落入F的正投影的边界范围内，或者E的正投影的边界与F的正投影的边界重叠。
在一些示例性实施方式中，显示基板的制备过程可以包括如下操作。
(1)、提供衬底。在一些示例中，衬底可以为透明基底，例如，可以为石英基底、玻璃基底或有机树脂基底。然而，本实施例对此并不限定。
(2)、形成第一导电层。在一些示例中，在衬底上沉积第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成第一导电层。如图8A所 示，第一导电层可以至少包括：晶体管T1的栅极411、以及多条第一信号线(例如扫描线)。
(3)、形成半导体层。在一些示例中，在形成前述结构的衬底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成第一绝缘层以及设置在第一绝缘层上的半导体层。如图8B所示，半导体层可以包括：晶体管T1的有源层410。
(4)、形成第一透明导电层。在一些示例中，在形成前述结构的衬底上沉积第一透明导电薄膜，通过图案化工艺对第一透明导电薄膜进行图案化，形成第一透明导电层。如图8C所示，第一透明导电层可以包括：多个触控电极430。
(5)、形成第二导电层。在一些示例中，在形成前述结构的衬底上沉积第二导电薄膜，通过图案化工艺对第二导电薄膜进行图案化，形成第二导电层。如图8D所示，第二导电层可以包括：晶体管T1的第一极412、第二极413和第三极414、多条第二信号线(例如数据线)、触控信号线以及多条第二通信走线。
(6)、形成第二绝缘层和第三绝缘层。在一些示例中，在形成前述结构的衬底上沉积第二绝缘薄膜，随后，涂覆第三绝缘薄膜，通过对第三绝缘薄膜进行图案化形成第三绝缘层，对第二绝缘薄膜进行图案化形成第二绝缘层。在一些示例中，如图8E所示，第三绝缘层和第二绝缘层可以开设多个过孔。
(7)、形成第二透明导电层。在一些示例中，在形成前述结构的衬底上沉积第二透明导电薄膜，通过图案化工艺对第二透明导电薄膜进行图案化，形成第二透明导电层。在一些示例中，如图6、图9A、图11A和图12A所示，第二透明导电层可以包括：多个像素电极420、多个第一连接电极452、多个第二连接电极440。
至此，可以制备得到电路结构层。随后，可以通过粘贴方式将电子纸膜贴附在电路结构层远离衬底的一侧。
在一些示例性实施方式中，第一绝缘层301和第二绝缘层302可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第三绝缘层303可以采用有机材料。 第一导电薄膜和第二导电薄膜可以采用金属材料，例如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。第一透明导电薄膜和第二透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)等透明导电材料。然而，本实施例对此并不限定。
本公开实施例的显示基板的结构及其制备过程仅仅是一种示例性说明。在一些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。
本示例提供的显示基板，通过在电路结构层增设近场通信线圈，可以实现在EPD显示产品集成触控功能和NFC功能，从而增强产品竞争力。而且，本实施例无需增加膜层和制备工艺，没有掩模版的成本增加，有利于降低成本。另外，本实施例的显示基板在使用时可以倒置使用，即，使用时将衬底一侧朝向使用者，在衬底一侧进行触控操作，并透过衬底利用电子纸膜进行显示，不会对显示产品的透光率产生影响。
图13A为本公开至少一实施例的显示区域的电路结构层的另一示意图。图13B为图13A中形成第二导电层后的电路结构层的示意图。图14为图13A中沿U-U’方向的局部放大示意图。图13A示意了近场通信区域内的两个相邻子像素区域的结构。
在一些示例中，如图13A至图14所示，至少一条第二通信走线NL在衬底的正投影可以与第一通信走线的第一子通信线段451在衬底的正投影存在交叠。第二通信走线NL可以与第一子通信线段451直接接触以实现电连接。第一连接电极451的一端可以电连接第二通信走线NL，另一端可以电连接另一个第一子通信线段451，从而实现相邻第一子通信子线段的电连接。在本示例中，第一子通信线段451的一端可以与第一连接电极451电连接，另一端可以直接与第二通信走线NL电连接。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图15为本公开至少一实施例的显示区域的电路结构层的另一示意图。图16为图15中沿P-P’方向的局部放大示意图。图15示意了近场通信区域内的 一个子像素区域的结构。
在一些示例中，如图15和图16所示，第一通信走线ML可以位于第一导电层。第二通信走线NL可以位于第二导电层。第二通信走线NL可以通过第一绝缘层开设的过孔与第一通信走线ML电连接。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
本公开实施例还提供一种显示基板的制备方法，包括：在衬底上形成电路结构层；在电路结构层远离衬底一侧设置电子纸膜。电路结构层包括：沿第一方向延伸的多条第一信号线、沿第二方向延伸的多条第二信号线、多个驱动单元、以及至少一个近场通信线圈。第一方向与第二方向交叉。多条第一信号线和多条第二信号线交叉形成多个子像素区域。驱动单元位于所述子像素区域，并与第一信号线和第二信号线电连接。近场通信线圈包括：沿第一方向延伸的至少一条第一通信走线以及沿第二方向延伸的至少一条第二通信走线，至少一条第一通信走线和至少一条第二通信走线电连接。电路结构层的驱动单元配置为控制所述子像素区域对应的电子纸膜的显示图案。
在一些示例性实施方式中，在衬底上形成电路结构层可以包括：在衬底上依次形成第一导电层、第一绝缘层、半导体层、第一透明导电层、第二导电层、第二绝缘层、第三绝缘层和第二透明导电层。所述第一导电层至少包括：所述多条第一信号线、所述驱动单元的晶体管的栅极；所述半导体层至少包括：所述驱动单元的晶体管的有源层；所述第一透明导电层至少包括：多个触控电极；所述第二导电层至少包括：所述多条第二信号线、所述至少一条第二通信走线和多条触控信号线、所述驱动单元的晶体管的第一极和第二极；所述第二透明导电层至少包括：多个像素电极。
在一些示例性实施方式中，驱动单元的晶体管与第一信号线为一体结构，驱动单元的晶体管的第一极与第二信号线为一体结构，晶体管的第二极与像素电极电连接。
关于本实施例的提供的显示基板的制备过程可以参照前述实施例的说明，故于此不再赘述。
本公开实施例还提供一种显示装置，包括如上所述的显示基板。
图17为本公开至少一实施例的显示装置的示意图。如图17所示，本实 施例提供一种显示装置900，包括：显示基板910。显示基板910可以为前述实施例提供的显示基板。在一些示例中，显示基板910可以为EPD面板。显示装置900可以为：EPD显示装置、电子标签等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (20)

  1. 一种显示基板，包括：
    衬底、以及依次设置在所述衬底上的电路结构层和电子纸膜；
    所述电路结构层包括：沿第一方向延伸的多条第一信号线、沿第二方向延伸的多条第二信号线、多个驱动单元、以及至少一个近场通信线圈；所述第一方向与所述第二方向交叉；所述多条第一信号线和多条第二信号线交叉形成多个子像素区域；所述驱动单元位于所述子像素区域，并与所述第一信号线和第二信号线电连接，所述驱动单元配置为控制所述子像素区域对应的电子纸膜的显示图案；
    所述近场通信线圈包括：沿所述第一方向延伸的至少一条第一通信走线以及沿所述第二方向延伸的至少一条第二通信走线，所述至少一条第一通信走线和所述至少一条第二通信走线电连接。
  2. 根据权利要求1所述的显示基板，其中，至少一条第一信号线在所述第二方向上与所述第一通信走线相邻，至少一条第二信号线在所述第一方向上与所述第二通信走线相邻。
  3. 根据权利要求1或2所述的显示基板，其中，在所述第二方向上相邻两条第一通信走线之间间隔至少一个子像素区域，在所述第一方向上相邻两条第二通信走线之间间隔至少一个子像素区域。
  4. 根据权利要求1至3中任一项所述的显示基板，其中，所述至少一条第一通信走线位于所述至少一条第二通信走线靠近所述衬底的一侧；所述多条第一信号线位于所述多条第二信号线靠近所述衬底的一侧。
  5. 根据权利要求1至4中任一项所述的显示基板，其中，所述至少一条第二通信走线与所述多条第二信号线为同层结构。
  6. 根据权利要求4或5所述的显示基板，其中，所述至少一条第一通信走线与所述多条第一信号线为同层结构。
  7. 根据权利要求4或5所述的显示基板，其中，所述至少一条第一通信走线位于所述多条第一信号线远离所述衬底的一侧。
  8. 根据权利要求1至7中任一项所述的显示基板，其中，所述至少一条 第一通信走线包括：沿所述第一方向延伸且依次排布的多个第一子通信线段，相邻两个第一子通信线段通过第一连接电极电连接，所述第一连接电极位于所述第一子通信线段远离所述衬底的一侧。
  9. 根据权利要求1至8中任一项所述的显示基板，其中，所述衬底包括：至少一个近场通信区域和至少一个非近场通信区域；所述至少一个近场通信线圈位于所述至少一个近场通信区域内，所述至少一个非近场通信区域设置有沿所述第一方向延伸的至少一条第一虚拟通信走线和沿所述第二方向延伸的至少一条第二虚设线圈；所述第一通信走线与所述第一虚拟通信走线断开，所述第二通信走线与所述第二虚设通信走线断开。
  10. 根据权利要求1至9中任一项所述的显示基板，其中，所述电路结构层还包括：多条触控信号线和多个触控电极；所述多条触控信号线沿所述第二方向延伸，至少一条触控信号线与彼此电连接且间隔开的多个触控电极电连接。
  11. 根据权利要求10所述的显示基板，其中，所述至少一条第二通信走线间隔排布在所述多条触控信号线之间，相邻的所述第二通信走线与所述触控信号线之间间隔至少一个子像素区域。
  12. 根据权利要求10或11所述的显示基板，其中，所述驱动单元至少包括：晶体管和像素电极；所述像素电极位于所述子像素区域内；所述晶体管的栅极与所述第一信号线电连接，所述晶体管的第一极与所述第二信号线电连接，所述晶体管的第二极与所述像素电极电连接。
  13. 根据权利要求12所述的显示基板，其中，在垂直于所述显示基板的方向上，所述电路结构层包括：依次设置在所述衬底上的第一导电层、半导体层、第一透明导电层、第二导电层和第二透明导电层；
    所述第一导电层至少包括：所述多条第一信号线、所述驱动单元的晶体管的栅极；
    所述半导体层至少包括：所述驱动单元的晶体管的有源层；
    所述第一透明导电层至少包括：所述多个触控电极；
    所述第二导电层至少包括：所述多条第二信号线、所述至少一条第二通 信走线和所述多条触控信号线；
    所述第二透明导电层至少包括：所述像素电极。
  14. 根据权利要求13所述的显示基板，其中，所述至少一条第一通信走线位于所述第一导电层或所述第一透明导电层。
  15. 根据权利要求14所述的显示基板，其中，所述第二导电层与所述透明导电层之间设置有无机绝缘层和有机绝缘层，所述有机绝缘层位于所述无机绝缘层远离所述衬底的一侧。
  16. 根据权利要求1至15中任一项所述的显示基板，其中，所述电子纸膜被配置为利用所述衬底一侧入射的光线进行显示。
  17. 一种显示装置，包括如权利要求1至16中任一项所述的显示基板。
  18. 一种显示基板的制备方法，包括：
    在衬底上形成电路结构层，所述电路结构层包括：沿第一方向延伸的多条第一信号线、沿第二方向延伸的多条第二信号线、多个驱动单元、以及至少一个近场通信线圈；所述第一方向与所述第二方向交叉；所述多条第一信号线和多条第二信号线交叉形成多个子像素区域；所述驱动单元位于所述子像素区域，并与所述第一信号线和第二信号线电连接；所述近场通信线圈包括：沿所述第一方向延伸的至少一条第一通信走线以及沿所述第二方向延伸的至少一条第二通信走线，所述至少一条第一通信走线和所述至少一条第二通信走线电连接；
    在所述电路结构层远离所述衬底一侧设置电子纸膜；所述电路结构层的驱动单元配置为控制所述子像素区域对应的电子纸膜的显示图案。
  19. 根据权利要求18所述的制备方法，其中，所述在衬底上形成电路结构层，包括：在所述衬底上依次形成第一导电层、第一绝缘层、半导体层、第一透明导电层、第二导电层、第二绝缘层、第三绝缘层和第二透明导电层；
    所述第一导电层至少包括：所述多条第一信号线、所述驱动单元的晶体管的栅极；
    所述半导体层至少包括：所述驱动单元的晶体管的有源层；
    所述第一透明导电层至少包括：多个触控电极；
    所述第二导电层至少包括：所述多条第二信号线、所述至少一条第二通信走线和多条触控信号线、所述驱动单元的晶体管的第一极和第二极；
    所述第二透明导电层至少包括：多个像素电极。
  20. 根据权利要求19所述的制备方法，其中，所述驱动单元的晶体管与所述第一信号线为一体结构，所述驱动单元的晶体管的第一极与第二信号线为一体结构，所述晶体管的第二极与像素电极电连接。
PCT/CN2022/104677 2022-07-08 2022-07-08 显示基板及显示装置 WO2024007315A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2022/104677 WO2024007315A1 (zh) 2022-07-08 2022-07-08 显示基板及显示装置
CN202280002162.1A CN117694035A (zh) 2022-07-08 2022-07-08 显示基板及显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/104677 WO2024007315A1 (zh) 2022-07-08 2022-07-08 显示基板及显示装置

Publications (1)

Publication Number Publication Date
WO2024007315A1 true WO2024007315A1 (zh) 2024-01-11

Family

ID=89454579

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/104677 WO2024007315A1 (zh) 2022-07-08 2022-07-08 显示基板及显示装置

Country Status (2)

Country Link
CN (1) CN117694035A (zh)
WO (1) WO2024007315A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108509899A (zh) * 2018-03-29 2018-09-07 上海天马微电子有限公司 一种显示面板和显示装置
CN109004012A (zh) * 2018-08-03 2018-12-14 上海天马有机发光显示技术有限公司 显示面板及其显示装置
CN109037194A (zh) * 2018-08-03 2018-12-18 上海天马有机发光显示技术有限公司 一种显示面板及其显示装置
WO2021246221A1 (ja) * 2020-06-01 2021-12-09 株式会社ジャパンディスプレイ 電子デバイス及び表示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108509899A (zh) * 2018-03-29 2018-09-07 上海天马微电子有限公司 一种显示面板和显示装置
CN109004012A (zh) * 2018-08-03 2018-12-14 上海天马有机发光显示技术有限公司 显示面板及其显示装置
CN109037194A (zh) * 2018-08-03 2018-12-18 上海天马有机发光显示技术有限公司 一种显示面板及其显示装置
WO2021246221A1 (ja) * 2020-06-01 2021-12-09 株式会社ジャパンディスプレイ 電子デバイス及び表示装置

Also Published As

Publication number Publication date
CN117694035A (zh) 2024-03-12

Similar Documents

Publication Publication Date Title
US10691263B2 (en) Display device including touch sensor and driving method thereof
US10705662B2 (en) Touch substrate and preparation method therefor, and display panel
US9727195B2 (en) Touch panel and method for fabricating the same
CN103677399B (zh) 传感器基板及其制造方法和具有其的感测显示面板
US8289457B2 (en) Liquid crystal display including touch sensor layer and manufacturing method thereof
CN104956297B (zh) 具含银的透明导电层的投影电容式触控面板
CN103262011B (zh) 触摸面板及具备其的显示装置以及触摸面板的制造方法
US7852451B2 (en) Manufacturing method of liquid display device having touch screen function
US20110316810A1 (en) Display device with touch panel
KR102262470B1 (ko) 터치 스크린 패널 제조 방법
CN109839779A (zh) 液晶面板
CN104423715A (zh) 触摸窗和包括该触摸窗的显示器
CN102089735A (zh) 触摸面板、显示装置和电子设备
KR20120001406A (ko) 터치 패널
TWI361331B (en) E-paper apparatus
CN109791452A (zh) 带天线的触摸面板显示器
JP5927915B2 (ja) タッチパネルセンサ基板及びその基板の製造方法
CN111474800B (zh) 阵列基板及其制备方法、电子纸显示装置及其驱动方法
JP2014211685A (ja) タッチセンサ一体型表示装置
KR20110100102A (ko) 터치 패널 일체형 표시 장치
CN112578585A (zh) 显示面板及其制备方法、显示装置
WO2024007315A1 (zh) 显示基板及显示装置
CN109716421A (zh) 安装基板及显示面板
US20170235389A1 (en) Touch Panel and Display Device
US20230168757A1 (en) Touch Panel and Preparation Method thereof, and Display Touch Apparatus