WO2024001192A1 - 片上系统、片上系统的电压控制方法及终端 - Google Patents

片上系统、片上系统的电压控制方法及终端 Download PDF

Info

Publication number
WO2024001192A1
WO2024001192A1 PCT/CN2023/074517 CN2023074517W WO2024001192A1 WO 2024001192 A1 WO2024001192 A1 WO 2024001192A1 CN 2023074517 W CN2023074517 W CN 2023074517W WO 2024001192 A1 WO2024001192 A1 WO 2024001192A1
Authority
WO
WIPO (PCT)
Prior art keywords
storage
voltage
physical layer
voltage domain
chip
Prior art date
Application number
PCT/CN2023/074517
Other languages
English (en)
French (fr)
Inventor
刘卓睿
Original Assignee
哲库科技(上海)有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 哲库科技(上海)有限公司 filed Critical 哲库科技(上海)有限公司
Publication of WO2024001192A1 publication Critical patent/WO2024001192A1/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • Embodiments of the present application relate to the field of storage technology, and in particular to a system on a chip, a voltage control method and a terminal of the system on a chip.
  • Mobile terminals such as mobile phones and tablets are equipped with systems on a chip.
  • the system-on-chip integrates various electrical components such as a central processing unit (CPU), a graphics processor (Graphics Processing Unit, GPU), memory, and power management chips.
  • CPU central processing unit
  • GPU Graphics Processing Unit
  • memory volatile and non-volatile memory
  • power management chips power management chips.
  • the power management chip When the system on chip is working, the power management chip provides power to other electrical components of the system on chip.
  • the power management chip provides power to other electrical components of the system on chip.
  • more and more electrical components are integrated into on-chip systems, and the power consumption per unit time is increasing, resulting in the battery life of mobile terminals being unable to meet design requirements.
  • Embodiments of the present application provide a system on a chip, a voltage control method and a terminal of the system on a chip.
  • the technical solutions are as follows:
  • a system-on-chip which system-on-chip includes: a main device and a plurality of storage-related devices;
  • the main device is a device with data processing capabilities; the main device is connected to at least one of the plurality of storage-related devices;
  • the plurality of storage-related devices include: at least two groups of storage-related devices operating in at least two voltage domains;
  • the at least two voltage domains are independent voltage domains, and the at least two voltage domains correspond to the at least two groups of storage-related devices in a one-to-one correspondence.
  • a voltage control method for a system-on-chip is provided.
  • the method is applied to the system-on-chip as described above.
  • the method includes:
  • the master device controls the storage-related device operating in a target voltage domain to be at a low power consumption voltage, and the target voltage domain is at least one of the at least two voltage domains;
  • the low power consumption voltage is an operating voltage lower than a normal operating voltage.
  • a terminal is provided, the terminal is provided with a memory and a system-on-chip as described above.
  • the memory may be double data rate DDR memory.
  • the operating voltage of each voltage domain can be controlled independently without being affected by adjacent voltage domains, enabling finer-grained and more flexible control of different storage-related devices.
  • the voltage control supports controlling some storage-related devices on the on-chip system to be in a low-power voltage state, effectively reducing the power consumption of the on-chip system on the premise of meeting the voltage requirements under different working states.
  • Figure 1 is an architectural schematic diagram of the memory reading architecture in related technologies
  • Figure 2 is a schematic structural diagram of a system-on-chip according to an exemplary embodiment of the present application
  • Figure 3 is a voltage domain schematic diagram of a system-on-chip shown in an exemplary embodiment of the present application
  • Figure 4 is a schematic structural diagram of a physical layer interface shown in an exemplary embodiment of the present application.
  • Figure 5 is a voltage domain schematic diagram of a system-on-chip shown in an exemplary embodiment of the present application
  • Figure 6 is a schematic structural diagram of a system-on-chip according to an exemplary embodiment of the present application.
  • Figure 7 is a schematic structural diagram of a system-on-chip according to an exemplary embodiment of the present application.
  • Figure 8 is a schematic structural diagram of a system-on-chip according to an exemplary embodiment of the present application.
  • Figure 9 is a schematic structural diagram of a system-on-chip according to an exemplary embodiment of the present application.
  • Figure 11 is a schematic structural diagram of a system-on-chip according to an exemplary embodiment of the present application.
  • Figure 12 is a flow chart of a voltage control method of a system-on-chip according to an exemplary embodiment of the present application
  • Figure 13 is a schematic diagram of a voltage control method of a system-on-chip according to an exemplary embodiment of the present application
  • Figure 14 is a schematic structural diagram of a terminal according to an exemplary embodiment of the present application.
  • the "plurality” mentioned in this article means two or more than two.
  • “And/or” describes the relationship between associated objects, indicating that there can be three relationships.
  • a and/or B can mean: A exists alone, A and B exist simultaneously, and B exists alone.
  • the character “/” generally indicates that the related objects are in an "or” relationship.
  • first, second, third, etc. may be used in this application to describe various information, the information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other.
  • first information may also be called second information, and similarly, the second information may also be called first information.
  • word “if” as used herein may be interpreted as "when” or “when” or “in response to determining.”
  • SoC System on Chip
  • Master 101 to 10N set in the terminal
  • the master devices include but are not limited to Central Processing Unit (CPU) ), image processor (Graphics Processing Unit, GPU), neural network processor (Neural-network Processing Unit, NPU), digital signal processor (Digital Signal Processor, DSP) and other processors, as well as image sensor (Image Sensor), Non-processors such as Image Signal Processing Unit (ISP) and Video Processing Unit (VPU).
  • CPU Central Processing Unit
  • image processor Graphics Processing Unit, GPU
  • NPU neural network processor
  • DSP digital signal processor
  • image sensor Image Sensor
  • Non-processors such as Image Signal Processing Unit (ISP) and Video Processing Unit (VPU).
  • ISP Image Signal Processing Unit
  • VPU Video Processing Unit
  • the above-mentioned main devices all have memory data reading and/or writing requirements during operation.
  • the slave bus 12, the controller 13 and the physical layer interface 14 can be considered as storage-related devices.
  • the storage related device It is a device used to provide a data path between the host device and memory.
  • embodiments of the present application improve the system-on-chip so that the main device or different storage-related devices on the system-on-chip run in independent voltage domains, effectively reducing the power consumption of the system-on-chip while meeting work requirements.
  • the structure and working principle of the system-on-chip are described below through illustrative embodiments.
  • the system-on-chip in this application can be applied to mobile terminals, such as smartphones, smart watches, e-book readers, tablet computers, laptop computers, desktop computers, televisions, game consoles, and augmented reality (Augmented Reality, AR) terminals. , Virtual Reality (VR) terminals and Mixed Reality (MR) terminals, wearable devices, vehicle-mounted devices, electronic tags, etc.
  • mobile terminals such as smartphones, smart watches, e-book readers, tablet computers, laptop computers, desktop computers, televisions, game consoles, and augmented reality (Augmented Reality, AR) terminals.
  • VR Virtual Reality
  • MR Mixed Reality
  • FIG. 2 shows a schematic structural diagram of a system-on-chip 200 provided by an exemplary embodiment of the present application.
  • the system-on-chip 200 in this embodiment includes: a master device 201, a primary bus (Primary Bus) 203, a secondary bus (Secondary Bus) 205, a storage controller 207, and a physical layer (Physical Layer, PHY) interface 209.
  • the master bus 203, the slave bus 205, the storage controller 207 and the physical layer interface 209 are all storage-related devices.
  • the main device 201 is a device with data processing capabilities, that is, a device with data access requirements.
  • the device may include a processor or a non-processor.
  • the processor may include CPU, GPU, NPU, DSP, etc.
  • the non-processor may include image sensor, ISP, VPU, etc.
  • the main device 201 may be a main device that needs to read and write data, such as a processor, or it may only need to read or write, such as an image sensor. Whether the master device 201 has both reading and writing requirements does not constitute a limitation on this application.
  • the processor includes a CPU, a GPU, and an NPU
  • the non-processor includes an image sensor and a VPU.
  • the processor uses various interfaces and lines to connect various parts of the entire terminal device, and executes the terminal device by running or executing instructions, programs, code sets or instruction sets stored in the memory, and calling data stored in the memory. various functions and process data.
  • the processor may adopt at least one of digital signal processing (Digital Signal Processing, DSP), field-programmable gate array (Field-Programmable Gate Array, FPGA), and programmable logic array (Programmable Logic Array, PLA).
  • DSP Digital Signal Processing
  • FPGA field-programmable gate array
  • PLA programmable logic array
  • the processor can integrate one or a combination of CPU, GPU, NPU and baseband chip.
  • the CPU mainly handles the operating system, user interface, and applications;
  • the GPU is responsible for rendering and drawing the content that needs to be displayed on the display;
  • the NPU is used to implement AI functions;
  • the baseband chip is used to process wireless communications.
  • the master device 201 is connected to at least one of a plurality of storage-related devices.
  • the main device 201 is connected to other storage-related devices through the main bus 203 .
  • the master device 201 is connected to the master bus 203 through m links, and the master bus 203 interleaves the links corresponding to different master devices to establish m links with the slave bus 205, m is an integer not less than 1.
  • the embodiment of this application takes m as 4 as an example for description.
  • the link between the master device 201 and the master bus 203 and the link between the master bus 203 and the slave bus 205 use the same bus protocol.
  • this link uses the Advanced eXtensible Interface (AXI) bus protocol.
  • AXI Advanced eXtensible Interface
  • the embodiments of this application do not limit the specific bus protocol adopted by the link.
  • the main bus 203 is implemented as a system cache (System Cache, SC) bus, or the main bus is implemented as an SC bus and an SC slice (or strip, Slice).
  • SC System Cache
  • SC slice or strip, Slice
  • the number of SC slices is m.
  • the main bus 203 has data caching capabilities.
  • the slave bus 205 is connected to the memory controller 207 .
  • the storage controller 207 includes k controllers (corresponding to k memory channels), and k is a positive integer.
  • the link between the slave bus 205 and the storage controller 207 adopts the AXI protocol. The embodiments of this application do not limit the specific bus protocol adopted by the link.
  • k memory channels are established between the slave bus 205 and the memory controller 207 .
  • memory The number of channels is related to the shunt structure in the master bus 203 or the slave bus 205, and k may be an integer multiple or a non-integer multiple of m, which is not limited in this embodiment.
  • 4 links are established between the master bus and the slave bus.
  • the slave bus is connected to 8 controllers to establish 8 memory channels.
  • the storage controller includes DMC 2071, DMC 2072, DMC 2073, DMC 2074, DMC 2075, DMC 2076, DMC 2077 and DMC 2078.
  • K memory channels are established between the storage controller 207 and the physical layer interface 209.
  • the storage controller 207 reads and writes data from the memory through the physical layer interface 209.
  • the physical layer interface 209 includes DDR PHY 2091, DDR PHY 2092, DDR PHY 2093, DDR PHY 2094, DDR PHY 2095, DDR PHY 2096, DDR PHY 2097, and DDR PHY 2098.
  • the physical layer interface 209 includes N groups of physical layer interfaces, where N is a positive integer not less than 1. For example, 8 physical layer interfaces 209 are divided into two groups, and each 4 physical layer interfaces 209 is a group; or, 8 physical layer interfaces 209 are divided into two groups, 2 physical layer interfaces 209 are a group, and 6 One physical layer interface 209 is another group; or, eight physical layer interfaces 209 are divided into two groups, one physical layer interface 209 is one group, and seven physical layer interfaces 209 are another group.
  • the main device operates in one of the at least two voltage domains; or, the main device operates in a voltage domain independent of the at least two voltage domains.
  • the main device operates in another voltage domain, for example, the top (TOP) voltage domain.
  • each group of at least two groups of storage-related devices includes: at least one device among a master bus 203, a slave bus 205, a storage controller 207, and a physical layer interface 209.
  • the distribution of at least two voltage domains of multiple storage-related devices can be divided into at least the following four categories:
  • Type 1 Divided into two voltage domains
  • Type 2 Divided into three voltage domains
  • Type 3 Divided into four voltage domains
  • Type 1 Divided into two voltage domains
  • At least two groups of storage-related devices include: a first storage-related device operating in a first voltage domain, and a second storage-related device operating in a second voltage domain.
  • the first storage-related device includes a master bus 203 and the second storage-related device includes a slave bus 205, a storage controller 207, and a physical layer interface 209.
  • the first storage-related device includes the master bus 203 and the slave bus 205
  • the second storage-related device includes the storage controller 207 and the physical layer interface 209 .
  • the physical layer interface 209 includes N groups of physical layer interfaces, each group of physical layer interfaces in the N groups of physical layer interfaces operating in the first voltage domain and the second voltage domain respectively; or, the N groups of physical layer interfaces Each set of physical layer interfaces in the layer interfaces operates in the second voltage domain.
  • At least two groups of memory-related devices include: a first memory-related device operating in a first voltage domain, a second memory-related device operating in a second voltage domain, and a third memory-related device operating in a third voltage domain. related devices.
  • the first storage-related device includes the master bus 203
  • the second storage-related device includes the slave bus 205 and the storage controller 207
  • the third storage-related device includes the physical layer interface 209 .
  • the first storage-related device includes the master bus 203
  • the second storage-related device includes the slave bus 205
  • the third storage-related device includes the storage controller 207 and the physical layer interface 209 .
  • the first storage-related device includes the master bus 203 and the slave bus 205
  • the second storage-related device includes the storage controller 207
  • the third storage-related device includes the physical layer interface 209 .
  • the physical layer interface 209 includes N groups of physical layer interfaces, each group of physical layer interfaces in the N groups of physical layer interfaces respectively running at least one of the first voltage domain, the second voltage domain, and the third voltage domain. in two voltage domains; or, each group of physical layer interfaces in the N groups of physical layer interfaces operates in a third voltage domain.
  • Type 3 Divided into four voltage domains
  • At least two groups of storage-related devices include: a first storage-related device operating in a first voltage domain (SC voltage domain), and a second storage-related device operating in a second voltage domain (belonging to the DMC voltage domain). , a third storage-related device operating in a third voltage domain (belonging to the DMC voltage domain), and a fourth storage-related device operating in a fourth voltage domain (PHYD voltage domain).
  • SC voltage domain first voltage domain
  • PHYD voltage domain fourth storage-related device operating in a fourth voltage domain
  • the first storage-related device includes the master bus 203
  • the second storage-related device includes the slave bus 205
  • the third storage-related device includes the storage controller 207
  • the fourth storage-related device includes the physical layer interface 209 .
  • the physical layer interface 209 includes N groups of physical layer interfaces. Each group of physical layer interfaces in the N groups of physical layer interfaces respectively operates in the first voltage domain, the second voltage domain, the third voltage domain and the fourth voltage domain. In at least two voltage domains among the voltage domains; or, each group of physical layer interfaces in the N groups of physical layer interfaces operates in a fourth voltage domain.
  • the physical layer interface 209 includes N groups of physical layer interfaces, that is, the k physical layer interfaces are divided into N groups, and each group of physical layer interfaces in the N groups of physical layer interfaces operates in the same or different voltage domains.
  • k is 8 as an example for schematic explanation.
  • N is 1, and the 8 physical layer interfaces are 1 set of physical layer interfaces, operating in the fourth voltage domain as described in Type 3.
  • N is a positive integer greater than 1.
  • N is 2 as an example for schematic explanation.
  • the 8 physical layer interfaces are divided into 2 groups of physical layer interfaces.
  • the first group of physical layer interfaces is a part of the eight physical layer interfaces
  • the second group of physical layer interfaces is a part of the eight physical layer interfaces except the first group of physical layer interfaces.
  • the first group of physical layer interfaces are four physical layer interfaces, namely physical layer interface 2091, physical layer interface 2092, physical layer interface 2093 and physical layer interface 2094.
  • the second group of physical layer interfaces are There are 4 physical layer interfaces, namely physical layer interface 2095, physical layer interface 2096, physical layer interface 2097 and physical layer interface 2098.
  • the number of physical layer interfaces in each group of physical layer interfaces can be any positive integer less than k.
  • This application does not impose any limitation on this, and this embodiment is intended to be schematically illustrated.
  • the first group of physical layer interfaces includes 1 physical layer interface, and the second group of physical layer interfaces includes 7 physical layer interfaces; or, the first group of physical layer interfaces includes 2 physical layer interfaces, and the second group of physical layer interfaces includes 2 physical layer interfaces.
  • the layer interface includes 6 physical layer interfaces, which depend on the specific embodiment and are not limited in this application.
  • At least two groups of storage-related devices include: a first storage-related device operating in a first voltage domain, a second storage-related device operating in a second voltage domain, and a third storage-related device operating in a third voltage domain. a third storage-related device in a voltage domain, a fourth storage-related device operating in a fourth voltage domain, and a fifth storage-related device operating in a fifth voltage domain.
  • the first storage-related device includes the master bus 203
  • the second storage-related device includes the slave bus 205
  • the third storage-related device includes the storage controller 207
  • the fourth storage-related device includes the first group of physical layers in the physical layer interface 209.
  • Interface the fifth storage-related device includes a second set of physical layer interfaces in the physical layer interface 209 .
  • N is 3 as an example for schematic explanation.
  • the 8 physical layer interfaces are divided into 3 groups of physical layer interfaces.
  • the first group of physical layer interfaces is a part of the 8 physical layer interfaces
  • the second group of physical layer interfaces is another part of the 8 physical layer interfaces
  • the third group of physical layer interfaces is 8 physical layer interfaces.
  • the interfaces except the first group of physical layer interfaces and A part of the physical layer interfaces outside the second group of physical layer interfaces.
  • the first group of physical layer interfaces includes 1 physical layer interface
  • the second group of physical layer interfaces includes 5 physical layer interfaces
  • the third group of physical layer interfaces includes 2 physical layer interfaces.
  • At least two sets of memory-related devices include: a first memory-related device operating in a first voltage domain, a second memory-related device operating in a second voltage domain, and a third memory-related device operating in a third voltage domain. related devices, a fourth storage-related device operating in a fourth voltage domain, a fifth storage-related device operating in a fifth voltage domain, and a sixth storage-related device operating in a sixth voltage domain.
  • the first storage-related device includes the master bus 203
  • the second storage-related device includes the slave bus 205
  • the third storage-related device includes the storage controller 207
  • the fourth storage-related device includes the first group of physical layers in the physical layer interface 209.
  • the fifth storage-related device includes a second group of physical layer interfaces in the physical layer interface 209
  • the sixth storage-related device includes a third group of physical layer interfaces in the physical layer interface 209 .
  • the number of N can be increased or decreased according to the needs of the working mode and dynamically configured by the master device.
  • the number of physical layer interfaces in each group of physical layer interfaces increases or decreases as required by the working mode, and is dynamically configured by the master device.
  • the embodiments of the present application realize finer-grained and more flexible voltage control of the main device or storage-related devices, and support the control of some parts of the on-chip system.
  • the device is in a low-power voltage state, which effectively reduces the power consumption of the on-chip system while meeting the voltage requirements under different working states.
  • the above-mentioned at least two voltage domains can be implemented by different power management chips (Power Management Integrated Circuit, PMIC), or a combination of PMIC and low dropout regulator (Low Dropout Regulator, LDO).
  • PMIC Power Management Integrated Circuit
  • LDO Low Dropout Regulator
  • This application provides a schematic embodiment of the structure of a system-on-chip 200.
  • the system-on-chip 200 includes at least two PMICs as an example for description.
  • Each voltage domain described in the above embodiments has a one-to-one corresponding PMIC.
  • the system-on-chip 200 includes two PMICs, and the system-on-chip 200 includes two voltage domains corresponding to the PMICs one-to-one.
  • the master bus 203 running in the first voltage domain is connected to the PMIC 601
  • the slave bus 205, the memory controller 207 and the physical layer interface 209 running in the second voltage domain are connected to the PMIC 602.
  • the main device operates in the first voltage domain and is connected to the PMIC 601; or the main device operates in the second voltage domain and is connected to the PMIC 602.
  • the system-on-chip 200 includes three PMICs, and the system-on-chip 200 includes three voltage domains corresponding to the PMICs.
  • the main bus 203 running in the first voltage domain is connected to the PMIC 701
  • the slave bus 205 and the memory controller 207 running in the second voltage domain are connected to the PMIC 702
  • the slave bus 205 and the memory controller 207 running in the third voltage domain are connected to the PMIC 702.
  • the physical layer interface 209 is connected to the PMIC 703.
  • the main device operates in the first voltage domain and is connected to the PMIC 701; or the main device operates in the second voltage domain and is connected to the PMIC 702; or the main device operates in the third voltage domain and is connected to the PMIC 702. 703 connected.
  • multiple storage-related devices operate in two voltage domains, corresponding to two PMICs, and the main device operates in another independent voltage domain, corresponding to the third PMIC.
  • the system-on-chip 200 includes four PMICs, and the system-on-chip 200 includes four voltage domains that correspond to the PMICs one-to-one.
  • the master bus 203 running in the first voltage domain is connected to the PMIC 801
  • the slave bus 205 running in the second voltage domain is connected to the PMIC 802
  • the memory controller 207 running in the third voltage domain is connected.
  • the physical layer interface 209 running in the fourth voltage domain is connected to PMIC 804.
  • the main device operates in the first voltage domain and is connected to the PMIC 801; or the main device operates in the second voltage domain and is connected to the PMIC 802; or the main device operates in the third voltage domain and is connected to the PMIC 802.
  • the main device 803 is connected; alternatively, the main device operates in the fourth voltage domain and is connected to PMIC 804.
  • multiple storage-related devices operate in three voltage domains, corresponding to three PMICs, and the main device operates in another independent voltage domain, corresponding to the fourth PMIC.
  • the system-on-chip 200 includes 3+N PMICs, and the system-on-chip 200 includes 3+N voltage domains corresponding to the PMICs one-to-one.
  • N is 2, and k physical layer interfaces in the physical layer interface 209 run respectively Among the two voltage domains, both voltage domains have one-to-one corresponding PMICs.
  • the main device operates alone in one of the above voltage domains and has a corresponding PMIC; alternatively, the main device and some of the storage-related devices in at least two groups of storage-related devices jointly run in one of the above voltage domains and jointly have a corresponding PMIC. PMIC.
  • each voltage domain corresponding to the PMIC The possible situations of storage-related devices operating in each voltage domain corresponding to the PMIC are as described in the previous embodiment. This embodiment will not be repeated. This embodiment is intended to schematically illustrate that each independent voltage domain has One-to-one corresponding PMIC.
  • the system-on-chip provided by the embodiments of the present application divides the system-on-chip into at least two independent voltage domains, and each independent voltage domain is provided with a one-to-one corresponding power management chip, achieving a more detailed view of the system-on-chip.
  • Granular and more flexible voltage control supports controlling devices in the corresponding voltage domain through an independent power management chip to be in a low-power voltage state, effectively reducing the power consumption of the on-chip system.
  • This application provides a schematic embodiment of the structure of a system-on-chip 200.
  • the system-on-chip 200 includes at least one PMIC as an example for description.
  • the number of PMICs is less than the number of voltage domains in the system-on-chip 200 .
  • M voltage domains sharing the same PMIC.
  • the M voltage domains are connected to the same PMIC through M LDOs.
  • the M voltage domains correspond to the M LDOs in a one-to-one correspondence.
  • M is no larger than the system-on-chip 200. Positive integer number of medium voltage domains.
  • the system-on-chip 200 has two voltage domains sharing the same PMIC, and the two voltage domains are connected to one PMIC through two LDOs.
  • the main bus 203 running in the first voltage domain is connected to the PMIC 902 through the LDO 901
  • the slave bus 205, the storage controller 207, and the physical layer interface 209 running in the second voltage domain pass through LDO 903 is connected to PMIC 902.
  • the system-on-chip 200 has three voltage domains sharing the same PMIC, and the three voltage domains are connected to one PMIC through three LDOs.
  • the main bus 203 running in the first voltage domain is connected to the PMIC 1002 through the LDO 1001
  • the slave bus 205 and the memory controller 207 running in the second voltage domain are connected to the PMIC through the LDO 1003. 1002.
  • the physical layer interface 209 operating in the third voltage domain is connected to the PMIC 1002 through the LDO 1004.
  • the system-on-chip 200 has four voltage domains sharing the same PMIC, and the four voltage domains are connected to one PMIC through four LDOs.
  • the main bus 203 running in the first voltage domain is connected to the PMIC 1102 through the LDO 1101
  • the slave bus 205 running in the second voltage domain is connected to the PMIC 1102 through the LDO 1103.
  • the memory controller 207 in the three voltage domains is connected to the PMIC 1102 through the LDO 1104, and the physical layer interface 209 running in the fourth voltage domain is connected to the PMIC 1102 through the LDO 1105.
  • the system-on-chip 200 has 3+N voltage domains sharing the same PMIC, and the 3+N voltage domains are connected to one PMIC through 3+N LDOs.
  • N is 2
  • the k physical layer interfaces in the physical layer interface 209 respectively operate in two voltage domains, and the two voltage domains are connected to the same PMIC through corresponding LDOs.
  • the main device operates alone in one of the above voltage domains and is connected to a PMIC through an LDO; alternatively, the main device and some of the storage-related devices in at least two groups of storage-related devices jointly run in one of the above voltage domains and are connected through the same An LDO is connected to a PMIC.
  • the system-on-chip divides the system-on-chip into at least two independent voltage domains.
  • Each independent voltage domain is connected to a PMIC through an independent LDO, achieving a more fine-grained control of the system-on-chip.
  • More flexible voltage control supports controlling the devices in its corresponding voltage domain to be in a low-power voltage state through an independent power management chip, effectively reducing the power consumption of the system-on-chip and reducing the setup cost of the system-on-chip.
  • Figure 12 shows a flow chart of a voltage control method for a system-on-chip provided by an exemplary embodiment of the present application. The method is applied to the system-on-chip 200 as described above. The method includes at least some of the following steps:
  • Step 121 The master device controls the storage-related devices operating in the target voltage domain to be at a low power consumption voltage.
  • the master device controls the storage-related devices running in the target voltage domain to be at a low power consumption voltage based on the working scenario. Different working scenarios are determined by the working status of at least one storage-related device among the plurality of storage-related devices.
  • At least one storage-related device includes a main bus 203.
  • the master device controls the storage-related device running in the target voltage domain to be at low power. consumes voltage.
  • the target voltage domain is the voltage domain in which the slave bus 205 and/or the memory controller 207 and/or the physical layer interface 209 are located.
  • overload refers to the situation where the data read and write load exceeds the threshold.
  • the threshold is predefined, or preconfigured, or dynamically configured by the master device. For example, when the data cached in the main bus 203 exceeds a preconfigured threshold, the main bus 203 reaches overload.
  • the main device 201 controls the voltage in the voltage domain where the storage controller 207 and the physical layer interface 209 are located to reduce to a low power consumption voltage, without affecting the operation of the main bus 203.
  • the total power consumption of the system-on-chip enables more fine-grained low-power control and improves the battery life of the terminal.
  • At least one storage-related device includes a main bus 203
  • the master device 201 controls the storage-related device running in the target voltage domain to be at a low power consumption voltage when the main bus 203 is in bypass mode.
  • the target voltage domain is the voltage domain in which the main bus 203 is located.
  • the fact that the main bus 203 is in the bypass mode means that the main bus 203 is only used for signaling and/or data transmission and does not process data.
  • whether the main bus 203 is in bypass mode is dynamically configured by the master device.
  • the main device 201 controls the main bus 203 to be in bypass mode, and controls the voltage of the voltage domain where the main bus 203 is located to reduce to a low power consumption voltage.
  • the on-chip system includes the main device. 201 and the current path between storage-related devices other than the voltage domain where the main bus 203 is located, without affecting the work of other storage-related devices, reducing the total power consumption of the on-chip system, achieving more fine-grained low-power control, and improving the terminal battery life.
  • At least one storage-related device includes N groups of physical layer interfaces
  • the master device has a first group of physical layer interfaces in the N groups of physical layer interfaces in the target working mode and other than the first group of physical layer interfaces.
  • control the storage-related devices operating in the target voltage domain to be at a low power consumption voltage.
  • the target voltage domain is a voltage domain in which other groups of physical layer interfaces except the first group of physical layer interfaces are located.
  • the target working mode is a working mode, a high-performance working mode, or a common working mode.
  • the working mode refers to the state of providing data access services (or read and write services) to the main device;
  • the high-performance working mode refers to the state of providing data access services to high-performance applications;
  • the common working mode refers to the state that is usually in The common working mode can be the default setting, or defined by the main device, or determined based on the frequency of use.
  • the voltage in the voltage domain of the physical layer interfaces in the physical layer interface 209 other than the first group of physical layer interfaces is controlled to be reduced to a low level.
  • the power consumption voltage can reduce the total power consumption of the on-chip system without affecting the operation of the first group of physical layer interfaces, achieve more fine-grained low-power consumption control, and improve the battery life of the terminal.
  • At least one storage-related device includes all storage-related devices.
  • the master device controls the storage-related devices running in the target voltage domain to be at a low power consumption voltage.
  • the target voltage domain is a voltage domain in which at least one storage-related device among all storage-related devices is located.
  • the non-target working mode is an idle mode or a low-performance working mode.
  • the idle mode refers to a state that does not provide data access services to the main device;
  • the low-performance mode refers to a state that only provides low-performance applications or the default kernel.
  • the (Kernal) control provides the status of the data access service.
  • the main bus 203, the slave bus 205, the storage controller 207, and the physical layer interface 209 are all in idle mode, or all in a low-performance working mode, control the main bus 203, the slave bus 205, and the storage controller 207.
  • the voltage in the voltage domain where the physical layer interface 209 is located is reduced to a low power consumption voltage, which reduces the total power consumption of the on-chip system without affecting the operation of the on-chip system, enables more fine-grained low power consumption control, and improves the battery life of the terminal. .
  • the voltage in the voltage domain of the storage-related device in the idle mode is controlled to be reduced to a low level.
  • the power consumption voltage can reduce the total power consumption of the on-chip system without affecting the operation of the on-chip system, achieve more fine-grained low-power consumption control, and improve the battery life of the terminal.
  • step 121 includes at least the following two implementation methods:
  • Method 1 The master device sends control instructions to the PMIC;
  • the control instructions are used to control the storage-related devices operating in the target voltage domain to be at a low power consumption voltage.
  • Method 2 The master device sends control instructions to the LDO.
  • the control instructions are used to control the storage-related devices operating in the target voltage domain to be at a low power consumption voltage.
  • the method provided by this embodiment controls the main device and storage-related devices in the on-chip system through independent PMIC or LDO to be in at least two voltage domains under different working states, so that some devices are in low power consumption. Under the premise of ensuring the normal operation of the on-chip system, the power consumption of the on-chip system can be effectively reduced.
  • Figure 13 shows a schematic diagram of a voltage control method for a system-on-chip 200 provided by an exemplary embodiment of the present application.
  • the main bus 203 includes an SC bus and four SC slices
  • the slave bus 205 includes four DDR buses.
  • the storage controller 207 includes 8 controllers
  • the physical layer interface 209 includes 8 physical layer interfaces for description as an example, which does not mean to limit the specific structure of the system-on-chip 200 in this application.
  • Phase 1 In the initialization phase, the master device 201, the master bus 203, the slave bus 205, the storage controller 207 and the physical layer interface 209 are all in the same voltage domain.
  • Stage 2 When the system-on-chip 200 is in the default working state, the master device 201 is in the first voltage domain, and the master bus 203, slave bus 205, memory controller 207 and physical layer interface 209 are all in the second voltage domain. Wherein, the voltage in the second voltage domain is less than or equal to the voltage in the first voltage domain.
  • Phase 3 When the cache data in the main bus 203 reaches the reload condition, the main device 201 sends control instructions to the PMIC or LDO connected to other storage-related components other than the main bus 203 to control other components other than the main bus 203.
  • Storage related components are at low power consumption voltages.
  • the master device 201 is in the first voltage domain
  • the master bus 203 is in the second voltage domain
  • the slave bus 205, the storage controller 207 and the physical layer interface 209 are in the third voltage domain.
  • the voltage in the third voltage domain is less than or equal to the voltage in the first voltage domain
  • the voltage in the first voltage domain is less than or equal to the voltage in the second voltage domain.
  • Stage 4 When the physical layer interface 209 is in idle mode, the master device 201 sends control instructions to the PMIC or LDO connected to the physical layer interface 209 to control other storage-related components except the main bus 203 to be at low power consumption voltages.
  • the master device 201 is in the first voltage domain
  • the master bus 203 is in the second voltage domain
  • the slave bus 205 and the memory controller 207 are in the third voltage domain
  • the physical layer interface 209 is in the fourth voltage domain.
  • the voltage in the fourth voltage domain is less than or equal to the voltage in the third voltage domain
  • the voltage in the third voltage domain is less than or equal to the voltage in the first voltage domain
  • the voltage in the first voltage domain is less than or equal to the second voltage domain. voltage in the voltage domain.
  • Phase 5 When the first group of physical layer interfaces in the physical layer interface 209 switches to the working mode, the second group of physical layer interfaces in the physical layer interface 209 is still in the idle mode, and the main device 201 communicates with the first group of physical layer interfaces.
  • the connected PMIC or LDO sends a control instruction to control the first group of physical layer interfaces to switch to the same voltage domain or another independent voltage domain of the master device 201 or the master bus 203 or the slave bus 205 or the memory controller 207 .
  • the master device 201 is in the first voltage domain
  • the master bus 203 and the slave bus 205 are in the second voltage domain
  • the memory controller 207 is in the third voltage domain
  • the object The second group of physical layer interfaces in the physical layer interface 209 is in the fourth voltage domain
  • the first group of physical layer interfaces in the physical layer interface 209 is in the fifth voltage domain.
  • the voltage in the fourth voltage domain is less than or equal to the voltage in the third voltage domain and the fifth voltage domain
  • the voltage in the third voltage domain and the fifth voltage domain is less than or equal to the voltage in the first voltage domain
  • the first The voltage in the voltage domain is less than or equal to the voltage in the second voltage domain.
  • the voltage control method of the system-on-chip supports independently controlling the voltage adjustment of devices in the target voltage domain based on changes in working status, and controls the voltage in the system-on-chip in a finer-grained and more flexible manner.
  • the main device and storage-related devices are at low power consumption voltage, effectively reducing the power consumption of the on-chip system.
  • Figure 14 shows a structural block diagram of a terminal provided by an exemplary embodiment of the present application. Take the terminal 1400 in this embodiment including the system-on-chip 200 and the memory 1402 as an example for explanation:
  • the terminal 1400 is provided with the system-on-chip 200 described in the above embodiment, and the system-on-chip 200 is electrically connected to the memory 1402.
  • the memory 1402 may be provided inside the system-on-chip 200 or outside the system-on-chip 200 .
  • the memory 1402 is a memory that supports k memory channels, and the k storage elements in the memory 1402 each have a working bus, that is, the working bus of each storage element is connected to the system-on-chip 200 in a concurrent manner.
  • k storage elements in the memory 1402 are respectively connected to k physical layer interfaces in the system-on-chip 200 .
  • k is 8
  • the 8 physical layer interfaces correspond to 8 storage elements in a one-to-one manner
  • 8 memory channels are formed between the physical layer interface 209 and the memory 1402.
  • the link between the physical layer interface 209 and the memory 1402 adopts the AXI protocol.
  • the embodiments of this application do not limit the specific bus protocol adopted by the link.
  • the internal particles of the memory element may be arranged in a 2D manner or in a 3D manner.
  • each storage element has a specification of 16Gb ⁇ 16 data width (Data Width).
  • Data Width 16Gb ⁇ 16 data width
  • some storage elements have the same component parameters, some storage components have different component parameters, or different storage components have different component parameters. The embodiments of this application do not limit the specific component parameters of each storage component.
  • K storage elements are packaged into a memory particle, such as a dynamic random access memory device using stacked packaging (package stacking technology).
  • the k storage elements are packaged in 2D or 3D.
  • the embodiments of this application do not limit the specific packaging method.
  • the terminal 1400 can also include other necessary components, such as read-only memory (Read-Only Memory, ROM), display components, input units, audio circuits, speakers, microphones, power supplies and other components. This embodiment will not be described in detail here.
  • ROM read-only memory
  • display components input units
  • audio circuits speakers
  • microphones power supplies and other components. This embodiment will not be described in detail here.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Sources (AREA)

Abstract

本申请实施例公开了一种片上系统、片上系统的电压控制方法及终端，属于存储技术领域。所述片上系统包括：主设备和多个存储相关器件；所述主设备是具有数据处理能力的器件；所述主设备和所述多个存储相关器件中的至少一个相连；所述多个存储相关器件包括：运行在至少两个电压域的至少两组存储相关器件；其中，所述至少两个电压域是相互独立的电压域，所述至少两个电压域和所述至少两组存储相关器件一一对应。通过将片上系统划分为至少两个独立的电压域，每个独立的电压域可以单独实现工作电压而互不影响，实现了对片上系统更细粒度、更灵活的电压控制，支持独立地控制电压域内的器件处于低功耗电压状态，有效降低了片上系统的功耗。

Description

片上系统、片上系统的电压控制方法及终端
本申请要求于2022年6月30日提交的、申请号为202210769914.9、发明名称为“片上系统、片上系统的电压控制方法及终端”的专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及存储技术领域，特别涉及一种片上系统、片上系统的电压控制方法及终端。
背景技术
在诸如手机、平板电脑之类的移动终端中设置有片上系统。该片上系统集成有中央处理器(Central Processing Unit，CPU)、图像处理器(Graphics Processing Unit，GPU)、存储器、电源管理芯片等各种电气元件。
在片上系统工作时，由电源管理芯片为片上系统的其它电气元件提供供电。但随着技术发展，片上系统集成的电气元件越来越多，单位时间内的功耗越来越大，导致移动终端的续航能力无法满足设计需求。
发明内容
本申请实施例提供了一种片上系统、片上系统的电压控制方法及终端。所述技术方案如下：
根据本申请的一个方面，提供了一种片上系统，所述片上系统包括：主设备和多个存储相关器件；
所述主设备是具有数据处理能力的器件；所述主设备和所述多个存储相关器件中的至少一个相连；
所述多个存储相关器件包括：运行在至少两个电压域的至少两组存储相关器件；
其中，所述至少两个电压域是相互独立的电压域，所述至少两个电压域和所述至少两组存储相关器件一一对应。
根据本申请的一个方面，提供了一种片上系统的电压控制方法，所述方法应用于如上所述的片上系统中，所述方法包括：
所述主设备控制运行在目标电压域的存储相关器件处于低功耗电压，所述目标电压域是所述至少两个电压域中的至少一个电压域；
其中，所述低功耗电压是小于正常工作电压的工作电压。
根据本申请的一个方面，提供了一种终端，所述终端上设置有存储器和如上所述的片上系统。该存储器可以是双倍数据速率DDR存储器。
本申请实施例提供的技术方案至少包括如下有益效果：
通过将片上系统划分为至少两个独立的电压域，每个电压域的工作电压可以单独控制，而不受相邻电压域的影响，实现了对不同的存储相关器件进行更细粒度、更灵活的电压控制，支持控制片上系统上的一部分存储相关器件处于低功耗电压状态，在满足不同工作状态下电压需求的前提下有效降低了片上系统的功耗。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域 普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是相关技术中内存读取架构的架构示意图；
图2是本申请一个示例性实施例示出的片上系统的结构示意图；
图3是本申请一个示例性实施例示出的片上系统的电压域示意图；
图4是本申请一个示例性实施例示出的物理层接口的结构示意图；
图5是本申请一个示例性实施例示出的片上系统的电压域示意图；
图6是本申请一个示例性实施例示出的片上系统的结构示意图；
图7是本申请一个示例性实施例示出的片上系统的结构示意图；
图8是本申请一个示例性实施例示出的片上系统的结构示意图；
图9是本申请一个示例性实施例示出的片上系统的结构示意图；
图10是本申请一个示例性实施例示出的片上系统的结构示意图；
图11是本申请一个示例性实施例示出的片上系统的结构示意图；
图12是本申请一个示例性实施例示出的片上系统的电压控制方法的流程图；
图13是本申请一个示例性实施例示出的片上系统的电压控制方法的示意图；
图14是本申请一个示例性实施例示出的终端的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
在本文中提及的“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。在本申请和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。
应当理解，尽管在本申请可能采用术语第一、第二、第三等来描述各种信息，但这些信息不应限于这些术语。这些术语仅用来将同一类型的信息彼此区分开。例如，在不脱离本申请范围的情况下，第一信息也可以被称为第二信息，类似地，第二信息也可以被称为第一信息。取决于语境，如在此所使用的词语“如果”可以被解释成为“在……时”或“当……时”或“响应于确定”。
相关技术中的片上系统(System on Chip，SoC)，如图1所示，终端中设置有N个主设备(Master)101至10N，主设备包括但不限于中央处理器(Central Processing Unit，CPU)、图像处理器(Graphics Processing Unit，GPU)、神经网络处理器(Neural-network Processing Unit，NPU)、数字信号处理器(Digital Signal Processor，DSP)等处理器，以及图像传感器(Image Sensor)、图像信号处理单元(Image Signal Processing Unit，ISP)、视频处理单元(Video Processing Unit，VPU)等非处理器。上述主设备在运行过程中均具有内存数据读和/或写的需求。
图1中各个主设备101至10N与主总线11建立有4条总线链路，以通过总线链路向主总线11发送数据读写指令。主总线11与存储控制装置的从总线12之间也建立有4条链路，而从总线12则与4个控制器13之间建立有4条内存通道。进行数据读写时，从总线12将数据读写指令发送某一内存通道对应的控制器13，由控制器13通过物理层接口14实现对存储器15的数据读写。相关技术中，主设备与主总线11、从总线12、控制器13和物理层接口14均处于同一电压域，在上述部分中的任一部分需要处于高电压状态时，其它部分也需要处于高电压状态下，导致该片上系统的功耗较大，影响终端的续航能力。
其中，从总线12、控制器13和物理层接口14可认为是存储相关器件。该存储相关器件 是用于提供主设备和存储器之间的数据通路的器件。
基于上述问题，本申请实施例对片上系统进行改进，使得片上系统上的主设备或不同的存储相关器件运行在独立的电压域中，满足工作需求的前提下有效降低片上系统的功耗。下面通过示意性的实施例对片上系统的结构以及工作原理进行说明。
本申请中的片上系统可以运用于移动终端，如智能手机、智能手表、电子书阅读器、平板电脑、膝上便携计算机、台式计算机、电视机、游戏机、增强现实(Augmented Reality，AR)终端、虚拟现实(Virtual Reality，VR)终端和混合现实(Mixed Reality，MR)终端、可穿戴式设备、车载设备、电子标签等。
图2示出了本申请一个示例性实施例提供的片上系统200的结构示意图。本实施例中的片上系统200包括：主设备201、主总线(Primary Bus)203、从总线(Secondary Bus)205、存储控制器207以及物理层(Physical Layer，PHY)接口209。其中，主总线203、从总线205、存储控制器207和物理层接口209均为存储相关器件。
主设备201是具有数据处理能力的器件，即具有数据访问需求的设备，该设备可以包括处理器或者非处理器。其中，处理器可以包括CPU、GPU、NPU、DSP等等，而非处理器可以包括图像传感器、ISP、VPU等等。主设备201可以是有数据读和写的需求的主设备，如处理器，也可能只有读或者写的需求，如图像传感器。主设备201是否同时具有读和写的需求不构成对本申请的限定。本申请实施例中以处理器包括CPU、GPU和NPU，非处理器包括图像传感器与VPU为例进行示意性说明，但并不对此构成限定。
其中，处理器利用各种接口和线路连接整个终端设备内的各个部分，通过运行或执行存储在存储器内的指令、程序、代码集或指令集，以及调用存储在存储器内的数据，执行终端设备的各种功能和处理数据。
在一些实施例中，处理器可以采用数字信号处理(Digital Signal Processing，DSP)、现场可编程门阵列(Field-Programmable Gate Array，FPGA)、可编程逻辑阵列(Programmable Logic Array，PLA)中的至少一种硬件形式来实现。
处理器可集成CPU、GPU、NPU和基带芯片等中的一种或几种的组合。其中，CPU主要处理操作系统、用户界面和应用程序等；GPU用于负责显示屏所需要显示的内容的渲染和绘制；NPU用于实现AI功能；基带芯片用于处理无线通信。
主设备201和多个存储相关器件中的至少一个相连。示例性地，主设备201通过主总线203与其它存储相关器件相连。
在一些实施例中，主设备201与主总线203之间通过m条链路相连，主总线203则通过对不同主设备对应的链路进行交织，从而与从总线205建立m条链路，m为不小于1的整数。本申请实施例以m为4为例进行说明。
在一些实施例中，主设备201与主总线203之间的链路，以及主总线203与从总线205之间的链路采用相同的总线协议。比如，该链路均采用先进可扩展接口(Advanced eXtensible Interface，AXI)总线协议。本申请实施例并不对链路所采用的具体总线协议进行限定。
在一些实施例中，主总线203实现成为系统缓存(System Cache，SC)总线，或者，主总线实现成为SC总线和SC片(或称条带，Slice)。可选地，SC片数量为m。主总线203具有数据缓存能力。
从总线205与存储控制器207相连。存储控制器207包括k个控制器(对应k条内存通道)，k为正整数。示例性地，从总线205与存储控制器207之间的链路采用AXI协议。本申请实施例并不对链路所采用的具体总线协议进行限定。
在一些实施例中，从总线实现成为双倍数据速率(Double Data Rate，DDR)总线。示例性地，从总线205包括DDR总线2051、DDR总线2052、DDR总线2053和DDR总线2054。
在一些实施例中，从总线205与存储控制器207之间建立有k条内存通道。其中，内存 通道的数量与主总线203或从总线205中的分路结构相关，k可以为m的整数倍或者非整数倍，本实施例对此不作限定。示例性地，主总线与从总线之间建立有4条链路，经过从总线分路后，从总线与8个控制器相连，建立8条内存通道。示例性地，存储控制器(DDR controller，DMC)包括DMC 2071、DMC 2072、DMC 2073、DMC 2074、DMC 2075、DMC 2076、DMC2077和DMC 2078。
存储控制器207与物理层接口209之间建立有k条内存通道，存储控制器207通过物理层接口209实现对存储器的数据读写。示例性地，物理层接口209包括DDR PHY 2091、DDR PHY 2092、DDR PHY 2093、DDR PHY 2094、DDR PHY 2095、DDR PHY 2096、DDR PHY 2097和DDR PHY 2098。
在一些实施例中，物理层接口209中包括N组物理层接口，N为不小于1的正整数。比如，将8个物理层接口209划分为两组，每4个物理层接口209为一组；或者，将8个物理层接口209划分为两组，2个物理层接口209为一组，6个物理层接口209为另一组；或者，将8个物理层接口209划分为两组，1个物理层接口209为一组，7个物理层接口209为另一组。
本申请实施例中，主设备和多个存储相关器件可以运行在相同或不同的电压域中，多个存储相关器件包括运行在至少两个电压域的至少两组存储相关器件。其中，该至少两个电压域是相互独立的电压域，该至少两个电压域和至少两组存储相关器件一一对应。不同的电压域之间互不影响。
在一些实施例中，针对存储相关器件对应的至少两个电压域，主设备运行在该至少两个电压域中的一个电压域中；或者，主设备运行在与该至少两个电压域独立的另一电压域中，比如，顶层(TOP)电压域。
本申请实施例中，至少两组存储相关器件中的每组存储相关器件包括：主总线203、从总线205、存储控制器207、物理层接口209中的至少一种器件。
本申请实施例中，多个存储相关器件的至少两个电压域分布情况至少可以分为以下四类：
类型一：分为两个电压域；
类型二：分为三个电压域；
类型三：分为四个电压域；
类型四：分为3+N个电压域。
接下来介绍四种类型下多个存储相关器件的电压域分布情况：
类型一：分为两个电压域
该类型中，至少两组存储相关器件包括：运行在第一电压域的第一存储相关器件，和，运行在第二电压域的第二存储相关器件。
在一些实施例中，第一存储相关器件包括主总线203，第二存储相关器件包括从总线205、存储控制器207和物理层接口209。
在一些实施例中，第一存储相关器件包括主总线203和从总线205，第二存储相关器件包括存储控制器207和物理层接口209。
在一些实施例中，第一存储相关器件包括主总线203，从总线205和存储控制器207，第二存储相关器件包括物理层接口209。
在一些实施例中，物理层接口209包括N组物理层接口，该N组物理层接口中的每组物理层接口分别运行在第一电压域和第二电压域中；或者，该N组物理层接口中的每组物理层接口均运行在第二电压域中。
类型二：分为三个电压域
该类型中，至少两组存储相关器件包括：运行在第一电压域的第一存储相关器件，运行在第二电压域的第二存储相关器件，和，运行在第三电压域的第三存储相关器件。
在一些实施例中，第一存储相关器件包括主总线203，第二存储相关器件包括从总线205和存储控制器207，第三存储相关器件包括物理层接口209。
在一些实施例中，第一存储相关器件包括主总线203，第二存储相关器件包括从总线205，第三存储相关器件包括存储控制器207和物理层接口209。
在一些实施例中，第一存储相关器件包括主总线203和从总线205，第二存储相关器件包括存储控制器207，第三存储相关器件包括物理层接口209。
在一些实施例中，物理层接口209包括N组物理层接口，该N组物理层接口中的每组物理层接口分别运行在第一电压域、第二电压域和第三电压域中的至少两个电压域中；或者，该N组物理层接口中的每组物理层接口均运行在第三电压域中。
类型三：分为四个电压域
如图3所示，至少两组存储相关器件包括：运行在第一电压域(SC电压域)的第一存储相关器件，运行在第二电压域(属于DMC电压域)的第二存储相关器件，运行在第三电压域(属于DMC电压域)的第三存储相关器件，和，运行在第四电压域(PHYD电压域)的第四存储相关器件。
其中，第一存储相关器件包括主总线203，第二存储相关器件包括从总线205，第三存储相关器件包括存储控制器207，第四存储相关器件包括物理层接口209。
在一些实施例中，物理层接口209包括N组物理层接口，该N组物理层接口中的每组物理层接口分别运行在第一电压域、第二电压域、第三电压域和第四电压域中的至少两个电压域中；或者，该N组物理层接口中的每组物理层接口均运行在第四电压域中。
类型四：分为3+N个电压域
该类型中，物理层接口209包括N组物理层接口，即k个物理层接口分为N组，该N组物理层接口中的每组物理层接口分别运行在相同或不同的电压域中。
本申请实施例中，以k为8为例进行示意性说明。
在一些实施例中，N为1，8个物理层接口为1组物理层接口，运行在如类型三所述的第四电压域中。
在一些实施例中，N为大于1的正整数，示例性地，以N为2为例进行示意性说明。8个物理层接口分为2组物理层接口。第一组物理层接口是8个物理层接口中的一部分物理层接口，第二组物理层接口是8个物理层接口中除第一组物理层接口外的一部分物理层接口。示例性的如图4所示，第一组物理层接口是4个物理层接口，分别为物理层接口2091、物理层接口2092、物理层接口2093和物理层接口2094，第二组物理层接口是4个物理层接口，分别为物理层接口2095、物理层接口2096、物理层接口2097和物理层接口2098。
需要注意的是，每组物理层接口中的物理层接口数量可以是小于k的任一个正整数，本申请对此不做任何限定，本实施例旨在示意性说明。比如，第一组物理层接口中包括1个物理层接口，第二组物理层接口中包括7个物理层接口；或者，第一组物理层接口中包括2个物理层接口，第二组物理层接口中包括6个物理层接口，视具体的实施例而定，本申请不加以限定。
在一些实施例中，如图5所示，至少两组存储相关器件包括：运行在第一电压域的第一存储相关器件，运行在第二电压域的第二存储相关器件，运行在第三电压域的第三存储相关器件，运行在第四电压域的第四存储相关器件，和，运行在第五电压域的第五存储相关器件。
其中，第一存储相关器件包括主总线203，第二存储相关器件包括从总线205，第三存储相关器件包括存储控制器207，第四存储相关器件包括物理层接口209中的第一组物理层接口，第五存储相关器件包括物理层接口209中的第二组物理层接口。
示例性地，以N为3为例进行示意性说明。8个物理层接口分为3组物理层接口。第一组物理层接口是8个物理层接口中的一部分物理层接口，第二组物理层接口是8个物理层接口中的另一部分物理层接口，第三组物理层接口是8个物理层接口中除第一组物理层接口和 第二组物理层接口外的一部分物理层接口。示例性地，第一组物理层接口中包括1个物理层接口，第二组物理层接口中包括5个物理层接口，第三组物理层接口中包括2个物理层接口。
在一些实施例中，至少两组存储相关器件包括：运行在第一电压域的第一存储相关器件，运行在第二电压域的第二存储相关器件，运行在第三电压域的第三存储相关器件，运行在第四电压域的第四存储相关器件，运行在第五电压域的第五存储相关器件，和，运行在第六电压域的第六存储相关器件。
其中，第一存储相关器件包括主总线203，第二存储相关器件包括从总线205，第三存储相关器件包括存储控制器207，第四存储相关器件包括物理层接口209中的第一组物理层接口，第五存储相关器件包括物理层接口209中的第二组物理层接口，第六存储相关器件包括物理层接口209中的第三组物理层接口。
在一些实施例中，N的数量可以随着工作模式的需要进行增加或减少，由主设备进行动态配置。
在一些实施例中，每组物理层接口中的物理层接口数量随着工作模式的需要进行增加或减少，由主设备进行动态配置。
综上所述，本申请实施例通过将片上系统划分为至少两个独立的电压域，实现了对主设备或存储相关器件进行更细粒度、更灵活的电压控制，支持控制片上系统上的部分器件处于低功耗电压状态，在满足不同工作状态下电压需求的前提下有效降低了片上系统的功耗。
上述至少两个电压域，可以由不同的电源管理芯片(Power Management Integrated Circuit，PMIC)实现，或者，PMIC和低压差稳压器(Low Dropout Regulator，LDO)的组合来实现。
针对每个电压域采用单独的PMIC实现的实施例：
本申请提供了一种片上系统200结构的示意性实施例，本实施例以片上系统200中包括至少两个PMIC为例进行说明。每个上述实施例中所述的电压域均具有一一对应的PMIC。
在一些实施例中，片上系统200中包括两个PMIC，片上系统200中包括与PMIC一一对应的两个电压域。示例性的如图6所示，运行在第一电压域的主总线203与PMIC 601相连，运行在第二电压域的从总线205、存储控制器207和物理层接口209与PMIC 602相连。可选地，主设备运行在第一电压域中，与PMIC 601相连；或者，主设备运行在第二电压域中，与PMIC 602相连。
在一些实施例中，片上系统200中包括三个PMIC，片上系统200中包括与PMIC一一对应的三个电压域。示例性的如图7所示，运行在第一电压域的主总线203与PMIC 701相连，运行在第二电压域的从总线205、存储控制器207与PMIC 702相连，运行在第三电压域的物理层接口209与PMIC 703相连。可选地，主设备运行在第一电压域中，与PMIC 701相连；或者，主设备运行在第二电压域中，与PMIC 702相连；或者，主设备运行在第三电压域中，与PMIC 703相连。或者，多个存储相关器件运行在两个电压域中，分别与两个PMIC一一对应，主设备运行在另一个独立的电压域中，与第三个PMIC对应。
在一些实施例中，片上系统200中包括四个PMIC，片上系统200中包括与PMIC一一对应的四个电压域。示例性的如图8所示，运行在第一电压域的主总线203与PMIC 801相连，运行在第二电压域的从总线205与PMIC 802相连，运行在第三电压域的存储控制器207与PMIC 803相连，运行在第四电压域的物理层接口209与PMIC 804相连。可选地，主设备运行在第一电压域中，与PMIC 801相连；或者，主设备运行在第二电压域中，与PMIC 802相连；或者，主设备运行在第三电压域中，与PMIC 803相连；或者，主设备运行在第四电压域中，与PMIC 804相连。或者，多个存储相关器件运行在三个电压域中，分别与三个PMIC一一对应，主设备运行在另一个独立的电压域中，与第四个PMIC对应。
在一些实施例中，片上系统200中包括3+N个PMIC，片上系统200中包括与PMIC一一对应的3+N个电压域。示例性地，N为2，物理层接口209中的k个物理层接口分别运行 在2个电压域中，该2个电压域均具有一一对应的PMIC。
主设备单独运行在上述其中一个电压域中，单独具有一个对应的PMIC；或者，主设备和至少两组存储相关器件中的一部分存储相关器件共同运行在上述其中一个电压域中，共同具有一个对应的PMIC。
每个与PMIC一一对应的电压域中运行的存储相关器件的可能情况如上一实施例中所述，本实施例不再赘述，本实施例旨在示意性说明每个独立的电压域均具有一一对应的PMIC。
综上所述，本申请实施例提供的片上系统，将片上系统划分为至少两个独立的电压域，每个独立的电压域设置有一一对应的电源管理芯片，实现了对片上系统更细粒度、更灵活的电压控制，支持通过独立的电源管理芯片控制其对应的电压域内的器件处于低功耗电压状态，有效降低了片上系统的功耗。
针对独立的电压域采用PMIC+LDO实现的实施例：
本申请提供了一种片上系统200结构的示意性实施例，本实施例以片上系统200中包括至少一个PMIC为例进行说明。本实施例中，PMIC的数量少于片上系统200中电压域的数量。
本实施例中，存在M个电压域共用同一个PMIC，该M个电压域通过M个LDO与同一个PMIC相连，该M个电压域和M个LDO一一对应，M为不大于片上系统200中电压域的数量的正整数。
在一些实施例中，片上系统200存在2个电压域共用同一个PMIC，该两个电压域通过两个LDO相连至一个PMIC。示例性的如图9所示，运行在第一电压域中的主总线203通过LDO 901相连至PMIC 902，运行在第二电压域中的从总线205、存储控制器207、物理层接口209通过LDO 903相连至PMIC 902。
在一些实施例中，片上系统200存在3个电压域共用同一个PMIC，该三个电压域通过三个LDO相连至一个PMIC。示例性的如图10所示，运行在第一电压域中的主总线203通过LDO 1001相连至PMIC 1002，运行在第二电压域中的从总线205、存储控制器207通过LDO 1003相连至PMIC 1002，运行在第三电压域中的物理层接口209通过LDO 1004相连至PMIC 1002。
在一些实施例中，片上系统200存在4个电压域共用同一个PMIC，该四个电压域通过四个LDO相连至一个PMIC。示例性的如图11所示，运行在第一电压域中的主总线203通过LDO 1101相连至PMIC 1102，运行在第二电压域中的从总线205通过LDO 1103相连至PMIC 1102，运行在第三电压域中的存储控制器207通过LDO 1104相连至PMIC 1102，运行在第四电压域中的物理层接口209通过LDO 1105相连至PMIC 1102。
在一些实施例中，片上系统200存在3+N个电压域共用同一个PMIC，该3+N个电压域通过3+N个LDO相连至一个PMIC。示例性地，N为2，物理层接口209中的k个物理层接口分别运行在2个电压域中，该2个电压域分别通过对应的LDO相连至同一个PMIC。
主设备单独运行在上述其中一个电压域中，单独通过一个LDO相连至一个PMIC；或者，主设备和至少两组存储相关器件中的一部分存储相关器件共同运行在上述其中一个电压域中，通过同一个LDO相连至一个PMIC。
每个与LDO相连的电压域中运行的存储相关器件的可能情况如前述实施例中所述，本实施例不再赘述，本实施例旨在示意性说明每个独立的电压域通过单独的LDO相连至一个PMIC。
综上所述，本申请实施例提供的片上系统，将片上系统划分为至少两个独立的电压域，每个独立的电压域通过独立的LDO连接至一个PMIC，实现了对片上系统更细粒度、更灵活的电压控制，支持通过独立的电源管理芯片控制其对应的电压域内的器件处于低功耗电压状态，有效降低了片上系统的功耗，并且减少了片上系统的设置成本。
图12示出了本申请一个示例性实施例提供的一种片上系统的电压控制方法的流程图，该方法应用于如上所述的片上系统200中，该方法包括如下步骤中的至少部分步骤：
步骤121：主设备控制运行在目标电压域的存储相关器件处于低功耗电压。
目标电压域是至少两个电压域中的至少一个电压域，低功耗电压是小于或等于正常工作电压的工作电压。
在一些实施例中，主设备基于多个存储相关器件中的至少一个存储相关器件的工作状态，控制运行在目标电压域的存储相关器件处于低功耗电压。
在一些实施例中，主设备基于工作场景，控制运行在目标电压域的存储相关器件处于低功耗电压。不同的工作场景由多个存储相关器件中的至少一个存储相关器件的工作状态决定。
在一些实施例中，至少一个存储相关器件包括主总线203，主设备在主总线203中的缓存数据达到重载(Heavy Load)的情况下，控制运行在目标电压域的存储相关器件处于低功耗电压。可选地，目标电压域是从总线205和/或存储控制器207和/或物理层接口209所处的电压域。其中，重载是指数据读写承载超过阈值的情况。可选地，该阈值是预定义的，或预配置的，或由主设备动态配置的。比如，当主总线203中缓存的数据超过预配置的阈值时，主总线203达到重载。
示例性的，当主总线203达到重载条件时，主设备201控制存储控制器207和物理层接口209所在电压域的电压降低至低功耗电压，在不影响主总线203工作的情况下，降低片上系统的总功耗，实现更细粒度的低功耗控制，提升终端的续航能力。
在一些实施例中，至少一个存储相关器件包括主总线203，主设备201在主总线203处于旁路(Bypass)模式的情况下，控制运行在目标电压域的存储相关器件处于低功耗电压。可选地，目标电压域是主总线203所处的电压域。其中，主总线203处于旁路模式是指主总线203仅用于信令和/或数据的传递，并不对数据进行处理。可选地，由主设备动态配置主总线203是否处于旁路模式。
示例性的，当无需主总线203提供数据访问服务时，主设备201控制主总线203处于旁路模式，控制主总线203所在电压域的电压降低至低功耗电压，片上系统中形成包括主设备201与除主总线203所在电压域以外的存储相关器件的电流通路，在不影响其它存储相关器件工作的情况下，降低片上系统的总功耗，实现更细粒度的低功耗控制，提升终端的续航能力。
在一些实施例中，至少一个存储相关器件包括N组物理层接口，主设备在N组物理层接口中的第一组物理层接口处于目标工作模式且除第一组物理层接口之外的其他组物理层接口处于非目标工作模式的情况下，控制运行在目标电压域的存储相关器件处于低功耗电压。可选地，目标电压域是除第一组物理层接口之外的其他组物理层接口所处的电压域。
示例性的，目标工作模式为工作模式，或高性能工作模式，或常用工作模式。其中，工作模式是指正在为主设备提供数据访问服务(或称读写服务)的状态；高性能工作模式是指正在为高性能应用程序提供数据访问服务的状态；常用工作模式是指通常处于的工作状态，该常用工作模式可以为默认设置的，或主设备定义的，或基于使用频率确定得到的。
示例性的，当物理层接口209中的第一组物理层接口处于高性能工作模式时，控制物理层接口209中除第一组物理层接口以外的物理层接口所在电压域的电压降低至低功耗电压，在不影响第一组物理层接口工作的情况下，降低片上系统的总功耗，实现更细粒度的低功耗控制，提升终端的续航能力。
在一些实施例中，至少一个存储相关器件包括全部存储相关器件，主设备在全部存储相关器件满足非目标工作模式的情况下，控制运行在目标电压域的存储相关器件处于低功耗电压。可选地，目标电压域是全部存储相关器件中的至少一个存储相关器件所处的电压域。
示例性的，非目标工作模式为空闲模式，或低性能工作模式。其中，空闲模式是指不为主设备提供数据访问服务的状态；低性能模式是指仅在为低性能应用程序或默认内核 (Kernal)控件提供数据访问服务的状态。
示例性的，当主总线203、从总线205、存储控制器207和物理层接口209全都处于空闲模式，或全都处于低性能工作模式的情况下，控制主总线203、从总线205、存储控制器207和物理层接口209所在电压域的电压降低至低功耗电压，在不影响片上系统工作的情况下，降低片上系统的总功耗，实现更细粒度的低功耗控制，提升终端的续航能力。
当主总线203、从总线205、存储控制器207和物理层接口209中的一部分处于空闲模式、一部分处于低性能工作模式的情况下，控制处于空闲模式的存储相关器件所在电压域的电压降低至低功耗电压，在不影响片上系统工作的情况下，降低片上系统的总功耗，实现更细粒度的低功耗控制，提升终端的续航能力。
在一些实施例中，目标电压域具有独立的PMIC，或者，目标电压域具有独立的LDO。因此，步骤121至少包括以下两种实现方式：
方式一：主设备向PMIC发送控制指令；
控制指令用于控制运行在目标电压域的存储相关器件处于低功耗电压。
方式二：主设备向LDO发送控制指令。
控制指令用于控制运行在目标电压域的存储相关器件处于低功耗电压。
综上所述，本实施例提供的方法，在不同工作状态下，通过独立的PMIC或LDO控制片上系统中的主设备和存储相关器件处于至少两个电压域中，使部分器件处于低功耗电压下，在保证片上系统正常工作的前提下，有效减少片上系统的功耗。
图13示出了本申请一个示例性实施例提供的一种片上系统200的电压控制方法的示意图，本实施例以主总线203包括SC总线和4个SC片，从总线205包括4个DDR总线，存储控制器207包括8个控制器，物理层接口209中包括8个物理层接口为例进行说明，并不意味着对本申请中的片上系统200的具体结构做出限定。
阶段一：在初始化阶段，主设备201、主总线203、从总线205、存储控制器207和物理层接口209均处于同一电压域中。
阶段二：当片上系统200处于默认工作状态下时，主设备201处于第一电压域中，主总线203、从总线205、存储控制器207和物理层接口209均处于第二电压域中。其中，第二电压域的电压小于或等于第一电压域中的电压。
阶段三：当主总线203中的缓存数据达到重载条件的情况下，主设备201向与除主总线203以外的其它存储相关元件相连的PMIC或LDO发送控制指令，控制除主总线203以外的其它存储相关元件处于低功耗电压。示例性地，主设备201处于第一电压域中，主总线203处于第二电压域中，从总线205、存储控制器207和物理层接口209处于第三电压域中。其中，第三电压域中的电压小于或等于第一电压域中的电压，第一电压域中的电压小于或等于第二电压域中的电压。
阶段四：当物理层接口209处于空闲模式时，主设备201向与物理层接口209相连的PMIC或LDO发送控制指令，控制除主总线203以外的其它存储相关元件处于低功耗电压。示例性地，主设备201处于第一电压域中，主总线203处于第二电压域中，从总线205、存储控制器207处于第三电压域中，物理层接口209处于第四电压域中。其中，第四电压域中的电压小于或等于第三电压域中的电压，第三电压域中的电压小于或等于第一电压域中的电压，第一电压域中的电压小于或等于第二电压域中的电压。
阶段五：当物理层接口209中的第一组物理层接口切换至工作模式时，物理层接口209中的第二组物理层接口仍处于空闲模式，主设备201向与第一组物理层接口相连的PMIC或LDO发送控制指令，控制第一组物理层接口切换至主设备201或主总线203或从总线205或存储控制器207相同的电压域或另一独立的电压域中。示例性地，主设备201处于第一电压域中，主总线203和从总线205处于第二电压域中，存储控制器207处于第三电压域中，物 理层接口209中的第二组物理层接口处于第四电压域中，物理层接口209中的第一组物理层接口处于第五电压域中。其中，第四电压域中的电压小于或等于第三电压域、第五电压域中的电压，第三电压域、第五电压域中的电压小于或等于第一电压域中的电压，第一电压域中的电压小于或等于第二电压域中的电压。
综上所述，本申请实施例提供的片上系统的电压控制方法，支持基于工作状态的变化，独立地控制目标电压域中的器件调整电压，通过更细粒度、更灵活地控制片上系统中的主设备和存储相关器件处于低功耗电压，有效降低了片上系统的功耗。
图14示出了本申请一个示例性实施例提供的终端的结构框图。以本实施例中的终端1400包括片上系统200和存储器1402为例进行说明：
终端1400设置有上述实施例所述的片上系统200，片上系统200和存储器1402电性相连。其中，该存储器1402可以设置在片上系统200的内部，或者，设置在片上系统200的外部。
在一些实施例中，存储器1402是支持k条内存通道的存储器，且存储器1402中的k个存储元件分别具备工作总线，即各个存储元件的工作总线通过并发方式与片上系统200相连。
在一些实施例中，存储器1402中的k个存储元件分别与片上系统200中的k个物理层接口相连。示例性的，k为8，8个物理层接口分别于8个存储元件一一对应，物理层接口209与存储器1402之间形成8条内存通道。示例性的，物理层接口209与存储器1402之间的链路采用AXI协议。本申请实施例并不对链路所采用的具体总线协议进行限定。
在一些实施例中，存储元件的内部颗粒可以采用2D方式排列或者3D方式排列。
在一些实施例中，各个存储元件的元件参数(比如容量)相同，比如，各个存储元件均为16Gb×16数据位宽(Data Width)的规格。在另一些实施例中，部分存储元件的元件参数相同，部分存储元件的元件参数不同，或者，不同存储元件的元件参数不同，本申请实施例并不对各个存储元件的具体元件参数进行限定。
k个存储元件被封装成一个存储颗粒，比如采用叠层封装(封装体叠层技术)的动态随机存取存储器器件。在一些可能的设计中，k个存储元件采用2D封装或者3D封装，本申请实施例并不对具体封装方式进行限定。
需要说明的是，除了片上系统200外，终端1400还可以包括其它必要组件，比如只读存储器(Read-Only Memory，ROM)、显示组件、输入单元、音频电路、扬声器、麦克风、电源等部件，本实施例在此不作赘述。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (19)

  1. 一种片上系统，其特征在于，所述片上系统包括：主设备和多个存储相关器件；
    所述主设备是具有数据处理能力的器件；所述主设备和所述多个存储相关器件中的至少一个相连；
    所述多个存储相关器件包括：运行在至少两个电压域的至少两组存储相关器件；
    其中，所述至少两个电压域是相互独立的电压域，所述至少两个电压域和所述至少两组存储相关器件一一对应。
  2. 根据权利要求1所述的片上系统，其特征在于，所述至少两组存储相关器件中的每组存储相关器件包括：主总线、从总线、存储控制器、物理层接口中的至少一种器件。
  3. 根据权利要求2所述的片上系统，其特征在于，所述至少两组存储相关器件包括：运行在第一电压域的第一存储相关器件，和，运行在第二电压域的第二存储相关器件；
    所述第一存储相关器件包括所述主总线，所述第二存储相关器件包括所述从总线，所述存储控制器和所述物理层接口；
    或，
    所述第一存储相关器件包括所述主总线和所述从总线，所述第二存储相关器件包括所述存储控制器和所述物理层接口；
    或，
    所述第一存储相关器件包括所述主总线，所述从总线和所述存储控制器，所述第二存储相关器件包括所述物理层接口。
  4. 根据权利要求2所述的片上系统，其特征在于，所述至少两组存储相关器件包括：运行在第一电压域的第一存储相关器件，运行在第二电压域的第二存储相关器件，和，运行在第三电压域的第三存储相关器件；
    所述第一存储相关器件包括所述主总线，所述第二存储相关器件包括所述从总线和所述存储控制器，所述第三存储相关器件包括所述物理层接口；
    或，
    所述第一存储相关器件包括所述主总线，所述第二存储相关器件包括所述从总线，所述第三存储相关器件包括所述存储控制器和所述物理层接口；
    或，
    所述第一存储相关器件包括所述主总线和所述从总线，所述第二存储相关器件包括所述存储控制器，所述第三存储相关器件包括所述物理层接口。
  5. 根据权利要求2所述的片上系统，其特征在于，所述至少两组存储相关器件包括：运行在第一电压域的第一存储相关器件，运行在第二电压域的第二存储相关器件，运行在第三电压域的第三存储相关器件，和，运行在第四电压域的第四存储相关器件；
    所述第一存储相关器件包括所述主总线，所述第二存储相关器件包括所述从总线，所述第三存储相关器件包括所述存储控制器，所述第四存储相关器件包括所述物理层接口。
  6. 根据权利要求2至5任一所述的片上系统，其特征在于，所述物理层接口包括N组物理层接口，所述N组物理层接口中的每组物理层接口分别运行在不同的电压域中，所述N为大于1的正整数。
  7. 根据权利要求1至6任一所述的片上系统，其特征在于，
    所述主设备运行在所述至少两个电压域中的一个电压域中；
    或，
    所述主设备运行在与所述至少两个电压域独立的另一电压域中。
  8. 根据权利要求1至7任一所述的片上系统，其特征在于，所述片上系统包括至少两个电源管理芯片，每个所述电压域具有一一对应的所述电源管理芯片。
  9. 根据权利要求1至7任一所述的片上系统，其特征在于，所述片上系统包括至少一个电源管理芯片，所述电源管理芯片的数量少于所述电压域的数量；
    存在M个电压域共用同一个所述电源管理芯片，所述M个电压域通过M个低压差稳压器LDO与同一个所述电源管理芯片相连，所述M个电压域和所述M个低压差稳压器LDO一一对应，M为不大于所述电压域的数量的正整数。
  10. 一种片上系统的电压控制方法，其特征在于，所述方法应用于如权利要求1至9任一所述的片上系统中，所述方法包括：
    所述主设备控制运行在目标电压域的存储相关器件处于低功耗电压，所述目标电压域是所述至少两个电压域中的至少一个电压域；
    其中，所述低功耗电压是小于正常工作电压的工作电压。
  11. 根据权利要求10所述的电压控制方法，其特征在于，所述主设备控制运行在目标电压域的存储相关器件处于低功耗电压，包括：
    所述主设备基于所述多个存储相关器件中的至少一个存储相关器件的工作状态，控制运行在所述目标电压域的存储相关器件处于所述低功耗电压。
  12. 根据权利要求11所述的电压控制方法，其特征在于，所述至少一个存储相关器件包括主总线；
    所述主设备基于所述多个存储相关器件中的至少一个存储相关器件的工作状态，控制运行在所述目标电压域的存储相关器件处于所述低功耗电压，包括：
    所述主设备在所述主总线中的缓存数据达到重载条件的情况下，控制运行在所述目标电压域的存储相关器件处于所述低功耗电压；
    其中，所述目标电压域是从总线和/或存储控制器和/或物理层接口所处的电压域。
  13. 根据权利要求11所述的电压控制方法，其特征在于，所述至少一个存储相关器件包括N组物理层接口；
    所述主设备基于所述多个存储相关器件中的至少一个存储相关器件的工作状态，控制运行在所述目标电压域的存储相关器件处于所述低功耗电压，包括：
    所述主设备在所述N组物理层接口中的第一组物理层接口处于目标工作模式且除所述第一组物理层接口之外的其他组物理层接口处于非目标工作模式的情况下，控制运行在所述目标电压域的存储相关器件处于所述低功耗电压；
    其中，所述目标电压域是除所述第一组物理层接口之外的其他组物理层接口所处的电压域。
  14. 根据权利要求11所述的电压控制方法，其特征在于，所述至少一个存储相关器件包括主总线；
    所述主设备基于所述多个存储相关器件中的至少一个存储相关器件的工作状态，控制运 行在所述目标电压域的存储相关器件处于所述低功耗电压，包括：
    所述主设备在所述主总线处于旁路模式的情况下，控制运行在所述目标电压域的存储相关器件处于所述低功耗电压；
    其中，所述目标电压域是所述主总线所处的电压域。
  15. 根据权利要求11所述的电压控制方法，其特征在于，所述至少一个存储相关器件包括全部存储相关器件；
    所述主设备基于所述多个存储相关器件中的至少一个存储相关器件的工作状态，控制运行在所述目标电压域的存储相关器件处于所述低功耗电压，包括：
    所述主设备在所述全部存储相关器件满足非目标工作模式的情况下，控制运行在所述目标电压域的存储相关器件处于所述低功耗电压；
    其中，所述目标电压域是所述全部存储相关器件中的至少一个存储相关器件所处的电压域。
  16. 根据权利要求10至15任一所述的电压控制方法，其特征在于，所述目标电压域具有独立的电源管理芯片；
    所述主设备向所述电源管理芯片发送控制指令，所述控制指令用于控制运行在所述目标电压域的存储相关器件处于所述低功耗电压。
  17. 根据权利要求10至15任一所述的电压控制方法，其特征在于，所述目标电压域具有独立的低压差稳压器LDO；
    所述主设备向所述LDO发送控制指令，所述控制指令用于控制运行在所述目标电压域的存储相关器件处于所述低功耗电压。
  18. 一种终端，其特征在于，所述终端上设置有存储器和如权利要求1至9任一所述的片上系统。
  19. 根据权利要求18所述的终端，其特征在于，所述存储器为双倍数据速率DDR存储器。
PCT/CN2023/074517 2022-06-30 2023-02-06 片上系统、片上系统的电压控制方法及终端 WO2024001192A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210769914.9A CN117370267A (zh) 2022-06-30 2022-06-30 片上系统、片上系统的电压控制方法及终端
CN202210769914.9 2022-06-30

Publications (1)

Publication Number Publication Date
WO2024001192A1 true WO2024001192A1 (zh) 2024-01-04

Family

ID=89383871

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/074517 WO2024001192A1 (zh) 2022-06-30 2023-02-06 片上系统、片上系统的电压控制方法及终端

Country Status (2)

Country Link
CN (1) CN117370267A (zh)
WO (1) WO2024001192A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140181471A1 (en) * 2012-12-21 2014-06-26 Apple Inc. Adaptive Data Collection Practices in a Multi-Processor Device
CN105183432A (zh) * 2015-08-26 2015-12-23 中国航天科工集团第三研究院第八三五七研究所 一种面向健康管理的SoC系统
CN112860428A (zh) * 2019-11-28 2021-05-28 华为技术有限公司 一种高能效的显示处理方法及设备

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140181471A1 (en) * 2012-12-21 2014-06-26 Apple Inc. Adaptive Data Collection Practices in a Multi-Processor Device
CN105183432A (zh) * 2015-08-26 2015-12-23 中国航天科工集团第三研究院第八三五七研究所 一种面向健康管理的SoC系统
CN112860428A (zh) * 2019-11-28 2021-05-28 华为技术有限公司 一种高能效的显示处理方法及设备

Also Published As

Publication number Publication date
CN117370267A (zh) 2024-01-09

Similar Documents

Publication Publication Date Title
US11567695B2 (en) Buffer circuit with data bit inversion
KR101728973B1 (ko) 성능 및 전력을 위해 구성가능한 3ｄ 메모리
US20050146529A1 (en) Scalable unified memory architecture
US10241932B2 (en) Power saving method and apparatus for first in first out (FIFO) memories
US8959298B2 (en) System and method for managing performance of a computing device having dissimilar memory types
US11809906B2 (en) Systems and methods to control bandwidth through shared transaction limits
DE112012006070B4 (de) Speichergerät, das auf Gerätebefehle zur Betriebssteuerung reagiert
WO2024001192A1 (zh) 片上系统、片上系统的电压控制方法及终端
US11152046B1 (en) Sram bit cell retention
TWI763158B (zh) 記憶體共享
US9081766B2 (en) Memory and process sharing via input/output with virtualization
WO2024021657A1 (zh) 存储控制方法、装置、设备、存储介质、芯片及存储器
WO2023231437A1 (zh) 存储器、片上系统、终端设备及供电控制方法
CN115687196B (zh) 用于对多通道存储器进行控制的方法和装置
US20220171551A1 (en) Available memory optimization to manage multiple memory channels
CN117130976A (zh) 存储器、片上系统、终端及数据读写方法
JP2024513743A (ja) 適応型の動的クロックおよび電圧スケーリング
CN117193510A (zh) 存储器的控制方法、存储器、片上系统及终端
CN110809754A (zh) 用于计算设备中的动态缓冲器大小设定的系统和方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23829385

Country of ref document: EP

Kind code of ref document: A1