WO2024001065A1

WO2024001065A1 - Pixel circuit and display panel

Info

Publication number: WO2024001065A1
Application number: PCT/CN2022/138783
Authority: WO
Inventors: 陈书志
Original assignee: 上海闻泰电子科技有限公司
Priority date: 2022-06-30
Filing date: 2022-12-13
Publication date: 2024-01-04
Also published as: CN115019722A

Abstract

Embodiments of the present disclosure provide a pixel circuit and a display panel. The pixel circuit comprises a driving unit, a light emitting unit, a first writing unit, a second writing unit, a duration adjusting unit, and a signal selecting unit; the driving unit is configured to drive, according to a first power supply, the light emitting unit to emit light; the first writing unit is configured to write a first data voltage and a compensation voltage to a first node of the driving unit; the second writing unit is configured to write a second data voltage to a first node of the duration adjusting unit; the signal selecting unit is configured to select different signal selecting circuits to output frequency sweep signals; and the duration adjusting unit is configured to control, according to the frequency sweep signals outputted by the signal selecting circuits selected by the signal selecting unit, the second data voltage, the first power supply, the first data voltage, and the compensation voltage, a duration of a current flowing through the light emitting unit. By implementing the embodiments of the present disclosure, the light emitting duration can be controlled.

Description

Pixel circuit and display panel

Related cross-references

This disclosure claims priority to the Chinese patent application filed with the China Patent Office on June 30, 2022, with application number 2022107725340 and the invention name "pixel circuit and display panel", the entire content of which is incorporated into this disclosure by reference.

Technical field

The present disclosure relates to pixel circuits and display panels.

Background technique

Micro LED display devices have attracted more and more attention due to their advantages such as low driving voltage, long life, and wide temperature resistance. The Micro LED display is a current-type driven light-emitting display unit, which is different from the liquid crystal voltage-type drive. Current-type control needs to control the passing current of the TFT to control the current passing by the Micro LED. Therefore, in the case of low gray scale, the voltage of data is relatively small and modulated within a minimum unit voltage range. The brightness difference caused by the difference in current of the Micro LED is not obvious, causing some gray scales to be unable to be displayed and lost, and The lighting duration cannot be controlled.

Contents of the invention

(1) Technical problems to be solved

In the existing technology, the brightness difference of Micro LED due to the difference in current is not obvious, resulting in the phenomenon that some grayscales of Micro LED cannot be displayed and are lost, and there is a problem that the lighting time cannot be controlled.

(2) Technical solutions

According to various embodiments of the present disclosure, a pixel circuit and a display panel are provided.

A pixel circuit, the pixel circuit includes a driving unit, a light-emitting unit, a first writing unit, a second writing unit, a duration adjustment unit and a signal selection unit; the driving unit is used to drive the The light-emitting unit emits light; the first writing unit is used to write the first data voltage and the compensation voltage to the first node of the driving unit; the second writing unit is used to write the first data voltage and the compensation voltage to the duration adjustment unit The second data voltage is written to the first node of The output sweep signal, the second data voltage, the first power supply, the first data voltage and the compensation voltage control the duration of current flowing through the light-emitting unit.

As an optional implementation manner of the embodiment of the present disclosure, the signal selection unit includes three signal selection circuits, each of the signal selection circuits includes a thin film transistor and a coupling capacitor, and the capacitance value of each coupling capacitor is are different; the first electrode of each thin film transistor is connected to the frequency sweep signal, the gate electrode of each thin film transistor is connected to a turn-on signal, and the second electrode of each thin film transistor is connected to a corresponding coupling capacitor. One end of the coupling capacitor is connected to the second node of the duration adjustment unit; the other end of each coupling capacitor is connected to the third power supply.

As an optional implementation of the embodiment of the present disclosure, the driving unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor and a first capacitor; the first electrode of the first thin film transistor is connected to the first thin film transistor respectively. The first power supply, the third node of the duration adjustment unit and one end of the first capacitor are connected, and the second pole of the first thin film transistor is respectively connected to the first node of the first writing unit and the first capacitor. The first electrode of the second thin film transistor is connected; the second electrode of the second thin film transistor is respectively connected to the first electrode of the third thin film transistor and the second node of the first writing unit; the third The second electrode of the thin film transistor is connected to the light-emitting unit; the gate electrode of the first thin film transistor and the gate electrode of the third thin film transistor are connected to the first start signal, and the gate electrode of the second thin film transistor is respectively connected to The fourth node of the first writing unit, the third node of the duration adjustment unit and the other end of the first capacitor are connected.

As an optional implementation manner of the embodiment of the present disclosure, the first writing unit includes a fourth thin film transistor and a fifth thin film transistor; the first electrode of the fourth thin film transistor is connected to the first data voltage, The second electrode of the fourth thin film transistor is connected to the second electrode of the first thin film transistor and the first electrode of the second thin film transistor respectively; the first electrode of the fifth thin film transistor is connected to the first electrode of the fifth thin film transistor respectively. The second electrode of the two thin film transistors is connected to the first electrode of the third thin film transistor, and the second electrode of the fifth thin film transistor is respectively connected to the gate electrode of the second thin film transistor and the fourth electrode of the duration adjustment unit. The node is connected to the other end of the first capacitor; the gate electrode of the fourth thin film transistor and the gate electrode of the fifth thin film transistor are respectively connected to the second start signal.

As an optional implementation manner of the embodiment of the present disclosure, the second writing unit includes a sixth thin film transistor; the first electrode of the sixth thin film transistor is connected to the second data voltage, and the sixth thin film transistor The second electrode of the transistor is connected to the first node of the duration adjustment unit; the gate electrode of the sixth thin film transistor is connected to the second start signal.

As an optional implementation of the embodiment of the present disclosure, the duration adjustment unit includes a seventh thin film transistor, an eighth thin film transistor, and a second capacitor; the first pole of the seventh thin film transistor is connected to the first power supply respectively. , the first electrode of the first thin film transistor is connected to one end of the first capacitor, the second electrode of the seventh thin film transistor is respectively connected to the first electrode of the eighth thin film transistor; the eighth thin film transistor The second electrode of the transistor is respectively connected to the second electrode of the fifth thin film transistor, the gate electrode of the second thin film transistor and the other end of the first capacitor; the gate electrode of the seventh thin film transistor is respectively connected to the gate electrode of the seventh thin film transistor. The second electrodes of the six thin film transistors are connected to one end of the second capacitor, and the gate electrode of the eighth thin film transistor is connected to the control signal; the other end of the second capacitor is connected to each coupling in the signal selection unit. One end of the capacitor is connected.

As an optional implementation of the embodiment of the present disclosure, the circuit further includes a reset unit; the reset unit is used to adjust the voltage of the first node of the driving unit and the first node of the duration adjustment unit. to the reference voltage.

As an optional implementation manner of the embodiment of the present disclosure, the reset unit includes a ninth thin film transistor, a tenth thin film transistor, and an eleventh thin film transistor; the first electrode of the ninth thin film transistor is connected to the input of the light-emitting unit respectively. terminal is connected to the second terminal of the third thin film transistor, and the second terminal of the ninth thin film transistor is respectively connected to the reference voltage, the first terminal of the tenth thin film transistor, and the first terminal of the eleventh thin film transistor. The first electrode is connected; the second electrode of the tenth thin film transistor is respectively connected to the second electrode of the eighth thin film transistor, the second electrode of the fifth thin film transistor, the gate electrode of the second thin film transistor, and the second electrode of the tenth thin film transistor. The other end of the first capacitor is connected; the second electrode of the eleventh thin film transistor is respectively connected to the gate electrode of the seventh thin film transistor, the second electrode of the sixth thin film transistor and one end of the second capacitor; The gate electrode of the ninth thin film transistor, the gate electrode of the tenth thin film transistor, and the gate electrode of the eleventh thin film transistor are respectively connected to the third start signal.

As an optional implementation manner of the embodiment of the present disclosure, the capacitance value of the coupling capacitor in the signal selection circuit selected by the signal selection unit is positively correlated with the time period during which the duration adjustment unit controls the current to flow through the light-emitting unit. .

As an optional implementation manner of the embodiment of the present disclosure, the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, the At least one of the sixth thin film transistor, the seventh thin film transistor, the eighth thin film transistor, the ninth thin film transistor, the tenth thin film transistor, and the eleventh thin film transistor is a P-type transistor.

A display panel includes a plurality of pixel circuits, and the pixel circuits are any pixel circuits disclosed in this disclosure.

As an optional implementation of the embodiment of the present disclosure, the display panel includes a display area and an edge area located at the periphery of the display area, and the driving unit, the light-emitting unit, the first writing unit, and the second writing unit , duration adjustment units are located in the display area, and the signal selection unit is arranged in the edge area.

As an optional implementation of the embodiment of the present disclosure, the edge area includes a wiring area and a blank area;

The signal selection unit is arranged in the blank area.

As an optional implementation manner of the embodiment of the present disclosure, the pixel circuit further includes a reset unit, the reset unit is used to adjust the voltage of the first node of the driving unit and the first node of the duration adjustment unit. to the reference voltage, and the reset unit is disposed in the display area.

As an optional implementation manner of the embodiment of the present disclosure, the display panel is a micro-light-emitting diode display panel or an organic light-emitting diode display panel.

Additional features and advantages of the disclosure will be set forth in the description which follows, and, in part, will be apparent from the description, or may be learned by practice of the disclosure. The objectives and other advantages of the disclosure may be realized and attained by the structure particularly pointed out in the specification, claims and appended drawings, and the details of one or more embodiments of the disclosure are set forth in the accompanying drawings and description below.

In order to make the above objects, features and advantages of the present disclosure more obvious and understandable, optional embodiments are listed below and described in detail with reference to the accompanying drawings.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following will briefly introduce the drawings needed to describe the embodiments or the prior art. Obviously, for those of ordinary skill in the art, It is said that other drawings can be obtained based on these drawings without exerting creative labor.

Figure 1 is a schematic structural diagram of a pixel circuit provided by one or more embodiments of the present disclosure;

Figure 2 is a driving timing diagram of a pixel circuit provided by one or more embodiments of the present disclosure;

FIG. 3 is a schematic diagram of voltage and current changes over time of a pixel circuit provided by one or more embodiments of the present disclosure;

Figure 4 is a schematic structural diagram of a display panel provided by one or more embodiments of the present disclosure;

Among them, the reference numbers are: 10. Driving unit; 20. Light-emitting unit; 30. First writing unit; 40. Second writing unit; 50. Duration adjustment unit; 60. Signal selection unit; 70. Reset unit; T1, first thin film transistor; T2, second thin film transistor; T3, third thin film transistor; T4, fourth thin film transistor; T5, fifth thin film transistor; T6, sixth thin film transistor; T7, seventh thin film transistor; T8 , eighth thin film transistor; T9, ninth thin film transistor; T10, tenth thin film transistor; T11, eleventh thin film transistor; EM, first start signal; G(n), second start signal; G(n-1 ), the third start signal; Control, control signal; Data1, first data voltage; Data2, second data voltage; C1, first capacitor; C2, second capacitor; Ca, coupling capacitor; Cb, coupling capacitor; Cc, Coupling capacitor; S1, turn-on signal; S2, turn-on signal; S3, turn-on signal; Sweep, frequency sweep signal; VDD, first power supply; VSS, third power supply; Vref, reference voltage.

Detailed ways

In order to understand the above objects, features and advantages of the present disclosure more clearly, the solutions of the present disclosure will be further described below. It should be noted that, as long as there is no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other.

Many specific details are set forth in the following description to fully understand the present disclosure, but the present disclosure can also be implemented in other ways different from those described here; obviously, the embodiments in the description are only part of the embodiments of the present disclosure, and Not all examples.

The terms "first", "second", etc. in the description and claims of the present disclosure are used to distinguish different objects, rather than to describe a specific order of objects. For example, the first camera and the second camera are used to distinguish different cameras, rather than to describe a specific order of the cameras.

In the embodiments of the present disclosure, words such as “exemplary” or “for example” mean examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "such as" in the present disclosure is not intended to be construed as preferred or advantageous over other embodiments or designs. To be precise, the use of words such as "exemplary" or "such as" is intended to present relevant concepts in a specific manner. In addition, in the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "plurality" refers to both one or more than two.

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this disclosure.

It should be noted that the terms "including" and "having" and any variations thereof in the embodiments of the present disclosure and the drawings are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes Other steps or units inherent to such processes, methods, products or devices.

Embodiments of the present disclosure disclose a pixel circuit and a display panel that can select different driving methods to improve gray scale loss or poor display in low gray scale situations, and can control the lighting duration. Each is explained in detail below.

Please refer to Figure 1. Figure 1 is a schematic structural diagram of a pixel circuit disclosed in an embodiment of the present disclosure. As shown in FIG. 1 , the pixel circuit provided by the embodiment of the present disclosure can be used in a display panel to emit display light. Specifically, the pixel circuit may include: a driving unit 10 , a light emitting unit 20 , a first writing unit 30 , a second writing unit 40 , a duration adjustment unit 50 and a signal selection unit 60 .

The driving unit 10 is used to drive the light-emitting unit 20 to emit light according to the first power supply;

The first writing unit 30 is used to write the first data voltage and the compensation voltage to the first node of the driving unit 10;

The second writing unit 40 is used to write the second data voltage to the first node of the duration adjustment unit 50;

The signal selection unit 60 is used to select different signal selection circuits to output frequency sweep signals;

The duration adjustment unit 50 is used to control the duration of the current flowing through the light-emitting unit 20 according to the frequency sweep signal output by the signal selection circuit selected by the signal selection unit 60, the second data voltage, the first power supply, the first data voltage and the compensation voltage. .

In the embodiment of the present disclosure, the light-emitting unit 20 may be a current-driven light-emitting device including Micro LED (Micro Light Emitting Diode) in the prior art. In the embodiment of the present disclosure, Micro LED is used as an example. Be explained.

Using the above embodiment, the first writing unit 30 writes the first data voltage and the compensation voltage to the Q node in the circuit, where the compensation voltage is the internal compensation voltage generated when the gate and drain of the thin film transistor are connected; the second The writing unit 40 writes the second data voltage to the g node in the circuit, so that the driving unit 10 is turned on and outputs current to the light-emitting unit 20 to cause it to emit light. Then, after the signal selection unit 60 selects different signal selection circuits and outputs the frequency sweep signal, the frequency sweep signal is coupled with the second data voltage so that the duration adjustment unit 50 is turned on. After the duration adjustment unit 50 is turned on, the voltage at the Q point is coupled with the first power supply so that The driving unit 10 is turned off, so that the light emitting unit 20 stops emitting light. In this process, the signal selection unit 60 selects different signal selection circuits to output frequency sweep signals to control the conduction speed of the duration adjustment unit 50, thereby controlling the lighting duration of the light-emitting unit 20.

Please refer to Figure 1 again. In one embodiment, the signal selection unit 60 may include three signal selection circuits. Each signal selection circuit includes a thin film transistor and a coupling capacitor, and the capacitance values of each coupling capacitor are different;

The first electrode of each thin film transistor is respectively connected to the frequency sweep signal, the gate electrode of each thin film transistor is respectively connected to a turn-on signal, and the second electrode of each thin film transistor is respectively connected to one end of the corresponding coupling capacitor and the second node of the duration adjustment unit 50 connect;

The other end of each coupling capacitor is connected to the third power supply.

The driving unit 10 includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3 and a first capacitor C1; the first pole of the first thin film transistor T1 is connected to the first power supply and the third node of the duration adjustment unit 50 respectively. and one end of the first capacitor is connected, the second pole of the first thin film transistor T1 is connected to the first node of the first writing unit 30 and the first pole of the second thin film transistor T2 respectively; the second pole of the second thin film transistor T2 are respectively connected to the first electrode of the third thin film transistor T3 and the second node of the first writing unit 30; the second electrode of the third thin film transistor T3 is connected to the light emitting unit 20; the gate electrode of the first thin film transistor T1 and the third The gate of the thin film transistor T3 is connected to the first start signal, and the gate of the second thin film transistor T2 is connected to the fourth node of the first writing unit 30, the third node of the duration adjustment unit 50, and the other end of the first capacitor respectively. .

The first writing unit 30 includes a fourth thin film transistor T4 and a fifth thin film transistor T5; the first electrode of the fourth thin film transistor T4 is connected to the first data voltage, and the second electrode of the fourth thin film transistor T4 is connected to the first thin film transistor respectively. The second electrode of T1 is connected to the first electrode of the second thin film transistor T2; the first electrode of the fifth thin film transistor T5 is connected to the second electrode of the second thin film transistor T2 and the first electrode of the third thin film transistor T3 respectively. The second electrode of the fifth thin film transistor T5 is respectively connected to the gate electrode of the second thin film transistor T2, the fourth node of the duration adjustment unit 50 and the other end of the first capacitor; the gate electrode of the fourth thin film transistor T4 and the fifth thin film transistor T5 The gates of are respectively connected with the second start signal.

The second writing unit 40 includes a sixth thin film transistor T6; the first electrode of the sixth thin film transistor T6 is connected to the second data voltage, and the second electrode of the sixth thin film transistor T6 is connected to the first node of the duration adjustment unit 50; The gate electrode of the six thin film transistors T6 is connected to the second start signal.

The duration adjustment unit 50 includes a seventh thin film transistor T7, an eighth thin film transistor T8, and a second capacitor; the first electrode of the seventh thin film transistor T7 is connected to the first power supply, the first electrode of the first thin film transistor T1, and the first capacitor respectively. One end is connected, the second pole of the seventh thin film transistor T7 is connected to the first pole of the eighth thin film transistor T8 respectively; the second pole of the eighth thin film transistor T8 is respectively connected to the second pole of the fifth thin film transistor T5 and the second thin film transistor T5. The gate electrode of T2 is connected to the other end of the first capacitor; the gate electrode of the seventh thin film transistor T7 is connected to the second electrode of the sixth thin film transistor T6 and one end of the second capacitor respectively, and the gate electrode of the eighth thin film transistor T8 is connected to the control signal connection; the other end of the second capacitor is connected to one end of each coupling capacitor in the signal selection unit 60 .

Please refer to Figure 1 again. In one embodiment, the pixel circuit further includes a reset unit 70;

The reset unit 70 is used to adjust the voltages of the first node of the driving unit 10 and the first node of the duration adjustment unit 50 to the reference voltage.

The reset unit 70 includes a ninth thin film transistor T9 , a tenth thin film transistor T10 and an eleventh thin film transistor T11 ; the first electrode of the ninth thin film transistor T9 is connected to the input end of the light emitting unit 20 and the second electrode of the third thin film transistor T3 respectively. connection, the second pole of the ninth thin film transistor T9 is respectively connected to the reference voltage, the first pole of the tenth thin film transistor T10 and the first pole of the eleventh thin film transistor T11; the second pole of the tenth thin film transistor T10 is respectively connected to the first pole of the tenth thin film transistor T10. The second electrode of the eighth thin film transistor T8, the second electrode of the fifth thin film transistor T5, the gate electrode of the second thin film transistor T2 and the other end of the first capacitor are connected; the second electrode of the eleventh thin film transistor T11 is connected to the seventh thin film transistor T11 respectively. The gate electrode of the thin film transistor T7, the second electrode of the sixth thin film transistor T6 and one end of the second capacitor are connected; the gate electrode of the ninth thin film transistor T9, the gate electrode of the tenth thin film transistor T10 and the gate of the eleventh thin film transistor T11 The poles are respectively connected to the third start signal.

In the embodiments of the present disclosure, all thin film transistors are P-type transistors, but in other embodiments, they are not limited to the above-mentioned P-type transistors or P-type transistors. It should be noted that for P-type accumulation mode transistors, when the applied V GS is a positive voltage, the device operates in a depletion mode, and the carriers in the conductive channel are depleted, resulting in a high channel resistance. At this time The device is in the off state; when the applied V GS is a negative voltage, the device operates in an accumulation mode, and a large number of carriers are accumulated at the interface between the semiconductor layer and the insulating layer, forming a low-resistance conductive channel. At this time, the device is on.

In the embodiment of the present disclosure, please refer to FIG. 2 , which is a timing diagram disclosed in an embodiment. Based on the pixel circuit in FIG. 1 and the timing in FIG. 2 , the process of realizing the lighting duration control of the light-emitting unit 20 includes:

In the writing and compensation phase t1, the second start signal G(n) inputs a low level. At this time, the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6 are turned on. At this time, due to the fifth thin film transistor The first electrode and the second electrode of T5 are connected to the gate electrode and the second electrode of the second thin film transistor T2 respectively, thus causing the second thin film transistor T2 to be slightly turned on, so that the first data voltage passes through the fourth thin film transistor T4 and the second thin film transistor T2 in sequence. The thin film transistor T2 and the fifth thin film transistor T5 are written to the Q node in the circuit, and because the first electrode and the second electrode of the fifth thin film transistor T5 are respectively connected to the gate electrode and the second electrode of the second thin film transistor T2, Internal circuit compensation occurs, so the internal circuit compensated voltage V th is stored to the Q node in the circuit together with the first data voltage. After the sixth thin film transistor T6 is turned on, the second data voltage passes through the sixth thin film transistor T6 and is written to the g node in the circuit.

Among them, the passing current formula (1):

Wherein, I _ds is the source-drain current of the second thin film transistor T2, V _ds is the source-drain voltage of the second thin film transistor T2, k is the offset voltage temperature coefficient, V _GS is the gate-source voltage of the second thin film transistor T2, V _th is the compensation voltage. Since I _ds =0, it can be concluded that V _GS =V _th . Therefore, V _GS =V _g (Q point voltage) - V _s (first data voltage Data1) = V _th , it can be seen that the Q point voltage is V _s (first data voltage Data1) + V _th .

In the light-emitting phase t2, the second start-up signal G(n) and the third start-up signal G(n-1) input a high level, and the first start-up signal EM inputs a low level. Therefore, the fourth thin film transistor T4 and the fifth thin film transistor T4 The transistor T5 and the sixth thin film transistor T6 are turned off, and the first thin film transistor T1 and the third thin film transistor T3 are turned on. Since the first data voltage and the compensation voltage are written to the node Q in the circuit during the writing and compensation phase t1, the third thin film transistor T3 is turned on during the light emitting phase t2. The first power supply is input to the Micro LED through the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3, so that the Micro LED emits light.

At the same time, the Sweep voltage output by the signal selection unit 60 decreases linearly from a high level, and is pulled down to a low level while the Micro LED continues to emit light. At this time, the Sweep voltage is consistent with the second data voltage written at the g point. Capacitive coupling is formed through the second capacitor, and the capacitive coupling couples the g-point voltage toward a low level over time. Since the control signal is low level in the light-emitting phase t2, the eighth thin film transistor T8 is turned on, and the duration adjustment unit 50 is connected to the driving unit 10. In the light-emitting phase t2, when the g-point voltage is reduced to the threshold voltage of the seventh thin film transistor T7 by the capacitive coupling of the Sweep voltage from the second data voltage, the seventh thin film transistor T7 is turned on, and the Q-point voltage is instantly passed by the first power supply. The seventh thin film transistor T7 is pulled up from the sum of the voltage value of the first data voltage and the compensation voltage to the voltage value of the first power supply. At this time, the second thin film transistor T2 will turn off because the Q point voltage is pulled high, and the Micro LED will stop emitting light because the second thin film transistor T2 is turned off and no current flows through it.

Therefore, after writing the second data voltage to point g and entering the light-emitting phase t2, the seventh thin film transistor T7 is turned on due to the coupling between the Sweep voltage and the second data voltage, so that the duration adjustment unit 50 is connected to the driving unit 10, thereby making The first power supply is coupled with the first data voltage and the compensation voltage to turn off the second thin film transistor T2. Therefore, the time during which the duration adjustment unit 50 is connected to the driving unit 10 can be controlled by controlling the capacitive coupling speed of the Sweep voltage and the second data voltage, thereby controlling the lighting duration of the light-emitting unit 20 .

In one embodiment, please refer to Figures 1 and 2 again, the process of controlling the lighting duration of the light-emitting unit 20 also includes:

In the reset phase t0, the third start signal G(n-1) inputs a low level, and the ninth thin film transistor T9, the tenth thin film transistor T10, and the eleventh thin film transistor T11 are turned on. At this time, the reference voltage passes through the ninth thin film transistor respectively. The transistor T9, the tenth thin film transistor T10, and the eleventh thin film transistor T11 pull the voltage of the Q node, the voltage of the g node, and the voltage of the Micro LED input terminal in the circuit to the value of the reference voltage. This allows the key nodes in the circuit to return to the same voltage reference point at the beginning of each frame before starting data writing, ensuring that the voltage status of important nodes is consistent before each data writing.

In one embodiment, please refer to FIG. 3 , which is a schematic diagram of changes in voltage and current over time disclosed in an embodiment. In the embodiment of the present disclosure, the capacitance value of the capacitor Cc in the signal selection unit 60 is greater than the capacitance value of the capacitor Cb, and the capacitance value of the capacitor Cb is greater than the capacitance value of the capacitor Ca. 3 shows that when the coupling capacitors in the signal selection circuit selected by the signal selection unit 60 are capacitor Ca, capacitor Cb and capacitor Cc, the voltage at point g in the circuit is capacitively coupled with the Sweep signal to achieve the seventh Time variation diagram of the turn-on voltage of thin film transistor T7. FIG. 3 also shows the time variation diagram of the current flowing through the light-emitting unit 20 when the coupling capacitors in the signal selection circuit selected by the signal selection unit 60 are capacitance Ca, capacitance Cb and capacitance Cc respectively. Therefore, combined with FIG. 3 and the relationship between the capacitance values of the capacitance Ca, the capacitance Cb and the capacitance Cc, it can be known that when the coupling capacitance in the signal selection circuit selected by the signal selection unit 60 is larger, the voltage at point g is capacitively coupled to The longer the low level is to turn on the seventh thin film transistor T7, the longer the current can flow to the light-emitting unit 20, that is, the longer the light-emitting time of the light-emitting unit 20 is. Therefore, the signal selected by the signal selection unit 60 The capacitance value of the coupling capacitor in the selection circuit is positively correlated with the time period during which the duration adjustment unit 50 controls the current to flow through the light-emitting unit 20 .

In the embodiment of the present disclosure, please refer to FIG. 1 again. The signal selection unit 60 includes three signal selection circuits. The first signal selection circuit includes a thin film transistor and a coupling capacitor Ca. This thin film transistor is controlled by a turn-on signal. S1 controls on or off; the second signal selection circuit includes a thin film transistor and coupling capacitor Cb, which is controlled on or off by the turn-on signal S2; the third signal selection circuit includes a thin film transistor and coupling capacitor Cc, this thin film transistor is turned on or off controlled by the turn-on signal S3. Wherein, when the turn-on signal is low level, the corresponding thin film transistor is turned on. Therefore, according to the relationship between the capacitance value and the coupling speed of the g-point voltage and the lighting duration of the light-emitting unit 20, the coupling capacitance of the appropriate signal selection circuit can be better selected through each turn-on signal, thereby effectively controlling the lighting duration of the light-emitting unit 20. ground control.

In one embodiment, a display panel is provided, including a plurality of pixel circuits, and the pixel circuits are the pixel circuits described in any of the above embodiments.

In embodiments of the present disclosure, the display panel can be a Micro-LED display panel or an Organic Light-emitting Diode (OLED) display panel, and can be applied to electronic paper, mobile phones, tablets, televisions, monitors, and notebook computers. , digital photo frames, navigators and other products with display functions.

In one embodiment, please refer to FIG. 4 , which is a schematic structural diagram of a display panel disclosed in one embodiment. The display panel 400 includes a display area 410 and an edge area located at the periphery of the display area. The driving unit, the light-emitting unit, the first writing unit, the second writing unit, and the duration adjustment unit are all located in the display area 410. The signal selection unit is disposed in the edge area. .

In some embodiments, the reset unit is also located in the display area 410. Among them, the reset unit is located in the display area, which can better combine the reset stage with the writing and compensation stages and the light-emitting stage.

In one embodiment, please refer to FIG. 4 again, the edge area includes a wiring area 420 and a blank area 430, and the signal selection unit is disposed in the blank area 430. Wherein, each signal selection unit on the blank area corresponds to a pixel circuit. By integrating the signal selection unit added by the conventional pixel circuit into the edge area or even the blank area of the display panel, the cost can be reduced without affecting the wiring of the conventional pixel circuit on the display panel.

It will be understood that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic associated with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. Those skilled in the art should also know that the embodiments described in the specification are optional embodiments, and the actions and units involved are not necessarily necessary for the present disclosure.

In various embodiments of the present disclosure, it should be understood that the size of the sequence numbers of the above-mentioned processes does not necessarily mean the order of execution. The execution order of each process should be determined by its functions and internal logic, and should not be implemented in the present disclosure. The implementation of the examples does not constitute any limitations.

The units described above as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of this embodiment.

In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above integrated units can be implemented in the form of hardware or software functional units.

The above has introduced in detail a pixel circuit and a display panel disclosed in the embodiments of the present disclosure. This article uses specific examples to illustrate the principles and implementations of the present disclosure. The description of the above embodiments is only used to help understand the present disclosure. methods and their core ideas. At the same time, for those of ordinary skill in the art, there will be changes in the specific implementation and application scope based on the ideas of the present disclosure. In summary, the contents of this description should not be understood as limiting the present disclosure.

Industrial applicability

The pixel circuit provided by the present disclosure includes a driving unit, a light emitting unit, a first writing unit, a second writing unit, a duration adjustment unit and a signal selection unit. Wherein, the driving unit is used to drive the light-emitting unit to emit light according to the first power supply; the first writing unit is used to write the first data voltage and the compensation voltage to the first node of the driving unit; the second writing unit, Used to write the second data voltage to the first node of the duration adjustment unit; the signal selection unit is used to select different signal selection circuits to output sweep signals; the duration adjustment unit is used to select the circuit according to the signal selected by the signal selection unit The output sweep signal, the second data voltage, the first power supply, the first data voltage and the compensation voltage control the duration of current flowing through the light-emitting unit. Different driving methods can be selected to improve gray scale loss or poor display in low gray scale situations, and the lighting duration can be controlled, which has strong industrial applicability.

Claims

A pixel circuit including a driving unit, a light-emitting unit, a first writing unit, a second writing unit, a duration adjustment unit and a signal selection unit;

The driving unit is used to drive the light-emitting unit to emit light according to the first power supply;

The first writing unit is used to write the first data voltage and the compensation voltage to the first node of the driving unit;

The second writing unit is used to write a second data voltage to the first node of the duration adjustment unit;

The signal selection unit is used to select different signal selection circuits to output frequency sweep signals;

The duration adjustment unit is used to control the frequency sweep signal output by the signal selection circuit selected by the signal selection unit, the second data voltage, the first power supply, the first data voltage and the compensation voltage. The length of time that current flows through the light-emitting unit.
The circuit according to claim 1, wherein the signal selection unit includes three signal selection circuits, each of the signal selection circuits includes a thin film transistor and a coupling capacitor, and the capacitance value of each of the coupling capacitors is different. ;

The first electrode of each thin film transistor is connected to the frequency sweep signal, the gate electrode of each thin film transistor is connected to a turn-on signal, and the second electrode of each thin film transistor is connected to one end of the corresponding coupling capacitor and The second node connection of the duration adjustment unit;

The other end of each coupling capacitor is connected to the third power supply.
The circuit of claim 2, wherein the driving unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor and a first capacitor;

The first pole of the first thin film transistor is respectively connected to the first power supply, the third node of the duration adjustment unit and one end of the first capacitor, and the second pole of the first thin film transistor is respectively connected to the first power supply, the third node of the duration adjustment unit and one end of the first capacitor. The first node of the first writing unit and the first pole of the second thin film transistor are connected;

The second pole of the second thin film transistor is connected to the first pole of the third thin film transistor and the second node of the first writing unit respectively;

The second electrode of the third thin film transistor is connected to the light-emitting unit;

The gate electrode of the first thin film transistor and the gate electrode of the third thin film transistor are connected to the first start signal, and the gate electrode of the second thin film transistor is respectively connected to the fourth node of the first writing unit and the first writing unit. The third node of the duration adjustment unit is connected to the other end of the first capacitor.
The circuit of claim 3, wherein the first writing unit includes a fourth thin film transistor and a fifth thin film transistor;

The first electrode of the fourth thin film transistor is connected to the first data voltage, and the second electrode of the fourth thin film transistor is connected to the second electrode of the first thin film transistor and the second electrode of the second thin film transistor respectively. One pole connection;

The first electrode of the fifth thin film transistor is respectively connected to the second electrode of the second thin film transistor and the first electrode of the third thin film transistor, and the second electrode of the fifth thin film transistor is respectively connected to the second electrode of the third thin film transistor. The gates of the two thin film transistors, the fourth node of the duration adjustment unit and the other end of the first capacitor are connected;

The gate electrode of the fourth thin film transistor and the gate electrode of the fifth thin film transistor are respectively connected to the second start signal.
The circuit of claim 4, wherein the second writing unit includes a sixth thin film transistor;

The first pole of the sixth thin film transistor is connected to the second data voltage, and the second pole of the sixth thin film transistor is connected to the first node of the duration adjustment unit;

The gate electrode of the sixth thin film transistor is connected to the second start signal.
The circuit of claim 5, wherein the duration adjustment unit includes a seventh thin film transistor, an eighth thin film transistor and a second capacitor;

The first pole of the seventh thin film transistor is respectively connected to the first power supply, the first pole of the first thin film transistor and one end of the first capacitor, and the second pole of the seventh thin film transistor is respectively connected to The first electrode of the eighth thin film transistor is connected;

The second electrode of the eighth thin film transistor is respectively connected to the second electrode of the fifth thin film transistor, the gate electrode of the second thin film transistor, and the other end of the first capacitor;

The gate electrode of the seventh thin film transistor is connected to the second electrode of the sixth thin film transistor and one end of the second capacitor respectively, and the gate electrode of the eighth thin film transistor is connected to the control signal;

The other end of the second capacitor is connected to one end of each coupling capacitor in the signal selection unit.
The circuit of claim 6, wherein the circuit further includes a reset unit;

The reset unit is used to adjust the voltages of the first node of the driving unit and the first node of the duration adjustment unit to a reference voltage.
The circuit of claim 7, wherein the reset unit includes a ninth thin film transistor, a tenth thin film transistor, and an eleventh thin film transistor;

The first pole of the ninth thin film transistor is respectively connected to the input terminal of the light-emitting unit and the second pole of the third thin film transistor, and the second pole of the ninth thin film transistor is respectively connected to the reference voltage and the third thin film transistor. The first electrode of the tenth thin film transistor is connected to the first electrode of the eleventh thin film transistor;

The second electrode of the tenth thin film transistor is connected to the second electrode of the eighth thin film transistor, the second electrode of the fifth thin film transistor, the gate electrode of the second thin film transistor and the first capacitor respectively. Connect the other end;

The second electrode of the eleventh thin film transistor is respectively connected to the gate electrode of the seventh thin film transistor, the second electrode of the sixth thin film transistor, and one end of the second capacitor;

The gate electrode of the ninth thin film transistor, the gate electrode of the tenth thin film transistor, and the gate electrode of the eleventh thin film transistor are respectively connected to the third start signal.
The circuit according to any one of claims 2 to 8, wherein the capacitance value of the coupling capacitor in the signal selection circuit selected by the signal selection unit is proportional to the time period during which the duration adjustment unit controls the current to flow through the light-emitting unit. relationship.
The circuit of claim 8, wherein the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, the sixth thin film transistor, At least one of the thin film transistor, the seventh thin film transistor, the eighth thin film transistor, the ninth thin film transistor, the tenth thin film transistor, and the eleventh thin film transistor is a P-type transistor.
A display panel includes a plurality of pixel circuits, and the pixel circuits are the pixel circuits described in any one of claims 1 to 10.
The display panel according to claim 11, wherein the display panel includes a display area and an edge area located at the periphery of the display area, the driving unit, the light emitting unit, the first writing unit, the second writing unit, The duration adjustment units are all located in the display area, and the signal selection unit is arranged in the edge area.
The display panel according to claim 12, wherein the edge area includes a wiring area and a blank area;

The signal selection unit is arranged in the blank area.
The display panel of claim 12, wherein the pixel circuit further includes a reset unit configured to adjust voltages of the first node of the driving unit and the first node of the duration adjustment unit to Reference voltage, the reset unit is provided in the display area.
The display panel according to any one of claims 11 to 14, wherein the display panel is a micro-light-emitting diode display panel or an organic light-emitting diode display panel.