CN115019722A - Pixel circuit and display panel - Google Patents
Pixel circuit and display panel Download PDFInfo
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- CN115019722A CN115019722A CN202210772534.0A CN202210772534A CN115019722A CN 115019722 A CN115019722 A CN 115019722A CN 202210772534 A CN202210772534 A CN 202210772534A CN 115019722 A CN115019722 A CN 115019722A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
Abstract
The embodiment of the application discloses a pixel circuit and a display panel, wherein the pixel circuit comprises a driving unit, a light-emitting unit, a first writing unit, a second writing unit, a duration adjusting unit and a signal selecting unit; the driving unit is used for driving the light-emitting unit to emit light according to the first power supply; a first write unit for writing a first data voltage and a compensation voltage to a first node of the driving unit; a second writing unit for writing a second data voltage to the first node of the duration adjustment unit; the signal selection unit is used for selecting different signal selection circuits to output sweep frequency signals; and the duration adjusting unit is used for controlling the duration of the current flowing through the light-emitting unit according to the sweep frequency signal, the second data voltage, the first power supply, the first data voltage and the compensation voltage which are output by the signal selection circuit and selected by the signal selection unit. By implementing the embodiment of the application, the light-emitting time can be controlled.
Description
Technical Field
The application relates to the technical field of display, in particular to a pixel circuit and a display panel.
Background
Micro LED display devices have drawn more and more attention because of their advantages such as low driving voltage, long life span, and wide temperature resistance. The Micro LED display is a current-mode driving light emitting display unit, which is different from a liquid crystal voltage-mode driving, and current-mode control requires controlling a passing current of a TFT to control a passing current of a Micro LED. Therefore, in the low gray scale condition, the voltage of the data is relatively small and is modulated within a minimum unit voltage range, the brightness difference of the Micro LED caused by the current difference is not obvious, so that some gray scales cannot be displayed and lost, and the light emitting time length cannot be controlled.
Disclosure of Invention
The embodiment of the application discloses a pixel circuit and a display panel, which can select different driving modes to improve gray scale loss or poor display under the condition of low gray scale and can control the light-emitting duration.
The embodiment of the application discloses a pixel circuit in a first aspect, which comprises a driving unit, a light-emitting unit, a first writing unit, a second writing unit, a duration adjusting unit and a signal selecting unit;
the driving unit is used for driving the light emitting unit to emit light according to a first power supply;
the first writing unit is used for writing a first data voltage and a compensation voltage into a first node of the driving unit;
the second writing unit is used for writing a second data voltage into the first node of the duration adjustment unit;
the signal selection unit is used for selecting different signal selection circuits to output sweep frequency signals;
the duration adjusting unit is configured to control a duration of current flowing through the light emitting unit according to the sweep signal output by the signal selecting circuit selected by the signal selecting unit, the second data voltage, the first power supply, the first data voltage, and the compensation voltage.
As an optional implementation manner, in the first aspect of this embodiment, the signal selection unit includes three signal selection circuits, each signal selection circuit includes a thin film transistor and a coupling capacitor, and capacitance values of the coupling capacitors are different;
the first pole of each thin film transistor is respectively connected with the sweep frequency signal, the grid of each thin film transistor is respectively connected with a starting signal, and the second pole of each thin film transistor is respectively connected with one end of the corresponding coupling capacitor and the second node of the duration adjusting unit;
the other end of each coupling capacitor is connected with the third power supply.
As an optional implementation manner, in the first aspect of this embodiment, the driving unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, and a first capacitor;
a first pole of the first thin film transistor is connected with the first power supply, the third node of the duration adjustment unit and one end of the first capacitor, and a second pole of the first thin film transistor is connected with the first node of the first write-in unit and the first pole of the second thin film transistor;
a second pole of the second thin film transistor is connected with a first pole of the third thin film transistor and a second node of the first writing unit respectively;
a second electrode of the third thin film transistor is connected to the light emitting unit;
the gate of the first thin film transistor and the gate of the third thin film transistor are connected with a first starting signal, and the gate of the second thin film transistor is respectively connected with the fourth node of the first writing unit, the third node of the duration adjusting unit and the other end of the first capacitor.
As an optional implementation manner, in the first aspect of this embodiment, the first writing unit includes a fourth thin film transistor and a fifth thin film transistor;
a first pole of the fourth thin film transistor is connected with the first data voltage, and a second pole of the fourth thin film transistor is respectively connected with the second pole of the first thin film transistor and the first pole of the second thin film transistor;
a first pole of the fifth thin film transistor is connected with a second pole of the second thin film transistor and a first pole of the third thin film transistor respectively, and a second pole of the fifth thin film transistor is connected with a grid electrode of the second thin film transistor, a fourth node of the duration adjusting unit and the other end of the first capacitor respectively;
and the grid electrode of the fourth thin film transistor and the grid electrode of the fifth thin film transistor are respectively connected with a second starting signal.
As an optional implementation manner, in the first aspect of this embodiment, the second writing unit includes a sixth thin film transistor;
a first pole of the sixth thin film transistor is connected to the second data voltage, and a second pole of the sixth thin film transistor is connected to the first node of the duration adjustment unit;
and the grid electrode of the sixth thin film transistor is connected with the second starting signal.
As an optional implementation manner, in the first aspect of this embodiment, the duration adjustment unit includes a seventh thin film transistor, an eighth thin film transistor, and a second capacitor;
a first electrode of the seventh thin film transistor is connected with the first power supply, the first electrode of the first thin film transistor and one end of the first capacitor, and a second electrode of the seventh thin film transistor is connected with the first electrode of the eighth thin film transistor;
a second pole of the eighth thin film transistor is respectively connected with a second pole of the fifth thin film transistor, a grid electrode of the second thin film transistor and the other end of the first capacitor;
the grid electrode of the seventh thin film transistor is respectively connected with the second pole of the sixth thin film transistor and one end of the second capacitor, and the grid electrode of the eighth thin film transistor is connected with a control signal;
the other end of the second capacitor is connected with one end of each coupling capacitor in the signal selection unit.
As an optional implementation manner, in the first aspect of this embodiment, the circuit further includes a reset unit;
the reset unit is used for adjusting the voltage of the first node of the driving unit and the voltage of the first node of the duration adjusting unit to a reference voltage.
As an optional implementation manner, in the first aspect of the present embodiment, the reset unit includes a ninth thin film transistor, a tenth thin film transistor, and an eleventh thin film transistor;
a first electrode of a ninth thin film transistor is connected to the input terminal of the light emitting unit and the second electrode of the third thin film transistor, respectively, and a second electrode of the ninth thin film transistor is connected to the reference voltage, the first electrode of the tenth thin film transistor, and the first electrode of the eleventh thin film transistor, respectively;
a second pole of the tenth thin film transistor is connected with the second pole of the eighth thin film transistor, the second pole of the fifth thin film transistor, the gate of the second thin film transistor and the other end of the first capacitor respectively;
a second pole of the eleventh thin film transistor is respectively connected with a gate of the seventh thin film transistor, a second pole of the sixth thin film transistor and one end of the second capacitor;
and the grid electrode of the ninth thin film transistor, the grid electrode of the tenth thin film transistor and the grid electrode of the eleventh thin film transistor are respectively connected with a third starting signal.
As an optional implementation manner, in the first aspect of this embodiment, the capacitance value of the coupling capacitor in the signal selection circuit selected by the signal selection unit has a positive correlation with the time length for which the time length adjustment unit controls the current to flow through the light emitting unit.
A second aspect of the embodiments of the present application provides a display panel, which includes a plurality of pixel circuits, where the pixel circuits are any one of the pixel circuits disclosed in the embodiments of the present application.
As an optional implementation manner, in the second aspect of this embodiment, the display panel includes a display area and an edge area located at the periphery of the display area, the driving unit, the light emitting unit, the first writing unit, the second writing unit, and the duration adjusting unit are all located in the display area, and the signal selecting unit is disposed in the edge area.
As an optional implementation manner, in the second aspect of this embodiment, the edge area includes a trace area and a blank area;
the signal selection unit is disposed in the blank region.
Compared with the related art, the embodiment of the application has the following beneficial effects:
the pixel circuit comprises a driving unit, a light emitting unit, a first writing unit, a second writing unit, a time length adjusting unit and a signal selecting unit. The driving unit is used for driving the light emitting unit to emit light according to a first power supply; a first write unit for writing a first data voltage and a compensation voltage to a first node of the driving unit; a second writing unit for writing a second data voltage to the first node of the duration adjustment unit; the signal selection unit is used for selecting different signal selection circuits to output sweep frequency signals; and the duration adjusting unit is used for controlling the duration of the current flowing through the light-emitting unit according to the sweep frequency signal, the second data voltage, the first power supply, the first data voltage and the compensation voltage which are output by the signal selection circuit and selected by the signal selection unit. The gray scale loss or poor display under the condition of low gray scale can be improved by selecting different driving modes, and the light-emitting time length can be controlled.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a pixel circuit disclosed in an embodiment of the present application;
fig. 2 is a driving timing diagram of a pixel circuit according to an embodiment of the disclosure;
FIG. 3 is a schematic diagram of voltage and current of a pixel circuit varying with time according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a display panel disclosed in an embodiment of the present application;
wherein the reference numerals are: 10. a drive unit; 20. a light emitting unit; 30. a first writing unit; 40. a second writing unit; 50. a duration adjustment unit; 60. a signal selection unit; 70. a reset unit; t1, a first thin film transistor; t2, a second thin film transistor; t3, a third thin film transistor; t4, a fourth thin film transistor; t5, a fifth thin film transistor; t6, a sixth thin film transistor; t7, a seventh thin film transistor; t8, an eighth thin film transistor; t9, a ninth thin film transistor; t10, tenth thin film transistor; t11, an eleventh thin film transistor; EM, a first start signal; g (n), a second start signal; g (n-1), a third start signal; control, Control signal; data1, a first Data voltage; data2, second Data voltage; c1, a first capacitance; c2, a second capacitor; ca. A coupling capacitor; cb. A coupling capacitor; cc. A coupling capacitor; s1, starting a signal; s2, starting a signal; s3, starting a signal; sweep, Sweep signal; VDD, a first power supply; VSS, third power supply; vref, reference voltage.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It is to be noted that the terms "comprises" and "comprising" and any variations thereof in the examples and figures of the present application are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
The embodiment of the application discloses a pixel circuit and a display panel, which can select different driving modes to improve gray scale loss or poor display under the condition of low gray scale and can control the light-emitting duration. The following are detailed below.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure. As shown in fig. 1, the pixel circuit provided in the embodiment of the present application can be used in a display panel for emitting display light. Specifically, the pixel circuit may include: the driving unit 10, the light emitting unit 20, the first writing unit 30, the second writing unit 40, the time length adjusting unit 50, and the signal selecting unit 60.
A driving unit 10 for driving the light emitting unit 20 to emit light according to a first power;
a first writing unit 30 for writing a first data voltage and a compensation voltage to a first node of the driving unit 10;
a second writing unit 40 for writing a second data voltage to the first node of the duration adjustment unit 50;
a signal selection unit 60, configured to select different signal selection circuits to output sweep signals;
the duration adjustment unit 50 is configured to control a duration of the current flowing through the light emitting unit 20 according to the sweep signal output by the signal selection circuit, the second data voltage, the first power supply, the first data voltage, and the compensation voltage selected by the signal selection unit 60.
In the embodiment of the present application, the Light Emitting unit 20 may be a current-driven Light Emitting device including a Micro LED (Micro Light Emitting Diode) in the prior art, and the Micro LED is taken as an example in the embodiment of the present application for description.
With the above embodiment, the first writing unit 30 writes the first data voltage and the compensation voltage to the Q node in the circuit, wherein the compensation voltage is an internal compensation voltage generated when the gate and the drain of the thin film transistor are connected; the second writing unit 40 writes the second data voltage to the g node in the circuit, so that the driving unit 10 is turned on and outputs a current to the light emitting unit 20 to emit light. Then, after the signal selection unit 60 selects different signal selection circuits to output the sweep frequency signal, the sweep frequency signal is coupled to the second data voltage to turn on the duration adjustment unit 50, and after the duration adjustment unit 50 is turned on, the voltage at the Q point is coupled to the first power supply to turn off the driving unit 10, so that the light emitting unit 20 stops emitting light. In this process, the signal selection unit 60 selects different signal selection circuits to output the sweep signal, which can control the on/off speed of the duration adjustment unit 50, thereby implementing the control of the light-emitting duration of the light-emitting unit 20.
Referring to fig. 1 again, in an embodiment, the signal selecting unit 60 may include three signal selecting circuits, each of which includes a thin film transistor and a coupling capacitor, and the capacitance values of the coupling capacitors are different;
the first pole of each thin film transistor is respectively connected with the sweep frequency signal, the grid of each thin film transistor is respectively connected with a starting signal, and the second pole of each thin film transistor is respectively connected with one end of the corresponding coupling capacitor and the second node of the duration adjusting unit 50;
the other end of each coupling capacitor is connected with a third power supply.
The driving unit 10 includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, and a first capacitor C1; a first electrode of the first thin film transistor T1 is connected to the first power supply, the third node of the duration adjustment unit 50, and one end of the first capacitor, respectively, and a second electrode of the first thin film transistor T1 is connected to the first node of the first write unit 30 and the first electrode of the second thin film transistor T2, respectively; a second pole of the second thin film transistor T2 is connected to a first pole of the third thin film transistor T3 and a second node of the first write unit 30, respectively; a second electrode of the third thin film transistor T3 is connected to the light emitting unit 20; the gate of the first thin film transistor T1 and the gate of the third thin film transistor T3 are connected to the first start signal, and the gate of the second thin film transistor T2 is connected to the fourth node of the first writing unit 30, the third node of the duration adjustment unit 50, and the other end of the first capacitor, respectively.
The first write unit 30 includes a fourth thin film transistor T4 and a fifth thin film transistor T5; a first pole of the fourth thin film transistor T4 is connected to the first data voltage, and a second pole of the fourth thin film transistor T4 is connected to the second pole of the first thin film transistor T1 and the first pole of the second thin film transistor T2, respectively; a first electrode of the fifth thin film transistor T5 is connected to the second electrode of the second thin film transistor T2 and the first electrode of the third thin film transistor T3, respectively, and a second electrode of the fifth thin film transistor T5 is connected to the gate electrode of the second thin film transistor T2, the fourth node of the duration adjustment unit 50, and the other end of the first capacitor, respectively; the gate of the fourth thin film transistor T4 and the gate of the fifth thin film transistor T5 are connected to the second start signal, respectively.
The second writing unit 40 includes a sixth thin film transistor T6; a first pole of the sixth thin film transistor T6 is connected to the second data voltage, and a second pole of the sixth thin film transistor T6 is connected to the first node of the duration adjustment unit 50; the gate of the sixth thin film transistor T6 is connected to the second enable signal.
The duration adjustment unit 50 includes a seventh thin film transistor T7, an eighth thin film transistor T8, and a second capacitor; a first electrode of the seventh thin film transistor T7 is connected to the first power supply, the first electrode of the first thin film transistor T1, and one end of the first capacitor, respectively, and a second electrode of the seventh thin film transistor T7 is connected to the first electrode of the eighth thin film transistor T8, respectively; a second electrode of the eighth thin film transistor T8 is respectively connected to the second electrode of the fifth thin film transistor T5, the gate electrode of the second thin film transistor T2 and the other end of the first capacitor; a gate of the seventh thin film transistor T7 is connected to the second electrode of the sixth thin film transistor T6 and one end of the second capacitor, respectively, and a gate of the eighth thin film transistor T8 is connected to the control signal; the other end of the second capacitor is connected to one end of each coupling capacitor in the signal selection unit 60.
Referring again to fig. 1, in one embodiment, the pixel circuit further includes a reset unit 70;
a reset unit 70 for adjusting the voltages of the first node of the driving unit 10 and the first node of the duration adjustment unit 50 to the reference voltage.
The reset unit 70 includes a ninth thin film transistor T9, a tenth thin film transistor T10, and an eleventh thin film transistor T11; a first electrode of the ninth thin film transistor T9 is respectively connected to the input terminal of the light emitting unit 20 and the second electrode of the third thin film transistor T3, and a second electrode of the ninth thin film transistor T9 is respectively connected to the reference voltage, the first electrode of the tenth thin film transistor T10 and the first electrode of the eleventh thin film transistor T11; a second pole of the tenth thin film transistor T10 is connected to the second pole of the eighth thin film transistor T8, the second pole of the fifth thin film transistor T5, the gate of the second thin film transistor T2, and the other end of the first capacitor, respectively; a second pole of the eleventh thin film transistor T11 is respectively connected to the gate of the seventh thin film transistor T7, the second pole of the sixth thin film transistor T6, and one end of the second capacitor; the gate of the ninth thin film transistor T9, the gate of the tenth thin film transistor T10, and the gate of the eleventh thin film transistor T11 are connected to the third enable signal, respectively.
In the embodiments of the present application, all the tfts are P-type tfts, but in other embodiments, the above-mentioned P-type tfts or P-type tfts are not limited. It should be noted that, for the P-type accumulation mode transistor, when V is added GS For positive voltage, the device works in a depletion mode, carriers of the conduction channel are depleted, a high channel resistance is generated, and the device is in an off state; when V is added GS For negative voltages, the device operates in an accumulation mode, and a large number of carriers are accumulated at the interface of the semiconductor layer and the insulating layer to form a low resistance conduction channel, when the device is in an on state.
In an embodiment of the present application, referring to fig. 2, fig. 2 is a timing chart disclosed in an embodiment, and a process of implementing the control of the light emitting duration of the light emitting unit 20 based on the pixel circuit in fig. 1 and the timing sequence in fig. 2 includes:
in the write and compensation stage T1, the second enable signal g (n) is input with a low level, and the fourth tft T4, the fifth tft T5 and the sixth tft T6 are turned on, and the first data voltage sequentially passes through the fourth tft T4, the second tft T2 and the second tft T4, and the second tft T2 is slightly turned on because the first electrode and the second electrode of the fifth tft T5 are respectively connected to the gate electrode and the second electrode of the second tft T2The thin film transistor T2 and the fifth thin film transistor T5 are written into the Q node of the circuit, and the voltage V compensated by the internal circuit is generated because the first pole and the second pole of the fifth thin film transistor T5 are connected to the gate of the second thin film transistor T2 and the second pole, respectively, for the internal circuit compensation th Is stored to the Q node in the circuit along with the first data voltage. And, after the sixth thin film transistor T6 is turned on, the second data voltage is written to the g node in the circuit through the sixth thin film transistor T6.
Wherein, by current formula (1):
I ds ＝k×[(V GS -V th )V ds -1/2×V ds ^2] (1)
wherein, I ds Is the source drain current, V, of the second TFT T2 ds Is the source-drain voltage of the second TFT T2, k is the offset voltage temperature coefficient, V GS Is the gate-source voltage, V, of the second thin film transistor T2 th To compensate for the voltage. Due to I ds When it is 0, V can be obtained GS ＝V th . Thus V GS Vg (Q-point voltage) -Vs (first Data voltage Data1) ═ Vth, and it can be seen that the Q-point voltage is Vs (first Data voltage Data1) + V th 。
In the light emitting period T2, the second enable signal G (n) and the third enable signal G (n-1) are inputted with a high level, and the first enable signal EM is inputted with a low level, so that the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6 are turned off, and the first thin film transistor T1 and the third thin film transistor T3 are turned on. Since the first data voltage and the compensation voltage are written to the node Q in the circuit during the writing and compensation phase T1, the third tft T3 is turned on during the light emitting phase T2. The first power is input to the micro led through the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3, so that the micro led emits light.
Meanwhile, the Sweep voltage output by the signal selection unit 60 is linearly decreased from a high level and is pulled down to a low level in the process of continuous light emission of the micro led, and at this time, the Sweep voltage and the second data voltage written at the point g form capacitive coupling through a second capacitor, and the capacitive coupling couples the voltage at the point g to a low level direction along with time. Since the control signal is at a low level in the light emitting period T2, the eighth thin film transistor T8 is turned on, and the duration adjustment unit 50 is connected to the driving unit 10. In the light-emitting period T2, when the g-point voltage decreases from the capacitive coupling of the second data voltage with the sweep voltage to the threshold voltage of the seventh tft T7, the seventh tft T7 is turned on, and the Q-point voltage is momentarily pulled up to the voltage value of the first power supply by the first power supply through the seventh tft T7 from the sum of the voltage values of the first data voltage and the compensation voltage. At this time, the second tft T2 is turned off by the voltage at the Q-point being pulled high, and the micro led stops emitting light because the second tft T2 is turned off and no current flows through.
Therefore, after writing the second data voltage into the g point and entering the lighting period T2, the seventh tft T7 is turned on due to the coupling of the Sweep voltage and the second data voltage, so that the duration adjustment unit 50 is connected to the driving unit 10, and the first power source is coupled to the first data voltage and the compensation voltage to turn off the second tft T2. Therefore, the time when the duration adjustment unit 50 is connected to the driving unit 10 can be controlled by controlling the capacitive coupling speed of the Sweep voltage and the second data voltage, thereby controlling the light emitting duration of the light emitting unit 20.
In one embodiment, referring to fig. 1 and fig. 2 again, the process of implementing the light emitting duration control of the light emitting unit 20 further includes:
in the reset period T0, when the third start signal G (n-1) is inputted with a low level, the ninth tft T9, the tenth tft T10 and the eleventh tft T11 are turned on, and the reference voltage passes through the ninth tft T9, the tenth tft T10 and the eleventh tft T11, respectively, so as to pull the voltage of the Q node, the voltage of the G node and the voltage of the micro led input terminal to the values of the reference voltage. Therefore, the key nodes in the circuit can return to the same voltage reference point after each frame starts to start data writing, and the voltage states of the important nodes before each data writing can be ensured to be consistent.
In one embodiment, please refer to fig. 3, fig. 3 is a schematic diagram of voltage and current variation with time according to one embodiment. In the embodiment of the present application, the capacitance of the capacitor Cc in the signal selecting unit 60 is greater than that of the capacitor Cb, and the capacitance of the capacitor Cb is greater than that of the capacitor Ca. Fig. 3 is a time chart showing how the voltage at the point g in the circuit is capacitively coupled with the Sweep frequency signal to reach the turn-on voltage of the seventh tft T7 when the coupling capacitors in the signal selection circuit selected by the signal selection unit 60 are the capacitor Ca, the capacitor Cb, and the capacitor Cc, respectively. Fig. 3 also shows a time variation diagram of the current flowing through the light emitting unit 20 when the coupling capacitances in the signal selection circuit selected by the signal selection unit 60 are the capacitance Ca, the capacitance Cb, and the capacitance Cc, respectively. Therefore, referring to fig. 3 and the relationship among the capacitance values of the capacitor Ca, the capacitor Cb, and the capacitor Cc, it can be known that the larger the coupling capacitance in the signal selection circuit selected by the signal selection unit 60 is, the longer the time for which the voltage at the point g is capacitively coupled to the low level to turn on the seventh thin film transistor T7 is, and the longer the time for which the current can flow to the light emitting unit 20 is, that is, the longer the light emitting time period of the light emitting unit 20 is, so that the capacitance value of the coupling capacitance in the signal selection circuit selected by the signal selection unit 60 has a positive correlation with the time period for which the time period adjustment unit 50 controls the current to flow through the light emitting unit 20.
In the embodiment of the present application, referring to fig. 1 again, the signal selecting unit 60 includes three signal selecting circuits, a first signal selecting circuit includes a thin film transistor and a coupling capacitor Ca, and the thin film transistor is controlled to be turned on or off by the turn-on signal S1; the second signal selection circuit includes a thin film transistor and a coupling capacitor Cb, and the thin film transistor is controlled to be turned on or off by the turn-on signal S2; the third signal selection circuit includes a thin film transistor and a coupling capacitor Cc, and the thin film transistor is controlled to be turned on or off by the turn-on signal S3. When the turn-on signal is at a low level, the corresponding thin film transistor is turned on. Therefore, according to the relationship between the capacitance value and the coupling speed of the g-point voltage and the light emitting duration of the light emitting unit 20, the appropriate coupling capacitance of the signal selection circuit can be better selected by each turn-on signal, so that the light emitting duration of the light emitting unit 20 can be effectively controlled.
In an embodiment, a display panel is provided, which includes a plurality of pixel circuits, and the pixel circuits are the pixel circuits described in any one of the above embodiments.
In the embodiment of the present application, the display panel may be a Micro-light emitting diode (Micro-LED) display panel or an Organic Light Emitting Diode (OLED) display panel, and may be applied to any product with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.
In an embodiment, please refer to fig. 4, wherein fig. 4 is a schematic structural diagram of a display panel according to an embodiment. The display panel 400 includes a display area 410 and an edge area located at the periphery of the display area, the driving unit, the light emitting unit, the first writing unit, the second writing unit, and the duration adjusting unit are all located in the display area 410, and the signal selecting unit is disposed in the edge area.
In some embodiments, the reset unit is also located in the display area 410. The reset unit is positioned in the display area, and can better combine the reset phase with the writing and compensation phase and the light-emitting phase.
In one embodiment, referring to fig. 4 again, the edge area includes a trace area 420 and a blank area 430, and the signal selection unit is disposed in the blank area 430. Wherein, each signal selection unit on the blank area corresponds to one pixel circuit. The signal selection unit added by the conventional pixel circuit is integrated in the edge area or even the blank area of the display panel, so that the cost can be reduced, and the wiring condition of the conventional pixel circuit on the display panel is not influenced.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Those skilled in the art should also appreciate that the embodiments described in the specification are exemplary and alternative embodiments, and that acts and elements referred to are not necessarily required in the application.
In various embodiments of the present application, it should be understood that the size of the serial number of each process described above does not mean that the execution sequence is necessarily sequential, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The pixel circuit and the display panel disclosed in the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are described herein using specific examples, and the above description of the embodiments is only provided to help understand the method and the core idea of the present application. Meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (12)
1. A pixel circuit is characterized by comprising a driving unit, a light-emitting unit, a first writing unit, a second writing unit, a time length adjusting unit and a signal selecting unit;
the driving unit is used for driving the light emitting unit to emit light according to a first power supply;
the first writing unit is used for writing a first data voltage and a compensation voltage into a first node of the driving unit;
the second writing unit is used for writing a second data voltage into the first node of the duration adjustment unit;
the signal selection unit is used for selecting different signal selection circuits to output sweep frequency signals;
the duration adjusting unit is configured to control a duration of current flowing through the light emitting unit according to the sweep signal output by the signal selecting circuit selected by the signal selecting unit, the second data voltage, the first power supply, the first data voltage, and the compensation voltage.
2. The circuit according to claim 1, wherein the signal selection unit comprises three signal selection circuits, each signal selection circuit comprises a thin film transistor and a coupling capacitor, and the capacitance values of the coupling capacitors are different;
the first pole of each thin film transistor is respectively connected with the sweep frequency signal, the grid of each thin film transistor is respectively connected with a starting signal, and the second pole of each thin film transistor is respectively connected with one end of the corresponding coupling capacitor and the second node of the duration adjusting unit;
and the other end of each coupling capacitor is connected with the third power supply.
3. The circuit according to claim 2, wherein the driving unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, and a first capacitor;
a first electrode of the first thin film transistor is connected with the first power supply, the third node of the duration adjustment unit and one end of the first capacitor, and a second electrode of the first thin film transistor is connected with the first node of the first write-in unit and the first electrode of the second thin film transistor;
a second pole of the second thin film transistor is respectively connected with a first pole of the third thin film transistor and a second node of the first writing unit;
a second electrode of the third thin film transistor is connected to the light emitting unit;
the gate of the first thin film transistor and the gate of the third thin film transistor are connected with a first start signal, and the gate of the second thin film transistor is respectively connected with the fourth node of the first writing unit, the third node of the duration adjustment unit and the other end of the first capacitor.
4. The circuit according to claim 3, wherein the first writing unit includes a fourth thin film transistor and a fifth thin film transistor;
a first pole of the fourth thin film transistor is connected with the first data voltage, and a second pole of the fourth thin film transistor is respectively connected with the second pole of the first thin film transistor and the first pole of the second thin film transistor;
a first pole of the fifth thin film transistor is connected with a second pole of the second thin film transistor and a first pole of the third thin film transistor respectively, and a second pole of the fifth thin film transistor is connected with a grid electrode of the second thin film transistor, a fourth node of the duration adjusting unit and the other end of the first capacitor respectively;
and the grid electrode of the fourth thin film transistor and the grid electrode of the fifth thin film transistor are respectively connected with a second starting signal.
5. The circuit according to claim 4, wherein the second writing unit includes a sixth thin film transistor;
a first pole of the sixth thin film transistor is connected with the second data voltage, and a second pole of the sixth thin film transistor is connected with the first node of the duration adjustment unit;
and the grid electrode of the sixth thin film transistor is connected with the second starting signal.
6. The circuit according to claim 5, wherein the duration adjustment unit includes a seventh thin film transistor, an eighth thin film transistor, and a second capacitor;
a first electrode of the seventh thin film transistor is connected with the first power supply, the first electrode of the first thin film transistor and one end of the first capacitor, and a second electrode of the seventh thin film transistor is connected with the first electrode of the eighth thin film transistor;
a second pole of the eighth thin film transistor is respectively connected with a second pole of the fifth thin film transistor, a grid electrode of the second thin film transistor and the other end of the first capacitor;
the grid electrode of the seventh thin film transistor is respectively connected with the second pole of the sixth thin film transistor and one end of the second capacitor, and the grid electrode of the eighth thin film transistor is connected with a control signal;
the other end of the second capacitor is connected with one end of each coupling capacitor in the signal selection unit.
7. The circuit of claim 6, further comprising a reset unit;
the reset unit is used for adjusting the voltage of the first node of the driving unit and the voltage of the first node of the duration adjusting unit to a reference voltage.
8. The circuit according to claim 7, wherein the reset unit includes a ninth thin film transistor, a tenth thin film transistor, and an eleventh thin film transistor;
a first electrode of a ninth thin film transistor is connected to the input terminal of the light emitting unit and the second electrode of the third thin film transistor, respectively, and a second electrode of the ninth thin film transistor is connected to the reference voltage, the first electrode of the tenth thin film transistor, and the first electrode of the eleventh thin film transistor, respectively;
a second pole of the tenth thin film transistor is connected with the second pole of the eighth thin film transistor, the second pole of the fifth thin film transistor, the gate of the second thin film transistor and the other end of the first capacitor respectively;
a second pole of the eleventh thin film transistor is respectively connected with a gate of the seventh thin film transistor, a second pole of the sixth thin film transistor and one end of the second capacitor;
and the grid electrode of the ninth thin film transistor, the grid electrode of the tenth thin film transistor and the grid electrode of the eleventh thin film transistor are respectively connected with a third starting signal.
9. The circuit according to any one of claims 2 to 8, wherein the capacitance value of the coupling capacitor in the signal selection circuit selected by the signal selection unit is in positive correlation with the time period for which the time period adjustment unit controls the current to flow through the light emitting unit.
10. A display panel comprising a plurality of pixel circuits, wherein the pixel circuits are the pixel circuits according to any one of claims 1 to 9.
11. The display panel according to claim 10, wherein the display panel comprises a display region and an edge region located at a periphery of the display region, the driving unit, the light emitting unit, the first writing unit, the second writing unit, and the duration adjusting unit are located in the display region, and the signal selecting unit is disposed in the edge region.
12. The display panel of claim 11, wherein the edge area comprises a trace area and a blank area;
the signal selection unit is disposed in the blank region.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210772534.0A CN115019722A (en) | 2022-06-30 | 2022-06-30 | Pixel circuit and display panel |
| PCT/CN2022/138783 WO2024001065A1 (en) | 2022-06-30 | 2022-12-13 | Pixel circuit and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210772534.0A CN115019722A (en) | 2022-06-30 | 2022-06-30 | Pixel circuit and display panel |
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| Publication Number | Publication Date |
|---|---|
| CN115019722A true CN115019722A (en) | 2022-09-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210772534.0A Pending CN115019722A (en) | 2022-06-30 | 2022-06-30 | Pixel circuit and display panel |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN115019722A (en) |
| WO (1) | WO2024001065A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024001065A1 (en) * | 2022-06-30 | 2024-01-04 | 上海闻泰电子科技有限公司 | Pixel circuit and display panel |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3389039A1 (en) * | 2017-04-13 | 2018-10-17 | Samsung Electronics Co., Ltd. | Display panel and driving method of display panel |
| CN110085161B (en) * | 2018-04-18 | 2020-12-04 | 友达光电股份有限公司 | Display panel and pixel circuit |
| CN111145686B (en) * | 2020-02-28 | 2021-08-17 | 厦门天马微电子有限公司 | Pixel driving circuit, display panel and driving method |
| CN111477163B (en) * | 2020-04-21 | 2021-09-28 | 京东方科技集团股份有限公司 | Pixel driving circuit, driving method thereof and display panel |
| CN114170956A (en) * | 2021-12-09 | 2022-03-11 | 湖北长江新型显示产业创新中心有限公司 | Pixel driving circuit and driving method thereof, display panel and display device |
| CN114120883B (en) * | 2022-01-27 | 2022-05-24 | 深圳晶微峰光电科技有限公司 | Pixel circuit, display device, and display control method for pixel circuit |
| CN114519980A (en) * | 2022-02-21 | 2022-05-20 | Tcl华星光电技术有限公司 | Pixel driving circuit, driving method thereof and display panel |
| CN115019722A (en) * | 2022-06-30 | 2022-09-06 | 上海闻泰电子科技有限公司 | Pixel circuit and display panel |
-
2022
- 2022-06-30 CN CN202210772534.0A patent/CN115019722A/en active Pending
- 2022-12-13 WO PCT/CN2022/138783 patent/WO2024001065A1/en unknown
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024001065A1 (en) * | 2022-06-30 | 2024-01-04 | 上海闻泰电子科技有限公司 | Pixel circuit and display panel |
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| WO2024001065A1 (en) | 2024-01-04 |
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