CN111243514B - Pixel driving circuit, driving method thereof and display panel - Google Patents
Pixel driving circuit, driving method thereof and display panel Download PDFInfo
- Publication number
- CN111243514B CN111243514B CN202010191441.XA CN202010191441A CN111243514B CN 111243514 B CN111243514 B CN 111243514B CN 202010191441 A CN202010191441 A CN 202010191441A CN 111243514 B CN111243514 B CN 111243514B
- Authority
- CN
- China
- Prior art keywords
- unit
- signal
- electrode
- transistor
- control unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Control Of El Displays (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The invention provides a pixel driving circuit, a driving method thereof and a display panel, belongs to the technical field of display, and can at least partially solve the problem that the existing pixel driving circuit cannot realize low-gray-scale display. A pixel driving circuit of the present invention includes: the device comprises a driving unit, a light emitting unit, a storage unit, a writing compensation unit, a current control unit, a duration adjusting unit and a gray scale control unit; a current control unit for controlling the magnitude of the current flowing through the light emitting unit by controlling the driving unit; the gray level control unit is used for controlling the time length of current flowing through the light emitting unit according to signals of the second grid terminal and the second data voltage terminal; and the time length adjusting unit is used for adjusting the time length of current written into the light emitting unit together with the current control unit, and the time of simultaneous conduction of the time length adjusting unit and the current control unit is smaller than the time of independent conduction of the current control unit.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to a pixel driving circuit, a driving method thereof and a display panel.
Background
Compared to Organic Light Emitting Diode (OLED) display devices, micro light emitting diode display devices, such as Micro-LED display devices, have advantages of low driving voltage, long life, wide temperature resistance, and the like, and thus, have been receiving more and more attention.
In a pixel driving circuit of a Micro-LED display device in the prior art, the display gray scale of the display element is controlled by controlling the driving current and the light emitting time length of the display element, the specific light emitting time length is shorter and can display low gray scale, and the light emitting time length is longer and can display high gray scale.
However, since the minimum value of the on-time period of the path in which the driving current is located is certain (e.g., greater than 6.5 μs) in order for the pixel driving circuit to be able to form a normal driving current, the display time period required for the realization of the minimum gray scale is smaller than the minimum on-time period of the path in which the driving current is located, and thus it may be difficult for the pixel driving circuit to realize the display of the low gray scale.
Disclosure of Invention
The invention at least partially solves the problem that the existing pixel driving circuit can not realize low gray scale display, and provides the pixel driving circuit capable of displaying low gray scale.
The technical scheme adopted for solving the technical problem of the invention is a pixel driving circuit, which comprises: the device comprises a driving unit, a light emitting unit, a storage unit, a writing compensation unit, a current control unit, a duration adjusting unit and a gray scale control unit;
the driving unit is used for driving the light-emitting unit to emit light;
the first end of the storage unit is connected with a first voltage end, and the second end of the storage unit is connected with a first node;
the write compensation unit is used for writing data signals and compensation data of a data line end into the driving unit through adjustment of the storage unit;
the current control unit is used for controlling the current flowing through the light-emitting unit by controlling the driving unit;
the gray level control unit is used for controlling the duration of the current flowing through the light emitting unit according to the signals of the second grid terminal and the second data voltage terminal;
the time length adjusting unit is used for adjusting the time length of writing the current into the light-emitting unit together with the current control unit, and the time of conducting the time length adjusting unit and the current control unit simultaneously is smaller than the time of conducting the current control unit singly.
The time length adjusting unit includes: and the grid electrode of the first transistor is connected with the second signal end.
It is further preferred that the write compensation unit includes: a second transistor, the gate of which is connected with the first gate terminal, the first electrode is connected with the first node, and the second electrode is connected with the second node; and the grid electrode of the third transistor is connected with the first grid electrode end, the first electrode is connected with the third node, and the second electrode is connected with the first data voltage end.
It is further preferred that the driving unit includes: and the grid electrode of the fourth transistor is connected with the first node, the first electrode of the fourth transistor is connected with the third node, and the second electrode of the fourth transistor is connected with the second node.
It is further preferable that the current control unit includes: a fifth transistor, the gate of which is connected with the first signal terminal, the first electrode is connected with the first voltage terminal, and the second electrode is connected with the third node; and the grid electrode of the sixth transistor is connected with the first signal end, the first electrode of the sixth transistor is connected with the second node, and the second electrode of the sixth transistor is connected with the first electrode of the first transistor.
It is further preferred that the storage unit includes: and the first electrode of the first capacitor is connected with the first voltage end, and the second electrode of the first capacitor is connected with the first node.
Further preferably, the gray-scale control unit includes: a seventh transistor having a gate connected to the second gate terminal, a first electrode connected to the second data voltage terminal, and a first electrode connected to the fourth node; the first electrode of the second capacitor is connected with the fourth node, and the second electrode of the second capacitor is connected with the third voltage end; and the grid electrode of the eighth transistor is connected with the fourth node, the first electrode of the eighth transistor is connected with the second electrode of the first transistor, and the second electrode of the eighth transistor is connected with the light-emitting unit.
It is further preferable that the pixel driving circuit further includes: and the reset unit is used for adjusting the voltage of the first node by the signals of the second voltage end and the reset end, and comprises a ninth transistor, wherein the grid electrode of the ninth transistor is connected with the reset end, the first electrode of the ninth transistor is connected with the first node, and the first electrode of the ninth transistor is connected with the second voltage end.
It is further preferable that the light emitting unit is a micro light emitting diode.
The technical scheme adopted for solving the technical problem of the invention is a pixel driving method based on the pixel driving circuit, and the pixel driving method comprises the following steps:
in the data writing stage, the writing compensation unit writes data signals and compensation data of a data line end to the driving unit through adjustment of the storage unit;
in the display stage, the current control unit controls the current flowing through the light emitting unit by controlling the driving unit, the gray scale control unit controls the time length of the current flowing through the light emitting unit according to the signals of the second grid terminal and the second data voltage terminal, the time length adjusting unit and the current control unit jointly adjust the time length of the current written into the light emitting unit, and the time length adjusting unit and the current control unit are conducted simultaneously is smaller than the time length of the current control unit conducted independently.
Further preferably, the pixel driving circuit is the above pixel driving circuit, and the pixel driving method specifically includes: a reset stage of inputting a reset signal to the second voltage terminal, inputting a turn-on signal to the reset terminal, and inputting turn-off signals to the first gate terminal, the second gate terminal, the first signal terminal, and the second signal terminal; a data writing stage, in which a data signal is input to the first data voltage terminal, a conduction signal is input to the first gate terminal, and a turn-off signal is input to the reset terminal, the second gate terminal, the first signal terminal and the second signal terminal; the display stage comprises at least one sub-display stage, each sub-display stage comprises a control stage and a light-emitting stage, in the control stage, a control signal is input to the second data voltage end, a conduction signal is input to the second gate end, a turn-off signal is input to the reset end, the first gate end, the first signal end and the second signal end, in the light-emitting stage, a display signal is input to the first voltage end, a conduction signal is input to the first signal end and the second signal end, and a turn-off signal is input to the reset end, the first gate end and the second gate end, wherein the conduction time of the first signal end is earlier than that of the second signal end.
The technical scheme adopted for solving the technical problem of the invention is that the display panel comprises a plurality of pixel driving circuits, wherein the pixel driving circuits are the pixel driving circuits.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the description serve to explain, without limitation, the invention. In the drawings:
fig. 1 is a schematic diagram of a pixel driving circuit according to an embodiment of the invention;
FIG. 2 is a timing diagram illustrating the operation of the pixel driving circuit shown in FIG. 1 with high gray scale;
FIG. 3 is a timing diagram illustrating a low gray scale operation of the pixel driving circuit shown in FIG. 1;
fig. 4 is a schematic circuit diagram of a circuit structure for providing a signal to a first signal terminal or a second signal terminal in a pixel driving circuit according to an embodiment of the invention;
fig. 5 is a schematic circuit diagram of a circuit structure for providing a signal to a first signal terminal or a second signal terminal in a pixel driving circuit according to an embodiment of the invention;
wherein, the reference numerals are as follows: 1. a driving unit; 2. a light emitting unit; 3. a storage unit; 4. a write compensation unit; 5. a current control unit; 6. a duration adjusting unit; 7. a gray-scale control unit; 8. a reset unit; VDD, a first voltage terminal; vinit, second voltage terminal; VCOM, the third voltage terminal; VSS, fourth voltage terminal; an EM and a first signal terminal; EM', second signal terminal; gate a, first gate terminal; gate b, second gate terminal; vdatai, the first data voltage terminal; vdatat, the second data voltage terminal; RST, reset end; t1, a first transistor; t2, a second transistor; t3, third transistor; t4, fourth transistor; t5, fifth transistor; t6, sixth transistor; t7, seventh transistor; t8, eighth transistor; t9, ninth transistor; n1, a first node; n2, a second node; n3, a third node; n4, a fourth node; c1, a first capacitor; c2, a second capacitor; t1, a reset stage; t2, a data writing stage; t3, a display stage; a. a control stage; b. and a light emitting stage.
Detailed Description
The present invention will be described in further detail below with reference to the drawings and detailed description for the purpose of better understanding of the technical solution of the present invention to those skilled in the art.
The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown in the drawings.
Numerous specific details of the invention, such as construction, materials, dimensions, processing techniques and technologies, may be set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Example 1:
as shown in fig. 1 to 3, the present embodiment provides a pixel driving circuit including: a driving unit 1, a light emitting unit 2, a storage unit 3, a writing compensation unit 4, a current control unit 5, a duration adjustment unit 6, and a gray scale control unit 7;
a driving unit 1 for driving the light emitting unit 2 to emit light;
the first end of the memory cell 3 is connected to the first voltage end VDD, and the second end thereof is connected to the first node N1;
a write compensation unit 4 for writing a data signal of a data line end and compensation data to the driving unit 1 by adjustment of the storage unit 3;
a current control unit 5 for controlling the magnitude of the current flowing through the light emitting unit 2 by controlling the driving unit 1;
a gray-scale control unit 7 for controlling a period of time during which a current flows through the light emitting unit 2 according to signals of the second gate terminal GateB and the second data voltage terminal Vdatat;
and the duration adjusting unit 6 is used for adjusting the duration of current written into the light emitting unit 2 together with the current control unit 5, and the time that the duration adjusting unit 6 is conducted simultaneously with the current control unit 5 is smaller than the time that the current control unit 5 is conducted independently.
Further, the light emitting unit 2 in the present embodiment may be a current driven light emitting device including a Micro-LED (Micro Light Emitting Diode ) or an OLED (Organic Light Emitting Diode, organic light emitting diode) in the related art, and is described taking the Micro-LED as an example in the present embodiment.
Note that, the light emitting efficiency of the Micro-LED display device may decrease with decreasing current density at low current density, and the color coordinates may change with a change in current density. Therefore, the Micro-LED display device needs to realize gray scale display under high current density, namely, high current. In a pixel driving circuit of a Micro-LED display device in the prior art, the display gray scale of the display element is controlled by controlling the driving current and the light emitting time length of the display element, the specific light emitting time length is shorter and can display low gray scale, and the light emitting time length is longer and can display high gray scale. However, since the minimum of the on-time of the path in which the driving current is located is certain (e.g., greater than 6.5 μs) in order for the pixel driving circuit to be able to form a normal driving current, the display time required for the realization of the minimum gray scale is smaller than the minimum of the on-time of the path in which the driving current is located, and thus it may be difficult for the pixel driving circuit to realize the display of the low gray scale.
In the pixel driving circuit of the embodiment, the minimum light emitting duration can be further shortened under the premise of ensuring the normal current through the combined action of the duration adjusting unit 6 and the current control unit 5, so that the display of low gray scale is ensured, and the performance of the pixel driving circuit is further ensured.
Specifically, the time length adjustment unit 6 includes: the gate of the first transistor T1 is connected to the second signal terminal EM'.
The write compensation unit 4 includes: a second transistor T2 having a gate connected to the first gate terminal GateA, a first electrode connected to the first node N1, and a second electrode connected to the second node N2; the third transistor T3 has a gate connected to the first gate terminal GateA, a first pole connected to the third node N3, and a second pole connected to the first data voltage terminal Vdatai.
The drive unit 1 includes: the gate of the fourth transistor T4 is connected to the first node N1, the first pole is connected to the third node N3, and the second pole is connected to the second node N2.
The current control unit 5 includes: a fifth transistor T5 having a gate connected to the first signal terminal EM, a first pole connected to the first voltage terminal VDD, and a second pole connected to the third node N3; the gate of the sixth transistor T6 is connected to the first signal terminal EM, the first pole is connected to the second node N2, and the second pole is connected to the first pole of the first transistor T1.
The storage unit 3 includes: the first capacitor C1 has a first pole connected to the first voltage terminal VDD, and a second pole connected to the first node N1.
The gradation control unit 7 includes: a seventh transistor T7 having a gate connected to the second gate terminal GateB, a first electrode connected to the second data voltage terminal Vdatat, and a first electrode connected to the fourth node N4; a first pole of the second capacitor C2 is connected to the fourth node N4, and a second pole is connected to the third voltage end VCOM; the eighth transistor T8 has a gate connected to the fourth node N4, a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the light emitting unit 2.
The pixel driving circuit of the present embodiment further includes: the reset unit 8 is configured to adjust the voltage of the first node N1 by using signals of the second voltage terminal Vinit and the reset terminal RST, and the reset unit 8 includes a ninth transistor T9, where a gate thereof is connected to the reset terminal RST, a first pole thereof is connected to the first node N1, and a first pole thereof is connected to the second voltage terminal Vinit.
Preferably, all transistors are N-type transistors; alternatively, all transistors are P-type transistors.
Example 2:
as shown in fig. 1 to 3, the present embodiment provides a pixel driving method, based on the pixel driving circuit of embodiment 1, the pixel driving method including:
in the data writing stage t2, the write compensation unit 4 writes the data signal and the compensation data at the data line end to the drive unit 1 by the adjustment of the storage unit 3;
in the display stage t3, the current control unit 5 controls the magnitude of the current flowing through the light emitting unit 2 by controlling the driving unit 1, the gray scale control unit 7 controls the duration of the current flowing through the light emitting unit 2 according to the signals of the second gate terminal GateB and the second data voltage terminal Vdatat, the duration adjusting unit 6 and the current control unit 5 jointly adjust the duration of the current written into the light emitting unit 2, and the time of the simultaneous conduction of the duration adjusting unit 6 and the current control unit 5 is smaller than the time of the separate conduction of the current control unit 5.
Specifically, in the method, the first voltage terminal VDD is used to provide a working voltage, and the fourth voltage terminal VSS is used to provide a reference voltage; the method specifically comprises the following steps:
s11, in the reset stage t1, a reset signal is input to the second voltage terminal Vinit, a conduction signal is input to the reset terminal RST, and a turn-off signal is input to the first gate terminal GateA, the second gate terminal GateB, the first signal terminal EM and the second signal terminal EM'.
The on signal refers to a signal that turns on the transistor when the transistor is loaded on the gate of the transistor, and the off signal refers to a signal that turns off the transistor when the transistor is loaded on the gate of the transistor.
It should be noted that, in the following description, all transistors are P-type transistors, so that the on signal is a low level signal and the off signal is a high level signal.
As shown in fig. 1 to 3, in this stage, that is, a high level is input to the first gate terminal GateA, so that the second transistor T2 and the third transistor T3 are turned off; inputting a high level to the second gate terminal GateB so that the seventh transistor T7 is turned off; inputting a high level to the first signal terminal EM such that the fifth transistor T5 and the sixth transistor T6 are turned off; a high level is input to the second signal terminal EM' such that the first transistor T1 is turned off. The reset terminal RST is inputted with a low level, and the ninth transistor T9 is turned on, so that the voltage of the second voltage terminal Vinit is written into the first node N1, and further, the initialization signal is written into the first capacitor C1.
S12, in the data writing stage t2, a data signal is input to the first data voltage terminal Vdatai, a conduction signal is input to the first gate terminal GateA, and a turn-off signal is input to the reset terminal RST, the second gate terminal GateB, the first signal terminal EM and the second signal terminal EM'.
As shown in fig. 1 to 3, in this stage, that is, a high level is input to the reset terminal RST, so that the ninth transistor T9 is turned off; inputting a high level to the second gate terminal GateB so that the seventh transistor T7 is turned off; inputting a high level to the first signal terminal EM such that the fifth transistor T5 and the sixth transistor T6 are turned off; a high level is input to the second signal terminal EM' such that the first transistor T1 is turned off. Inputting a low level to the first gate terminal GateA, and turning on the second transistor T2 and the third transistor T3; the fourth transistor T4 is turned on due to the signal of the first capacitor C1 of the upper stage. Thus, the data signal of the first data voltage terminal Vdatai is written into the first node N1 through the third transistor T3, the fourth transistor T4, and the second transistor T2 in sequence, and the compensation data is also written into the first node N1, i.e. stored in the first capacitor C1.
S13, a display stage t3, which comprises at least one sub-display stage, wherein each sub-display stage comprises a control stage a and a light-emitting stage b, in the control stage a, a control signal is input to a second data voltage terminal Vdatat, a conduction signal is input to a second gate terminal GateB, a reset terminal RST, a first gate terminal GateA, a first signal terminal EM and a second signal terminal EM ' are input to turn-off signals, in the light-emitting stage b, a display signal is input to a first voltage terminal VDD, a conduction signal is input to the first signal terminal EM and the second signal terminal EM ', and a turn-off signal is input to the reset terminal RST, the first gate terminal GateA and the second gate terminal GateB, wherein the conduction time of the first signal terminal EM is earlier than that of the second signal terminal EM '.
As shown in fig. 1 to 3, the display stage t3 may include a plurality of sub-display stages, and 3 sub-display stages are illustrated in fig. 2 and 3 as an example. Each sub-display stage comprises a control stage a and a lighting stage b, such that the display stage t3 comprising a plurality of sub-display stages is actually a spaced distribution of a plurality of control stages a and lighting stages b.
Specifically, in the control phase a of each sub-display phase, a high level is input to the reset terminal RST, so that the ninth transistor T9 is turned off; inputting a high level to the first gate terminal GateA so that the second transistor T2 and the third transistor T3 are turned off; inputting a high level to the first signal terminal EM such that the fifth transistor T5 and the sixth transistor T6 are turned off; a high level is input to the second signal terminal EM' such that the first transistor T1 is turned off. The low level is input to the second data voltage terminal Vdatat, and the seventh transistor T7 is turned on, so that the control signal of the second data voltage terminal Vdatat is written into the fourth node N4 and stored in the second capacitor C2.
In the light emitting stage b of each sub-display stage, first, a high level is input to the reset terminal RST so that the ninth transistor T9 is turned off; inputting a high level to the first gate terminal GateA so that the second transistor T2 and the third transistor T3 are turned off; inputting a high level to the second gate terminal GateB so that the seventh transistor T7 is turned off; inputting a high level to the second signal terminal EM' such that the first transistor T1 is turned off; the first signal terminal EM is inputted with a low level, and the fifth transistor T5 and the sixth transistor T6 are turned on. Secondly, the reset terminal RST, the first gate terminal GateA, the second gate terminal GateB, and the first signal terminal EM remain unchanged, and a low level is input to the second signal terminal EM', so that the first transistor T1 is turned on, and because the fourth transistor T4 is turned on under the action of the first capacitor C1, a current sequentially passes through the fifth transistor T5, the fourth transistor T4, the sixth transistor T6, and the first transistor T1 and is written into the light emitting unit 2, so that the light emitting unit 2 displays normally.
The display process is equivalent to that the second signal end EM 'inputs the conducting signal in a delayed manner compared with the first signal end EM, and when the conducting signal is input by both the second signal end EM' and the first signal end EM, the current can be input to the light emitting unit 2, so that the light emitting time of the light emitting unit 2 is the time when the second signal end EM 'and the first signal end EM are simultaneously conducted, and the light emitting time can be adjusted by controlling the time of the conducting signal input of the second signal end EM'.
Specifically, when the input duration of the on signal of the second signal terminal EM ' is fixed, the shorter the input delay of the on-limit number of the second signal terminal EM ' is, the longer the light emitting time is, and the shorter the input delay of the on-limit number of the second signal terminal EM ' is, the shorter the light emitting time is.
In fig. 2, the second signal end EM' and the first signal end EM have the same on time, so that the light emitting time is relatively long, and the method is suitable for displaying high gray scale; in fig. 3, the second signal terminal EM' is delayed from the first signal terminal EM by the input on signal, and the actual light emitting time is shown by eland, so that the light emitting time is shortened, and the display device is suitable for displaying low gray scale.
In summary, in the pixel driving method of the present embodiment, the second signal terminal EM' delays the input on signal compared with the first signal terminal EM, so that the minimum light emitting duration is further shortened on the premise of ensuring the normal current, thereby ensuring the display of low gray scale and further ensuring the performance of the pixel driving circuit.
Example 3:
the present embodiment provides a display panel, including a plurality of pixel driving circuits, where the pixel driving circuits are the above-mentioned pixel driving circuits.
The display panel of the present embodiment further includes: the gray scale judging module (PAM or PWM) and the luminous time length judging module (ESTV) are used for judging the gray scale to be displayed by the pixel corresponding to each pixel driving circuit, and the luminous time length judging module is used for obtaining the required luminous time length according to the gray scale to be displayed by each pixel and calculating the delay time of the second signal end EM' relative to the first signal end EM.
That is, before steps S11 to S13 of embodiment 2, first, the gray scale to be displayed by the pixel corresponding to each pixel driving circuit is determined, and second, the delay time of the second signal end EM' relative to the first signal end EM is calculated according to the light emitting duration required by the gray scale to be displayed by each pixel.
In addition, the circuit configuration for supplying the first signal terminal EM and the second signal terminal EM' may be a shift register circuit as shown in fig. 4 and 5, or may be other suitable circuit configuration. In fig. 4 and 5, M1, M2, M3, M4, M5, M6, M7, M8 respectively denote transistors, p1, p2, p3 respectively denote capacitances, GCL, VGL, CK, CB, VGL, VGH, GCB, GCK, GSTV, ESTV, VL, VH respectively denote control terminals or signal terminals, and Gate Ouput denotes a port for supplying a signal to the first signal terminal EM or the second signal terminal EM'.
Specifically, the display panel may be any product or component with a display function, such as a Micro light emitting diode (Micro-LED) display panel, an Organic Light Emitting Diode (OLED) display panel, electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (11)
1. A pixel driving circuit, comprising: the device comprises a driving unit, a light emitting unit, a storage unit, a writing compensation unit, a current control unit, a duration adjusting unit and a gray scale control unit; the light-emitting unit is a Micro light-emitting diode Micro-LED;
the driving unit is used for driving the light-emitting unit to emit light;
the first end of the storage unit is connected with a first voltage end, and the second end of the storage unit is connected with a first node;
the write compensation unit is used for writing data signals and compensation data of a data line end into the driving unit through adjustment of the storage unit;
the current control unit is used for controlling the current flowing through the light-emitting unit by controlling the driving unit;
the gray level control unit is used for controlling the duration of the current flowing through the light emitting unit according to signals of the second grid terminal and the second data voltage terminal;
the time length adjusting unit is configured to adjust, together with the current control unit, a time length when the current is written into the light emitting unit, where the time length adjusting unit and the current control unit are simultaneously turned on is less than a time length when the current control unit is separately turned on, and the time length adjusting unit includes: the grid electrode of the first transistor is connected with the second signal end;
the time length adjusting unit and the current control unit jointly adjust the time length of writing the current into the light-emitting unit when the light-emitting unit displays a first gray level, and the time length adjusting unit and the current control unit jointly adjust the time length of writing the current into the light-emitting unit when the light-emitting unit displays a second gray level, wherein the first gray level is larger than the second gray level;
when the light-emitting unit displays the second gray level, the duration adjusting unit and the current control unit jointly adjust the duration of writing the current into the light-emitting unit to be smaller than the duration of independent conduction of the current control unit; the second gray level includes a minimum gray level.
2. The pixel driving circuit according to claim 1, wherein the write compensation unit includes:
a second transistor, the gate of which is connected with the first gate terminal, the first electrode is connected with the first node, and the second electrode is connected with the second node;
and the grid electrode of the third transistor is connected with the first grid electrode end, the first electrode is connected with the third node, and the second electrode is connected with the first data voltage end.
3. The pixel driving circuit according to claim 2, wherein the driving unit includes: and the grid electrode of the fourth transistor is connected with the first node, the first electrode of the fourth transistor is connected with the third node, and the second electrode of the fourth transistor is connected with the second node.
4. A pixel driving circuit according to claim 3, wherein the current control unit comprises:
a fifth transistor, the gate of which is connected with the first signal terminal, the first electrode is connected with the first voltage terminal, and the second electrode is connected with the third node;
and the grid electrode of the sixth transistor is connected with the first signal end, the first electrode of the sixth transistor is connected with the second node, and the second electrode of the sixth transistor is connected with the first electrode of the first transistor.
5. The pixel driving circuit according to claim 4, wherein the storage unit includes: and the first electrode of the first capacitor is connected with the first voltage end, and the second electrode of the first capacitor is connected with the first node.
6. The pixel driving circuit according to claim 5, wherein the gray-scale control unit includes:
a seventh transistor having a gate connected to the second gate terminal, a first electrode connected to the second data voltage terminal, and a first electrode connected to the fourth node;
the first electrode of the second capacitor is connected with the fourth node, and the second electrode of the second capacitor is connected with the third voltage end;
and the grid electrode of the eighth transistor is connected with the fourth node, the first electrode of the eighth transistor is connected with the second electrode of the first transistor, and the second electrode of the eighth transistor is connected with the light-emitting unit.
7. The pixel driving circuit according to claim 6, further comprising: and the reset unit is used for adjusting the voltage of the first node by the signals of the second voltage end and the reset end, and comprises a ninth transistor, wherein the grid electrode of the ninth transistor is connected with the reset end, the first electrode of the ninth transistor is connected with the first node, and the first electrode of the ninth transistor is connected with the second voltage end.
8. The pixel driving circuit according to claim 1, wherein the light emitting unit is a micro light emitting diode.
9. A pixel driving method, characterized in that based on the pixel driving circuit according to any one of claims 1 to 8, the pixel driving method comprises:
in the data writing stage, the writing compensation unit writes data signals and compensation data of a data line end to the driving unit through adjustment of the storage unit;
in a display stage, the current control unit controls the current flowing through the light emitting unit by controlling the driving unit, the gray scale control unit controls the time length of the current flowing through the light emitting unit according to the signals of the second grid terminal and the second data voltage terminal, the time length adjusting unit and the current control unit jointly adjust the time length of the current written into the light emitting unit, and the time length adjusting unit and the current control unit are simultaneously conducted is smaller than the time length of the current control unit conducted independently;
the light-emitting unit is a Micro light-emitting diode Micro-LED; the time length adjusting unit and the current control unit jointly adjust the time length of writing the current into the light-emitting unit when the light-emitting unit displays a first gray level, and the time length adjusting unit and the current control unit jointly adjust the time length of writing the current into the light-emitting unit when the light-emitting unit displays a second gray level, wherein the first gray level is larger than the second gray level; when the light-emitting unit displays the second gray level, the duration adjusting unit and the current control unit jointly adjust the duration of writing the current into the light-emitting unit to be smaller than the duration of independent conduction of the current control unit; the second gray level includes a minimum gray level.
10. The pixel driving method according to claim 9, wherein the pixel driving circuit is the pixel driving circuit according to claim 8, and the pixel driving method specifically comprises:
a reset stage of inputting a reset signal to the second voltage terminal, inputting a turn-on signal to the reset terminal, and inputting turn-off signals to the first gate terminal, the second gate terminal, the first signal terminal, and the second signal terminal;
a data writing stage, in which a data signal is input to the first data voltage terminal, a conduction signal is input to the first gate terminal, and a turn-off signal is input to the reset terminal, the second gate terminal, the first signal terminal and the second signal terminal;
the display stage comprises at least one sub-display stage, each sub-display stage comprises a control stage and a light-emitting stage, in the control stage, a control signal is input to the second data voltage end, a conduction signal is input to the second gate end, a turn-off signal is input to the reset end, the first gate end, the first signal end and the second signal end, in the light-emitting stage, a display signal is input to the first voltage end, a conduction signal is input to the first signal end and the second signal end, and a turn-off signal is input to the reset end, the first gate end and the second gate end, wherein the conduction time of the first signal end is earlier than that of the second signal end.
11. A display panel comprising a plurality of pixel driving circuits, the pixel driving circuits being the pixel driving circuits according to any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010191441.XA CN111243514B (en) | 2020-03-18 | 2020-03-18 | Pixel driving circuit, driving method thereof and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010191441.XA CN111243514B (en) | 2020-03-18 | 2020-03-18 | Pixel driving circuit, driving method thereof and display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111243514A CN111243514A (en) | 2020-06-05 |
| CN111243514B true CN111243514B (en) | 2023-07-28 |
Family
ID=70865138
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010191441.XA Active CN111243514B (en) | 2020-03-18 | 2020-03-18 | Pixel driving circuit, driving method thereof and display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111243514B (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111785201B (en) * | 2020-07-02 | 2021-09-24 | 深圳市华星光电半导体显示技术有限公司 | Pixel driving circuit and driving method thereof, display panel and display device |
| WO2022059933A1 (en) * | 2020-09-17 | 2022-03-24 | 삼성전자주식회사 | Display module |
| CN114792511B (en) * | 2021-01-26 | 2023-10-24 | 京东方科技集团股份有限公司 | Pixel driving circuit, driving control method and display panel |
| CN113990243B (en) * | 2021-11-04 | 2023-01-24 | 京东方科技集团股份有限公司 | Pixel circuit and driving method thereof, display device and display driving method |
| CN113889039B (en) * | 2021-11-18 | 2023-06-13 | 京东方科技集团股份有限公司 | Pixel circuit, driving method thereof, display substrate and display device |
| TW202329259A (en) * | 2021-12-16 | 2023-07-16 | 日商半導體能源研究所股份有限公司 | Display device and electronic apparatus |
| CN114241980A (en) * | 2021-12-17 | 2022-03-25 | 重庆惠科金渝光电科技有限公司 | Drive chip, control method and display panel |
| CN114299870A (en) * | 2022-02-14 | 2022-04-08 | Tcl华星光电技术有限公司 | Drive circuit and display panel |
| CN114530120B (en) * | 2022-03-15 | 2023-06-02 | Tcl华星光电技术有限公司 | Pixel circuit, pixel driving method and display device |
| CN114927089B (en) * | 2022-05-20 | 2024-03-05 | 京东方科技集团股份有限公司 | Driving circuit, display panel and electronic equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110010057A (en) * | 2019-04-25 | 2019-07-12 | 京东方科技集团股份有限公司 | Pixel-driving circuit, image element driving method and display device |
| CN110459169A (en) * | 2019-08-23 | 2019-11-15 | 云谷（固安）科技有限公司 | A kind of digital drive pixel circuit and its driving method and display panel |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20150101505A (en) * | 2014-02-26 | 2015-09-04 | 삼성디스플레이 주식회사 | Organic light emitting device and method for driving the same |
| CN108538241A (en) * | 2018-06-29 | 2018-09-14 | 京东方科技集团股份有限公司 | Pixel circuit and its driving method, display device |
| CN110021263B (en) * | 2018-07-05 | 2020-12-22 | 京东方科技集团股份有限公司 | Pixel circuit, driving method thereof and display panel |
| CN109872680B (en) * | 2019-03-20 | 2020-11-24 | 京东方科技集团股份有限公司 | Pixel circuit, driving method, display panel, driving method and display device |
| CN109817159B (en) * | 2019-03-29 | 2021-07-20 | 昆山国显光电有限公司 | Pixel driving circuit and display device |
| CN110047436B (en) * | 2019-06-06 | 2021-11-23 | 京东方科技集团股份有限公司 | Pixel circuit, array substrate, driving method of array substrate, display panel and display device |
| CN110491335A (en) * | 2019-09-03 | 2019-11-22 | 京东方科技集团股份有限公司 | A kind of driving circuit and its driving method, display device |
-
2020
- 2020-03-18 CN CN202010191441.XA patent/CN111243514B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110010057A (en) * | 2019-04-25 | 2019-07-12 | 京东方科技集团股份有限公司 | Pixel-driving circuit, image element driving method and display device |
| CN110459169A (en) * | 2019-08-23 | 2019-11-15 | 云谷（固安）科技有限公司 | A kind of digital drive pixel circuit and its driving method and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111243514A (en) | 2020-06-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111243514B (en) | Pixel driving circuit, driving method thereof and display panel | |
| CN111243650B (en) | Shifting register, driving method thereof and grid driving circuit | |
| CN112513963B (en) | Display panel and display device | |
| CN110268465B (en) | Pixel circuit, display panel and driving method of pixel circuit | |
| KR101857808B1 (en) | Scan Driver and Organic Light Emitting Display Device using thereof | |
| WO2018129932A1 (en) | Shift register unit circuit and drive method therefor, gate drive circuit, and display device | |
| US20180286313A1 (en) | Pixel circuit, driving method thereof, array substrate, display device | |
| US9905194B2 (en) | Integrated circuit for driving adaptable power to display and display device including the same | |
| CN105161051A (en) | Pixel circuit and driving method therefor, array substrate, display panel and display device | |
| US11183102B2 (en) | Sub-pixel unit, display panel, and display apparatus and drive method therefor | |
| CN104658480A (en) | Pixel circuit, pixel circuit driving method and display device | |
| US11626065B2 (en) | Display substrate, driving method thereof and display device | |
| CN102708795A (en) | Gate driver on array unit, gate driver on array circuit and display device | |
| CN113299223B (en) | Display panel and display device | |
| CN110930944B (en) | Display panel driving method and display device | |
| CN108428434A (en) | Pixel circuit, organic light emitting display panel and display device | |
| CN114283739B (en) | Pixel circuit, driving method thereof and display device | |
| US11205389B2 (en) | Scan driver and display device having same | |
| CN111754941A (en) | Pixel circuit, driving method thereof, display substrate and display device | |
| TW202113797A (en) | Pixel circuit and display panel | |
| JP2010238323A (en) | Shift register and electronic equipment | |
| CN113643661B (en) | Display panel and display device | |
| CN109147673B (en) | Pixel circuit, driving method thereof and display device | |
| CN111951731B (en) | Pixel unit array, driving method thereof, display panel and display device | |
| CN113643659A (en) | Organic light emitting diode display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |