WO2024000786A1 - Display panel and display device - Google Patents

Abstract

The present application discloses a display panel and a display device. The display panel comprises a non-folding region and a folding region. The non-folding region is adjacent to the folding region. The display panel is folded with reference to the folding region. Furthermore, the display panel comprises a plurality of data lines, a plurality of gate lines and a plurality of gate driving units. The plurality of data lines extend in a column direction. The plurality of gate lines extend in a row direction. The gate lines and the data lines intersect to define a region where sub-pixels are located. The plurality of gate driving units are sequentially arranged in the column direction. The gate driving units are connected to corresponding gate lines. The gate lines are connected to pixel driving circuits of the sub-pixels. On the basis of the foregoing, by means of arranging, in the non-folding region, some components of the gate driving units located in the folding region, the number of components in the folding region is suitably reduced. Therefore, the stress concentration of the folding region is reduced, thereby reducing the possibility of circuit electrical changes and circuit wiring breakage of the folding region, and further enhancing the display effect of the display panel.

Description

A display panel and display device

This application claims priority to the Chinese patent application filed with the China Patent Office on June 29, 2022, with the application number 202210763989.6 and the application title "A display panel and display device", the entire content of which is incorporated into this application by reference. .

Technical field

The present application relates to the field of display technology, and in particular, to a display panel and a display device.

Background technique

An easy-to-carry display device with foldable performance is an important development direction of future display devices. However, in the current related technology, when the display device is folded, the stress concentration in the folding area is relatively large, causing electrical changes in the circuits in the folding area and even breakage of the circuit wiring, thus affecting the display effect of the folding area and even the entire display panel.

Contents of the invention

The present application provides a display panel and a display device to reduce the stress concentration in the folding area, thereby reducing the possibility of circuit electrical changes and circuit wiring breakage in the folding area, and improving the display effect of the display panel.

According to one aspect of the present application, a display panel is provided, including a non-folding area and a folding area, including:

Multiple data lines extending along the column direction;

A plurality of gate lines extending along the row direction; the intersection of the gate lines and the data lines defines an area where the sub-pixels are located;

A plurality of gate driving units are arranged sequentially along the column direction; the gate driving units are connected to the corresponding gate lines, and the gate lines are electrically connected to the pixel driving circuits of the sub-pixels;

Wherein, the non-folding area is arranged adjacent to the folding area, the display panel is folded with reference to the folding area, and some components of the gate driving unit located in the folding area are arranged in the non-folding area. district.

Optionally, the non-folding area includes a device setting area and a device reserved area;

The device reserved area is located between the device setting area and the folding area. The components of the gate driving unit located in the non-folding area are arranged in the device setting area. The components of the gate driving unit located in the folding area are located in the folding area. Some components of the gate driving unit are arranged in the device reserved area.

Optionally, the gate driving unit includes a first gate driving unit and a second gate driving unit, the first gate driving unit is located in the non-folding area, and the second gate driving unit is located in the non-folding area. Describe the folding area.

Optionally, each of the first gate driving units is arranged at equal intervals in a direction from the non-folded area to the adjacent folded area;

Preferably, the distance between two adjacent first gate driving units increases sequentially in the direction from the non-folded area to the adjacent folded area.

Optionally, in the same non-folding area, the components of the first gate driving unit that are relatively close to the adjacent folding area are placed in a manner that is relatively far from the same folding area. The components of the first gate driving unit are placed in different ways;

Preferably, the components of the first gate driving unit that are relatively close to the folding area are arranged in m rows, and the components of the first gate driving unit that are relatively far from the folding area are arranged in m rows. Arranged in n rows; where m and n are both positive integers and m<n;

Preferably, in the first gate driving unit that is relatively close to the folding area, the spacing between two adjacent components is a first spacing; and in the first gate driving unit that is relatively far from the folding area, In the gate driving unit, the spacing between two adjacent components is a second spacing; wherein the first spacing is smaller than the second spacing;

Preferably, the display panel includes a display area and a non-display area, and the sub-pixel is located in the display area; the sub-pixel that is relatively close to the folding area and relatively close to the non-display area, The components in the display are arranged at non-equal intervals; some components of the first gate driving unit that are relatively close to the folding area are located in the display area.

Optionally, a folding axis is defined in the folding area;

Each component of the second gate driving unit located in the folding area is arranged at equal intervals;

Preferably, in the folding area, in the direction from the folding axis to the non-folding area, the spacing between two adjacent second gate driving units shows a decreasing trend;

Preferably, in the folding area, in the direction from the folding axis to the non-folding area, the distance between two adjacent components shows a decreasing trend, and the component is the second gate driver. components of the unit.

Optionally, the second gate driving unit includes a plurality of thin film transistors; the size of the thin film transistors of the second gate driving unit in the non-folding area is larger than that of the second gate in the folding area. The size of the thin film transistors of the driver unit;

Preferably, the second gate driving unit includes a plurality of capacitors, and at least one capacitor of the second gate driving unit is disposed in the non-folding region.

Optionally, the gate driving unit includes:

Scan the first transistor, scan the second transistor, scan the third transistor, scan the fourth transistor, scan the fifth transistor, scan the sixth transistor, scan the seventh transistor, scan the eighth transistor, scan the first capacitor, and scan the second capacitor;

The first end of the first scanning transistor is connected to a first enable signal, the second end of the first scanning transistor is connected to the first end of the second scanning transistor, and the control end of the first scanning transistor is connected to Enter the first clock signal;

The second terminal of the second scanning transistor is connected to the first terminal of the third scanning transistor, and the control terminal of the second scanning transistor is connected to the second clock signal;

The second end of the third scanning transistor is connected to the first potential signal, and the control end of the third scanning transistor is connected to the first end of the fourth scanning transistor;

The second terminal of the fourth scanning transistor is connected to the first clock signal, and the control terminal of the fourth scanning transistor is connected to the second terminal of the first scanning transistor;

The first end of the fifth scanning transistor is connected to the first end of the fourth scanning transistor, the second end of the fifth scanning transistor is connected to the second potential signal, and the control end of the fifth scanning transistor is connected to the first clock signal;

The control terminal of the sixth scanning transistor is connected to the first terminal of the fifth scanning transistor, the first terminal of the sixth scanning transistor is connected to the first potential signal, and the second terminal of the sixth scanning transistor is connected to the first terminal of the sixth scanning transistor. Connect the output end of the gate driving unit;

The first terminal of the seventh scanning transistor is connected to the output terminal of the gate driving unit, the second terminal of the seventh scanning transistor is connected to the second clock signal, and the control terminal of the seventh scanning transistor is connected to the scanning first terminal of the eighth transistor;

The second terminal of the eighth scanning transistor is connected to the control terminal of the fourth scanning transistor, and the control terminal of the eighth scanning transistor is connected to the second potential signal;

The scanning first capacitor is connected between the control terminal and the first terminal of the scanning sixth transistor;

The second scanning capacitor is connected between the control terminal and the first terminal of the seventh scanning transistor;

Wherein, the sixth scanning transistor, the seventh scanning transistor, the first scanning capacitor and the second scanning capacitor are arranged in the non-folding area.

Optionally, the gate driving unit includes:

first light emission control transistor, second light emission control transistor, third light emission control transistor, fourth light emission control transistor, fifth light emission control transistor, sixth light emission control transistor, seventh light emission control transistor, eighth light emission control transistor, light emission control a ninth transistor, a tenth light-emission control transistor, a first light-emission control capacitor, a second light-emission control capacitor, and a third light-emission control capacitor;

The first end of the first light-emitting control transistor is connected to the second enable signal, and the second end of the first light-emitting control transistor is connected to the control end of the second light-emitting control transistor. The first light-emitting control transistor The control terminal is connected to the third clock signal;

The first end of the second light-emitting control transistor is connected to the first clock signal, and the second end of the second light-emitting control transistor is connected to the first end of the third light-emitting control transistor;

The second end of the third light-emitting control transistor is connected to a fourth potential signal, and the control end of the third light-emitting control transistor is connected to the third clock signal;

The control terminal of the fourth luminescence control transistor is connected to the first terminal of the third luminescence control transistor, the first terminal of the fourth luminescence control transistor is connected to a third potential signal, and the third terminal of the fourth luminescence control transistor is connected to Two terminals are connected to the first terminal of the fifth light-emitting control transistor;

The second end of the fifth light-emitting control transistor is connected to the second end of the first light-emitting control transistor, and the control end of the fifth light-emitting control transistor is connected to a fourth clock signal;

The control end of the sixth light-emitting control transistor is connected to the second end of the first light-emitting control transistor, and the first end of the sixth light-emitting control transistor is connected to the third potential signal. The sixth light-emitting control transistor The second terminal is connected to the first terminal of the seventh light-emitting control transistor;

The second end of the seventh light-emitting control transistor is connected to the first end of the eighth light-emitting control transistor, and the control end of the seventh light-emitting control transistor is connected to the fourth clock signal;

The second end of the eighth light-emitting control transistor is connected to the fourth clock signal, and the control end of the eighth light-emitting control transistor is connected to the first end of the third light-emitting control transistor;

The first terminal of the ninth luminescence control transistor is connected to the third potential signal, the second terminal of the ninth luminescence control transistor is connected to the output terminal of the gate driving unit, and the ninth terminal of the luminescence control transistor is connected to the third potential signal. The control terminal is connected to the second terminal of the sixth light-emitting control transistor;

The first end of the tenth light-emitting control transistor is connected to the output end of the gate driving unit, the second end of the tenth light-emitting control transistor is connected to the fourth potential signal, and the tenth light-emitting control transistor has a second end connected to the fourth potential signal. The control terminal is connected to the second terminal of the first transistor for controlling light emission;

The first emission control capacitor is connected between the first terminal and the control terminal of the eighth emission control transistor;

The first end of the second light-emitting control capacitor is connected to the control end of the tenth light-emitting control transistor, and the second end of the light-emitting control capacitor is connected to the fourth clock signal;

The third emission control capacitor is connected between the control terminal and the first terminal of the ninth emission control transistor;

Wherein, the eighth luminescence control transistor, the ninth luminescence control transistor, the tenth luminescence control transistor, the first luminescence control capacitor, the second luminescence control capacitor and the third luminescence control capacitor are configured in the unfolded region.

Optionally, the display panel also includes a clock line, a potential line and an enable line;

Each of the gate driving units is connected to the clock line, and each of the gate driving units is connected to the potential line; the enable line is used to provide a start signal to the gate driving unit; wherein, folding The clock line, the potential line and/or the enable line located between two adjacent gate driving units in the area are arranged obliquely in the plane where the display panel is located.

According to another aspect of the present application, a display device is provided, which includes the display panel as described in the above aspect.

According to the technical solution of the embodiment of the present application, the display panel includes a non-folding area and a folding area, the non-folding area is arranged adjacent to the folding area, and the display panel is folded with reference to the folding area; and the display panel includes multiple data lines and multiple gate electrodes. Lines and multiple gate drive units; multiple data lines extend along the column direction, multiple gate lines extend along the row direction, the intersection of the gate line and the data line defines the area where the sub-pixel is located, and multiple gate drives The units are arranged sequentially along the column direction, the gate driving units are connected to corresponding gate lines, and the gate lines are connected to corresponding sub-pixels. Based on this, by arranging some components of the gate drive unit located in the folded area in the non-folded area, the number of components in the folded area is appropriately reduced, thereby reducing the stress concentration in the folded area, thereby reducing the risk of folding. It reduces the possibility of electrical changes in the area circuit and breakage of the circuit traces, thereby improving the display effect of the display panel.

It should be understood that the content described in this section is not intended to identify key or important features of the embodiments of the application, nor is it intended to limit the scope of the application. Other features of the present application will become readily understood from the following description.

Description of drawings

Figure 1 is a schematic structural diagram of a display panel;

Figure 2 is a schematic structural diagram of another display panel;

Figure 3 is a schematic structural diagram of another display panel;

Figure 4 is a schematic structural diagram of a display device;

Figure 5 is a schematic structural diagram of a display panel provided by an embodiment of the present application;

Figure 6 is a schematic structural diagram of another display panel provided by an embodiment of the present application;

Figure 7 is a schematic diagram of the arrangement of components of a first gate driving unit provided by an embodiment of the present application;

FIG. 8 is a schematic diagram of the arrangement of components of another first gate driving unit provided by an embodiment of the present application;

FIG. 9 is a schematic diagram of the arrangement of components of another first gate driving unit provided by an embodiment of the present application;

Figure 10 is a schematic structural diagram of a second gate driving unit provided by an embodiment of the present application;

Figure 11 is a schematic structural diagram of another second gate driving unit provided by an embodiment of the present application;

Figure 12 is a partial enlarged view of the display panel shown in Figure 5;

FIG. 13 is a schematic structural diagram of a display device provided by an embodiment of the present application.

Detailed ways

As mentioned in the background art, currently, when a display device is folded, the stress concentration in the folding area is relatively large, causing the electrical properties of the circuit in the folding area to change and even the circuit wiring to break. In this regard, the applicant found after long-term research that the specific reasons are as follows:

Referring to Figure 1, the display panel includes a first non-folding area 12_1, a second non-folding area 12_2 and a folding area 11. The folding area 11 is located between the first non-folding area 12_1 and the second non-folding area 12_2; the display panel includes a gate electrode Line 14, data line 15 and gate driving unit 13. The intersection of the gate line 14 and the data line 15 defines the area where the sub-pixel is located. The gate line 14 is connected to the corresponding sub-pixel, and the gate driving unit 13 is connected to the corresponding gate Pole line 14 is connected. Continuing to refer to FIG. 1 , since the gate driving unit 13 is provided in the folding area 11 , when the display panel is folded with reference to the folding area 11 , the gate driving unit 13 in the folding area 11 will be bent, causing stress in the folding area 11 to concentrate. Therefore, as the number of folding increases, the gate driving unit 13 in the folding area 11 is more likely to suffer from damage fatigue, causing damage to the components and the breakage of the wiring 16 between the gate driving units 13, even causing the folding area 11 to components failed. When components fail, signals cannot be transmitted normally, which will affect the display effect of the folding area 11, and in severe cases, the display effect of the entire display panel.

Referring to FIG. 2 , the display panel includes a non-folding area 22 and a folding area 21 . The non-folding area 22 includes a plurality of first gate lines 24_1, a plurality of first data lines 25_1, a plurality of first sub-pixels and a plurality of first gate driving units 23_1; the first gate lines 24_1 and the corresponding first The sub-pixels are connected, the first data line 25_1 is connected to the corresponding first sub-pixel, and the first gate driving unit 23_1 is connected to the corresponding first gate line 24_1; wherein the first gate line 24_1 extends along the row direction x, The first data line 25_1 extends along the column direction y. The folding area 21 includes a plurality of second gate lines 24_2, a plurality of second data lines 25_2, a plurality of second sub-pixels and a plurality of second gate driving units 23_2. The second gate lines 24_2 and corresponding second sub-pixels The pixels are connected, the second data line 25_2 is connected to the corresponding second sub-pixel, and the second gate driving unit 23_2 is connected to the corresponding second gate line 24_2; wherein the second gate line 24_2 extends along the column direction y, and the second gate driving unit 23_2 extends along the column direction y. The two data lines 25_2 extend along the row direction x. Continuing to refer to FIG. 2 , the first gate driving unit 23_1 located in the non-folding area 22 and the second gate driving unit 23_2 located in the folding area 21 are independently designed to avoid that the second gate driving unit 23_2 will not be affected by the display panel. The effect of bending. However, this type of design still does not essentially reduce the stress concentration in the folded area, and independent design of the gate driving units in the non-folded area 22 and the folded area 21 can easily cause display screen splitting.

Referring to FIG. 3 , the display panel includes a first non-folding area 32_1 , a second non-folding area 32_2 and a folding area 31 . The folding area 31 is located between the first non-folding area 32_1 and the second non-folding area 32_2 . The display panel includes a plurality of gate lines 35, a plurality of data lines 34, a plurality of first data pins 36_1 and a plurality of second data pins 36_2. The gate lines 35 pass through the first non-folding area 32_1 and the folding area 31 in sequence. and the second non-folding area 32_2. The data line 34 includes a first data line 34_1 located in the first non-folding area 32_1 and a second data line 34_2 located in the second non-folding area 32_2. The first data line 34_1 and the first data line 34_1 are located in the first non-folding area 32_2. The first data pin 36_1 in the folded area 32_1 is connected, and the second data line 34_2 is connected with the second data pin 36_2 located in the second non-folded area 32_2; wherein, the gate line 35 extends along the column direction y, and the data line 34 extends along the column direction y. Row direction x extends. Continuing to refer to FIG. 3 , by setting the extension direction of the data line 34 to be parallel to the folding axis KK', the bending of the data line 34 is avoided. At the same time, because the gate line 35 spans the first non-folding area 32_1 and the folding area 31 and the second non-folded area 32_2, so that scanning signals can be provided from both sides of the gate line 35. However, although this type of design avoids setting the gate driving unit 33 in the folding area 31 and thus avoids multiple bending of the gate driving unit in the folding area 31, due to the gap between the first non-folding area 32_1 and the second non-folding area 32_2 respectively sets the first data pin 36_1 and the second data pin 36_2, which causes the flexible circuit board (not shown in the figure) connecting the first data pin 36_1 and the second data pin 36_2 to involve multiple bends. That is to say, the bending problem of the gate drive unit in the folding area 31 is transferred to the flexible circuit board. The technical problem has not been solved in essence, and the two binding areas can easily cause the display to split.

Referring to FIG. 4 , the display device includes a substrate 40 , a plurality of gate lines, a plurality of data lines, and a plurality of gate drivers 43 . The gate driver 43 includes a plurality of gate driving blocks, and the gate driving blocks are connected to corresponding gate lines. Connection; wherein, the gate lines extend along the row direction x, and the data lines extend along the column direction y. Continuing to refer to FIG. 4 , the substrate 40 defines a folding line QQ′ and a folding part 41. By not disposing the gate driver 43 on the folding line QQ′, that is, not disposing the gate driver 43 on the folding part 41, that is, not disposing the gate driver 43 on the folding part 41. 41 is not provided such as a thin film transistor with overlapping electrodes, so that even if the display device is repeatedly folded, the gate driver 43 is not directly affected. However, in this type of design, since all the gate driving blocks are arranged in the non-folding area 42, the non-folding area 42 has a larger frame, which in turn results in a larger frame of the display device.

In view of this, embodiments of the present application provide a display panel and a display device to specifically solve the technical problem of large stress concentration in the folding area, reduce the possibility of circuit electrical changes and circuit wiring breakage in the folding area, and thereby improve The display effect of the display panel, at the same time, achieves a narrow bezel design and avoids split-screen display.

FIG. 5 is a schematic structural diagram of a display panel provided by an embodiment of the present application. Referring to Figure 5, the display panel includes a non-folding area 52 and a folding area 51. The display panel includes: a plurality of data lines 55 extending along the column direction y; a plurality of gate lines 54 extending along the row direction x; the gate lines 54 and The data lines 55 intersect to define the area where the sub-pixels are located; a plurality of gate driving units are arranged in sequence along the column direction y; the gate driving units 53 are connected to the corresponding gate lines 54, and the gate lines 54 are connected to the corresponding sub-pixels (Specifically, the gate line 54 can be electrically connected to the pixel driving circuit of the sub-pixel); wherein, the non-folding area 52 is arranged adjacent to the folding area 51, the display panel is folded with reference to the folding area 51, and the gate drive located in the folding area 51 Some components of the unit 53 are arranged in the non-folding area 52 .

Specifically, the display panel may be a flexible foldable display panel, and the display panel may have at least two non-folding areas 52 and at least one folding area 51 , and the folding area 51 is located between two adjacent non-folding areas 52 . Each folding area 51 defines a folding axis PP', and the display panel can be folded and bent (bent) along the folding axis in the folding area 51 so that the planar curvature of the display panel in the folding area 51 is not 0. As schematically illustrated in FIG. 5 , the display panel has two non-folding areas 52 (ie, a first non-folding area 52_1 and a second non-folding area 52_2 ) and one folding area 51 (defining a folding axis PP'). The folding area 51 Located between the first unfolded area 52_1 and the second unfolded area 52_2.

Sub-pixels (not shown in the figure) are provided in the area defined by the intersection of the data line 55 and the gate line 54, so that multiple sub-pixels are arranged in an array in the display panel, and the sub-pixel array covers the first non-folding area 52_1, the folding area 52_1 and the folding area 52_1. area 51 and the second unfolded area 52_2. The sub-pixel may include a light-emitting element and a pixel driving circuit (pixel circuit for short). The light-emitting element is connected to the pixel circuit. The pixel circuit is used to drive the connected light-emitting element to emit light according to the driving signal. The driving signal includes a data signal, a scanning signal, an initialization signal, etc. , the light-emitting element is, for example, a light-emitting diode (Light-Emitting Diode, LED).

Among them, the data signal is provided by the data line 55. The scan signal is provided by the gate line 54; the scan signal can be used as a scan signal Scan to drive switching transistors such as a data writing transistor and an initialization transistor, or as a light-emitting control signal EM to drive the light-emitting control transistor. Here, the data writing transistor refers to the switching transistor in the pixel circuit for transmitting the data signal to the storage capacitor, the initialization transistor is the switching transistor for transmitting the initialization signal to the gate of the driving transistor and/or the anode of the light-emitting element, and the light emission control The transistor is a switching transistor used to control the light-emitting phase of the light-emitting element.

The driver in the display panel includes a data driving unit (not shown in the figure) and a gate driving unit 53. The data driving unit is connected to the corresponding data line 55. The data driving unit is used to generate a data signal. The gate driving unit 53 is connected to the corresponding data line 55. The gate lines 54 are connected, and the gate driving unit 53 is used to generate scanning signals. Each gate driving unit 53 can be used as a shift register, and multiple cascaded gate driving units 53 constitute multiple cascaded shift registers; wherein, the input end of the first-stage gate driving unit 53 is connected to The gate driving unit 53 can shift and output the starting signal from its own output terminal according to the received clock signal. The output is the scanning signal, and the input terminal of the next-level gate driving unit 53 can be connected to the previous stage. The output terminal of the gate driving unit 53 .

A plurality of gate driving units 53 are arranged sequentially along the column direction y on the periphery of the sub-pixel array. The first non-folding area 52_1, the folding area 51 and the second non-folding area 52_2 are all provided with gate driving units 53. Each gate driving unit 53 may include multiple components, that is, multiple components may be electrically connected to each other to form a gate driving unit 53. The components may be thin film transistors or capacitors, etc.; the thin film transistors may be stacked active components. The capacitor can be composed of multiple metal film layers stacked on top of each other.

It can be seen from this that when the display panel is folded with reference to the folding area 51, since the folding area 51 is provided with the gate driving unit 53, the gate driving unit 53 in the folding area 51 will be bent, and the components in the gate driving unit 53 will be bent. The active layer and metal film layer of the device are relatively hard, and generally the gate driving unit 53 contains a large number of components and the components are densely arranged. Therefore, the stress concentration in the folding area 51 is relatively large. As the number of times increases, the gate driving unit 53 in the folding area 51 is prone to damage fatigue, resulting in damage to the components of the gate driving unit 53 and breakage of the wiring between the gate driving units 53 . Among them, the wiring between the units 53 includes but is not limited to an enable line used to provide a start signal, a clock line used to provide a clock signal, and a potential line used to provide a potential signal; the potential signal, for example, has a higher voltage. potential signal or a potential signal with a lower voltage.

In this regard, in the technical solution of this embodiment, some components of the gate driving unit 53 located in the folding area 51 are arranged in the non-folding area 52 , for example, some components of the gate driving unit 53 located in the folding area 51 It is provided in the first non-folding area 52_1 and/or the second non-folding area 52_2 so that the number of components in the folding area 51 is appropriately reduced. If there are fewer components in the folding area 51, the volume of the active layer and metal film layer in the folding area 51 will be smaller, and the components can be arranged more densely, so the stress concentration in the folding area 51 will be smaller. This implementation For example, this reduces the stress concentration in the folded area 51, thereby reducing the possibility of damage to the components of the gate drive unit 53 in the folded area 51 and breakage of the wiring between units, so that the gate drive unit 53 in the folded area 51 can be generated normally. The signal and transmission signal work normally. This embodiment thus improves the stability, reliability and display effect of the folding area 51 and the display panel.

At the same time, due to the technical solution of this embodiment, only some components of the gate driving unit 53 located in the folding area 51 are arranged in the non-folding area 52. If multiple gate driving units 53 are provided in the folding area 51, only It is enough to arrange some components of each gate driving unit 53 in the folded area 51 in the non-folded area 52. The occupied area of the non-folded area 52 is very small. Therefore, compared with the solutions shown in FIGS. 4 and 3 , reducing the frame of the non-folding area 52, thereby reducing the frame of the display device, realizing a narrow frame design, and because the occupied area of the non-folding area 52 is very small, it is possible to avoid damaging each grid in the non-folding area 52. The arrangement of the polar driving units 53 is greatly moved, changed, and adjusted, so that the reliability of the non-folding area 52 is higher, and thus the reliability of the display panel is higher. Moreover, compared with the horizontal and vertical screen designs shown in Figures 3 and 2, the technical solution of this embodiment can avoid split-screen display, thereby further improving the display effect. Moreover, the technical solution of this embodiment not only reduces the stress concentration in the folding area 51 by reducing the number of components in the folding area 51, but also softens the folding area 51, thereby improving the bending of the folding area 51. performance, thus improving the service life and reliability of the display panel.

Continuing to refer to Figure 5, as an embodiment of the present application, optionally, the non-folding area 52 includes a device setting area 56 and a device reserved area 57; the device reserved area 57 is located between the device setting area 56 and the folding area 51 ; The components of the gate driving unit 53 located in the non-folding area 52 are arranged in the device setting area 56, and some components of the gate driving unit 53 located in the folding area 51 are arranged in the device reserved area 57; wherein, the device setting area 56 and device reserved area 57 are located at the periphery of the sub-pixel array.

Specifically, the technical solution of this embodiment uses the non-folding area 52 as an area for setting the gate driving unit 53, freeing up a small area to set some components of the gate driving unit 53 in the folding area 51. This freeing up area The small area vacated is the device reserved area 57, and the area not vacated is the device setting area 56. The device setting area 56 is used to set the gate driving unit 53 in the non-folding area 52 , and the device reserved area 57 is used to set some components of the gate driving unit 53 in the folding area 51 , that is, in the gate driving unit 53 in the folding area 51 Components that need to be moved to the non-folding area 52 can be placed in the component reserved area 57 . The device reserved area 57 is arranged between the device setting area 56 and the non-folding area 52 so that the components in the gate driving unit 53 in the folding area 51 that are moved to the non-folding area 52 can be placed nearby to shorten the folding time as much as possible. By shortening the wiring length between the components in the gate drive unit 53 in area 51 and shortening the wiring length between the folded area 51 and the non-folded area 52, not only can the IR-Drop (IR voltage drop) on the wiring be reduced, but also the wiring length can be reduced. It can simplify the wiring around the sub-pixel array and improve the reliability of the display panel.

For example, continuing to refer to FIG. 5 , the first non-folding area 52_1 may include a first device setting area 56_1 and a first device reserved area 57_1, and/or the second non-folding area 52_2 may include a second device setting area 56_2 and the second device reserved area 57_2. Among them, the first device setting area 56_1 is used to set the gate driving unit 53 of the first non-folding area 52_1, and the second device setting area 56_2 is used to set the gate driving unit 53 of the second non-folding area 52_2. The reserved area 57_1 is located between the first device setting area 56_1 and the folding area 51. The second device reserved area 57_2 is located between the second device setting area 56_2 and the folding area 51. The gate driving unit 53 in the folding area 51 needs to be moved to The components in the non-folding area 52 may be arranged in the first device reserved area 57_1 and/or the second device reserved area 57_2.

In the embodiment of the present application, there are many ways to set up the device setting area and the device reserved area in the non-folding area. Several of them will be exemplarily described below, but this is not intended to limit the present application. Among them, the gate driving unit 53 includes a first gate driving unit 53_1 and a second gate driving unit 53_2. The first gate driving unit 53_1 is arranged in the non-folding area 52, and the second gate driving unit 53_2 is arranged in the folding area 51. . As schematically shown in FIG. 5 , the first gate driving unit 53_1 is disposed in the first non-folding area 52_1 and the second non-folding area 52_2; the direction of the non-folding area 52 away from the adjacent folding area 51 includes the first non-folding area. 52_1 is in a direction away from the folding area 51 , and the second non-folding area 52_2 is in a direction away from the folding area 51 .

Continuing to refer to FIG. 5 , optionally, in an embodiment of the present application, each first gate driving unit 53_1 is arranged at equal intervals in the direction of the non-folding area 52 away from the adjacent folding area 51 .

Specifically, in this embodiment, in the first non-folding area 52_1, in the direction away from the folding area 51 from the first non-folding area 52_1, the first gate driving units 53_1 are arranged at equal intervals, and in the second non-folding area 52_2 , starting from the direction of the second non-folding area 52_2 away from the folding area 51, each first gate driving unit 53_1 is arranged at an equal distance; thus, the first device reserved area 57_1 is formed by connecting all the first gates of the first non-folding area 52_1. The gate driving unit 53_1 is translated as a whole in the direction away from the folding area 51, and the second device reserved area 57_2 is obtained by moving all the first gate driving units 53_1 in the second non-folding area 52_2 in a direction away from the folding area 51. Obtained by translation in the direction.

Moreover, since in this embodiment only some components of the second gate driving unit 53_2 are arranged in the first non-folding area 52_1 or the second non-folding area 52_2, the first device reserved area 57_1 and the second device reserved area The remaining area 57_2 does not need to be too large, so that all the first gate driving units 53_1 do not need to be translated too far as a whole in the non-folding area 52. Accordingly, this embodiment achieves narrow stress concentration reduction in the folding area 51. Border design.

Referring to Figure 6, Figure 6 is a schematic structural diagram of another display panel provided by an embodiment of the present application. In another embodiment of the present application, optionally, the non-folding area 52 is away from the adjacent folding area 51. direction, the spacing between two adjacent first gate driving units 53_1 shows an increasing trend (that is, the spacing between two adjacent first gate driving units 53_1 increases sequentially).

For example, in the first non-folded area 52_1, in the direction away from the folded area 51 from the first non-folded area 52_1, the spacing between two adjacent first gate driving units 53_1 tends to increase, and in the second In the non-folded area 52_2, from the direction of the second non-folded area 52_2 away from the folded area 51, the distance between two adjacent first gate driving units 53_1 tends to increase; thus, the first device reserved area 57_1 is passed through The distance between two adjacent first gate driving units 53_1 close to the folded area 51 in the first non-folded area 52_1 is reduced, and the second device reserved area 57_2 is obtained by reducing the distance between the second non-folded area 52_2 and , the spacing between two adjacent first gate driving units 53_1 close to the folding area 51 is reduced. That is to say, by "squeezing" the first gate driving units 53_1 in the first non-folded area 52_1 along the column direction y, so that they are compactly arranged in the column direction y, so that in the first non-folded area 52_1 A small area is allowed in the folded area 52_1 as the first device reserved area 57_1, and the first gate driving units 53_1 in the second non-folded area 52_2 are "squeezed" with each other along the column direction y, so that they are They are arranged compactly in the column direction y, thereby leaving a small area in the second non-folding area 52_2 as the second device reserved area 57_2.

Among them, since the device reserved area 57 is located between the device setting area 56 and the folding area 51, the spacing between two adjacent first gate driving units 53_1 in the non-folding area 52 and close to the folding area 51 can be prioritized. Compress and shrink to make room for a small area as a device reserved area 57. Moreover, in this embodiment, only some components of the second gate driving unit 53_2 are arranged in the area squeezed out by the first gate driving unit 53_1 in the non-folding area 52 (that is, the released devices are pre-positioned in the non-folding area 52). area) instead of occupying any other area, so it will not cause any increase in the non-folding area 52. Accordingly, this embodiment further realizes a narrow frame design while reducing stress concentration in the folding area 51.

FIG. 7 is a schematic diagram of the placement of components of a first gate driving unit provided by an embodiment of the present application. FIG. 8 is a placement of components of another first gate driving unit provided by an embodiment of the present application. Schematic diagram of the method. In another embodiment of the present application, optionally, in the same non-folding area 52 , the components D of the first gate driving unit that are relatively close to the adjacent folding area 51 are placed (please refer to 8), which is different from the arrangement of the components D of the first gate driving unit that are relatively far away from the same folding area 51 (refer to FIG. 7). Accordingly, a device preset can also be reserved in the non-folding area 52. Leave area 57.

Continuing to refer to FIGS. 7 and 8 , in another embodiment of the present application, optionally, in the same non-folding area 52 , the components of the first gate driving unit relatively close to the folding area 51 are arranged in m rows. Place, the components of the first gate driving unit relatively far away from the folding area 51 are placed in n rows; where m and n are both positive integers and m<n, the first gate is schematically illustrated in Figure 7 The driving unit may be the first gate driving unit 53_106 in the first non-folding area 52_1 in FIG. 6 (relatively far from the folding area 51), and the first gate unit illustratively illustrated in FIG. 8 may be the first gate driving unit 53_106 in the first non-folding area 52_1 in FIG. 6 . A first gate driving unit 53_101 in the non-folded area 52_1 (relatively close to the folded area 51).

Specifically, the specific structure of each gate driving unit 53 in a general display panel is the same, that is, the type and number of components included are the same. In the same non-folding area 52 , the components of the first gate driving unit 53_1 that are relatively far away from the folding area 51 are arranged in n rows, and the components of the first gate driving unit 53_1 that are relatively close to the folding area 51 are arranged in n rows. The components are arranged in m rows; thus, the device reserved area 57 is formed by placing the components of the first gate driving unit 53_1 in the non-folding area 52 close to the folding area 51 and placing fewer components in the column direction y. By placing more of them in the row direction x, a small area is left in the non-folding area 52 as a device reserved area 57 . For example, originally the components of the first gate driving unit 53_101 in the first non-folding area 52_1 and the components of the first gate driving unit 53_106 in the first non-folding area 52_1 are arranged in 4 rows and 3 columns. By arranging the components of the first gate driving unit 53_101 in three rows and four columns, a small area is left in the first non-folding area 52_1 as the first device reserved area 57_1. Moreover, since in this embodiment only some components of the second gate driving unit 53_2 are arranged in the first non-folding area 52_1 or the second non-folding area 52_2, the first device reserved area 57_1 and the second device reserved area The remaining area 57_2 does not need to be too large, so there is no need to provide more components of the first gate driving unit 53_1. The components of the first gate driving unit 53_1 are placed less in the column direction y and more in the row direction x. This embodiment is based on this While reducing stress concentration in the folding area 51, a narrow frame design is achieved.

Continuing to refer to Figures 7 and 8, in another embodiment of the present application, optionally, in the same non-folding area 52, in the first gate driving unit 53_101 relatively close to the folding area 51, two adjacent The spacing between components D is the first spacing L1; in the first gate driving unit 53_106 which is relatively far away from the folding area 51, the spacing between two adjacent components D is the second spacing L2; The distance L1 is smaller than the second distance L2.

Specifically, setting the distance between two adjacent components D in the first gate driving unit 53_1 relatively close to the folding area 51 to be smaller is not only beneficial to freeing up the device reserved area 57, but also This is beneficial to the process of freeing up the device reserved area 57 without causing an increase in the frame, thereby achieving a narrow frame design while reducing stress concentration in the folding area 51 .

FIG. 9 is a schematic diagram of another arrangement of components of the first gate driving unit provided by an embodiment of the present application. Combining Figure 6 and Figure 9, in another embodiment of the present application, optionally, the display panel includes a display area AA and a non-display area NAA, and the sub-pixels are located in the display area AA; in the same non-folding area 52, the distance The components in the sub-pixels that are relatively close to the area 51 and relatively close to the non-display area NAA are not arranged at equal intervals; some components of the first gate driving unit 53_1 that are relatively close to the folding area 51 are located in the display area. District AA.

Specifically, the components of the pixel circuit in the sub-pixels that are relatively close to the folding area 51 and relatively close to the non-display area NAA can be arranged at non-equal intervals, so that the components in the pixel circuit are arranged along the column direction. y or "squeeze each other" along the row direction Some components are included, thereby allowing a small area in the non-folding area 52 to be used as a device reserved area 57 . Since in this embodiment, some components of the first gate driving unit 53_1 are squeezed into the display area AA to free up the device reserved area 57 in the non-folding area 52, it does not cause an increase in the frame. Therefore, this embodiment achieves a narrow frame design while reducing stress concentration in the folding area 51 .

Based on any of the above technical solutions, in the embodiment of the present application, there are various ways of placing the components located in the folding area 51 of the second gate driving unit 53_2. Several of them are exemplarily described below. But it does not limit this application.

In an embodiment of the present application, optionally, the components of the second gate driving unit 53_2 located in the folding area 51 are arranged at equal intervals, that is, the components of the second gate driving unit 53_2 located in the folding area 51 Evenly distributed in the folding area 51 , the stress concentration in the folding area 51 can be further reduced, the folding area 51 can be further softened, and the bending performance of the folding area 51 can be improved.

In another embodiment of the present application, optionally, in the folding area 51, with the folding axis PP' pointing in the direction of the non-folding area 52, the spacing between two adjacent second gate driving units 53_2 decreases. Small trends. That is, from the direction in which the folding axis PP' points to the non-folding area 52, the distance between two adjacent second gate driving units 53_2 that are far away from the folding axis PP' is relatively small, and the distance between the two adjacent second gate driving units 53_2 that is closer to the folding axis PP' is relatively small. The spacing between two adjacent second gate driving units 53_2 is relatively large, that is, the arrangement of the second gate driving units 53_2 in the area closer to the folding axis PP' is relatively sparse and not dense, thereby further reducing the The stress in the folded area 51 is concentrated.

In another embodiment of the present application, optionally, in the folding area 51, with the folding axis PP' pointing in the direction of the non-folding area 52, the spacing between two adjacent components tends to decrease, where The device is a component of the second gate driving unit 53_2. That is, in the folding area 51, from the folding axis PP' to the direction of the non-folding area 52, the distance between two adjacent components farther from the folding axis PP' is relatively small, and the distance between two adjacent components closer to the folding axis PP' is relatively small. The distance between two adjacent components is relatively large, that is, the components in the area closer to the folding axis PP' are sparsely arranged and not aggregated, which can further reduce the stress concentration in the folding area 51 .

In the embodiment of the present application, any component of the second gate driving unit 53_2 may be disposed in the non-folding area 52, which is not specifically limited in this embodiment. For example, it can be based on the layout design of the first gate driving unit 53_1 and the second gate driving unit 53_2 in the display panel, on the premise that it will basically not have any adverse effects on the layout design, and on the requirement of simplifying wiring. Some components of the second gate driving unit 53_2 are selected to be arranged in the non-folding area 52 .

In an embodiment of the present application, optionally, the second gate driving unit 53_2 includes a plurality of thin film transistors; wherein the size of the thin film transistors of the second gate driving unit 53_2 disposed in the non-folding area 52 is greater than The size of the thin film transistor of the second gate driving unit 53_2 provided in the folding area 51.

Specifically, generally among the plurality of thin film transistors included in the second gate driving unit 53_2, some thin film transistors are relatively small in size, and some thin film transistors are relatively large in size. The stress concentration of the relatively large thin film transistors is relatively small. Larger, moving the relatively large thin film transistor from the folding area 51 to the non-folding area 52 can not only greatly reduce the stress concentration of the large size thin film transistor, protect the large size thin film transistor from damage or electrical changes, but also can The total component volume in the folding area 51 is effectively reduced, thereby effectively reducing stress concentration in the folding area 51, effectively softening the folding area 51, and improving the bending performance of the folding area 51. On this basis, the size of the components located in the folding area 51 of the second gate driving unit 53_2 can be specially designed to be relatively small, so as to further reduce the stress concentration in the folding area 51, further soften the folding area 51, and improve the folding area. Zone 51 bending performance.

In another embodiment of the present application, optionally, the second gate driving unit 53_2 further includes a plurality of capacitors; wherein at least one capacitor of the second gate driving unit 53_2 is disposed in the non-folding region 52 .

Specifically, generally the capacitor in the second gate driving unit 53_2 is used to ensure that the second gate driving unit 53_2 stably outputs the scanning signal. If the capacitor is damaged or electrically changed due to bending, it will more easily affect the normal operation of the second gate driving unit 53_2, thereby affecting the display of the folding area 51 or even the entire display panel. Accordingly, arranging the capacitor of the second gate driving unit 53_2 in the non-folded area 52 can not only avoid the stress concentration of the capacitor and protect the capacitor from damage or electrical changes, but also effectively reduce the total cost in the folded area 51 device volume, thereby effectively reducing stress concentration in the folding area 51, effectively softening the folding area 51, and improving the bending performance of the folding area 51.

As an implementation manner of the present application, optionally, the second gate driving unit 53_2 includes an 8T2C structure to output the scan signal Scan. Figure 10 is a schematic structural diagram of a second gate driving unit provided by an embodiment of the present application. For example, referring to Figure 10, the second gate driving unit 53_2 with an 8T2C structure includes:

The first transistor T1 is scanned, the second transistor T2 is scanned, the third transistor T3 is scanned, the fourth transistor T4 is scanned, the fifth transistor T5 is scanned, the sixth transistor T6 is scanned, the seventh transistor T7 is scanned, the eighth transistor T8 is scanned, and the third transistor T8 is scanned. a capacitor C1 and a second capacitor C2 for scanning;

The first end of the first scanning transistor T1 is connected to the first enable signal SIN, the second end of the first scanning transistor T1 is connected to the first end of the second scanning transistor T2, and the control end of the first scanning transistor T1 is connected to the first enable signal SIN. Clock signal SCK1;

The second terminal of the second scanning transistor T2 is connected to the first terminal of the third scanning transistor T3, and the control terminal of the second scanning transistor T2 is connected to the second clock signal SCK2;

The second terminal of the third scanning transistor T3 is connected to the first potential signal VGH1, and the control terminal of the third scanning transistor T3 is connected to the first terminal of the fourth scanning transistor T4;

The second terminal of the fourth scanning transistor T4 is connected to the first clock signal SCK1, and the control terminal of the fourth scanning transistor T4 is connected to the second terminal of the first scanning transistor T1;

The first terminal of the fifth scanning transistor T5 is connected to the first terminal of the fourth scanning transistor T4, the second terminal of the fifth scanning transistor T5 is connected to the second potential signal VGL1, and the control terminal of the fifth scanning transistor T5 is connected to the first clock. signal SCK1;

The control terminal of the sixth scanning transistor T6 is connected to the first terminal of the fifth scanning transistor T5, the first terminal of the sixth scanning transistor T6 is connected to the first potential signal VGH1, and the second terminal of the sixth scanning transistor T6 is connected to the gate driving unit. the output terminal;

The first terminal of the seventh scanning transistor T7 is connected to the output terminal of the gate driving unit, the second terminal of the seventh scanning transistor T7 is connected to the second clock signal SCK2, and the control terminal of the seventh scanning transistor T7 is connected to the output terminal of the eighth scanning transistor T8. first end;

The second terminal of the eighth scanning transistor T8 is connected to the control terminal of the fourth scanning transistor T4, and the control terminal of the eighth scanning transistor T8 is connected to the second potential signal VGL1;

The first scanning capacitor C1 is connected between the control terminal and the first terminal of the sixth scanning transistor T6;

The second scanning capacitor C2 is connected between the control terminal and the first terminal of the seventh scanning transistor T7;

Among them, the sixth scanning transistor T6 and the seventh scanning transistor T7 are transistors used by the gate driving unit to output the scanning signal Scan. Their sizes are generally larger than those of other scanning transistors. Therefore, the sixth scanning transistor T6 and the scanning seventh transistor T7 can be combined with each other. The seven transistors T7 are set in the non-folding area 52; the first scanning capacitor C1 and the second scanning capacitor C2 are used to ensure that the gate unit outputs a stable scanning signal Scan, so the first scanning capacitor C1 and the second scanning capacitor C2 can be set in Unfolded area 52.

As another implementation manner of the present application, optionally, the second gate driving unit 53_2 includes: a 10T3C structure to output the light emission control signal EM. Figure 11 is a schematic structural diagram of another second gate driving unit provided by an embodiment of the present application. For example, referring to Figure 11, the second gate driving unit 53_2 with a 10T3C structure includes:

The first light emission control transistor M1, the second light emission control transistor M2, the third light emission control transistor M3, the fourth light emission control transistor M4, the fifth light emission control transistor M5, the sixth light emission control transistor M6, the seventh light emission control transistor M7, the light emission control transistor M7. controlling an eighth transistor M8, a ninth light-emission control transistor M9, a tenth light-emission control transistor M10, a first light-emission control capacitor C3, a second light-emission control capacitor C4, and a third light-emission control capacitor C5;

The first end of the first light-emitting control transistor M1 is connected to the second enable signal EIN, the second end of the first light-emitting control transistor M1 is connected to the control end of the second light-emitting control transistor M2, and the control end of the first light-emitting control transistor M1 Access the third clock signal ECK1;

The first terminal of the second light-emitting control transistor M2 is connected to the first clock signal SCK1, and the second terminal of the second light-emitting control transistor M2 is connected to the first terminal of the third light-emitting control transistor M3;

The second end of the third light-emitting control transistor M3 is connected to the fourth potential signal VGL2, and the control end of the third light-emitting control transistor M3 is connected to the third clock signal ECK1;

The control terminal of the fourth luminescence control transistor M4 is connected to the first terminal of the third luminescence control transistor M3. The first terminal of the fourth luminescence control transistor M4 is connected to the third potential signal VGH2. The second terminal of the fourth luminescence control transistor M4 is connected to Light emission control first terminal of the fifth transistor M5;

The second end of the fifth light-emission control transistor M5 is connected to the second end of the first light-emission control transistor M1, and the control end of the fifth light-emission control transistor M5 is connected to the fourth clock signal ECK2;

The control terminal of the sixth luminescence control transistor M6 is connected to the second terminal of the first luminescence control transistor M1, the first terminal of the sixth luminescence control transistor M6 is connected to the third potential signal VGH2, and the second terminal of the sixth luminescence control transistor M6 is connected to The first terminal of the seventh transistor M7 for lighting control;

The second terminal of the seventh light-emitting control transistor M7 is connected to the first terminal of the eighth light-emitting control transistor M8, and the control terminal of the seventh light-emitting control transistor M7 is connected to the fourth clock signal ECK2;

The second terminal of the eighth light-emitting control transistor M8 is connected to the fourth clock signal ECK2, and the control terminal of the eighth light-emitting control transistor M8 is connected to the first terminal of the third light-emitting control transistor M3;

The first end of the ninth light-emitting control transistor M9 is connected to the third potential signal VGH2, the second end of the ninth light-emitting control transistor M9 is connected to the output end of the gate driving unit, and the control end of the ninth light-emitting control transistor M9 is connected to the third potential signal VGH2. the second terminal of the six-transistor M6;

The first end of the tenth light-emitting control transistor M10 is connected to the output end of the gate driving unit, the second end of the tenth light-emitting control transistor M10 is connected to the fourth potential signal VGL2, and the control end of the tenth light-emitting control transistor M10 is connected to the third light-emitting control transistor M10 . a second terminal of the transistor M1;

The first emission control capacitor C3 is connected between the first terminal and the control terminal of the eighth emission control transistor M8;

The first end of the second light-emitting control capacitor C4 is connected to the control end of the tenth light-emitting control transistor M10, and the second end of the light-emitting control capacitor is connected to the fourth clock signal ECK2;

The third emission control capacitor C5 is connected between the control terminal and the first terminal of the ninth emission control transistor M9;

Among them, the eighth light-emission control transistor M8, the ninth light-emission control transistor M9, and the tenth light-emission control transistor M10 are generally larger in size than other light-emission control transistors. Therefore, the eighth light-emission control transistor M8, the ninth light-emission control transistor M10 can be The transistor M9 and the tenth luminescence control transistor M10 are arranged in the non-folding area 52; the first luminescence control capacitor C3, the second luminescence control capacitor C4 and the third luminescence control capacitor C5 are used to ensure that the gate unit outputs a stable luminescence control signal EM, Therefore, the first light-emission control capacitor C3, the second light-emission control capacitor C4, and the third light-emission control capacitor C5 can be disposed in the non-folding area 52.

It should be noted that the second gate driving unit 53_2 provided in this embodiment includes an 8T2C structure or a 10T3C structure only as an example. The second gate driving unit 53_2 may also include other structures, which is not specifically limited in this embodiment; Also, the first gate driving unit 53_1 and the second gate driving unit 53_2 may have the same structure. In addition, the second gate driving unit 53_2 of the 8T2C structure can be disposed in the display panel at the same time to output the scanning signal Scan and the second gate driving unit 53_2 of the 10T3C structure can be provided at the same time to output the light emission control signal EM, wherein the second gate of the 10T3C structure The driving unit 53_2 may be disposed at the periphery of the second gate driving unit 53_2 of the 8T2C structure.

Figure 12 is a partial enlarged view of the display panel shown in Figure 5. Based on any of the above embodiments, combined with Figure 5 and Figure 12, optionally, the display panel also includes a clock line 58, a potential line 59 and an enable line. (Not shown in the figure); each gate driving unit 53 is connected to the clock line 58, and each gate driving unit 53 is connected to the potential line 59; the clock line 58 is used to provide a clock signal, and the potential line 59 is used to provide a potential signal, so that The energy line is used to provide a start signal to the gate driving unit 53; wherein, the clock line 58, the potential line 59 and/or the enable line 51 located between two adjacent gate driving units 53 in the folding area are shown in the figure. The panel is arranged at an angle in the plane, thereby further reducing the stress concentration in the folding area 51, further softening the folding area 51, and improving the bending performance of the folding area 51.

FIG. 13 is a schematic structural diagram of a display device provided by an embodiment of the present application. Referring to FIG. 13 , an embodiment of the present application further provides a display device. The display device includes the display panel of any of the above embodiments. The display device and the display panel provided by the embodiments of this application belong to the same application concept and can achieve the same technical effect, and the repeated content will not be repeated here.

Claims (10)

1. A display panel includes a non-folding area and a folding area, and also includes:

   Multiple data lines extending along the column direction;

   A plurality of gate lines extending along the row direction; the intersection of the gate lines and the data lines defines an area where the sub-pixels are located;

   A plurality of gate driving units are arranged sequentially along the column direction; the gate driving units are connected to the corresponding gate lines, and the gate lines are electrically connected to the pixel driving circuits that drive the sub-pixels;

   Wherein, the non-folding area is arranged adjacent to the folding area, and some components of the gate driving unit located in the folding area are arranged in the non-folding area.
2. The display panel according to claim 1, wherein the non-folding area includes a device setting area and a device reserved area;

   The device reserved area is located between the device setting area and the folding area. The components of the gate driving unit located in the non-folding area are arranged in the device setting area. The components of the gate driving unit located in the folding area are located in the folding area. Some components of the gate driving unit are arranged in the device reserved area.
3. The display panel according to claim 1, wherein the gate driving unit includes a first gate driving unit and a second gate driving unit, the first gate driving unit is located in the non-folding area, and the The second gate driving unit is located in the folding area.
4. The display panel according to claim 2, wherein each of the first gate driving units is arranged at equal intervals in a direction from the non-folding area to the adjacent folding area;

   Preferably, the spacing between two adjacent first gate driving units increases sequentially in the direction from the non-folded area to the adjacent folded area;

   Optionally, in the same non-folding area, the components of the first gate driving unit that are relatively close to the adjacent folding area are placed in a manner that is relatively far from the same folding area. The components of the first gate driving unit are placed in different ways;

   Preferably, the components of the first gate driving unit that are relatively close to the folding area are arranged in m rows, and the components of the first gate driving unit that are relatively far from the folding area are arranged in m rows. Arranged in n rows; where m and n are both positive integers and m<n;

   Preferably, in the first gate driving unit that is relatively close to the folding area, the spacing between two adjacent components is a first spacing; and in the first gate driving unit that is relatively far from the folding area, In the gate driving unit, the spacing between two adjacent components is a second spacing; wherein the first spacing is smaller than the second spacing;

   Preferably, the display panel includes a display area and a non-display area, and the sub-pixel is located in the display area; the sub-pixel that is relatively close to the folding area and relatively close to the non-display area, The components in the display are arranged at non-equal intervals; some components of the first gate driving unit that are relatively close to the folding area are located in the display area.
5. The display panel according to claim 3, wherein

   A folding axis is defined in the folding area;

   Each component of the second gate driving unit located in the folding area is arranged at equal intervals;

   Preferably, in the folding area, in the direction from the folding axis to the non-folding area, the spacing between two adjacent second gate driving units shows a decreasing trend;

   Preferably, in the folding area, in the direction from the folding axis to the non-folding area, the distance between two adjacent components shows a decreasing trend, and the component is the second gate driver. components of the unit.
6. The display panel according to claim 3, wherein

   The second gate driving unit includes a plurality of thin film transistors; the size of the thin film transistors of the second gate driving unit in the non-folding area is larger than that of the second gate driving unit in the folding area. Transistor size;

   Preferably, the second gate driving unit includes a plurality of capacitors, and at least one capacitor of the second gate driving unit is disposed in the non-folding region.
7. The display panel of claim 1, wherein the gate driving unit includes:

   Scan the first transistor, scan the second transistor, scan the third transistor, scan the fourth transistor, scan the fifth transistor, scan the sixth transistor, scan the seventh transistor, scan the eighth transistor, scan the first capacitor, and scan the second capacitor;

   The first end of the first scanning transistor is connected to a first enable signal, the second end of the first scanning transistor is connected to the first end of the second scanning transistor, and the control end of the first scanning transistor is connected to Enter the first clock signal;

   The second terminal of the second scanning transistor is connected to the first terminal of the third scanning transistor, and the control terminal of the second scanning transistor is connected to the second clock signal;

   The second end of the third scanning transistor is connected to the first potential signal, and the control end of the third scanning transistor is connected to the first end of the fourth scanning transistor;

   The second terminal of the fourth scanning transistor is connected to the first clock signal, and the control terminal of the fourth scanning transistor is connected to the second terminal of the first scanning transistor;

   The first end of the fifth scanning transistor is connected to the first end of the fourth scanning transistor, the second end of the fifth scanning transistor is connected to the second potential signal, and the control end of the fifth scanning transistor is connected to the first clock signal;

   The control terminal of the sixth scanning transistor is connected to the first terminal of the fifth scanning transistor, the first terminal of the sixth scanning transistor is connected to the first potential signal, and the second terminal of the sixth scanning transistor is connected to the first terminal of the sixth scanning transistor. Connect the output end of the gate driving unit;

   The first terminal of the seventh scanning transistor is connected to the output terminal of the gate driving unit, the second terminal of the seventh scanning transistor is connected to the second clock signal, and the control terminal of the seventh scanning transistor is connected to the scanning first terminal of the eighth transistor;

   The second terminal of the eighth scanning transistor is connected to the control terminal of the fourth scanning transistor, and the control terminal of the eighth scanning transistor is connected to the second potential signal;

   The scanning first capacitor is connected between the control terminal and the first terminal of the scanning sixth transistor;

   The second scanning capacitor is connected between the control terminal and the first terminal of the seventh scanning transistor;

   Wherein, the sixth scanning transistor, the seventh scanning transistor, the first scanning capacitor and the second scanning capacitor are arranged in the non-folding area.
8. The display panel of claim 1, wherein the gate driving unit includes:

   first light emission control transistor, second light emission control transistor, third light emission control transistor, fourth light emission control transistor, fifth light emission control transistor, sixth light emission control transistor, seventh light emission control transistor, eighth light emission control transistor, light emission control a ninth transistor, a tenth light-emission control transistor, a first light-emission control capacitor, a second light-emission control capacitor, and a third light-emission control capacitor;

   The first end of the first light-emitting control transistor is connected to the second enable signal, and the second end of the first light-emitting control transistor is connected to the control end of the second light-emitting control transistor. The first light-emitting control transistor The control terminal is connected to the third clock signal;

   The first end of the second light-emitting control transistor is connected to the first clock signal, and the second end of the second light-emitting control transistor is connected to the first end of the third light-emitting control transistor;

   The second end of the third light-emitting control transistor is connected to a fourth potential signal, and the control end of the third light-emitting control transistor is connected to the third clock signal;

   The control terminal of the fourth luminescence control transistor is connected to the first terminal of the third luminescence control transistor, the first terminal of the fourth luminescence control transistor is connected to a third potential signal, and the third terminal of the fourth luminescence control transistor is connected to Two terminals are connected to the first terminal of the fifth light-emitting control transistor;

   The second end of the fifth light-emitting control transistor is connected to the second end of the first light-emitting control transistor, and the control end of the fifth light-emitting control transistor is connected to a fourth clock signal;

   The control end of the sixth light-emitting control transistor is connected to the second end of the first light-emitting control transistor, and the first end of the sixth light-emitting control transistor is connected to the third potential signal. The sixth light-emitting control transistor The second terminal is connected to the first terminal of the seventh light-emitting control transistor;

   The second end of the seventh light-emitting control transistor is connected to the first end of the eighth light-emitting control transistor, and the control end of the seventh light-emitting control transistor is connected to the fourth clock signal;

   The second end of the eighth light-emitting control transistor is connected to the fourth clock signal, and the control end of the eighth light-emitting control transistor is connected to the first end of the third light-emitting control transistor;

   The first terminal of the ninth luminescence control transistor is connected to the third potential signal, the second terminal of the ninth luminescence control transistor is connected to the output terminal of the gate driving unit, and the ninth terminal of the luminescence control transistor is connected to the third potential signal. The control terminal is connected to the second terminal of the sixth light-emitting control transistor;

   The first end of the tenth light-emitting control transistor is connected to the output end of the gate driving unit, the second end of the tenth light-emitting control transistor is connected to the fourth potential signal, and the tenth light-emitting control transistor has a second end connected to the fourth potential signal. The control terminal is connected to the second terminal of the first transistor for controlling light emission;

   The first emission control capacitor is connected between the first terminal and the control terminal of the eighth emission control transistor;

   The first end of the second light-emitting control capacitor is connected to the control end of the tenth light-emitting control transistor, and the second end of the light-emitting control capacitor is connected to the fourth clock signal;

   The third emission control capacitor is connected between the control terminal and the first terminal of the ninth emission control transistor;

   Wherein, the eighth luminescence control transistor, the ninth luminescence control transistor, the tenth luminescence control transistor, the first luminescence control capacitor, the second luminescence control capacitor and the third luminescence control capacitor are configured in the unfolded region.
9. The display panel according to claim 1, wherein the display panel further includes a clock line, a potential line and an enable line;

   Each of the gate driving units is connected to the clock line, and each of the gate driving units is connected to the potential line; the enable line is used to provide a start signal to the gate driving unit; wherein, fold The clock line, the potential line and/or the enable line located between two adjacent gate driving units in the area are arranged obliquely in the plane where the display panel is located.
10. A display device comprising the display panel according to any one of claims 1-9.

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