WO2024000643A1 - 像素电路及驱动系统 - Google Patents

像素电路及驱动系统 Download PDF

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Publication number
WO2024000643A1
WO2024000643A1 PCT/CN2022/105105 CN2022105105W WO2024000643A1 WO 2024000643 A1 WO2024000643 A1 WO 2024000643A1 CN 2022105105 W CN2022105105 W CN 2022105105W WO 2024000643 A1 WO2024000643 A1 WO 2024000643A1
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Prior art keywords
pulse signal
signal
pulse
driving
parameter
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PCT/CN2022/105105
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English (en)
French (fr)
Inventor
刘钊
陈龙
孙亮
曾勉
袁志先
李哲
Original Assignee
武汉华星光电半导体显示技术有限公司
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Publication of WO2024000643A1 publication Critical patent/WO2024000643A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements

Definitions

  • the present application relates to the field of display technology, and specifically to a pixel circuit and a driving system.
  • Light-emitting devices such as mini-LEDs, micro-LEDs, and organic light-emitting diodes have the advantages of high brightness, high contrast, and high color gamut, and have been widely used in high-performance displays.
  • the leakage phenomenon is serious.
  • the gate potential of the driving transistor will change, resulting in a large change in brightness within a frame display period under low-frequency driving, causing flickering ( Flicker), affecting the display quality of the display device.
  • This application provides a pixel circuit and a driving system to solve the technical problem in the prior art that display panels are prone to flickering under low-frequency driving.
  • This application provides a pixel circuit, which includes:
  • a driving module connected to the light-emitting device to drive the light-emitting device to emit light
  • the lighting control module is connected to the driving module.
  • the lighting control module, the lighting device and the driving module are all connected in series between the first power signal and the second power signal.
  • the control terminal of the lighting control module is connected to the driving module. Enter the lighting control signal;
  • the light-emitting control signal includes at least one pulse signal
  • the light-emitting control module turns off the light-emitting device under the action of the pulse signal
  • the pulse signal is set according to the spectrum of the brightness waveform of a frame display period.
  • the lighting control signal further includes a first reference pulse signal and a second reference pulse signal, the first reference pulse signal is located at the beginning of a frame display period, and the The second reference pulse signal is located at at least one time equal point of a frame display period;
  • the pulse signal there is a time interval between any two of the pulse signal, the first reference pulse signal and the second reference pulse signal, or the pulse signal is different from the first reference pulse signal or the second reference pulse signal.
  • the second reference pulse signal is partially overlapped and set.
  • the pixel circuit operates in one of multiple driving modes, the refresh frequency of each driving mode is different, and the light-emitting control signal is Each driving mode has a corresponding set of pulse signals.
  • the pixel circuit operates at least in a first driving mode or a second driving mode, and the refresh frequency of the first driving mode is smaller than the refresh frequency of the second driving mode;
  • the number of the pulse signals in the first driving mode is greater than or equal to the number of the pulse signals in the second driving mode.
  • the refresh frequency when the refresh frequency is 15 Hz, the number of pulse signals is no less than 5, and when the refresh frequency is 20 Hz, the number of pulse signals is no less than 5.
  • the number of pulse signals is not less than 5.
  • the refresh frequency is 30 Hz, the number of pulse signals is not less than 1.
  • the pulse signal is set corresponding to a low-frequency component in the spectrum of the brightness waveform of one frame display period, and the frequency of the low-frequency component is less than 60 Hz.
  • a frame display period includes a first display stage and a second display stage, the display brightness of the first display stage is greater than the display brightness of the second display stage, and the pulse The distribution density of the signal in the first display stage is greater than the distribution density of the pulse signal in the second display stage.
  • this application also provides a driving system, which includes a signal generation module, the signal generation module having an output terminal, the output terminal being used to output the light-emitting control signal in any of the above-mentioned pixel circuits. .
  • the signal generation module includes a storage unit and a pulse signal generation unit
  • the storage unit is used to store parameter information of the pulse signal
  • the pulse signal generation unit is connected to the storage unit
  • the pulse signal generation unit is used to generate the pulse signal according to the parameter information.
  • the parameter information includes pulse starting position control parameters, pulse step type control parameters, pulse starting position parameters, and pulse ending position parameters.
  • the pulse signal generating unit includes a counter, a first judgment subunit and a second judgment subunit;
  • the counter is used to count according to the pulse starting position control parameter and the pulse step type control parameter to obtain the first parameter; the first judgment subunit combines the first parameter with the pulse
  • the starting position parameter is compared. If the first parameter is less than the pulse starting position parameter, the counter continues counting. If the first parameter is equal to the pulse starting position parameter, the pulse signal is determined. The starting position of If the first parameter is equal to the pulse end position parameter, then the end position of the pulse signal is determined.
  • the storage unit stores multiple sets of parameter information, each set of parameter information corresponds to a refresh frequency, and the pulse signal generating unit obtains corresponding data according to different refresh frequencies. of the parameter information.
  • the signal generation module further includes a start signal generation unit and a GOA circuit
  • the pulse signal generation unit is provided in the start signal generation unit, and the start signal The generation unit is used to generate a start signal including the pulse signal.
  • the GOA circuit is connected to the start signal generation unit.
  • the GOA circuit is used to generate a multi-level signal according to the start signal including the pulse signal.
  • the lighting control signal is used to generate a multi-level signal according to the start signal including the pulse signal.
  • the driving system further includes a driving chip, and the start signal generating unit is provided in the driving chip.
  • the signal generation module further includes a first GOA circuit, the first GOA circuit is connected to the pulse signal generation unit, and the first GOA circuit is used to generate a multi-level the pulse signal.
  • the pixel circuit includes a driving module, a light-emitting control module and a light-emitting device.
  • the light-emitting control module, the light-emitting device and the driving module are all connected in series between the first power signal and the second power signal.
  • the control of the light-emitting control module The terminal receives the lighting control signal.
  • This application adds at least one pulse signal to the light-emitting control signal. Since the light-emitting control module is turned off under the action of the pulse signal and the light-emitting device does not emit light, the pulse signal is set according to the spectrum of the brightness waveform of one frame display period, which can reduce the pulse signal.
  • the luminous brightness of the corresponding time period is reduced, thereby reducing the low-frequency component in the brightness spectrum of one frame display period, and improving the flicker perception and value.
  • Figure 1 is a schematic structural diagram of a pixel circuit provided by this application.
  • Figure 2 is a signal timing diagram of the pixel circuit shown in Figure 1 provided by this application;
  • Figure 3 is a schematic diagram of the brightness change of the display panel provided by this application within one frame display period
  • Figure 4 is a first structural schematic diagram of the pixel circuit provided by this application.
  • FIG. 5 is a timing diagram of the lighting control signal provided by this application.
  • Figure 6 is a schematic diagram of the frequency characteristics of an integrator used to process brightness signals provided by this application.
  • FIG. 7 is a schematic structural diagram of a GOA circuit provided by this application.
  • Figure 8 is a schematic diagram of the original driving brightness waveform and its brightness spectrum at a refresh frequency of 30Hz provided by this application;
  • Figure 9 is a schematic diagram of the brightness waveform increment and its brightness spectrum caused by the pulse signal at the 30Hz refresh frequency provided by this application;
  • Figure 10 is a schematic diagram of the new driving brightness waveform and its brightness spectrum at a refresh frequency of 30Hz provided by this application;
  • Figure 11 is a schematic diagram of the original driving brightness waveform and its brightness spectrum at a refresh frequency of 10Hz provided by this application;
  • Figure 12 is a schematic diagram of the brightness waveform increment and its brightness spectrum caused by the pulse signal at the 10Hz refresh frequency provided by this application;
  • Figure 13 is a schematic diagram of the new driving brightness waveform and its brightness spectrum at a refresh frequency of 10Hz provided by this application;
  • Figure 14 is a first structural schematic diagram of the driving system provided by this application.
  • FIG. 15 is a schematic structural diagram of the signal generation module provided by this application.
  • FIG 16 is a schematic structural diagram of the pulse signal generation unit provided by this application.
  • Figure 17 is a schematic flow chart for determining pulse starting position parameters provided by this application.
  • Figure 18 is a schematic flow chart for determining pulse termination position parameters provided by this application.
  • Figure 19 is a signal timing diagram of a start signal provided by this application and a start signal including a pulse signal;
  • Figure 20 is a second structural schematic diagram of the drive system provided by this application.
  • Figure 21 is a third structural schematic diagram of the driving system provided by this application.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as “first”, “second”, etc. may explicitly or implicitly include one or more of the described features, and therefore cannot be construed as a limitation of the present application.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by this application.
  • FIG. 2 is a signal timing diagram of the pixel circuit shown in FIG. 1 provided by this application.
  • the driving timing of the pixel circuit 10 includes a reset phase t1, a data writing and compensation phase t2, and a light emitting phase t3.
  • the n-1th level scanning signal S(n-1) is at a low level
  • the third transistor T3 and the sixth transistor T6 are turned on
  • the gate of the driving transistor Td and the anode of the light-emitting device D are reset to reset. Voltage Vi.
  • the enable signal EM and the n-th level scan signal S(n) are at high potential, the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are all turned off, and the light-emitting device D does not emit light.
  • the n-th level scanning signal S(n) is at a low level
  • the first transistor T1, the second transistor T2, and the driving transistor Td are all turned on
  • the data voltage Da passes through the first transistor T1 and the driving transistor Td.
  • the second transistor T2 charges the gate of the driving transistor Td.
  • Vth is the threshold voltage of the driving transistor Td
  • the driving transistor Td is turned off, the gate potential of the driving transistor Td no longer rises, and the threshold voltage is stored in the storage capacitor Cst.
  • threshold voltage compensation of the driving transistor Td is achieved.
  • the enable signal EM still maintains a high potential
  • the fourth transistor T4 and the fifth transistor T5 are both turned off, and the light-emitting device D does not emit light.
  • the enable signal EM changes from high potential to low potential, and both the fourth transistor T4 and the fifth transistor T5 are turned on.
  • the power supply voltage VDD begins to charge the anode of the light-emitting device D.
  • the light-emitting device D starts to emit light.
  • both the second transistor T2 and the third transistor T3 are connected to the gate of the driving transistor Td, the leakage current characteristics of the two transistors will directly affect the brightness stability of the light-emitting phase t3.
  • the leakage current of the LTPS (Low Temperature Poly-Silicon) transistor commonly used in OLED (Organic Light-Emitting Diode, organic light-emitting diode) displays is large, and the gate potential of the driving transistor Td will change, resulting in low-frequency When driven, the brightness within one frame display period will change greatly and flicker will occur.
  • FIG. 3 is a schematic diagram of the brightness change of the display panel provided by the present application within one frame display period.
  • the dotted line P represents the target brightness of the display panel within one frame display period.
  • Curve Q represents the actual brightness change trend of the display panel within one frame display period. It can be seen from Figure 3 that within one frame display period, the brightness change amount of the display screen is ⁇ L. The change amount is large and flickering is easy to occur.
  • Figure 4 is a first structural schematic diagram of the pixel circuit provided by this application.
  • FIG. 5 is a timing diagram of the lighting control signal provided by this application.
  • the pixel circuit 10 includes a driving module 10a, a light emitting control module 10b and a light emitting device D.
  • the light-emitting control module 10b, the light-emitting device D and the driving module 10a are all connected in series between the first power signal VDD and the second power signal VSS.
  • the control terminal of the lighting control module 10b is connected to the lighting control signal EM.
  • the driving module 10a at least includes a driving transistor Td.
  • the light emission control module 10b includes at least a light emission control transistor T0.
  • the source and drain of the driving transistor Td, the source and drain of the light-emitting control transistor T0, and the light-emitting device D are all connected in series between the first power signal VDD and the second power signal VSS.
  • the gate of the light emission control transistor T0 is connected to the light emission control signal EM.
  • the light emission control signal EM includes at least one pulse signal C.
  • the light emission control transistor T0 is turned off under the action of the pulse signal C.
  • the pulse signal C is set according to the spectrum of the brightness distribution of one frame display period.
  • the spectrum of the brightness distribution of one frame of display period refers to: collecting the brightness signal of the display panel during one frame of display period, and converting the brightness signal into a digital signal. All digital signals are then Fourier transformed to obtain a set of amplitudes of signals with different frequencies. Or, continuously collect the brightness signals of multiple frames of the display panel within a period of time, and convert all the brightness signals into digital signals. All digital signals are then Fourier transformed to obtain a set of amplitudes of signals with different frequencies.
  • the spectrum of the brightness distribution is simply referred to as the brightness spectrum.
  • the first power signal VDD and the second power signal VSS are both used to output a preset voltage value.
  • the potential of the first power signal VDD is greater than the potential of the second power signal VSS.
  • the potential of the second power signal VSS may be the potential of the ground terminal.
  • the potential of the second power signal VSS can also be other values.
  • At least one pulse signal C is added to the light-emitting control signal EM. Since the light-emitting control module 10b is turned off under the action of the pulse signal C and the light-emitting device D does not emit light, the pulse is set according to the spectrum of the brightness waveform of one frame display period. Signal C can reduce the luminous brightness in the time period corresponding to the pulse signal, thereby reducing the low-frequency component in the brightness spectrum of one frame display period and improving the flicker perception and value.
  • FIG. 6 is a schematic diagram of the frequency characteristics of an integrator for processing brightness signals provided by this application.
  • the abscissa is frequency
  • the unit is Hertz (Hz).
  • the ordinate is level
  • the unit dB is a numerical value without any unit label.
  • the frequency characteristics of the integrator are the same as the response characteristics of human vision to different frequencies.
  • the frequency is below 60Hz, the level increases sharply. That is, during a frame display period, the brightness changes with time. Fourier transform of the brightness time domain signal can obtain different frequency components of the signal.
  • the human eye has different sensitivity values to different frequency components. For example, in the range of less than 60Hz, when the brightness amplitude is the same, the higher the frequency, the lighter and less sensitive the human eye's flickering experience. That is to say, the human eye is sensitive to flickers with frequencies below 60Hz in the brightness spectrum.
  • the display panel has a low refresh rate (such as ⁇ 60Hz)
  • a low refresh rate such as ⁇ 60Hz
  • the brightness spectrum will have a large amplitude component at low frequencies (such as ⁇ 60Hz)
  • the flicker value will Larger, the human eye will also notice the flicker clearly.
  • the position with high brightness corresponds to the peak phase of the low-frequency component.
  • some embodiments of the present application set the pulse signal C to correspond to the low-frequency component in the brightness spectrum of one frame display period, and the frequency of the low-frequency component is less than 60 Hz. Since the light-emitting control transistor T0 is turned off under the action of the pulse signal C, the light-emitting device D does not emit light, thereby reducing the light-emitting brightness in the time period corresponding to the pulse signal C, thereby reducing the low-frequency component in the brightness spectrum of one frame display period. , to improve the flicker look and feel and value.
  • the range of the low frequency in the low frequency component can also be set according to the flicker specification requirements of the display panel in actual applications, which is not specifically limited in this application.
  • LTPO Low Temperature Polycrystalline Oxide
  • IGZO Indium Gallium Zinc Oxide
  • Embodiments of the present application may use only LTPS transistors, and do not need to combine LTPS transistors and IGZO transistors.
  • the structure and process of the pixel circuit 10 are simpler, which effectively reduces the cost.
  • the pixel circuit 10 may be the pixel circuit 10 shown in FIG. 1 .
  • the pixel circuit 10 shown in FIG. 1 is only an example and cannot be understood as limiting the present application.
  • the embodiment of the present application takes as an example that each transistor is a P-type transistor, but each transistor may also be an N-type transistor, a dual-gate transistor, etc.
  • the pixel circuit 10 may also include other types of threshold voltage compensation structures or power supply voltage VDD compensation structures, which are not limited in this application.
  • the light-emitting control module 10b may include the transistor T4 and/or the transistor T5 in FIG. 1, as long as the conditions for the light-emitting control module 10b to control the light-emitting device D to emit or not emit under the control of the light-emitting control signal EM are met. That’s it.
  • the light emission control signal EM can be obtained by superimposing the pulse signal C on the enable signal EM(n).
  • the light emission control signal EM can also be obtained by superimposing the pulse signal C on other signals that can control the light emission of the light emitting device D.
  • the GOA circuit 30 includes multiple levels of cascaded GOA units 31 .
  • the GOA circuit 30 is used to generate multi-level enable signals, such as the first-level enable signal EM(1), based on the clock signal The second level enable signal EM(2), the third level enable signal EM(3), the n-1th level enable signal EM(n-1), the nth level enable signal EM(n), etc.
  • the first reference pulse signal A and the second reference pulse signal B exist in the start signal STV_EM.
  • the start signal STV_EM is transmitted through 30 stages of the GOA circuit, and the enable signal EM(n) of each stage is output.
  • Each stage enable signal EM(n) has the same waveform as the start signal STV_EM, but there is a time offset. Therefore, the signal timing of the start signal STV_EM determines the timing of the enable signal EM(n).
  • the pulse signal C can be added to the start signal STV_EM timing sequence, so that the enable signal EM(n) output by the GOA circuit 30 also includes the pulse signal C, that is, the light-emitting control signal EM is formed.
  • the pulse signal C since the function of the pulse signal C is to add a non-luminous time period within a frame display period according to the pulse signal C in the original driving brightness waveform, the pulse signal C can be generated by the enable signal EM(n) in addition to In addition to the GOA circuit 30 provided, a group of GOA circuits can also be used to generate the GOA circuit alone, or other GOA circuits that generate other signals that can control the light-emitting state of the light-emitting device D can be added. This application does not limit this.
  • each of the following embodiments of the present application takes as an example that the light-emission control transistor T0 is a P-type transistor and the light-emission control signal EM is obtained by superimposing the pulse signal C with the enable signal EM(n).
  • the light-emission control transistor T0 is a P-type transistor and the light-emission control signal EM is obtained by superimposing the pulse signal C with the enable signal EM(n).
  • the light emission control signal EM also includes a first reference pulse signal A and a second reference pulse signal B.
  • the first reference pulse signal A is located at the beginning of a frame display period.
  • the second reference pulse signal B and the first reference pulse signal A are located at at least one time equal point of a frame display period.
  • the time equal points refer to the 2nd equal points, the 3rd equal points, the 4th equal points, the 32nd equal points, etc. of a frame display period.
  • the first reference pulse signal A and the second reference pulse signal B constitute the enable signal EM(n).
  • the pixel circuit 10 is in the reset phase t1 and the data writing and compensation phase t2 to perform reset and compensation charging.
  • the first reference pulse signal A is a high-level pulse
  • the light-emitting control transistor T0 is turned off, and the light-emitting device D does not emit light.
  • the original enable signal EM(n) remains at a low level, and the light-emitting device D emits light.
  • the light-emitting device D does not emit light during the action period of the second reference pulse signal B.
  • the second reference pulse signal B is used to adjust the screen brightness using PWM (Pulse Width Modulation, pulse width modulation) technology.
  • display panels of the same model generally use the same first reference pulse signal A and second reference pulse signal B.
  • the pulse signal C can be independently adjusted for each display panel to achieve the best flicker reduction effect. That is, the pixel circuit 10 can be applied in multiple display panels, and the light emission control signal EM can have a corresponding set of pulse signals C in each display panel.
  • the position with high brightness corresponds to the peak phase of the low-frequency component. Therefore, more pulse signals C can be set in the period of higher brightness in each frame display period. For example, for a brightness waveform in which the brightness gradually decreases within a frame display period, the pulse signal C is more concentrated at the front of the frame period. For a brightness waveform in which the brightness gradually increases within a frame display period, the pulse signal C is more concentrated at a later time within a frame. For an arbitrary-shaped brightness waveform, the pulse signal C is more concentrated near the maximum value of the brightness waveform.
  • one frame display period can be set to include a first display stage and a second display stage according to the brightness distribution of one frame display period.
  • the display brightness in the first display stage is greater than the display brightness in the second display stage.
  • the distribution density of the pulse signal C in the first display stage is set to be greater than the distribution density of the pulse signal C in the second display stage, thereby simplifying the setting step of the pulse C.
  • multiple display stages can be set according to the actual brightness distribution, and this application does not specifically limit this.
  • the pixel circuit 10 can operate in multiple driving modes.
  • Each driving mode corresponds to a refresh frequency.
  • the refresh frequency refers to the number of times the screen frame is refreshed per second, that is, the number of frame display cycles per second.
  • the lighting control signal EM may include a set of pulse signals C with different positions, pulse widths, and numbers. Among them, “multiple" refers to two or more than two.
  • the pixel circuit 10 can operate in the first driving mode or the second driving mode.
  • the refresh frequency of the first driving mode is lower than the refresh frequency of the second driving mode.
  • the number of pulse signals C in the first driving mode is greater than or equal to the number of pulse signals C in the second driving mode.
  • the refresh frequency of the first driving mode is lower than the refresh frequency of the second driving mode
  • the duration of the lighting phase t3 of one frame display period in the first driving mode is longer than that in the second driving mode.
  • the longer the lighting time the greater the change in lighting brightness due to leakage and other reasons, and the greater the possibility of flickering. Therefore, by setting the number of pulse signals C in the first driving mode to be greater than or equal to the number of pulse signals C in the second driving mode, different pulse signals C can be set in the light-emitting control signal EM in different driving modes, Thereby better improving flicker.
  • the refresh frequency when the refresh frequency is 10 Hz, the number of pulse signals C in one frame display period is no less than 10. When the refresh frequency is 15Hz, the number of pulse signals C within one frame display period is no less than 5. When the refresh frequency is 20Hz, the number of pulse signals C in one frame display period is no less than 5. When the refresh frequency is 30Hz, the number of pulse signals C within one frame display period is no less than one.
  • the embodiments of the present application are not listed here one by one.
  • the number of pulse signals C may be one or more.
  • the start time and end time of each pulse signal C can appear at any position in a frame display period.
  • the pulse signal C may be arranged to at least partially overlap with the first reference pulse signal A or to at least partially overlap with the second reference pulse B.
  • the pulse signal C has a time interval with both the first reference pulse signal A and the second reference pulse signal.
  • the position, pulse width and pulse number of the pulse signal C in the light emission control signal EM are determined by the original driving brightness waveform.
  • the original driving brightness waveform refers to the brightness waveform driven by the enable signal EM(n) excluding the pulse signal C.
  • the low-frequency component in the brightness spectrum obtained by Fourier transformation of the original driving brightness waveform determines the position, pulse width and pulse number of the pulse signal C in the light emission control signal EM.
  • the pulse signal C is introduced into the light emission control signal EM, compared with the original driving brightness waveform, under the action of the pulse signal C, a new brightness change, that is, a brightness waveform increment, will be introduced.
  • the low-frequency component in the spectrum of the original driving brightness waveform and the low-frequency component in the brightness increment spectrum introduced by the pulse signal C should have the same amplitude as much as possible and the opposite phase as much as possible at the same frequency.
  • the low-frequency amplitude component in the spectrum of the original driving brightness waveform can be eliminated or reduced, thereby reducing the flicker value and reducing the perception of flicker to the human eye.
  • the acquisition method of the position, pulse width and quantity of the pulse signal C may include the following steps:
  • a brightness measuring instrument such as a luminance meter can be used to detect the brightness in one frame display period to obtain a brightness signal, and convert the brightness signal into a digital signal to obtain the original driving brightness waveform.
  • the principle and process of Fourier transforming the original driving brightness waveform are techniques well known to those skilled in the art, and will not be described again here.
  • the brightness spectrum of the original driving brightness waveform can be obtained through Fourier transform.
  • the brightness spectrum includes frequency domain amplitude information and frequency domain phase information. From this, the amplitude and phase of each low-frequency ( ⁇ 60Hz) component in the brightness spectrum of the original driving brightness waveform can be obtained.
  • each low-frequency component match the negative increment of the brightness waveform with equal amplitude and opposite phase.
  • negative value increments of the brightness waveform with equal amplitude and opposite phase can be matched respectively. You can also take part of the low-frequency components, and then match the negative increments of the brightness waveform with equal amplitude and opposite phase according to the amplitude and phase of each low-frequency component.
  • the position, pulse width and number of the pulse signal C can be determined based on the position, width and number of negative increments of the brightness waveform. Then it is superimposed on the enable signal EM(n) or other signals that can control the light emitting device D to emit light, and the light emitting control signal EM can be obtained.
  • the refresh frequency is 30 Hz as an example for description.
  • Figure 8 is a schematic diagram of the original driving brightness waveform and its brightness spectrum at a refresh frequency of 30Hz provided by this application.
  • Figure 9 is a schematic diagram of the brightness waveform increment and its brightness spectrum caused by the pulse signal at a refresh frequency of 30Hz provided by this application.
  • Figure 10 is a schematic diagram of the new driving brightness waveform and its brightness spectrum at a refresh frequency of 30Hz provided by this application.
  • Figure (a) is the original driving brightness waveform
  • Figure (b) is the frequency domain amplitude spectrum of the original driving brightness waveform
  • Figure (c) is the frequency domain phase spectrum of the original driving brightness waveform.
  • Figure (d) shows the brightness waveform increment introduced by the pulse signal C
  • Figure (e) shows the frequency domain amplitude spectrum of the brightness waveform increment
  • Figure (f) shows the frequency domain phase spectrum of the brightness waveform increment.
  • Figure (g) shows the new drive brightness waveform, that is, the brightness waveform obtained by driving the pulse signal C superimposed on the original drive.
  • Figure (h) shows the frequency domain amplitude spectrum of the new drive brightness waveform.
  • Figure (i) is the frequency domain phase spectrum of the new driving brightness waveform.
  • the original driving brightness waveform has a frequency component with an amplitude of 31.29 and a phase of -90.45° at the 30Hz frequency.
  • the number of additional pulse signals C is 4.
  • the position and pulse width of each pulse signal C can be seen in Figure (d).
  • the brightness waveform increment has a frequency component with an amplitude of 31.18 and a phase of 90.49° at a frequency of 30Hz.
  • the amplitude of the low-frequency component of the brightness waveform increment introduced by the pulse signal C is close to the same as the low-frequency component of the original driving brightness waveform, and the phase is close to opposite.
  • the original brightness waveform and the brightness waveform are superimposed, and the component amplitude of the new driving brightness waveform at the 30Hz frequency is 0.52.
  • the component amplitude at the 30Hz frequency domain is reduced to 1/60 of the original value. Therefore, the setting of the pulse signal C can eliminate or reduce the low-frequency amplitude component of the original driving brightness waveform, thereby reducing the flicker perception of the human eye and reducing the Flicker value.
  • the Flicker JEITA value of the original driver calculated by the JEITA method is -21.9dB
  • the Flicker JEITA value of the new driver is -56.72dB. It can be seen that the flicker has been well improved.
  • the JEITA method calculates Flicker flicker values based on the amplitudes of signals of different frequencies. It is characterized by being more in line with the human eye's perception of different flicker frequencies, and the measurement results are more objective and stable.
  • the refresh frequency is 10 Hz as an example for description.
  • Figure 11 is a schematic diagram of the original driving brightness waveform and its brightness spectrum at a refresh frequency of 10Hz provided by this application.
  • Figure 12 is a schematic diagram of the brightness waveform increment and its brightness spectrum caused by the pulse signal at a refresh frequency of 10Hz provided by this application.
  • Figure 13 is a schematic diagram of the new driving brightness waveform and its brightness spectrum at a refresh frequency of 10Hz provided by this application.
  • Figure (a) is the original driving brightness waveform
  • Figure (b) is the frequency domain amplitude spectrum of the original driving brightness waveform
  • Figure (c) is the frequency domain phase spectrum of the original driving brightness waveform.
  • Figure (d) shows the brightness waveform increment introduced by the pulse signal C
  • Figure (e) shows the frequency domain amplitude spectrum of the brightness waveform increment
  • Figure (f) shows the frequency domain phase spectrum of the brightness waveform increment.
  • Figure (g) shows the new drive brightness waveform, that is, the brightness waveform obtained by driving the pulse signal C superimposed on the original drive.
  • Figure (h) shows the frequency domain amplitude spectrum of the new drive brightness waveform.
  • Figure (i) is the frequency domain phase spectrum of the new driving brightness waveform.
  • the frequency component amplitudes of the original driving brightness waveform at frequencies of 10Hz, 20Hz, 30Hz, 40Hz and 50Hz are all larger, with amplitudes of 31.31, 31.31 and 50Hz respectively. 15.91, 11.11, 11.41 and 5.83.
  • the number of additional pulse signals C is 20.
  • the position and pulse width of each pulse signal C can be seen in Figure (d).
  • the frequency component amplitudes of the new driving brightness waveform at the frequencies of 10Hz, 20Hz, 30Hz, 40Hz and 50Hz are all smaller.
  • the values are 1.35, 1.06, 1.86, 0.99 and 1.32 respectively.
  • the original driver Flicker JEITA value is -18.91dB, and the new driver Flicker JEITA value is -44.75dB. Therefore, the setting of the pulse signal C can eliminate or reduce the low-frequency amplitude component of the original driving brightness waveform, thereby reducing the flicker perception of the human eye and reducing the Flicker value.
  • FIG 14 is a first structural schematic diagram of the drive system provided by this application.
  • An embodiment of the present application provides a driving system 100.
  • the drive system 100 includes a signal generation module 20 .
  • the signal generation module 20 has an output terminal 20a.
  • the output terminal 20a is used to output the light emission control signal EM in the pixel circuit 10 described in any of the above embodiments.
  • FIG. 15 is a schematic structural diagram of the signal generation module provided by the present application.
  • the signal generation module 20 includes a storage unit 21 and a pulse signal generation unit 22 .
  • the storage unit 21 is used to store parameter information of the pulse signal C.
  • the pulse signal generating unit 22 is connected to the storage unit 21 to obtain the parameter information of the pulse signal C.
  • the pulse signal generating unit 22 is used to generate the pulse signal C according to the parameter information.
  • the storage unit 21 may be MIPI (Mobile Industry Processor Interface, mobile industry processor interface) register, ROM (Read-Only Memory, read-only memory) or external Flash IC (flash memory chip).
  • MIPI Mobile Industry Processor Interface, mobile industry processor interface
  • ROM Read-Only Memory, read-only memory
  • Flash IC flash memory chip
  • the parameter information can be obtained according to the acquisition method of the position, pulse width and quantity of the pulse signal C in the previous embodiment, which will not be described again here.
  • the parameter information can be stored in the storage unit 21 through OTP (One Time Programmable, one-time programmable) programming or Flash programming when the display device is produced.
  • OTP One Time Programmable, one-time programmable
  • the storage unit 21 can store multiple sets of parameter information, and each set of parameter information corresponds to a refresh frequency.
  • the pulse signal generating unit 22 obtains corresponding parameter information according to different refresh frequencies.
  • the driving system 100 may include multiple driving modes, and each driving mode corresponds to a different refresh frequency. It can be known from the foregoing embodiments that under different refresh frequencies, the position, pulse width and number of the pulse signals C included in the lighting control signal EM may be different. Therefore, this embodiment of the present application stores multiple sets of parameter information in the storage unit 21 . When the driving system 100 adopts different refresh frequencies, the pulse signal generating unit 22 can obtain the corresponding parameter information and generate the corresponding pulse signal C, thereby improving the switching efficiency of the driving system 100 under different refresh frequencies.
  • the parameter information of the pulse signal C may include a pulse starting position control parameter, a pulse step type control parameter, a pulse starting position parameter, and a pulse ending position parameter.
  • the pulse starting position control parameter is used to control the starting position reference point of the pulse signal C.
  • the reference point can be a frame synchronization signal or a frame blanking signal, and can be defined by a minimum data bit.
  • the pulse step type control parameter can be understood as a counting unit.
  • the pulse step type can be a horizontal synchronization duration or a high-level pulse of a clock signal, and the minimum can be defined by one data bit.
  • the counter can be incremented by one every time the rising edge of the clock signal comes.
  • the pulse starting position parameter refers to the rising edge position or falling edge position of the pulse signal C. Because the embodiment of the present application takes the transistor as a P-type transistor as an example, the pulse starting position parameter here refers to the rising edge position of the pulse signal C.
  • the light emission control signal EM may include N pulse signals C.
  • N is an integer greater than or equal to 1.
  • Each pulse signal C has a pulse starting position parameter.
  • the starting position parameter of pulse i describes the starting time position of the i-th pulse signal C, and each parameter is a fixed data bit length.
  • i is an integer greater than or equal to 1 and less than or equal to N.
  • the bit length is 24, and the time range that can be represented is 0 ⁇ 16777215. The units of each number are determined by the pulse step type control parameter.
  • the pulse end position parameter refers to the rising edge position or falling edge position of the pulse signal C. Because the embodiment of the present application takes the transistor as a P-type transistor as an example, the pulse termination position parameter here refers to the falling edge position of the pulse signal C.
  • the light emission control signal EM may include N pulse signals C.
  • N is an integer greater than or equal to 1.
  • Each pulse signal C has a pulse end position parameter.
  • the end position parameter of pulse i describes the time position of the end of the i-th pulse signal C, and each parameter is a fixed data bit length.
  • the bit length is 24, and the time range that can be represented is 0 ⁇ 16777215. The units of each number are determined by the pulse step type control parameter.
  • the pulse end position parameter and the pulse start position parameter work in pairs.
  • FIG. 16 is a schematic structural diagram of the pulse signal generating unit provided by the present application.
  • the pulse signal generation unit 22 includes a counter 221, a first judgment sub-unit 222 and a second judgment sub-unit 223.
  • the counter 221 counts according to the pulse starting position control parameter and the pulse step type control parameter to obtain the first parameter.
  • the first judgment subunit 222 compares the first parameter with the pulse starting position parameter. If the first parameter is less than the pulse starting position parameter, the counter 221 continues counting. If the first parameter is equal to the pulse starting position parameter, the pulse is determined. The starting position of the signal.
  • the second judgment subunit 223 compares the first parameter with the pulse end position parameter. If the first parameter is less than the pulse end position parameter, the counter 221 continues counting. If the first parameter is equal to the pulse end position parameter, the termination of the pulse signal is determined. Location.
  • Figure 17 is a schematic flow chart for determining pulse starting position parameters provided by this application.
  • Figure 18 is a schematic flowchart of determining pulse termination position parameters provided by this application.
  • the embodiment of the present application takes the i-th pulse signal C as an example for description, but this should not be understood as a limitation of the present application.
  • the counter 221 starts counting according to the pulse start position control parameter. Counting is then performed based on the pulse step type control parameters.
  • the first judgment subunit 222 compares the count value with the pulse i starting position parameter. If the counting value is less than the pulse i starting position parameter, the counter 221 continues counting and the count value is +1. If the count value is equal to the pulse i starting position parameter, the starting position of the pulse signal is determined. At this time, if the start signal STV_EM is low level, the start signal STV_EM changes from low level to high level, that is, the rising edge position of pulse i is determined. If the start signal STV_EM is at a high level, for example, the second pulse signal B in the start signal STV_EM exists at this position, the start signal STV_EM remains at a high level.
  • the counter 221 continues counting, and the second judgment subunit 223 compares the count value with the pulse end position parameter. If the count value is less than the pulse end position parameter, the counter 221 continues counting. If the count value is equal to the pulse end position parameter, the end position of the pulse signal is determined. At this time, if the start signal STV_EM) is high level, the start signal STV_EM changes from high level to low level, that is, the falling edge position of pulse i is determined. If the start signal STV_EM is low level, the start signal STV_EM remains low level.
  • the refresh frequency is 30 Hz as an example for explanation.
  • a start signal STV_EM including the pulse signal C can be obtained.
  • the first pulse signal C is inserted in the t1-t2 time period
  • the second pulse signal C is inserted in the t3-t4 time period
  • the second pulse signal C is inserted in the t5-t6 time period.
  • the third pulse signal C is inserted in the time period
  • the fourth pulse signal C is inserted in the t7-t8 time period. It can be seen that both the second pulse signal C and the third pulse signal C partially overlap with the second reference pulse signal B.
  • the signal generation module 20 also includes a start signal generation unit 41 and a GOA circuit 30 .
  • the pulse signal generating unit 22 is provided in the start signal generating unit 41.
  • the start signal generating unit 41 is used to generate a start signal STV_EM including the pulse signal C.
  • the GOA circuit 30 is connected to the start signal generating unit 41.
  • the GOA circuit 30 generates a multi-level light emission control signal EM based on the start signal number STV_EM including the pulse signal C.
  • the multi-level light emission control signals EM are transmitted to different pixel circuits 10 respectively.
  • the driving system 100 also includes a driving chip 40 .
  • the start signal generating unit 41 is provided in the driver chip 40 .
  • the driving chip 40 is a chip used to drive the display panel to display images.
  • One of the functions of the driver chip 40 is to generate the start signal STV_EM.
  • the GOA circuit 30 generates the multi-level enable signal EM(n) according to the start signal STV_EM.
  • the pulse signal C is superimposed on the start signal STV_EM, and the start signal STV_EM including the pulse signal C can be obtained. Then, the GOA circuit 30 may generate the multi-level lighting control signal EM according to the start signal STV_EM of the pulse signal C.
  • the signal generation module 20 includes a first GOA circuit 50 .
  • the first GOA circuit 50 is connected to the pulse signal generating unit 22 .
  • the first GOA circuit 50 is used to generate a multi-level pulse signal C.
  • the first GOA circuit 50 and the GOA circuit 30 in FIG. 20 are independent of each other. It can be understood that since the function of the pulse signal C is to add a non-luminous time period to the original brightness waveform according to the position of the pulse signal C within a frame display period, the pulse signal C can be provided by the GOA circuit 30, It can also be generated by using a group of first GOA circuits 50 alone.
  • a group of first GOA circuits 50 are used alone to generate a multi-level pulse signal C, and the light-emitting state of the light-emitting device D in the pixel circuit 10 can be directly controlled by the pulse signal C.
  • the control accuracy of the pulse signal C on the luminous brightness of one frame display period can be improved.

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Abstract

一种像素电路(10)及驱动系统(100)。在像素电路(10)，发光控制模块(10b)、发光器件(D)以及驱动模块(10a)均串联在第一电源信号(VDD)和第二电源信号(VSS)之间，发光控制模块(10b)的控制端接入发光控制信号(EM)。发光控制信号(EM)包括至少一脉冲信号，发光控制模块(10b)在脉冲信号的作用下关闭发光器件(D)，脉冲信号根据一帧显示周期的亮度波形的频谱设置。

Description

像素电路及驱动系统 技术领域
本申请涉及显示技术领域，具体涉及一种像素电路及驱动系统。
 背景技术
迷你发光二极管、微型发光二极管以及有机发光二极管等发光器件具有高亮度、高对比度及高色域等优点，目前已被广泛地应用于高性能显示领域中。在现有的像素电路中，漏电现象较为严重。后续在发光器件的发光过程中，由于漏电流的原因，驱动晶体管的栅极电位会发生改变，从而导致在低频驱动的情况下，一帧显示周期内的亮度产生较大的变化，出现闪烁（Flicker），影响显示装置的显示画质。
 技术问题
本申请提供一种像素电路及驱动系统，以解决现有技术中显示面板在低频驱动下易出现闪烁的技术问题。
 技术解决方案
本申请提供一种像素电路，其包括：
发光器件；
驱动模块，连接于所述发光器件以驱动所述发光器件发光；以及
发光控制模块，连接于所述驱动模块，所述发光控制模块、所述发光器件以及所述驱动模块均串联在第一电源信号和第二电源信号之间，所述发光控制模块的控制端接入发光控制信号；
其中，所述发光控制信号包括至少一脉冲信号，所述发光控制模块在所述脉冲信号的作用下关闭所述发光器件，所述脉冲信号根据一帧显示周期的亮度波形的频谱设置。
可选的，在本申请一些实施例中，所述发光控制信号还包括第一基准脉冲信号和第二基准脉冲信号，所述第一基准脉冲信号位于一帧显示周期的起始处，所述第二基准脉冲信号位于一帧显示周期的至少一时间等分点处；
其中，所述脉冲信号、所述第一基准脉冲信号以及所述第二基准脉冲信号中的任意两者之间均具有时间间隔，或者所述脉冲信号与所述第一基准脉冲信号或所述第二基准脉冲信号部分重叠设置。
可选的，在本申请一些实施例中，所述像素电路在多个驱动模式中的一个所述驱动模式下工作，每一所述驱动模式的刷新频率均不相同，所述发光控制信号在每一所述驱动模式下具有相应的一组所述脉冲信号。
可选的，在本申请一些实施例中，所述像素电路至少在第一驱动模式或第二驱动模式下工作，所述第一驱动模式的刷新频率小于所述第二驱动模式的刷新频率；
其中，在一帧显示周期内，所述脉冲信号在所述第一驱动模式下的数量大于或等于所述脉冲信号在所述第二驱动模式下的数量。
可选的，在本申请一些实施例中，在一帧显示周期内，当刷新频率为15赫兹时，所述脉冲信号的个数不少于5个，当刷新频率为20赫兹时，所述脉冲信号的个数不少于5个，当刷新频率为30赫兹时，所述脉冲信号的个数不少于1个。
可选的，在本申请一些实施例中，所述脉冲信号对应一帧显示周期的亮度波形的频谱中的低频分量设置，所述低频分量的频率小于60赫兹。
可选的，在本申请一些实施例中，一帧显示周期包括第一显示阶段和第二显示阶段，所述第一显示阶段的显示亮度大于所述第二显示阶段的显示亮度，所述脉冲信号在所述第一显示阶段的分布密度大于所述脉冲信号在所述第二显示阶段的分布密度。
相应的，本申请还提供一种驱动系统，其包括信号产生模块，所述信号产生模块具有输出端子，所述输出端子用于输出上述任一项所述的像素电路中的所述发光控制信号。
可选的，在本申请一些实施例中，所述信号产生模块包括存储单元和脉冲信号产生单元；
所述存储单元用于存储所述脉冲信号的参数信息，所述脉冲信号产生单元与所述存储单元连接，所述脉冲信号产生单元用于根据所述参数信息生成所述脉冲信号。
可选的，在本申请一些实施例中，所述参数信息包括脉冲起始位置控制参数、脉冲步长类型控制参数、脉冲起始位置参数以及脉冲终止位置参数。
可选的，在本申请一些实施例中，所述脉冲信号产生单元包括计数器、第一判断子单元以及第二判断子单元；
其中，所述计数器用于根据所述脉冲起始位置控制参数以及所述脉冲步长类型控制参数进行计数，得到第一参数；所述第一判断子单元将所述第一参数与所述脉冲起始位置参数进行比较，若所述第一参数小于所述脉冲起始位置参数，则所述计数器继续计数，若所述第一参数等于所述脉冲起始位置参数，则确定所述脉冲信号的起始位置；所述第二判断子单元将所述第一参数与所述脉冲终止位置参数进行比较，若所述第一参数小于所述脉冲终止位置参数，则所述计数器继续计数，若所述第一参数等于所述脉冲终止位置参数，则确定所述脉冲信号的终止位置。
可选的，在本申请一些实施例中，所述存储单元存储有多组所述参数信息，每组所述参数信息对应一种刷新频率，所述脉冲信号产生单元根据不同的刷新频率获取相应的所述参数信息。
可选的，在本申请一些实施例中，所述信号产生模块还包括起始信号产生单元和GOA电路，所述脉冲信号产生单元设置在所述起始信号产生单元中，所述起始信号产生单元用于生成包括所述脉冲信号的起始信号，所述GOA电路与所述起始信号产生单元连接，所述GOA电路用于根据所述包括所述脉冲信号的起始信号生成多级所述发光控制信号。
可选的，在本申请一些实施例中，所述驱动系统还包括驱动芯片，所述起始信号产生单元设置在所述驱动芯片内。
可选的，在本申请一些实施例中，所述信号产生模块还包括第一GOA电路，所述第一GOA电路与所述脉冲信号产生单元连接，所述第一GOA电路用于生成多级所述脉冲信号。
 有益效果
本申请提供一种像素电路及驱动系统。像素电路包括驱动模块、发光控制模块以及发光器件，所述发光控制模块、所述发光器件以及所述驱动模块均串联在第一电源信号和第二电源信号之间，所述发光控制模块的控制端接入发光控制信号。本申请在发光控制信号中增设至少一脉冲信号，由于发光控制模块在脉冲信号的作用下关闭，发光器件不发光，所以根据一帧显示周期的亮度波形的频谱设置脉冲信号，可以减小脉冲信号对应的时间段的发光亮度，从而减小一帧显示周期的亮度频谱中的低频分量，改善闪烁观感和闪烁值。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获取其他的附图。
图1是本申请提供的像素电路的一种结构示意图；
图2是本申请提供的图1所示的像素电路的信号时序图；
图3为本申请提供的显示面板在一帧显示周期内的亮度变化示意图；
图4是本申请提供的像素电路的第一结构示意图；
图5是本申请提供的发光控制信号的一种时序示意图；
图6是本申请提供的用于处理亮度信号的积分器的频率特性示意图；
图7是本申请提供的一种GOA电路的结构示意图；
图8是本申请提供的在30Hz刷新频率下的原驱动亮度波形及其亮度频谱示意图；
图9是本申请提供的在30Hz刷新频率下，由脉冲信号引起的亮度波形增量及其亮度频谱示意图；
图10是本申请提供的在30Hz刷新频率下新驱动亮度波形及其亮度频谱示意图；
图11是本申请提供的在10Hz刷新频率下的原驱动亮度波形及其亮度频谱示意图；
图12是本申请提供的在10Hz刷新频率下，由脉冲信号引起的亮度波形增量及其亮度频谱示意图；
图13是本申请提供的在10Hz刷新频率下新驱动亮度波形及其亮度频谱示意图；
图14是本申请提供的驱动系统的第一结构示意图；
图15是本申请提供的信号产生模块的结构示意图；
图16是本申请提供的脉冲信号产生单元的结构示意图；
图17是本申请提供的判断脉冲起始位置参数的流程示意图；
图18是本申请提供的判断脉冲终止位置参数的流程示意图；
图19是本申请提供的起始信号以及包括脉冲信号的起始信号的信号时序图；
图20是本申请提供的驱动系统的第二结构示意图；
图21是本申请提供的驱动系统的第三结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获取的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”和“第二”等的特征可以明示或者隐含地包括一个或者更多个所述特征，因此不能理解为对本申请的限制。
本申请提供一种驱动系统，以下进行详细说明。需要说明的是，以下实施例的描述顺序不作为对本申请实施例优选顺序的限定。
请参阅图1和图2。图1是本申请提供的像素电路的一种结构示意图。图2是本申请提供的图1所示的像素电路的信号时序图。其中，在一帧显示周期内，像素电路10的驱动时序包括复位阶段t1、数据写入及补偿阶段t2以及发光阶段t3。
在复位阶段t1，第n-1级扫描信号S(n-1)为低电位，第三晶体管T3和第六晶体管T6打开，驱动晶体管Td的栅极以及发光器件D的阳极均被复位至复位电压Vi。
此时，使能信号EM和第n级扫描信号S(n)为高电位，第一晶体管T1、第二晶体管T2、第四晶体管T4以及第五晶体管T5均关闭，发光器件D不发光。
在数据写入及补偿阶段t2，第n级扫描信号S(n)为低电位，第一晶体管T1、第二晶体管T2以及驱动晶体管Td均打开，数据电压Da通过第一晶体管T1、驱动晶体管Td以及第二晶体管T2对驱动晶体管Td的栅极充电。当驱动晶体管Td的栅极电位上升到Vdata-Vth（Vth为驱动晶体管Td的阈值电压）时，驱动晶体管Td截止，驱动晶体管Td的栅极电位不再上升，阈值电压存储在存储电容Cst中，从而实现对驱动晶体管Td的阈值电压补偿。
此时，使能信号EM仍保持为高电位，第四晶体管T4和第五晶体管T5均关闭，发光器件D不发光。
在发光阶段t3，使能信号EM由高电位转变为低电位，第四晶体管T4和第五晶体管T5均打开。此时，电源电压VDD开始对发光器件D的阳极进行充电。当充电达到发光器件D的启亮电压时，发光器件D开始发光。
可以理解的是，由于第二晶体管T2和第三晶体管T3均与驱动晶体管Td的栅极连接，这两个晶体管的漏电流特性将直接影响发光阶段t3的亮度稳定性。而OLED（Organic Light-Emitting Diode，有机发光二极管）显示器中常采用的LTPS（Low Temperature Poly-Silicon，低温多晶硅）晶体管的漏电流较大，驱动晶体管Td的栅极电位会发生改变，从而导致在低频驱动的情况下，一帧显示周期内的亮度会产生较大的变化，出现闪烁。
具体的，请参阅图3，图3为本申请提供的显示面板在一帧显示周期内的亮度变化示意图。其中，虚线P代表显示面板在一帧显示周期内的目标亮度。曲线Q表示显示面板在一帧显示周期内的实际亮度变化趋势。由图3可知，在一帧显示周期内，显示画面的亮度变化量为ΔL，变化量较大，易出现闪烁。
对此，请参阅图4和图5，图4是本申请提供的像素电路的第一结构示意图。图5是本申请提供的发光控制信号的一种时序示意图。本申请实施例提供一种像素电路10。像素电路10包括驱动模块10a、发光控制模块10b以及发光器件D。发光控制模块10b、发光器件D以及驱动模块10a均串联在第一电源信号VDD和第二电源信号VSS之间。发光控制模块10b的控制端接入发光控制信号EM。
其中，驱动模块10a至少包括驱动晶体管Td。发光控制模块10b至少包括发光控制晶体管T0。驱动晶体管Td的源极和漏极、发光控制晶体管T0的源极和漏极以及发光器件D均串接于第一电源信号VDD和第二电源信号VSS之间。发光控制晶体管T0的栅极接入发光控制信号EM。发光控制信号EM包括至少一脉冲信号C。发光控制晶体管T0在脉冲信号C的作用下关闭。脉冲信号C根据一帧显示周期的亮度分布的频谱设置。
其中，一帧显示周期的亮度分布的频谱是指：在一帧显示周期内采集显示面板的亮度信号，将亮度信号转换为数字信号。然后将所有数字信号进行傅里叶变换得到一组不同频率信号的幅值。又或者，在一段时间内连续采集显示面板多帧的亮度信号，将所有亮度信号转换为数字信号。然后将所有数字信号进行傅里叶变换得到一组不同频率信号的幅值。在以下各实施例中，亮度分布的频谱简称为亮度频谱。
其中，第一电源信号VDD和第二电源信号VSS均用于输出一预设电压值。此外，在本申请实施例中，第一电源信号VDD的电位大于第二电源信号VSS的电位。具体的，第二电源信号VSS的电位可以为接地端的电位。当然，可以理解地，第二电源信号VSS的电位还可以为其它。
本申请实施例在发光控制信号EM中增设至少一脉冲信号C，由于发光控制模块10b在脉冲信号C的作用下关闭，发光器件D不发光，所以根据一帧显示周期的亮度波形的频谱设置脉冲信号C，可减小脉冲信号对应的时间段的发光亮度，从而减小一帧显示周期的亮度频谱中的低频分量，改善闪烁观感和闪烁值。
请参阅图6，图6是本申请提供的用于处理亮度信号的积分器的频率特性示意图。其中，横坐标为频率，单位为赫兹（Hz）。纵坐标为水平（Level），单位dB是一个数值，没有任何单位标注。
其中，积分器的频率特性与人类视觉对不同频率的响应特性相同。在频率为60Hz以下时，其水平急剧变大。也即，在一帧显示周期中，亮度会随时间发生变化。将亮度的时域信号进行傅里叶变换可以得到该信号不同的频率成分。人眼对不同的频率成分的敏感值是不同的。如在小于60Hz范围内，在亮度幅值相同的情况下，频率越高，人眼的闪烁感受越轻，越不敏感。也即，人眼对亮度频谱中60Hz以下频率的闪烁比较敏感。显示面板在低刷新率（如<60Hz）下，如果一帧显示周期内的亮度存在较大下降或者上升，那么亮度频谱在低频处（如<60Hz）存在较大的幅值分量，闪烁值会较大，人眼也会明显察觉到闪烁。
而在周期性连续亮度波形中，亮度大的位置，对应着低频分量的峰值相位。为了进一步消除亮度频谱中的低频分量，本申请一些实施例将脉冲信号C对应一帧显示周期的亮度频谱中的低频分量设置，低频分量的频率小于60赫兹。由于发光控制晶体管T0在脉冲信号C的作用下关闭，发光器件D不发光，由此可减小脉冲信号C对应的时间段的发光亮度，从而减小一帧显示周期的亮度频谱中的低频分量，改善闪烁观感和闪烁值。
当然，在申请一些实施例中，低频分量中的低频的范围也可根据实际应用中对显示面板的闪烁规格要求进行设定，本申请对此不作具体限定。
此外，相较于现有LTPO（Low Temperature Polycrystalline Oxide，低温多晶氧化物）技术采用漏电流较低的IGZO（Indium Gallium Zinc Oxide，铟镓锌氧化物）晶体管来解决低频驱动下闪烁较严重的问题。本申请实施例可以仅使用LTPS晶体管，不需要将LTPS晶体管和IGZO晶体管结合在一起。像素电路10的结构和工艺更加简单，有效地降低了成本。
需要说明的是，在本申请实施例中，像素电路10可以是图1所示的像素电路10。但是，图1所示的像素电路10仅为一种示例，不能理解为对本申请的限定。比如，本申请实施例以各晶体管均为P型晶体管为例进行说明，但各晶体管也可以是N型晶体管、双栅晶体管等。又比如，像素电路10还可以包括其它类型的阈值电压补偿结构或电源电压VDD补偿结构等，本申请对此不作限定。
此外，本申请实施例中，发光控制模块10b可以包括图1中的晶体管T4和/或晶体管T5，只要满足发光控制模块10b在发光控制信号EM的控制下控制发光器件D发光或不发光的条件即可。发光控制信号EM可以是由使能信号EM(n)叠加脉冲信号C得到。发光控制信号EM也可以是由其他可控制发光器件D发光的信号中叠加脉冲信号C得到。
具体的，请参阅图7，图7是本申请提供的一种GOA电路的结构示意图。GOA电路30包括多级级联的GOA单元31。GOA电路30用于基于时钟信号XCK、高电平信号Vgh以及低电平信号Vgl，并以起始信号STV_EM为基准，生成多级使能信号，比如第一级使能信号EM(1)、第二级使能信号EM(2)、第三级使能信号EM(3)、第n-1级使能信号EM(n-1)、第n级使能信号EM(n)等。
其中，第一基准脉冲信号A和第二基准脉冲信号B存在于起始信号STV_EM中。起始信号STV_EM经过GOA电路30级传，输出每一级的使能信号EM(n)。每一级使能信号EM(n)与起始信号STV_EM的波形相同，时间存在偏移。因此，起始信号STV_EM的信号时序决定了使能信号EM(n)的时序。脉冲信号C可以添加到起始信号STV_EM时序中，这样GOA电路30输出的使能信号EM(n)也就包含脉冲信号C，也即形成了发光控制信号EM。
需要说明的是，由于脉冲信号C的作用是在原驱动亮度波形中，根据脉冲信号C在一帧显示周期内添加不发光的时间段，因此脉冲信号C除了可以由产生使能信号EM(n)的GOA电路30提供以外，也可以单独使用一组GOA电路产生，或者添加产生其他可以控制发光器件D发光状态的信号的GOA电路中，本申请对此不作限制。
本申请以下各实施例均以发光控制晶体管T0为P型晶体管，发光控制信号EM为由使能信号EM(n)叠加脉冲信号C得到为例进行说明，但不能理解为对本申请的限定。
在本申请实施例中，发光控制信号EM还包括第一基准脉冲信号A和第二基准脉冲信号B。其中，第一基准脉冲信号A位于一帧显示周期的起始处。第二基准脉冲信号B与第一基准脉冲信号A之间具有一定的时间间隔，且位于一帧显示周期的至少一时间等分点处。其中，时间等分点是指一帧显示周期的2等分点、3等分点、4等分点、32等分点等等。
可以理解的是，第一基准脉冲信号A和第二基准脉冲信号B构成使能信号EM(n)。在一帧显示周期中，且在第一基准脉冲信号A的作用时间段内，像素电路10处于复位阶段t1和数据写入及补偿阶段t2，以进行复位和补偿充电。此时，第一基准脉冲信号A为高电平脉冲，发光控制晶体管T0关闭，发光器件D不发光。在一帧显示周期的发光阶段t3，原本使能信号EM(n)保持为低电平，发光器件D发光。但由于加入了高电平的第二基准脉冲信号B，在第二基准脉冲信号B的作用时间段内，发光器件D不发光。第二基准脉冲信号B用于以PWM（Pulse Width Modulation，脉宽调制）技术调节屏幕亮度。
通常，同一型号的显示面板个体之间一般采用相同第一基准脉冲信号A和第二基准脉冲信号B。但由于每一片显示面板的时间亮度波形不同，脉冲信号C可以针对每一片显示面板独立调节以达到最佳降低闪烁的效果。也即，像素电路10可以应用在多个显示面板中，发光控制信号EM在每一显示面板中可以具有相应的一组脉冲信号C。
由前述分析可知，在周期性连续亮度波形中，亮度大的位置，对应着低频分量的峰值相位。因此可以在每一帧显示周期中亮度较高的时间段内设置更多的脉冲信号C。比如，对于一帧显示周期内亮度逐渐下降的亮度波形，脉冲信号C在一帧周期内靠前的时间更集中。对于一帧显示周期内亮度逐渐上升的亮度波形，脉冲信号C在一帧内靠后的时间更集中。对于任意形状的亮度波形，脉冲信号C在靠近亮度波形最大值的位置更集中。
具体的，可以根据一帧显示周期的亮度分布，设置一帧显示周期包括第一显示阶段和第二显示阶段。第一显示阶段的显示亮度大于第二显示阶段的显示亮度。在这种情形下，设置脉冲信号C在第一显示阶段的分布密度大于脉冲信号C在第二显示阶段的分布密度，由此可以简化脉冲C的设置步骤。当然，可以根据实际的亮度分布，设置多个显示阶段，本申请对此并不做具体限定。
在本申请实施例中，像素电路10可以在多个驱动模式下工作。每一驱动模式对应一刷新频率。其中，刷新频率是指屏幕每秒钟画面帧被刷新的次数，也即每秒钟帧显示周期的个数。在不同刷新频率下，发光控制信号EM可以包括位置、脉冲宽度以及数量不同的一组脉冲信号C。其中，“多个”指的是两个或两个以上。
具体的，像素电路10可以在第一驱动模式或第二驱动模式下工作。第一驱动模式的刷新频率小于第二驱动模式的刷新频率。其中，在一帧显示周期内，脉冲信号C在第一驱动模式下的数量大于或等于脉冲信号C在第二驱动模式下的数量。
可以理解的是，由于第一驱动模式的刷新频率小于第二驱动模式的刷新频率，则一帧显示周期的发光阶段t3在第一驱动模式下的时长大于在第二驱动模式下的时长。发光时长越长，由于漏电等原因，发光亮度的变化量可能就越大，产生闪烁的可能性也就越大。因此，通过设置脉冲信号C在第一驱动模式下的数量大于或等于脉冲信号C在第二驱动模式下的数量，可以在不同驱动模式下，在发光控制信号EM中设置不同的脉冲信号C，从而更好的改善闪烁。
比如，在刷新频率为10Hz的情况下，一帧显示周期内的脉冲信号C的个数为不少于10个。刷新频率为15Hz的情况下，一帧显示周期内的脉冲信号C的个数为不少于5个。在刷新频率为20Hz的情况下，一帧显示周期内的脉冲信号C的个数为不少于5个。在刷新频率为30Hz的情况下，一帧显示周期内的脉冲信号C的个数为不少于1个。本申请实施例在此不一一例举。
在本申请实施例中，在任一刷新频率下，脉冲信号C的个数可以是1个或者多个。在一帧显示周期内，每个脉冲信号C的起始时间、终止时间可以出现在一帧显示周期的任意位置。
具体的，脉冲信号C可以与第一基准脉冲信号A至少部分重叠或与第二基准脉冲B至少部分重叠设置。或者脉冲信号C与第一基准脉冲信号A以及第二基准脉冲信号均具有时间间隔。当脉冲信号C与第一基准脉冲信号A或第二基准脉冲B重叠设置时，并不影响脉冲信号C降低低频成分的功能。
在本申请实施例中，脉冲信号C在发光控制信号EM中的位置、脉冲宽度以及脉冲数量由原驱动亮度波形决定。原驱动亮度波形是指在不包括脉冲信号C的使能信号EM(n)驱动下的亮度波形。具体的，原驱动亮度波形经过傅里叶变换得到的亮度频谱中的低频分量决定了脉冲信号C在发光控制信号EM中的位置、脉冲宽度以及脉冲数量。
可以理解的是，在发光控制信号EM中引入脉冲信号C后，相较于原驱动亮度波形，在脉冲信号C的作用下，会引入新的亮度变化，也即亮度波形增量。其中，原驱动亮度波形频谱中的低频分量与脉冲信号C所引入的亮度增量频谱中的低频分量，在相同频率上幅值尽量相等，相位尽量相反。由此，可以消除或减轻原驱动亮度波形频谱中的低频幅值分量，从而降低闪烁值、减轻人眼闪烁观感。
具体的，脉冲信号C的位置、脉冲宽度以及数量的获取方式可以包括以下步骤：
101、在使能信号EM的驱动下，测量得到原驱动亮度波形。
具体的，可使用亮度计等亮度测量仪对一帧显示周期下的亮度进行侦测，得到亮度信号，并将亮度信号转变为数字信号，得到原驱动亮度波形。
102、对原驱动亮度波形进行傅里叶变换，得到各低频分量的幅值和相位。
其中，对原驱动亮度波形进行傅里叶变换的原理以及过程为本领域技术人员熟知的技术，在此不再赘述。通过傅里叶变换可以得到原驱动亮度波形的亮度频谱。其中亮度频谱包括频域幅值信息和频域相位信息。由此，可以得到原驱动亮度波形的亮度频谱中各低频（<60Hz）分量的幅值和相位。
103、根据各低频分量的幅值和相位，匹配幅值相等、相位相反的亮度波形负值增量。
具体的，可以根据每一低频分量的幅值和相位，分别匹配幅值相等、相位相反的亮度波形负值增量。也可以取部分低频分量，再根据每一低频分量的幅值和相位，分别匹配幅值相等、相位相反的亮度波形负值增量。
104、将亮度波形负值增量的位置、宽度和数量对应叠加到使能信号EM(n)或者其他可控制发光器件D发光的信号上，从而得到脉冲信号C以及发光控制信号EM。
其中，由于在脉冲信号C的作用下，发光器件D不发光。因此，根据亮度波形负值增量的位置、宽度和数量可以判断出脉冲信号C的位置、脉冲宽度以及数量。再将其叠加到使能信号EM(n)或其他可控制发光器件D发光的信号上，可以得到发光控制信号EM。
在本申请一实施例中，以刷新频率为30Hz为例进行说明。
请同时参阅图8-图10。图8是本申请提供的在30Hz刷新频率下的原驱动亮度波形及其亮度频谱示意图。图9是本申请提供的在30Hz刷新频率下，由脉冲信号引起的亮度波形增量及其亮度频谱示意图。图10是本申请提供的在30Hz刷新频率下新驱动亮度波形及其亮度频谱示意图。
具体的，在图7中，图(a)为原驱动亮度波形，图(b)为原驱动亮度波形的频域幅值谱，图(c)为原驱动亮度波形的频域相位谱。在图8中，图(d)为脉冲信号C引入的亮度波形增量，图(e)为亮度波形增量的频域幅值谱，图(f)为亮度波形增量的频域相位谱。在图9中，图(g)为新驱动亮度波形，也即在原驱动中叠加了脉冲信号C的驱动下得到的亮度波形，图(h)为新驱动亮度波形的频域幅值谱，图(i)为新驱动亮度波形的频域相位谱。
如图(b)和图(c)所示，在30Hz刷新频率下，原驱动亮度波形在30Hz频率处有一个幅值为31.29，相位为-90.45°的频率分量。对此，结合图(a)和图(d)所示，增设的脉冲信号C的个数为4。各脉冲信号C的位置与脉冲宽度均可参阅图(d)。如图(e)和图(f)所示，亮度波形增量在30Hz频率处有一个幅值为31.18，相位为90.49°的频率分量。
可知，脉冲信号C引入的亮度波形增量的低频分量与原驱动亮度波形的低频分量的幅值接近相等，相位接近相反。原亮度波形与亮度波形增亮叠加，得到的新驱动亮度波形在30Hz频率处的分量幅值为0.52。30Hz频域处的分量幅值被减少为原来的1/60。因此，脉冲信号C的设置可以消除或减轻原驱动亮度波形的低频幅值分量，从而减轻人眼闪烁观感，降低Flicker值。
需要说明的是，虽然60Hz处的幅值由15.91变化为31.84，但由上述分析可知，人眼对60Hz频率的闪烁极不敏感。因此脉冲信号C的设置对闪烁带来极大改善。
进一步的，通过JEITA方法计算得到的原驱动的Flicker JEITA值为-21.9dB，新驱动的Flicker JEITA值为-56.72dB，可知闪烁得到了良好改善。其中，JEITA方法是根据不同频率信号的幅值计算Flicker闪烁值，特点是更符合人眼对不同闪烁频率的感受，测量结果更客观稳定。
在本申请一实施例中，以刷新频率为10Hz为例进行说明。
请同时参阅图11-图13。图11是本申请提供的在10Hz刷新频率下的原驱动亮度波形及其亮度频谱示意图。图12是本申请提供的在10Hz刷新频率下，由脉冲信号引起的亮度波形增量及其亮度频谱示意图。图13是本申请提供的在10Hz刷新频率下新驱动亮度波形及其亮度频谱示意图。
具体的，在图11中，图(a)为原驱动亮度波形，图(b)为原驱动亮度波形的频域幅值谱，图(c)为原驱动亮度波形的频域相位谱。在图12中，图(d)为脉冲信号C引入的亮度波形增量，图(e)为亮度波形增量的频域幅值谱，图(f)为亮度波形增量的频域相位谱。在图13中，图(g)为新驱动亮度波形，也即在原驱动中叠加了脉冲信号C的驱动下得到的亮度波形，图(h)为新驱动亮度波形的频域幅值谱，图(i)为新驱动亮度波形的频域相位谱。
如图(b)和图(c)所示，在10Hz刷新频率下，原驱动亮度波形在10Hz、20Hz、30Hz、40Hz以及50Hz频率处的频率分量幅值均较大，幅值分别为31.31、15.91、11.11、11.41以及5.83。对此，对此，结合图(a)和图(d)所示，增设的脉冲信号C的个数为20。各脉冲信号C的位置与脉冲宽度均可参阅图(d)。如图(e)和图(f)所示，原亮度波形与亮度波形增亮叠加后，新驱动亮度波形在10Hz、20Hz、30Hz、40Hz以及50Hz频率处的频率分量幅值均较小，幅值分别为1.35、1.06、1.86、0.99以及1.32。原驱动Flicker JEITA值为-18.91dB，新驱动Flicker JEITA值为-44.75dB。因此，脉冲信号C的设置可以消除或减轻原驱动亮度波形的低频幅值分量，从而减轻人眼闪烁观感，降低Flicker值。
相应的，请参阅图14，图14是本申请提供的驱动系统的第一结构示意图。本申请实施例提供一种驱动系统100。驱动系统100包括信号产生模块20。信号产生模块20具有输出端子20a。输出端子20a用于输出上述任一实施例所述的像素电路10中的发光控制信号EM。
在本申请实施例中，请参阅图15，图15是本申请提供的信号产生模块的结构示意图。信号产生模块20包括存储单元21和脉冲信号产生单元22。
其中，存储单元21用于存储脉冲信号C的参数信息。脉冲信号产生单元22与存储单元21连接，以获取脉冲信号C的参数信息。脉冲信号产生单元22用于根据参数信息生成脉冲信号C。
其中，存储单元21可以是MIPI（Mobile Industry Processor Interface，移动产业处理器接口）寄存器、ROM（Read-Only Memory，只读存储器）或者外置Flash IC（闪存芯片）中。
其中，参数信息可根据前述实施例中脉冲信号C的位置、脉冲宽度以及数量的获取方式得到，在此不再赘述。参数信息可在显示装置生产时通过OTP（One Time Programmable，一次性可编程）烧录或Flash烧写等方式，存储在存储单元21中。
在本申请实施例中，存储单元21可以存储有多组参数信息，每组参数信息对应一种刷新频率。脉冲信号产生单元22根据不同的刷新频率获取相应的参数信息。
可以理解的是，驱动系统100可以包括多种驱动模式，每种驱动模式对应不同的刷新频率。由前述实施例可知，在不同刷新频率下，发光控制信号EM包括的脉冲信号C的位置、脉冲宽度以及数量可能不相同。因此，本申请实施例在存储单元21中存储多组参数信息。当驱动系统100采用不同刷新频率时，脉冲信号产生单元22可获取相应的参数信息，并产生相应的脉冲信号C，从而提高驱动系统100在不同刷新频率下的切换效率。
在本申请实施例中，脉冲信号C的参数信息可包括脉冲起始位置控制参数、脉冲步长类型控制参数、脉冲起始位置参数以及脉冲终止位置参数。
其中，脉冲起始位置控制参数用于控制脉冲信号C的起始位置参考点。参考点可以是帧同步信号或者帧消隐信号，最低可由一个数据位定义。
其中，脉冲步长类型控制参数可以理解为计数单位。比如脉冲步长类型可是一个行同步时长或者一个时钟信号高电平脉冲，最低可由一个数据位定义。比如，可以在时钟信号的上升沿每来临一次，计数器计数加一。
其中，脉冲起始位置参数是指脉冲信号C的上升沿位置或下降沿位置。因为本申请实施例以晶体管为P型晶体管为例进行说明，因此，此处的脉冲起始位置参数是指脉冲信号C的上升沿位置。
比如，发光控制信号EM可以包括N个脉冲信号C。N为大于等于1的整数。每一个脉冲信号C均具有一个脉冲起始位置参数。比如，pulse i的起始位置参数描述第i个脉冲信号C的起始的时间位置，每个参数为固定的数据位长。i为大于等于1，且小于等于N的整数。例如位长为24，可以表示的时间范围为0~16777215。每个数的单位由脉冲步长类型控制参数确定。
其中，脉冲终止位置参数是指脉冲信号C的上升沿位置或下降沿位置。因为本申请实施例以晶体管为P型晶体管为例进行说明，因此，此处的脉冲终止位置参数是指脉冲信号C的下降沿位置。
比如，发光控制信号EM可以包括N个脉冲信号C。N为大于等于1的整数。每一个脉冲信号C均具有一个脉冲终止位置参数。比如，pulse i的终止位置参数描述第i个脉冲信号C的终止的时间位置，每个参数为固定的数据位长。例如位长为24，可以表示的时间范围为0~16777215。每个数的单位由脉冲步长类型控制参数确定。
其中，脉冲终止位置参数与脉冲起始位置参数成对工作。
请参阅图16，图16是本申请提供的脉冲信号产生单元的结构示意图。在本申请实施例中，脉冲信号产生单元22包括计数器221、第一判断子单元222以及第二判断子单元223。
其中，计数器221根据脉冲起始位置控制参数以及脉冲步长类型控制参数进行计数，得到第一参数。第一判断子单元222将第一参数与脉冲起始位置参数进行比较，若第一参数小于脉冲起始位置参数，则计数器221继续计数，若第一参数等于脉冲起始位置参数，则确定脉冲信号的起始位置。第二判断子单元223将第一参数与脉冲终止位置参数进行比较，若第一参数小于脉冲终止位置参数，则计数器221继续计数，若第一参数等于脉冲终止位置参数，则确定脉冲信号的终止位置。
具体的，请参阅图17和图18，图17是本申请提供的判断脉冲起始位置参数的流程示意图。图18是本申请提供的判断脉冲终止位置参数的流程示意图。本申请实施例以第i个脉冲信号C为例进行说明，但不能理解为对本申请的限定。
如图17所示，计数器221根据脉冲起始位置控制参数开始计数。然后根据脉冲步长类型控制参数进行计数。第一判断子单元222将计数值与pulse i起始位置参数进行比较，若计数值小于pulse i起始位置参数，则计数器221继续计数，计数值+1。若计数值等于pulse i起始位置参数，则确定脉冲信号的起始位置。此时，若起始信号STV_EM为低电平，则起始信号STV_EM从低电平转为高电平，也即确定了pulse i的上升沿位置。若起始信号STV_EM为高电平，比如此处位置存在起始信号STV_EM中的第二脉冲信号B，则起始信号STV_EM保持高电平不变。
接着，如图18所示，在确定pulse i起始位置后，计数器221继续计数，第二判断子单元223将计数值与脉冲终止位置参数进行比较，若计数值小于脉冲终止位置参数，则计数器221继续计数。若计数值等于脉冲终止位置参数，则确定脉冲信号的终止位置。此时，若起始信号STV_EM)为高电平，则起始信号STV_EM从高电平转为低电平，也即确定了pulse i的下降沿位置。若起始信号STV_EM为低电平，则起始信号STV_EM保持低电平不变。
由此，如图19所示，以刷新频率为30Hz为例进行说明。在经过脉冲信号产生单元22的处理后，相较于起始信号STV_EM可得到包括脉冲信号C的起始信号STV_EM。在一帧显示周期内，在包括脉冲信号C的起始信号STV_EM中，t1-t2时间段插入了第一个脉冲信号C，t3-t4时间段插入了第二个脉冲信号C，t5-t6时间段插入了第三个脉冲信号C，t7-t8时间段插入了第四个脉冲信号C。可知，第二个脉冲信号C和第三个脉冲信号C均与第二基准脉冲信号B有部分重叠。
在本申请实施例中，请参阅图20，图20是本申请提供的驱动系统的第二结构示意图。在本申请实施例中，信号产生模块20还包括起始信号产生单元41和GOA电路30。脉冲信号产生单元22设置在起始信号产生单元41中。起始信号产生单元41用于生成包括脉冲信号C的起始信号STV_EM。GOA电路30与起始信号产生单元41连接。GOA电路30根据包括脉冲信号C的起始信号号STV_EM生成多级发光控制信号EM。多级发光控制信号EM分别传输至不同的像素电路10。
进一步的，驱动系统100还包括驱动芯片40。起始信号产生单元41设置在驱动芯片40内。其中，驱动芯片40是用于驱动显示面板进行画面显示的芯片。驱动芯片40的功能之一是生成起始信号STV_EM。然后，GOA电路30根据起始信号STV_EM生成多级使能信号EM(n)。
本申请实施例在起始信号STV_EM中叠加脉冲信号C，可以得到包括脉冲信号C的起始信号STV_EM。然后，GOA电路30可根据脉冲信号C的起始信号STV_EM生成多级发光控制信号EM。
当然，在本申请其他实施例中，请参阅图21，图21是本申请提供的驱动系统的第三结构示意图。在本申请实施例中，信号产生模块20包括第一GOA电路50。第一GOA电路50与脉冲信号产生单元22连接。第一GOA电路50用于生成多级脉冲信号C。
其中，第一GOA电路50与图20中的GOA电路30相互独立。可以理解的是，由于脉冲信号C的作用是在原有亮度波形中根据脉冲信号C在一帧显示周期内的位置中添加不发光的时间段，因此脉冲信号C除了可以由GOA电路30提供以外，也可以单独使用一组第一GOA电路50产生。
本申请实施例通过单独使用一组第一GOA电路50产生多级脉冲信号C，可以直接通过脉冲信号C控制像素电路10中发光器件D的发光状态。由此，可提高脉冲信号C对一帧显示周期的发光亮度的控制精度。
以上对本申请提供的驱动系统进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (19)

  1. 一种像素电路，其包括：
    发光器件；
    驱动模块，连接于所述发光器件以驱动所述发光器件发光；以及
    发光控制模块，连接于所述驱动模块，所述发光控制模块、所述发光器件以及所述驱动模块均串联在第一电源信号和第二电源信号之间，所述发光控制模块的控制端接入发光控制信号；
    其中，所述发光控制信号包括至少一脉冲信号，所述发光控制模块在所述脉冲信号的作用下关闭所述发光器件，所述脉冲信号根据一帧显示周期的亮度波形的频谱设置。
  2. 根据权利要求1所述的像素电路，其中，所述发光控制信号还包括第一基准脉冲信号和第二基准脉冲信号，所述第一基准脉冲信号位于一帧显示周期的起始处，所述第二基准脉冲信号位于一帧显示周期的至少一时间等分点处；
    其中，所述脉冲信号、所述第一基准脉冲信号以及所述第二基准脉冲信号中的任意两者之间均具有时间间隔，或者所述脉冲信号与所述第一基准脉冲信号或所述第二基准脉冲信号部分重叠设置。
  3. 根据权利要求1所述的像素电路，其中，所述像素电路在多个驱动模式中的一个所述驱动模式下工作，每一所述驱动模式的刷新频率均不相同，所述发光控制信号在每一所述驱动模式下具有相应的一组所述脉冲信号。
  4. 根据权利要求3所述的像素电路，其中，所述像素电路至少在第一驱动模式或第二驱动模式下工作，所述第一驱动模式的刷新频率小于所述第二驱动模式的刷新频率；
    其中，在一帧显示周期内，所述脉冲信号在所述第一驱动模式下的脉冲数量大于或等于所述脉冲信号在所述第二驱动模式下的脉冲数量。
  5. 根据权利要求3所述的像素电路，其中，在一帧显示周期内，当刷新频率为15赫兹时，所述脉冲信号的个数不少于5个，当刷新频率为20赫兹时，所述脉冲信号的个数不少于5个，当刷新频率为30赫兹时，所述脉冲信号的个数不少于1个。
  6. 根据权利要求1所述的像素电路，其中，所述脉冲信号对应一帧显示周期的亮度波形的频谱中的低频分量设置，所述低频分量的频率小于60赫兹。
  7. 根据权利要求1所述的像素电路，其中，一帧显示周期包括第一显示阶段和第二显示阶段，所述第一显示阶段的显示亮度大于所述第二显示阶段的显示亮度，所述脉冲信号在所述第一显示阶段的分布密度大于所述脉冲信号在所述第二显示阶段的分布密度。
  8. 一种驱动系统，其中，包括信号产生模块，所述信号产生模块具有输出端子，所述输出端子用于输出如权利要求1所述的像素电路中的所述发光控制信号。
  9. 根据权利要求8所述的驱动系统，其中，所述信号产生模块包括存储单元和脉冲信号产生单元；
    所述存储单元用于存储所述脉冲信号的参数信息，所述脉冲信号产生单元与所述存储单元连接，所述脉冲信号产生单元用于根据所述参数信息生成所述脉冲信号。
  10. 根据权利要求8所述的驱动系统，其中，所述参数信息包括脉冲起始位置控制参数、脉冲步长类型控制参数、脉冲起始位置参数以及脉冲终止位置参数。
  11. 根据权利要求10所述的驱动系统，其中，所述脉冲信号产生单元包括计数器、第一判断子单元以及第二判断子单元；
    其中，所述计数器用于根据所述脉冲起始位置控制参数以及所述脉冲步长类型控制参数进行计数，得到第一参数；所述第一判断子单元将所述第一参数与所述脉冲起始位置参数进行比较，若所述第一参数小于所述脉冲起始位置参数，则所述计数器继续计数，若所述第一参数等于所述脉冲起始位置参数，则确定所述脉冲信号的起始位置；所述第二判断子单元将所述第一参数与所述脉冲终止位置参数进行比较，若所述第一参数小于所述脉冲终止位置参数，则所述计数器继续计数，若所述第一参数等于所述脉冲终止位置参数，则确定所述脉冲信号的终止位置。
  12. 根据权利要求9所述的驱动系统，其中，所述存储单元存储有多组所述参数信息，每组所述参数信息对应一种刷新频率，所述脉冲信号产生单元根据不同的刷新频率获取相应的所述参数信息。
  13. 根据权利要求9所述的驱动系统，其中，所述信号产生模块还包括起始信号产生单元和GOA电路，所述脉冲信号产生单元设置在所述起始信号产生单元中，所述起始信号产生单元用于生成包括所述脉冲信号的起始信号，所述GOA电路与所述起始信号产生单元连接，所述GOA电路用于根据所述包括所述脉冲信号的起始信号生成多级所述发光控制信号。
  14. 根据权利要求13所述的驱动系统，其中，所述驱动系统还包括驱动芯片，所述起始信号产生单元设置在所述驱动芯片内。
  15. 根据权利要求9所述的驱动系统，其中，所述信号产生模块还包括第一GOA电路，所述第一GOA电路与所述脉冲信号产生单元连接，所述第一GOA电路用于生成多级所述脉冲信号。
  16. 根据权利要求8所述的驱动系统，其中，所述脉冲信号对应一帧显示周期的亮度波形的频谱中的低频分量设置，所述低频分量的频率小于60赫兹。
  17. 根据权利要求8所述的驱动系统，其中，所述发光控制信号还包括第一基准脉冲信号和第二基准脉冲信号，所述第一基准脉冲信号位于一帧显示周期的起始处，所述第二基准脉冲信号位于一帧显示周期的至少一时间等分点处；
    其中，所述脉冲信号、所述第一基准脉冲信号以及所述第二基准脉冲信号中的任意两者之间均具有时间间隔，或者所述脉冲信号与所述第一基准脉冲信号或所述第二基准脉冲信号部分重叠设置。
  18. 根据权利要求8所述的驱动系统，其中，所述像素电路在多个驱动模式中的一个所述驱动模式下工作，每一所述驱动模式的刷新频率均不相同，所述发光控制信号在每一所述驱动模式下具有相应的一组所述脉冲信号。
  19. 根据权利要求8所述的驱动系统，其中，一帧显示周期包括第一显示阶段和第二显示阶段，所述第一显示阶段的显示亮度大于所述第二显示阶段的显示亮度，所述脉冲信号在所述第一显示阶段的分布密度大于所述脉冲信号在所述第二显示阶段的分布密度。
PCT/CN2022/105105 2022-06-29 2022-07-12 像素电路及驱动系统 WO2024000643A1 (zh)

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