Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
  • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
  • H10D12/411—Insulated-gate bipolar transistors [IGBT]
  • H10D12/441—Vertical IGBTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
  • H10D12/411—Insulated-gate bipolar transistors [IGBT]
  • H10D12/441—Vertical IGBTs
  • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
  • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
  • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
  • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
  • H10D64/311—Gate electrodes for field-effect devices
  • H10D64/411—Gate electrodes for field-effect devices for FETs
  • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
  • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
  • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
  • H10D62/149—Source or drain regions of field-effect devices
  • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
  • H10D62/156—Drain regions of DMOS transistors
  • H10D62/157—Impurity concentrations or distributions

Definitions

• POWER SEMICONDUCTOR DEVICE AND PRODUCTION METHOD A power semiconductor device is provided. Further, a production method for such a power semiconductor device is provided.
• Document US 6 503 786 B2 refers to a power MOS device with an asymmetrical channel structure for enhanced linear operation capability.
• Document WO 2017/112276 A1 discloses a non-uniform gate oxide thickness for DRAM devices.
• Document US 2007/0063269 A1 describes a trench IGBT with an increased short circuit capability.
• Document US 2016/0064550 A1 refers to power devices.
• Documents EP 1 248 300 A2, US 2008/0166846 A1 and US 2016/0093719 A1 refer to electronic devices. Embodiments of the disclosure relate to a power semiconductor device that shows improved electrical behavior.
• the power semiconductor device comprises: - a semiconductor body having a source region of a first conductivity type and a well region of a second conductivity type different from the first conductivity type, and the well region comprises a channel region starting directly at the source region, - a gate electrode arranged at the semiconductor body and assigned to the channel region, and - a gate insulator directly between the semiconductor body and the gate electrode, wherein the gate insulator has a non-uniform thickness Tox along the channel region so that, along the channel region, the gate insulator is thickest in a first part remote from the source region.
• the gate electrode is insulated from the semiconductor body by the gate insulator.
• the at least one gate electrode is partially or completely arranged in at least one trench formed in the semiconductor body.
• the at least one trench and, thus, the assigned gate electrode may extend through the well region into the drift region, for example, in a direction away from a top side of the semiconductor body. Consequently, the at least one gate insulator is located partially or completely in the assigned trench, too.
• the power semiconductor device could be a trench-based device. Otherwise, the at least one gate electrode and the at least one gate insulator are applied on the top side of the semiconductor body.
• the top side may be a planar face.
• the at least one source region is in direct contact with the assigned gate insulator and/or is directly at the assigned channel region.
• the first conductivity type is, for example, n-conductive and, thus, the at least one source region is n-doped.
• the at least one channel region is also of the second conductivity type different from the first conductivity type.
• the second conductivity type is, for example, p-conductive and, thus, the at least one channel region is p-doped. It is possible that a maximum doping concentration of the at least one channel region is less than a maximum doping concentration of the at least one source region.
• the semiconductor body further comprises a drift region which may be of the first conductivity type, too.
• the drift region is in direct contact with the gate insulator and/or is directly at the channel region.
• the drift region may be located between the channel region and a drain region or a collector region of the semiconductor body.
• the optional trench may terminate in the drift region.
• the semiconductor body can comprise an enhancement layer.
• the enhancement layer is located directly between the well region and the drift region and may have a higher maximum doping concentration than the drift region.
• the enhancement layer can also be of the first conductivity type.
• the enhancement layer may work as a hole blocking layer, that is, it enhances plasma concentration near the source side resulting in an improved V ce-sat without increasing E off too much.
• the enhancement layer also helps in controlling a length of the channel region and minimizes manufacturing process-induced variability.
• a thickness of the enhancement layer is at least 1 ⁇ m and/or is at most 5 ⁇ m.
• the well region extends from the top side of the semiconductor body to the drift region.
• the channel region is part of the well region and may have the same doping concentration.
• the electrons flow in the channel region from the source region to the drift region along the gate insulator.
• the channel region has a thickness in a direction perpendicular to an interface between the gate insulator and the well region, for example, in a nanometer range, exemplarily 1 nm to 50 nm.
• the power semiconductor device is a metal–insulator–semiconductor field-effect transistor, MISFET, a metal–oxide–semiconductor field-effect transistor, MOSFET, an insulated-gate bipolar transistor, IGBT, or a reverse-conducting insulated-gate bipolar transistor, RC-IGBT.
• the semiconductor body is of Silicon, Si for short.
• the semiconductor body can alternatively be of a wide-bandgap semiconductor material like SiC, Ga 2 O 3 or GaN.
• the gate insulator is made of any electrically insulating material, which may be an oxide.
• the gate insulator is of at least one of the following materials: SiO 2 , Si 3 N 4 , Al 2 O 3 , Y 2 O 3 , ZrO 2 , HfO 2 , La 2 O 3 , Ta 2 O 5 , TiO 2 .
• the gate insulator may also be referred to as gate oxide.
• the power semiconductor device is a power device.
• the power semiconductor device is configured for a maximum voltage of at least 0.2 kV or of at least 0.6 kV or of at least 1.2 kV.
• the power semiconductor device is, for example, for a power module in a vehicle to convert direct current from a battery or a fuel cell to alternating current for an electric motor, for example, in hybrid vehicles or plug-in electric vehicles.
• the power semiconductor device can be a fuse, for example, in a vehicle like a car.
• the thickness of the gate insulator along the channel region increases monotonically or strictly monotonically towards the drift region.
• the gate insulator has a first part.
• the first part may be remote from the source region and consequently may be next to the drift region.
• the first part is a thickest part of the gate insulator seen along the channel region.
• a length of the first part is at least 5% or is at least 10% or is at least 15% of an overall length of the channel region along the gate insulator. Alternatively or additionally, said length is at most 40% or at most 30% or at most 25% of said overall length.
• the gate insulator has a second part which is located next to the source region, seen along the channel region.
• the gate insulator, along the channel region may consist of the second part and of the first part.
• the gate insulator has a constant thickness along the channel region in the second part. That is, the only intentional thickness variation of the gate insulator may be in the first part or at a boundary between the first part and the second part.
• the thickness of the gate insulator along the channel region varies by at least 10% or by at least 20% or by at least 30% of a maximum thickness of the gate insulator.
• the remainder of the gate insulator has a thickness of at most 70% or of at most 80% or of at most 90% of a thickness of the first part.
• the thickness of the gate insulator along the channel region changes in a stepped manner so that there is one or a plurality of steps in the thickness of the gate insulator along the channel region. Otherwise, the thickness of the gate insulator may change in a continuous, step-less manner.
• the gate insulator is of multi-layer fashion so that the gate insulator comprises at least two sub-layers. Otherwise, the gate insulator is of single-layer fashion and comprises only one layer.
• the sub-layers can be made of different materials and/or can have different dielectric constants.
• the sub-layers may follow directly on top of each other. It is possible that the sub-layers have different sizes so that the sub-layers can be arranged non-congruently. It is also possible that the sub-layers have different thicknesses, alternatively, the sub-layers are all of the same thickness.
• the channel region has a non-uniform channel doping profile along the gate insulator. For example, a doping concentration N A in the channel region is largest in the first part and consequently may be smallest in the second part.
• the doping concentration N A in the channel region is largest at a depth from the top side of the semiconductor body of at least 0.5 ⁇ m or of at least 1.5 ⁇ m.
• Said maximum doping concentration N A may also be at a distance of at least 0.5 ⁇ m or of at least 1.5 ⁇ m from the source region, seen along the gate insulator. Said maximum may be located within the well region. Accordingly, said maximum is achieved by epitaxial growth and not by ion implantation.
• the gate electrode has a non-uniform gate electrode work function profile along the channel region, such that a threshold voltage of the gate electrode is highest in the first part.
• a work function ⁇ m of the gate electrode in the first part remote from the source region is largest for devices having a p-type doped well region and, thus, a p-type doped channel region, and smallest for devices having an n-type doped well region and, thus, an n-type doped channel region.
• the gate insulator has a non-uniform gate dielectric constant profile along the channel region, such that a relative dielectric constant of the gate insulator is lowest in the first part of the channel region remote from the source region.
• the non- uniform thickness profile as well as the non-uniform channel doping profile and/or the non-uniform gate electrode work function profile and/or the non-uniform gate dielectric constant profile. That is, the non-uniform gate insulator thickness profile can be combined with the non-uniform channel doping profile, the non-uniform gate electrode work function profile or the non-uniform gate dielectric constant profile, or with two of the non-uniform channel doping profile, the non-uniform gate electrode work function profile and the non-uniform gate dielectric constant profile, or with all three other non-uniform profiles.
• the power semiconductor device is configured so that both a saturation current and a short-circuit current are decreased, for example, while a collector-emitter saturation voltage V ce-sat , and consequently on-state losses, may remain unaffected. This may be true because of the non-uniform thickness profile of the gate insulator where the thickness is increased in the first part while it is decreased in the remaining part of the gate insulator along the channel region, as compared to an analogously set-up reference semiconductor device having a constant thickness of a gate insulator along a channel region.
• a method for manufacturing the power semiconductor device is additionally provided. By means of the method, a power semiconductor device is produced as indicated in connection with at least one of the above-stated embodiments.
• the method for producing the power semiconductor device comprises the following steps, in particular in the stated order: - providing a semiconductor substrate, and - epitaxially growing at least one semiconductor layer onto the semiconductor substrate.
• the semiconductor substrate comprises at least part of the drift region.
• the at least one epitaxially grown semiconductor layer comprises the well region and the source region.
• Figure 1 is a schematic sectional view of a reference semiconductor device
• Figure 2 is a schematic sectional view of an exemplary embodiment of a power semiconductor device described herein
• Figure 3 is a top view of the power semiconductor device of Figure 2
• Figures 4 to 7 are schematic representations of electric data of power semiconductor devices described herein and of a reference semiconductor device
• Figure 8 is a schematic representation of gate insulator thicknesses of power semiconductor devices described herein and of a reference semiconductor device
• Figures 9 to 12 are simulation results of electric data of power semiconductor devices described herein and of a reference semiconductor device
• Figures 13 to 19 are schematic sectional views of exemplary embodiments of power semiconductor devices described herein.
• Figure 1 illustrates a reference semiconductor device 9 that corresponds to exemplary embodiments of power semiconductor devices 1 described herein except for a design of a gate insulator 4.
• the reference semiconductor device 9 comprises a semiconductor body 2 which is, for example, of Si.
• the semiconductor body 2 comprises a source region 21 and a well region 22 through which a trench passes. In the well region 22, there is a channel region 220.
• the reference semiconductor device 9 is in an on-state, then electrons flow from the source region 21 to a drift region 23 through the channel region 220 which is located directly at a gate insulator 4.
• the source region 21 is of a first conductivity type, like n- conducting, and the well region, and consequently the channel region 220, is of a second, different conductivity type, like p-conducting.
• the gate electrode 31 In the trench, there is a gate electrode 31 that is separated from the semiconductor body 2 by means of the electrically insulating gate insulator 4. The trench and, hence, the gate electrode 31 ends in the drift region 23 of the semiconductor body 2.
• the drift region 23 is of the first conductivity type, too.
• the gate insulator 4 is of constant thickness at least all along the channel region 220. Contrary to that, in the exemplary embodiments of the power semiconductor devices 1, the gate insulator 4 has a non-uniform thickness along the channel region 220.
• the gate insulator 4 comprises one step 43 at which the thickness of the gate insulator 4 changes in an abrupt manner. After the step, seen along the channel region 220, the gate insulator 4 comprises a first part 44 in which the gate insulator 4 has its maximum thickness Tmax.
• the term ‘along the channel region 220' means, for example, from the point where the channel region 220 starts at the gate insulator 4 close to the source region 21, and until the drift region 23 begins, that is, means along a direction x from the source region 21 until the drift region 23, for example, directly at the gate insulator 4.
• the region of the gate insulator 4 being of interest here and in the following has a length L which corresponds to a distance between the source region 21 and the drift region 23 directly at the gate insulator 4.
• the length L may be defined as the length of the second conductivity type layer between the layers of the first conductivity type, for example, the source region 21 and the drift region 23, wherein the drift region 23 may comprise a layer of lower doping concentration, not illustrated in the Figures.
• an enhancement layer 27 between the drift region 23 and the well region 22, there is an enhancement layer 27.
• the enhancement layer 27 is of the first conductivity type, too.
• Both the source region 21 and the well region 22 may be electrically connected by means of at least one source electrode 32 which is located at a top side 20 of the semiconductor body 2.
• the plug 25 may have a different thickness than the well region 22 so that the plug 25 can extend deeper or shallower into the semiconductor body 2 than the well region 22. Further, the thicknesses of the source region 21 and of the plug 25 can be the same or can be different. Both the source region 21 and the at least one plug 25 may be electrically connected by means of the at least one source electrode 32 which is located at the top side 20. Exemplarily, the plug 25 has a higher maximum doping concentration than the well region 22 or the channel region 220. The depth of the plug may be lower, deeper or the same as of the well region/channel region.
• the power semiconductor device 1 is an insulated-gate bipolar transistor, IGBT for short.
• a collector region 26 which is of the second conductivity type, too.
• a buffer region of the first conductivity type between the drift region 23 and the collector region 26, not shown.
• a doping concentration of the buffer region can be higher than that of the drift region 23.
• the collector region 26 there is a collector electrode 34.
• the semiconductor body 2 is at least in part produced by epitaxial growth. That is, the doping concentrations of the respective layers of the semiconductor body 2 may be produced during growth and may not be produced after growth, for example, by means of ion implantation.
• the drift region 23 can be partly or completely be part of a growth substrate.
• the trench accommodating the gate electrode 31 may be of extended fashion.
• the source region 21, the at least one plug 25 as well as the channel region 21 may be arranged symmetrically on both sides of the trench, see Figure 3.
• the thickness of the gate insulator along the channel region out of the first part is between 20 nm and 80 nm inclusive or is between 40 nm and 80 nm inclusive.
• said thickness is between 120 nm and 250 nm inclusive or is between 120 nm and 180 nm inclusive.
• maximum doping concentrations of the source regions 21, the collector region 26 or instead of a drain region 24 and the at least one plug 25 are at least 1 x 10 18 cm -3 or at least 5 x 10 18 cm -3 or at least 1 x 10 19 cm -3 and/or at most 5 x 10 20 cm -3 or at most 2 x 10 20 cm -3 or at most 1 x 10 20 cm -3 .
• a maximum doping concentration of the well region 22 and, thus, of the channel region 220 may be at least 5 x 10 16 cm -3 or at least 1 x 10 17 cm -3 and/or at most 5 x 10 19 cm -3 or at most 5 x 10 18 cm -3 .
• a maximum doping concentration of the enhancement layer 27 is at least 10 15 cm -3 and/or is at most 10 18 cm -3 .
• a maximum doping concentration of the drift region 23 may be at least 1 x 10 11 cm -3 or at least 1 x 10 12 cm -3 or at least 1 x 10 13 cm -3 and/or at most 1 x 10 17 cm -3 or at most 5 x 10 16 cm -3 or at most 1 x 10 16 cm -3 .
• the source region 21 and the at least one plug 25 are located along only one side of the gate electrode 31 so that there is a channel region 220 only along one outward side of the gate insulator 4.
• the source region 21 as well as the at least one plug 25 can also be located along two sides of the gate electrode 31, compare, for example, Figure 13, or all around the gate electrode 31, when seen in top view.
• Vce- sat some means to lower an on-state voltage drop Vce- sat, for example, by reducing the channel length L or increasing a channel width W, often result in an undesired higher saturation current I sat , as illustrated schematically using output characteristics I c vs. V ce , see Figure 4.
• the higher I sat is directly related to a higher short circuit current I sc , adversely affecting the short circuit capability of the power semiconductor device 1.
• raising a threshold voltage V th of the power semiconductor device 1 in order to lower I sat for example, by increasing a channel doping concentration, results in higher V ce-sat as illustrated in Figure 5.
• Figures 4 and 5 are schematics of typical output characteristics of an IGBT with a uniform threshold profile along the whole channel region, in Figure 4 for a same V th and different channel resistance, and in Figure 5 for different threshold voltages V th .
• Other techniques to reduce the short-circuit current such as: a) increasing the channel length L, b) reducing an anode injection efficiency, by reducing an anode implant dose, c) reducing the channel width, by decreasing a source coverage along the trench, and d) reducing the channel width, by increasing a cell pitch, also undesirably result in higher on-state losses.
• techniques such as d) can also adversely affect the breakdown capability of the power semiconductor device 1.
• Reducing gate biasing in order to reduce short-circuit current may also not be desirable as it leads to unstable dynamic behavior and moreover it is mainly defined by the application requirements.
• I sc short circuit current
• Another possibility to affect the electric behavior at a gate electrode in non-IGBT devices is, for example, using relatively thicker gate-oxides at trench bottom, mainly for prevention against hot carrier injection.
• thicker oxide may be limited to an n-base region and may not be extended into a p-doped region where it would have affected MOS channel characteristics.
• asymmetry in the channel doping or gate oxide thickness may be introduced with respect to a neighbouring cell and not in the channel region of the same cell.
• the use of a relatively thicker gate-oxide, with a thickness of, for example, 180 nm to 250 nm, uniformly along trench sidewalls and a trench bottom may also be possible to improve an IGBT short-circuit capability by raising its threshold voltage. However, this approach will suffer from a higher on-state voltage drop.
• Another method of fabricating a non-uniform gate oxide for DRAM device may use relatively thicker oxide at the top section of the recess sidewall.
• the trade-off between on-state losses and short circuit current is improved by improving the latter without adversely affecting the former.
• the described design features a non-uniform threshold voltage profile along the channel region 220 next to the gate insulator 4 to lower down the saturation current for a given Vce-sat.
• the proposed non-uniform V th in the power semiconductor device 1 described herein is achieved by implementing the non-uniform gate insulator thickness along the channel region 220.
• the described power semiconductor device 1 does not adversely affect the breakdown capability and more so ever the turn-off losses of the power semiconductor device 1.
• the described concept is applicable to any MOS device in general such as power-MOSFET or IGBT or reverse conducting IGBT devices and is even compatible with both planar and trench architectures.
• an improved MISFET, MOSFET or IGBT device with an enhanced short circuit capability is introduced without a detrimental effect on the on-state losses.
• the improved design also relaxes the design constraints of the IGBT, enabling the possibility to independently explore the other methods mentioned above to minimize the on-state losses which are normally limited by the short circuit capability of the respective device.
• some theoretical background to the idea of the semiconductor device 1 described herein is presented.
• V pinch-off is responsible for the current saturation in the output characteristics, which ultimately determines the short circuit current.
• the channel pinch-off voltage V pinch-off is determined by the threshold voltage V th .
• V ce the voltage drop perpendicular to the channel is less than V th and therefore the channel cannot sustain any longer near the drain end.
• V th (x) the local threshold voltage
• V th (x) the local threshold voltage
• the curve for the power semiconductor device 1 on the other hand consists of a non-uniform V th profile along the channel, where V th is locally raised near the channel end, that is, in the first part 44, such that V th-2 (L) > V th-1 in order to lower the pinch-off point, while V th-2’ ⁇ V th-1 in the rest of the channel to keep the overall channel resistance the same.
• V th-2 (L) > V th-1 in order to lower the pinch-off point
• V th-2’ ⁇ V th-1 in the rest of the channel to keep the overall channel resistance the same.
• N a is the channel body doping, ⁇ s is the permittivity of the semiconductor, C ox is the gate insulator capacitance, and ⁇ B is the semiconductor surface potential and: where k is the Boltzmann constant, T is the temperature and n i is the intrinsic carrier concentration of the semiconductor.
• the focus is on gate insulator thickness variation, but said thickness variation can of course be combined with a varying channel doping profile, a varying gate dielectric and/or a varying gate metal work function.
• Figures 1 and 2 above show schematic cross-sections of the reference semiconductor device 9 with uniform gate insulator thickness profile and of the power semiconductor device 1 with the non-uniform gate insulator thickness profile as implemented in the simulations presented below.
• Three different gate-oxide profiles were investigated, see Figure 8.
• the design referring to the reference semiconductor device 9 has a uniform gate-oxide thickness Tox of 100 nm, which served as a reference.
• Tox in the first part 44 was raised to 140 nm in order to increase the local V th (L) at that point, while Tox was reduced to 40 nm in the remaining part of the channel region 220 as to maintain the same on-state as that of the reference semiconductor device 9.
• Design B with even greater Tox at the first part 44 shows further improvement in I sat , however, with slightly higher V ce-sat which is increased by about 5% as compared to the reference semiconductor device 9, see Figure 10. This is attributed to relatively thicker Tox in the remainder of the gate insulator 4 along the channel region 220. As shown in Figure 11, a clear reduction, for example, of 20% or 40%, in the short circuit current can be observed for designs A and B, compared with the reference semiconductor device 9, as expected. As shown in Figure 12, the breakdown characteristics of the device remain unaffected with varying gate insulator profiles as expected. Switching losses Eoff remain largely unaffected with Tox profile variation, compare the list below that summarizes the simulation results for designs A and B with different Tox profiles.
• the length L of the channel is in each case 2.5 ⁇ m, and the first part 44 in designs A, B has a length of 1.0 ⁇ m.
• the thickness of the gate insulator 4 changes in two steps 43.
• the second step is larger than the first step, so that the thickness increase is larger at the step 43 close to the drift region 23, or vice versa.
• the thickness Tox of the gate insulator 4 increases monotonically towards the drift region 23.
• an outward side 40 of the gate insulator 4 facing the semiconductor body 2 may be of planar fashion, at least along the channel region 220.
• the thickness variation of the gate insulator 4 may affect an interior side of the gate insulator 4 only, the interior side faces the gate electrode 31.
• the power semiconductor device 1 of Figure 13 is not an IGBT, but a MOSFET or MISFET.
• the power semiconductor device 1 comprises a drain region 24 instead of the collector region 26.
• the drain region 24 which is of the first conductivity type, too, but, for example, with a maximum doping concentration higher than in the drift region 23.
• the drain region 24 there is a drain electrode 33.
• all the gate insulator designs of the IGBT power semiconductor devices 1 can apply for the MOSFET and MISFET power semiconductor device 1, and vice versa.
• all the power semiconductor devices 1 could be configured as a reverse-conducting IGBT.
• a reverse-conducting IGBT comprises a collector region of the second conductivity type alternating with shorts of the first conductivity type.
• the gate insulator 4 comprises a plurality of the steps 43, and the thickness is not monotonically increasing. Thus, there can be a minor first step to higher thicknesses near the source region 21 and a minor second step back to the original thickness, and there is a major third step to a higher, final thickness next to the drift region 23. Otherwise, the same as to Figures 2 to 13 may also apply to Figure 14, and vice versa. In Figure 15, it is illustrated that the thickness changes not in a stepped manner, but continuously at a beginning of the first 44.
• a transitional region 46 in which the thickness Tox changes, amounts, for example, to at least 2% and/or to at most 15% or to at most 10% or to at most 5% of the length L. Similar to Figures 13 or 14, there may be more than one such transitional region 46. Otherwise, the same as to Figures 2 to 14 may also apply to Figure 15, and vice versa.
• the gate insulator 4 is of a single continuous layer of the same material and having the varying thickness. Contrary to that, see Figure 16, the gate insulator 4 is of multi-layer fashion. For example, the gate insulator 4 comprises a third sub-layer 45 next to the semiconductor body 2 and extending completely between the latter and the gate electrode 31.
• first sub-layer 41 next to the gate electrode 31 and reaching into the drift region 23, as well as a second sub- layer 42 between the first and third sub-layers 41, 45.
• the first sub-layer 41 is only partially present through the well region 22 and is not present near the source region 21.
• the first sub-layer 41 it the thickest one of the sub-layers, and the second sub-layer 42 or alternatively the third sub-layer 45 is the thinnest sub-layer.
• Each one of the sub-layers 41, 42, 45 may have a thickness not varying within the respective sub-layer 41, 42, 45, so that the sub- layers 41, 42, 45 may each be of constant thickness. Where the first and second sub-layers 41, 42 end, there are the steps 43.
• the sub-layers 41, 42, 45 are not congruent. All the sub-layers 41, 42, 45 can be of the same material or can otherwise be of different materials.
• a length along which the second sub-layer 42 protrudes from the first sub-layer 41 amounts to at most 50% or to at most 30% of an extent of the first part 44 along the length L. Otherwise, the same as to Figures 2 to 15 may also apply to Figure 16, and vice versa.
• Figure 17 it is illustrated that a thickness of the gate insulator 4 increases in a strictly monotonically manner, for example, in a linear manner, throughout the well region 22.
• the power semiconductor device 1 is of a planar design and not of a trench design like, for example, the power semiconductor device 1 of Figures 2 and 3.
• the top side 20 is planar, and the gate insulator 4 and the gate electrode 31 are applied on the top side 20. Consequently, the length L between the source region 21 and the drift region 23 is in parallel with the top side 20, and not like in the other exemplary embodiments perpendicular to the top side 20. The same applies to the direction x along which the thickness Tox varies.
• the channel region 220 protrudes from the source region 21 in a lateral direction, that is, in parallel with the top side 20, and extends below the gate insulator 4. Also the source region 21 may extend below the gate insulator 4, but less far. All the above-mentioned different designs of the gate insulator 4 can analogously be applied to the planar concept of Figure 18, both in case of a MISFET or MOSFET as well in case of an IGBT. Hence, the same as to Figures 2 to 17 can also apply to Figure 18.
• FIG. 19 it is illustrated that there is not only the non-uniform gate insulator thickness profile, but also a non-uniform gate dielectric constant profile because of at least two different materials 81, 82, the gate insulator 4 is composed of. That is, the thickness of the gate insulator 4 varies along the channel region 220.
• a difference of the relative dielectric constant along the channel region 220 because of the at least two different materials 81, 82 is at least 2.0 or is at least 3.0 or is at least 3.5.
• said difference is at most 50 or is at most 25.
• the gate insulator 4 can be of a single material. Additionally or alternatively to the non-uniform gate dielectric constant profile, there can be a non-uniform gate electrode work function profile 72 of the gate electrode 31.
• the gate electrode 31 can include a first gate material 84 next to the source region 21 and a second gate material 85 next to the drain region 23. The gate materials 84, 85 may change where the materials 81, 82 of the gate insulator 4 change.
• a work function ⁇ m of the gate electrode 31 in the first part 44 remote from the source region 21 is largest for devices having a p-doped well region 22 and, thus, a p-doped channel region 220, and is smallest for devices having an n-doped well region 22 and, thus, a n- doped channel region 220.
• a work function difference of the gate electrode along the channel region 220 is at least 0.7 eV or is at least 1.0 eV or is at least 1.1 eV. This applies, for example, when the gate electrode 31 is based on poly-silicon.
• the work function difference may be at least 1.3 eV or at least 1.4 eV.
• the work function difference is at most 2.0 eV or at most 1.5 eV.
• the second gate material 85 is p + -doped poly- silicon having a work function ⁇ m of about 5.22 eV.
• the first gate material 84 is n + -doped poly-silicon having a work function ⁇ m of about 4.1 eV.
• non-uniform gate electrode work function profile 72 there is a step in the non-uniform gate electrode work function profile 72 at the interface between the first part 44 and the second part 47, see the insert in Figure 19.
• a non- uniform channel doping profile 71 there can be a non- uniform channel doping profile 71. That is, a doping concentration N A in the well region 22 varies along the channel region 220.
• a maximum doping concentration present in the non-uniform channel doping profile 71 is at least 5 x 10 16 cm -3 and at most 5 x 10 19 cm -3 and/or a minimum doping concentration present in the non-uniform channel doping profile 71 is at most 2 x 10 17 cm -3 or at most 1 x 10 17 cm -3 .
• the maximum doping concentration may be present in the first part 44, and the minimum doping concentration may be present in the second part 47.
• the doping concentration N A may be constant so that the doping concentration N A varies in a stepped manner, for example.
• a step in the doping concentration N A does not need to exactly follow a theta function or unit step function, but there can be of sinusoidal shape, see the insert in Figure 19.
• Said step may be at the location where the materials 81, 82 of the gate insulator 4 change.
• Such at least one of the non-uniform gate electrode work function profile 72, the non-uniform gate insulator dielectric constant profile and the non-uniform channel doping profile 71 can be present analogously in all the other exemplary embodiments, too. Otherwise, the same as to Figures 2 to 18 may also apply to Figure 19, and vice versa.

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• 2021
  • 2021-07-16 EP EP21186089.5A patent/EP4120360A1/en active Pending
• 2022
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  • 2022-07-13 CN CN202280050300.3A patent/CN117652033A/zh active Pending
  • 2022-07-13 WO PCT/EP2022/069637 patent/WO2023285550A1/en not_active Ceased

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