WO2023284395A1 - 电压转换电路与存储器 - Google Patents

电压转换电路与存储器 Download PDF

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Publication number
WO2023284395A1
WO2023284395A1 PCT/CN2022/092546 CN2022092546W WO2023284395A1 WO 2023284395 A1 WO2023284395 A1 WO 2023284395A1 CN 2022092546 W CN2022092546 W CN 2022092546W WO 2023284395 A1 WO2023284395 A1 WO 2023284395A1
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Prior art keywords
signal
type transistor
voltage
inverter
conversion circuit
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PCT/CN2022/092546
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English (en)
French (fr)
Inventor
冀康灵
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长鑫存储技术有限公司
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Publication of WO2023284395A1 publication Critical patent/WO2023284395A1/zh
Priority to US18/157,155 priority Critical patent/US20230170885A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Definitions

  • the present disclosure relates to the field of integrated circuits, in particular, to a voltage conversion circuit and a memory using the voltage conversion circuit.
  • level conversion unit In some application scenarios of memory, it is necessary to introduce a level conversion unit to convert a signal with a smaller level value into a signal with a higher level value, or to convert a signal with a higher level value into a signal with a lower level value signal of.
  • existing level shifting circuits also need to continuously optimize power consumption, speed and area.
  • the purpose of the present disclosure is to provide a voltage conversion circuit and a memory using the voltage conversion circuit, which are used to overcome limitations and defects due to related technologies at least to a certain extent.
  • a voltage conversion circuit including: a driving circuit powered by a first voltage, an output terminal outputs a first signal, and the high level voltage of the first signal is lower than the first voltage
  • the receiving circuit is powered by the first voltage, the first input terminal receives the first signal, the second input terminal receives the sampling signal, and is used to output a second signal according to the sampling signal, and the high of the second signal
  • the voltage of the level is equal to the first voltage.
  • the receiving circuit includes: a first P-type transistor, the gate of which is connected to the first input terminal, and the source of which is connected to the first voltage; a second P-type transistor, The gate is electrically connected to the second input terminal through the first inverter, and the source is connected to the drain of the first P-type transistor; for the first N-type transistor, the gate is connected to the first input terminal, and the source is grounded the second N-type transistor, the gate is electrically connected to the second input terminal, the source is connected to the drain of the first N-type transistor, and the drain is connected to the drain of the second P-type transistor; the second The drain of the N-type transistor is the output terminal of the receiving circuit.
  • the voltage conversion circuit further includes: a latch circuit, an input terminal of the latch circuit receives the second signal, and is used for latching the second signal.
  • the latch circuit includes: a second inverter, the input end of the second inverter is connected to the output end of the receiving circuit, and the second inverter The output end of the phaser is connected to the output end of the latch circuit; the third inverter, the input end of the third inverter is connected to the output end of the latch circuit, and the output of the third inverter The terminal is connected to the input terminal of the second inverter.
  • the third inverter when the sampling signal is in an enabled state, the third inverter is in an off state.
  • the enable level of the sampling signal occurs within a preset time period when the level of the first signal changes.
  • the duration of the enable level of the sampling signal is less than half of the high level time of the first signal.
  • the sampling signal is a pulse signal with a set period.
  • the duty cycle of the enable level in the sampling signal is less than 1/2.
  • the value of the high level of the first signal makes the pull-up capability of the first P-type transistor greater than the pull-down capability of the first N-type transistor.
  • the difference between the first voltage and the high level of the first signal is less than or equal to the threshold voltage of the first P-type transistor.
  • the driving circuit includes: a third N-type transistor and a fourth N-type transistor, the drain of the third N-type transistor is connected to the first voltage, the The source of the third N-type transistor is connected to the drain of the fourth N-type transistor, the source of the fourth N-type transistor is grounded, and the drain of the fourth N-type transistor is used as the output terminal of the driving circuit .
  • the gate of the third N-type transistor receives a first control signal
  • the gate of the fourth N-type transistor receives a second control signal
  • the first control The signal is opposite in phase to the second control signal
  • the size of the third N-type transistor is the same as that of the fourth N-type transistor.
  • a memory including the voltage conversion circuit described in any one of the above items.
  • Embodiments of the present disclosure use an N-type transistor powered by a first voltage to output a first signal, and use a receiving circuit to convert the first signal to generate a second signal whose high-level voltage is equal to the first voltage, which can reduce the output of the second signal.
  • the overall power consumption of the circuit at the time of the signal by using the sampling signal in the receiving circuit to sample the first signal with a lower voltage and then output the second signal, the first signal with a lower voltage can be converted into an output signal with a higher voltage using few components, reducing the Component footprint and power dissipation during voltage conversion.
  • FIG. 1 is a schematic structural diagram of a voltage conversion circuit in an exemplary embodiment of the present disclosure.
  • FIG. 2 is a circuit diagram of the receiving circuit 2 in one embodiment of the present disclosure.
  • FIG. 3 is a timing control diagram of the receiving circuit 2 in the embodiment shown in FIG. 2 .
  • 4A to 4D are schematic diagrams of equivalent circuits of the receiving circuit 2 shown in FIG. 2 under the timing control shown in FIG. 3 .
  • FIG. 5 is a circuit diagram of the latch circuit 3 in one embodiment of the present disclosure.
  • 6A to 6D are schematic diagrams of equivalent circuits of the circuit of the embodiment shown in FIG. 5 under the sequence shown in FIG. 3 .
  • FIG. 7 is a circuit diagram of a driving circuit in one embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of the overall circuit of the voltage conversion circuit in an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of example embodiments to those skilled in the art.
  • the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided in order to give a thorough understanding of embodiments of the present disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details being omitted, or other methods, components, devices, steps, etc. may be adopted.
  • well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a voltage conversion circuit in an exemplary embodiment of the present disclosure.
  • the voltage conversion circuit 100 may include:
  • the driving circuit 1 is powered by the first voltage Vcc, the output terminal outputs the first signal S1, and the high level voltage of the first signal S1 is lower than the first voltage Vcc;
  • the receiving circuit 2 is powered by the first voltage Vcc, the first input terminal IN1 receives the first signal S1, the second input terminal IN2 receives the sampling signal Ss, and is used to output the second signal S2 according to the sampling signal Ss, and the high of the second signal S2
  • the voltage of the level is equal to the first voltage Vcc.
  • FIG. 2 is a circuit diagram of the receiving circuit 2 in one embodiment of the present disclosure.
  • the receiving circuit 2 may include:
  • the first P-type transistor M1 the gate is connected to the first input terminal IN1, and the source is connected to the first voltage Vcc;
  • the gate of the second P-type transistor M2 is electrically connected to the second input terminal IN2 through the first inverter OP1, and the source is connected to the drain of the first P-type transistor M1;
  • the first N-type transistor M3, the gate is connected to the first input terminal IN1, and the source is grounded;
  • the second N-type transistor M4 the gate is electrically connected to the second input terminal IN2, the source is connected to the drain of the first N-type transistor M3, and the drain is connected to the drain of the second P-type transistor M2; the second N-type transistor M4 The drain is the output terminal OUT1 of the receiving circuit.
  • the receiving circuit 2 provided by the embodiment of the present disclosure can be implemented with fewer components, which greatly reduces the occupied area and power consumption of the components for the voltage conversion function.
  • the receiving circuit 2 works under the first voltage Vcc, therefore, the conversion signal generated by the first P-type transistor M1 and the first N-type transistor M3 according to the first signal S1 (not shown, through the above two The drain output of a transistor) is a signal under the first voltage Vcc, the conversion signal is sampled by the second P-type transistor M2 and the second N-type transistor M4, and the second signal whose high level is the first voltage Vcc can be output. S2, implementing voltage boosting of the first signal S1.
  • the enable level of the sampling signal Ss may appear within a preset time period when the level of the first signal S1 changes, that is, the sampling signal Ss may be triggered by the polarity change of the first signal S1, thereby The timing of the second signal S2 is made consistent with that of the first signal S1.
  • the sampling signal Ss can also be a pulse signal with a set period, so as to convert the aperiodic first signal S1 into a periodic second signal S2, making the timing of the signal easier to control
  • the first signal S1 with different timings can form a signal group with the same timing by processing the sampling signals, which is more conducive to the use of subsequent circuits.
  • the enable level of the sampling signal Ss is a high level, which is equal to the first voltage Vcc.
  • the gate of the second P-type transistor M2 is connected to the second input terminal IN2 through the first inverter OP1 (as shown in FIG. 2 ), and the gate of the second N-type transistor M4 is connected to the second input terminal IN2.
  • the enable level of the sampling signal Ss is a low level, and the low level may be a zero potential.
  • the gate of the second P-type transistor M2 is connected to the second input terminal IN2 (not shown), and the gate of the second N-type transistor M4 is connected to the second input terminal IN2 through the first inverter OP1.
  • FIG. 3 is a timing control diagram of the receiving circuit 2 in the embodiment shown in FIG. 2 .
  • the first signal S1 is a periodic signal
  • the sampling signal Ss is also a periodic signal.
  • the sampling signal Ss appears within the preset time when the level of the first signal S1 changes, and the second signal S2 follows the sampling signal.
  • the level change range of the first signal S1 is from the second voltage Vcc_Low to zero potential (the second voltage Vcc_Low is smaller than the first voltage Vcc), and the inversion signal of the sampling signal Ss after passing through the first inverter OP1, the second The level change range of the signal S2 is from the first voltage Vcc to zero potential.
  • 4A to 4D are schematic diagrams of equivalent circuits of the receiving circuit 2 shown in FIG. 2 under the timing control shown in FIG. 3 .
  • the first P-type transistor M1, the second P-type transistor M2, and the second N-type transistor M4 are turned on, and the first N-type transistor M3 is turned off, and at this moment, the first voltage Vcc is output to the output terminal OUT1 through the first P-type transistor M1 and the second P-type transistor M2 to generate a current I1, so that the second signal S2 is Vcc, that is, a high level.
  • the second P-type transistor M2, the first N-type transistor M3, and the second N-type transistor M4 are turned on, and the first P-type transistor M1 is turned off (or at least the pull-up capability of M1 is less than the pull-down capability of M3), at this time, the output terminal OUT1 is grounded through the first N-type transistor M3 and the second N-type transistor M4, generating a discharge current I2, so that the second signal S2 is 0, that is, low level.
  • the first P-type transistor M1 may not be completely turned off, and there will be A certain charging current I3, the charging current I3 is from Vcc to the output terminal OUT1, and the discharging current I2 is from the output terminal OUT1 to the ground terminal.
  • the value of the second voltage Vcc_Low needs to make the pull-up capability of the first P-type transistor M1 less than The pull-down capability of the first N-type transistor M3.
  • the difference between the first voltage Vcc and the second voltage Vcc_Low may be less than or equal to the threshold voltage Vp1 of the first P-type transistor M1, and the value of Vp1 may be 0.5V, for example.
  • the receiving circuit 2 can convert the first signal S1 with a lower voltage range (Vcc_Low ⁇ 0) into a second signal with a higher voltage range (Vcc ⁇ 0). S2, the phase of the second signal S2 is opposite to that of the first signal S1.
  • an inverter can be connected to the output terminal OUT1 , which will not be repeated here.
  • the output terminal OUT1 when the sampling signal Ss is at a low level, no matter what kind of signal the first signal S1 is, the output terminal OUT1 does not produce a signal change.
  • one way is to control the sampling signal Ss to always be at a high level, and at this time the second P-type transistor M2 and the second N-type transistor can also be removed. M4, but this method will continuously generate a charging current I3 to the ground when the first signal S1 is at a high level, resulting in an increase in power consumption of the circuit.
  • Another way is to connect a latch after the output terminal OUT1, so that when the sampling signal Ss is at low level, the output signal of the whole circuit can still remain unchanged.
  • FIG. 5 is a circuit diagram of a latch circuit in another embodiment of the present disclosure.
  • the voltage conversion circuit further includes a latch circuit 3 , and an input terminal of the latch circuit 3 receives the second signal S2 for latching the second signal S2 .
  • the latch circuit 3 may include:
  • the second inverter OP2 the input end of the second inverter OP2 is connected to the output end OUT1 of the receiving circuit 2, and the output end of the second inverter OP2 is connected to the output end OUT2 of the latch circuit 3;
  • the third inverter OP3 the input end of the third inverter OP3 is connected to the output end OUT2 of the latch circuit 3, and the output end of the third inverter OP3 is connected to the input end of the second inverter OP2.
  • both the second inverter OP2 and the third inverter OP3 are connected to the first voltage Vcc, which is not shown in the figure.
  • 6A to 6D are schematic diagrams of equivalent circuits of the circuit shown in FIG. 5 under the sequence shown in FIG. 3 .
  • the first P-type transistor M1, the second P-type transistor M2, and the second N-type transistor M4 are turned on, and the first N-type transistor M3 is turned off (or at least the pull-up capability of M1 is less than the pull-down capability of M3), at this time the first voltage Vcc is output to the output terminal OUT1 of the receiving circuit 2 through the first P-type transistor M1 and the second P-type transistor M2, generating a current I1, make the second signal S2 be Vcc, that is, high level.
  • the second signal S2 enters the second inverter OP2 and outputs a low-level third signal S3 through the output terminal OUT2, and the phase of the third signal S3 is synchronized with the phase of the sampling signal Ss.
  • the third signal S3 output from the output terminal OUT2 returns to the output terminal OUT1 through the third inverter OP3, and is still at a high level. Since the third inverter OP3 does not need to work to maintain the voltage of the second signal S2 at this time, in order to reduce power consumption, the third inverter OP3 can be controlled to be turned off in this state.
  • the second P-type transistor M2, the first N-type transistor M3, and the second N-type transistor M4 are turned on, and the first P-type transistor M1 is turned off, and at this time the drain of the second N-type transistor M4 is grounded through the first N-type transistor M3 and the second N-type transistor M4 to generate a discharge current I2, so that the second signal S2 is 0, ie a low level.
  • the high level of the first signal S1 is Vcc_Low, the first P-type transistor M1 will not be completely turned off, and there will be a certain charging current I3.
  • the second signal S2 passes through the second inverter OP2 and outputs a high-level third signal S3 through the output terminal OUT2, and the phase of the third signal S3 is synchronized with the phase of the sampling signal Ss.
  • the third signal S3 returns to the output terminal OUT1 through the third inverter OP3, and is still at a low level. Since the third inverter OP3 does not need to work to maintain the voltage of the third signal S3 at this time, in order to reduce power consumption, the third inverter OP3 can be controlled to be turned off in this state. That is, when the sampling signal Ss is in the enable state, the third inverter OP3 can be set in the off state.
  • the third inverter OP3 can be enabled to form a feedback path between the output terminal OUT1 and the output terminal OUT2, since the second inverter OP2 and The third inverter OP3 is an active device, so when the latch circuit 3 is working, it can maintain the voltage of the output terminal OUT1 , and then maintain the voltage of the output terminal OUT2 unchanged.
  • FIG. 6D The embodiment shown in FIG. 6D is the same, and the present disclosure will not repeat it here.
  • sampling signal Ss Since the sampling signal Ss is in an enabled state and the first signal S1 is at a high level, a charging current I3 will be generated to increase power consumption.
  • the latch circuit 3 When the latch circuit 3 is used to maintain the output signal unchanged, the use of the sampling signal Ss can be reduced as much as possible. The energy state can be maintained for a long time, so as to reduce the power consumption of the circuit.
  • the maintaining time of the enabling level of the sampling signal Ss may be shorter than the first signal S1, for example. Half of the high level time of a signal S1.
  • the duty ratio of the enable level in the sampling signal Ss may be less than 1/2, for example.
  • the duty cycle of the sampling signal Ss may be lower, for example, may be less than 1/4, less than 1/10 or less than 1/20.
  • the charging current I3 can also be reduced.
  • FIG. 7 is a circuit diagram of a driving circuit in one embodiment of the present disclosure.
  • the driving circuit 1 may include:
  • the sources of the four N-type transistors M6 are grounded, and the drain of the fourth N-type transistor M6 serves as the output terminal of the driving circuit 1 and is connected to the first input terminal IN1 of the receiving circuit 2 .
  • the size of the third N-type transistor M5 is the same as that of the fourth N-type transistor M6.
  • the gate of the third N-type transistor M5 can receive the first control signal CON1
  • the gate of the fourth N-type transistor M6 can receive the second control signal CON2
  • the first control signal The phases of CON1 and the second control signal CON2 are opposite.
  • both the first control signal CON1 and the second control signal CON2 are generated through control signals output from the control port CON.
  • a fourth inverter OP4 and a fifth inverter OP5 are arranged between the control port CON and the gate of the third N-type transistor M5, and a sixth inverter OP4 is arranged between the control port CON and the gate of the fourth N-type transistor M6.
  • the inverter OP6 has ensured the inversion between the first control signal CON1 and the second control signal CON2.
  • an inverter may also be set between the control port CON and the gate of the third N-type transistor M5, and two inverters may be set between the control port CON and the gate of the fourth N-type transistor M6. Inverter for the same purpose.
  • the complete inversion of the first control signal CON1 and the second control signal CON2 may also be implemented in other ways, which is not specifically limited in the present disclosure.
  • the driving circuit 1 shown in FIG. 7 when the control signal of the control port CON is at a high level, the third N-type transistor M5 is turned on, and the fourth N-type transistor M6 is turned off, and the output can be output through the source of the third N-type transistor M5.
  • the voltage Vcc-VthN where VthN is the threshold voltage of the third N-type transistor M5, is greater than zero.
  • the control signal of the control port CON is at a low level
  • the third N-type transistor M5 is turned off, and the fourth N-type transistor M6 is turned on, so that the drain of the fourth N-type transistor M6 can pass a low voltage (zero potential).
  • the driving circuit 1 can output the first signal S1 whose high level is Vcc-VthN and whose low level is zero potential according to the change of the control signal of the control port CON.
  • the embodiment shown in FIG. 7 outputs high level through NMOS (that is, the pull-up transistor is changed from PMOS to NMOS), which can reduce the overall power consumption of the circuit.
  • FIG. 8 is a schematic diagram of the overall circuit of the voltage conversion circuit in an embodiment of the present disclosure.
  • the drive circuit 1 since the drive circuit 1 outputs a high level through the N-type transistor, the overall power consumption of the drive circuit 1 can be reduced, and the output high level is lower than the first voltage Vcc.
  • the receiving circuit 2 shown in FIG. 2 or FIG. 5 is connected behind the driving circuit 1 , and the second signal S2 with a high level of Vcc and a low level of zero potential can be generated according to the first signal S1 .
  • the sampling signal Ss can be set to output the sampling level of the enabled state after the preset time of the level transition of the control signal CON0 input to the control port CON, and the duration of the sampling level As short as possible, so that the first signal S1 generated according to the first control signal CON1 and the second control signal CON2 can be sampled through the sampling signal Ss, so that the phase of the control signal CON0 has a fixed delay and the level direction is output through the output terminal OUT2
  • the third signal S3 is the same, and the high level is Vcc, and the low level is zero level.
  • the voltage conversion circuit Due to the simple structure of the receiving circuit 2, the power consumption is low. Compared with the related technology, the voltage conversion circuit provided by the embodiment of the present disclosure can realize the output of the signal whose high level is Vcc and the low level is zero potential through a simple structure and low power consumption, and greatly reduces the The components of the voltage converting circuit occupy an area, and the volume of the components is reduced.
  • a memory including the voltage conversion circuit as shown in any one of the above embodiments. From the above description, it can be seen that the memory provided with the voltage conversion circuit provided by the embodiment of the present disclosure can have lower power consumption and smaller occupied area of components, and the present disclosure will not be repeated here.
  • Embodiments of the present disclosure use an N-type transistor powered by a first voltage to output a first signal, and use a receiving circuit to convert the first signal to generate a second signal whose high-level voltage is equal to the first voltage, which can reduce the output of the second signal.
  • the overall power consumption of the circuit at the time of the signal by using the sampling signal in the receiving circuit to sample the first signal with a lower voltage and then output the second signal, the first signal with a lower voltage can be converted into an output signal with a higher voltage using few components, reducing the Component footprint and power dissipation during voltage conversion.

Abstract

一种电压转换电路（100）与存储器。电压转换电路（100）包括：驱动电路（1），由第一电压（Vcc）供电，输出端输出第一信号（S1），所述第一信号（S1）的高电平的电压小于所述第一电压（Vcc）；接收电路（2），由所述第一电压（Vcc）供电，第一输入端（IN1）接收所述第一信号（S1），第二输入端（IN2）接收采样信号（Ss），用于根据所述采样信号（Ss）输出第二信号（S2），所述第二信号（S2）的高电平的电压等于所述第一电压（Vcc）。该电压转换电路（100）具有较低的功率和较小的元件占用面积。

Description

电压转换电路与存储器
交叉引用
本公开要求于2021年07月16日提交的申请号为202110808613.8、名称为“电压转换电路与存储器”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及集成电路领域，具体而言，涉及一种电压转换电路以及应用该电压转换电路的存储器。
背景技术
在存储器的某些应用场景中，需要引入电平转换单元来将电平值较小的信号转换为电平值较高的信号，或者将电平值较高的信号转换为电平值较小的信号。随着存储器对功耗、速度和面积的要求越来越高，现有的电平转换电路也需要不断的对功耗、速度和面积进行优化。
因此，需要一种能兼顾低功耗、元件占用面积小的电压转换电路。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种电压转换电路以及应用该电压转换电路的存储器，用于至少在一定程度上克服由于相关技术的限制和缺陷。
根据本公开的第一方面，提供一种电压转换电路，包括：驱动电路，由第一电压供电，输出端输出第一信号，所述第一信号的高电平的电压小于所述第一电压；接收电路，由所述第一电压供电，第一输入端接收所述第一信号，第二输入端接收采样信号，用于根据所述采样信号输出第二信号，所述第二信号的高电平的电压等于所述第一电压。
在本公开的一种示例性实施例方式中，所述接收电路包括：第一P型晶体管，栅极连接所述第一输入端，源极连接所述第一电压；第二P型晶体管，栅极通过第一反相器电连接所述第二输入端，源极连接所述第一P型晶体管的漏极；第一N型晶体管，栅极连接所述第一输入端，源极接地；第二N型晶体管，栅极电连接所述第二输入端，源极连接所述第一N型晶体管的漏极，漏极连接所述第二P型晶体管的漏极；所述第二N型晶体管的漏极为所述接收电路的输出端。
在本公开的一种示例性实施例方式中，电压转换电路还包括：锁存电路，所述锁存电路的输入端接收所述第二信号，用于锁存所述第二信号。
在本公开的一种示例性实施例方式中，所述锁存电路包括：第二反相器，所述第二反相器的输入端连接所述接收电路的输出端，所述第二反相器的输出端连接所述锁存电路的输出端；第三反相器，所述第三反相器的输入端连接所述锁存电路的输出端，所述第三反相器的输出端连接所述第二反相器的输入端。
在本公开的一种示例性实施例方式中，在所述采样信号为使能状态时，所述第三反相器为关闭状态。
在本公开的一种示例性实施例方式中，所述采样信号的使能电平出现在所述第一信号发生电平改变的预设时间内。
在本公开的一种示例性实施例方式中，所述采样信号的使能电平的维持时间小于所述第一信号中高电平时间的一半。
在本公开的一种示例性实施例方式中，所述采样信号为设定周期的脉冲信号。
在本公开的一种示例性实施例方式中，所述采样信号中的使能电平的占空比小于1/2。
在本公开的一种示例性实施例方式中，所述第一信号的高电平的值使得所述第一P型晶体管的上拉能力大于所述第一N型晶体管的下拉能力。
在本公开的一种示例性实施例方式中，所述第一电压与所述第一信号的高电平的差值小于等于所述第一P型晶体管的阈值电压。
在本公开的一种示例性实施例方式中，所述驱动电路包括：第三N型晶体管和第四N型晶体管，所述第三N型晶体管的漏极连接所述第一电压，所述第三N型晶体管的源极连接所述第四N型晶体管的漏极，所述第四N型晶体管的源极接地，所述第四N型晶体管的漏极作为所述驱动电路的输出端。
在本公开的一种示例性实施例方式中，所述第三N型晶体管的栅极接收第一控制信号，所述第四N型晶体管的栅极接收第二控制信号，所述第一控制信号与所述第二控制信号的相位相反。
在本公开的一种示例性实施例方式中，所述第三N型晶体管的尺寸与所述第四N型晶体管的尺寸相同。
根据本公开的第二方面，提供一种存储器，包括如上任一项所述的电压转换电路。
本公开实施例使用由第一电压供电的N型晶体管输出第一信号，并使用接收电路对第一信号进行转换以生成高电平电压等于第一电压的第二信号，可以降低输出该第二信号时电路的整体功耗。此外，通过在接收电路中使用采样信号对较低电压的第一信号进行采样后输出第二信号，可以使用很少的元件将电压较低的第一信号转换为电压较高的输出信号，降低电压转换过程中元件的占用面积和功耗。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开示例性实施例中电压转换电路的结构示意图。
图2是本公开一个实施例中接收电路2的电路图。
图3是图2所示实施例中接收电路2的时序控制图。
图4A～图4D是图3所示时序控制下图2所示接收电路2的等效电路示意图。
图5是本公开一个实施例中锁存电路3的电路图。
图6A～图6D是图5所示实施例的电路在图3所示时序下的等效电路示意图。
图7是本公开一个实施例中驱动电路的电路图。
图8是本公开一个实施例中电压转换电路整体电路的示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
下面结合附图对本公开示例实施方式进行详细说明。
图1是本公开示例性实施例中电压转换电路的结构示意图。
参考图1，电压转换电路100可以包括：
驱动电路1，由第一电压Vcc供电，输出端输出第一信号S1，第一信号S1的高电平的电压小于第一电压Vcc；
接收电路2，由第一电压Vcc供电，第一输入端IN1接收第一信号S1，第二输入端IN2接收采样信号Ss，用于根据采样信号Ss输出第二信号S2，第二信号S2的高电平的电压等于第一电压Vcc。
图2是本公开一个实施例中接收电路2的电路图。
参考图2，在一个实施例中，接收电路2可以包括：
第一P型晶体管M1，栅极连接第一输入端IN1，源极连接第一电压Vcc；
第二P型晶体管M2，栅极通过第一反相器OP1电连接第二输入端IN2，源极连接第一P型晶体管M1的漏极；
第一N型晶体管M3，栅极连接第一输入端IN1，源极接地；
第二N型晶体管M4，栅极电连接第二输入端IN2，源极连接第一N型晶体管M3的漏极，漏极连接第二P型晶体管M2的漏极；第二N型晶体管M4的漏极为接收电路的输出端OUT1。
由于结构简单，本公开实施例提供的接收电路2可以通过较少的元件实现，极大降低了电压转换功能的元件占用面积和功耗。
在本公开实施例中，接收电路2工作在第一电压Vcc下，因此，第一P型晶体管M1、第一N型晶体管M3根据第一信号S1生成的转换信号(未示出，通过上述两个晶体管的漏极输出)为第一电压Vcc下的信号，通过第二P型晶体管M2和第二N型晶体管M4对该转换信号采样，可以输出高电平为第一电压Vcc的第二信号S2，实现对第一信号S1的电压抬升。
在本公开一个实施例中，采样信号Ss的使能电平可以出现在第一信号S1发生电平改变的预设时间内，即采样信号Ss可以被第一信号S1的极性变化触发，从而使第二信号S2的时序与第一信号S1一致。
在本公开的另一个实施例中，采样信号Ss也可以为设定周期的脉冲信号，从而将非周期性的第一信号S1转换为周期性的第二信号S2，使信号的时序更加容易控制，不同时序的第一信号S1可以通过采样信号的处理形成相同时序的信号组，更有利于后续电路的使用。
在一个实施例中，采样信号Ss的使能电平为高电平，该高电平等于第一电压Vcc。此时第二P型晶体管M2的栅极通过第一反相器OP1连接第二输入端IN2(如图2所示)，第二N型晶体管M4的栅极连接第二输入端IN2。在另一个实施例中，采样信号Ss的使能电平为低电平，该低电平可以为零电位。此时第二P型晶体管M2的栅极连接第二输入端IN2(未示出)，第二N型晶体管M4的栅极通过第一反相器OP1连接第二输入端IN2。
下面，通过控制时序说明图2所示实施例的接收电路2的工作原理。
图3是图2所示实施例中接收电路2的时序控制图。
在图3所示实施例中，第一信号S1是周期信号，采样信号Ss也是周期信号，采样信号Ss出现在第一信号S1发生电平变换的预设时间内，第二信号S2随采样信号Ss的出现而发生电平变化。此时，第一信号S1的电平变化范围是第二电压Vcc_Low至零电位(第二电压Vcc_Low小于第一电压Vcc)，采样信号Ss经过第一反相器OP1后的反相信号、第二信号S2的电平变化范围均为第一电压Vcc至零电位。
图4A～图4D是图3所示时序控制下图2所示接收电路2的等效电路示意图。
参考图4A，当第一信号S1为低电平、采样信号Ss为高电平时，第一P型晶体管M1、第二P型晶体管M2、第二N型晶体管M4导通，第一N型晶体管M3关断，此时第一电压Vcc通过第一P型晶体管M1和第二P型晶体管M2输出到输出端OUT1，产生电流I1，使第二信号S2为Vcc，即高电平。
参考图4B，当第一信号S1为高电平、采样信号Ss为高电平时，第二P型晶体管M2、第一N型晶体管M3、第二N型晶体管M4导通，第一P型晶体管M1关断(或至少M1的上拉能力小于M3的下拉能力)，此时输出端OUT1通过第一N型晶体管M3和第二N型晶体管M4接地，产生放电电流I2，使第二信号S2为0，即低电平。可以理解的是，由于第一信号S1的高电平为Vcc_Low，而Vcc_Low小于Vcc(例如Vcc_Low为0.5V、Vcc为1.2V)，因此第一P型晶体管M1也许不会完全关断，会存在一定的充电电流I3，充电电流I3是从Vcc到输出端OUT1，放电电流I2是从输出端OUT1到接地端。
为了使充电电流I3远小于放电电流I2，从而使输出端OUT1的第二信号S2达到0V，在本公开实施例中，第二电压Vcc_Low的值需要使第一P型晶体管M1的上拉能力小于第一N型晶体管M3的下拉能力。在本公开的一种示例性实施例中，第一电压Vcc与第二电压Vcc_Low的差值例如可以小于等于第一P型晶体管M1的阈值电压Vp1，而Vp1的值例如可以为0.5V。
从图4A和图4B所示实施例可以看出，接收电路2能够将电压变化范围较低(Vcc_Low～0)的第一信号S1转换为电压变化范围较高(Vcc～0)的第二信号S2，第二信号S2的相位与第一信号S1相反。
如果需要设置第二信号S2的相位与第一信号S1相同，可以在输出端OUT1接入反相器，本公开于此不再赘述。
参考图4C和图4D，当采样信号Ss为低电平时，无论第一信号S1为何种信号，输出端OUT1均不产生信号变动。为了使输出端OUT1的第二信号S2与第一信号S1相位相同，一种方式是控制采样信号Ss常为高电平，此时也可以移除第二P型晶体管M2和第二N型晶体管M4，但是这种方式会在第一信号S1为高电平时，持续产生到地的充电电流I3，造成电路功耗上升。另一种方式是，在输出端OUT1后接入锁存器，以在采样信号Ss为低电平时，使整个电路的输出信号仍然能够保持不变。
图5是本公开另一个实施例中锁存电路的电路图。
参考图5，在本公开另一个实施例中，电压转换电路还包括锁存电路3，锁存电路3的输入端接收第二信号S2，用于锁存第二信号S2。如图5所示，在一个实施例中，锁存电路3可以包括：
第二反相器OP2，第二反相器OP2的输入端连接接收电路2的输出端OUT1，第二反相器OP2的输出端连接锁存电路3的输出端OUT2；
第三反相器OP3，第三反相器OP3的输入端连接锁存电路3的输出端OUT2，第三 反相器OP3的输出端连接第二反相器OP2的输入端。
在图5所示实施例中，第二反相器OP2和第三反相器OP3均连接第一电压Vcc，图中未示出。
图6A～图6D是图5所示电路在图3所示时序下的等效电路示意图。
参考图6A，当第一信号S1为低电平、采样信号Ss为高电平时，第一P型晶体管M1、第二P型晶体管M2、第二N型晶体管M4导通，第一N型晶体管M3关断(或至少M1的上拉能力小于M3的下拉能力)，此时第一电压Vcc通过第一P型晶体管M1和第二P型晶体管M2输出到接收电路2的输出端OUT1，产生电流I1，使第二信号S2为Vcc，即高电平。
第二信号S2进入第二反相器OP2并通过输出端OUT2输出低电平的第三信号S3，第三信号S3的相位与采样信号Ss的相位同步。输出端OUT2输出的第三信号S3经第三反相器OP3返回到输出端OUT1，仍旧为高电平。由于此时无需第三反相器OP3工作以维持第二信号S2的电压，为了减少功耗，可以在此状态下控制第三反相器OP3为关闭状态。
参考图6B，当第一信号S1为高电平、采样信号Ss为高电平时，第二P型晶体管M2、第一N型晶体管M3、第二N型晶体管M4导通，第一P型晶体管M1关断，此时第二N型晶体管M4的漏极通过第一N型晶体管M3和第二N型晶体管M4接地，产生放电电流I2，使第二信号S2为0，即低电平。可以理解的是，由于第一信号S1的高电平为Vcc_Low，因此第一P型晶体管M1不会完全关断，会存在一定的充电电流I3。
第二信号S2经第二反相器OP2并通过输出端OUT2输出高电平的第三信号S3，第三信号S3的相位与采样信号Ss的相位同步。第三信号S3经第三反相器OP3返回到输出端OUT1，仍旧为低电平。由于此时无需第三反相器OP3工作以维持第三信号S3的电压，为了减少功耗，可以在此状态下控制第三反相器OP3为关闭状态。即，在采样信号Ss为使能状态时，可以设置第三反相器OP3为关闭状态。
参考图6C，当采样信号Ss为低电平时，无论第一信号S1为何种信号，输出端OUT1均不产生信号变动。在此状态形成之前，即在控制采样信号Ss为低电平之前，可以使能第三反相器OP3，在输出端OUT1和输出端OUT2之间形成反馈通路，由于第二反相器OP2和第三反相器OP3均为有源器件，因此锁存电路3工作时可以维持输出端OUT1的电压，进而维持输出端OUT2的电压不变。图6D所示实施例同理，本公开于此不再赘述。
由于采样信号Ss为使能状态、第一信号S1为高电平时，会产生充电电流I3，增加功耗，当使用锁存电路3维持输出信号不变时，可以尽可能缩减采样信号Ss的使能状态维持时间，以降低电路功耗。
在本公开的一个实施例中，当采样信号Ss的使能电平出现在第一信号S1发生电平改变的预设时间内时，采样信号Ss的使能电平的维持时间例如可以小于第一信号S1中高电平时间的一半。
在本公开的另一个实施例中，当采样信号Ss为设定周期的脉冲信号时，采样信号Ss中的使能电平的占空比例如可以小于1/2。为了进一步减小功耗，采样信号Ss的占空比可以更低，例如可以小于1/4、小于1/10或者小于1/20。
以上数值仅为示例，在实际应用中，本领域技术人员可以根据实际情况自行设置采样信号Ss的使能电平维持时间。
此外，通过减小第二P型晶体管M2和第二N型晶体管M4的尺寸，也可以降低充电电流I3。
图7是本公开一个实施例中驱动电路的电路图。
参考图7，在本公开的一个实施例中，驱动电路1可以包括：
第三N型晶体管M5和第四N型晶体管M6，第三N型晶体管M5的漏极连接第一电压Vcc，第三N型晶体管M5的源极连接第四N型晶体管M6的漏极，第四N型晶体管M6的源极接地，第四N型晶体管M6的漏极作为驱动电路1的输出端，连接接收电路2的第一输入端IN1。在本公开的一种示例性实施例方式中，第三N型晶体管M5的尺寸与第四N型晶体管M6的尺寸相同。
在本公开的一种示例性实施例方式中，第三N型晶体管M5的栅极可以接收第一控制信号CON1，第四N型晶体管M6的栅极接收第二控制信号CON2，第一控制信号CON1与第二控制信号CON2的相位相反。
在图7所示实施例中，第一控制信号CON1与第二控制信号CON2均通过控制端口CON输出的控制信号生成。控制端口CON与第三N型晶体管M5的栅极之间设置有第四反相器OP4以及第五反相器OP5，控制端口CON与第四N型晶体管M6的栅极之间设置有第六反相器OP6，已保证第一控制信号CON1与第二控制信号CON2之间反相。在另一些实施例中，也可以在控制端口CON与第三N型晶体管M5的栅极之间设置一个反相器，在控制端口CON与第四N型晶体管M6的栅极之间设置两个反相器，以实现同样目的。或者，在本公开的其他实施例中，也可以通过其他方式实现第一控制信号CON1与第二控制信号CON2的完全反相，本公开对此不作特殊限制。
图7所示的驱动电路1在控制端口CON的控制信号为高电平时，第三N型晶体管M5导通，第四N型晶体管M6关断，能够通过第三N型晶体管M5的源极输出电压Vcc-VthN，其中VthN为第三N型晶体管M5的阈值电压，大于零。在控制端口CON的控制信号为低电平时，第三N型晶体管M5关断，第四N型晶体管M6导通，能够通过第四N型晶体管M6的漏极低电压(零电位)。进而，驱动电路1能够根据控制端口CON的控制信号的变化输出高电平为Vcc-VthN、低电平为零电位的第一信号S1。
相较于相关技术中通过CMOS结构输出高电平，图7所示实施例通过NMOS(即上拉管从PMOS改为NMOS)输出高电平，能够降低电路的整体功耗。
图8是本公开一个实施例中电压转换电路整体电路的示意图。
参考图8，由于驱动电路1通过N型晶体管输出高电平，可以降低驱动电路1的整体 功耗，输出的高电平小于第一电压Vcc。而本公开实施例在驱动电路1后连接如图2或图5所示的接收电路2，可以根据第一信号S1生成高电平为Vcc、低电平为零电位的第二信号S2。
在图8所示电路实施例中，可以设置采样信号Ss在控制端口CON输入的控制信号CON0发生电平转换的预设时间后输出使能状态的采样电平，且该采样电平的持续时间尽可能短，这样能够通过采样信号Ss对根据第一控制信号CON1和第二控制信号CON2生成的第一信号S1进行采样，以通过输出端OUT2输出与控制信号CON0相位具有固定延迟、电平方向相同，且高电平为Vcc、低电平为零电平的第三信号S3。
由于接收电路2结构简单，功耗低。相较于相关技术，本公开实施例提供的电压转换电路能够通过简单的结构和较低的功耗实现高电平为Vcc、低电平为零电位的信号的输出，并且极大减小了该电压转换电路的元件占用面积，缩小元件体积。
根据本公开的第二方面，提供一种存储器，包括如上任一实施例所示的电压转换电路。通过上述描述可知，设置有本公开实施例提供的电压转换电路的存储器能够具有较低的功耗和较小的元件占用面积，本公开于此不再赘述。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和构思由权利要求指出。
工业实用性
本公开实施例使用由第一电压供电的N型晶体管输出第一信号，并使用接收电路对第一信号进行转换以生成高电平电压等于第一电压的第二信号，可以降低输出该第二信号时电路的整体功耗。此外，通过在接收电路中使用采样信号对较低电压的第一信号进行采样后输出第二信号，可以使用很少的元件将电压较低的第一信号转换为电压较高的输出信号，降低电压转换过程中元件的占用面积和功耗。

Claims (15)

  1. 一种电压转换电路，包括：
    驱动电路，由第一电压供电，输出端输出第一信号，所述第一信号的高电平的电压小于所述第一电压；
    接收电路，由所述第一电压供电，第一输入端接收所述第一信号，第二输入端接收采样信号，用于根据所述采样信号输出第二信号，所述第二信号的高电平的电压等于所述第一电压。
  2. 如权利要求1所述的电压转换电路，其中，所述接收电路包括：
    第一P型晶体管，栅极连接所述第一输入端，源极连接所述第一电压；
    第二P型晶体管，栅极通过第一反相器电连接所述第二输入端，源极连接所述第一P型晶体管的漏极；
    第一N型晶体管，栅极连接所述第一输入端，源极接地；
    第二N型晶体管，栅极电连接所述第二输入端，源极连接所述第一N型晶体管的漏极，漏极连接所述第二P型晶体管的漏极；
    所述第二N型晶体管的漏极为所述接收电路的输出端。
  3. 如权利要求1所述的电压转换电路，其中，还包括：
    锁存电路，所述锁存电路的输入端接收所述第二信号，用于锁存所述第二信号。
  4. 如权利要求3所述的电压转换电路，其中，所述锁存电路包括：
    第二反相器，所述第二反相器的输入端连接所述接收电路的输出端，所述第二反相器的输出端连接所述锁存电路的输出端；
    第三反相器，所述第三反相器的输入端连接所述锁存电路的输出端，所述第三反相器的输出端连接所述第二反相器的输入端。
  5. 如权利要求4所述的电压转换电路，其中，在所述采样信号为使能状态时，所述第三反相器为关闭状态。
  6. 如权利要求1～5任一项所述的电压转换电路，其中，所述采样信号的使能电平出现在所述第一信号发生电平改变的预设时间内。
  7. 如权利要求6所述的电压转换电路，其中，所述采样信号的使能电平的维持时间小于所述第一信号中高电平时间的一半。
  8. 如权利要求1～5任一项所述的电压转换电路，其中，所述采样信号为设定周期的脉冲信号。
  9. 如权利要求8所述的电压转换电路，其中，所述采样信号中的使能电平的占空比小于1/2。
  10. 如权利要求2所述的电压转换电路，其中，所述第一信号的高电平的值使得所述第一P型晶体管的上拉能力大于所述第一N型晶体管的下拉能力。
  11. 如权利要求2所述的电压转换电路，其中，所述第一电压与所述第一信号的高电平的差值小于等于所述第一P型晶体管的阈值电压。
  12. 如权利要求1所述的电压转换电路，其中，所述驱动电路包括：
    第三N型晶体管和第四N型晶体管，所述第三N型晶体管的漏极连接所述第一电压，所述第三N型晶体管的源极连接所述第四N型晶体管的漏极，所述第四N型晶体管的源极接地，所述第四N型晶体管的漏极作为所述驱动电路的输出端。
  13. 如权利要求12所述的电压转换电路，其中，所述第三N型晶体管的栅极接收第一控制信号，所述第四N型晶体管的栅极接收第二控制信号，所述第一控制信号与所述第二控制信号的相位相反。
  14. 如权利要求13所述的电压转换电路，其中，所述第三N型晶体管的尺寸与所述第四N型晶体管的尺寸相同。
  15. 一种存储器，包括如权利要求1～14任一项所述的电压转换电路。
PCT/CN2022/092546 2021-07-16 2022-05-12 电压转换电路与存储器 WO2023284395A1 (zh)

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US20030076149A1 (en) * 2001-10-03 2003-04-24 Nec Corporation Sampling level converter circuit, 2-phase and multiphase expanding circuit, and display device
CN103532526A (zh) * 2013-10-22 2014-01-22 北京兆易创新科技股份有限公司 电压转换电路及电压转换方法
CN108649939A (zh) * 2018-04-16 2018-10-12 芯原微电子(上海)有限公司 电源检测电路及方法
CN111342834A (zh) * 2020-05-07 2020-06-26 深圳青铜剑技术有限公司 电平转换电路
CN112671391A (zh) * 2020-12-21 2021-04-16 海光信息技术股份有限公司 一种电平转换电路

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030076149A1 (en) * 2001-10-03 2003-04-24 Nec Corporation Sampling level converter circuit, 2-phase and multiphase expanding circuit, and display device
CN103532526A (zh) * 2013-10-22 2014-01-22 北京兆易创新科技股份有限公司 电压转换电路及电压转换方法
CN108649939A (zh) * 2018-04-16 2018-10-12 芯原微电子(上海)有限公司 电源检测电路及方法
CN111342834A (zh) * 2020-05-07 2020-06-26 深圳青铜剑技术有限公司 电平转换电路
CN112671391A (zh) * 2020-12-21 2021-04-16 海光信息技术股份有限公司 一种电平转换电路

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