WO2023283972A1 - 一种半导体结构及其形成方法 - Google Patents

一种半导体结构及其形成方法 Download PDF

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WO2023283972A1
WO2023283972A1 PCT/CN2021/107199 CN2021107199W WO2023283972A1 WO 2023283972 A1 WO2023283972 A1 WO 2023283972A1 CN 2021107199 W CN2021107199 W CN 2021107199W WO 2023283972 A1 WO2023283972 A1 WO 2023283972A1
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layer
substrate
conductive
forming
semiconductor structure
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PCT/CN2021/107199
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English (en)
French (fr)
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高远皓
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长鑫存储技术有限公司
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Priority to US17/479,146 priority Critical patent/US12125749B2/en
Publication of WO2023283972A1 publication Critical patent/WO2023283972A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers

Definitions

  • the present application relates to, but is not limited to, a semiconductor structure and a method for forming the same.
  • TSV Through Silicon Via
  • the TSV structure has a large aspect ratio, a problem in any one of the etching process, the filling process and the alignment process will lead to the failure of the TSV structure.
  • an embodiment of the present application provides a method for forming a semiconductor structure, the method comprising:
  • the device layer including a memory array and a contact structure
  • the second conductive column is electrically connected to the first conductive column through the conductive layer.
  • an embodiment of the present application provides a semiconductor structure, including: a substrate; a device layer, the device layer being located on the front side of the substrate;
  • the through-silicon vias are disposed inside the substrate and penetrate through the substrate and the device layer.
  • a trench is first formed on the back of the first substrate, a first conductive pillar is formed in the trench, and a second conductive column is formed on the front of the first substrate after the device layer is formed. column, and the first conductive column and the second conductive column are electrically connected through the conductive layer in the trench to form a through-silicon via structure.
  • FIG. 1 is a schematic flow diagram of a method for forming a TSV structure provided in an embodiment of the present application
  • FIGS. 2a to 2n are partial cross-sectional schematic diagrams of the formation process of the TSV structure according to an embodiment of the present application.
  • FIG. 3 is a schematic cross-sectional view of a semiconductor structure provided by an embodiment of the present application.
  • spatially relative terms such as “below”, “under”, “under”, “under”, “on”, “above”, etc. are used herein Descriptive convenience may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “beneath” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • FIG. 1 is a schematic flow diagram of a method for forming a semiconductor structure provided in the embodiment of the present application. As shown in FIG. 1 , the method mainly includes the following steps:
  • Step 110 providing a first substrate.
  • Step 120 etching the back surface of the first substrate to form a trench; forming a conductive layer in the trench.
  • a first substrate is provided, wherein the first substrate may be a semiconductor substrate, and the semiconductor substrate may be a single semiconductor material substrate (such as a silicon (Si) substrate, germanium (Ge ) substrates, etc.), compound semiconductor material substrates (such as silicon germanium (SiGe) substrates, etc.), or silicon-on-insulator (SOI) substrates, germanium-on-insulator (GeOI) substrates, etc.
  • semiconductor material substrate such as a silicon (Si) substrate, germanium (Ge ) substrates, etc.
  • compound semiconductor material substrates such as silicon germanium (SiGe) substrates, etc.
  • SOI silicon-on-insulator
  • GeOI germanium-on-insulator
  • CMP chemical mechanical polishing
  • a first insulating layer, a first diffusion barrier layer, and a copper thin film layer are sequentially deposited in the trench; the copper thin film layer at the bottom of the trench constitutes the conductive layer; Depositing a second diffusion barrier layer in the groove, the second diffusion barrier layer covers the copper film layer; filling the trench with an insulating material to form an insulating filling layer, the insulating filling layer covers the second diffusion barrier layer .
  • FIG. 2a to 2n are partial cross-sectional schematic views of the formation process of the semiconductor structure according to an embodiment of the present application.
  • a method for forming a semiconductor structure according to an embodiment of the present application will be described below with reference to FIG. 1 and FIG. 2a to FIG. 2n.
  • a photoresist layer 202 is formed on the back of the first substrate 201, and the photoresist layer 202 is exposed and developed to obtain a patterned photoresist layer 202.
  • the patterned photoresist layer 202 has a first opening 203 .
  • the first opening may be a circular opening with a diameter of 10-30um. It should be noted that the first opening may also be openings of other shapes, such as oval openings, square openings, etc., which are not limited in this application.
  • the first substrate 201 is etched using the patterned photoresist layer 202 as a mask to form a trench 204 .
  • the photoresist layer 202 is removed, and the formed structure is shown in FIG. 2b.
  • the formed structure may also be cleaned to remove etching residues.
  • etching the first substrate may be performed by using a dry etching process.
  • the etching depth of the trench 204 may be 30-50 um. In actual application, the etching depth of the trench can be adjusted according to actual requirements.
  • the depth of the groove is equal to half of the thickness of the first substrate.
  • a first insulating layer 205 , a first diffusion barrier layer 206 and a copper thin film layer 207 are sequentially deposited in the trench.
  • the copper thin film layer at the bottom of the trench constitutes the conductive layer 2071 .
  • the thickness of the conductive layer 2071 may be 700nm-1000nm. In actual application, the thickness of the conductive layer can be adjusted according to actual needs.
  • an atomic layer deposition (Atomic Layer Deposition, ALD) process may be used to form the first insulating layer 205 in the trench, and the material of the first insulating layer 205 includes but not limited to SiO 2 , Si 3 N 4 , at least one of low dielectric constant materials; a first diffusion barrier layer 206 is formed on the first insulating layer 205 using a physical vapor deposition (Physical Vapor Deposition, PVD) process, and the material of the first diffusion barrier layer 206 includes But not limited to at least one of TaN, Ta, ZrN, Cu; the copper thin film layer 207 is formed on the first diffusion barrier layer 206 by using an electroplating process.
  • ALD atomic layer deposition
  • the deposition rate can be controlled by adding accelerators and inhibitors in the electroplating process, so that the copper thin film layer 207 is formed on the bottom and top of the trench, and on the sides of the trench. Only a small thin film layer of copper is deposited on the walls.
  • the accelerator can be polyalkylene glycol
  • the inhibitor can be organic sulfide.
  • the copper film layer deposited on the sidewall of the trench may also be removed by dry etching, leaving only the copper film layer at the bottom and top of the trench.
  • a second diffusion barrier layer 208 is deposited in the trench, and an insulating material is filled in the trench to form an insulating filling layer 209, and the formed structure is shown in FIG. 2d.
  • the ALD process is used to deposit the second diffusion barrier layer, and the material of the second diffusion barrier layer includes but not limited to at least one of SiN, TaN, and Tia.
  • a chemical vapor deposition (Chemical Vapor Deposition, CVD) process is used to form an insulating filling layer in the trench, and the material of the insulating filling layer includes but is not limited to at least one of SiO 2 , Si 3 N 4 , and low dielectric constant materials. .
  • the trench structure includes: a first insulating layer 205, a first diffusion barrier layer 206, a copper film layer 207, a second diffusion barrier layer 208, and an insulating filling layer 209; wherein, the copper film layer at the bottom of the trench constitutes The conductive layer 2071.
  • the materials of the first insulating layer 205 and the insulating filling layer 209 may be the same.
  • Step 130 forming a first conductive pillar extending into the trench on the back surface of the first substrate.
  • a patterned first photomask layer 210 having second openings 211 is formed.
  • the second opening may be a circular opening with a diameter of 7um-10um. It should be noted that the second opening may also be openings of other shapes, such as oval openings, square openings, etc., which are not limited in the present application.
  • the insulating filling layer 209 and the second diffusion barrier layer 208 are etched using the patterned first photomask layer 210 containing the second opening as a mask to form a first blind hole 212 .
  • the patterned first photomask layer 210 is removed, and the formed structure is shown in FIG. 2f.
  • the first blind hole 212 exposes part of the conductive layer 2071 .
  • the conductive layer 2071 can be used as an etching stop layer, and by controlling the etching selectivity, the etching of the first blind hole is stopped on the copper film layer 207, so that the first blind hole The hole penetrates through the insulating filling layer 209 and the second diffusion barrier layer 208 , exposing part of the conductive layer 2071 .
  • a third diffusion barrier layer 213 is deposited in the first blind hole 212 , and the third diffusion barrier layer 213 covers the sidewall of the first blind hole 212 and the exposed part of the conductive layer 2071 .
  • the first metal material 214 is filled in the first blind hole, and the first metal material 214 covers the third diffusion barrier layer 213 .
  • a PVD process is used to deposit a third diffusion barrier layer 213 in the first blind hole, and the material of the third diffusion barrier layer includes but not limited to at least one of TaN, Ta, ZrN, and Cu;
  • the electroplating process fills the first blind hole with the first metal material 214 , and the first metal material includes but not limited to at least one of copper and tungsten.
  • the materials of the third diffusion barrier layer 213 and the first diffusion barrier layer 206 may be the same.
  • the materials of the first metal material 214 and the copper thin film layer 207 may be the same.
  • a chemical mechanical polishing process is performed on the back surface of the first substrate, so that the top surface of the first conductive pillar is flush with the top surface of the substrate, and the formed structure is shown in FIG. 2h.
  • the first substrate can also be thinned from the back side of the first substrate through the above-mentioned chemical mechanical grinding process, and the thickness of the first substrate can be ground to 40-60 um. In practical applications, the thinned thickness of the first substrate can be adjusted according to actual needs.
  • the first conductive column 215 extending into the first substrate 201 is formed on the back side of the first substrate 201, and the first conductive column 215 is formed in the trench structure, And electrically connected with the conductive layer 2071 at the bottom of the trench.
  • the third diffusion barrier layer 213 in the first conductive column 215 is in contact with the conductive layer 2071 through the opening of the second diffusion barrier layer 208 at the bottom of the trench, so that the filled in the first conductive column 215
  • the first metal material 214 is electrically connected to the conductive layer 2071 through the third diffusion barrier layer 213 .
  • Step 140 forming a device layer on the front surface of the first substrate, the device layer including a memory array and a contact structure.
  • the structure shown in FIG. 2h is turned over so that the front side of the first substrate 201 faces upward.
  • a device layer 216 is formed on the front surface of the first substrate 201 , and the device layer 216 includes a memory array 217 and a contact structure 218 .
  • the memory array 217 may include structures such as active regions, word lines, bit lines, and capacitors.
  • the contact structure 218 may include a conductive contact structure and a metal layer formed on the memory array 217, and the contact structure 218 is used to electrically lead out the memory array.
  • the contact structure 218 may be used to control signal transmission of one or more sources and/or drains of the active region, as well as word lines, bit lines, and the like.
  • the contact structure 218 is formed in the insulating layer.
  • the contact structure 218 may include a peripheral contact structure formed on the memory array 217 , a metal layer electrically connected to the peripheral contact structure, and a conductive contact structure electrically connected to the metal layer.
  • the metal layer is located between the peripheral contact structure and the conductive contact structure.
  • Step 150 forming a second conductive pillar penetrating through the device layer and extending into the first substrate; the second conductive pillar is electrically connected to the first conductive pillar through the conductive layer.
  • a patterned second photomask layer 219 is formed, and the patterned second photomask layer 219 has a third opening 220 .
  • the third opening may be a circular opening with a diameter of 7um. It should be noted that, the third opening can also be an opening of other shapes, such as an oval opening, a square opening, etc., which is not limited in the present application.
  • the device layer 216 and the first substrate 201 are etched using the patterned second photomask layer 219 containing the third opening as a mask to form a second blind hole 221
  • the patterned second photomask layer 219 is removed, and the second blind hole 221 exposes part of the conductive layer 2071 .
  • the conductive layer 2071 is used as an etching stop layer, and the second blind hole 221 is formed by etching, and the second blind hole penetrates through the device layer 216, the first insulating layer 205 and the first insulating layer 205 by controlling the etching selectivity. Diffusion barrier layer 206, and part of the conductive layer 2071 is exposed.
  • the opening size of the first blind hole is the same as or different from the opening size of the second blind hole, and the opening size of the first blind hole and the opening size of the second blind hole are smaller than the conductive layer.
  • the width of 2071 (along the horizontal direction of the first substrate) is sufficient.
  • the ALD process is used to deposit the second insulating layer in the trench, and the material of the second insulating layer includes but not limited to at least one of SiO 2 , Si 3 N 4 , and low dielectric constant materials;
  • a fourth diffusion barrier layer is deposited on the insulating layer, and the material of the fourth diffusion barrier layer includes but not limited to at least one of TaN, Ta, ZrN, and Cu;
  • an electroplating process is used to fill the second metal material in the first blind hole, and the second
  • the two-metal material includes but not limited to at least one of copper and tungsten.
  • the materials of the second insulating layer 222 and the first insulating layer 205 may be the same.
  • the material of the fourth diffusion barrier layer 223 and the third diffusion barrier layer 213 may be the same.
  • the second metal material 224 and the first metal material 214 may be the same.
  • the fourth diffusion barrier layer 223 in the second conductive pillar 225 is in contact with the conductive layer 2071 through the opening of the second insulating layer 222 at the bottom of the second blind hole, so that the second conductive pillar 225 is filled with
  • the second metal material 224 is electrically connected to the conductive layer 2071 through the fourth diffusion barrier layer 223 .
  • the second conductive pillar 225 and the first conductive pillar 215 are electrically connected through the conductive layer 2071 at the bottom of the trench.
  • the chemical mechanical polishing process is performed on the structure shown in FIG. 2m to planarize the second conductive pillars from the front surface of the first substrate 201, so that the top surface of the second conductive pillars 225 is in contact with the device layer
  • the top surface of 216 is flush, and the formed TSV structure is shown in FIG. 2n.
  • the TSV structure includes a first conductive pillar 215 , a second conductive pillar 225 and a conductive layer 2071 electrically connected, and the TSV structure is in a "cross shape".
  • the widths of the first conductive pillars 215 and the second conductive pillars 225 decrease in a vertical direction and toward the conductive layer 2071 .
  • the first conductive column 215 is formed in the trench structure, and the first conductive column 215 and the second conductive column 225 are electrically connected through the conductive layer 2071.
  • the width of the layer 2071 is greater than the width of the contact surface of the first conductive pillar 215 and the second conductive pillar 225 with the conductive layer 2071, so that when the second conductive pillar 225 is formed on the front surface of the first substrate, it only needs to be in contact with the conductive layer 2071.
  • the projections of the first conductive pillar 215 and the second conductive pillar 225 on the conductive layer 2071 may not completely overlap.
  • the process window of the second conductive column is increased, the difficulty of aligning the first conductive column and the second conductive column is reduced, the contact area between the first conductive column and the second conductive column is increased, and the TSV is reduced. resistance, which improves the conductivity of TSVs.
  • the method further includes: forming an interconnection layer on the device layer, and the interconnection layer is electrically connected to the second conductive pillar; wherein, the interconnection layer Includes interconnect vias and interconnect metal layers.
  • the interconnection layer Includes interconnect vias and interconnect metal layers.
  • multiple stacked interconnection layers can be formed on the device layer. According to the stacking sequence of the interconnection layers, the interconnection layer closest to the device layer can be called the first interconnection layer, and the first interconnection layer can be called the first interconnection layer.
  • the interconnect layer above the tie layer is called the second interconnect layer, and so on.
  • the method further includes: providing a bonding structure, the bonding structure including a second substrate and an interconnection layer formed on the second substrate; wherein, The interconnection layer includes an interconnection via hole and an interconnection metal layer; the interconnection layer is bonded to the device layer.
  • the interconnection layer is electrically connected to the second conductive pillar.
  • multiple stacked interconnection layers may be formed on the second substrate.
  • the uppermost interconnection layer is bonded to the device layer. According to the stacking order of the interconnection layers, the interconnection layer closest to the device layer can be called the first interconnection layer, and the first interconnection layer can be called the first interconnection layer.
  • the interconnect layer above the tie layer is called the second interconnect layer, and so on.
  • the interconnection vias in the interconnection layer are electrically connected to the second conductive pillars.
  • the device layer and the interconnection layer are formed on different substrates. In this way, the manufacturing process of the device layer and the interconnection layer can be performed simultaneously, thereby effectively shortening the manufacturing time of the memory chip.
  • the embodiment of the present application also provides a semiconductor structure, the semiconductor structure includes: a substrate; a device layer, the device layer is located on the front side of the substrate; through silicon vias, the through silicon vias are arranged on the substrate bottom inside and through the substrate and the device layer.
  • FIG. 3 shows a semiconductor structure provided by an embodiment of the present application; as shown in FIG. 3 , the semiconductor structure includes: a substrate 310; a device layer 320, and the device layer 320 is located on the front side of the semiconductor substrate 310;
  • the through-silicon vias are disposed inside the substrate and pass through the substrate 310 and the device layer 320 .
  • the device layer 320 includes a memory array 321 and a contact structure 322 .
  • the TSV includes: a first conductive pillar 331, the first conductive pillar 331 extends from the back of the substrate toward the inside of the substrate; a second conductive pillar 331, the second conductive pillar 331 runs through the device layer 320 and extends from the front of the substrate to the interior of the substrate; a conductive layer 3333 , through which the first conductive pillar 331 and the second conductive pillar 332 are electrically connected.
  • the TSV further includes a trench structure 333 , and the trench structure 333 extends from the back surface of the substrate toward the inside of the substrate and does not penetrate the substrate 310 .
  • the trench structure includes: a first insulating layer 3331, a first diffusion barrier layer 3332, a copper film layer, a second diffusion barrier layer 3334, and an insulating filling layer 3335;
  • the copper film layer at the bottom of 333 constitutes the conductive layer 3333 .
  • the copper thin film layer when forming the copper thin film layer, the copper thin film layer may only be formed on the bottom of the trench, and not formed on the sidewall of the trench. At this time, the copper film layer in the groove is the conductive layer.
  • the first conductive pillar 331 penetrates through the insulating filling layer 3335 and the second diffusion barrier layer 3334 , and is electrically connected to the conductive layer 3333 .
  • the second conductive pillar 332 penetrates through the first insulating medium layer 3331 and the first diffusion barrier layer 3332 , and is electrically connected to the conductive layer 3333 .
  • the first conductive column is formed in the trench structure, and the first conductive column and the second conductive column are electrically connected through the conductive layer in the trench structure.
  • the width is greater than the width of the contact surface between the first conductive pillar and the second conductive pillar and the conductive layer, so that when the second conductive pillar is formed on the front surface of the first substrate, it only needs to be aligned with the conductive layer.
  • the first conductive pillar It may not completely overlap with the projection of the second conductive pillar on the conductive layer.
  • the process window of the second conductive column is increased, the difficulty of aligning the first conductive column and the second conductive column is reduced, the contact area between the first conductive column and the second conductive column is increased, and the TSV is reduced. resistance, which improves the conductivity of TSVs.

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Abstract

本申请实施例公开了一种半导体结构及其形成方法，所述半导体结构的形成方法包括：提供第一衬底；在所述第一衬底的背面刻蚀形成沟槽；在所述沟槽内形成导电层；在所述第一衬底的背面形成延伸进入所述沟槽内的第一导电柱；在所述第一衬底的正面形成器件层，所述器件层包括存储阵列及接触结构；形成贯穿所述器件层并延伸进入所述第一衬底内的第二导电柱；所述第二导电柱和第一导电柱通过所述导电层电连接。

Description

一种半导体结构及其形成方法
相关申请的交叉引用
本申请基于申请号为202110790535.3、申请日为2021年07月13日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及但不限于一种半导体结构及其形成方法。
背景技术
随着半导体技术的发展，集成电路的特征尺寸不断缩小，器件互连密度不断提高。为了实现器件的高密度化，获得更优越的性能和更低的总体成本，技术人员研究出一系列先进的封装技术。其中三维封装技术具有良好的电学性能以及较高的可靠性，同时能实现较高的封装密度，被广泛应用于各种高速电路以及小型化系统中。硅通孔(Through Silicon Via，TSV)技术是三维集成电路中堆叠芯片实现互连的一种新技术，通过在硅圆片上制作出许多垂直互连TSV结构来实现不同芯片之间的电互连。TSV技术能够使芯片在三维方向堆叠的密度最大、芯片之间的互连线最短、外形尺寸最小，并且大大改善芯片速度和低功耗的性能，是目前电子封装技术中最引人注目的一种技术。
然而由于TSV结构具有较大的深宽比，其刻蚀工艺、填充工艺和对准工艺任何之一出现问题均会导致该TSV结构失效。
发明内容
第一方面，本申请实施例提供一种半导体结构的形成方法，所述方法 包括：
提供第一衬底；
在所述第一衬底的背面刻蚀形成沟槽；
在所述沟槽内形成导电层；
在所述第一衬底的背面形成延伸进入所述沟槽内的第一导电柱；
在所述第一衬底的正面形成器件层，所述器件层包括存储阵列及接触结构；
形成贯穿所述器件层并延伸进入所述第一衬底内的第二导电柱；
所述第二导电柱和第一导电柱通过所述导电层电连接。
第二方面，本申请实施例提供一种半导体结构，包括：衬底；器件层，所述器件层位于所述衬底的正面；
硅通孔，所述硅通孔设置在所述衬底内部且贯穿所述衬底及所述器件层。
在本申请所提供的技术方案中，先在第一衬底的背面形成沟槽，在沟槽内形成第一导电柱，再在形成器件层后，在第一衬底的正面形成第二导电柱，且第一导电柱和第二导电柱通过沟槽内的导电层电连接，以构成硅通孔结构。由此增加了工艺窗口，降低了第一导电柱和第二导电柱的刻蚀难度和对准难度。
附图说明
在附图中，除非另外规定，否则贯穿多个附图相同的附图标记表示相同或相似的部件或元素。这些附图不一定是按照比例绘制的。应该理解，这些附图仅描绘了根据本申请公开的一些实施方式，而不应将其视为是对本申请范围的限制。
图1为本申请实施例提供的一种TSV结构的形成方法的实现流程示意图；
图2a至图2n为本申请一实施例的TSV结构的形成过程的局部剖面示意图；
图3为本申请实施例提供的一种半导体结构的剖面示意图。
具体实施方式
下面将参照附图更详细地描述本申请公开的示例性实施方式。虽然附图中显示了本申请的示例性实施方式，然而应当理解，可以以各种形式实现本申请，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本申请，并且能够将本申请公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本申请更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本申请可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本申请发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
此外，附图仅为本申请的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
附图中所示的流程图仅是示例性说明，不是必须包括所有的步骤。例如，有的步骤还可以分解，而有的步骤可以合并或部分合并，因此实际执行的顺序有可能根据实际情况改变。
应当明白，空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而 被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
本申请实施例提供一种半导体结构的形成方法，图1为本申请实施例提供的一种半导体结构的形成方法的实现流程示意图，如图1所示，所述方法主要包括以下步骤：
步骤110、提供第一衬底。
步骤120、在所述第一衬底的背面刻蚀形成沟槽；在所述沟槽内形成导电层。
在本申请实施例中，提供第一衬底，其中，第一衬底可以为半导体衬底，所述半导体衬底可以为单质半导体材料衬底(例如为硅(Si)衬底、锗(Ge)衬底等)、复合半导体材料衬底(例如为锗硅(SiGe)衬底等)，或绝缘体上硅(SOI)衬底、绝缘体上锗(GeOI)衬底等。
在本申请实施例中，在步骤120之前，还可以对第一衬底的背面进行化学机械抛光CMP处理，以对第一衬底进行减薄处理，例如，将第一衬底 的厚度研磨至50-70um。在实际应用时，可以根据实际需求而调整第一衬底的减薄厚度。
在本申请实施例中，在所述沟槽内依次沉积第一绝缘层、第一扩散阻挡层、铜薄膜层；位于所述沟槽底部的铜薄膜层构成所述导电层；在所述沟槽内沉积第二扩散阻挡层，所述第二扩散阻挡层覆盖所述铜薄膜层；在所述沟槽内填充绝缘材料形成绝缘填充层，所述绝缘填充层覆盖所述第二扩散阻挡层。
图2a至图2n为本申请一实施例的半导体结构的形成过程的局部剖面示意图。下面结合图1和图2a至图2n描述本申请实施例的半导体结构的形成方法。
在本申请实施例中，如图2a所示，在第一衬底201的背面形成光刻胶层202，对所述光刻胶层202进行曝光显影，得到图案化后的光刻胶层202，该图案化后的光刻胶层202具有第一开口203。在一具体实施例中，第一开口可以为圆形开口，该圆形开口的直径为10-30um。需要说明的是，第一开口还可以为其他形状的开口，例如椭圆形开口，方形开口等，本申请对此不做限制。
以图案化后的光刻胶层202为掩膜对所述第一衬底201进行刻蚀，以形成沟槽204。形成沟槽204后，去除光刻胶层202，形成的结构如图2b所示。在一些实施例中，在去除图案化的光刻胶层202后，还可以对形成的结构进行清洗，以去除刻蚀残留。在实际应用时，对所述第一衬底进行刻蚀，可以采用干法刻蚀工艺进行。在一具体实施例中，沟槽204的刻蚀深度可以为30-50um。在实际应用时，可以根据实际需求而调整沟槽的刻蚀深度。
在本申请实施例中，所述沟槽的深度等于所述第一衬底厚度的一半。
在所述沟槽内依次沉积第一绝缘层205、第一扩散阻挡层206和铜薄膜层207。位于所述沟槽底部的铜薄膜层构成所述导电层2071。在一具体实 施例中，导电层2071的厚度可以为700nm-1000nm。在实际应用时，可以根据实际需求而调整导电层的厚度。
在一实施例中，可以采用原子层沉积(Atomic Layer Deposition，ALD)工艺在沟槽内形成第一绝缘层205，所述第一绝缘层205的材料包括但不限于SiO 2、Si 3N 4、低介电常数材料中的至少一种；采用物理气相沉积(Physical Vapor Deposition，PVD)工艺在第一绝缘层205上形成第一扩散阻挡层206，所述第一扩散阻挡层206的材料包括但不限于TaN、Ta、ZrN、Cu中的至少一种；采用电镀工艺在第一扩散阻挡层206上方形成铜薄膜层207。
在一些实施例中，在形成铜薄膜层207时，可以通过在电镀工艺中添加加速剂和抑制剂控制沉积速率，使得铜薄膜层207形成在沟槽的底部和顶部，而在沟槽的侧壁仅沉积有少量的铜薄膜层。在一具体示例中，加速剂可以为聚亚烷基二醇，抑制剂可以为有机硫化物。在一些实施例中，也可以通过干法刻蚀去除沟槽侧壁沉积的铜薄膜层，仅保留沟槽底部和顶部的铜薄膜层。
在进行上述沉积后，形成的结构如图2c所示。
在所述沟槽内沉积第二扩散阻挡层208，并在所述沟槽内填充绝缘材料形成绝缘填充层209，形成的结构如图2d所示。在一些实施例中，采用ALD工艺沉积第二扩散阻挡层，所述第二扩散阻挡层的材料包括但不限于SiN、TaN、Tia中的至少一种。采用化学气相沉积(Chemical Vapor Deposition，CVD)工艺在沟槽内形成绝缘填充层，所述绝缘填充层的材料包括但不限于SiO 2、Si 3N 4、低介电常数材料中的至少一种。
这里，沟槽结构包括：第一绝缘层205、第一扩散阻挡层206、铜薄膜层207、第二扩散阻挡层208和绝缘填充层209；其中，位于所述沟槽底部的铜薄膜层构成所述导电层2071。
这里，第一绝缘层205和绝缘填充层209的材料可以相同。
步骤130、在所述第一衬底的背面形成延伸进入所述沟槽内的第一导电 柱。
如图2e所示，形成图案化的第一光掩模层210，该图案化的第一光掩模层210具有第二开口211。在一具体实施例中，第二开口可以为圆形开口，该圆形开口的直径为7um-10um。需要说明的是，第二开口还可以为其他形状的开口，例如椭圆形开口，方形开口等，本申请对此不做限制。
以含有第二开口的图案化的第一光掩模层210为掩膜对所述绝缘填充层209和所述第二扩散阻挡层208进行刻蚀，以形成第一盲孔212。形成第一盲孔212后，去除图案化的第一光掩模层210，形成的结构如图2f所示。这里，所述第一盲孔212暴露部分导电层2071。在刻蚀形成第一盲孔212时，可以将导电层2071作为刻蚀停止层，通过控制刻蚀选择比，从而使得第一盲孔的刻蚀停止在铜薄膜层207上，使得第一盲孔贯穿所述绝缘填充层209和所述第二扩散阻挡层208，暴露部分导电层2071。
如图2g所示，在所述第一盲孔212内沉积第三扩散阻挡层213，所述第三扩散阻挡层213覆盖第一盲孔212的侧壁及暴露的部分导电层2071。在所述第一盲孔内填充第一金属材料214，第一金属材料214覆盖第三扩散阻挡层213。在一些实施例中，采用PVD工艺在第一盲孔内沉积第三扩散阻挡层213，所述第三扩散阻挡层的材料包括但不限于TaN、Ta、ZrN、Cu中的至少一种；采用电镀工艺在第一盲孔内填充第一金属材料214，第一金属材料包括但不限于铜、钨中的至少一种。
这里，第三扩散阻挡层213和第一扩散阻挡层206的材料可以相同。第一金属材料214和铜薄膜层207的材料可以相同。
如图2g所示，对第一衬底的背面进行化学机械研磨工艺，以使所述第一导电柱顶表面与所述衬底顶表面齐平，形成的结构如图2h所示。这里，还可以通过上述化学机械研磨工艺从第一衬底的背面对第一衬底进行减薄，可以将第一衬底的厚度研磨至40-60um。在实际应用时，可以根据实际需求而调整第一衬底的减薄厚度。
结合图2a至图2h，即在所述第一衬底201的背面形成了延伸进入所述第一衬底201内的第一导电柱215，该第一导电柱215形成于沟槽结构内，并与沟槽底部的导电层2071电连接。
如图2h所示，第一导电柱215中的第三扩散阻挡层213通过第二扩散阻挡层208在沟槽底部的开口与导电层2071接触，从而使所述第一导电柱215中填充的第一金属材料214通过第三扩散阻挡层213与导电层2071电连接。
步骤140、在所述第一衬底的正面形成器件层，所述器件层包括存储阵列及接触结构。
如图2i所示，将图2h所示的结构进行翻转，以使所述第一衬底201的正面朝上。
如图2j所示，在第一衬底201的正面形成器件层216，器件层216包括存储阵列217及接触结构218。存储阵列217可以包括有源区、字线、位线及电容等结构。接触结构218可以包括形成在所述存储阵列217上的导电接触结构和金属层，该接触结构218用于将存储阵列电引出。例如，接触结构218可用于控制有源区一个或多个源极和/或漏极及字线、位线等结构的信号传输。本实施例中接触结构218形成于绝缘层中。
在一具体示例中，所述接触结构218可以包括形成在所述存储阵列217上外围接触结构、与外围接触结构电连接的金属层和与金属层电连接的导电接触结构。其中，金属层位于外围接触结构和导电接触结构之间。
步骤150、形成贯穿所述器件层并延伸进入所述第一衬底内的第二导电柱；所述第二导电柱和第一导电柱通过所述导电层电连接。
在本申请实施例中，如图2k所示，形成图案化的第二光掩模层219，该图案化的第第二光掩膜层219具有第三开口220。在一具体实施例中，第三开口可以为圆形开口，该圆形开口的直径为7um。需要说明的是，第三开口还可以为其他形状的开口，例如椭圆形开口，方形开口等，本申请对 此不做限制。
如图2l所示，以含有第三开口的图案化的第二光掩膜层219为掩膜对所述器件层216和所述第一衬底201进行刻蚀，以形成第二盲孔221，形成第二盲孔221后，去除图案化的第二光掩膜层219，所述第二盲孔221暴露部分所述导电层2071。将导电层2071作为刻蚀停止层，刻蚀形成第二盲孔221，通过控制刻蚀选择比，使得第二盲孔贯穿所述器件层216、所述第一绝缘层205和所述第一扩散阻挡层206，并暴露部分所述导电层2071。
在一些实施例中，所述第一盲孔的开口尺寸与所述第二盲孔的开口尺寸相同或不同，满足第一盲孔的开口尺寸和第二盲孔的开口尺寸小于所述导电层2071的宽度(沿第一衬底的水平方向)即可。
如图2m所示，在第二盲孔221内沉积第二绝缘层222，并刻蚀去除第二盲孔底部的第二绝缘层222；在所述第二盲孔内沉积第四扩散阻挡层223并填充第二金属材料224，以形成第二导电柱225。这里，采用ALD工艺在沟槽内沉积第二绝缘层，第二绝缘层的材料包括但不限于SiO 2、Si 3N 4、低介电常数材料中的至少一种；采用PVD工艺在第二绝缘层上沉积第四扩散阻挡层，第四扩散阻挡层的材料包括但不限于TaN、Ta、ZrN、Cu中的至少一种；采用电镀工艺在第一盲孔内填充第二金属材料，第二金属材料包括但不限于铜、钨中的至少一种。
这里，第二绝缘层222和第一绝缘层205的材料可以相同。第四扩散阻挡层223和第三扩散阻挡层213的材料可以相同。第二金属材料224和第一金属材料214可以相同。
在本申请实施例中，第二导电柱225中的第四扩散阻挡层223通过第二绝缘层222在第二盲孔底部的开口与导电层2071接触，从而所述第二导电柱225中填充的第二金属材料224通过第四扩散阻挡层223与导电层2071电连接。
在本申请实施例中，所述第二导电柱225和第一导电柱215通过所述 沟槽底部的导电层2071进行电连接。
对图2m所示的结构进行化学机械研磨工艺，以从所述第一衬底201的正面对所述第二导电柱进行平坦化，以使第二导电柱225的顶表面与所述器件层216的顶表面齐平，形成的硅通孔结构如图2n所示。
如图2n所示，该硅通孔结构包括电连接的第一导电柱215、第二导电柱225和导电层2071，该硅通孔结构呈“十字形”。第一导电柱215和第二导电柱225的宽度在垂直且朝向导电层2071的方向递减。
由此，本申请实施例中在沟槽结构中形成第一导电柱215，第一导电柱215和第二导电柱225通过导电层2071进行电连接，在平行于衬底的方向上，由于导电层2071的宽度大于第一导电柱215和第二导电柱225与导电层2071的接触面的宽度，从而使得在第一衬底正面形成第二导电柱225时，只需与导电层2071接触即可，换言之，第一导电柱215和第二导电柱225在导电层2071上的投影可以不完全重叠。如此，增加了第二导电柱的工艺窗口，降低了第一导电柱和第二导电柱的对准难度，增加了第一导电柱和第二导电柱的接触面积，进而降低了硅通孔的电阻，提高了硅通孔的导电性能。
在一些实施例中，在步骤140之后，所述方法还包括：在所述器件层上形成互连层，所述互连层与所述第二导电柱电连接；其中，所述互连层包括互连通孔和互连金属层。在实际应用时，可以在器件层上形成多个层叠的互连层，根据互连层的层叠排列顺序，可以将最接近器件层的互连层称为第一互连层，将第一互连层上方的互连层称为第二互连层，依次类推。
在另一些实施例中，在步骤140之后，所述方法还包括：提供键合结构，所述键合结构包括第二衬底和形成在所述第二衬底上的互连层；其中，所述互连层包括互连通孔和互连金属层；将所述互连层与所述器件层进行键合。这里，所述互连层与所述第二导电柱电连接。在实际应用时，可以在第二衬底上形成多个层叠的互连层。在键合时，将最上层的互连层与器 件层进行键合，根据互连层的层叠排列顺序，可以将最接近器件层的互连层称为第一互连层，将第一互连层上方的互连层称为第二互连层，依次类推。
在本申请实施例中，所述互连层中的互连通孔与所述第二导电柱电连接。
本申请实施例中将器件层和互连层放在不同的衬底上形成，如此，能够同步进行器件层和互连层的制程，从而有效地缩短存储芯片的制造时间。
本申请实施例中还提供一种半导体结构，所述半导体结构包括：衬底；器件层，所述器件层位于所述衬底的正面；硅通孔，所述硅通孔设置在所述衬底内部且贯穿所述衬底及所述器件层。图3示出了本申请实施例提供的半导体结构；如图3所示，所述半导体结构包括：衬底310；器件层320，所述器件层320位于所述半导体衬底310的正面；
硅通孔，所述硅通孔设置在所述衬底内部且贯穿所述衬底310及所述器件层320。
本申请实施例中，所述器件层320包括存储阵列321及接触结构322。
本申请实施例中，所述硅通孔包括：第一导电柱331，所述第一导电柱331从所述衬底背面向衬底内部延伸；第二导电柱331，所述第二导电柱331贯穿所述器件层320，并从所述衬底正面向衬底内部延伸；导电层3333，所述第一导电柱331和所述第二导电柱332通过所述导电层3333电连接。
本申请实施例中，所述硅通孔还包括沟槽结构333，所述沟槽结构333从所述衬底背面向衬底内部延伸，且未贯穿所述衬底310。
本申请实施例中，所述沟槽结构包括：第一绝缘层3331、第一扩散阻挡层3332、铜薄膜层、第二扩散阻挡层3334和绝缘填充层3335；其中，位于所述沟槽结构333底部的铜薄膜层构成所述导电层3333。
需要说明的是，在形成铜薄膜层时，可以仅在沟槽的底部形成铜薄膜层，而不在沟槽的侧壁形成铜薄膜层。此时，沟槽内的铜薄膜层即为导电 层。
本申请实施例中，所述第一导电柱331贯穿所述绝缘填充层3335和所述第二扩散阻挡层3334，并与所述导电层3333电连接。
本申请实施例中，所述第二导电柱332贯穿所述第一绝缘介质层3331和所述第一扩散阻挡层3332，并与所述导电层3333电连接。
本申请实施例中在沟槽结构中形成第一导电柱，第一导电柱和第二导电柱通过沟槽结构中的导电层进行电连接，在平行于衬底的方向上，由于导电层的宽度大于第一导电柱和第二导电柱与导电层的接触面的宽度，从而使得在第一衬底正面形成第二导电柱时，只需与导电层对齐即可，换言之，第一导电柱和所述第二导电柱在导电层上的投影可以不完全重叠。如此，增加了第二导电柱的工艺窗口，降低了第一导电柱和第二导电柱的对准难度，增加了第一导电柱和第二导电柱的接触面积，进而降低了硅通孔的电阻，提高了硅通孔的导电性能。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
本申请所提供的几个方法实施例中所揭露的方法，在不冲突的情况 下可以任意组合，得到新的方法实施例。
本申请所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。
本申请所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种半导体结构的形成方法，所述方法包括：
    提供第一衬底；
    在所述第一衬底的背面刻蚀形成沟槽；
    在所述沟槽内形成导电层；
    在所述第一衬底的背面形成延伸进入所述沟槽内的第一导电柱；
    在所述第一衬底的正面形成器件层，所述器件层包括存储阵列及接触结构；
    形成贯穿所述器件层并延伸进入所述第一衬底内的第二导电柱；
    所述第一导电柱和所述第二导电柱通过所述导电层电连接。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，在所述沟槽内形成导电层的步骤，包括：
    在所述沟槽内依次沉积第一绝缘层、第一扩散阻挡层、铜薄膜层；
    位于所述沟槽底部的铜薄膜层构成所述导电层。
  3. 根据权利要求2所述的半导体结构的形成方法，其中，在所述第一衬底的背面形成延伸进入所述沟槽内的第一导电柱的步骤，包括：
    在所述沟槽内沉积第二扩散阻挡层，所述第二扩散阻挡层覆盖所述铜薄膜层；
    在所述沟槽内填充绝缘材料形成绝缘填充层，所述绝缘填充层覆盖所述第二扩散阻挡层；
    对所述绝缘填充层和所述第二扩散阻挡层进行刻蚀以形成第一盲孔，所述第一盲孔暴露部分所述导电层；
    在所述第一盲孔内沉积第三扩散阻挡层，所述第三扩散阻挡层覆盖所述第一盲孔的侧壁及暴露的部分所述导电层；
    在所述第一盲孔内填充第一金属材料，所述第一金属材料覆盖所述第 三扩散阻挡层。
  4. 根据权利要求3所述的半导体结构的形成方法，在所述形成第一盲孔的步骤之前，所述方法还包括：
    在所述绝缘填充层表面形成第一光掩膜层，以图案化的所述第一光掩模层作为掩膜，刻蚀所述绝缘填充层和所述第二扩散阻挡层，以形成所述第一盲孔。
  5. 根据权利要求3所述的半导体结构的形成方法，其中，
    所述沟槽的开口尺寸大于所述第一盲孔的开口尺寸。
  6. 根据权利要求3所述的半导体结构的形成方法，其中，在所述第一盲孔内填充第一金属材料后，所述方法还包括：
    对所述第一衬底的背面进行化学机械研磨工艺，以使所述第一导电柱顶表面与所述衬底顶表面齐平。
  7. 根据权利要求3所述的半导体结构的形成方法，其中，形成贯穿所述器件层并延伸进入所述第一衬底内的第二导电柱的步骤，包括：
    刻蚀形成贯穿所述器件层并延伸进入所述第一衬底内的第二盲孔，所述第二盲孔暴露部分所述导电层；
    在所述第二盲孔内沉积第二绝缘层，并刻蚀去除所述第二盲孔底部的第二绝缘层；
    在所述第二盲孔内沉积第四扩散阻挡层并填充第二金属材料。
  8. 根据权利要求7所述的半导体结构的形成方法，在所述形成第二盲孔的步骤之前，所述方法还包括：
    在所述器件层表面形成第二光掩膜层，以图案后化的所述第二光掩模层作为掩膜，刻蚀所述器件层及所述第一衬底，以形成所述第二盲孔。
  9. 根据权利要求7所述的半导体结构的形成方法，所述方法还包括：
    对所述第一衬底的正面进行化学机械研磨工艺，以使所述器件层顶表面与所述第二导电柱顶表面齐平。
  10. 根据权利要求7所述的半导体结构的形成方法，所述方法还包括：
    在所述器件层上形成互连层，所述互连层与所述第二导电柱电连接；
    其中，所述互连层包括互连通孔和互连金属层。
  11. 根据权利要求7所述的半导体结构的形成方法，所述方法还包括：
    提供键合结构，所述键合结构包括第二衬底和形成在所述第二衬底上的互连层；
    其中，所述互连层包括互连通孔和互连金属层；
    将所述互连层与所述器件层进行键合。
  12. 根据权利要求11所述的半导体结构的形成方法，其中，
    所述互连层与所述第二导电柱电连接。
  13. 一种半导体结构，包括：
    衬底；
    器件层，所述器件层位于所述衬底的正面；
    硅通孔，所述硅通孔设置在所述衬底内部且贯穿所述衬底及所述器件层。
  14. 根据权利要求13所述的半导体结构，其中，
    所述器件层包括存储阵列及接触结构。
  15. 根据权利要求13所述的半导体结构，其中，所述硅通孔包括：
    第一导电柱，所述第一导电柱从所述衬底背面向衬底内部延伸；
    第二导电柱，所述第二导电柱贯穿所述器件层，并从所述衬底正面向衬底内部延伸；
    导电层，所述第一导电柱和所述第二导电柱通过所述导电层电连接。
  16. 根据权利要求15所述的半导体结构，其中，所述硅通孔还包括沟槽结构，所述沟槽结构从所述衬底背面向衬底内部延伸，且未贯穿所述衬底。
  17. 根据权利要求16所述的半导体结构，其中，
    所述沟槽结构包括：第一绝缘层、第一扩散阻挡层、铜薄膜层、第二扩散阻挡层和绝缘填充层；
    其中，位于所述沟槽结构底部的所述铜薄膜层构成所述导电层。
  18. 根据权利要求17所述的半导体结构，其中，
    所述第一导电柱贯穿所述绝缘填充层和所述第二扩散阻挡层，并与所述导电层电连接。
  19. 根据权利要求18所述的半导体结构，其中，
    所述第二导电柱贯穿所述第一绝缘层和所述第一扩散阻挡层，并与所述导电层电连接。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060148250A1 (en) * 2004-12-30 2006-07-06 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
CN103210486A (zh) * 2010-09-17 2013-07-17 德塞拉股份有限公司 芯片两侧分段式通路的形成
CN111769072A (zh) * 2019-04-02 2020-10-13 长鑫存储技术有限公司 半导体互连结构及其制造方法
CN111883498A (zh) * 2020-06-30 2020-11-03 复旦大学 一种dram芯片三维集成系统及其制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060148250A1 (en) * 2004-12-30 2006-07-06 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
CN103210486A (zh) * 2010-09-17 2013-07-17 德塞拉股份有限公司 芯片两侧分段式通路的形成
CN111769072A (zh) * 2019-04-02 2020-10-13 长鑫存储技术有限公司 半导体互连结构及其制造方法
CN111883498A (zh) * 2020-06-30 2020-11-03 复旦大学 一种dram芯片三维集成系统及其制备方法

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