WO2023279911A1

WO2023279911A1 - Chip detection device, detection method, and chip component

Info

Publication number: WO2023279911A1
Application number: PCT/CN2022/097827
Authority: WO
Inventors: 翟峰
Original assignee: 重庆康佳光电技术研究院有限公司
Priority date: 2021-07-08
Filing date: 2022-06-09
Publication date: 2023-01-12
Also published as: CN115602661A; CN115602661B

Abstract

A chip detection device, a detection method, and a chip component. In the chip detection device (20), a first conductive layer (22), an insulation layer (23), and a second conductive layer (24) are sequentially stacked on an insulating bearing plate (21), and an electrode accommodation slot (200) is formed by penetrating through the second conductive layer (22) and the insulation layer (23); the electrode accommodation slot (200) is configured to accommodate a high electrode in a chip under test; a first test region (201) in the first conductive layer (22) that is configured to be electrically connected to the high electrode is exposed out of the bottom of the electrode accommodation slot (200), and a second test region (202) that is electrically connected to a short electrode in the chip under test is disposed on the side of the second conductive layer (24) facing away from the insulation layer (23); and the first conductive layer (22) and the second conductive layer (24) are connected to a first pole and a second pole of a power supply, respectively.

Description

A chip detection device, detection method and chip component

technical field

The present application relates to the field of electronic technology, in particular to a chip testing device, a testing method and a chip assembly.

Background technique

Micro-LED (micro-light-emitting diode) display technology has the advantages of high brightness, high response speed, low power consumption, and long life, and has become a research hotspot for people pursuing a new generation of display technology.

Due to the small size of Micro-LED chips and the large number of chips in the display panel, it is not suitable to power on the finished product after transferring the Micro-LED chips to the driver backplane in the production of Micro-LED display panels to detect and identify dead pixels, because Micro-LED The number of dead chips in LED display panels must be much greater than the number of dead chips in ordinary display panels, and the repair cost and difficulty of repairing a single dead chip must be much higher than that of a single dead chip in ordinary display panels. Repair cost, repair difficulty. Therefore, if this chip inspection scheme is continued to be used in the production process of the Micro-LED display panel, it will lead to the problems of low production efficiency and high cost of the Micro-LED display panel.

Therefore, how to realize the detection of the Micro-LED chip before it is transferred to the driving backplane is an urgent problem to be solved.

technical problem

In view of the deficiencies of the above-mentioned related technologies, the purpose of this application is to provide a chip testing device, a testing method and a chip component, aiming to solve the production cost of the display panel caused by the chip testing after the Micro-LED chip is transferred to the driving backplane High and low production efficiency.

technical solution

The application provides a chip detection device, including:

Insulation bearing plate;

first conductive layer;

a second conductive layer; and

an insulating layer located between the first conductive layer and the second conductive layer;

Wherein, the first conductive layer, the insulating layer, and the second conductive layer are sequentially stacked on the insulating carrier plate; the chip detection device is formed with an electrode receiving groove through the second conductive layer and the insulating layer, and the electrode receiving groove is configured to accommodate the received The high electrode in the test chip, the first test area configured to be electrically connected to the high electrode in the first conductive layer is exposed at the bottom of the electrode containing groove, and the second conductive layer is provided on the side facing away from the insulating layer. The second test area electrically connected to the middle and short electrodes; the first conductive layer and the second conductive layer are respectively configured to be connected to the first pole and the second pole of the power supply.

Based on the same inventive concept, the present application also provides a chip detection method, which is applied to the aforementioned chip detection equipment. The chip detection method includes:

Extending the high electrode of the chip under test into the electrode receiving groove of the chip testing equipment, so that the high electrode is electrically connected with the first test area, and the short electrode is electrically connected with the second test area;

powering the chip detection device via a power supply; and

Determine the detection result of the tested chip according to whether the tested chip is lit.

Based on the same inventive concept, the present application also provides a chip assembly, including:

a carrier substrate; and

Multiple chips under test located on the same surface of the carrier substrate;

Among them, the electrodes of the two chips in the tested chip are located on the first side of the epitaxial layer, and the distances from the free end faces of the electrodes of the two chips to the second side of the epitaxial layer are different, the second side is opposite to the first side, and the free ends of the electrodes of the two chips are opposite to the first side. The one with the larger distance from the end face to the second side is the high electrode, and the one with the smaller distance is the short electrode; the high electrode and the short electrode are respectively configured to be electrically connected to the first test area and the second test area in the chip testing device, The first test area and the second test area provide a potential difference between the high electrode and the short electrode; multiple tested chips are arranged in an array on the carrier substrate, and any tested chip is oriented in the same direction as the rest of the tested chips in the row ;Any chip under test is arranged oppositely to the adjacent chip under test in its row. The opposite arrangement refers to the direction from the high electrode of one chip under test to its short electrode and the direction from the high electrode of another chip under test. The direction of its dwarf electrodes is opposite.

Beneficial effect

The above-mentioned chip detection equipment includes an insulating carrier board, a first conductive layer, an insulating layer and a second conductive layer. The insulating layer realizes the electrical isolation between the two conductive layers, the first conductive layer is connected to one pole of the power supply, and the second conductive layer layer is connected to the other pole of the power supply; the electrode containing groove is formed by penetrating the second conductive layer and the insulating layer, the first test area on the first conductive layer is exposed to the bottom of the electrode containing groove, and the second conductive layer faces away from the insulating layer One side of the device is provided with a second test area, and the first test area and the second test area respectively provide a potential difference between two chip electrodes of the chip under test, so as to realize the lighting test of the chip under test. The chip detection equipment can provide high voltage for the chip under test, so whether the chip under test can be lit can be realized before the chip under test is bonded to the drive backplane, and if the chip under test is a dead point chip, it will not be transferred To the driver backplane, this avoids the heavy chip repair work caused by the chip under test being identified as a dead chip after being bound to the driver backplane, improves the production efficiency of the display panel, and reduces the cost of the display panel.

The above-mentioned chip detection method utilizes the potential difference provided by the aforementioned chip detection equipment between the electrodes of the two chips of the chip under test, so whether the chip under test can be lit can be realized before the chip under test is bonded to the drive backplane. If the chip under test is a dead point chip, it will not be transferred to the drive backplane, which avoids the heavy chip repair work caused by the chip under test being identified as a dead point chip after it is bound to the drive backplane, and improves the display panel. The production efficiency is improved, and the cost of the display panel is reduced.

The above-mentioned chip assembly contains a plurality of chips under test, and there is a height difference between the two chip electrodes of these chips under test. Provide voltage for the chip under test before transferring to the driver backplane, and test whether the chip under test can be lit normally, which avoids the heavy chip caused by being identified as a dead chip after the chip under test is bound to the driver backplane The repair work has improved the production efficiency of the display panel and reduced the cost of the display panel.

Description of drawings

FIG. 1 is a schematic structural diagram of a light-emitting chip provided in an optional embodiment of the present application;

FIG. 2 is a schematic diagram of a three-dimensional structure of a chip detection device provided in an optional embodiment of the present application;

FIG. 3 is a schematic diagram of the cooperation between the chip detection device and the chip under test shown in an optional embodiment of the present application;

FIG. 4 is a schematic structural diagram of another chip testing device shown in an optional embodiment of the present application;

FIG. 5 is a schematic structural diagram of another chip testing device shown in an optional embodiment of the present application;

FIG. 6 is a schematic structural diagram of another chip testing device shown in an optional embodiment of the present application;

Fig. 7 is a schematic diagram of arrangement of tested chips in a chip assembly shown in another optional embodiment of the present application;

Fig. 8a is a schematic cross-sectional view of another chip assembly shown in another optional embodiment of the present application;

Fig. 8b is a schematic top view of the chip assembly in Fig. 8a;

Fig. 8c is a schematic diagram of cooperation between the chip assembly and the chip testing equipment in Fig. 8a;

FIG. 9 is a schematic structural diagram of a chip testing device shown in another optional embodiment of the present application;

FIG. 10 is a schematic structural diagram of another chip testing device shown in another optional embodiment of the present application;

Fig. 11 is a schematic cross-sectional view of the chip detection device in Fig. 10;

Fig. 12 is a schematic flowchart of a chip detection method provided in another optional embodiment of the present application.

Explanation of reference signs:

10-Light-emitting chip; 11-Epitaxial layer; 12-Chip electrode; 20-Chip testing equipment; 200-Electrode holding tank; 201-First test area; 1st conductive layer; 23-insulating layer; 24-second conductive layer; 25-first signal application pad; 26-second signal application pad; 27-conductive connector; 28-insulator; 30-tested chip; 40 -chip testing equipment; 400-elastic components; 50-chip testing equipment; 500-elastic conductive parts; 60-chip testing equipment; 70-chip components; ; 81-carrier substrate; 82-tested chip; a, b, c-tested chip; 90-chip testing equipment; 900-power interface; 100-chip testing equipment.

Embodiments of the present invention

In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Preferred embodiments of the application are shown in the accompanying drawings. However, the present application can be embodied in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the application more thorough and comprehensive.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terminology used herein in the description of the application is only for the purpose of describing specific embodiments, and is not intended to limit the application.

Compared with the existing liquid crystal display, Micro-LED display technology has higher photoelectric efficiency, higher brightness, higher contrast, and lower power consumption, and it can also be combined with flexible panels to achieve flexible display, so many manufacturers Consider it as a next-generation display technology and start actively researching it.

The existing technical solution for LED chip detection is to transfer the LED chip to the driving backplane, power on the driving backplane, and detect dead pixels through a probe. However, Micro-LED display panels are different from ordinary LED display panels. The chip size and chip consumption are not the same order of magnitude as ordinary LED display panels. Higher, lower repair success rate.

Based on this, the present application hopes to provide a solution capable of solving the above-mentioned technical problems, the details of which will be described in subsequent embodiments.

An optional embodiment of the application:

This application first introduces a light-emitting chip, please refer to the schematic structural diagram of the light-emitting chip shown in Figure 1:

The light emitting chip 10 includes an epitaxial layer 11 and two chip electrodes 12 . The epitaxial layer 11 includes at least an N-type semiconductor layer, an active layer, and a P-type semiconductor layer arranged in sequence. In addition, the epitaxial layer 11 may also include a current spreading layer arranged on the side of the P-type semiconductor layer away from the active layer. , the buffer layer disposed on the side of the N-type semiconductor layer away from the active layer, the electron blocking layer disposed between the active layer and the P-type semiconductor layer, the transition layer disposed between the active layer and the N-type semiconductor layer, etc. At least one of several layer structures. In this embodiment, the two chip electrodes 12 of the light-emitting chip 10 are arranged on the same side of the epitaxial layer 11, and the side where the chip electrodes 12 are located is referred to as the "first side" of the epitaxial layer 11, and the epitaxial layer 11 and the The side opposite the first side is the "second side". The respective fixed ends of the two chip electrodes 12 are connected to the epitaxial layer 11, and one of the chip electrodes 12 is electrically connected to the N-type semiconductor layer in the epitaxial layer 11, which is the N electrode of the light-emitting chip 10; the other chip electrode 12 is connected to the epitaxial layer. The P-type semiconductor layer in 12 is electrically connected to the P-electrode of the light-emitting chip 10 . In this embodiment, the distances between the end surfaces of the free ends of the two chip electrodes 12 and the second side of the epitaxial layer 11 are different, and the distance between the free end surfaces of the free ends and the second side of the epitaxial layer 11 is relatively large. High electrode”, and the one whose free end surface is relatively small from the second layer of the epitaxial layer 11 is the “short electrode” of the light-emitting chip 10 . Those skilled in the art can understand that the so-called "high electrode" and "short electrode" in this embodiment are relative to the two chip electrodes 12 in the same light-emitting chip 10, and are relative to the second side of the epitaxial layer 11. In terms of , it has nothing to do with the actual height of the chip electrode 12 protruding from the surface of the epitaxial layer 11 . In the drawings of this embodiment, figures filled with squares represent high electrodes, and figures filled with oblique lines represent short electrodes. In some examples of this embodiment, the high electrode is a P electrode electrically connected to the P-type semiconductor layer, and the short electrode is an N electrode electrically connected to the N-type semiconductor layer; however, in some other examples of this embodiment, The high electrode can also be an N electrode, and the short electrode can be a P electrode.

For the detection work of the light-emitting chip 10 above, this embodiment also provides a chip detection device, please refer to a schematic structural diagram of the chip detection device 20 shown in FIG. plate 21 , first conductive layer 22 , insulating layer 23 and second conductive layer 24 . As the name implies, the insulating carrier board 21 is insulated from the insulating layer 23 , while the first conductive layer 22 and the second conductive layer 24 have good electrical conductivity.

The insulating carrier board 21 is used to carry the first conductive layer 22, the insulating layer 23 and the second conductive layer 24. The insulating carrier board 21 is usually a hard substrate, which is not easy to deform, or even basically has no deformability. For example, its It may not be limited to any one of sapphire substrates, glass substrates, silicon nitride substrates, silicon oxide substrates, and the like. The insulating layer 23 is arranged between the first conductive layer 22 and the second conductive layer 24 to electrically isolate the two. In this embodiment, the insulating layer 23 can also be a silicon nitride substrate, a silicon oxide substrate or a sapphire substrate. However, since the insulating layer 23 needs to be penetrated in the chip testing equipment, the insulating layer 23 is generally an insulating material that is relatively easy to be patterned. The first conductive layer 22 and the second conductive layer 24 can be conductive metals, such as copper, aluminum, etc., or non-metallic materials with good electrical conductivity, such as indium tin oxide, carbon nanotube materials, etc.

On the chip testing device 20, an electrode receiving groove 200 is formed through the second conductive layer 24 and the insulating layer 23. The notch of the electrode receiving groove 200 is located on the surface of the second conductive layer 24 away from the insulating layer 23, and the first conductive layer 22 Part of the area is exposed at the bottom of the electrode containing groove 200 , forming the first test area 201 of the chip testing device 20 . It can be understood that the electrode accommodating groove 200 is used for accommodating the electrodes of the chip under test, specifically, it is used for accommodating the upper electrodes of the chip under test having a structure similar to that of the aforementioned light-emitting chip 10, and the first test area 201 is configured to be electrically connected to the high electrode in the chip under test. A second test area 202 is provided on the side of the second conductive layer 24 away from the insulating layer 23 , and the second test area 202 is configured to be electrically connected to the short electrodes in the chip under test. In this embodiment, the first conductive layer 22 and the second conductive layer 24 are respectively connected to the first pole and the second pole of the power supply to provide a voltage between the two chip electrodes 12 of the chip under test, that is, to provide a potential Difference. It should be understood that the chip under test is a light-emitting diode, such as Mini-LED (mini light-emitting diode), Micro-LED or OLED (Organic Light-Emitting Diode, organic light-emitting diode), which has unidirectional conduction characteristics, so , when the first conductive layer 22 and the second conductive layer 24 are connected to the power supply, it should be determined according to the distribution of the N electrode and the P electrode between the high electrode and the short electrode. For example, if the high electrode is a P electrode, then on the second conductive layer 24 The second test area 202 on the first conductive layer 22 should provide a high level to the chip under test, and the first test area 201 on the first conductive layer 22 should provide a low level to the chip under test. In this case, the second conductive Layer 24 should be connected to the positive pole of the power supply and the first conductive layer 22 should be connected to the negative pole of the power supply, so that the first pole of the power supply is negative and the second pole is positive.

Undoubtedly, the high electrode of the chip under test needs to be electrically connected with the first conductive layer 22, but cannot be electrically contacted with the second conductive layer 24. Therefore, when the high electrode of the chip under test stretches into the electrode receiving groove 200 , it should be ensured that the end surface of the high electrode can be electrically connected with the first test area 201 , but at the same time, the side surface of the high electrode will not be in contact with the exposed second conductive layer 24 on the side wall of the electrode containing groove 200 . Therefore, in some examples of this embodiment, the size of the electrode receiving groove 200 should be relatively large, so as to ensure that when the high electrode extends into it, the side of the high electrode will not touch the side wall of the electrode receiving groove 200 . In some other examples, an insulating material may be covered on the sidewall of the electrode containing groove 200 to ensure that the second conductive layer 24 will not be exposed from inside and outside the electrode containing groove 200 .

It can be understood that there is a height difference between the high electrode and the short electrode in the tested chip 30, as shown in FIG. In some examples of this embodiment, the end faces of the high electrodes in the tested chip 30 are configured to be bonded to the first test area 201, and the end faces of the short electrodes are configured to be bonded to the second test area 202. The chip electrode 12 of the test chip is directly in contact with the conductive layer in the chip testing device 20. When there is no deformation space in the first conductive layer 22 and the second conductive layer 24, the first test area in the chip testing device 20 The height difference between 201 and the second test area 202 is equal to the height difference between the upper electrode and the lower electrode in the tested chip 30 , as shown in FIG. 3 .

However, in some examples of this embodiment, at least one of the first conductive layer 22 and the second conductive layer 24 in the chip testing device 40 has a deformation space. For example, as shown in FIG. 4 , the first conductive layer 22 is flexible. Conductive layer, and in the first test area 201, and between the first conductive layer 22 and the insulating bearing plate 21, an elastic member 400, such as a spring or a rubber pad, is arranged, and the elastic member 400 can be compressed when squeezed , so as to reduce the distance between the first conductive layer 22 and the insulating carrier plate 21 in the first test area 201, that is, increase the groove depth of the electrode containing groove 200, and when the pressure is removed, it can naturally return to its original shape. In these examples, before testing the chip under test, the height difference between the first test area 201 and the second test area 202 in the chip testing device 40 is usually smaller than the height difference between the two chip electrodes 12 in the test chip.

In some examples, there is no deformation space for the first conductive layer 22 and the second conductive layer 24, but when the chip testing equipment detects the chip under test, at least one of the two chip electrodes 12 of the chip under test does not Directly contact with the corresponding test area in the chip testing equipment, for example, in the chip testing equipment 50 shown in Fig. When the high electrode in the chip is electrically connected to the first test area 201 of the chip testing device 50, it is realized through the elastic conductive member 500. In this case, the free end of the elastic conductive member 500 (that is, the end away from the first conductive layer 22) The height difference between the second test area 202 is less than the height difference between the two chip electrodes 12 in the tested chip, but the height difference between the first test area 201 and the second test area 202 is greater than the two chip electrodes 12 in the tested chip height difference between them.

In some examples of this embodiment, the electrode accommodating groove 200 is only formed by penetrating the insulating layer 23 and the second conductive layer 24. In this case, the depth of the electrode accommodating groove 200 is equal to that of the insulating layer 23 and the second conductive layer 24. , that is, the side of the first conductive layer 22 facing the insulating layer 23 is flat, as shown in FIG. 3 . In some other examples, the groove depth of the electrode containing groove 200 is greater than the sum of the thicknesses of the insulating layer 23 and the second conductive layer 24, but less than the thicknesses of the first conductive layer 22, the insulating layer 23 and the second conductive layer 24. And, that is, the first conductive layer 22 will also be recessed toward the side of the insulating carrier plate 21, but will not be penetrated, as shown in the chip testing device 60 in FIG. 6 . In some examples, the electrode accommodating groove 200 is formed by etching. For example, when the chip testing device is formed, when the insulating carrier plate 21, the first conductive layer 22, the insulating layer 234 and the second conductive layer 24 are stacked together, this None of the four layer structures have been patterned, and then patterned from the side where the second conductive layer 24 is located, such as dry etching or wet etching, to form the electrode receiving groove 200 . In some other examples, before the four layer structures are stacked together, the insulating layer 234 and the second conductive layer 24 have been patterned, for example, the patterned insulating layer 234 or the patterned second conductive layer 24 is passed through the mold. Formed by casting etc.

The chip detection device provided in this embodiment can realize EL (electroluminescence) detection of the light-emitting chip before transferring the light-emitting chip to the driving backplane, identify dead chips in advance, and reduce the cost of manufacturing and repairing the display panel.

Another optional embodiment of this application:

This embodiment will further introduce the structure of the chip detection equipment on the basis of the previous embodiment, please continue to combine Figure 1 to Figure 6:

In some examples of this embodiment, one electrode containing groove 200 is only used to accommodate the upper electrode of one chip under test. Grooves, for example, in one example, the chip testing device has a plurality of electrode accommodating grooves 200 arranged in an array. In some other examples, one electrode accommodating groove 200 can at least accommodate the upper electrodes of two chips under test at the same time.

In some examples, the notch of the electrode containing groove 200 is rectangular, the direction parallel to the long side of the notch is the groove length direction of the electrode containing groove 200, and the direction parallel to the short side of the notch is the groove of the electrode containing groove 200. In the width direction, it can be understood that the groove length direction and the groove width direction are perpendicular to each other. In some examples of this embodiment, the length of the electrode receiving groove 200 can allow the high electrodes of multiple chips under test arranged along the length of the groove on the carrier substrate to protrude into it at the same time (that is, into the electrode receiving groove 200 ), As shown in FIG. 2 , the notch of the electrode receiving groove 200 in the chip testing device 20 is roughly elongated, that is, the ratio of length to width is large, so that it can support a row (or column) of the high electrodes on the substrate roughly in a straight line. The high electrodes of the chips under test extend into it at the same time, and the straight line formed by the high electrodes of the row (or column) of the chips under test will not pass through the short electrodes of any one of the chips under test in this row (or column). Usually, the short electrodes of a row (or column) of chips under test whose high electrodes extend into the same electrode receiving groove 200 are also on a straight line, which is parallel to the straight line formed by the high electrodes, for example, please refer to FIG. 7 for further details. A schematic diagram of the arrangement of the tested chips in a chip assembly is shown: the chip assembly 70 includes a carrier substrate 71 and a plurality of tested chips 72. same. The plurality of tested chips 72 are arranged in an array on the carrier substrate 71 . In the chip assembly 70, the orientation of each tested chip 72 is the same, and the orientation mentioned here refers to the direction in which the high electrode in the tested chip 72 points to its short electrode (or the short electrode points to its high electrode), as shown in Fig. In 7, the figure filled with squares represents the high electrode, and the figure filled with oblique lines represents the short electrode. In FIG. 7 , the high electrodes of each column of tested chips 72 can extend into the same electrode receiving groove 200 of the chip testing device 20, corresponding to the same first test area 201, and the short electrodes of each column of tested chips 72 can correspond to the same first test area 201. Second test area 202. Undoubtedly, in some other chip assemblies, the tested chips 72 whose high electrodes correspond to the same first test area 201 can also be arranged in a row on the carrier substrate.

In some examples of this embodiment, the groove width of the electrode receiving groove 200 only needs to ensure that the high electrode of a chip under test protrudes into it, and the high electrode will not interfere with the second conductive layer in the side wall of the electrode containing groove 200. Just get in touch. For example, when the chip testing equipment is testing the chip 72 under test in the chip assembly 70 , along the groove width direction of the electrode containing groove 200 , one electrode containing groove 200 has only one high electrode. In some other examples of this embodiment, the groove width of the electrode receiving groove 200 can be extended into it by the high electrodes of the first chip group under test on the carrier substrate at the same time, and the first chip group under test consists of two chips along the groove width direction. For example, please refer to a schematic diagram of another chip assembly 80 shown in FIG. 8a and FIG. A plurality of tested chips 82, the structure of the tested chip 82 can refer to the structure of the light-emitting chip 10 in Figure 1, in Figure 8, the tested chips a and b can form a first tested chip group: for example, a and b is in the same row, and at the same time, the direction of the high electrode of a pointing to its short electrode is opposite to the direction of the high electrode of b pointing to its short electrode, therefore, a and b are arranged in opposite directions; moreover, the distance between the high electrodes of a and b smaller than the pitch of the short electrodes. In some examples of this embodiment, in the chip testing device 20 shown in FIG. The electrodes extend into it at the same time, and at the same time, the width of the electrode containing groove 200 can allow the upper electrodes of the first chipset under test on the carrier substrate 81 to extend into it at the same time. Corresponding to Fig. 8a and Fig. 8b, that is, the high electrodes of the tested chips a and b can extend into the same electrode receiving groove 200, and the tested chip 82 in the same column as a and the tested chip 82 in the same column as b The upper electrode can also protrude into the same electrode receiving groove 200 . In Figure 8a and Figure 8b, the figures filled with squares represent high electrodes, and the figures filled with oblique lines represent short electrodes

In some examples of this embodiment, the chip testing device includes a plurality of electrode containing grooves 200 whose groove lengths are parallel to each other. Please continue to refer to FIG. The test area 202 includes the strip-shaped gap area. In some examples of this embodiment, the gap width of the strip-shaped gap region only needs to ensure that the short electrode of one chip under test is covered. For example, when the chip testing device is testing the chip 72 under test in the chip assembly 70 , along the width direction of the strip-shaped gap region, one strip-shaped gap region only needs to cover one short electrode. In some other examples of this embodiment, the gap width of the strip-shaped gap region can cover the short electrodes of a second chip group under test on the carrier substrate at the same time, and the second chip group under test consists of two chips facing each other along the gap width direction. Arranged chips under test constitute, for example, please continue to refer to FIG. 8a and FIG. 8b: chips under test c and b can form a second chip group under test: for example, c and b are in the same row, and the two are arranged opposite to each other; and The distance between the high electrodes of b and c is greater than the distance between the short electrodes. If the tested chips a and b are arranged "face-to-face", then the tested chips b and c are arranged "back-to-back". In the chip testing device 20 shown in FIG. 2 in some examples, the gap length of the strip-shaped gap region can ensure that the strip-shaped gap region simultaneously covers the short electrodes of a plurality of chips under test 82 arranged along the gap length direction on the carrier substrate 81. , at the same time, the gap width of the strip-shaped gap region can ensure that the strip-shaped gap region covers the carrier substrate 81 and the short electrodes of the second chipset under test at the same time. Corresponding to Figure 8a and Figure 8b, that is, the short electrodes of the tested chips b and c can be covered by the same strip-shaped gap area, and the tested chip 82 in the same column as c and the tested chip 82 in the same column as b The short electrodes can also be covered by the strip-shaped gap area at the same time, as shown in FIG. 8c.

It can be understood that, in the chip assembly 80 provided in FIGS. 8a and 8b , the tested chips 82 are arranged in an array on the carrier substrate 81 , and the carrier substrate 81 can be the growth substrate of these tested chips 82 or just a temporary substrate. The tested chip 82 can be a flip-chip structure or a front-chip structure. When using the chip detection equipment to detect the tested chip 82 in the chip assembly 80, a spectrometer can be used to record the positions of the dead chips that cannot be lighted. In some examples, the chip detection equipment has a spectrometer. In other examples, the spectrometer is an external device of the chip detection device. The spectrometer can record the mapping diagram of the chip under test 82 in the chip assembly 80 after it is lit.

It can be seen from FIG. 8 b that any tested chip 82 is oriented in the same direction as the other tested chips 82 in the column, and any tested chip 82 is arranged opposite to the adjacent tested chips 82 in the row. In the corresponding chip testing equipment, for two adjacent columns of tested chips 82 that can form a plurality of first tested chip groups, only one electrode accommodating groove 200 can be provided, which is compared with a column of tested chips 82 exclusively occupying one electrode. In the case of the accommodating groove 200, when the size of the chip under test 82 is fixed, the size of the electrode accommodating groove 200 can be increased; , can share one strip-shaped gap area, which is compared with the situation where a column of tested chips 82 exclusively occupies one strip-shaped gap area, and the size of the strip-shaped gap area can be increased when the size of the tested chip 82 is given. In this way, large-sized chip testing equipment can be applied to the testing of small-sized chips, reducing the production difficulty of chip testing equipment, especially reducing the production difficulty of chip testing equipment for testing small-sized devices such as Micro-LED chips.

The chip detection equipment and chip components provided in this embodiment can not only accurately identify dead chips in advance and reduce the production and repair costs of the display panel, but also when the chip detection equipment performs chip testing, the two adjacent rows of light-emitting chips form A plurality of first tested chip groups can share one electrode containing groove, and a plurality of second tested chip groups formed by adjacent two columns of light-emitting chips can correspond to the same strip-shaped gap area, which can increase the electrode containing groove. The size and the size of the gap between the electrode accommodating grooves reduce the requirement on the dimensional accuracy of the chip testing equipment, thereby reducing the production difficulty of the chip testing equipment.

Another optional embodiment of the present application:

In order to make the structure and advantages of the chip testing equipment provided by this application clearer to those skilled in the art, this embodiment will introduce the aforementioned chip testing equipment in more detail:

In the chip testing device, the first conductive layer is configured to be electrically connected to the first pole of the power supply, and the second conductive layer is configured to be electrically connected to the second pole of the power supply. In some examples of this embodiment, as shown in FIG. 9 In the chip testing device 90 shown, at least part of the side areas of the first conductive layer 22 and the second conductive layer 24 are exposed, so that the power interface 900 connected to the power supply is provided so that the two ends of the electrodes of the power supply can be directly connected to the chip testing device through wires. The side surfaces of 90 are connected to the first conductive layer 22 and the second conductive layer 24 . In some other examples, the chip testing device 100 shown in FIG. 10 and FIG. 11 further includes a first signal application pad 25 and a second signal application pad 26 disposed on the side of the second conductive layer 22 away from the insulating layer 23. , wherein the first signal application pad 25 is electrically connected to the first conductive layer 22 through a conductive connector 27 , while the second signal application pad 26 can be directly electrically connected to the second conductive layer 24 . In addition, the chip testing device 100 also includes an insulator 28 that realizes electrical isolation between the first signal application pad 25 and the second conductive layer 24, and between the conductive connector 27 and the second conductive layer. In an example, the conductive connector 27 can realize the electrical connection between the first signal application pad 25 and the first conductive layer 22 from the side of the chip testing device 100. In some examples, the chip testing device is provided with a penetrating second conductive layer. The connection hole between the layer 24 and the insulating layer 23, and the conductive connection member 27 is located in the connection hole, as shown in FIG. 10 . When the missile connector 27 is arranged in the connection hole, the insulating member 28 can be an insulating ring, which can be sleeved on the side of the conductive connector 27, and placed between the first signal application pad 25 and the second conductive layer 24, such as Figure 11 shows.

The conductive connector 27 may include metal solder (such as In (indium), Sn (tin), etc.), or polymer conductive materials including PEDOT (a polymer of EDOT (3,4-ethylenedioxythiophene monomer)), or Including nano-metal materials such as nano-silver wire.

In some examples of this embodiment, in order to ensure that the electrical connection between the power supply and the first conductive layer 22 and the second conductive layer 24 does not occupy the contact area between the chip testing device 100 and the chip under test, or does not occupy the electrode receiving groove 200 If there is a strip-shaped gap area between the setting area of the electrode receiving groove 200, the first signal application pad 25 and the second signal application pad 26 can be arranged on the edge area of the second conductive layer 24, and the edge area mentioned here includes The area adjacent to the side of the second conductive layer 24 and the corner area of the second conductive layer 24 . In some examples of this embodiment, the first signal application pad 25 and the second signal application pad 26 are respectively located at two different corner regions of the second conductive layer 24, and in another example, the two signal application pads are respectively close to two sides of the second conductive layer 24 . However, in an example of this embodiment, the first signal application pad 25 and the second signal application pad 26 are located on the same side of the second conductive layer 24 .

This embodiment also provides a chip detection method, the chip detection method is applied to any of the aforementioned chip detection devices, please refer to the schematic flow diagram shown in Figure 12:

S1202: Insert the high electrode of the chip under test into the electrode receiving groove of the chip testing device, so that the high electrode is electrically connected with the first test area, and the short electrode is electrically connected with the second test area.

It can be understood that when using the chip testing equipment provided in any of the above examples to test the chip under test, it is necessary to align the chip under test with the chip testing device to ensure that the high electrodes of the chip under test can go deep into the electrodes of the chip testing device The accommodating groove cooperates with the first test area in the electrode accommodating groove, and at the same time, the short electrode of the chip under test can cooperate with the second test area on the chip testing equipment. If the chip detection equipment is to simultaneously detect multiple tested chips arranged in an array on the chip assembly, the chip detection equipment must be aligned with the chip assembly.

If the height difference between the first test area and the second test area in the chip testing equipment is just equal to the height difference between the chip electrodes in the chip under test, the high electrode is electrically connected to the first test area, and the short electrode is electrically connected to the second test area. The connection method is to ensure that the end face of the high electrode is attached to the first test area, and the end face of the short electrode is attached to the second test area; if there is an elastic conductive part in the first test area, it is necessary to ensure that the high electrode and the elastic conductive part touch.

S1204: Supply power to the chip detection device through a power supply.

In this embodiment, the chip testing equipment is powered on after the alignment and connection between the chip testing equipment and the chip under test are completed. Although it is theoretically possible to power on the chip testing equipment at the beginning, because the chip testing equipment In the process of alignment and connection with the chip under test, an unstable electrical connection may occur, which may damage the chip under test. Therefore, in this embodiment, after adjusting the positional relationship between the chip under test and the chip detection device, the power is turned on. Ensure the safety of the testing process.

It can be understood that if the high electrode of the tested chip is a P electrode and the short electrode is an N electrode, then a high potential can be applied to the first conductive layer and a low potential can be applied to the second conductive layer through the power supply, for example, the chip detection device Connect the first signal application pad to the positive pole of the power supply, and connect the second signal application pad to the negative pole of the power supply.

S1206: Determine the detection result of the tested chip according to whether the tested chip is turned on.

After supplying power to the chip detection equipment, for any chip under test, it can be determined whether the chip under test is a dead point chip according to whether it is lit: if the chip under test is lit up, it is not a bad point chip Chip, if it cannot be lit, it is a dead chip.

After testing multiple tested chips in the chip assembly, the position of the dead chip on the carrier substrate can be recorded, and then the dead chip can be removed by laser, etc., or only the dead chip can be recorded first and ensure the follow-up The dead chip is not transferred, not removed.

The chip detection method provided in this embodiment utilizes the potential difference provided by the aforementioned chip detection equipment between the two chip electrodes of the chip under test, so whether the chip under test can be lit can be determined before the chip under test is bonded to the drive backplane. Realized, if the chip under test is a dead point chip, it will not be transferred to the driver backplane, which avoids the heavy chip repair work caused by the chip under test being identified as a dead point chip after being bound to the driver backplane, The production efficiency of the display panel is improved, and the cost of the display panel is reduced.

It should be understood that the application of the present application is not limited to the above examples, and those skilled in the art can make improvements or changes based on the above descriptions, and all these improvements and changes should belong to the protection scope of the appended claims of the present application.

Claims

A chip detection device, comprising:

Insulation bearing plate;

first conductive layer;

a second conductive layer; and

an insulating layer between the first conductive layer and the second conductive layer;

Wherein, the first conductive layer, the insulating layer, and the second conductive layer are sequentially stacked on the insulating carrier plate; the chip detection device passes through the second conductive layer and the insulating layer An electrode accommodating groove is formed, the electrode accommodating groove is configured to accommodate the high electrode in the chip under test, and the first test area configured to be electrically connected to the high electrode in the first conductive layer is exposed to the electrode The groove bottom of the accommodating groove, the second conductive layer is provided with a second test area electrically connected to the short electrode in the chip under test on the side facing away from the insulating layer; the first conductive layer, the second The conductive layers are respectively configured to be connected to the first pole and the second pole of the power supply.
The chip testing device according to claim 1, further comprising:

a first signal application pad electrically connected to the first conductive layer;

a second signal application pad electrically connected to the second conductive layer;

conductive connectors; and

insulation;

Wherein, the first signal application pad is connected to the first conductive layer through the conductive connector, and the first signal application pad and the second signal application pad are both located at the back side of the second conductive layer. On one side of the insulating layer, the insulating member is configured to electrically isolate the second conductive layer from the first signal application pad, and the second conductive layer from the conductive connecting member.
The chip testing device according to claim 2, wherein a connection hole penetrating through the second conductive layer and the insulating layer is provided on the chip testing device, and the conductive connecting member is located in the connection hole.
The chip inspection device according to claim 2, wherein the first signal application pad and the second signal application pad are located at an edge area of the second conductive layer.
The chip testing device according to claim 1, wherein the sidewall of the electrode containing groove is covered with an insulating material.
The chip inspection device according to claim 1, wherein at least one of silicon oxide and silicon nitride is included in the insulating layer.
The chip testing device according to claim 1, wherein the length of the electrode receiving groove can allow the high electrodes of the chips under test arranged along the length of the groove on the carrier substrate to simultaneously extend into the electrodes In the accommodating groove, the groove length direction is the direction in which the long side of the electrode accommodating groove extends, and the groove length direction and the groove width direction are perpendicular to each other.
The chip testing device according to claim 7, wherein the width of the electrode receiving groove allows the upper electrodes of the first chip group under test on the carrier substrate to simultaneously extend into the electrode receiving groove, The first chip group under test is composed of two chips under test arranged oppositely along the groove width direction, and the distance between the two high electrodes in the first chip group under test is smaller than the two The distance between the short electrodes; the opposite arrangement means that the direction from the high electrode of one chip under test to its short electrode is opposite to the direction from the high electrode of another chip under test to its short electrode.
The chip testing device according to claim 7, wherein said chip testing device has at least two electrode containing grooves whose groove lengths are parallel to each other.
The chip testing device according to claim 9, wherein said second test area comprises a strip-shaped gap between adjacent said electrode accommodating grooves, and the gap width of said strip-shaped gap is sufficient to simultaneously cover said The short electrode of the second chip group under test on the carrier substrate, the second chip group under test is composed of two chips under test arranged oppositely along the groove width direction, and the second chip group under test The distance between the two short electrodes in the test chip group is less than the distance between the two high electrodes; the opposite arrangement refers to the direction from the high electrode of one of the tested chips to its short electrode and the direction from the other said tested chip. The high electrodes of the test chip point in the opposite direction to the short electrodes.
The chip testing device according to claim 1, wherein the chip testing device further comprises a spectrometer, and the spectrometer is configured to communicate with a plurality of the tested chips in the first testing area and the second testing area, respectively. When the high electrode and the short electrode of the chip are bonded, and the first conductive layer and the second conductive layer are respectively connected to the first pole and the second pole, record the chip under test The position of the dead pixel chip that is not lit.
The chip testing apparatus according to claim 1, wherein a side of the first conductive layer facing the insulating layer is flat.
The chip testing device according to claim 1, wherein the height difference between the first test area and the second test area is equal to the height between the high electrode and the short electrode in the chip under test Difference.
A chip detection method, applied to the chip detection device as claimed in claim 1, said chip detection method comprising:

Extending the high electrode of the chip under test into the electrode containing groove of the chip testing device, so that the high electrode is electrically connected to the first test area, and the short electrode is electrically connected to the second test area ;

powering the chip detection device through the power supply; and

The detection result of the tested chip is determined according to whether the tested chip is turned on.
A chip assembly, comprising:

a carrier substrate; and

Multiple tested chips located on the same surface of the carrier substrate;

Wherein, the two chip electrodes in the tested chip are located on the first side of the epitaxial layer, and the distances from the free end faces of the two chip electrodes to the second side of the epitaxial layer are different, and the second side is different from the second side of the epitaxial layer. The first side is opposite, and the one with the larger distance from the free end surface of the two chip electrodes to the second side is a high electrode, and the one with a smaller distance is a short electrode; the high electrode and the short electrode are respectively configured In order to be electrically connected with the first test area and the second test area in the chip testing equipment, the first test area and the second test area provide a potential difference between the high electrode and the short electrode; The tested chips are arranged in an array on the carrier substrate, any one of the tested chips faces the same direction as the rest of the tested chips in the column, and any one of the tested chips faces the adjacent tested chips in the row. Arrangement, opposite arrangement means that the direction from the high electrode of one chip under test to its short electrode is opposite to the direction from the high electrode of another chip under test to its short electrode.