WO2023274158A1 - 一种量子器件及其制备方法和一种电子器件 - Google Patents

一种量子器件及其制备方法和一种电子器件 Download PDF

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WO2023274158A1
WO2023274158A1 PCT/CN2022/101569 CN2022101569W WO2023274158A1 WO 2023274158 A1 WO2023274158 A1 WO 2023274158A1 CN 2022101569 W CN2022101569 W CN 2022101569W WO 2023274158 A1 WO2023274158 A1 WO 2023274158A1
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quantum
lead
signal
chip
substrate
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PCT/CN2022/101569
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English (en)
French (fr)
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杨晖
李业
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合肥本源量子计算科技有限责任公司
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Priority claimed from CN202110718555.XA external-priority patent/CN115602639A/zh
Priority claimed from CN202121464017.4U external-priority patent/CN215008192U/zh
Application filed by 合肥本源量子计算科技有限责任公司 filed Critical 合肥本源量子计算科技有限责任公司
Priority to EP22831972.9A priority Critical patent/EP4365937A1/en
Publication of WO2023274158A1 publication Critical patent/WO2023274158A1/zh
Priority to US18/488,931 priority patent/US20240090348A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • H10N60/81—Containers; Mountings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • H10N60/82—Current path
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control

Definitions

  • the present application belongs to the field of quantum information, especially the technical field of quantum computing.
  • the present application relates to a quantum device, a preparation method thereof, and an electronic device.
  • Quantum chips carrying qubits require a stable working environment. Therefore, in order to reduce the impact of the external environment on quantum chips, it is usually necessary to package the quantum chips first and then run the quantum chips at low temperatures. During packaging, the signal port of the quantum chip needs to be electrically connected to the transmission line located outside the quantum chip. The transmission line is used to lead out the signal port to realize the input and output of the signal. Performance directly affects signal transmission, which in turn affects the operation of quantum chips.
  • aluminum wire bonding (wire bonding) is usually used to electrically connect the signal port to the above-mentioned transmission line.
  • wire bonding is usually used to electrically connect the signal port to the above-mentioned transmission line.
  • the way of connecting the signal ports and the above-mentioned transmission lines by aluminum wire bonding doubles the number of aluminum wires. Each aluminum wire All will bring impedance and inductive reactance, and then introduce complex field effects, which will cause unpredictable interference to the transmission signal on the quantum chip.
  • the purpose of this application is to provide a quantum device and its preparation method and an electronic device to solve the complex field effect introduced by the aluminum wire connecting the quantum chip and the external transmission line in the prior art, which will cause the transmission signal on the quantum chip The problem of unpredictable interference.
  • An embodiment of the present application provides a quantum device, including:
  • a quantum chip, a signal transmission element is formed on the quantum chip, and a connection portion electrically connected to the signal transmission element;
  • a packaging substrate on which a lead-out portion is formed, and a lead-out signal line for electrical connection with a signal connector, the lead-out signal line is electrically connected to the lead-out portion;
  • a ball grid array electrically connects the corresponding connecting portion and the lead-out portion.
  • the surface of the connection part in contact with the ball grid array is higher than the surface of the quantum chip.
  • the surface of the connection portion in contact with the ball grid array is a flat plane or an arc-shaped convex surface.
  • the signal transmission element is located on the first surface of the quantum chip
  • the connection part is located on the second surface of the quantum chip opposite to the first surface
  • the first A through hole is formed between the surface and the second surface
  • a superconducting metal for electrically connecting the connection part and the signal transmission element is formed in the through hole.
  • the through hole runs through the connection part.
  • connection part is made of titanium nitride.
  • the quantum chip includes:
  • a first substrate, the first substrate is formed with a first part of the signal transmission element, and a coupled qubit and a read resonant cavity, the first part is coupled with the qubit or the read resonant cavity connect;
  • a superconducting element electrically connects the first portion with the second portion.
  • the superconducting element is indium.
  • the second substrate is flip-chip on the packaging substrate, and the first substrate is flip-chip on the second substrate.
  • each packaging substrate there are multiple packaging substrates, the multiple packaging substrates are stacked, and the lead-out portion of each packaging substrate is electrically connected to the corresponding connecting portion.
  • Another embodiment of the present application provides a method for preparing a quantum device, including:
  • a quantum chip is provided, and a signal transmission element and a connection portion electrically connected to the signal transmission element are formed on the quantum chip;
  • the packaging substrate is formed with a lead-out part, and a lead-out signal line for connecting with a signal connector, the lead-out signal line is electrically connected to the lead-out part;
  • a ball grid array is formed to electrically connect the connecting portion and the corresponding lead-out portion.
  • the third embodiment of the present application provides an electronic device, including:
  • the quantum device includes a quantum chip, a packaging substrate and a ball grid array.
  • the quantum chip is formed with a signal transmission element and a connection portion electrically connected to the signal transmission element
  • the packaging substrate is formed with a lead. part and the lead-out signal line for electrical connection with the signal connector, and the lead-out signal line is electrically connected with the lead-out part
  • the ball grid array electrically connects the connection part corresponding to the signal transmission property with the lead-out part, thereby realizing
  • the quantum chip is electrically connected to the outgoing signal line, and then the connecting part is electrically connected to the external signal connector.
  • the ball grid array will not produce complicated field effects, and the ball grid array is used to electrically connect the corresponding The connection part and the lead-out part can avoid field effect interference introduced by bonding aluminum wires.
  • Fig. 1 (a) is the schematic structural diagram of a kind of quantum chip in the prior art
  • Fig. 1 (b) is the schematic diagram that is used for the transmission line that the signal port is drawn out and quantum chip bonding connection;
  • FIG. 2 is a schematic structural view of a packaging substrate 2 according to an embodiment of the present application
  • Fig. 3 is a schematic structural diagram of a quantum device according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a quantum device according to another embodiment of the present application.
  • FIG. 5 is a schematic structural view of the first substrate 17 and the second substrate 18 of a quantum chip according to an embodiment of the present application;
  • Fig. 6 is a schematic flowchart of steps of a method for preparing a quantum device in an embodiment of the present application.
  • a layer (or film), region, pattern or structure when referred to as being "on" a substrate, layer (or film), region and/or pattern, it can be directly on another layer or on the substrate, and/or there may also be intervening layers. Further, it will be understood that when a layer is referred to as being 'under' another layer, it can be directly under, and/or one or more intervening layers may also be present. In addition, designations regarding 'on' and 'under' each layer may be made based on drawings.
  • Fig. 1(a) is a schematic structural diagram of a quantum chip in the prior art
  • Fig. 1(b) is a schematic diagram of a bonding connection between a transmission line leading out of a signal port and a quantum chip.
  • Quantum computing is a new type of computing mode that follows the laws of quantum mechanics to control quantum information units for calculation.
  • the most basic principle of quantum computing is the principle of quantum mechanical state superposition.
  • the principle of quantum mechanical state superposition makes the state of quantum information units can be It is in a superposition state of multiple possibilities, so that quantum information processing has greater potential in terms of efficiency than classical information processing.
  • a quantum chip is a processor that performs quantum calculations in a quantum computer, and the qubit structure contained in the quantum chip is the processing unit of the processor.
  • the quantum chip 1 is integrated with a plurality of one-to-one corresponding and mutually coupled qubits 10 and read resonant cavities 11, and the end of each read resonant cavity 11 away from the corresponding qubit is connected to the read readout integrated on the quantum chip.
  • the transmission line 14, the reading transmission line 14 is used to receive the detection signal and transmit the feedback signal of the detection signal; each qubit 10 is coupled with an XY transmission line 12 and a Z transmission line 13 .
  • the XY transmission line 12 is used to receive the quantum state control signal, and the Z transmission line 13 is used to receive the magnetic flux control signal.
  • the magnetic flux control signal includes a bias voltage signal and/or a pulse bias control signal, and the bias voltage signal and the pulse bias signal
  • the regulation signal can regulate the frequency of the qubit.
  • the reading transmission line 14 is used to receive the reading detection signal and transmit the reading feedback signal. Specifically, a carrier frequency pulse signal is applied through the reading transmission line 14, which is usually called a reading detection signal.
  • the reading detection signal is usually a frequency of 4 -8GHz microwave signal, and determine the quantum state of the qubit by analyzing the read feedback signal output by the read transmission line 14.
  • the XY transmission line 12, the Z transmission line 13 and the read transmission line 14 have signal ports for inputting signals on the external transmission line and/or outputting the signal on the quantum chip to the external transmission line, schematically, as shown in the connection in Figure 1 part 15, it should be noted that the structures of other functional elements except the connecting part 15 are not shown in Fig. 1(b).
  • the transmission line is electrically connected to the signal port on the quantum chip 1 through a bonded aluminum wire (wire bonding), the aluminum wire increases the inductance on the signal transmission path, etc., which affects the transmission of the signal.
  • the number of signal ports on the quantum chip 1 is also increasing, and the number of aluminum wires in the structure connecting the transmission line and the quantum chip is doubled, and each aluminum wire will bring impedance and inductive reactance. Furthermore, complex field effects are introduced, which cause unpredictable interference to the transmission signal on the quantum chip 1, resulting in a large deviation between the signal transmission mode of the quantum chip during actual operation and the expected signal transmission mode.
  • the embodiment of the present application proposes a quantum device, a preparation method of a quantum device, and an electronic device to solve the complex field effect introduced by connecting the quantum chip and the external transmission line through an aluminum wire in the prior art.
  • the problem of unpredictable interference caused by signal transmission on the chip is a problem of unpredictable interference caused by signal transmission on the chip.
  • FIG. 2 is a schematic structural diagram of a packaging substrate 2 according to an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a quantum device according to an embodiment of the present application.
  • a quantum device proposed in the embodiment of the present application includes:
  • Quantum chip 1 a signal transmission element is formed on the quantum chip 1, and a connection portion 15 electrically connected to the signal transmission element;
  • the quantum chip 1 is a superconducting quantum chip, and the signal transmission element Including at least one of the following: an XY transmission line 12 coupled with the qubit 10 on the superconducting quantum chip, a Z transmission line 13 coupled with the qubit 10 on the superconducting quantum chip, and a readout line 13 coupled with the qubit 10 on the superconducting quantum chip
  • the resonant cavity 11 is coupled to the reading transmission line 14, and the connecting part 15 is a metal pattern formed on the quantum chip by coating and deposition.
  • Each XY transmission line 12, each Z transmission line 13, and each reading transmission line 14 are Electrically connected with the corresponding connecting portion 15;
  • the packaging substrate 2 is formed with a lead-out portion 21 and a lead-out signal line 22 for electrical connection with a signal connector.
  • the lead-out signal line 22 is electrically connected to the lead-out portion 21, and is implemented in this application.
  • the packaging substrate 2 may be a PCB (Printed Circuit Board, printed circuit board); and
  • the ball grid array 3 electrically connects the connection part 15 corresponding to the signal transmission property and the lead part 21, thereby realizing the quantum chip 1 and the lead signal line 22. , and then lead the connection part 15 to the external signal connector through the lead-out signal line 22 (the signal connector connected to the connector joint 23 is not shown in Figure 1), compared to the aluminum in the prior art Wire connection, in the embodiment of the present application, the ball grid array 3 will not produce complex field effects, and the use of the ball grid array 3 to electrically connect the corresponding connecting portion 15 and the lead-out portion 21 can avoid the introduction of complicated problems caused by bonding aluminum wires.
  • the corresponding signal transmission property means that the signal transmitted by the connection part 15 and the lead-out part 21 electrically connected to the ball grid array 3 is the same for the quantum chip.
  • the connection part 15 is used to access For the quantum state control signal
  • the lead-out part 21 corresponding to the signal transmission property of the connection part 15 is used to transmit the quantum state control signal.
  • FIG. 4 is a schematic structural diagram of a quantum device according to another embodiment of the present application, wherein the structures of other functional elements except the connecting portion 15 and the through hole 16 are not shown in FIG. 4 .
  • the surface of the connection part 15 in contact with the ball grid array 3 is higher than the surface of the quantum chip 1, that is, the connection part 15 is away from
  • the surface of one side of the quantum chip 1 protrudes outward relative to the surface of the quantum chip 1 where the connecting portion 15 is located, so as to avoid welding when the surface of the connecting portion 15 in contact with the ball grid array 3 is concave
  • the problem of voids, specifically, the concave surface is not easy to discharge air when soldering with solder balls, etc., and then gathers to form soldering voids.
  • the surface of the connecting portion 15 in contact with the ball grid array 3 is a flat plane or an arc-shaped convex surface.
  • the signal transmission element is located on the first surface of the quantum chip 1 (see the upper surface of the quantum chip in FIG. 4 ), and the connecting part 15 is located at the same The second surface of the quantum chip 1 opposite to the first surface (see the lower surface of the quantum chip in FIG. 4 ), and a perforation 16 is formed between the first surface and the second surface, the The superconducting metal used to electrically connect the connection part 15 and the signal transmission element is formed in the through hole 16, that is, the connection part 15 and the signal transmission element of the quantum chip 1 and other functional elements are located on different surfaces of the quantum chip.
  • the soldering structure of the ball grid array 3 has little influence on other functional elements such as signal transmission elements on the quantum chip 1 .
  • the superconducting metal inside the through hole 16 may be a superconducting metal layer attached to the inner wall of the through hole 16 , or a superconducting metal column completely filling the through hole 16 .
  • the perforation 16 runs through the connecting portion 15, the superconducting metal is a superconducting metal layer attached to the inner wall of the perforation 16, and the superconducting metal layer in the perforation 16 forms an air discharge channel to facilitate solder balls The air is discharged during soldering, so as to avoid soldering voids formed due to the accumulation of air on the soldering contact surface between the solder ball and the connecting portion 15 and the inability to be discharged.
  • the connecting portion 15 is made of titanium nitride material.
  • the connecting portion 15 is a titanium nitride pad formed on the surface of the quantum chip 1. Titanium nitride is easy to adhere without the need for an intermediate metal. It is electrically connected to the solder balls of the BGA process.
  • FIG. 5 is a schematic structural diagram of a first substrate 17 and a second substrate 18 of a quantum chip according to an embodiment of the present application.
  • the quantum chip 1 includes:
  • the first substrate 17, the first part of the signal transmission element is formed on the first substrate 17, and the coupled qubit 10 and the read resonant cavity 11, the first part and the qubit 10 or the The reading resonant cavity 11 is coupled and connected; in the embodiment of the present application, the first part of the signal transmission element can be exemplarily: the first part of the XY transmission line 121, the first part of the Z transmission line 131, and the first part of the reading transmission line 141;
  • the second substrate 18, the second part of the signal transmission element is formed on the second substrate 18, in the embodiment of the present application, the second part of the signal transmission element can be exemplarily: the second part XY transmission line 122, second section Z transmission line 132, second section read transmission line 142; and
  • the superconducting element electrically connects the first part and the second part, for example, the superconducting element electrically connects the first part of the XY transmission line 121 and the second part of the XY transmission line 122, the The superconducting element electrically connects the first portion of the Z transmission line 131 with the second portion of the Z transmission line 132 , and the superconducting element electrically connects the first portion of the read transmission line 141 with the second portion of the read transmission line 142 .
  • some embodiments of the present application divide the signal transmission element into different parts and arrange them on different substrates respectively.
  • the first part of the signal transmission element When a part is connected with the second part of the signal transmission element, the complete graphic structure of the signal transmission element is formed.
  • This structural arrangement allows more space for the substrate used to prepare qubits to be used for preparing qubit graphic structures, thereby facilitating the expansion of the number of qubits.
  • the superconducting element is a structure formed of any superconducting material, for example, the superconducting element is an indium column.
  • the second substrate 18 is flip-chip on the packaging substrate 2
  • the first substrate 17 is flip-chip on the second substrate 18, and the pattern structure of the connection part 15 and the qubit 1
  • the signal transmission element can be led out to the packaging substrate 2 by means of flip-chip soldering using solder balls.
  • the lead-out portion 21 of each packaging substrate 2 is connected to the corresponding connecting portion 15 Electrical connection, considering that the number of qubits is large, the number of signal connectors that need to be connected to the package is large, and the joints of the signal connectors (for example, SMA joints or SMP joints) are usually large in size and need to occupy a certain area.
  • the lead-out parts 21 of multiple packaging substrates 2 are electrically connected to the corresponding connecting parts 15 , so that the external signal connectors are distributed to multiple packaging substrates 2 and connected to the connector joints 23 .
  • FIG. 6 is a schematic flowchart of a method for preparing a quantum device in an embodiment of the present application.
  • a method for preparing a quantum device proposed in the embodiment of the present application includes:
  • a quantum chip 1 is provided, on which a signal transmission element and a connection portion 15 electrically connected to the signal transmission element are formed;
  • the quantum chip 1 is a superconducting quantum chip, and the signal transmission element Including at least one of the following: an XY transmission line 12 coupled with the qubit 10 on the superconducting quantum chip, a Z transmission line 13 coupled with the qubit 10 on the superconducting quantum chip, and a readout line 13 coupled with the qubit 10 on the superconducting quantum chip
  • the reading transmission line 14 coupled to the resonant cavity 11;
  • a packaging substrate 2 is provided, on which a lead-out portion 21 is formed, and a lead-out signal line 22 for connecting to a signal connector is provided, and the lead-out signal line 22 is electrically connected to the lead-out portion 21, which is implemented in this application
  • the packaging substrate 2 may be a PCB (Printed Circuit Board, printed circuit board);
  • a ball grid array 3 is formed to electrically connect the connecting portion 15 and the corresponding lead-out portion 21. It can be understood that, in a quantum device including a superconducting quantum chip, the ball grid array 3 may include a superconducting material such as tin. A plurality of solder balls formed of different materials, that is, a plurality of solder balls are used to electrically connect the corresponding connecting portion 15 and the lead-out portion 21 .
  • the quantum chip 1 is flip-chip mounted on the package substrate 2 , and the connection portion 15 is electrically connected to the corresponding lead-out portion 21 by using the formed ball grid array 3 .
  • the quantum chip 1 is mounted on the packaging substrate 2, and the connection part 15 is electrically connected to the corresponding lead-out part 21 by using the formed ball grid array 3.
  • the quantum chip 1 The signal transmission element is formed on the first surface of the quantum chip 1, and the connection part 15 is formed on the second surface of the quantum chip 1 opposite to the first surface, and then on the first surface and the second A through hole 16 is formed between the two surfaces, and a superconducting metal for electrically connecting the connection part 15 and the signal transmission element is formed in the through hole 16 .
  • the superconducting metal inside the through hole 16 may be a superconducting metal layer attached to the inner wall of the through hole 16 , or may be a superconducting metal column completely filling the through hole 16 .
  • the perforation 16 runs through the connecting portion 15, the superconducting metal is a superconducting metal layer attached to the inner wall of the perforation 16, and the superconducting metal layer in the perforation 16 forms an air discharge channel to facilitate tin Air is discharged during soldering of balls, etc., so as to avoid soldering voids formed due to air gathering on the soldering contact surface between the solder ball and the connection portion 15 and being unable to be discharged.
  • the connecting portion 15 is made of titanium nitride.
  • the connecting portion 15 is a titanium nitride pad formed on the surface of the quantum chip 1. Titanium nitride is easy to adhere without the use of an intermediate metal. It can be electrically connected with the solder balls of the BGA process.
  • the provided quantum chip 1 includes:
  • the first substrate 17, the first part of the signal transmission element is formed on the first substrate 17, and the coupled qubit 10 and the read resonant cavity 11, the first part and the qubit 10 or the The reading resonant cavity 11 is coupled and connected; in the embodiment of the present application, the first part of the signal transmission element can be exemplarily: the first part of the XY transmission line 121, the first part of the Z transmission line 131, and the first part of the reading transmission line 141;
  • the second substrate 18, the second part of the signal transmission element is formed on the second substrate 18, in the embodiment of the present application, the second part of the signal transmission element can be exemplarily: the second part XY transmission line 122, second section Z transmission line 132, second section read transmission line 142; and
  • the superconducting element electrically connects the first part and the second part, for example, the superconducting element electrically connects the first part of the XY transmission line 121 and the second part of the XY transmission line 122, the The superconducting element electrically connects the first portion of the Z transmission line 131 with the second portion of the Z transmission line 132 , and the superconducting element electrically connects the first portion of the read transmission line 141 with the second portion of the read transmission line 142 .
  • the ball grid array 3 connects the connecting part 15 corresponding to the signal transmission property with the lead-out part 21, thereby realizing the connection between the quantum chip 1 and the lead-out part.
  • the electrical connection of the signal line 22, and then lead the connecting portion 15 to an external signal connector since the ball grid array 3 will not produce complicated field effects, therefore, the ball grid array 3 is used to electrically connect the quantum chip 1 when it is packaged.
  • the corresponding connection portion 15 and the lead-out portion 21 can avoid interference introduced by bonding aluminum wires.
  • An electronic device is also provided in the embodiment of the present application, including: a package assembly; a signal connector, the signal connector is mounted on the package assembly; and the quantum device in the above embodiment, the quantum device Located in the package assembly, and the outgoing signal line 22 is electrically connected to the signal connector.
  • the outgoing signal line 22 is electrically connected to the signal connector through a connector joint 23.
  • the packaging component may be a packaging box, or other structural components that can isolate the quantum device from the external environment.

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Abstract

一种量子器件及其制备方法和一种电子器件。其中，量子器件包括：量子芯片，所述量子芯片上形成有信号传输元件，及与所述信号传输元件电连接的连接部；封装基板，所述封装基板上形成有引出部，及用于与信号连接器电连接的引出信号线，引出信号线与引出部电连接；以及球栅阵列，所述球栅阵列将相对应的所述连接部和所述引出部电连接。球栅阵列将信号传输属性相对应的连接部和引出部电连接，从而实现了量子芯片与传输线的电连接，进而将所述连接部引出至外部的信号连接器，本申请中球栅阵列不会产生复杂的场效应，利用球栅阵列电连接对应的所述连接部和所述引出部能够避免产生键合铝线所引入的干扰。

Description

一种量子器件及其制备方法和一种电子器件
本申请要求于2021年6月28日提交中国专利局、申请号为202110718555.X、发明名称为“一种量子器件及其制备方法和一种电子器件”的中国专利申请的优先权，并且，要求于2021年6月28日提交中国专利局、申请号为202121464017.4、发明名称为“一种量子器件和一种电子器件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于量子信息领域，尤其是量子计算技术领域，特别地，本申请涉及一种量子器件及其制备方法和一种电子器件。
背景技术
承载量子比特的量子芯片需要稳定的工作环境，因此，为了减少外界环境对量子芯片的影响，通常需要将量子芯片先封装，然后在低温下运行量子芯片。封装时，需要将量子芯片的信号端口与设于量子芯片外的传输线路电连接，该传输线路用于将信号端口引出进而实现信号的输入和输出，因此，信号端口与该传输线路的电连接性能直接影响了信号传输，进而影响量子芯片的运行。
现有技术中，通常采用铝线键合(wire bonding)将信号端口与上述传输线路电连接。然而，随着量子比特数量的增加，量子芯片上信号端口的数量也越来越多，铝线键合连接信号端口和上述传输线路的方式使得铝线的数量成倍的增加，每根铝线都会带来阻抗感抗，进而引入复杂的场效应，这种复杂的场效应对量子芯片上的传输信号产生不可预知的干扰。
发明内容
本申请的目的是提供一种量子器件及其制备方法和一种电子器件，以解决现有技术中的铝线连接量子芯片与外部传输线路引入复杂的场效应，对量子芯片上的传输信号产生不可预知的干扰的问题。
本申请的一个实施例提供了一种量子器件，包括：
量子芯片，所述量子芯片上形成有信号传输元件，及与所述信号传输元件电连接的连接部；
封装基板，所述封装基板上形成有引出部，及用于与信号连接器电连接的引出信号线，所述引出信号线与所述引出部电连接；以及
球栅阵列，所述球栅阵列将相对应的所述连接部和所述引出部电连接。
如上所述的量子器件，所述连接部与所述球栅阵列接触的表面高于所述量子芯片的表面。
如上所述的量子器件，所述连接部与所述球栅阵列接触的表面为平整平面或弧形凸面。
如上所述的量子器件，所述信号传输元件位于所述量子芯片的第一表面，所述连接部位于与所述第一表面相背的所述量子芯片的第二表面，且所述第一表面和所述第二表面之间形成有穿孔，所述穿孔内形成有用于电连接所述连接部和所述信号传输元件的超导金属。
如上所述的量子器件，所述穿孔贯穿所述连接部。
如上所述的量子器件，所述连接部为氮化钛。
如上所述的量子器件，所述量子芯片包括：
第一基底，所述第一基底上形成有所述信号传输元件的第一部分，以及耦合连接的量子比特和读取谐振腔，所述第一部分与所述量子比特或所述读取谐振腔耦合连接；
第二基底，所述第二基底上形成有所述信号传输元件的第二部分；
超导元件，所述超导元件将所述第一部分与所述第二部分电连接。
如上所述的量子器件，所述超导元件为铟。
如上所述的量子器件，所述第二基底倒装于所述封装基板，所述第一基底倒装于所述第二基底。
如上所述的量子器件，所述封装基板为多个，多个所述封装基板层叠设置，且每个所述封装基板的所述引出部与对应的所述连接部电连接。
本申请的另一个实施例提供了一种量子器件的制备方法，包括：
提供量子芯片，所述量子芯片上形成有信号传输元件及与所述信号传输元件电连接的连接部；
提供封装基板，所述封装基板上形成有引出部，及用于与信号连接器连接的引出信号线，所述引出信号线与所述引出部电连接；以及
形成球栅阵列以将所述连接部和对应的所述引出部电连接。
本申请的第三个实施例提供了一种电子器件，包括：
封装组件；信号连接器，所述信号连接器安装于所述封装组件；以及如上所述的量子器件，所述量子器件位于所述封装组件内，且所述引出信号线与所述信号连接器电连接。
与现有技术相比，本申请提供的量子器件，包括量子芯片、封装基板和球栅阵列，量子芯片上形成有信号传输元件及与信号传输元件电连接的连接部，封装基板上形成有引出部及用于与信号连接器电连接的引出信号线，且引出信号线与引出部电连接，球栅阵列将信号传输属性相对应的所述连接部和所述引出部电连接，从而实现了量子芯片与引出信号线的电连接，进而将所述连接部引出与外部的信号连接器电连接，本申请中球栅阵列不会产生复杂的场效应，利用球栅阵列电连接对应的所述连接部和所述引出部能够避免产生键合铝线所引入的场效应干扰。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1(a)为现有技术中的一种量子芯片的结构示意图，图1(b)为用于将信号端口引出的传输线路与量子芯片键合连接的示意图；
图2为本申请一个实施例的封装基板2的结构示意图
图3为本申请一个实施例的量子器件的结构示意图；
图4为本申请另一个实施例的量子器件的结构示意图；
图5为本申请一个实施例的量子芯片的第一基底17和第二基底18的结构示意图；
图6为本申请一个实施例中量子器件的制备方法的步骤流程示意图。
附图标记说明：
1-量子芯片，10-量子比特，11-读取谐振腔，12-XY传输线，13-Z传输线，14-读取传输线，15-连接部，16-穿孔；
17-第一基底，18-第二基底，121-第一部分XY传输线，122-第二部分XY传输线，131-第一部分Z传输线，132-第二部分Z传输线，141-第一部分读取传输线，142-第二部分读取传输线；
2-封装基板，21-引出部，22-引出信号线，23-连接器接头；
3-球栅阵列。
具体实施方式
下面通过参考附图描述的实施例是示例性的，仅用于解释本申请，而不能解释为对本申请的限制。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合相互引用。
需要说明的是，本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
另外，应该理解的是，当层(或膜)、区域、图案或结构被称作在衬底、层(或膜)、 区域和/或图案“上”时，它可以直接位于另一个层或衬底上，和/或还可以存在插入层。另外，应该理解，当层被称作在另一个层“下”时，它可以直接位于另一个层下，和/或还可以存在一个或多个插入层。另外，可以基于附图进行关于在各层“上”和“下”的指代。
图1(a)为现有技术中的一种量子芯片的结构示意图，图1(b)为用于将信号端口引出的传输线路与量子芯片键合连接的示意图。
量子计算是一种遵循量子力学规律调控量子信息单元进行计算的新型计算模式，其中，量子计算基于的最基本的一个原理为量子力学态叠加原理，量子力学态叠加原理使得量子信息单元的状态可以处于多种可能性的叠加状态，从而使得量子信息处理从效率上相比于经典信息处理具有更大潜力。量子芯片是量子计算机中执行量子计算的处理器，量子芯片包含的量子比特结构为处理器的处理单元。
量子芯片1上集成有多个一一对应的且相互耦合的量子比特10和读取谐振腔11，各读取谐振腔11远离对应量子比特的一端均连接至集成设置在量子芯片上的读取传输线14，读取传输线14用于接收探测信号和发射探测信号的反馈信号；各量子比特10均耦合连接有XY传输线12和Z传输线13。XY传输线12用于接收量子态调控信号，Z传输线13用于接收磁通量调控信号，磁通量调控信号包括偏置电压信号和/或脉冲偏置调控信号，所述偏置电压信号和所述脉冲偏置调控信号均可以对所述量子比特的频率进行调控。读取传输线14用于接收读取探测信号和发射读取反馈信号，具体的，通过读取传输线14施加载频脉冲信号，通常称之为读取探测信号，读取探测信号通常是频率为4-8GHz的微波信号，并通过解析读取传输线14输出的读取反馈信号确定量子比特所处于的量子态。
XY传输线12、Z传输线13和读取传输线14具有用于将外部传输线路上的信号输入和/或将量子芯片上的信号输出至外部传输线路的信号端口，示意性的，如图1中的连接部15，需要说明的是，图1(b)中除了连接部15以外的其他功能元件的结构未示意出。该传输线路通过键合铝线(绑定线，wire bonding)与量子芯片1上信号端口电连接时，铝线增加了信号传输路径上的电感等，影响了信号的传输，随着量子比特数量的增加，量子芯片1上信号端口的数量也越来越多，铝线键合连接该传输线路和量子芯片的结构中铝线的数量成倍增加，每根铝线都会带来阻抗感抗，进而引入了复杂的场效应，这种复杂的场效应对量子芯片1上的传输信号产生难以预知的干扰，导致量子芯片实际运行时的信号传输模式与预期的信号传输模式偏离较大。
本申请的实施例提出一种量子器件、一种量子器件的制备方法以及一种电子器件，以解决现有技术中通过铝线连接量子芯片和外部传输线路的方式引入复杂的场效应，对量子芯片上的信号传输产生不可预知的干扰的问题。
图2为本申请一个实施例的封装基板2的结构示意图，图3为本申请一个实施例的量子器件的结构示意图。
结合图2和图3所示，本申请实施例提出的一种量子器件，包括：
量子芯片1，所述量子芯片1上形成有信号传输元件，及与所述信号传输元件电连接的连接部15；示例性的，所述量子芯片1为超导量子芯片，所述信号传输元件至 少包括以下之一：与超导量子芯片上的量子比特10耦合连接的XY传输线12，与超导量子芯片上的量子比特10耦合连接的Z传输线13，及与超导量子芯片上的读取谐振腔11耦合连接的读取传输线14，所述连接部15为通过镀膜、沉积方式在量子芯片上形成的金属图形，每条XY传输线12、每条Z传输线13、每条读取传输线14均与对应的连接部15电连接；
封装基板2，所述封装基板2上形成有引出部21，及用于与信号连接器电连接的引出信号线22，所述引出信号线22与所述引出部21电连接，在本申请实施例中，封装基板2可以是PCB板(Printed Circuit Board，印刷电路板)；以及
球栅阵列3，所述球栅阵列3将相对应的所述连接部15和所述引出部21电连接，可以理解的是，在包括超导量子芯片的量子器件中，球栅阵列3可以包括采用锡等超导材料形成的多个锡球，即利用多个锡球将相对应的所述连接部15和所述引出部21电连接。
与现有技术相比，本申请实施例提供的量子器件中，球栅阵列3将信号传输属性相对应的连接部15和引出部电21电连接，从而实现了量子芯片1与引出信号线22的电连接，进而将所述连接部15通过引出信号线22引出至外部的信号连接器(图1中与连接器接头23连接的信号连接器未示意出)，相对于现有技术中的铝线连接，本申请实施例中球栅阵列3不会产生复杂的场效应，利用球栅阵列3电连接对应的所述连接部15和所述引出部21能够避免产生键合铝线引入复杂的场效应，也即避免了复杂场效应对量子芯片信号传输的干扰。需要说明的是，信号传输属性相对应是指球栅阵列3电连接的连接部15和引出部电21传输的信号对量子芯片而言是相同的，例如，若连接部15是用于接入量子态调控信号，与该连接部15信号传输属性相对应的引出部电21则是用于传输量子态调控信号。
图4为本申请另一个实施例的量子器件的结构示意图，其中，图4中除了连接部15和穿孔16以外的其他功能元件的结构未示意出。
结合图3和图4所示，在本申请的一些实施例中，所述连接部15与所述球栅阵列3接触的表面高于所述量子芯片1的表面，即所述连接部15背离所述量子芯片1的一侧的表面相对于所述连接部15所在的量子芯片1的表面向外突出，以避免连接部15与所述球栅阵列3接触的表面为凹陷状时产生的焊接空洞问题，具体的，凹陷状的表面在利用锡球等焊接时空气不易排出，进而聚集形成焊接空洞。在具体实施的一个实施例中，所述连接部15与所述球栅阵列3接触的表面为平整平面或弧形凸面。
结合图4所示，在本申请的另一些实施例中，所述信号传输元件位于所述量子芯片1的第一表面(参见图4中量子芯片的上表面)，所述连接部15位于与所述第一表面相背的所述量子芯片1的第二表面(参见图4中量子芯片的下表面)，且所述第一表面和所述第二表面之间形成有穿孔16，所述穿孔16内形成有用于电连接所述连接部15和所述信号传输元件的超导金属，即连接部15与量子芯片1的信号传输元件等其他功能元件的图形位于量子芯片的不同表面的结构形式，这种结构形式中球栅阵列3的焊接结构对量子芯片1上的信号传输元件等其他功能元件产生的影响较小。示例性的，位于穿孔16内的超导金属可以是附着在穿孔16的内壁的超导金属层，也可 以是完全填充满穿孔16的超导金属柱。
示例性的，所述穿孔16贯穿所述连接部15，所述超导金属为附着在穿孔16的内壁的超导金属层，穿孔16内的超导金属层形成空气排出通道有助于锡球等焊接时排出空气，避免由于空气聚集在锡球与连接部15的焊接接触面无法排出而形成的焊接空洞。
示例性的，所述连接部15为氮化钛材质，例如，所述连接部15为在量子芯片1的表面形成的氮化钛焊盘，氮化钛易于粘附，无须借助中间金属即可与BGA工艺的锡球等电连接。
图5为本申请一个实施例的量子芯片的第一基底17和第二基底18的结构示意图。
结合图5所示，在本申请的一些实施例中，所述量子芯片1包括：
第一基底17，所述第一基底17上形成有所述信号传输元件的第一部分，以及耦合连接的量子比特10和读取谐振腔11，所述第一部分与所述量子比特10或所述读取谐振腔11耦合连接；在本申请实施例中，所述信号传输元件的第一部分示例性的可以是：第一部分XY传输线121，第一部分Z传输线131，第一部分读取传输线141；
第二基底18，所述第二基底18上形成有所述信号传输元件的第二部分，在本申请实施例中，所述信号传输元件的第二部分示例性的可以是：第二部分XY传输线122，第二部分Z传输线132，第二部分读取传输线142；以及
超导元件，所述超导元件将所述第一部分与所述第二部分电连接，示例性的，所述超导元件将第一部分XY传输线121与第二部分XY传输线122电连接，所述超导元件将第一部分Z传输线131与第二部分Z传输线132电连接，以及所述超导元件将第一部分读取传输线141与第二部分读取传输线142电连接。
为了避免量子芯片上错综复杂的布线占据的空间影响量子比特数量的扩展，本申请的一些实施例将所述信号传输元件分割成不同部分并分别设在不同的基底上，所述信号传输元件的第一部分与所述信号传输元件的第二部分连接时即构成完整的信号传输元件的图形结构。这种结构布置方式使得用于制备量子比特的基底则可以留出更多空间用于制备量子比特图形结构，从而便于对量子比特数量进行扩展。具体实施时，所述超导元件为任一超导材料形成的结构，示例性的，所述超导元件为铟柱。
在本申请的一些实施例中，所述第二基底18倒装于所述封装基板2，所述第一基底17倒装于所述第二基底18，连接部15和量子比特1的图形结构位于不同基底时，采用倒装焊接的方式即可利用锡球将信号传输元件引出至封装基板2。
在本申请的一些实施例中，所述封装基板2为多个，多个所述封装基板2层叠设置，且每个所述封装基板2的所述引出部21与对应的所述连接部15电连接，考虑到量子比特的数量较大时，封装所需连接的信号连接器的数量较大，而信号连接器的接头(例如，SMA接头或SMP接头)通常尺寸较大，需占据一定的空间，此时通过多个封装基板2的所述引出部21与对应的所述连接部15电连接，便于外部信号连接器分散到多个封装基板2上与连接器接头23连接。
图6为本申请一个实施例中量子器件的制备方法的流程示意图。
结合图6所示，本申请实施例提出的一种量子器件的制备方法，包括：
提供量子芯片1，所述量子芯片1上形成有信号传输元件及与所述信号传输元件电连接的连接部15；示例性的，所述量子芯片1为超导量子芯片，所述信号传输元件至少包括以下之一：与超导量子芯片上的量子比特10耦合连接的XY传输线12，与超导量子芯片上的量子比特10耦合连接的Z传输线13，及与超导量子芯片上的读取谐振腔11耦合连接的读取传输线14；
提供封装基板2，所述封装基板2上形成有引出部21，及用于与信号连接器连接的引出信号线22，所述引出信号线22与所述引出部21电连接，在本申请实施例中，封装基板2可以是PCB板(Printed Circuit Board，印刷电路板)；以及
形成球栅阵列3以将所述连接部15和对应的所述引出部21电连接，可以理解的是，在包括超导量子芯片的量子器件中，球栅阵列3可以包括采用锡等超导材料形成的多个锡球，即利用多个锡球将相对应的所述连接部15和所述引出部21电连接。
在本申请的一个实施例中，量子芯片1倒装于封装基板2，利用形成的球栅阵列3将所述连接部15和对应的所述引出部21电连接。
在本申请的另一个实施例中，量子芯片1正装于封装基板2，利用形成的球栅阵列3将所述连接部15和对应的所述引出部21电连接，具体的，在量子芯片1的第一表面形成有所述信号传输元件，在与所述第一表面相背的所述量子芯片1的第二表面形成有所述连接部15，然后在所述第一表面和所述第二表面之间形成有穿孔16，并在所述穿孔16内形成用于电连接所述连接部15和所述信号传输元件的超导金属。示例性的，位于穿孔16内的超导金属可以是附着在穿孔16的内壁的超导金属层，也可以是完全填充满穿孔16的超导金属柱。在一个示例中，所述穿孔16贯穿所述连接部15，所述超导金属为附着在穿孔16的内壁的超导金属层，穿孔16内的超导金属层形成空气排出通道有助于锡球等焊接时排出空气，避免由于空气聚集在锡球与连接部15的焊接接触面无法排出而形成的焊接空洞。在另一个示例中，所述连接部15为氮化钛材质，例如，所述连接部15为在量子芯片1的表面形成的氮化钛焊盘，氮化钛易于粘附，无须借助中间金属即可与BGA工艺的锡球等电连接。
在本申请的一些实施例中，为了便于对量子比特数量进行扩展，提供的所述量子芯片1包括：
第一基底17，所述第一基底17上形成有所述信号传输元件的第一部分，以及耦合连接的量子比特10和读取谐振腔11，所述第一部分与所述量子比特10或所述读取谐振腔11耦合连接；在本申请实施例中，所述信号传输元件的第一部分示例性的可以是：第一部分XY传输线121，第一部分Z传输线131，第一部分读取传输线141；
第二基底18，所述第二基底18上形成有所述信号传输元件的第二部分，在本申请实施例中，所述信号传输元件的第二部分示例性的可以是：第二部分XY传输线122，第二部分Z传输线132，第二部分读取传输线142；以及
超导元件，所述超导元件将所述第一部分与所述第二部分电连接，示例性的，所述超导元件将第一部分XY传输线121与第二部分XY传输线122电连接，所述超导元件将第一部分Z传输线131与第二部分Z传输线132电连接，以及所述超导元件将第一部分读取传输线141与第二部分读取传输线142电连接。
与现有技术相比，利用本申请实施例中的制备方法制备的量子器件，球栅阵列3将信号传输属性相对应的连接部15和引出部电21连接，从而实现了量子芯片1与引出信号线22的电连接，进而将所述连接部15引出至外部的信号连接器，由于球栅阵列3不会产生复杂的场效应，因此，在量子芯片1封装时利用球栅阵列3电连接对应的所述连接部15和所述引出部21能够避免产生键合铝线所引入的干扰。
在本申请实施例中还提供了一种电子器件，包括：封装组件；信号连接器，所述信号连接器安装于所述封装组件；以及上述实施例中的所述量子器件，所述量子器件位于所述封装组件内，且所述引出信号线22与所述信号连接器电连接，示例性的，所述引出信号线22通过连接器接头23与所述信号连接器电连接，示例性的，所述封装组件可以是封装盒，或是其他可以将所述量子器件与外部环境隔离的结构组件。
以上依据图式所示的实施例详细说明了本申请的构造、特征及作用效果，以上所述仅为本申请的较佳实施例，但本申请不以图面所示限定实施范围，凡是依照本申请的构想所作的改变，或修改为等同变化的等效实施例，仍未超出说明书与图示所涵盖的精神时，均应在本申请的保护范围内。

Claims (12)

  1. 一种量子器件，其特征在于，包括：
    量子芯片，所述量子芯片上形成有信号传输元件，及与所述信号传输元件电连接的连接部；
    封装基板，所述封装基板上形成有引出部，及用于与信号连接器电连接的引出信号线，所述引出信号线与所述引出部电连接；以及
    球栅阵列，所述球栅阵列将相对应的所述连接部和所述引出部电连接。
  2. 根据权利要求1所述的量子器件，其特征在于，所述连接部与所述球栅阵列接触的表面高于所述量子芯片的表面。
  3. 根据权利要求2所述的量子器件，其特征在于，所述连接部与所述球栅阵列接触的表面为平整平面或弧形凸面。
  4. 根据权利要求1至3任一项所述的量子器件，其特征在于，所述信号传输元件位于所述量子芯片的第一表面，所述连接部位于与所述第一表面相背的所述量子芯片的第二表面，且所述第一表面和所述第二表面之间形成有穿孔，所述穿孔内形成有用于电连接所述连接部和所述信号传输元件的超导金属。
  5. 根据权利要求4所述的量子器件，其特征在于，所述穿孔贯穿所述连接部。
  6. 根据权利要求4所述的量子器件，其特征在于，所述连接部的材质为氮化钛。
  7. 根据权利要求1所述的量子器件，其特征在于，所述量子芯片包括：
    第一基底，所述第一基底上形成有所述信号传输元件的第一部分，以及耦合连接的量子比特和读取谐振腔，所述第一部分与所述量子比特或所述读取谐振腔耦合连接；
    第二基底，所述第二基底上形成有所述信号传输元件的第二部分；
    超导元件，所述超导元件将所述第一部分与所述第二部分电连接。
  8. 根据权利要求7所述的量子器件，其特征在于，所述超导元件为铟。
  9. 根据权利要求7所述的量子器件，其特征在于：所述第二基底倒装于所述封装基板，所述第一基底倒装于所述第二基底。
  10. 根据权利要求1所述的量子器件，其特征在于，所述封装基板为多个，多个所述封装基板层叠设置，且每个所述封装基板的所述引出部与对应的所述连接部电连接。
  11. 一种量子器件的制备方法，其特征在于，包括：
    提供量子芯片，所述量子芯片上形成有信号传输元件及与所述信号传输元件电连接的连接部；
    提供封装基板，所述封装基板上形成有引出部，及用于与信号连接器连接的引出信号线，所述引出信号线与所述引出部电连接；以及
    形成球栅阵列以将所述连接部和对应的所述引出部电连接。
  12. 一种电子器件，其特征在于，包括：
    封装组件；
    信号连接器，所述信号连接器安装于所述封装组件；以及
    根据权利要求1-10中任意一项所述的量子器件，所述量子器件位于所述封装组件内，且所述引出信号线与所述信号连接器电连接。
PCT/CN2022/101569 2021-06-28 2022-06-27 一种量子器件及其制备方法和一种电子器件 WO2023274158A1 (zh)

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