WO2023273097A1 - Parallel array led chip suitable for visible light communication, and manufacturing method therefor - Google Patents

Parallel array led chip suitable for visible light communication, and manufacturing method therefor Download PDF

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Publication number
WO2023273097A1
WO2023273097A1 PCT/CN2021/130187 CN2021130187W WO2023273097A1 WO 2023273097 A1 WO2023273097 A1 WO 2023273097A1 CN 2021130187 W CN2021130187 W CN 2021130187W WO 2023273097 A1 WO2023273097 A1 WO 2023273097A1
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layer
electrode
led chip
columnar
emitting active
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PCT/CN2021/130187
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French (fr)
Chinese (zh)
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李国强
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河源市众拓光电科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/642—Heat extraction or cooling elements characterized by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0075—Processes relating to semiconductor body packages relating to heat extraction or cooling elements

Definitions

  • the invention belongs to the technical field of visible light communication, and in particular relates to a parallel array LED chip suitable for visible light communication and a preparation method thereof.
  • VLC Visible light communication
  • LED In visible light communication, LED is an ideal light source due to its short response time and high-speed modulation.
  • visible light communication technology has high requirements on the light source. It not only needs a large enough modulation bandwidth to meet high-speed communication, but also needs sufficient power and light efficiency to meet its lighting needs.
  • the embedded electrode vertical structure has excellent photoelectric performance due to its excellent current expansion capability. On this basis, it is of great significance to prepare high-bandwidth array LED chips to meet the needs of dual-purpose LED chips for general lighting.
  • one of the purposes of the present invention is to provide a parallel array LED chip suitable for visible light communication, which reduces the junction capacitance of the chip, thereby reducing the RC time constant, and obtaining a high bandwidth suitable for visible light communication LED chips.
  • the second object of the present invention is to provide a method for preparing parallel array LED chips suitable for visible light communication.
  • a parallel array LED chip suitable for visible light communication including a conductive substrate, a bonding metal layer, a first insulating layer, a p-contact reflector metal and a protective layer, and a light-emitting active region sequentially connected from bottom to top.
  • the active area includes a P electrode and a plurality of light-emitting active units distributed in an array, and an etching channel is provided between adjacent light-emitting active units.
  • Each light-emitting active unit includes a functional layer and at least one columnar N electrode, so
  • the functional layer includes a p-type GaN layer, an InGaN/GaN multi-quantum well layer and an n-type GaN layer sequentially connected from bottom to top, the columnar N electrode is located inside the functional layer, and the top of the columnar N electrode is connected to the The n-type GaN layer is in ohmic contact, and the bottom of the columnar N electrode passes through the metal of the p-contact mirror and the protective layer, the first insulating layer and the bonding metal layer to form electrical conduction, and the p-electrode and the p-contact mirror The metal and the protection layer are in electrical contact to form electrical conduction.
  • each light-emitting active unit includes 1-4 columnar N electrodes.
  • the N electrode is any one or an alloy of two or more of Ti, Cr, Ag, Au and Pt; the columnar N electrode has a diameter of 5-100 ⁇ m and a height of 1-10 ⁇ m.
  • the P electrode is a rectangular dam structure surrounding the outside of the light-emitting active unit, and the P electrode is any one or an alloy of two or more of Ti, Cr, Ag, Au, and Pt; the The thickness of the P electrode is 1-10 ⁇ m.
  • the light-emitting active region is also provided with a second insulating layer, the second insulating layer covers the outer surface of the P electrode, between the P electrode and the light-emitting active unit, the etching channel and the light-emitting area. The top surface of the active cell.
  • first insulating layer and the second insulating layer are SiO 2 insulating layers with a thickness of 30-300 ⁇ m.
  • the conductive substrate is a conductive silicon substrate with a thickness of 100-600 ⁇ m.
  • the p-contact mirror metal and protective layer include a p-contact mirror metal layer and a protective layer connected to the bottom surface of the p-contact mirror metal layer;
  • the metal layer of the p-contact mirror is composed of Ag and/or Ni, and the thickness of the metal layer of the p-contact mirror is 50-5000nm;
  • the protection layer is a TiW layer, and the thickness of the protection layer is 50-300nm.
  • the bonding metal layer is any one or an alloy of two or more of Ni, Au, Sn, Ti, and the thickness of the bonding metal layer is 500 nm-10 ⁇ m.
  • a method for preparing a parallel array LED chip suitable for visible light communication comprising the following steps:
  • step S3 depositing a first bonding metal layer on the surface of the LED epitaxial wafer treated in step S2, thereby obtaining a first wafer;
  • the functional layer is etched and divided into a plurality of independent light-emitting active units, and etching channels are formed between adjacent light-emitting active units, and each light-emitting active unit contains at least one columnar N electrode;
  • step S8 engraving the step of the P electrode on the semi-finished LED chip processed in step S7, depositing the P electrode, and obtaining the finished product of the parallel array LED chip.
  • the columnar N electrode is an embedded electrode with a vertical structure, optimizes current distribution, has the characteristics of fast heat dissipation, easy processing, and high luminous efficiency; at the same time, the light-emitting active area is divided Forming multiple light-emitting active units and adopting a parallel array reduces the junction capacitance of the chip, thereby reducing the RC time constant, and can be used to prepare high-bandwidth LED chips suitable for visible light communication.
  • the parallel array of LED chips suitable for visible light communication provided by the present invention can further increase the light output power of LEDs by increasing the number of parallel chips, and is suitable for more application scenarios.
  • the preparation method of a parallel array LED chip suitable for visible light communication of the present invention has simple process and high yield, and is suitable for industrialized production.
  • Fig. 1 is the top view of parallel array LED chip structure in embodiment 1;
  • Fig. 2 is the sectional view of parallel array LED chip structure in embodiment 1;
  • Fig. 3 is the top view of parallel array LED chip structure in embodiment 2;
  • Fig. 4 is the sectional view of parallel array LED chip structure in embodiment 2;
  • Fig. 5 is the top view of LED chip structure in comparative example 1;
  • FIG. 6 is a cross-sectional view of the LED chip structure in Comparative Example 1.
  • 101 conductive substrate; 102, bonding metal layer; 103, first insulating layer; 104, p-contact mirror metal and protective layer; 105, p-type GaN layer; 106, InGaN/GaN multiple quantum well layer; 107, n-type GaN layer; 108, P electrode; 109, columnar N electrode; 110, second insulating layer.
  • a parallel array LED chip suitable for visible light communication includes a conductive substrate 101, a bonding metal layer 102, a first insulating layer 103, and a p-contact mirror connected in sequence from bottom to top
  • the metal and protective layer 104 and the light-emitting active area includes a P electrode 108 and a plurality of light-emitting active units distributed in an array, etching channels are provided between adjacent light-emitting active units, each light-emitting active
  • Each unit includes a functional layer and at least one columnar N electrode 109.
  • the functional layer includes a p-type GaN layer 105, an InGaN/GaN multi-quantum well layer 106, and an n-type GaN layer 107 connected sequentially from bottom to top.
  • the electrode 109 is located inside the functional layer, the top of the columnar N electrode 109 is in ohmic contact with the n-type GaN layer 107, and the bottom of the columnar N electrode 109 passes through the p-contact mirror metal and the protective layer 104,
  • the first insulating layer 103 forms electrical conduction with the bonding metal layer 102, and the P electrode 108 is in electrical contact with the p-contact mirror metal and the protective layer 104 to form electrical conduction;
  • the light-emitting active region is also provided with a second insulating layer 110 , the second insulating layer 110 covers the outer surface of the P electrode 108 , between the P electrode 108 and the light emitting active unit, the etching channel and the top surface of the light emitting active unit.
  • the number of the light emitting active units is 16, and each light emitting active unit includes a columnar N electrode 109 .
  • the N electrode is an alloy electrode of Cr and Pt; the diameter of the columnar N electrode 109 is 20 ⁇ m, and the height is 3 ⁇ m.
  • the P-electrode 108 is a rectangular dam structure surrounding the outside of the light-emitting active unit, and the P-electrode 108 is a Ti, Cr alloy electrode; the thickness of the P-electrode 108 is 3 ⁇ m.
  • the conductive substrate 101 is a conductive silicon substrate with a thickness of 500 ⁇ m; both the first insulating layer 103 and the second insulating layer 110 are SiO 2 insulating layers, and the first insulating layer 103 The thickness is 300 ⁇ m.
  • the p-contact mirror metal and protective layer 104 includes a p-contact mirror metal layer and a protective layer connected to the bottom surface of the p-contact mirror metal layer;
  • the p-contact mirror metal layer is made of Ag and /composition, the thickness of the metal layer of the p-contact mirror is 50nm;
  • the protection layer is a TiW layer, and the thickness of the protection layer is 300nm.
  • the bonding metal layer 102 is an alloy of Ni and Au, and the thickness of the bonding metal layer 102 is 3 ⁇ m.
  • a method for preparing a parallel array LED chip suitable for visible light communication includes the following steps:
  • a through-hole structure is prepared on the LED epitaxial wafer by photolithography and ICP etching; the through-hole structure radially penetrates the p-contact reflector metal and protective layer 104, p-type GaN layer 105 and InGaN/GaN sequentially
  • the multi-quantum well layer 106, the through-hole structure extends to the bottom of the n-type GaN layer 107, and an embedded columnar N electrode 109 channel is formed on the LED epitaxial wafer;
  • step (4) Depositing the first bonding metal layer on the LED chip described in step (4), and making the columnar N electrode 109 electrically conduct with the first bonding metal layer, thereby obtaining the first wafer;
  • Another conductive silicon substrate is taken as the conductive substrate 101, and a second bonding metal layer is prepared on the conductive substrate 101 through a deposition process, thereby obtaining a second wafer;
  • the step of the P electrode 108 is carved in the second insulating layer 110 by photolithography, and the P electrode 108 is deposited, so that the P electrode 108 is in electrical contact with the p-contact mirror metal and the protective layer 104 to form electrical conduction, and obtain Finished products of parallel array LED chips.
  • a parallel array LED chip suitable for visible light communication includes a conductive substrate 101, a bonding metal layer 102, a first insulating layer 103, and a p-contact mirror metal that are sequentially connected from bottom to top And the protective layer 104 and the light-emitting active area, the light-emitting active area includes a P electrode 108 and a plurality of light-emitting active units distributed in an array, an etching channel is provided between adjacent light-emitting active units, and each light-emitting active unit Each includes a functional layer and at least one columnar N electrode 109.
  • the functional layer includes a p-type GaN layer 105, an InGaN/GaN multi-quantum well layer 106 and an n-type GaN layer 107 connected sequentially from bottom to top.
  • the columnar N electrode 109 is located inside the functional layer, the top of the columnar N electrode 109 is in ohmic contact with the n-type GaN layer 107, and the bottom of the columnar N electrode 109 passes through the p-contact mirror metal and protective layer 104, the first An insulating layer 103 is electrically connected to the bonding metal layer 102, and the p-electrode 108 is in electrical contact with the p-contact mirror metal and the protective layer 104 to form an electrical connection; the light-emitting active region is also provided with a second insulating layer 110, The second insulating layer 110 covers the outer surface of the P electrode 108 , between the P electrode 108 and the light emitting active unit, the etching channel and the top surface of the light emitting active unit.
  • the number of light-emitting active units is four, and each light-emitting active unit includes four columnar N electrodes 109 .
  • the N electrode is an alloy electrode of Cr and Pt; the diameter of the columnar N electrode 109 is 20 ⁇ m, and the height is 3 ⁇ m.
  • the P-electrode 108 is a rectangular dam structure surrounding the outside of the light-emitting active unit, and the P-electrode 108 is a Ti, Cr alloy electrode; the thickness of the P-electrode 108 is 3 ⁇ m.
  • the conductive substrate 101 is a conductive silicon substrate with a thickness of 500 ⁇ m; both the first insulating layer 103 and the second insulating layer 110 are SiO 2 insulating layers, and the first insulating layer 103 The thickness is 500 ⁇ m.
  • the p-contact mirror metal and protective layer 104 includes a p-contact mirror metal layer and a protective layer connected to the bottom surface of the p-contact mirror metal layer;
  • the p-contact mirror metal layer is made of Ag and /composition, the thickness of the metal layer of the p-contact mirror is 50nm;
  • the protection layer is a TiW layer, and the thickness of the protection layer is 300nm.
  • the bonding metal layer 102 is an alloy of Ni and Au, and the thickness of the bonding metal layer 102 is 3 ⁇ m.
  • Example 1 preparation method of this example is the same as Example 1.
  • An LED chip as shown in Figure 5 and Figure 6, comprises a conductive substrate 101, a bonding metal layer 102, a first insulating layer 103, a p-contact reflector metal and a protective layer 104, and a light emitting chip connected sequentially from bottom to top.
  • Active area, the light-emitting active area includes a P electrode 108, a functional layer and at least one columnar N electrode 109, and the functional layer includes a p-type GaN layer 105, an InGaN/GaN multi-quantum well layer 106 and a sequentially connected from bottom to top.
  • the source region is further provided with a second insulating layer 110 , the second insulating layer 110 covers the outer surface of the P electrode 108 , between the P electrode 108 and the light-emitting active unit, and the top surface of the light-emitting active unit.
  • the N electrode is an alloy electrode of Cr and Pt; the columnar N electrode 109 has a diameter of 20 ⁇ m and a height of 3 ⁇ m.
  • the P-electrode 108 is a rectangular dam structure surrounding the outside of the light-emitting active unit, the P-electrode 108 is a Ti, Cr alloy electrode; the thickness of the P-electrode 108 is 3 ⁇ m.
  • the conductive substrate 101 is a conductive silicon substrate with a thickness of 500 ⁇ m; both the first insulating layer 103 and the second insulating layer 110 are SiO 2 insulating layers, and the thickness of the first insulating layer 103 is 300 ⁇ m.
  • the p-contact mirror metal and protective layer 104 include a p-contact mirror metal layer and a protective layer connected to the bottom surface of the p-contact mirror metal layer; the p-contact mirror metal layer is composed of Ag and/or The metal layer of the p-contact mirror has a thickness of 50nm; the protection layer is a TiW layer, and the thickness of the protection layer is 300nm.
  • the bonding metal layer 102 is an alloy of Ni and Au, and the thickness of the bonding metal layer 102 is 3 ⁇ m.
  • a method for preparing an LED chip as shown in Figure 5 and Figure 6, comprises the following steps:
  • a through-hole structure is prepared on the LED epitaxial wafer by photolithography and ICP etching; the through-hole structure radially penetrates the p-contact reflector metal and protective layer 104, p-type GaN layer 105 and InGaN/GaN sequentially The multi-quantum well layer 106, the through-hole structure extends to the bottom of the n-type GaN layer 107, forming an embedded columnar N electrode 109 channel on the LED epitaxial wafer;
  • step (4) Depositing the first bonding metal layer on the LED chip described in step (4), and making the columnar N electrode 109 electrically conduct with the first bonding metal layer, thereby obtaining the first wafer;
  • Another conductive silicon substrate is taken as the conductive substrate 101, and a second bonding metal layer is prepared on the conductive substrate 101 through a deposition process, thereby obtaining a second wafer;
  • PECVD is used to deposit SiO 2 to form a second insulating layer 110;
  • the step of the P electrode 108 is carved in the second insulating layer 110 by photolithography, and the P electrode 108 is deposited, so that the P electrode 108 is in electrical contact with the p-contact mirror metal and the protective layer 104 to form electrical conduction, and obtain Finished LED chips.
  • the modulation bandwidth frequency of the parallel array LED chips of Examples 1 and 2 is higher than that of the LED chip of Comparative Example 1, wherein, Example 1 is divided into 16 light-emitting active units, each A light-emitting active unit includes a columnar N electrode 109, and the modulation bandwidth frequency is much higher than that of the LED chip of Comparative Example 1. It is proved that by dividing the light-emitting active area into a plurality of light-emitting active units distributed in an array, it is beneficial to reduce the cost of the chip. The junction capacitance, thereby reducing the RC time constant, obtains a high-bandwidth LED chip suitable for visible light communication.

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Abstract

A parallel array LED chip suitable for visible light communication, and a manufacturing method therefor, relating to the technical field of visible light communication. The chip comprises a conductive substrate, a bonding metal layer, a first insulating layer, a p-contact mirror metal and protection layer, and a light-emitting active area that are sequentially connected from bottom to top. The light-emitting active area comprises a P electrode and a plurality of light-emitting active units arranged in an array. Etching channels are provided between adjacent light-emitting active units. Each light-emitting active unit comprises a functional layer and at least one columnar N electrode. The functional layer comprises a p-type GaN layer, an InGaN/GaN multi-quantum well layer, and an n-type GaN layer. The columnar N electrode is located inside the functional layer. The top of the columnar N electrode is in ohmic contact with the n-type GaN layer. Electrical conduction is formed between the bottom of the columnar N electrode and the bonding metal layer. According to the present invention, the junction capacitance of the chip is reduced, such that the RC time constant is reduced, and a high-bandwidth LED chip suitable for visible light communication is obtained.

Description

一种适用于可见光通信的并联阵列LED芯片及其制备方法A parallel array LED chip suitable for visible light communication and its preparation method 技术领域technical field
本发明属于可见光通信技术领域，具体涉及一种适用于可见光通信的并联阵列LED芯片及其制备方法。The invention belongs to the technical field of visible light communication, and in particular relates to a parallel array LED chip suitable for visible light communication and a preparation method thereof.
背景技术Background technique
过去30年，移动通信的发展深刻地改变了人类的生活方式。可见光通信(VLC)通过照明与通信技术的有机结合，依靠其绿色环保，于人体无害，且无需频谱资源，又保密性很高的优点，可以有效解决传统无线网络在覆盖，电磁干扰，信息安全等方面的问题，正逐渐成为下一代移动通信的备选技术之一。In the past 30 years, the development of mobile communication has profoundly changed the way of life of human beings. Visible light communication (VLC) through the organic combination of lighting and communication technology, relying on its green environmental protection, harmless to the human body, no need for spectrum resources, and high confidentiality, can effectively solve the problem of traditional wireless network coverage, electromagnetic interference, information Safety and other issues are gradually becoming one of the candidate technologies for the next generation of mobile communications.
在可见光通信中，LED由于响应时间短，可以高速调制而成为理想的光源。但可见光通信技术对光源具备较高的要求，不仅需要足够大的调制带宽以满足高速通信，也需要足够的功率和光效来满足其照明需求。而近年来嵌入式电极垂直结构因为出色的电流扩展能力而具备优秀的光电性能，在此基础上制备高带宽阵列LED芯片来满足对通照两用LED芯片的需求就显得具有重要意义。In visible light communication, LED is an ideal light source due to its short response time and high-speed modulation. However, visible light communication technology has high requirements on the light source. It not only needs a large enough modulation bandwidth to meet high-speed communication, but also needs sufficient power and light efficiency to meet its lighting needs. In recent years, the embedded electrode vertical structure has excellent photoelectric performance due to its excellent current expansion capability. On this basis, it is of great significance to prepare high-bandwidth array LED chips to meet the needs of dual-purpose LED chips for general lighting.
发明内容Contents of the invention
为了克服现有技术的不足，本发明的目的之一在于提供一种适用于可见光通信的并联阵列LED芯片，降低了芯片的结电容，从而降低了RC时间常数，得到适用于可见光通信的高带宽LED芯片。In order to overcome the deficiencies of the prior art, one of the purposes of the present invention is to provide a parallel array LED chip suitable for visible light communication, which reduces the junction capacitance of the chip, thereby reducing the RC time constant, and obtaining a high bandwidth suitable for visible light communication LED chips.
本发明的目的之二在于提供一种适用于可见光通信的并联阵列LED芯片的制备方法。The second object of the present invention is to provide a method for preparing parallel array LED chips suitable for visible light communication.
本发明的目的之一采用如下技术方案实现：One of purpose of the present invention adopts following technical scheme to realize:
提供一种适用于可见光通信的并联阵列LED芯片，包括从下到上依次连接的导电衬底、键合金属层、第一绝缘层、p接触反射镜金属及保护层和发光有源区，发光有源区包括P电极和多个阵列分布的发光有源单元，相邻的发光有源单元之间设有刻蚀通道，每个发光有源单元均包括功能层和至少一个柱状N电极，所述功能层包括从下到上依次连接的p型GaN层、InGaN/GaN多量子阱层和n型GaN层，所述柱状N电极位于所述功能层的内部，所述柱状N电极的顶部与所述n型GaN层欧姆接触，所述柱状N电极的底部依次穿过p接触反射镜金属及保护层、第一绝缘层与键合金属层形成电导通，所述P电极与p接触反射镜金属及保护层电接触形成电导通。A parallel array LED chip suitable for visible light communication is provided, including a conductive substrate, a bonding metal layer, a first insulating layer, a p-contact reflector metal and a protective layer, and a light-emitting active region sequentially connected from bottom to top. The active area includes a P electrode and a plurality of light-emitting active units distributed in an array, and an etching channel is provided between adjacent light-emitting active units. Each light-emitting active unit includes a functional layer and at least one columnar N electrode, so The functional layer includes a p-type GaN layer, an InGaN/GaN multi-quantum well layer and an n-type GaN layer sequentially connected from bottom to top, the columnar N electrode is located inside the functional layer, and the top of the columnar N electrode is connected to the The n-type GaN layer is in ohmic contact, and the bottom of the columnar N electrode passes through the metal of the p-contact mirror and the protective layer, the first insulating layer and the bonding metal layer to form electrical conduction, and the p-electrode and the p-contact mirror The metal and the protection layer are in electrical contact to form electrical conduction.
进一步地，所述发光有源单元个数为2-16个，每个发光有源单元包括1-4个柱状N电极。Further, the number of the light-emitting active units is 2-16, and each light-emitting active unit includes 1-4 columnar N electrodes.
进一步地，所述N电极为Ti、Cr、Ag、Au和Pt中的任一种或两种以上的合金；所述柱状N电极的直径为5-100μm，高度为1-10μm。Further, the N electrode is any one or an alloy of two or more of Ti, Cr, Ag, Au and Pt; the columnar N electrode has a diameter of 5-100 μm and a height of 1-10 μm.
进一步地，所述P电极为环绕于发光有源单元外侧呈矩形的围坝结构，所述P电极为Ti、Cr、Ag、Au和Pt中的任一种或两种以上的合金；所述P电极厚度为1-10μm。Further, the P electrode is a rectangular dam structure surrounding the outside of the light-emitting active unit, and the P electrode is any one or an alloy of two or more of Ti, Cr, Ag, Au, and Pt; the The thickness of the P electrode is 1-10 μm.
进一步地，所述发光有源区还设有第二绝缘层，所述第二绝缘层覆盖于所述P电极的外侧面、所述P电极与发光有源单元之间、刻蚀通道和发光有源单元的顶面。Further, the light-emitting active region is also provided with a second insulating layer, the second insulating layer covers the outer surface of the P electrode, between the P electrode and the light-emitting active unit, the etching channel and the light-emitting area. The top surface of the active cell.
进一步地，所述第一绝缘层和第二绝缘层为SiO 2绝缘层，厚度为30-300μm。 Further, the first insulating layer and the second insulating layer are SiO 2 insulating layers with a thickness of 30-300 μm.
进一步地，所述导电衬底为导电硅衬底，其厚度为100-600μm。Further, the conductive substrate is a conductive silicon substrate with a thickness of 100-600 μm.
进一步地，所述p接触反射镜金属及保护层包括p接触反射镜金属层和与p接触反射镜金属层的底面连接的保护层；Further, the p-contact mirror metal and protective layer include a p-contact mirror metal layer and a protective layer connected to the bottom surface of the p-contact mirror metal layer;
所述p接触反射镜金属层由Ag和/或Ni组成，所述p接触反射镜金属层的厚度为50-5000nm；The metal layer of the p-contact mirror is composed of Ag and/or Ni, and the thickness of the metal layer of the p-contact mirror is 50-5000nm;
所述保护层为TiW层，所述保护层的厚度为50-300nm。The protection layer is a TiW layer, and the thickness of the protection layer is 50-300nm.
进一步地，所述键合金属层为Ni、Au、Sn、Ti中的任一种或两种以上的合金，所述键合金属层的厚度为500nm-10μm。Further, the bonding metal layer is any one or an alloy of two or more of Ni, Au, Sn, Ti, and the thickness of the bonding metal layer is 500 nm-10 μm.
本发明的目的之二采用如下技术方案实现：Two of the purpose of the present invention adopts following technical scheme to realize:
一种适用于可见光通信的并联阵列LED芯片的制备方法，包括如下步骤：A method for preparing a parallel array LED chip suitable for visible light communication, comprising the following steps:
S1，在所述外延衬底上依次生长功能层和p接触反射镜金属及保护层，得到LED外延片；S1, sequentially growing a functional layer, a p-contact reflector metal and a protective layer on the epitaxial substrate to obtain an LED epitaxial wafer;
S2，在LED外延片上刻蚀出嵌入式柱状N电极通道；并在LED外延片的上表面以及嵌入式柱状N电极通道的内壁上生长第一绝缘层；在嵌入式柱状N电极通道上沉积形成柱状N电极；S2, etching the embedded columnar N electrode channel on the LED epitaxial wafer; and growing the first insulating layer on the upper surface of the LED epitaxial wafer and the inner wall of the embedded columnar N electrode channel; depositing and forming on the embedded columnar N electrode channel Columnar N electrode;
S3，在步骤S2处理后的LED外延片的表面沉积第一键合金属层，从而得到第一晶圆；S3, depositing a first bonding metal layer on the surface of the LED epitaxial wafer treated in step S2, thereby obtaining a first wafer;
S4，另取导电衬底通过沉积得到第二键合金属层，从而得到第二晶圆；S4, taking another conductive substrate to obtain a second bonding metal layer by deposition, thereby obtaining a second wafer;
S5，将制得的第一晶圆与第二晶圆进行表面活化后，将键合第一键合金属层与第二键合金属层键合，形成键合金属层，得到LED芯片半成品；S5, after surface activating the prepared first wafer and the second wafer, bonding the first bonding metal layer to the second bonding metal layer to form a bonding metal layer to obtain a semi-finished LED chip;
S6，将LED芯片半成品的外延衬底一侧进行腐蚀处理，露出n型GaN层；S6, corroding one side of the epitaxial substrate of the LED chip semi-finished product to expose the n-type GaN layer;
S7，在步骤S6处理后的LED芯片半成品上将功能层刻蚀分割成多个独立的发光有源单元，相邻的发光有源单元之间形成刻蚀通道，每个发光有源单元 中包含至少一个柱状N电极；S7, on the semi-finished LED chip processed in step S6, the functional layer is etched and divided into a plurality of independent light-emitting active units, and etching channels are formed between adjacent light-emitting active units, and each light-emitting active unit contains at least one columnar N electrode;
S8，在步骤S7处理后的LED芯片半成品上刻出P电极的台阶，沉积P电极，得到并联阵列LED芯片成品。S8, engraving the step of the P electrode on the semi-finished LED chip processed in step S7, depositing the P electrode, and obtaining the finished product of the parallel array LED chip.
相比现有技术，本发明的有益效果在于：Compared with the prior art, the beneficial effects of the present invention are:
本发明的一种适用于可见光通信的并联阵列LED芯片，柱状N电极为具有垂直结构的嵌入式电极，优化电流分布，具有散热快、易加工，发光效率高等特点；同时将发光有源区分割成多个发光有源单元并采用并联阵列，降低了芯片的结电容，从而降低了RC时间常数，可用于制备适用于可见光通信的高带宽LED芯片。A parallel array LED chip suitable for visible light communication of the present invention, the columnar N electrode is an embedded electrode with a vertical structure, optimizes current distribution, has the characteristics of fast heat dissipation, easy processing, and high luminous efficiency; at the same time, the light-emitting active area is divided Forming multiple light-emitting active units and adopting a parallel array reduces the junction capacitance of the chip, thereby reducing the RC time constant, and can be used to prepare high-bandwidth LED chips suitable for visible light communication.
进一步地，本发明提供的适用于可见光通信的并联阵列LED芯片，可通过提升并联芯片的数目来进一步提升LED的光输出功率，适用于更多的应用场景。Furthermore, the parallel array of LED chips suitable for visible light communication provided by the present invention can further increase the light output power of LEDs by increasing the number of parallel chips, and is suitable for more application scenarios.
本发明的一种适用于可见光通信的并联阵列LED芯片的制备方法，流程简单，成品率高，适用于工业化生产。The preparation method of a parallel array LED chip suitable for visible light communication of the present invention has simple process and high yield, and is suitable for industrialized production.
附图说明Description of drawings
图1为实施例1中并联阵列LED芯片结构的俯视图；Fig. 1 is the top view of parallel array LED chip structure in embodiment 1;
图2为实施例1中并联阵列LED芯片结构的剖视图；Fig. 2 is the sectional view of parallel array LED chip structure in embodiment 1;
图3为实施例2中并联阵列LED芯片结构的俯视图；Fig. 3 is the top view of parallel array LED chip structure in embodiment 2;
图4为实施例2中并联阵列LED芯片结构的剖视图；Fig. 4 is the sectional view of parallel array LED chip structure in embodiment 2;
图5为对比例1中LED芯片结构的俯视图；Fig. 5 is the top view of LED chip structure in comparative example 1;
图6为对比例1中LED芯片结构的剖视图。FIG. 6 is a cross-sectional view of the LED chip structure in Comparative Example 1. FIG.
101、导电衬底；102、键合金属层；103、第一绝缘层；104、p接触反射镜金属及保护层；105、p型GaN层；106、InGaN/GaN多量子阱层；107、n型GaN层；108、P电极；109、柱状N电极；110、第二绝缘层。101, conductive substrate; 102, bonding metal layer; 103, first insulating layer; 104, p-contact mirror metal and protective layer; 105, p-type GaN layer; 106, InGaN/GaN multiple quantum well layer; 107, n-type GaN layer; 108, P electrode; 109, columnar N electrode; 110, second insulating layer.
具体实施方式detailed description
下面，结合附图与具体实施方式，对本发明做进一步描述，需要说明的是，在不相冲突的前提下，以下描述的各实施例之间或各技术特征之间可以任意组合形成新的实施例。Below, the present invention will be further described in conjunction with the accompanying drawings and specific implementation methods. It should be noted that, on the premise of not conflicting, the various embodiments described below or the technical features can be combined arbitrarily to form new embodiments. .
实施例1Example 1
一种适用于可见光通信的并联阵列LED芯片，如图1和图2所示，包括从下到上依次连接的导电衬底101、键合金属层102、第一绝缘层103、p接触反射镜金属及保护层104和发光有源区，发光有源区包括P电极108和多个阵列分布的发光有源单元，相邻的发光有源单元之间设有刻蚀通道，每个发光有源单元均包括功能层和至少一个柱状N电极109，所述功能层包括从下到上依次连接的p型GaN层105、InGaN/GaN多量子阱层106和n型GaN层107，所述柱状N电极109位于所述功能层的内部，所述柱状N电极109的顶部与所述n型GaN层107欧姆接触，所述柱状N电极109的底部依次穿过p接触反射镜金属及保护层104、第一绝缘层103与键合金属层102形成电导通，所述P电极108与p接触反射镜金属及保护层104电接触形成电导通；所述发光有源区还设有第二绝缘层110，所述第二绝缘层110覆盖于所述P电极108的外侧面、所述P电极108与发光有源单元之间、刻蚀通道和发光有源单元的顶面。A parallel array LED chip suitable for visible light communication, as shown in Figure 1 and Figure 2, includes a conductive substrate 101, a bonding metal layer 102, a first insulating layer 103, and a p-contact mirror connected in sequence from bottom to top The metal and protective layer 104 and the light-emitting active area, the light-emitting active area includes a P electrode 108 and a plurality of light-emitting active units distributed in an array, etching channels are provided between adjacent light-emitting active units, each light-emitting active Each unit includes a functional layer and at least one columnar N electrode 109. The functional layer includes a p-type GaN layer 105, an InGaN/GaN multi-quantum well layer 106, and an n-type GaN layer 107 connected sequentially from bottom to top. The electrode 109 is located inside the functional layer, the top of the columnar N electrode 109 is in ohmic contact with the n-type GaN layer 107, and the bottom of the columnar N electrode 109 passes through the p-contact mirror metal and the protective layer 104, The first insulating layer 103 forms electrical conduction with the bonding metal layer 102, and the P electrode 108 is in electrical contact with the p-contact mirror metal and the protective layer 104 to form electrical conduction; the light-emitting active region is also provided with a second insulating layer 110 , the second insulating layer 110 covers the outer surface of the P electrode 108 , between the P electrode 108 and the light emitting active unit, the etching channel and the top surface of the light emitting active unit.
在本实施例中，所述发光有源单元个数为16个，每个发光有源单元包括1个柱状N电极109。In this embodiment, the number of the light emitting active units is 16, and each light emitting active unit includes a columnar N electrode 109 .
在本实施例中，所述N电极为Cr、Pt的合金电极；所述柱状N电极109的直径为20μm，高度为3μm。In this embodiment, the N electrode is an alloy electrode of Cr and Pt; the diameter of the columnar N electrode 109 is 20 μm, and the height is 3 μm.
在本实施例中，所述P电极108为环绕于发光有源单元外侧呈矩形的围坝 结构，所述P电极108为Ti、Cr合金电极；所述P电极108厚度为3μm。In this embodiment, the P-electrode 108 is a rectangular dam structure surrounding the outside of the light-emitting active unit, and the P-electrode 108 is a Ti, Cr alloy electrode; the thickness of the P-electrode 108 is 3 μm.
在本实施例中，所述导电衬底101为导电硅衬底，其厚度为500μm；所述第一绝缘层103和第二绝缘层110均为SiO 2绝缘层，所述第一绝缘层103的厚度为300μm。 In this embodiment, the conductive substrate 101 is a conductive silicon substrate with a thickness of 500 μm; both the first insulating layer 103 and the second insulating layer 110 are SiO 2 insulating layers, and the first insulating layer 103 The thickness is 300 μm.
在本实施例中，所述p接触反射镜金属及保护层104包括p接触反射镜金属层和与p接触反射镜金属层的底面连接的保护层；所述p接触反射镜金属层由Ag和/组成，所述p接触反射镜金属层的厚度为50nm；所述保护层为TiW层，所述保护层的厚度为300nm。In this embodiment, the p-contact mirror metal and protective layer 104 includes a p-contact mirror metal layer and a protective layer connected to the bottom surface of the p-contact mirror metal layer; the p-contact mirror metal layer is made of Ag and /composition, the thickness of the metal layer of the p-contact mirror is 50nm; the protection layer is a TiW layer, and the thickness of the protection layer is 300nm.
在本实施例中，所述键合金属层102为Ni、Au的合金，所述键合金属层102的厚度为3μm。In this embodiment, the bonding metal layer 102 is an alloy of Ni and Au, and the thickness of the bonding metal layer 102 is 3 μm.
一种适用于可见光通信的并联阵列LED芯片的制备方法，如图1-2所示，包括如下步骤：A method for preparing a parallel array LED chip suitable for visible light communication, as shown in Figure 1-2, includes the following steps:
(1)取Si衬底作为外延衬底，采用MOCVD设备在所述外延衬底上依次生长5um厚的AlGaN缓冲层、n型GaN层107、InGaN/GaN多量子阱层106和p型GaN层105，然后继续使用电子束蒸发设备在p型GaN层105上沉积p接触反射镜金属及保护层104，金属蒸发速率为15埃/秒，得到LED外延片；(1) Take the Si substrate as the epitaxial substrate, and use MOCVD equipment to sequentially grow a 5um thick AlGaN buffer layer, n-type GaN layer 107, InGaN/GaN multi-quantum well layer 106 and p-type GaN layer on the epitaxial substrate 105, then continue to use electron beam evaporation equipment to deposit p-contact mirror metal and protective layer 104 on the p-type GaN layer 105, the metal evaporation rate is 15 angstroms/second, and obtain LED epitaxial wafers;
(2)在所述LED外延片上通过光刻和ICP刻蚀制备出通孔结构；所述通孔结构依次径向贯穿p接触反射镜金属及保护层104、p型GaN层105和InGaN/GaN多量子阱层106，所述通孔结构延伸至n型GaN层107底部，在LED外延片上形成嵌入式柱状N电极109通道；(2) A through-hole structure is prepared on the LED epitaxial wafer by photolithography and ICP etching; the through-hole structure radially penetrates the p-contact reflector metal and protective layer 104, p-type GaN layer 105 and InGaN/GaN sequentially The multi-quantum well layer 106, the through-hole structure extends to the bottom of the n-type GaN layer 107, and an embedded columnar N electrode 109 channel is formed on the LED epitaxial wafer;
(3)在p接触反射镜金属及保护层104的上表面以及通孔结构的内壁上用 PECVD(等离子体增强化学的气相沉积法)生长第一绝缘层103，使第一绝缘层103完全覆盖p接触反射镜金属及保护层104、通孔结构内壁和底部，再通过选择性酸腐去除通孔结构底部的绝缘层，暴露出通孔结构的孔底；(3) grow the first insulating layer 103 on the upper surface of the p contact mirror metal and the protective layer 104 and the inner wall of the through-hole structure, so that the first insulating layer 103 is completely covered p contact the mirror metal and protective layer 104, the inner wall and bottom of the through-hole structure, and then remove the insulating layer at the bottom of the through-hole structure by selective acid corrosion, exposing the bottom of the through-hole structure;
(4)在通孔结构内采用金属蒸镀仪沉积嵌入式柱状N金属，形成柱状N电极109；(4) depositing embedded columnar N metal in the through-hole structure using a metal vapor deposition apparatus to form columnar N electrodes 109;
(5)在步骤(4)所述得LED芯片上通过沉积第一键合金属层，并使柱状N电极109与第一键合金属层形成电导通，从而得到第一晶圆；(5) Depositing the first bonding metal layer on the LED chip described in step (4), and making the columnar N electrode 109 electrically conduct with the first bonding metal layer, thereby obtaining the first wafer;
(6)另取导电硅衬底作为导电衬底101，通过沉积工艺在导电衬底101上制备得到第二键合金属层，从而得到第二晶圆；(6) Another conductive silicon substrate is taken as the conductive substrate 101, and a second bonding metal layer is prepared on the conductive substrate 101 through a deposition process, thereby obtaining a second wafer;
(7)将制得的第一晶圆与第二晶圆的键合层进行表面活化，将处理后的键合层对准，然后一起送入键合机进行预键合，键合过程中从第二晶圆的导电衬底101的中心处开始施加压力，并逐渐向边缘拓展，达到键合压力2MPa后，在300℃温度下键合2h，随后退火，取出后送入退火炉，200℃下保温30min，预键合的晶圆间形成牢固的键合，形成键合金属层102，得到LED芯片半成品；(7) Activate the surface of the bonded layer of the first wafer and the second wafer, align the bonded layer after processing, and then send them into the bonding machine together for pre-bonding. During the bonding process Apply pressure from the center of the conductive substrate 101 of the second wafer, and gradually expand to the edge. After reaching the bonding pressure of 2MPa, bond at 300°C for 2h, then anneal, take it out and send it to the annealing furnace for 200 Keep warm at ℃ for 30 minutes, and form a firm bond between the pre-bonded wafers, form a bonding metal layer 102, and obtain a semi-finished LED chip;
(8)将具有双衬底的LED芯片半成品的外延衬底经过机械研磨再浸没于氢氟酸、冰乙酸和硝酸的混合液(按照物质的量浓度计，氢氟酸：冰乙酸：硝酸＝5:1:5)中，腐蚀至外延衬底消失为止，再采用ICP刻蚀去除AlGaN缓冲层，暴露出n型GaN层107；(8) The epitaxial substrate of the LED chip semi-finished product with double substrate is immersed in the mixed solution of hydrofluoric acid, glacial acetic acid and nitric acid (according to the amount concentration meter of substance, hydrofluoric acid: glacial acetic acid: nitric acid = 5:1:5), etch until the epitaxial substrate disappears, and then use ICP etching to remove the AlGaN buffer layer, exposing the n-type GaN layer 107;
(9)采用ICP刻蚀将n型GaN层107、InGaN/GaN多量子阱层106和p型GaN层105组成的功能层分割成多个独立的发光有源单元，相邻的发光有源单元之间形成刻蚀通道，每个发光有源单元中包含一个柱状N电极109，然后采用PECVD进行SiO 2沉积形成第二绝缘层110，所述第二绝缘层110包覆所有 的发光有源单元并填充于刻蚀通道内部，将不同的发光有源单元隔离； (9) Use ICP etching to divide the functional layer composed of n-type GaN layer 107, InGaN/GaN multi-quantum well layer 106 and p-type GaN layer 105 into a plurality of independent light-emitting active units, and adjacent light-emitting active units An etching channel is formed between them, and each light-emitting active unit contains a columnar N electrode 109, and then SiO2 is deposited by PECVD to form a second insulating layer 110, and the second insulating layer 110 covers all the light-emitting active units And fill in the inside of the etching channel to isolate different light-emitting active units;
(10)最终通过光刻在第二绝缘层110内刻出P电极108的台阶，沉积P电极108，使所述P电极108与p接触反射镜金属及保护层104电接触形成电导通，得到并联阵列LED芯片成品。(10) Finally, the step of the P electrode 108 is carved in the second insulating layer 110 by photolithography, and the P electrode 108 is deposited, so that the P electrode 108 is in electrical contact with the p-contact mirror metal and the protective layer 104 to form electrical conduction, and obtain Finished products of parallel array LED chips.
实施例2Example 2
一种适用于可见光通信的并联阵列LED芯片，如图3-4所示，包括从下到上依次连接的导电衬底101、键合金属层102、第一绝缘层103、p接触反射镜金属及保护层104和发光有源区，发光有源区包括P电极108和多个阵列分布的发光有源单元，相邻的发光有源单元之间设有刻蚀通道，每个发光有源单元均包括功能层和至少一个柱状N电极109，所述功能层包括从下到上依次连接的p型GaN层105、InGaN/GaN多量子阱层106和n型GaN层107，所述柱状N电极109位于所述功能层的内部，所述柱状N电极109的顶部与所述n型GaN层107欧姆接触，所述柱状N电极109的底部依次穿过p接触反射镜金属及保护层104、第一绝缘层103与键合金属层102形成电导通，所述P电极108与p接触反射镜金属及保护层104电接触形成电导通；所述发光有源区还设有第二绝缘层110，所述第二绝缘层110覆盖于所述P电极108的外侧面、所述P电极108与发光有源单元之间、刻蚀通道和发光有源单元的顶面。A parallel array LED chip suitable for visible light communication, as shown in Figure 3-4, includes a conductive substrate 101, a bonding metal layer 102, a first insulating layer 103, and a p-contact mirror metal that are sequentially connected from bottom to top And the protective layer 104 and the light-emitting active area, the light-emitting active area includes a P electrode 108 and a plurality of light-emitting active units distributed in an array, an etching channel is provided between adjacent light-emitting active units, and each light-emitting active unit Each includes a functional layer and at least one columnar N electrode 109. The functional layer includes a p-type GaN layer 105, an InGaN/GaN multi-quantum well layer 106 and an n-type GaN layer 107 connected sequentially from bottom to top. The columnar N electrode 109 is located inside the functional layer, the top of the columnar N electrode 109 is in ohmic contact with the n-type GaN layer 107, and the bottom of the columnar N electrode 109 passes through the p-contact mirror metal and protective layer 104, the first An insulating layer 103 is electrically connected to the bonding metal layer 102, and the p-electrode 108 is in electrical contact with the p-contact mirror metal and the protective layer 104 to form an electrical connection; the light-emitting active region is also provided with a second insulating layer 110, The second insulating layer 110 covers the outer surface of the P electrode 108 , between the P electrode 108 and the light emitting active unit, the etching channel and the top surface of the light emitting active unit.
在本实施例中，发光有源单元个数为4个，每个发光有源单元包括4个柱状N电极109。In this embodiment, the number of light-emitting active units is four, and each light-emitting active unit includes four columnar N electrodes 109 .
在本实施例中，所述N电极为Cr、Pt的合金电极；所述柱状N电极109的直径为20μm，高度为3μm。In this embodiment, the N electrode is an alloy electrode of Cr and Pt; the diameter of the columnar N electrode 109 is 20 μm, and the height is 3 μm.
在本实施例中，所述P电极108为环绕于发光有源单元外侧呈矩形的围坝 结构，所述P电极108为Ti、Cr合金电极；所述P电极108厚度为3μm。In this embodiment, the P-electrode 108 is a rectangular dam structure surrounding the outside of the light-emitting active unit, and the P-electrode 108 is a Ti, Cr alloy electrode; the thickness of the P-electrode 108 is 3 μm.
在本实施例中，所述导电衬底101为导电硅衬底，其厚度为500μm；所述第一绝缘层103和第二绝缘层110均为SiO 2绝缘层，所述第一绝缘层103的厚度为500μm。 In this embodiment, the conductive substrate 101 is a conductive silicon substrate with a thickness of 500 μm; both the first insulating layer 103 and the second insulating layer 110 are SiO 2 insulating layers, and the first insulating layer 103 The thickness is 500 μm.
在本实施例中，所述p接触反射镜金属及保护层104包括p接触反射镜金属层和与p接触反射镜金属层的底面连接的保护层；所述p接触反射镜金属层由Ag和/组成，所述p接触反射镜金属层的厚度为50nm；所述保护层为TiW层，所述保护层的厚度为300nm。In this embodiment, the p-contact mirror metal and protective layer 104 includes a p-contact mirror metal layer and a protective layer connected to the bottom surface of the p-contact mirror metal layer; the p-contact mirror metal layer is made of Ag and /composition, the thickness of the metal layer of the p-contact mirror is 50nm; the protection layer is a TiW layer, and the thickness of the protection layer is 300nm.
在本实施例中，所述键合金属层102为Ni、Au的合金，所述键合金属层102的厚度为3μm。In this embodiment, the bonding metal layer 102 is an alloy of Ni and Au, and the thickness of the bonding metal layer 102 is 3 μm.
进一步地，本实施例的制备方法与实施例1相同。Further, the preparation method of this example is the same as Example 1.
对比例1Comparative example 1
一种LED芯片，如图5和图6所示，包括从下到上依次连接的导电衬底101、键合金属层102、第一绝缘层103、p接触反射镜金属及保护层104和发光有源区，发光有源区包括P电极108、功能层和至少一个柱状N电极109，所述功能层包括从下到上依次连接的p型GaN层105、InGaN/GaN多量子阱层106和n型GaN层107，所述柱状N电极109位于所述功能层的内部，所述柱状N电极109的顶部与所述n型GaN层107欧姆接触，所述柱状N电极109的底部依次穿过p接触反射镜金属及保护层104、第一绝缘层103与键合金属层102形成电导通，所述P电极108与p接触反射镜金属及保护层104电接触形成电导通；所述发光有源区还设有第二绝缘层110，所述第二绝缘层110覆盖于所述P电极108的外侧面、所述P电极108与发光有源单元之间和发光有源单元的顶面。An LED chip, as shown in Figure 5 and Figure 6, comprises a conductive substrate 101, a bonding metal layer 102, a first insulating layer 103, a p-contact reflector metal and a protective layer 104, and a light emitting chip connected sequentially from bottom to top. Active area, the light-emitting active area includes a P electrode 108, a functional layer and at least one columnar N electrode 109, and the functional layer includes a p-type GaN layer 105, an InGaN/GaN multi-quantum well layer 106 and a sequentially connected from bottom to top. n-type GaN layer 107, the columnar N electrode 109 is located inside the functional layer, the top of the columnar N electrode 109 is in ohmic contact with the n-type GaN layer 107, and the bottom of the columnar N electrode 109 passes through in turn The p-contact reflector metal and the protective layer 104, the first insulating layer 103 and the bonding metal layer 102 form electrical conduction, and the P electrode 108 is in electrical contact with the p-contact reflector metal and the protective layer 104 to form electrical conduction; The source region is further provided with a second insulating layer 110 , the second insulating layer 110 covers the outer surface of the P electrode 108 , between the P electrode 108 and the light-emitting active unit, and the top surface of the light-emitting active unit.
进一步地，所述N电极为Cr、Pt的合金电极；所述柱状N电极109的直径为20μm，高度为3μm。Further, the N electrode is an alloy electrode of Cr and Pt; the columnar N electrode 109 has a diameter of 20 μm and a height of 3 μm.
进一步地，所述P电极108为环绕于发光有源单元外侧呈矩形的围坝结构，所述P电极108为Ti、Cr合金电极；所述P电极108厚度为3μm。Further, the P-electrode 108 is a rectangular dam structure surrounding the outside of the light-emitting active unit, the P-electrode 108 is a Ti, Cr alloy electrode; the thickness of the P-electrode 108 is 3 μm.
进一步地，所述导电衬底101为导电硅衬底，其厚度为500μm；所述第一绝缘层103和第二绝缘层110均为SiO 2绝缘层，所述第一绝缘层103的厚度为300μm。 Further, the conductive substrate 101 is a conductive silicon substrate with a thickness of 500 μm; both the first insulating layer 103 and the second insulating layer 110 are SiO 2 insulating layers, and the thickness of the first insulating layer 103 is 300 μm.
进一步地，所述p接触反射镜金属及保护层104包括p接触反射镜金属层和与p接触反射镜金属层的底面连接的保护层；所述p接触反射镜金属层由Ag和/组成，所述p接触反射镜金属层的厚度为50nm；所述保护层为TiW层，所述保护层的厚度为300nm。Further, the p-contact mirror metal and protective layer 104 include a p-contact mirror metal layer and a protective layer connected to the bottom surface of the p-contact mirror metal layer; the p-contact mirror metal layer is composed of Ag and/or The metal layer of the p-contact mirror has a thickness of 50nm; the protection layer is a TiW layer, and the thickness of the protection layer is 300nm.
进一步地，所述键合金属层102为Ni、Au的合金，所述键合金属层102的厚度为3μm。Further, the bonding metal layer 102 is an alloy of Ni and Au, and the thickness of the bonding metal layer 102 is 3 μm.
一种LED芯片的制备方法，如图5和图6所示，包括如下步骤：A method for preparing an LED chip, as shown in Figure 5 and Figure 6, comprises the following steps:
(1)取Si衬底作为外延衬底，采用MOCVD设备在所述外延衬底上依次生长5um厚的AlGaN缓冲层、n型GaN层107、InGaN/GaN多量子阱层106和p型GaN层105，然后继续使用电子束蒸发设备在p型GaN层105上沉积p接触反射镜金属及保护层104，金属蒸发速率为15埃/秒，得到LED外延片；(1) Take the Si substrate as the epitaxial substrate, and use MOCVD equipment to sequentially grow a 5um thick AlGaN buffer layer, n-type GaN layer 107, InGaN/GaN multi-quantum well layer 106 and p-type GaN layer on the epitaxial substrate 105, then continue to use electron beam evaporation equipment to deposit p-contact mirror metal and protective layer 104 on the p-type GaN layer 105, the metal evaporation rate is 15 angstroms/second, and obtain LED epitaxial wafers;
(2)在所述LED外延片上通过光刻和ICP刻蚀制备出通孔结构；所述通孔结构依次径向贯穿p接触反射镜金属及保护层104、p型GaN层105和InGaN/GaN多量子阱层106，所述通孔结构延伸至n型GaN层107底部，在LED 外延片上形成嵌入式柱状N电极109通道；(2) A through-hole structure is prepared on the LED epitaxial wafer by photolithography and ICP etching; the through-hole structure radially penetrates the p-contact reflector metal and protective layer 104, p-type GaN layer 105 and InGaN/GaN sequentially The multi-quantum well layer 106, the through-hole structure extends to the bottom of the n-type GaN layer 107, forming an embedded columnar N electrode 109 channel on the LED epitaxial wafer;
(3)在p接触反射镜金属及保护层104的上表面以及通孔结构的内壁上用PECVD(等离子体增强化学的气相沉积法)生长第一绝缘层103，使第一绝缘层103完全覆盖p接触反射镜金属及保护层104、通孔结构内壁和底部，再通过选择性酸腐去除通孔结构底部的绝缘层，暴露出通孔结构的孔底；(3) grow the first insulating layer 103 on the upper surface of the p contact mirror metal and the protective layer 104 and the inner wall of the through-hole structure, so that the first insulating layer 103 is completely covered p contact the mirror metal and protective layer 104, the inner wall and bottom of the through-hole structure, and then remove the insulating layer at the bottom of the through-hole structure by selective acid corrosion, exposing the bottom of the through-hole structure;
(4)在通孔结构内采用金属蒸镀仪沉积嵌入式柱状N金属，形成柱状N电极109；(4) depositing embedded columnar N metal in the through-hole structure using a metal vapor deposition apparatus to form columnar N electrodes 109;
(5)在步骤(4)所述得LED芯片上通过沉积第一键合金属层，并使柱状N电极109与第一键合金属层形成电导通，从而得到第一晶圆；(5) Depositing the first bonding metal layer on the LED chip described in step (4), and making the columnar N electrode 109 electrically conduct with the first bonding metal layer, thereby obtaining the first wafer;
(6)另取导电硅衬底作为导电衬底101，通过沉积工艺在导电衬底101上制备得到第二键合金属层，从而得到第二晶圆；(6) Another conductive silicon substrate is taken as the conductive substrate 101, and a second bonding metal layer is prepared on the conductive substrate 101 through a deposition process, thereby obtaining a second wafer;
(7)将制得的第一晶圆与第二晶圆的键合层进行表面活化，将处理后的键合层对准，然后一起送入键合机进行预键合，键合过程中从第二晶圆的导电衬底101的中心处开始施加压力，并逐渐向边缘拓展，达到键合压力2MPa后，在300℃温度下键合2h，随后退火，取出后送入退火炉，200℃下保温30min，预键合的晶圆间形成牢固的键合，形成键合金属层102，得到LED芯片半成品；(7) Activate the surface of the bonded layer of the first wafer and the second wafer, align the bonded layer after processing, and then send them into the bonding machine together for pre-bonding. During the bonding process Apply pressure from the center of the conductive substrate 101 of the second wafer, and gradually expand to the edge. After reaching the bonding pressure of 2MPa, bond at 300°C for 2h, then anneal, take it out and send it to the annealing furnace for 200 Keep warm at ℃ for 30 minutes, and form a firm bond between the pre-bonded wafers, form a bonding metal layer 102, and obtain a semi-finished LED chip;
(8)将具有双衬底的LED芯片半成品的外延衬底经过机械研磨再浸没于氢氟酸、冰乙酸和硝酸的混合液(按照物质的量浓度计，氢氟酸：冰乙酸：硝酸＝5:1:5)中，腐蚀至外延衬底消失为止，再采用ICP刻蚀去除AlGaN缓冲层，暴露出n型GaN层107；(8) The epitaxial substrate of the LED chip semi-finished product with double substrate is immersed in the mixed solution of hydrofluoric acid, glacial acetic acid and nitric acid (according to the amount concentration meter of substance, hydrofluoric acid: glacial acetic acid: nitric acid = 5:1:5), etch until the epitaxial substrate disappears, and then use ICP etching to remove the AlGaN buffer layer, exposing the n-type GaN layer 107;
(9)所述发光有源区中采用PECVD进行SiO 2沉积形成第二绝缘层110； (9) In the light-emitting active region, PECVD is used to deposit SiO 2 to form a second insulating layer 110;
(10)最终通过光刻在第二绝缘层110内刻出P电极108的台阶，沉积P电极108，使所述P电极108与p接触反射镜金属及保护层104电接触形成电导通，得到LED芯片成品。(10) Finally, the step of the P electrode 108 is carved in the second insulating layer 110 by photolithography, and the P electrode 108 is deposited, so that the P electrode 108 is in electrical contact with the p-contact mirror metal and the protective layer 104 to form electrical conduction, and obtain Finished LED chips.
性能测试Performance Testing
将实施例1、2和对比例1的LED芯片，在50mA电流下进行调制带宽测试，结果如表1所示。The LED chips of Examples 1 and 2 and Comparative Example 1 were subjected to a modulation bandwidth test at a current of 50 mA, and the results are shown in Table 1.
表1 性能测试结果Table 1 Performance test results
项目project 实施例1Example 1 实施例2Example 2 对比例1Comparative example 1
带宽(MHz)Bandwidth (MHz) 6565 3838 2020
如表1所示，在50mA电流测试下，实施例1、2的并联阵列LED芯片的调制带宽频率高于对比例1的LED芯片，其中，实施例1划分为16个发光有源单元，每个发光有源单元包括1个柱状N电极109，调制带宽频率远高于对比例1的LED芯片，证明通过将发光有源区划分为多个阵列分布的发光有源单元，有利于降低了芯片的结电容，从而降低了RC时间常数，得到适用于可见光通信的高带宽LED芯片。As shown in Table 1, under the 50mA current test, the modulation bandwidth frequency of the parallel array LED chips of Examples 1 and 2 is higher than that of the LED chip of Comparative Example 1, wherein, Example 1 is divided into 16 light-emitting active units, each A light-emitting active unit includes a columnar N electrode 109, and the modulation bandwidth frequency is much higher than that of the LED chip of Comparative Example 1. It is proved that by dividing the light-emitting active area into a plurality of light-emitting active units distributed in an array, it is beneficial to reduce the cost of the chip. The junction capacitance, thereby reducing the RC time constant, obtains a high-bandwidth LED chip suitable for visible light communication.
上述实施方式仅为本发明的优选实施方式，不能以此来限定本发明保护的范围，本领域的技术人员在本发明的基础上所做的任何非实质性的变化及替换均属于本发明所要求保护的范围。The above-mentioned embodiment is only a preferred embodiment of the present invention, and cannot be used to limit the protection scope of the present invention. Any insubstantial changes and substitutions made by those skilled in the art on the basis of the present invention belong to the scope of the present invention. Scope of protection claimed.

Claims (10)

  1. 一种适用于可见光通信的并联阵列LED芯片，其特征在于，包括从下到上依次连接的导电衬底、键合金属层、第一绝缘层、p接触反射镜金属及保护层和发光有源区，发光有源区包括P电极和多个阵列分布的发光有源单元，相邻的发光有源单元之间设有刻蚀通道，每个发光有源单元均包括功能层和至少一个柱状N电极，所述功能层包括从下到上依次连接的p型GaN层、InGaN/GaN多量子阱层和n型GaN层，所述柱状N电极位于所述功能层的内部，所述柱状N电极的顶部与所述n型GaN层欧姆接触，所述柱状N电极的底部依次穿过p接触反射镜金属及保护层、第一绝缘层与键合金属层形成电导通，所述P电极与p接触反射镜金属及保护层电接触形成电导通。A parallel array LED chip suitable for visible light communication, characterized in that it includes a conductive substrate, a bonding metal layer, a first insulating layer, a p-contact reflector metal and a protective layer, and a light-emitting active substrate sequentially connected from bottom to top. The light-emitting active area includes a P electrode and a plurality of light-emitting active units distributed in an array, and an etching channel is provided between adjacent light-emitting active units. Each light-emitting active unit includes a functional layer and at least one columnar N electrode, the functional layer includes a p-type GaN layer, an InGaN/GaN multi-quantum well layer, and an n-type GaN layer connected sequentially from bottom to top, the columnar N electrode is located inside the functional layer, and the columnar N electrode The top of the columnar N electrode is in ohmic contact with the n-type GaN layer, the bottom of the columnar N electrode passes through the p contact mirror metal and protective layer, the first insulating layer and the bonding metal layer to form electrical conduction, and the P electrode and the p The metal of the contact mirror and the protective layer are in electrical contact to form electrical conduction.
  2. 如权利要求1所述的一种适用于可见光通信的并联阵列LED芯片，其特征在于：所述发光有源单元个数为2-16个，每个发光有源单元包括1-4个柱状N电极。A parallel array LED chip suitable for visible light communication according to claim 1, wherein the number of the light-emitting active units is 2-16, and each light-emitting active unit includes 1-4 columnar N electrode.
  3. 如权利要求1所述的一种适用于可见光通信的并联阵列LED芯片，其特征在于：所述N电极为Ti、Cr、Ag、Au和Pt中的任一种或两种以上的合金；所述柱状N电极的直径为5-100μm，高度为1-10μm。A parallel array LED chip suitable for visible light communication according to claim 1, characterized in that: the N electrode is any one or an alloy of two or more of Ti, Cr, Ag, Au and Pt; The diameter of the columnar N electrode is 5-100 μm, and the height is 1-10 μm.
  4. 如权利要求1所述的一种适用于可见光通信的并联阵列LED芯片，其特征在于：所述P电极为环绕于发光有源单元外侧呈矩形的围坝结构，所述P电极为Ti、Cr、Ag、Au和Pt中的任一种或两种以上的合金；所述P电极厚度为1-10μm。A parallel array LED chip suitable for visible light communication according to claim 1, characterized in that: the P electrode is a rectangular dam structure surrounding the outside of the light-emitting active unit, and the P electrode is made of Ti, Cr , Ag, Au and Pt, or an alloy of two or more; the thickness of the P electrode is 1-10 μm.
  5. 如权利要求4所述的一种适用于可见光通信的并联阵列LED芯片，其特征在于：所述发光有源区还设有第二绝缘层，所述第二绝缘层覆盖于所述P电极的外侧面、所述P电极与发光有源单元之间、刻蚀通道和发光有源单元的顶 面。A parallel array LED chip suitable for visible light communication according to claim 4, characterized in that: the light-emitting active area is also provided with a second insulating layer, and the second insulating layer covers the P electrode The outer surface, between the P electrode and the light-emitting active unit, the etching channel and the top surface of the light-emitting active unit.
  6. 如权利要求5所述的一种适用于可见光通信的并联阵列LED芯片，其特征在于：所述第一绝缘层和第二绝缘层为SiO 2绝缘层。 A parallel array LED chip suitable for visible light communication according to claim 5, characterized in that: the first insulating layer and the second insulating layer are SiO 2 insulating layers.
  7. 如权利要求1所述的一种适用于可见光通信的并联阵列LED芯片，其特征在于：所述导电衬底为导电硅衬底，其厚度为100-600μm。A parallel array LED chip suitable for visible light communication according to claim 1, wherein the conductive substrate is a conductive silicon substrate with a thickness of 100-600 μm.
  8. 如权利要求1所述的一种适用于可见光通信的并联阵列LED芯片，其特征在于：所述p接触反射镜金属及保护层包括p接触反射镜金属层和与p接触反射镜金属层的底面连接的保护层；A parallel array LED chip suitable for visible light communication according to claim 1, characterized in that: the p-contact reflector metal and protective layer comprise a p-contact reflector metal layer and a bottom surface of the p-contact reflector metal layer connection protection layer;
    所述p接触反射镜金属层由Ag和/或Ni组成，所述p接触反射镜金属层的厚度为50-5000nm；The metal layer of the p-contact mirror is composed of Ag and/or Ni, and the thickness of the metal layer of the p-contact mirror is 50-5000nm;
    所述保护层为TiW层，所述保护层的厚度为50-300nm。The protective layer is a TiW layer, and the thickness of the protective layer is 50-300nm.
  9. 如权利要求1所述的一种适用于可见光通信的并联阵列LED芯片，其特征在于：所述键合金属层为Ni、Au、Sn、Ti中的任一种或两种以上的合金，所述键合金属层的厚度为500nm-10μm。A parallel array LED chip suitable for visible light communication according to claim 1, characterized in that: the bonding metal layer is any one of Ni, Au, Sn, Ti or an alloy of two or more, so The thickness of the bonding metal layer is 500nm-10μm.
  10. 权利要求1-9任一项所述的一种适用于可见光通信的并联阵列LED芯片的制备方法，其特征在于，包括如下步骤：A method for preparing a parallel array LED chip suitable for visible light communication according to any one of claims 1-9, characterized in that it comprises the following steps:
    S1，在所述外延衬底上依次生长功能层和p接触反射镜金属及保护层，得到LED外延片；S1, sequentially growing a functional layer, a p-contact reflector metal and a protective layer on the epitaxial substrate to obtain an LED epitaxial wafer;
    S2，在LED外延片上刻蚀出嵌入式柱状N电极通道；并在LED外延片的上表面以及嵌入式柱状N电极通道的内壁上生长第一绝缘层；在嵌入式柱状N电极通道上沉积形成柱状N电极；S2, etching an embedded columnar N electrode channel on the LED epitaxial wafer; and growing a first insulating layer on the upper surface of the LED epitaxial wafer and the inner wall of the embedded columnar N electrode channel; depositing and forming on the embedded columnar N electrode channel Columnar N electrode;
    S3，在步骤S2处理后的LED外延片的表面沉积第一键合金属层，从而得到第一晶圆；S3, depositing a first bonding metal layer on the surface of the LED epitaxial wafer treated in step S2, thereby obtaining a first wafer;
    S4，另取导电衬底通过沉积得到第二键合金属层，从而得到第二晶圆；S4, taking another conductive substrate to obtain a second bonding metal layer by deposition, thereby obtaining a second wafer;
    S5，将制得的第一晶圆与第二晶圆进行表面活化后，将键合第一键合金属层与第二键合金属层键合，形成键合金属层，得到LED芯片半成品；S5, after activating the surface of the prepared first wafer and the second wafer, bonding the first bonding metal layer to the second bonding metal layer to form a bonding metal layer to obtain a semi-finished LED chip;
    S6，将LED芯片半成品的外延衬底一侧进行腐蚀处理，露出n型GaN层；S6, corroding one side of the epitaxial substrate of the LED chip semi-finished product to expose the n-type GaN layer;
    S7，在步骤S6处理后的LED芯片半成品上将功能层刻蚀分割成多个独立的发光有源单元，相邻的发光有源单元之间形成刻蚀通道，每个发光有源单元中包含至少一个柱状N电极；S7, on the semi-finished LED chip processed in step S6, the functional layer is etched and divided into a plurality of independent light-emitting active units, and etching channels are formed between adjacent light-emitting active units, and each light-emitting active unit contains at least one columnar N electrode;
    S8，在步骤S7处理后的LED芯片半成品上刻出P电极的台阶，沉积P电极，得到并联阵列LED芯片成品。S8, engraving the step of the P electrode on the semi-finished LED chip processed in step S7, depositing the P electrode, and obtaining the finished product of the parallel array LED chip.
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