WO2023273016A1

WO2023273016A1 - Semiconductor test structure and preparation method therefor

Info

Publication number: WO2023273016A1
Application number: PCT/CN2021/124404
Authority: WO
Inventors: 王路广
Original assignee: 长鑫存储技术有限公司
Priority date: 2021-07-02
Filing date: 2021-10-18
Publication date: 2023-01-05
Also published as: CN113471174A

Abstract

The present application provides a preparation method for a semiconductor test structure, comprising: providing a semiconductor structure, the semiconductor structure comprising a substrate, and a capacitor array structure on the front of the substrate, the capacitor array structure comprising multiple capacitors arranged in an array, a lower electrode of each capacitor being connected to the substrate by means of a capacitor contact structure, upper electrodes of each capacitor sharing the same capacitor plate, and the capacitor plate extending to a lower part of one side of the capacitor array structure; performing back-thinning of the semiconductor structure until the capacitor contact structure is exposed; etching a edge region of the capacitor array structure from the bottom of the obtained structure until the capacitor plate is exposed; and forming a first test pad at a bottom part of the exposed capacitor plate.

Description

Semiconductor test structure and manufacturing method thereof

This application claims the priority of the Chinese patent application with the application number 202110753566.1 and the invention title "Semiconductor Test Structure and Preparation Method" submitted to the China Patent Office on July 02, 2021, the entire contents of which are incorporated by reference in this application .

technical field

The present application relates to, but is not limited to, a semiconductor test structure and a manufacturing method thereof.

Background technique

The DRAM (Dynamic Random Access Memory) capacitor structure is usually a columnar structure and is closely arranged. Multiple DRAM capacitor structures share an upper substrate, and the lower substrate of each DRAM capacitor structure is independently located on the contact pad. Therefore, the upper and lower substrates of the DRAM capacitor structure are on different planes.

Nano-probe technology can be used to measure the capacitance value of the capacitive structure in micro-devices, provided that the test probes are on the same plane. Therefore, it is temporarily impossible to use nano-probe technology to measure the capacitance in DRAM in the reverse analysis project of DRAM. Measurement.

Contents of the invention

The following is an overview of the subject matter described in detail in this application. This summary is not intended to limit the scope of the claims.

The application provides a semiconductor test structure and a preparation method thereof.

The first aspect of the present application provides a method for preparing a semiconductor test structure, including: providing a semiconductor structure, the semiconductor structure includes a substrate and a capacitor array structure located on the front surface of the substrate, and the capacitor array structure includes a plurality of Arranged capacitors, the lower electrode of each capacitor is connected to the substrate through a capacitive contact structure, the upper electrode of each capacitor shares the same capacitor plate, and the capacitor plate extends to the capacitor array The lower part of one side of the structure; thinning the back of the semiconductor structure until the capacitor contact structure is exposed; etching the edge region of the capacitor array structure from the bottom of the obtained structure until the capacitor plate is exposed; The exposed bottom of the capacitor plate forms a first test pad.

The preparation method of the semiconductor test structure above removes the substrate at the bottom of the capacitor array structure to expose the capacitor contact structure, and forms a pad at the bottom of the capacitor plate, so that the nano-probe technology can be applied to the capacitance value of the DRAM capacitor structure Measurement.

According to some embodiments of the present disclosure, the base includes a substrate and a dielectric layer located on the upper surface of the substrate, and a shallow trench isolation structure and several word lines arranged in parallel and at intervals are formed in the substrate, so that The shallow trench isolation structure isolates a number of active regions arranged in an array in the substrate; a number of parallel and spaced bit lines are formed in the dielectric layer; the capacitance contact structure is located in the adjacent Between the bit lines and in contact with the active region; the thinning the backside of the semiconductor structure includes: thinning the backside of the substrate until the substrate and part of the dielectric are removed. layer and the bit line until the capacitive contact structure is exposed.

According to some embodiments of the present disclosure, the etching the edge region of the capacitor array structure from the bottom of the obtained structure until the capacitor plate is exposed includes: etching the edge of the capacitor array structure from the bottom of the obtained structure The area is etched to form a first opening, and the first opening exposes the capacitor plate; a filling dielectric layer is formed in the first opening, and the filling dielectric layer fills the first opening; Forming a second opening in the filling medium layer, the second opening exposing the capacitor plate; forming a first test pad on the exposed bottom of the capacitor plate includes: the first test pad A disk is formed within the second opening.

According to some embodiments of the present disclosure, the edge region of the capacitor array structure is etched from the bottom of the resulting structure by using a focused ion beam process to form a first opening; the filling medium layer is formed by using a focused ion beam process; The filling medium layer is etched by a focused ion beam process to form the second opening in the filling medium layer.

According to some embodiments of the present disclosure, a silicon oxide layer is formed in the first opening as the filling medium layer.

According to some embodiments of the present disclosure, the width of the second opening is smaller than the width of the first opening.

According to some embodiments of the present disclosure, while forming the first test pad, a second test pad is also formed on the exposed bottom of the capacitive contact structure.

According to some embodiments of the present disclosure, the lower surface of the second test pad is flush with the lower surface of the first test pad.

According to some embodiments of the present disclosure, the number of the second test pads is the same as the number of the capacitors, and the second test pads are provided in one-to-one correspondence with the capacitors.

According to some embodiments of the present disclosure, the number of the second test pads is less than the number of the capacitors, and each of the second test pads is connected to the capacitive contact structures of a plurality of the capacitors.

The second aspect of the present application provides a semiconductor testing structure, including: a capacitor array structure, including a plurality of capacitors arranged in an array; a capacitive contact structure, which is provided in one-to-one correspondence with the capacitors, and is located at each of the capacitors The bottom of the lower electrode; the capacitor plate, connected to the upper electrode of each capacitor, and extending to the lower part of one side of the capacitor array structure; the first test pad, located at the lower part of the capacitor plate, and The capacitor plates are in contact.

According to some embodiments of the present disclosure, the semiconductor test structure further includes a filling dielectric layer located on the lower surface of the capacitor plate; the first test pad is located in the filling dielectric layer.

According to some embodiments of the present disclosure, the semiconductor test structure further includes a second test pad located at the bottom of the capacitive contact structure; the lower surface of the second test pad is the same as the lower surface of the first test pad. flush.

In the semiconductor test structure and the preparation method thereof provided in the embodiments of the present application, the problem that the capacitor structure of the DRAM cannot be measured by nano-probe technology is solved. Moreover, the above semiconductor testing structure can be applied to different forms of nano-probe testing, such as capacitance testing for a single capacitor, so as to flexibly measure the capacitance of the target capacitor. When the capacitance value of a single capacitor is too small to be measured accurately, it is also possible to set a large-area second test pad to cover multiple capacitive contact structures to conduct capacitance tests on multiple capacitors, and finally divide by the second test The capacitance of a single capacitor can be obtained from the number of capacitive contact structures covered by the pad.

Other aspects will be apparent to others upon reading and understanding the drawings and detailed description.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate the embodiments of the application and together with the description serve to explain the principles of the embodiments of the application. In the drawings, like reference numerals are used to denote like elements. The drawings in the following description are some embodiments of the present application, but not all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without any creative work.

FIG. 1 is a flow chart of a method for preparing a semiconductor test structure in an embodiment of the present application.

FIG. 2 is a cross-sectional schematic diagram of a semiconductor structure including a capacitor and a substrate in an embodiment of the present application.

FIG. 3 is a schematic cross-sectional view of the semiconductor structure obtained by thinning the backside of the semiconductor structure shown in FIG. 2 to expose the capacitive contact structure.

FIG. 4 is a schematic cross-sectional view of a semiconductor structure obtained after forming a first opening in the semiconductor structure shown in FIG. 3 according to an embodiment of the present application.

5 is a schematic cross-sectional view of a semiconductor structure obtained after forming a filling dielectric layer in the first opening according to an embodiment of the present application.

6 is a schematic cross-sectional view of a semiconductor structure obtained after forming a second opening in the filling dielectric layer according to an embodiment of the present application.

7 is a schematic cross-sectional view of a semiconductor structure obtained after forming a first test pad in a second opening according to an embodiment of the present application.

FIG. 8 is a schematic cross-sectional view of a semiconductor structure obtained after forming a second test pad in an embodiment of the present application.

FIG. 9 is a schematic cross-sectional view of a semiconductor structure obtained after forming a second test pad in another embodiment of the present application.

FIG. 10 is a schematic cross-sectional view of a semiconductor structure obtained after forming a second test pad in still another embodiment of the present application.

Description of reference numerals: 11, base; 111, substrate; 112, first dielectric layer; 12, capacitive contact structure; 13, shallow trench isolation structure; 14, active region; 16, bit line; 161, tungsten layer ; 162, titanium nitride layer; 17, bit line covering dielectric layer; 18, bit line sidewall; 19, bit line contact structure; 20, upper electrode; 21, second dielectric layer; 22, lower electrode; 23, top layer Support layer; 24, middle support layer; 25, bottom support layer; 26, capacitor plate; 27, first opening; 28, filling medium layer; 29, second opening; 30, first test pad; 31, second Two test pads.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are part of the embodiments of the application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of this application. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

With the continuous shrinking of the volume of semiconductor devices, the application of nano-probe technology in the field of semiconductor technology is becoming more and more extensive. Among them, nano-probe technology can be used to measure the capacitance in semiconductor structures, but the prerequisite is that the nano-probes are located on the same plane. However, the capacitance structure in the current DRAM is usually columnar, and the upper and lower electrodes are in different planes, so it is difficult to measure the capacitance value by using nano-probe technology. In view of the above problems, the present application proposes a semiconductor test structure and its preparation method, so as to realize the measurement of the capacitance value of DRAM by using nano-probe technology.

As shown in Figure 1, referring to Figures 1 to 7, an embodiment of the present application provides a method for preparing a semiconductor test structure, including:

Step S11: providing a semiconductor structure, the semiconductor structure includes a substrate 11 and a capacitor array structure located on the front surface of the substrate 11, the capacitor array structure includes a plurality of capacitors arranged in an array, and the lower electrode 22 of each capacitor is connected to the substrate through the capacitor contact structure 12 11, the upper electrode 20 of each capacitor shares the same capacitor plate 26, and the capacitor plate 26 extends to the lower part of one side of the capacitor array structure.

Step S12 : Thinning the backside of the semiconductor structure until the capacitive contact structure 12 is exposed.

Step S13: Etching the edge region of the capacitor array structure from the bottom of the obtained structure until the capacitor plate 26 is exposed.

Step S14 : forming a first test pad 30 on the exposed bottom of the capacitor plate 26 .

The semiconductor structure provided in step S11 is shown in FIG. 2 . The semiconductor structure includes a substrate 11 and a capacitor array structure on the front surface of the substrate 11 . Wherein, the base 11 includes a substrate 111 and a first dielectric layer 112 located on the upper surface of the substrate 111 . A shallow trench isolation structure 13 and several word lines (not shown in the figure) arranged at intervals in parallel are formed in the substrate 111. The shallow trench isolation structure 13 isolates several word lines arranged in an array in the substrate 111. active area 14 . A plurality of bit lines 16 arranged in parallel and spaced apart are formed in the first dielectric layer 112 , and the capacitive contact structure 12 is located between adjacent bit lines 16 and is in contact with the active region 14 . In an exemplary embodiment, the bit line 16 can be a titanium nitride layer 162 and a metal tungsten layer 161 stacked from bottom to top, the upper and lower parts of the bit line 16 are provided with a bit line covering dielectric layer 17, the bit line 16 and Bit line spacers 18 are provided on both sides of the bit line covering dielectric layer 17 . It can be understood that a bit line contact structure 19 is further formed between the bit line 16 and the active region 14 , and the bit line 16 and the active region 14 are electrically connected through the bit line contact structure 19 .

Please continue to refer to FIG. 2 , the capacitor array structure includes a plurality of capacitors arranged in an array, wherein the capacitors include an upper electrode 20 , a lower electrode 22 and a second dielectric layer 21 . Usually, in order to improve the stability of the capacitor structure, several supporting layers are also arranged in the capacitor array structure, for example, in the capacitor array structure in this embodiment, including the top support layer 23, the middle support layer 24 and the bottom support layer 25. The lower electrode 22 of each capacitor is connected to the substrate 11 through the capacitive contact structure 12 , as shown in FIG. 2 , the capacitive contact structure 12 penetrates the first dielectric layer 112 and contacts the active region 14 in the substrate 111 . The upper electrodes 20 share the same capacitive plate 26 , and the capacitive plate 26 extends to the lower part of one side of the capacitive array structure. In an exemplary embodiment, the capacitive plate 26 is in contact with the upper surface of the substrate 11 .

In step S12 , the backside of the semiconductor structure is thinned until the capacitive contact structure 12 is exposed. In an exemplary embodiment, the step of thinning the backside of the semiconductor structure includes: using a chemical mechanical polishing process to thin the backside of the substrate 11 until the substrate 111, part of the first dielectric layer 112 and the bit line 16 are removed until the exposed Capacitive contact structure 12 . After thinning the back of the semiconductor structure, a schematic cross-sectional structure as shown in FIG. 3 is obtained.

Referring to FIGS. 4 to 6, in step S13, the edge region of the capacitor array structure is etched from the bottom of the obtained structure until the step of exposing the capacitor plate 26 may include:

Step S131 : Etching the edge region of the capacitor array structure from the bottom of the obtained structure to form a first opening 27 , exposing the capacitor plate 26 through the first opening 27 .

In an exemplary embodiment, the edge region of the capacitor array structure may be etched from the bottom of the resulting structure by using a focused ion beam process to form the first opening 27 , and the etched first opening 27 is shown in FIG. 4 . The first opening 27 penetrates through the dielectric layer and exposes part of the capacitor plate 26 .

Step S132 : forming a filling medium layer 28 in the first opening 27 , and filling the first opening 27 with the filling medium layer 28 .

In an exemplary embodiment, the filling dielectric layer 28 may be formed in the first opening 27 by using a focused ion beam process. The filling dielectric layer 28 may be a silicon oxide layer. A schematic cross-sectional view of the semiconductor structure obtained after the filling dielectric layer 28 is formed is shown in FIG. 5 .

Step S133 : forming a second opening 29 in the filling dielectric layer 28 , exposing the capacitor plate 26 through the second opening 29 .

In an exemplary embodiment, the filling dielectric layer 28 may be etched by a focused ion beam process to form the second opening 29 in the filling dielectric layer 28 . The width of the second opening 29 is smaller than the width of the first opening 27. As shown in FIG. A schematic cross-sectional view of the semiconductor structure obtained after forming the second opening 29 is shown in FIG. 6 .

In step S14 , a first test pad 30 is formed on the exposed bottom of the capacitor plate 26 . In an exemplary embodiment, a first test pad 30 may be formed within the second opening 29 , as shown in FIG. 7 . The material of the first test pad 30 may be metal tungsten or platinum. Wherein, the lower surface of the first test pad 30 is flush with the lower surface of the exposed capacitive contact structure 12, so that when the nanoprobes are respectively connected to the capacitive contact structure 12 and the first test pad 30, the nanometer The probes are in the same plane, enabling the measurement of capacitance within semiconductor structures using nanoprobe technology.

The lower surface of the semiconductor test structure exposes the capacitive contact structure 12 and the first test pad 30, and the surface of the capacitive contact structure 12 and the first test pad 30 is located on the same plane, by connecting the nanoprobes to a capacitive contact structure 12 and the surface of the first test pad 30 , the capacitance value of the capacitor corresponding to the capacitive contact structure 12 can be measured.

In the exemplary embodiment, capacitive contact structure 12 includes contact pads. When backside thinning is performed on the semiconductor structure, the thinning is performed until the lower surface of the contact pad is exposed. The lower surface of the first test pad 30 formed in the second opening 29 is flush with the lower surface of the contact pad. When the nano-probe technology is used for capacitance measurement, the nano-probes are in contact with the lower surface of the contact pad and the lower surface of the first test pad 30 respectively, so that the nano-probes are in the same plane.

In an exemplary embodiment, as shown in FIG. 8 , while the first test pad 30 is formed in the second opening 29 , the second test pad 31 may also be formed at the bottom of the exposed capacitive contact structure 12 . Wherein, the lower surface of the second testing pad 31 is flush with the lower surface of the first testing pad 30 . When using the nano-probe technology for capacitance measurement, the nano-probes are in contact with the lower surface of the second test pad 31 and the lower surface of the first test pad 30 respectively, so that the nano-probes are in the same plane.

In an exemplary embodiment, the number of the second test pads 31 is the same as the number of capacitors, and the second test pads 31 are set in one-to-one correspondence with the capacitors, as shown in FIG. 9 , so that the nanoprobe can measure each Capacitance value of a capacitor.

In an exemplary embodiment, the number of second test pads 31 is less than the number of capacitors, and each second test pad 31 is connected to capacitive contact structures 12 of a plurality of capacitors, as shown in FIG. 10 . Since a single capacitor has a small volume and a small capacitance value, after the back surface is thinned to expose the capacitive contact structure 12, second test pads 31 with different area sizes can be deposited in the array area, according to the size of the single capacitor area. , the amount of capacitance covered by the second test pad 31 can be calculated. After the capacitance value is measured by the nanoprobe, it can be divided by the capacitance quantity to obtain the capacitance value of a single capacitor. Through this method, the accuracy of capacitance measurement can be improved, avoiding the inaccurate measurement due to the small value of a single capacitance.

In an exemplary embodiment, one second test pad 31 may be prepared under four adjacent capacitive contact structures 12, or one second test pad 31 may be prepared under six adjacent capacitive contact structures 12. . After the measured capacitance value is obtained, the capacitance value of a single capacitor can be obtained by dividing by the number of capacitors contacted by the second test pad 31 .

Since capacitors at different positions in the array area may have different capacitance values, in order to reduce errors and improve test accuracy, the second test pad 31 can be set at different positions in the array area, for example, in the middle and edge positions of the array area Second test pads 31 are provided respectively. It should be noted that no matter the position of the second test pad 31 is set in the middle or the edge of the array area, it is necessary to ensure that the lower surface of the second test pad 31 is flush with the lower surface of the first test pad 30 .

An embodiment of the present application also provides a semiconductor testing structure, as shown in FIG. 7 , including: a capacitor array structure, including a plurality of capacitors arranged in an array; a capacitor contact structure 12, which is provided in one-to-one correspondence with the capacitors, and Located at the bottom of the lower electrode 22 of each capacitor; the capacitor plate 26 is connected to the upper electrode 20 of each capacitor and extends to the lower part of one side of the capacitor array structure; the first test pad 30 is located on the capacitor plate 26 The lower part is in contact with the capacitor plate 26.

Wherein, the capacitor includes an upper electrode 20 , a lower electrode 22 and a second dielectric layer 21 . The lower electrode 22 of each capacitor is connected to the capacitive contact structure 12, and the upper electrode 20 shares the same capacitive plate 26, and the capacitive plate 26 extends to the lower part of one side of the capacitive array structure. The first test pad 30 is disposed on the lower part of the capacitor plate 26 , is based on the capacitor plate 26 and penetrates through the dielectric layer, so as to expose the lower surface of the first test pad 30 . The lower surface of the first test pad 30 is flush with the lower surface of each capacitive contact structure 12 . In an exemplary embodiment, the first test pad 30 may be metal tungsten or metal platinum. Capacitor plate 26 may be doped polysilicon.

The above-mentioned semiconductor test structure can be used in the measurement of capacitance in nanometer measurement technology. Since the lower surface of the first test pad 30 and the capacitive contact structure 12 are in the same plane, the nano-probes can be respectively arranged on the lower surface of the first test pad 30 and the lower surface of the capacitive contact structure 12 to measure Get the capacitance value of a single capacitor. The semiconductor test structure solves the problem that the traditional DRAM structure cannot directly measure capacitance by using nano-probe technology.

In the exemplary embodiment, the semiconductor test structure further includes a fill dielectric layer 28 . The filling medium layer 28 is located on the lower surface of the capacitor plate 26, and the first test pad 30 is located in the filling medium layer 28.

In an exemplary embodiment, as shown in FIG. 8 , the semiconductor test structure further includes a second test pad 31 located at the bottom of the capacitive contact structure 12; The lower surface is even.

In an exemplary embodiment, as shown in FIG. 9 , the number of second test pads 31 is the same as the number of capacitors, and the second test pads 31 are arranged in one-to-one correspondence with capacitors. By arranging the second test pad 31 at the capacitive contact structure 12 under each capacitor, the measurement object can be flexibly selected when the nano-probe technology is used to measure the capacitance value of the capacitor in the semiconductor structure.

In an exemplary embodiment, as shown in FIG. 10 , the number of second test pads 31 is less than the number of capacitors, and each second test pad 31 is connected to capacitive contact structures 12 of a plurality of capacitors. Since a single capacitor has a small volume and a small capacitance value, the second test pads 31 with different area sizes can be deposited in the array area, and the coverage of the second test pads 31 can be calculated according to the size of the single capacitance area. the number of capacitors. After the nano-probe technology is applied to the semiconductor test structure in this embodiment, the capacitance value can be measured by the nano-probe technology first, and then divided by the capacitance value to obtain the capacitance value of a single capacitor. Through this method, the accuracy of capacitance measurement can be improved, and the problem of inaccurate measurement due to too small a single capacitance value can be avoided.

Each embodiment or implementation manner in this specification is described in a progressive manner, each embodiment focuses on the differences from other embodiments, and the same and similar parts of each embodiment can be referred to each other.

In the description of this specification, descriptions with reference to the terms "embodiments", "exemplary embodiments", "some implementations", "exemplary implementations", "examples" and the like mean that the descriptions are described in conjunction with the implementations or examples. A specific feature, structure, material, or characteristic is included in at least one embodiment or example of the present application.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the described specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, use a specific orientation construction and operation, therefore should not be construed as limiting the application.

It can be understood that the terms "first", "second", etc. used in this application can be used to describe various structures in this application, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

In one or more drawings, like elements are indicated with like reference numerals. For the sake of clarity, various parts in the drawings are not drawn to scale. Also, some well-known parts may not be shown. For simplicity, the structure obtained after several steps can be described in one figure. In the following, many specific details of the present application, such as device structures, materials, dimensions, processing techniques and techniques, are described for a clearer understanding of the present application. However, as will be understood by those skilled in the art, the application may be practiced without these specific details.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit it; although the application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some or all of the technical features; these modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Industrial Applicability

Claims

A method for preparing a semiconductor test structure, comprising:

Provide a semiconductor structure, the semiconductor structure includes a substrate and a capacitor array structure located on the front surface of the substrate, the capacitor array structure includes a plurality of capacitors arranged in an array, the lower electrode of each capacitor is connected to the capacitor through a capacitor contact structure The bases are connected, and the upper electrodes of each capacitor share the same capacitor plate, and the capacitor plate extends to the lower part of one side of the capacitor array structure;

Thinning the backside of the semiconductor structure until the capacitive contact structure is exposed;

Etching the edge region of the capacitor array structure from the bottom of the obtained structure until the capacitor plate is exposed;

A first test pad is formed on the exposed bottom of the capacitor plate.
The preparation method of semiconductor test structure according to claim 1, wherein,

The base includes a substrate and a dielectric layer located on the upper surface of the substrate. A shallow trench isolation structure and several word lines arranged in parallel and at intervals are formed in the substrate. The shallow trench isolation structure is formed on the substrate. A plurality of active regions arranged in an array are isolated in the substrate; a plurality of parallel and spaced bit lines are formed in the dielectric layer; the capacitive contact structure is located between adjacent bit lines, and in contact with the active region;

The thinning the backside of the semiconductor structure includes:

Thinning the backside of the substrate until the substrate, part of the dielectric layer and the bit line are removed, until the capacitor contact structure is exposed.
The method for preparing a semiconductor test structure according to claim 1, wherein etching the edge region of the capacitor array structure from the bottom of the obtained structure until exposing the capacitor plate comprises:

Etching the edge region of the capacitor array structure from the bottom of the resulting structure to form a first opening, the first opening exposing the capacitor plate;

forming a filling medium layer in the first opening, the filling medium layer filling up the first opening;

forming a second opening in the filling dielectric layer, the second opening exposing the capacitor plate;

Forming the first test pad on the exposed bottom of the capacitor plate includes:

The first test pad is formed in the second opening.
The method for preparing a semiconductor test structure according to claim 3, wherein the edge region of the capacitor array structure is etched from the bottom of the resulting structure by using a focused ion beam process to form a first opening; using a focused ion beam process forming the filling medium layer; etching the filling medium layer by using a focused ion beam process to form the second opening in the filling medium layer.
The method for manufacturing a semiconductor test structure according to claim 3, wherein a silicon oxide layer is formed in the first opening as the filling dielectric layer.
The method for fabricating a semiconductor test structure according to claim 3, wherein the width of the second opening is smaller than the width of the first opening.
The method for preparing a semiconductor test structure according to any one of claims 1 to 6, wherein, while forming the first test pad, a second test pad is also formed on the exposed bottom of the capacitive contact structure. plate.
The method for manufacturing a semiconductor test structure according to claim 7, wherein the lower surface of the second test pad is flush with the lower surface of the first test pad.
The method for manufacturing a semiconductor test structure according to claim 7, wherein the number of the second test pads is the same as the number of the capacitors, and the second test pads are set in one-to-one correspondence with the capacitors.
The method for preparing a semiconductor test structure according to claim 7, wherein the number of the second test pads is less than the number of the capacitors, and each of the second test pads is connected to a plurality of capacitors. The capacitive contact structure.
A semiconductor test structure comprising:

A capacitor array structure, including a plurality of capacitors arranged in an array;

Capacitive contact structures are provided in one-to-one correspondence with the capacitors and are located at the bottom of the lower electrode of each capacitor;

a capacitor plate, connected to the upper electrode of each capacitor, and extending to the lower part of one side of the capacitor array structure;

The first test pad is located at the lower part of the capacitor plate and is in contact with the capacitor plate.
The semiconductor test structure according to claim 11, further comprising:

The filling medium layer is located on the lower surface of the capacitor plate; the first test pad is located in the filling medium layer.
The semiconductor test structure according to claim 11, further comprising:

The second test pad is located at the bottom of the capacitive contact structure; the lower surface of the second test pad is flush with the lower surface of the first test pad.
The semiconductor testing structure according to claim 13, wherein the number of the second test pads is the same as the number of the capacitors, and the second test pads are provided in one-to-one correspondence with the capacitors.
The semiconductor test structure according to claim 13, wherein the number of the second test pads is less than the number of the capacitors, each of the second test pads is connected to the capacitance of a plurality of the capacitors contact structure.