CN113471174A - Semiconductor test structure and preparation method thereof - Google Patents
Semiconductor test structure and preparation method thereof Download PDFInfo
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- CN113471174A CN113471174A CN202110753566.1A CN202110753566A CN113471174A CN 113471174 A CN113471174 A CN 113471174A CN 202110753566 A CN202110753566 A CN 202110753566A CN 113471174 A CN113471174 A CN 113471174A
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- 238000012360 testing method Methods 0.000 title claims abstract description 129
- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000003990 capacitor Substances 0.000 claims abstract description 200
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000005530 etching Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 26
- 238000010884 ion-beam technique Methods 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 18
- 239000000523 sample Substances 0.000 abstract description 14
- 238000005259 measurement Methods 0.000 abstract description 11
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
- G01R27/2605—Measuring capacitance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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Abstract
The invention relates to a preparation method of a semiconductor test structure, which comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a substrate and a capacitor array structure positioned on the front surface of the substrate, the capacitor array structure comprises a plurality of capacitors arranged in an array manner, the lower electrode of each capacitor is connected with the substrate through a capacitor contact structure, the upper electrodes of the capacitors share the same capacitor plate, and the capacitor plate extends to the lower part of one side of the capacitor array structure; thinning the back of the semiconductor structure until the capacitor contact structure is exposed; etching the edge area of the capacitor array structure from the bottom of the obtained structure until the capacitor plate is exposed; and forming a first test pad on the bottom of the exposed capacitor plate. According to the preparation method of the semiconductor test structure, the substrate at the bottom of the capacitor array structure is removed to expose the capacitor contact structure, and the bonding pad is formed at the bottom of the capacitor plate, so that the nano probe technology can be applied to capacitance measurement of the DRAM capacitor structure.
Description
Technical Field
The present invention relates to semiconductor device manufacturing technologies, and in particular, to a semiconductor test structure and a method for fabricating the same.
Background
The DRAM capacitor structures are generally columnar structures and are arranged closely, a plurality of DRAM capacitor structures share one upper substrate, and the lower substrate of each DRAM capacitor structure is independently located on the contact pad, so that the upper substrate and the lower substrate of each DRAM capacitor structure are located on different planes.
The nanoprobe technology can be used for measuring the capacitance value of a capacitor structure in a micro device, and the precondition is that the test probes are positioned on the same plane, so the nanoprobe technology cannot be used for measuring the capacitance in the DRAM temporarily in the reverse analysis engineering of the DRAM.
Disclosure of Invention
In view of the above, it is desirable to provide a semiconductor test structure and a method for fabricating the same.
A method for preparing a semiconductor test structure comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a substrate and a capacitor array structure positioned on the front surface of the substrate, the capacitor array structure comprises a plurality of capacitors arranged in an array manner, the lower electrode of each capacitor is connected with the substrate through a capacitor contact structure, the upper electrodes of the capacitors share the same capacitor plate, and the capacitor plate extends to the lower part of one side of the capacitor array structure; thinning the back of the semiconductor structure until the capacitor contact structure is exposed; etching the edge area of the capacitor array structure from the bottom of the obtained structure until the capacitor polar plate is exposed; and forming a first test pad at the bottom of the exposed capacitor plate.
According to the preparation method of the semiconductor test structure, the substrate at the bottom of the capacitor array structure is removed to expose the capacitor contact structure, and the bonding pad is formed at the bottom of the capacitor plate, so that the nano probe technology can be applied to capacitance measurement of the DRAM capacitor structure.
In one embodiment, the substrate comprises a substrate and a dielectric layer located on the upper surface of the substrate, a shallow trench isolation structure and a plurality of word lines arranged in parallel at intervals are formed in the substrate, and a plurality of active regions arranged in an array are isolated in the substrate by the shallow trench isolation structure; a plurality of bit lines which are arranged in parallel at intervals are formed in the dielectric layer; the capacitor contact structure is positioned between the adjacent bit lines and is in contact with the active region; the back face thinning of the semiconductor structure comprises: and thinning the back of the base until the substrate, part of the dielectric layer and the bit line are removed until the capacitor contact structure is exposed.
In one embodiment, the etching the edge region of the capacitor array structure from the bottom of the obtained structure until the capacitor plate is exposed includes: etching the edge area of the capacitor array structure from the bottom of the obtained structure to form a first opening, wherein the capacitor polar plate is exposed out of the first opening; forming a filling medium layer in the first opening, wherein the filling medium layer fills the first opening; forming a second opening in the filling dielectric layer, wherein the capacitor plate is exposed out of the second opening; the first test pad is formed in the second opening.
In one embodiment, the edge region of the capacitor array structure is etched from the bottom of the obtained structure by adopting a focused ion beam process to form a first opening; forming the filling dielectric layer by adopting a focused ion beam process; and etching the filling medium layer by adopting a focused ion beam process so as to form the second opening in the filling medium layer.
In one embodiment, a silicon oxide layer is formed in the first opening as the filling dielectric layer.
In one embodiment, the width of the second opening is smaller than the width of the first opening.
In one embodiment, a second test pad is formed on the bottom of the exposed capacitor contact structure while the first test pad is formed.
In one embodiment, a lower surface of the second test pad is flush with a lower surface of the first test pad.
In one embodiment, the number of the second test pads is the same as the number of the capacitors, and the second test pads are arranged in one-to-one correspondence with the capacitors.
In one embodiment, the number of the second test pads is less than the number of the capacitors, and each of the second test pads is connected to the capacitive contact structure of a plurality of the capacitors.
A semiconductor test structure, comprising: the capacitor array structure comprises a plurality of capacitors arranged in an array; the capacitor contact structures are arranged in one-to-one correspondence with the capacitors and are positioned at the bottoms of the lower electrodes of the capacitors; the capacitor plate is connected with the upper electrode of each capacitor and extends to the lower part of one side of the capacitor array structure; and the first test pad is positioned at the lower part of the capacitor plate and is in contact with the capacitor plate.
In one embodiment, the semiconductor test structure further comprises a filling dielectric layer located on the lower surface of the capacitor plate; the first test pad is located within the dielectric fill layer.
In one embodiment, the semiconductor test structure further comprises a second test pad located at the bottom of the capacitive contact structure; the lower surface of the second test pad is flush with the lower surface of the first test pad.
The semiconductor test structure solves the problem that the DRAM capacitor structure cannot utilize the nanoprobe technology to measure the capacitance. Moreover, the semiconductor test structure can be suitable for testing the nanoprobes in different forms, for example, the capacitance test of a single capacitor, and the capacitor of the target capacitor can be flexibly measured. When the capacitance value of a single capacitor is too small to be accurately measured, a plurality of capacitor contact structures can be covered by the second testing bonding pad with a large area, so that the capacitance of the plurality of capacitors can be tested, and finally the capacitance value of the single capacitor can be obtained by dividing the number of the capacitor contact structures covered by the second testing bonding pad.
Drawings
Fig. 1 is a flow chart of a method for fabricating a semiconductor test structure according to an embodiment of the present disclosure.
Fig. 2 is a cross-sectional structure diagram of a semiconductor structure including a capacitor and a substrate according to an embodiment of the present application.
Fig. 3 is a schematic cross-sectional view of the semiconductor structure shown in fig. 2 after backside thinning to expose the capacitor contact structure.
Fig. 4 is a schematic cross-sectional view of a semiconductor structure obtained after forming a first opening in the semiconductor structure shown in fig. 3 according to an embodiment of the present application.
Fig. 5 is a schematic cross-sectional view illustrating a semiconductor structure after a dielectric layer is formed in the first opening according to an embodiment of the present disclosure.
Fig. 6 is a schematic cross-sectional view of a semiconductor structure after forming a second opening in a filling dielectric layer according to an embodiment of the present application.
Fig. 7 is a cross-sectional view of a semiconductor structure after forming a first test pad in a second opening according to an embodiment of the present application.
FIG. 8 is a cross-sectional view of a semiconductor structure resulting from the formation of a second test pad in an embodiment of the present application.
FIG. 9 is a cross-sectional view of a semiconductor structure resulting from the formation of a second test pad in another embodiment of the present application.
FIG. 10 is a cross-sectional view of a semiconductor structure resulting from the formation of a second test pad in yet another embodiment of the present application.
The reference numbers illustrate: 11. a substrate; 111. a substrate; 112. a first dielectric layer; 12. a capacitive contact structure; 13. a shallow trench isolation structure; 14. an active region; 16. a bit line; 161. a tungsten layer; 162. a titanium nitride layer; 17. the bit line covers the dielectric layer; 18. a bit line side wall; 19. a bit line contact structure; 20. an upper electrode; 21. a second dielectric layer; 22. a lower electrode; 23. a top supporting layer; 24. a middle support layer; 25. a bottom support layer; 26. a capacitor plate; 27. a first opening; 28. filling the dielectric layer; 29. a second opening; 30. a first test pad; 31. a second test pad.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In describing positional relationships, unless otherwise specified, when an element such as a layer, film or substrate is referred to as being "on" another layer, it can be directly on the other layer or intervening layers may also be present. Further, when a layer is referred to as being "under" another layer, it can be directly under, or one or more intervening layers may also be present. It will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
Where the terms "comprising," "having," and "including" are used herein, another element may be added unless an explicit limitation is used, such as "only," "consisting of … …," etc. Unless mentioned to the contrary, terms in the singular may include the plural and are not to be construed as being one in number.
With the continuous reduction of the volume of semiconductor devices, the application of the nano probe technology in the field of semiconductor technology is wider and wider. Among them, the nanoprobe technology can be used to measure the capacitance in a semiconductor structure, but with the precondition that the nanoprobes are located in the same plane. The capacitance structure of the existing DRAM is generally columnar, the upper electrode and the lower electrode are positioned on different planes, and the capacitance value of the DRAM is difficult to measure by applying a nano probe technology. In order to solve the above problems, the present application provides a semiconductor test structure and a method for manufacturing the same, so as to implement measurement of a capacitance value of a DRAM by using a nanoprobe technology.
As shown in fig. 1, one embodiment of the present application provides a method for fabricating a semiconductor test structure, including:
s11: providing a semiconductor structure, wherein the semiconductor structure comprises a substrate 11 and a capacitor array structure positioned on the front surface of the substrate 11, the capacitor array structure comprises a plurality of capacitors arranged in an array, the lower electrode 22 of each capacitor is connected with the substrate 11 through a capacitor contact structure 12, the upper electrodes 20 of each capacitor share the same capacitor plate 26, and the capacitor plate 26 extends to the lower part of one side of the capacitor array structure.
S12: and thinning the back of the semiconductor structure until the capacitor contact structure 12 is exposed.
S13: the edge region of the capacitor array structure is etched from the bottom of the resulting structure until the capacitor plates 26 are exposed.
S14: a first test pad 30 is formed on the bottom of the exposed capacitor plate 26.
The semiconductor structure provided in step S11 is shown in fig. 2, and includes a substrate 11 and a capacitor array structure disposed on a front surface of the substrate 11. The base 11 includes a substrate 111 and a first dielectric layer 112 on an upper surface of the substrate 111. Shallow trench isolation structures 13 and a plurality of word lines (not shown) arranged in parallel at intervals are formed in the substrate 111, and the shallow trench isolation structures 13 isolate a plurality of active regions 14 arranged in an array in the substrate 111. A plurality of bit lines 16 are formed in the first dielectric layer 112 and spaced apart in parallel, and the capacitor contact structure 12 is located between adjacent bit lines 16 and contacts the active region 14. As an example, the bit line 16 may specifically be a titanium nitride layer 162 and a tungsten layer 161 stacked from bottom to top, the bit line 16 is provided with a bit line capping dielectric layer 17 on the upper portion and the lower portion, and the bit line 16 and both sides of the bit line capping dielectric layer 17 are provided with bit line sidewalls 18. It is to be understood that a bit line contact structure 19 is also formed between the bit line 16 and the active region 14, and the bit line 16 and the active region 14 are electrically connected through the bit line contact structure 19.
With reference to fig. 2, the capacitor array structure includes a plurality of capacitors arranged in an array, wherein the capacitors include an upper electrode 20, a lower electrode 22, and a second dielectric layer 21. In general, in order to improve the stability of the capacitor array structure, several support layers are further disposed in the capacitor array structure, for example, in the capacitor array structure in this embodiment, a top support layer 23, a middle support layer 24, and a bottom support layer 25 are included. The lower electrode 22 of each capacitor is connected to the base 11 through a capacitive contact structure 12, as shown in fig. 2, the capacitive contact structure 12 penetrating the first dielectric layer 112 and contacting the active region 14 in the substrate 111. The upper electrodes 20 share the same capacitor plate 26, and the capacitor plate 26 extends to a lower portion of one side of the capacitor array structure, for example, the capacitor plate 26 is in contact with the upper surface of the substrate 11.
In step S12, the semiconductor structure is back-thinned until the capacitive contact structure 12 is exposed. As an example, the step of back thinning the semiconductor structure includes: and thinning the back surface of the base 11 by adopting a chemical mechanical polishing process until the substrate 111, part of the first dielectric layer 112 and the bit line 16 are removed until the capacitor contact structure 12 is exposed. The back side of the semiconductor structure is thinned to obtain a schematic cross-sectional structure shown in fig. 3.
In step S13, the edge region of the capacitor array structure is etched from the bottom of the resulting structure until the capacitor plate 26 is exposed. The method comprises the following specific steps:
s131: the edge region of the capacitor array structure is etched from the bottom of the resulting structure to form a first opening 27, the first opening 27 exposing the capacitor plate 26.
As an example, the focused ion beam process may be used to etch the edge region of the capacitor array structure from the bottom of the resulting structure to form the first opening 27, and the etched first opening 27 is shown in fig. 4. A first opening 27 extends through the dielectric layer and exposes a portion of the capacitor plate 26.
S132: a filling dielectric layer 28 is formed in the first opening 27, and the filling dielectric layer 28 fills the first opening 27.
By way of example, a focused ion beam process may be used to form the fill dielectric layer 28 within the first opening 27. The fill dielectric layer 28 may be a silicon oxide layer. A cross-sectional view of the resulting semiconductor structure after forming the fill dielectric layer 28 is shown in fig. 5.
S133: a second opening 29 is formed in the filling dielectric layer 28, and the capacitor plate 26 is exposed from the second opening 29.
By way of example, the focused ion beam process may be used to etch the fill dielectric layer 28 to form a second opening 29 in the fill dielectric layer 28. The width of the second opening 29 is smaller than the width of the first opening 27. A schematic cross-sectional view of the resulting semiconductor structure after forming the second opening 29 is shown in fig. 6.
In step S14, a first test pad 30 is formed on the bottom of the exposed capacitor plate 26. As an example, a first test pad 30 may be formed in the second opening 29, as shown in fig. 7. The material of the first test pad 30 may be metal tungsten or platinum. The lower surface of the first testing pad 30 is flush with the exposed lower surface of the capacitor contact structure 12, so that when the nanoprobes are connected to the capacitor contact structure 12 and the first testing pad 30, the nanoprobes are in the same plane, and thus, the capacitance in the semiconductor structure can be measured by using the nanoprobe technology.
The lower surface of the semiconductor test structure exposes the capacitance contact structure 12 and the first test pad 30, and the surfaces of the capacitance contact structure 12 and the first test pad 30 are located on the same plane, and the capacitance value of the capacitor corresponding to the capacitance contact structure 12 can be measured by respectively connecting the nano probe to the surface of the capacitance contact structure 12 and the surface of the first test pad 30.
In one embodiment, the capacitive contact structure 12 includes a contact pad. And thinning the back of the semiconductor structure until the lower surface of the contact pad is exposed. The lower surface of the first test pad 30 formed in the second opening 29 is flush with the lower surface of the contact pad. When the nano probe technology is used for capacitance measurement, the nano probes are respectively in contact with the lower surface of the contact pad and the lower surface of the first test pad 30, so that the nano probes are in the same plane.
In one embodiment, as shown in fig. 8, a second test pad 31 may be formed on the bottom of the exposed capacitor contact structure 12 while forming the first test pad 30 in the second opening 29. Wherein the lower surface of the second test pad 31 is flush with the lower surface of the first test pad 30. When the nano-probe technique is used for capacitance measurement, the nano-probes are respectively in contact with the lower surfaces of the second test pad 31 and the first test pad 30, so that the nano-probes are in the same plane.
In one embodiment, the number of the second test pads 31 is the same as the number of the capacitors, and the second test pads 31 are disposed in one-to-one correspondence with the capacitors, as shown in fig. 9, so that the nanoprobe can measure the capacitance value of each capacitor.
In one embodiment, the number of second test pads 31 is less than the number of capacitors, each second test pad 31 connecting a capacitive contact structure 12 of a plurality of capacitors, as shown in fig. 10. Because the volume of a single capacitor is small and the capacitance value is also small, the second test pads 31 with different areas can be deposited in the array region after the back surface is thinned to expose the capacitor contact structure 12, and the number of the capacitors covered by the second test pads 31 can be calculated according to the area of the single capacitor. And after the capacitance value is obtained through the measurement of the nano probe, the capacitance value of a single capacitor can be obtained by dividing the capacitance number by the capacitance value. By the method, the measurement precision of the capacitance can be improved, and the problem that the measurement cannot be accurate due to the fact that a single capacitance value is too small is avoided.
As an example, one second test pad 31 may be prepared under four adjacent capacitive contact structures 12, or one second test pad 31 may be prepared under six adjacent capacitive contact structures 12. After the capacitance value is measured, the capacitance value of a single capacitor is obtained by dividing by the number of capacitors contacted by the second test pad 31.
Since the capacitors at different positions in the array region may have different capacitance values, in order to reduce errors and improve the test accuracy, the second test pads 31 may be disposed at different positions in the array region, for example, the second test pads 31 may be disposed at the middle and edge positions of the array region, respectively. It should be noted that, no matter the position of the second test pad 31 is disposed at the center or the edge of the array region, it is necessary to ensure that the lower surface of the second test pad 31 is flush with the lower surface of the first test pad 30.
An embodiment of the present application also provides a semiconductor test structure, as shown in fig. 7, including: the capacitor array structure comprises a plurality of capacitors arranged in an array; the capacitor contact structures 12 are arranged corresponding to the capacitors one by one and are positioned at the bottom of the lower electrode 22 of each capacitor; a capacitor plate 26 connected to the upper electrode 20 of each capacitor and extending to a lower portion of one side of the capacitor array structure; the first test pad 30 is located at a lower portion of the capacitor plate 26 and contacts the capacitor plate 26.
The capacitor includes an upper electrode 20, a lower electrode 22, and a second dielectric layer 21. The lower electrode 22 of each capacitor is connected to the capacitor contact structure 12, the upper electrodes 20 share the same capacitor plate 26, and the capacitor plate 26 extends to the lower part of one side of the capacitor array structure. The first test pad 30 is disposed under the capacitor plate 26, and is formed on the basis of the capacitor plate 26 and penetrates the dielectric layer to expose the lower surface of the first test pad 30. The lower surface of the first test pad 30 is flush with the lower surface of each of the capacitor contact structures 12. As an example, the first test pad 30 may be metal tungsten or metal platinum. The capacitor plate 26 may be doped polysilicon.
The semiconductor test structure can be used for measuring capacitance in nano-measurement technology. Since the lower surfaces of the first testing pad 30 and the capacitance contact structure 12 are in the same plane, the capacitance value of a single capacitor can be measured by respectively disposing the nanoprobes on the lower surface of the first testing pad 30 and the lower surface of the capacitance contact structure 12. The semiconductor test structure solves the problem that the traditional DRAM structure can not directly adopt the nano probe technology to measure the capacitance.
In one embodiment, the semiconductor test structure further includes a fill dielectric layer 28. A fill dielectric layer 28 is located on the lower surface of the capacitor plate 26 and a first test pad 30 is located within the fill dielectric layer 28.
In one embodiment, as shown in FIG. 8, the semiconductor test structure further includes a second test pad 31 located at the bottom of the capacitive contact structure 12; the lower surface of the second test pad 31 is flush with the lower surface of the first test pad 30.
In one embodiment, as shown in fig. 9, the number of the second test pads 31 is the same as the number of the capacitors, and the second test pads 31 are disposed in one-to-one correspondence with the capacitors. By providing the second test pad 31 at the capacitive contact structure 12 under each capacitor, the measurement object can be flexibly selected when the nanoprobe technology is applied to measure the capacitance value of the capacitor in the semiconductor structure.
In one embodiment, as shown in fig. 10, the number of second test pads 31 is less than the number of capacitors, each second test pad 31 connecting a capacitive contact structure 12 of a plurality of capacitors. Because the volume of a single capacitor is small, and the capacitance value is also small, the second test pads 31 with different areas can be deposited in the array area, and the number of the capacitors covered by the second test pads 31 can be calculated according to the area of the single capacitor. After the nanoprobe technology is applied to the semiconductor test structure in this embodiment, the capacitance value may be obtained by measuring the nanoprobe technology, and then dividing by the number of capacitors, so as to obtain the capacitance value of a single capacitor. By the method, the capacitance measurement precision can be improved, and the problem that the single capacitance value is too small to be accurately measured is solved.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (15)
1. A method for fabricating a semiconductor test structure, comprising:
providing a semiconductor structure, wherein the semiconductor structure comprises a substrate and a capacitor array structure positioned on the front surface of the substrate, the capacitor array structure comprises a plurality of capacitors arranged in an array manner, the lower electrode of each capacitor is connected with the substrate through a capacitor contact structure, the upper electrodes of the capacitors share the same capacitor plate, and the capacitor plate extends to the lower part of one side of the capacitor array structure;
thinning the back of the semiconductor structure until the capacitor contact structure is exposed;
etching the edge area of the capacitor array structure from the bottom of the obtained structure until the capacitor polar plate is exposed;
and forming a first test pad at the bottom of the exposed capacitor plate.
2. The method for manufacturing a semiconductor test structure according to claim 1, wherein the substrate comprises a substrate and a dielectric layer disposed on an upper surface of the substrate, a shallow trench isolation structure and a plurality of word lines arranged in parallel at intervals are formed in the substrate, and the shallow trench isolation structure isolates a plurality of active regions arranged in an array in the substrate; a plurality of bit lines which are arranged in parallel at intervals are formed in the dielectric layer; the capacitor contact structure is positioned between the adjacent bit lines and is in contact with the active region; the back face thinning of the semiconductor structure comprises:
and thinning the back of the base until the substrate, part of the dielectric layer and the bit line are removed until the capacitor contact structure is exposed.
3. The method of claim 1, wherein etching the edge region of the capacitor array structure from the bottom of the resulting structure until the capacitor plate is exposed comprises:
etching the edge area of the capacitor array structure from the bottom of the obtained structure to form a first opening, wherein the capacitor polar plate is exposed out of the first opening;
forming a filling medium layer in the first opening, wherein the filling medium layer fills the first opening;
forming a second opening in the filling dielectric layer, wherein the capacitor plate is exposed out of the second opening; the first test pad is formed in the second opening.
4. The method of claim 3, wherein the focused ion beam process is used to etch the edge region of the capacitor array structure from the bottom of the resulting structure to form the first opening; forming the filling dielectric layer by adopting a focused ion beam process; and etching the filling medium layer by adopting a focused ion beam process so as to form the second opening in the filling medium layer.
5. The method as claimed in claim 3, wherein a silicon oxide layer is formed in the first opening as the filling dielectric layer.
6. The method of claim 3, wherein the width of the second opening is less than the width of the first opening.
7. The method of fabricating a semiconductor test structure according to any of claims 1 to 6, wherein a second test pad is formed on the bottom of the exposed capacitive contact structure while the first test pad is formed.
8. The method of fabricating a semiconductor test structure according to claim 7, wherein a lower surface of the second test pad is flush with a lower surface of the first test pad.
9. The method of claim 7, wherein the number of the second test pads is the same as the number of the capacitors, and the second test pads are arranged in one-to-one correspondence with the capacitors.
10. The method of fabricating a semiconductor test structure according to claim 7, wherein the number of second test pads is less than the number of capacitors, each of the second test pads being connected to the capacitive contact structure of a plurality of the capacitors.
11. A semiconductor test structure, comprising:
the capacitor array structure comprises a plurality of capacitors arranged in an array;
the capacitor contact structures are arranged in one-to-one correspondence with the capacitors and are positioned at the bottoms of the lower electrodes of the capacitors;
the capacitor plate is connected with the upper electrode of each capacitor and extends to the lower part of one side of the capacitor array structure;
and the first test pad is positioned at the lower part of the capacitor plate and is in contact with the capacitor plate.
12. The semiconductor test structure of claim 11, further comprising:
the filling dielectric layer is positioned on the lower surface of the capacitor plate; the first test pad is located within the dielectric fill layer.
13. The semiconductor test structure of claim 11, further comprising:
a second test pad located at the bottom of the capacitive contact structure; the lower surface of the second test pad is flush with the lower surface of the first test pad.
14. The semiconductor test structure of claim 13, wherein the number of the second test pads is the same as the number of the capacitors, the second test pads being arranged in one-to-one correspondence with the capacitors.
15. The semiconductor test structure of claim 13, wherein the number of second test pads is less than the number of capacitors, each second test pad connecting the capacitive contact structures of a plurality of the capacitors.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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Cited By (4)
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| WO2023273016A1 (en) * | 2021-07-02 | 2023-01-05 | 长鑫存储技术有限公司 | Semiconductor test structure and preparation method therefor |
| CN115802745A (en) * | 2022-11-21 | 2023-03-14 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor device, semiconductor device and DRAM |
| TWI799041B (en) * | 2021-10-08 | 2023-04-11 | 南亞科技股份有限公司 | Benchmark device on a semiconductor wafer with fuse element and method for operating the same |
| US11876024B2 (en) | 2021-10-08 | 2024-01-16 | Nanya Technology Corporation | Method for operating a benchmark device on a semiconductor wafer with fuse element |
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| CN107993949A (en) * | 2017-11-16 | 2018-05-04 | 长江存储科技有限责任公司 | The test method of three-dimensional storage bit line capacitance |
| CN109283410A (en) * | 2018-09-11 | 2019-01-29 | 长鑫存储技术有限公司 | Capacity measurement device and forming method thereof |
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| US11876024B2 (en) | 2021-10-08 | 2024-01-16 | Nanya Technology Corporation | Method for operating a benchmark device on a semiconductor wafer with fuse element |
| CN115802745A (en) * | 2022-11-21 | 2023-03-14 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor device, semiconductor device and DRAM |
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| WO2023273016A1 (en) | 2023-01-05 |
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