WO2023272700A1

WO2023272700A1 - Temperature control apparatus and method

Info

Publication number: WO2023272700A1
Application number: PCT/CN2021/104085
Authority: WO
Inventors: 王海峰; 黄俊林; 康文红; 钟进国
Original assignee: 华为技术有限公司
Priority date: 2021-07-01
Filing date: 2021-07-01
Publication date: 2023-01-05
Also published as: CN117083529A

Abstract

A temperature control apparatus, comprising: a processor (110) and a temperature compensation apparatus (120), wherein the processor (110) is used for inputting a target operating frequency of a vector to be tested and said vector into a chip (130) to be tested, and during the process of said chip (130) executing said vector at the target operating frequency, the processor is used for controlling a junction temperature of said chip (130) by means of controlling the temperature compensation apparatus (120); and the temperature compensation apparatus (120) is used for compensating for the junction temperature of said chip (130). The target operating frequency is determined according to a reference power; the vector to be tested is any one of a plurality of test vectors of said chip (130); and the reference power is used for indicating a fluctuation benchmark of the power of said vector. Therefore, the difficulty in controlling the junction temperature of said chip (130) is reduced.

Description

Temperature control device and method

technical field

The present application relates to the technical field of temperature control, in particular to a temperature control device and method.

Background technique

Before the chip leaves the factory, it needs to be tested according to the requirements, for example, Burn-in test and ATE (Automatic Test Equipment, automated test equipment) test, etc., to ensure that there are no quality problems in the shipped chip.

During the chip testing process, the junction temperature of the chip needs to be controlled. For example, the junction temperature of the chip is controlled not to exceed the irreversible failure temperature of the chip, so as to avoid irreversible damage to the chip due to the junction temperature of the chip exceeding the irreversible failure temperature. Another example is to control the junction temperature of the chip at a temperature that can expose the weak point of the chip, and the temperature that can expose the weak point of the chip does not exceed the irreversible failure temperature of the chip. In this way, it can be effectively screened without causing irreversible damage to the chip. Defective chip.

With the development of technology, the power consumption of chips is increasing. For chips with high power consumption, there are large differences in power consumption between different test vectors. Since the chip generates heat when executing the test vector, and the generated heat is positively correlated with the power consumption of the test vector. Therefore, when the chip is switched between test vectors with large power consumption differences, large thermal fluctuations will be generated, which increases the difficulty of controlling the chip junction temperature.

Contents of the invention

The present application provides a temperature control method and device for reducing the difficulty of controlling the chip junction temperature.

In a first aspect, the present application provides a temperature control method, including: inputting the target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested; In the process of the vector to be measured, the junction temperature of the chip to be tested is controlled by controlling the temperature compensation device; wherein, the target operating frequency is determined according to the reference power, and the vector to be measured is the multiplicity of the chip to be tested. Any one of the test vectors, the reference power is used to indicate the fluctuation reference of the power of the vector to be tested.

The target operating frequency of the vector to be measured is determined according to the reference power, and the reference power is used to indicate the fluctuation reference of the power of the vector to be measured, that is, the target operating frequency of the vector to be measured is determined with the reference power as a reference, so as to limit the power of the vector to be measured Within the range of the reference power as the benchmark, the power consumption of the vector to be tested is limited within a certain range, which reduces the power consumption difference between different vectors to be tested, thereby reducing the time when the chip to be tested switches between different vectors to be tested. , resulting in heat fluctuations, thereby reducing the difficulty of controlling the junction temperature of the chip to be tested.

In a possible implementation manner, the controlling the junction temperature of the chip under test includes: controlling the junction temperature of the chip under test below a target temperature; Determine the test item to which the test vector belongs.

In a possible implementation, if the default power of the vector to be measured is less than or equal to the reference power, the target operating frequency is the default operating frequency of the vector to be measured; If the default power is greater than the reference power, the target operating frequency is the minimum operating frequency in the operable frequency range of the vector to be measured; wherein, the default power of the vector to be measured is that the vector to be measured is in the The power at the default operating frequency, the default operating frequency of the vector to be measured is an operating frequency in the operable frequency range of the vector to be measured.

In a possible implementation manner, the temperature compensation device includes a cooling device; the inputting the target operating frequency of the vector to be measured and the vector to be measured into the chip to be tested includes: if the vector to be measured is within the target The power at the operating frequency is greater than the reference power, then increase the power of the cooling device, and input the target operating frequency of the vector to be measured and the vector to be measured into the chip to be tested; if the If the power of the vector under test at the target operating frequency is less than or equal to the reference power, the target operating frequency of the vector under test and the vector under test are input into the chip under test.

In a possible implementation manner, the reference power is the power of a reference vector, and the reference vector is one of multiple test vectors of the chip under test.

In a possible implementation manner, the controlling the junction temperature of the chip under test includes: maintaining the junction temperature of the chip under test at a target temperature; The test item to which it belongs is determined.

In a possible implementation manner, the target operating frequency is a first operating frequency in the operable frequency range of the vector to be measured; wherein, the power of the vector to be measured at the first operating frequency is the highest close to the reference power.

In a possible implementation manner, the temperature compensation device includes a heating device; the inputting the target operating frequency of the vector to be measured and the vector to be measured into the chip to be tested includes: setting the power of the heating device, and, Inputting the target operating frequency of the vector under test and the vector under test into the chip under test; wherein the power of the heating device is determined according to the power and total power of the vector under test at the target operating frequency The total power is the sum of the power of the test vector and the power of the heating device that the chip under test is running when the junction temperature of the chip under test is maintained at the target temperature.

In a possible implementation manner, the reference power is the power of a reference vector, and the reference vector is one of a plurality of test vectors of the chip under test; or the reference power is the total power, wherein the The total power is the sum of the power of the test vectors running on the chip under test and the power of the heating device when the junction temperature of the chip under test is maintained at the target temperature.

In a possible implementation manner, controlling the junction temperature of the chip under test by controlling the temperature compensation device includes: obtaining the temperature sensor from at least one temperature sensor in contact with the package of the chip under test The shell temperature of the chip to be tested; according to the shell temperature of the chip to be tested, and by controlling the temperature compensation device, the junction temperature of the chip to be tested is controlled; or from at least one temperature sensor in the chip to be tested obtaining the junction temperature of the chip to be tested; controlling the junction temperature of the chip to be tested according to the junction temperature of the chip to be tested by controlling a temperature compensation device.

In a second aspect, the present application provides a temperature control device, including: a processor and a temperature compensation device; wherein, the processor is configured to input the target operating frequency of the vector to be measured and the vector to be measured into the chip to be tested, And, during the process of the chip under test executing the vector under test at the target operating frequency, the junction temperature of the chip under test is controlled by controlling the temperature compensation device; the temperature compensation device uses Compensating the junction temperature of the chip under test; the target operating frequency is determined according to a reference power, the vector under test is any one of a plurality of test vectors of the chip under test, and the reference power is used for A fluctuation reference indicating the power of the vector under test.

In a possible implementation manner, the processor is specifically configured to control the junction temperature of the chip to be tested below a target temperature; wherein the target temperature is determined according to a test item to which the vector to be tested belongs.

In a possible implementation manner, the temperature compensation device includes a cooling device; the processor is specifically configured to: if the power of the vector to be measured at the target operating frequency is greater than the reference power, the increased the power of the cooling device, and input the target operating frequency of the vector to be measured and the vector to be tested into the chip to be tested; if the power of the vector to be measured at the target operating frequency is less than or equal to For the reference power, input the target operating frequency of the vector under test and the vector under test into the chip under test.

In a possible implementation manner, the processor is specifically configured to maintain the junction temperature of the chip under test at a target temperature; wherein the target temperature is determined according to a test item to which the vector under test belongs.

In a possible implementation manner, the temperature compensation device includes a heating device; the processor is specifically configured to set the power of the heating device, and set the target operating frequency of the vector to be measured and the target operating frequency of the vector to be measured to The measured vector is input to the chip under test; wherein, the power of the heating device is determined according to the power and the total power of the vector to be measured at the target operating frequency; the total power is the junction of the chip under test When the temperature is maintained at the target temperature, the sum of the power of the running test vector of the chip under test and the power of the heating device.

In a possible implementation manner, at least one temperature sensor is arranged in the chip to be tested; the device also includes: a test substrate, a probe base, a pressing block and a heat sink, wherein: the probe base is set On the test substrate, it is used to place the chip to be tested, and electrically connect the pins of the chip to be tested to the test substrate through the probes in the probe holder; the pressing block, Located on the chip to be tested, it is used to apply pressure to the chip to be tested; the heat sink is arranged on the pressing block, and is used to bring out the temperature of the chip to be tested; the processor, specifically Inputting the target operating frequency of the vector to be tested and the vector to be tested into the chip under test through the test substrate, and executing the target operating frequency of the chip under test at the target operating frequency In the process of vector measurement, the junction temperature of the chip under test is controlled according to the junction temperature of the chip under test obtained from the at least one temperature sensor and by controlling the temperature compensation device.

In a possible implementation manner, the device further includes: a test substrate, a probe base, a pressing block, a thermal resistance module, at least one temperature sensor, and a heat sink, wherein: the probe base is arranged on the test The substrate is used to place the chip to be tested, and electrically connect the pins of the chip to be tested to the test substrate through the probes in the probe base; the thermal resistance module is located on the The chip to be tested is used to equalize the temperature between the chip to be tested and the pressing block; the pressing block is located on the thermal resistance module and is used to apply pressure to the chip to be tested; the at least A temperature sensor is in contact with the package body of the chip to be tested, and is used to measure the shell temperature of the chip to be tested; the heat sink is arranged on the pressing block, and is used to take out the temperature; the processor is specifically configured to input the target operating frequency of the vector under test and the vector under test into the chip under test through the test substrate, and, when the chip under test is in the During the process of executing the vector under test at the target operating frequency, according to the shell temperature of the chip under test obtained from the at least one temperature sensor and by controlling the temperature compensation device, the temperature of the chip under test is adjusted. The junction temperature is controlled.

In a third aspect, the present application provides a computer-readable storage medium, including a computer program. When the computer program is executed on a computer or a processor, the computer or processor executes any one of the methods described in the first aspect. Methods.

In a fourth aspect, the present application provides a computer program, which is used to execute the method described in any one of the first aspects when the computer program is executed by a computer or a processor.

In a fifth aspect, the present application provides an electronic device, including the temperature control device according to any one of the second aspect.

Description of drawings

FIG. 1 is a schematic structural view of a temperature control device provided in an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a temperature control device in a first application scenario provided by an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a temperature control device in a second application scenario provided by an embodiment of the present application;

FIG. 4 is a schematic structural diagram of a temperature control device in a third application scenario provided by an embodiment of the present application;

FIG. 5 is a schematic structural diagram of a temperature control device in a fourth application scenario provided by an embodiment of the present application;

FIG. 6 is a schematic structural diagram of a processor provided in an embodiment of the present application;

FIG. 7 is a schematic flowchart of a temperature control method provided in an embodiment of the present application.

detailed description

The technical solution in this application will be described below with reference to the accompanying drawings.

In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings in this application. Obviously, the described embodiments are part of the embodiments of this application , but not all examples. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

The terms "first" and "second" in the description, embodiments, claims and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be interpreted as indicating or implying relative importance, nor can they be interpreted as indicating or imply order. Furthermore, the terms "comprising" and "having", as well as any variations thereof, are intended to cover a non-exclusive inclusion, for example, of a sequence of steps or elements. A method, system, product or device is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to the process, method, product or device.

It should be understood that in this application, "at least one (item)" means one or more, and "multiple" means two or more. "And/or" is used to describe the association relationship of associated objects, indicating that there can be three types of relationships, for example, "A and/or B" can mean: only A exists, only B exists, and A and B exist at the same time , where A and B can be singular or plural. The character "/" generally indicates that the contextual objects are an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one item (piece) of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c ", where a, b, c can be single or multiple.

In order to solve the above technical problems, the present application provides a temperature control device, which can control the power consumption of the test vector within a certain range, reduce the power consumption difference between different test vectors, thereby reducing the power consumption of the chip under test. When switching between different test vectors, the generated heat fluctuates, thereby reducing the difficulty of controlling the junction temperature of the chip under test.

It should be noted that the chip to be tested here refers to a packaged chip, that is, the chip to be tested includes a bare chip (that is, the chip itself) and a package. The junction temperature of the chip under test refers to the temperature of the die in the chip under test.

The principle of the temperature control device provided by the application is as follows:

Since the power consumption of the test vector is greater, the chip under test generates more heat when executing the test vector. And because the power consumption of the test vector is positively correlated with the power of the test vector. Therefore, the greater the power of the test vector, the more heat will be generated when the chip under test executes the test vector.

The power of the test vector can be calculated by the following formula:

P _n is the power of test vector n, k _n is the constant of test vector n, V _n is the IO port voltage when the chip under test executes test vector n, f _n (k) is the operating frequency of test vector n, [fmin, fmax] is the operating frequency range of the test vector n, f _n (k)∈[fmin, fmax], fmin and fmax are determined by the chip to be tested.

It should be noted that different test vectors correspond to different k _n , different test vectors correspond to different V _n , and different test vectors have the same operable frequency range [fmin, fmax].

Since the operating frequency of the test vector has an operable frequency range, the power of the test vector can be adjusted by adjusting the operating frequency of the test vector.

Based on this, the power of the test vector can be adjusted by adjusting the operating frequency of the test vector, and then the power consumption of the test vector can be adjusted to control the power consumption of the test vector within a certain range and reduce the power consumption difference between different test vectors. Furthermore, the heat fluctuation generated when the chip to be tested is switched between different test vectors is reduced, thereby reducing the difficulty of controlling the junction temperature of the chip to be tested.

Next, a temperature control device constructed based on the above-mentioned principle will be described.

FIG. 1 is a schematic structural diagram of a temperature control device provided by an embodiment of the present application. As shown in FIG. 1 , the temperature control device includes: a processor 110 and a temperature compensation device 120 . in:

The processor 110 includes, but is not limited to, a central processing unit (CPU), a microcontroller (MCU), a digital signal processor (DSP), a neural processing unit (NPU), or a microprocessor. The processor 110 is used to input the target operating frequency of the vector to be tested and the vector to be tested into the chip 130 to be tested, and, during the process of the chip 130 to be tested executing the vector to be tested at the target operating frequency, by controlling the temperature compensation device 120, The junction temperature of the chip under test 130 is controlled. The target operating frequency of the vector to be measured is determined according to the reference power. The test vector is any one of the multiple test vectors of the chip under test 130 . The reference power is used to indicate the fluctuation reference of the power of the vector to be measured. The temperature compensation device 120 is used for compensating the junction temperature of the chip 130 to be tested. The specific implementation manner of the temperature compensation device 120 is determined according to the application scenario of the temperature control device. For example, the temperature compensating device 120 includes a heating device and a cooling device. For another example, the temperature compensating device 120 includes a cooling device. The heating device includes but is not limited to a heating rod, and the cooling device includes but is not limited to a fan, a water cooling device, and the like.

It can be seen from the above that the target operating frequency of the vector to be measured is determined according to the reference power, and the reference power is used to indicate the fluctuation reference of the power of the vector to be measured, that is, the target operating frequency of the vector to be measured is determined with the reference power as a reference, so that the target operating frequency of the vector to be measured is determined. The power of the vector is limited within the reference power range, thereby limiting the power consumption of the vector to be tested within a certain range, reducing the power consumption difference between different vectors to be tested, and further reducing the power consumption of the chip 130 to be tested under different conditions. When the measurement vectors are switched, the generated heat fluctuates, thereby reducing the difficulty of controlling the junction temperature of the chip under test 130 .

Since the temperature control device controls the junction temperature of the chip 130 to be tested during the process of testing the chip 130 to be tested, the relevant components for testing the chip 130 to be tested may be included in the temperature control device, or may not be included in the temperature control device. In the control device, this application does not make any special limitation.

When controlling the junction temperature of the chip under test 130 , there are the following two situations for the basic quantity used. in:

First, the basic data is the shell temperature of the chip under test 130 , that is, the shell temperature of the chip under test 130 is obtained, and the junction temperature of the chip under test 130 is controlled by the shell temperature of the chip under test 130 .

In the second type, the basic data is the junction temperature of the chip under test 130 , that is, the junction temperature of the chip under test 130 is obtained, and the junction temperature of the chip under test 130 is controlled by the junction temperature of the chip under test 130 .

When controlling the junction temperature of the chip under test 130 , the target of temperature control has the following two situations. in:

The first method is to control the junction temperature of the chip under test 130 below the target temperature. The target temperature is determined according to the test item to which the vector to be tested belongs. The test items include but are not limited to: ATE test, functional test and other test items that need to control the junction temperature of the chip under test 130 below a certain temperature. For example, the target temperature is the irreversible failure temperature of the chip under test 130 .

The second method is to maintain the junction temperature of the chip under test 130 at the target temperature. The target temperature is determined according to the test item to which the vector to be tested belongs. The test items include but not limited to: burn-in test, burn-in test and other test items that need to maintain the junction temperature of the chip under test 130 at a certain temperature. For example, the target temperature is a temperature capable of exposing weak points of the chip 130 to be tested.

Due to the different basic data used, the relevant components for testing the chip 130 to be tested are different. Also, due to the different temperature control goals, the methods of determining the reference power, the specific implementation form of the temperature compensation device 120 , and the methods of determining the target operating frequency of the vector to be measured are all different. Therefore, in the following, the structure and operation process of the temperature control device including the relevant components for testing the chip 130 to be tested will be described in detail under four application scenarios consisting of two types of basic data and two types of temperature control targets.

FIG. 2 is a schematic structural diagram of a temperature control device in a first application scenario provided by an embodiment of the present application. In the first application scenario, the basic data used is the junction temperature of the chip under test 130 , and the goal of temperature control is to control the junction temperature of the chip under test 130 below the target temperature.

Because the basic data adopted is the junction temperature of the chip under test 130, therefore, at least one temperature sensor (not shown in Fig. 2 ) needs to be set in the chip under test 130, to obtain the junction temperature of the chip under test 130 by at least one temperature sensor. temperature. Implementations of the temperature sensor include but are not limited to PN junctions. Since the goal of temperature control is to control the junction temperature of the chip under test 130 below the target temperature, the temperature compensating device 120 is a cooling device 121 .

As shown in FIG. 2 , the temperature control device includes: a processor 110 , a cooling device 121 , a test substrate 140 , a probe base 150 , a pressing block 160 and a radiator 170 . in:

The probe base 150 is arranged on the test substrate 140 , and the probe base 150 is used to place the chip under test 130 , and electrically connect the pins of the chip under test 130 to the test substrate 140 through the probes in the probe base 150 .

The pressing block 160 is located on the chip to be tested 130 , and the pressing block 160 is used to apply pressure to the chip to be tested 130 to ensure that the pins of the chip to be tested 130 are in full contact with the probes.

The radiator 170 is arranged on the pressing block 160, and the radiator 170 is used to take out the temperature of the chip 130 to be tested, so as to exchange the taken out temperature with the cooling device 121, so as to lower the temperature.

The processor 110 is disposed on the test substrate 140 . The test substrate 140 is provided with a printed circuit (not shown in FIG. 4 ), and the processor 110 is connected with the probes in the probe holder 150 through the printed circuit on the test substrate 140. In this way, the processor 110 can pass the printed circuit and The probes communicate with the chip under test 130 and provide power signals to the chip under test 130 . In addition, the cooling device 121 is connected to the printed circuit on the test substrate 140 , so that the processor 110 can provide a power signal to the cooling device 121 through the printed circuit and control the cooling device 121 .

It should be noted that, in other embodiments, the processor 110 can also be arranged outside the test substrate 140 , and the processor 110 and the cooling device 121 can also be connected to the test substrate through an electrical connector provided on the test substrate 140 . The electrical connectors are connected to the printed circuit on the test substrate 140 .

The processor 110 is used to provide a power signal to the chip 130 to be tested, input the target operating frequency of the vector to be tested and the vector to be tested into the chip 130 to be tested, and execute the chip 130 under the target operating frequency of the vector to be tested In the process of the vector to be measured, obtain the junction temperature of the chip to be tested 130 from at least one temperature sensor in the chip to be tested 130, according to the obtained junction temperature of the chip to be tested 130, and by controlling the cooling device 121, the chip to be tested The junction temperature of 130 is controlled below the target temperature. The processor 110 is also configured to provide a power signal to the cooling device 121 and control the cooling device 121 .

The methods for determining the reference power include but are not limited to the following two methods:

First, the reference power may be the power of a reference vector, and the reference vector is one of the multiple test vectors of the chip 130 under test. Specifically, the reference vector may be any one of the multiple test vectors of the chip under test 130 . The reference vector may also be a designated test vector among the multiple test vectors of the chip under test 130 , for example, the test vector with the largest power when the operating frequency is the smallest. The power of the reference vector can be obtained according to the above formula for calculating the power of the test vector. It should be noted that, the operating frequency used when calculating the power of the reference vector may be an operating frequency within the operable frequency range of the reference vector.

Second, the reference power may be one of the power ranges of the multiple test vectors of the chip under test 130 . Specifically, the reference power may be any power in the power ranges of the multiple test vectors of the chip under test 130 . The reference power may also be a specified power in the power ranges of the multiple test vectors of the chip under test 130 , for example, the middle value of the power range. The process of determining the power ranges of the multiple test vectors of the chip 130 to be tested is: calculating the power range of each test vector in the multiple test vectors, and combining the power ranges of the test vectors to obtain the power ranges of the multiple test vectors scope. It should be noted that, the above description about the reference power is only exemplary, and is not intended to limit the present application.

The method of determining the target operating frequency of the vector to be measured is: comparing the default power of the vector to be measured with the reference power. Wherein, the default power of the vector to be tested is the power of the vector to be tested at the default operating frequency of the vector to be tested. The default operating frequency of the vector to be tested is an operating frequency in the range of operable frequencies of the vector to be tested. Specifically, the default operating frequency of the vector to be tested may be any operating frequency in the range of operable frequencies of the vector to be tested. The default operating frequency of the vector to be measured may also be an operating frequency specified in the operable frequency range of the vector to be measured, for example, the middle value or the minimum value of the operable frequency range. If the default power of the vector under test is less than or equal to the reference power, the target operating frequency of the vector under test is the default operating frequency of the vector under test. If the default power of the vector to be tested is greater than the reference power, the target operating frequency of the vector to be tested is the minimum operating frequency in the operable frequency range of the vector to be tested.

Below, an example is given to illustrate the testing and temperature control process. The specific process is as follows:

The processor 110 inputs the operating frequency of the vector under test 1 and the vector under test 1 into the chip under test 130 . The operating frequency of the vector 1 to be tested is an operating frequency within the range of operable frequencies of the vector 1 to be tested.

When the chip under test 130 executes the test vector 1 at the operating frequency of the test vector 1 , the processor 110 obtains the junction temperature of the test chip 130 from at least one temperature sensor in the test chip 130 .

The processor 110 compares the junction temperature of the chip to be tested 130 with the target temperature, and if the junction temperature of the chip to be tested 130 is greater than the target temperature, then increase the power of the cooling device 121 to strengthen the cooling of the chip to be tested 130, for example, Increase the speed of the fan to accelerate heat dissipation until the junction temperature of the chip under test 130 is maintained below the target temperature. Take the vector 1 to be measured as the reference vector, and calculate the power of the reference vector according to the above formula, and use the power of the reference vector as the reference power. Ways to increase the power of the cooling device 121 include but not limited to increasing the operating voltage and/or current of the cooling device 121 .

The processor 110 determines the target running frequency of the vector 2 to be tested. Specifically, if the default power of the vector 2 to be measured is less than or equal to the reference power, the default operating frequency of the vector 2 to be measured is determined as the target operating frequency of the vector 2 to be measured. If the default power of the vector under test 2 is greater than the reference power, the minimum operating frequency in the operable frequency range of the vector under test 2 is determined as the target operating frequency of the vector under test 2 .

The processor 110 inputs the target operating frequency of the vector under test 2 and the vector under test 2 into the chip under test 130 .

During the process of the chip under test 130 executing the vector under test 2 at the target operating frequency of the vector under test 2, the processor 110 obtains the junction temperature of the chip under test 130 from at least one temperature sensor in the chip under test 130, and According to the junction temperature of the chip under test 130, combined with PID algorithm, linear temperature control algorithm, etc., and by controlling the cooling device 121, the junction temperature of the chip under test 130 is dynamically adjusted so that the junction temperature of the chip under test 130 is lower than the target temperature.

Based on the principle of executing vector 2 to be tested, the remaining vectors to be tested are executed.

It can be seen from the above that the calculation of the reference power and the target operating frequency of the vector under test is calculated in real time during the process of testing and temperature control. In other embodiments of the present application, the reference power and the target operating frequency of the vector to be measured can also be calculated in advance offline. That is, the reference power and the target operating frequency of each of the multiple test vectors are calculated in advance, so that during the test, the target operating frequency of the vector to be tested can be obtained directly from the target operating frequencies of the multiple test vectors, No online calculations are required.

In order to increase the stability and precision of temperature control and ensure the stability of the temperature of the chip under test 130, before the target operating frequency of the vector under test and the vector under test are input into the chip under test 130, the processor 110 can also calculate the vector under test Power at the target operating frequency, compare the power of the vector to be measured at the target operating frequency with the reference power, if the power of the vector to be measured at the target operating frequency is greater than the reference power, then increase the power of the cooling device 121 first, In order to increase the cooling force, the target operating frequency of the vector to be tested and the vector to be tested are input into the chip 130 to be tested. If the power of the vector under test at the target operating frequency is less than or equal to the reference power, then input the target operating frequency of the vector under test and the vector under test into the chip under test 130 without adjusting the power of the cooling device 121 .

Obviously, before the vector to be tested is input into the chip under test 130 , if the power of the vector under test at the target operating frequency is greater than the reference power, then increase the power of the cooling device 121 to increase the cooling force of the chip under test 130 . That is, the power of the cooling device 121 is predicted in advance, and the power of the cooling device 121 is adjusted according to the prediction result to perform temperature compensation in advance, which improves the stability and accuracy of temperature control, and ensures the stability of the temperature of the chip 130 to be tested. sex.

It should be noted that the test substrate 140 , the probe holder 150 , the pressing block 160 and the heat sink 170 are related components for testing the chip 130 to be tested.

Fig. 3 is a schematic structural diagram of a temperature control device in a second application scenario provided by an embodiment of the present application. In the second application scenario, the basic data used is the case temperature of the chip under test 130 , and the goal of temperature control is to control the junction temperature of the chip under test 130 below the target temperature.

The structural difference between the temperature control device in FIG. 3 and the temperature control device in FIG. 2 is that: a thermal resistance module 180 and at least one temperature sensor 190 are added to the temperature control device shown in FIG. 3 . Wherein, the thermal resistance module 180 is located between the chip 130 to be tested and the compact 160, and the thermal resistance module 180 is used to balance the temperature between the chip 130 to be tested and the compact 160, so as to improve the measurement accuracy of the shell temperature of the chip 130 to be tested. . The material of the thermal resistance module 180 can be, for example, indium, etc., which is not limited in this application. Since in this scenario, the basic data used is the shell temperature of the chip under test 130, therefore, there is no need to arrange a temperature sensor in the chip under test 130, and at least one temperature sensor 190 needs to be set on the package of the chip under test 130 to The case temperature of the chip under test 130 is obtained through the at least one temperature sensor 190 . At least one temperature sensor 190 is connected to the printed circuit on the test substrate 140, and the processor 110 is connected to the at least one temperature sensor 190 through the printed circuit, so as to provide a power signal to the at least one temperature sensor 190, and obtain the target value from the at least one temperature sensor 190. The case temperature of the chip 130 is measured.

The difference between the temperature control device in FIG. 3 and the temperature control device in FIG. 2 in the execution flow is: in the process of controlling the junction temperature of the chip 130 to be tested, the processor 110 is in contact with the package body of the chip 130 to be tested. Obtain the shell temperature of the chip to be tested 130 in at least one temperature sensor 190 of the chip to be tested, estimate the junction temperature of the chip to be tested 130 according to the shell temperature of the chip to be tested 130, then, according to the junction temperature of the speculated chip to be tested 130, and by controlling the temperature drop The device 121 controls the junction temperature of the chip under test 130 to be below the target temperature.

It should be noted that the test substrate 140 , the probe holder 150 , the pressing block 160 , the thermal resistance module 180 , at least one temperature sensor 190 and the heat sink 170 are related components for testing the chip 130 to be tested.

FIG. 4 is a schematic structural diagram of a temperature control device in a third application scenario provided by an embodiment of the present application. In the third application scenario, the basic data used is the junction temperature of the chip under test 130 , and the goal of temperature control is to maintain the junction temperature of the chip under test 130 at the target temperature. It should be noted that maintaining the junction temperature of the chip under test 130 at the target temperature means that the absolute value of the difference between the target temperature and the junction temperature of the chip under test 130 is less than a preset error value, and the preset error value can be set according to design requirements. Certainly.

Since the goal of temperature control is to maintain the junction temperature of the chip under test 130 at the target temperature, the temperature compensating device 120 includes a cooling device 121 and a heating device 122 .

The structural difference between the temperature control device in FIG. 4 and the temperature control device in FIG. 2 is that a heating device 122 is added to the temperature control device shown in FIG. 4 .

The positional relationship of the cooling device 121 , the test substrate 140 , the probe base 150 , the pressure block 160 and the heat sink 170 and the functions of each component have been described in FIG. 2 , and will not be repeated here. The heating device 122 is arranged in the compact 160 . It should be noted that, in other embodiments, the heating device 122 may also be disposed between the pressing block 160 and the chip 130 to be tested, which is not specifically limited in this application. The heating device 122 is connected to the printed circuit on the test substrate 140 . The processor 110 provides a power signal to the heating device 122 through the printed circuit, and controls the heating device 122, for example, increasing the power of the heating device 122 to increase the heating intensity of the chip 130 to be tested, and for example, reducing the heating power of the heating device 122. power, so as to weaken the heating intensity of the chip 130 to be tested. Ways to increase the power of the heating device 122 include but are not limited to increasing the operating voltage and/or current of the heating device 122 . The manner of reducing the power of the heating device 122 includes but not limited to reducing the operating voltage and/or current of the heating device 122 .

The processor 110 is used to provide a power signal to the chip 130 to be tested, input the target operating frequency of the vector to be tested and the vector to be tested into the chip 130 to be tested, and execute the chip 130 under the target operating frequency of the vector to be tested In the process of the vector to be measured, the junction temperature of the chip to be tested 130 is obtained from at least one temperature sensor in the chip to be tested 130, according to the obtained junction temperature of the chip to be tested 130, and by controlling the cooling device 121 and/or the heating device 122. Control and maintain the junction temperature of the chip under test 130 at the target temperature. The processor 110 is also used to provide power signals to the cooling device 121 and the heating device 122 , and to control the cooling device 121 and the heating device 122 .

The methods for determining the reference power include but are not limited to the following three methods:

The first type, the reference power is the power of the reference vector, the reference vector and the power of the reference vector have been described above, and will not be repeated here.

Second, the reference power may also be a power in the power range of multiple test vectors of the chip under test 130 . The second method has been described above and will not be repeated here.

The third type is that the reference power is the total power, wherein the total power is the sum of the power of the test vector and the power of the heating device 122 that the chip under test 130 is running when the junction temperature of the chip under test 130 is maintained at the target temperature.

The way to determine the target operating frequency of the vector to be measured is: the target operating frequency of the vector to be measured is the first operating frequency in the operable frequency range of the vector to be measured; wherein, the power of the vector to be measured at the first operating frequency is closest to the reference power.

Obviously, by determining the operating frequency when the power of the vector to be measured is closest to the reference power as the target operating frequency of the vector to be measured, the power of the vector to be measured at the target operating frequency is closest to the reference power, that is, by adjusting the target operating frequency, Make the power of the vector to be measured close to the reference power to control the power of the vector to be measured within a certain range, thereby controlling the power consumption of the vector to be measured within a certain range, reducing the power consumption difference between different vectors to be measured, and reducing When the chip under test 130 is switched between different vectors under test, the generated heat fluctuates, thereby reducing the difficulty of controlling the junction temperature of the chip under test 130 .

When the chip under test 130 executes the test vector 1 at the running frequency of the test vector 1 , the processor 110 obtains the junction temperature of the test chip 130 from at least one temperature sensor in the test chip 130 .

The processor 110 compares the junction temperature of the chip to be tested 130 with the target temperature, and if the junction temperature of the chip to be tested 130 is greater than the target temperature, then increase the power of the cooling device 121 to strengthen the cooling strength of the chip to be tested 130 and/or Reduce the power of the heating device 122 to reduce the heating intensity of the chip under test 130, for example, increase the speed of the fan, accelerate heat dissipation, reduce the power of the heating rod, and reduce the heating efficiency until the junction temperature of the chip under test 130 is maintained at the target temperature. If the junction temperature of the chip to be tested 130 is less than the target temperature, then increase the power of the heating device 122 to increase the heating intensity of the chip to be tested 130 and/or reduce the power of the cooling device 121 to reduce the cooling intensity of the chip to be tested 130, For example, increase the power of the heating rod, accelerate heating, reduce the rotation speed of the fan, and reduce the heat dissipation efficiency until the junction temperature of the chip 130 under test is maintained at the target temperature.

Under the condition that the junction temperature of the chip to be tested 130 is maintained at the target temperature, the vector to be measured 1 is used as the reference vector, and according to the above formula, the power of the reference vector is calculated, and the power of the reference vector is used as the reference power, or the vector to be measured is determined The power of 1 and the power of the heating device 122 are added to the power of the vector 1 to be measured and the power of the heating device 122 to obtain the total power, and the total power is used as the reference power.

The processor 110 determines the target operating frequency of the vector to be measured 2, wherein the target operating frequency of the vector to be measured 2 is the first operating frequency in the operable frequency range of the vector to be measured 2; The power at the frequency is closest to the reference power.

During the process of the chip under test 130 executing the vector under test 2, the processor 110 obtains the junction temperature of the chip under test 130 from at least one temperature sensor in the chip under test 130, and according to the junction temperature of the chip under test 130, combines PID algorithm, linear temperature control algorithm, etc., and dynamically adjust the junction temperature of the chip under test 130 by controlling the cooling device 121 and/or the heating device 122, so as to maintain the junction temperature of the chip under test 130 at the target temperature.

In order to increase the stability and precision of temperature control and ensure the stability of the temperature of the chip under test 130, before the vector to be measured is input into the chip under test 130, the processor 110 can also determine the power of the heating device 122, and then set the heating device 122 power, and then input the target operating frequency of the vector under test and the vector under test into the chip under test 130 .

The way to determine the power of the heating device 122 is: if the difference between the total power and the power of the vector to be measured at the target operating frequency is greater than 0, then the power of the heating device 122 is the difference; if the total power and the vector to be measured are within the target operating frequency If the power difference at the operating frequency is not greater than 0, then the power of the heating device 122 is 0.

Obviously, before the vector to be measured is input into the chip 130 to be tested, the power of the heating device 122 is determined according to the power and the total power of the vector to be measured at the target operating frequency, and the power of the heating device 122 is set, that is, the power of the heating device 122 is predicted in advance. power, and set the power of the heating device 122 according to the prediction result to perform temperature compensation in advance, which improves the stability and accuracy of temperature control, and ensures the stability of the temperature of the chip 130 to be tested.

FIG. 5 is a schematic structural diagram of a temperature control device in a fourth application scenario provided by an embodiment of the present application. In the fourth application scenario, the basic data used is the case temperature of the chip under test 130 , and the goal of temperature control is to maintain the junction temperature of the chip under test 130 at the target temperature.

The structural difference between the temperature control device in FIG. 5 and the temperature control device in FIG. 4 lies in that a thermal resistance module 180 and at least one temperature sensor 190 are added to the temperature control device shown in FIG. 5 . Wherein, the thermal resistance module 180 is located between the chip 130 to be tested and the compact 160, and the thermal resistance module 180 is used to balance the temperature between the chip 130 to be tested and the compact 160, so as to improve the accuracy of the measurement of the shell temperature of the chip 130 to be tested. Spend. The materials of the thermal resistance module 180 have been described above, and will not be repeated here. Since in this scenario, the basic data used is the shell temperature of the chip under test 130, therefore, there is no need to arrange a temperature sensor in the chip under test 130, and at least one temperature sensor 190 needs to be set on the package of the chip under test 130 to The case temperature of the chip under test 130 is obtained through the at least one temperature sensor 190 . At least one temperature sensor 190 is connected to the printed circuit on the test substrate 140, and the processor 110 is connected to the at least one temperature sensor 190 through the printed circuit, so as to provide a power signal to the at least one temperature sensor 190, and obtain the target value from the at least one temperature sensor 190. The case temperature of the chip 130 is measured.

The difference in execution flow between the temperature control device in FIG. 5 and the temperature control device in FIG. Obtain the case temperature of the chip under test 130 in at least one temperature sensor of the device, estimate the junction temperature of the chip under test 130 according to the case temperature of the chip under test 130, then, according to the junction temperature of the chip under test 130 estimated, and by controlling the cooling device 121 and/or the heating device 122 to maintain the junction temperature of the chip under test 130 at the target temperature.

It can be seen from the above that, in the scenario where the basic data used is the junction temperature of the chip under test 130 , the components used to test the chip under test 130 are relatively simple and the cost is low.

FIG. 6 is a schematic structural diagram of a processor provided in an embodiment of the present application. As shown in FIG. 6 , the processor 110 includes: a test vector control circuit 111 , a temperature obtaining circuit 112 , a test vector sending circuit 113 and a temperature compensation control circuit 114 . Wherein: the test vector control circuit 111 is used to determine the target operating frequency of the test vector, and send the target operating frequency of the test vector and the test vector to the test vector sending circuit 113 . The test vector sending circuit 113 is used for inputting the target operating frequency of the vector under test and the vector under test into the chip under test 130 . The temperature obtaining circuit 112 is used to obtain the junction temperature of the chip under test 130 or the shell temperature of the chip under test 130 , and transmit the junction temperature of the chip under test 130 or the shell temperature of the chip under test 130 to the test vector control circuit 111 . The test vector control circuit 111 is also used to generate a temperature control signal according to the junction temperature of the chip under test 130 or the shell temperature of the chip under test 130 combined with the target temperature, and transmit the temperature control signal to the temperature compensation control circuit 114 . The temperature compensation control circuit 114 is used to control the temperature compensation device 120 in response to the temperature control signal, for example, when the temperature compensation device 120 is the temperature reduction device 121, increase or decrease the power of the temperature reduction device 121 to strengthen or weaken the temperature reduction device 121 For another example, when the temperature compensating device 120 is the heating device 122 , the power of the heating device 122 is increased or decreased to increase or decrease the heating power of the heating device 122 .

It should be noted that, the foregoing description about the processor 110 is only exemplary, and is not intended to limit this embodiment.

The present application also provides a temperature control method, as shown in FIG. 7 , the temperature control method includes: 701. Input the target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested. 702. During the process of the chip under test executing the vector under test at the target operating frequency, control the junction temperature of the chip under test by controlling a temperature compensation device; wherein the target operating frequency Determined according to the reference power, the vector under test is any one of a plurality of test vectors of the chip under test, and the reference power is used to indicate a fluctuation reference of the power of the vector under test.

The implementation principles and technical effects of the above temperature control method of the present application have been described above, and will not be repeated here.

The present application also provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed on a computer or a processor, the computer or processor executes any one of the above method embodiments technical solutions.

The present application also provides a computer program product, which, when the computer program is executed by a computer, causes the computer or processor to execute the technical solution of any one of the above method embodiments.

The present application also provides an electronic device, including the above-mentioned temperature control device.

The present application also provides a chip, including a processor and a memory, and the processor is configured to execute the technical solution of any one of the above method embodiments.

Further, the chip may further include a memory and a communication interface. The communication interface may be an input/output interface, a pin, or an input/output circuit.

In the implementation process, each step of the above-mentioned method embodiment can be completed by an integrated logic circuit of hardware in the network card or an instruction in the form of software. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other possible Program logic devices, discrete gate or transistor logic devices, discrete hardware components. A general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like. The steps of the methods disclosed in the embodiments of the present application can be directly implemented by a hardware coded processor, or executed by a combination of hardware and software modules in the coded processor. The software module can be located in a mature storage medium in the field such as random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, register. The storage medium is located in the memory, and the processor reads the information in the memory, and completes the steps of the above method in combination with its hardware.

The memories mentioned in the above embodiments may be volatile memories or nonvolatile memories, or may include both volatile and nonvolatile memories. Among them, the non-volatile memory can be read-only memory (read-only memory, ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically programmable Erases programmable read-only memory (electrically EPROM, EEPROM) or flash memory. Volatile memory can be random access memory (RAM), which acts as external cache memory. By way of illustration and not limitation, many forms of RAM are available such as static random access memory (static RAM, SRAM), dynamic random access memory (dynamic RAM, DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous connection dynamic random access memory (synchlink DRAM, SLDRAM ) and direct memory bus random access memory (direct rambus RAM, DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but not be limited to, these and any other suitable types of memory.

Those skilled in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present application.

Those skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the above-described system, device and unit can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.

If the functions described above are realized in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (personal computer, server, or network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (read-only memory, ROM), random access memory (random access memory, RAM), magnetic disk or optical disc and other media that can store program codes. .

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims

A temperature control method, characterized in that, comprising:

Inputting the target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested;

During the process of the chip under test executing the vector under test at the target operating frequency, the junction temperature of the chip under test is controlled by controlling the temperature compensation device;

Wherein, the target operating frequency is determined according to a reference power, the vector to be tested is any one of a plurality of test vectors of the chip under test, and the reference power is used to indicate a fluctuation reference of the power of the vector to be tested .
The method according to claim 1, wherein the controlling the junction temperature of the chip under test comprises:

controlling the junction temperature of the chip under test below the target temperature;

Wherein, the target temperature is determined according to the test item to which the vector to be tested belongs.
The method according to claim 2, characterized in that,

If the default power of the vector to be measured is less than or equal to the reference power, the target operating frequency is the default operating frequency of the vector to be measured;

If the default power of the vector to be measured is greater than the reference power, the target operating frequency is the smallest operating frequency in the operable frequency range of the vector to be measured;

Wherein, the default power of the vector to be tested is the power of the vector to be tested at the default operating frequency, and the default operating frequency of the vector to be tested is one of the operating frequency ranges of the vector to be measured. frequency.
The method according to claim 2 or 3, wherein the temperature compensating device comprises a cooling device;

Said inputting the target operating frequency of the vector to be tested and said vector to be tested into the chip to be tested comprises:

If the power of the vector to be measured at the target operating frequency is greater than the reference power, then increase the power of the cooling device, and input the target operating frequency of the vector to be measured and the vector to be measured The chip to be tested;

If the power of the vector under test at the target operating frequency is less than or equal to the reference power, then input the target operating frequency of the vector under test and the vector under test into the chip under test.
The method according to any one of claims 2 to 4, wherein the reference power is the power of a reference vector, and the reference vector is one of a plurality of test vectors of the chip under test.
The method according to claim 1, wherein the controlling the junction temperature of the chip under test comprises:

maintaining the junction temperature of the chip under test at a target temperature;

Wherein, the target temperature is determined according to the test item to which the vector to be tested belongs.
The method according to claim 6, wherein the target operating frequency is the first operating frequency in the operable frequency range of the vector to be measured;

Wherein, the power of the vector to be measured at the first operating frequency is closest to the reference power.
The method according to claim 6 or 7, wherein the temperature compensating device comprises a heating device;

Said inputting the target operating frequency of the vector to be tested and said vector to be tested into the chip to be tested comprises:

Setting the power of the heating device, and inputting the target operating frequency of the vector under test and the vector under test into the chip under test;

Wherein, the power of the heating device is determined according to the power and total power of the vector to be measured at the target operating frequency;

The total power is the sum of the power of the test vectors running on the chip under test and the power of the heating device when the junction temperature of the chip under test is maintained at the target temperature.
The method according to any one of claims 6 to 8, wherein the reference power is the power of a reference vector, and the reference vector is one of a plurality of test vectors of the chip under test; or

The reference power is the total power, wherein the total power is the power of the test vector running on the chip under test and the power of the heating device when the junction temperature of the chip under test is maintained at the target temperature. sum of power.
The method according to any one of claims 1 to 9, wherein controlling the junction temperature of the chip under test by controlling the temperature compensation device includes:

Obtaining the case temperature of the chip under test from at least one temperature sensor in contact with the package of the chip under test;

controlling the junction temperature of the chip to be tested according to the case temperature of the chip to be tested by controlling a temperature compensation device; or

Obtaining the junction temperature of the chip under test from at least one temperature sensor in the chip under test;

According to the junction temperature of the chip to be tested, the junction temperature of the chip to be tested is controlled by controlling the temperature compensation device.
A temperature control device, characterized in that it includes: a processor and a temperature compensation device; wherein,

The processor is configured to input the target operating frequency of the vector to be tested and the vector to be tested into the chip under test, and during the process that the chip under test executes the vector to be tested at the target operating frequency , controlling the junction temperature of the chip under test by controlling the temperature compensation device;

The temperature compensation device is used to compensate the junction temperature of the chip under test;

The target operating frequency is determined according to a reference power, the vector to be tested is any one of a plurality of test vectors of the chip under test, and the reference power is used to indicate a fluctuation reference of the power of the vector to be tested.
The device according to claim 11, wherein the processor is specifically configured to control the junction temperature of the chip under test below the target temperature;

Wherein, the target temperature is determined according to the test item to which the vector to be tested belongs.
The device according to claim 12, characterized in that,

If the default power of the vector to be measured is less than or equal to the reference power, the target operating frequency is the default operating frequency of the vector to be measured;

If the default power of the vector to be measured is greater than the reference power, the target operating frequency is the smallest operating frequency in the operable frequency range of the vector to be measured;

Wherein, the default power of the vector to be tested is the power of the vector to be tested at the default operating frequency, and the default operating frequency of the vector to be tested is one of the operating frequency ranges of the vector to be measured. frequency.
The device according to claim 12 or 13, wherein the temperature compensating device comprises a cooling device;

The processor is specifically configured to increase the power of the cooling device if the power of the vector under test at the target operating frequency is greater than the reference power, and to operate the target vector of the vector under test frequency and the vector to be measured are input into the chip to be tested; if the power of the vector to be measured at the target operating frequency is less than or equal to the reference power, the target operating frequency of the vector to be measured and the The vector to be tested is input into the chip to be tested.
The device according to any one of claims 12-14, wherein the reference power is the power of a reference vector, and the reference vector is one of a plurality of test vectors of the chip under test.
The device according to claim 11, wherein the processor is specifically configured to maintain the junction temperature of the chip under test at a target temperature;

Wherein, the target temperature is determined according to the test item to which the vector to be tested belongs.
The device according to claim 16, wherein the target operating frequency is the first operating frequency in the operable frequency range of the vector to be measured;

Wherein, the power of the vector to be measured at the first operating frequency is closest to the reference power.
The device according to claim 16 or 17, wherein the temperature compensation device comprises a heating device;

The processor is specifically configured to set the power of the heating device, and input the target operating frequency of the vector under test and the vector under test into the chip under test;

Wherein, the power of the heating device is determined according to the power and total power of the vector to be measured at the target operating frequency;

The total power is the sum of the power of the test vectors running on the chip under test and the power of the heating device when the junction temperature of the chip under test is maintained at the target temperature.
The device according to any one of claims 16 to 18, wherein the reference power is the power of a reference vector, and the reference vector is one of a plurality of test vectors of the chip under test; or

The reference power is the total power, wherein the total power is the power of the test vector running on the chip under test and the power of the heating device when the junction temperature of the chip under test is maintained at the target temperature. sum of power.
The device according to any one of claims 11-19, characterized in that at least one temperature sensor is arranged in the chip to be tested;

The device also includes: a test substrate, a probe holder, a pressing block and a heat sink, wherein:

The probe base is arranged on the test substrate for placing the chip to be tested, and the pins of the chip to be tested are electrically connected to the test substrate through the probes in the probe base. connect;

The pressure block is located on the chip under test and is used to apply pressure to the chip under test;

The heat sink is arranged on the pressing block, and is used to bring out the temperature of the chip to be tested;

The processor is specifically configured to input the target operating frequency of the vector under test and the vector under test into the chip under test through the test substrate, and, when the chip under test runs at the target During the process of executing the vector under test at a high frequency, according to the junction temperature of the chip under test obtained from the at least one temperature sensor, and by controlling the temperature compensation device, the junction temperature of the chip under test Take control.
The device according to any one of claims 11-19, wherein the device further comprises: a test substrate, a probe base, a pressing block, a thermal resistance module, at least one temperature sensor and a heat sink, wherein:

The probe base is arranged on the test substrate for placing the chip to be tested, and the pins of the chip to be tested are electrically connected to the test substrate through the probes in the probe base. connect;

The thermal resistance module is located on the chip under test and is used to equalize the temperature between the chip under test and the compact;

The pressing block is located on the thermal resistance module and is used to apply pressure to the chip under test;

The at least one temperature sensor is in contact with the package of the chip under test, and is used to measure the case temperature of the chip under test;

The heat sink is arranged on the pressing block, and is used to bring out the temperature of the chip to be tested;

The processor is specifically configured to input the target operating frequency of the vector under test and the vector under test into the chip under test through the test substrate, and, when the chip under test runs at the target During the process of executing the vector under test at a high frequency, the junction temperature of the chip under test is adjusted according to the case temperature of the chip under test obtained from the at least one temperature sensor and by controlling the temperature compensation device. Take control.
A computer-readable storage medium, comprising a computer program, which, when executed on a computer or a processor, causes the computer or processor to execute the method according to any one of claims 1-10.
A computer program for performing the method according to any one of claims 1-10 when said computer program is executed by a computer or a processor.
An electronic device comprising the temperature control device according to any one of claims 11-21.