CN117083529A - Temperature control device and method - Google Patents

Abstract

A temperature control device, comprising: a processor (110) and a temperature compensation device (120); the processor (110) is configured to input a target operating frequency of a vector to be tested and the vector to be tested into the chip to be tested (130), and control a junction temperature of the chip to be tested (130) by controlling the temperature compensation device (120) in a process that the chip to be tested (130) executes the vector to be tested at the target operating frequency. And the temperature compensation device (120) is used for compensating the junction temperature of the chip (130) to be tested. The target operating frequency is determined based on a reference power, which is used to indicate a fluctuating basis for the power of the vector under test, the vector under test being any one of a plurality of test vectors for the chip under test (130). The difficulty in controlling the junction temperature of the chip (130) to be tested is reduced.

Description

Temperature control device and method Technical field

The present application relates to the technical field of temperature control, and specifically to a temperature control device and method.

Background technique

Before the chip leaves the factory, it needs to be tested according to requirements, such as Burn-in test and ATE (Automatic Test Equipment, automated test equipment) test, etc., to ensure that there are no quality problems in the chip shipped from the factory.

During the chip testing process, the junction temperature of the chip needs to be controlled. For example, the junction temperature of the chip is controlled not to exceed the irreversible failure temperature of the chip to avoid irreversible damage to the chip due to the junction temperature of the chip exceeding the irreversible failure temperature. For another example, the junction temperature of the chip is controlled to a temperature that can expose the weak points of the chip. The temperature that can expose the weak points of the chip does not exceed the irreversible failure temperature of the chip. In this way, it can effectively screen without causing irreversible damage to the chip. Defective chip.

With the development of technology, the power consumption of chips is increasing. For high-power consumption chips, there are large differences in power consumption between different test vectors. When the chip executes the test vector, it will generate heat, and the heat generated is positively correlated with the power consumption of the test vector. Therefore, when the chip switches between test vectors with large differences in power consumption, large heat fluctuations will occur, making it more difficult to control the chip junction temperature.

Contents of the invention

This application provides a temperature control method and device for reducing the difficulty of controlling chip junction temperature.

In a first aspect, the present application provides a temperature control method, which includes: inputting the target operating frequency of the vector to be measured and the vector to be measured into the chip to be tested; and executing the process at the target operating frequency of the chip under test. During the process of measuring the vector, the junction temperature of the chip under test is controlled by controlling the temperature compensation device; wherein, the target operating frequency is determined based on the reference power, and the vector to be measured is the multiple of the chip under test. Any one of the test vectors, the reference power is used to indicate the fluctuation standard of the power of the vector to be measured.

The target operating frequency of the vector to be measured is determined based on the reference power. The reference power is used to indicate the fluctuation baseline of the power of the vector to be measured. That is, the target operating frequency of the vector to be measured is determined based on the reference power to limit the power of the vector to be measured. Within the range based on the reference power, the power consumption of the vector to be measured is limited to a certain range, reducing the power consumption difference between different vectors to be measured, thereby reducing the time required for the chip under test to switch between different vectors to be measured. , the generated heat fluctuations reduce the difficulty of controlling the junction temperature of the chip under test.

In a possible implementation, the controlling the junction temperature of the chip under test includes: controlling the junction temperature of the chip under test below a target temperature; wherein the target temperature is determined according to the The test item to which the measurement vector belongs is determined.

In a possible implementation, if the default power of the vector to be measured is less than or equal to the reference power, the target operating frequency is the default operating frequency of the vector to be measured; if the default power of the vector to be measured is If the default power is greater than the reference power, then the target operating frequency is the smallest operating frequency in the operable frequency range of the vector to be measured; wherein, the default power of the vector to be measured is the vector to be measured in the The power at the default operating frequency. The default operating frequency of the vector to be measured is an operating frequency in the operable frequency range of the vector to be measured.

In a possible implementation, the temperature compensation device includes a cooling device; inputting the target operating frequency of the vector to be measured and the vector to be measured into the chip to be measured includes: if the vector to be measured is in the target If the power at the operating frequency is greater than the reference power, increase the power of the cooling device, and input the target operating frequency of the vector to be measured and the vector to be measured into the chip to be tested; if the vector to be measured is If the power of the measured vector at the target operating frequency is less than or equal to the reference power, then the target operating frequency of the vector to be measured and the vector to be measured are input to the chip to be measured.

In a possible implementation, the reference power is the power of a reference vector, and the reference vector is one of multiple test vectors of the chip under test.

In a possible implementation, the controlling the junction temperature of the chip under test includes: maintaining the junction temperature of the chip under test at a target temperature; wherein the target temperature is determined according to the vector under test The test project to which it belongs is determined.

In a possible implementation, the target operating frequency is the first operating frequency in the operable frequency range of the vector to be measured; wherein the power of the vector to be measured at the first operating frequency is the highest. close to the reference power.

In a possible implementation, the temperature compensation device includes a heating device; inputting the target operating frequency of the vector to be measured and the vector to be measured into the chip to be measured includes: setting the power of the heating device, and, The target operating frequency of the vector to be measured and the vector to be measured are input into the chip to be measured; wherein the power of the heating device is determined based on the power and total power of the vector to be measured at the target operating frequency. ; The total power is the sum of the power of the test vector that the chip under test is running and the power of the heating device when the junction temperature of the chip under test is maintained at the target temperature.

In a possible implementation, the reference power is the power of a reference vector, and the reference vector is one of multiple test vectors of the chip under test; or the reference power is the total power, where The total power is the sum of the power of the test vector that the chip under test is running and the power of the heating device when the junction temperature of the chip under test is maintained at the target temperature.

In a possible implementation, controlling the junction temperature of the chip under test by controlling the temperature compensation device includes: obtaining the temperature sensor from at least one temperature sensor in contact with the package of the chip under test. The shell temperature of the chip under test; controlling the junction temperature of the chip under test according to the shell temperature of the chip under test and by controlling the temperature compensation device; or from at least one temperature sensor in the chip under test Obtain the junction temperature of the chip under test; control the junction temperature of the chip under test according to the junction temperature of the chip under test and by controlling the temperature compensation device.

In a second aspect, this application provides a temperature control device, including: a processor and a temperature compensation device; wherein the processor is used to input the target operating frequency of the vector to be measured and the vector to be measured into the chip to be tested, And, in the process of the chip under test executing the vector under test at the target operating frequency, the junction temperature of the chip under test is controlled by controlling a temperature compensation device; the temperature compensation device is used To compensate the junction temperature of the chip under test; the target operating frequency is determined according to the reference power, the vector to be measured is any one of multiple test vectors of the chip under test, and the reference power is used for Indicates the fluctuation reference of the power of the vector to be measured.

In a possible implementation, the processor is specifically configured to control the junction temperature of the chip under test below a target temperature; wherein the target temperature is determined according to the test item to which the vector under test belongs.

In a possible implementation, if the default power of the vector to be measured is less than or equal to the reference power, the target operating frequency is the default operating frequency of the vector to be measured; if the default power of the vector to be measured is If the default power is greater than the reference power, then the target operating frequency is the smallest operating frequency in the operable frequency range of the vector to be measured; wherein, the default power of the vector to be measured is the vector to be measured in the The power at the default operating frequency. The default operating frequency of the vector to be measured is an operating frequency in the operable frequency range of the vector to be measured.

In a possible implementation, the temperature compensation device includes a cooling device; the processor is specifically configured to increase the power of the vector to be measured at the target operating frequency if it is greater than the reference power. The power of the cooling device, and inputting the target operating frequency of the vector to be measured and the vector to be measured into the chip to be measured; if the power of the vector to be measured at the target operating frequency is less than or equal to The reference power is input to the chip under test, the target operating frequency of the vector to be measured and the vector to be measured.

In a possible implementation, the reference power is the power of a reference vector, and the reference vector is one of multiple test vectors of the chip under test.

In a possible implementation, the processor is specifically configured to maintain the junction temperature of the chip under test at a target temperature; wherein the target temperature is determined according to the test item to which the vector under test belongs.

In a possible implementation, the target operating frequency is the first operating frequency in the operable frequency range of the vector to be measured; wherein the power of the vector to be measured at the first operating frequency is the highest. close to the reference power.

In a possible implementation, the temperature compensation device includes a heating device; the processor is specifically configured to set the power of the heating device, and combine the target operating frequency of the vector to be measured and the vector to be measured. The measured vector is input to the chip under test; wherein, the power of the heating device is determined based on the power of the vector to be measured at the target operating frequency and the total power; the total power is the junction of the chip under test. When the temperature is maintained at the target temperature, the power of the test vector that the chip under test is running is the sum of the power of the heating device.

In a possible implementation, the reference power is the power of a reference vector, and the reference vector is one of multiple test vectors of the chip under test; or the reference power is the total power, where The total power is the sum of the power of the test vector that the chip under test is running and the power of the heating device when the junction temperature of the chip under test is maintained at the target temperature.

In a possible implementation, at least one temperature sensor is provided in the chip under test; the device further includes: a test substrate, a probe holder, a pressure block and a heat sink, wherein: the probe holder is provided On the test substrate, the chip to be tested is placed, and the pins of the chip to be tested are electrically connected to the test substrate through probes in the probe holder; the pressure block, The heat sink is located on the chip to be tested and is used to apply pressure to the chip to be tested; the heat sink is provided on the pressure block and is used to bring out the temperature of the chip to be tested; the processor, specifically For inputting the target operating frequency of the vector to be measured and the vector to be measured into the chip to be tested through the test substrate, and executing the chip to be tested at the target operating frequency. During the vector measurement process, the junction temperature of the chip under test is controlled based on the junction temperature of the chip under test obtained from the at least one temperature sensor and by controlling the temperature compensation device.

In a possible implementation, the device further includes: a test substrate, a probe holder, a pressure block, a thermal resistance module, at least one temperature sensor and a heat sink, wherein: the probe holder is disposed on the test The substrate is used to place the chip under test and electrically connect the pins of the chip under test to the test substrate through the probes in the probe holder; the thermal resistance module is located on the On the chip to be tested, it is used to equalize the temperature between the chip to be tested and the pressing block; the pressing block is located on the thermal resistance module and is used to apply pressure to the chip to be tested; the at least A temperature sensor is in contact with the package of the chip to be tested and is used to measure the shell temperature of the chip to be tested; the heat sink is provided on the pressure block and is used to bring out the temperature of the chip to be tested. temperature; the processor is specifically configured to input the target operating frequency of the vector to be measured and the vector to be measured into the chip under test through the test substrate, and, when the chip under test is in the During the process of executing the vector under test at the target operating frequency, based on the shell temperature of the chip under test obtained from the at least one temperature sensor and by controlling the temperature compensation device, the temperature of the chip under test is adjusted. Junction temperature is controlled.

In a third aspect, the present application provides a computer-readable storage medium, including a computer program. When the computer program is executed on a computer or processor, the computer or processor causes the computer or processor to execute any one of the first aspects. Methods.

In a fourth aspect, the present application provides a computer program, which when the computer program is executed by a computer or processor, is used to perform the method described in any one of the first aspects.

In a fifth aspect, the present application provides an electronic device, including the temperature control device according to any one of the second aspects.

Description of the drawings

Figure 1 is a schematic structural diagram of a temperature control device provided by an embodiment of the present application;

Figure 2 is a schematic structural diagram of the temperature control device in the first application scenario provided by the embodiment of the present application;

Figure 3 is a schematic structural diagram of the temperature control device in the second application scenario provided by the embodiment of the present application;

Figure 4 is a schematic structural diagram of the temperature control device in the third application scenario provided by the embodiment of the present application;

Figure 5 is a schematic structural diagram of a temperature control device in the fourth application scenario provided by the embodiment of the present application;

Figure 6 is a schematic structural diagram of a processor provided by an embodiment of the present application;

Figure 7 is a schematic flowchart of a temperature control method provided by an embodiment of the present application.

Detailed ways

The technical solutions in this application will be described below with reference to the accompanying drawings.

In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application. , not all examples. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

The terms "first", "second", etc. in the description, embodiments, claims and drawings of this application are only used for the purpose of distinguishing and describing, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating. Or suggestive order. Furthermore, the terms "including" and "having" and any variations thereof are intended to cover a non-exclusive inclusion, for example, the inclusion of a series of steps or units. Methods, systems, products or devices are not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such processes, methods, products or devices.

It should be understood that in this application, "at least one (item)" refers to one or more, and "plurality" refers to two or more. "And/or" is used to describe the relationship between associated objects, indicating that there can be three relationships. For example, "A and/or B" can mean: only A exists, only B exists, and A and B exist simultaneously. , where A and B can be singular or plural. The character "/" generally indicates that the related objects are in an "or" relationship. “At least one of the following” or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items). For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c" ”, where a, b, c can be single or multiple.

In order to solve the above technical problems, this application provides a temperature control device that can control the power consumption of test vectors within a certain range, reduce the power consumption difference between different test vectors, thereby reducing the power consumption of the chip under test. When switching between different test vectors, the heat generated fluctuates, thereby reducing the difficulty of controlling the junction temperature of the chip under test.

It should be noted that the chip under test here refers to the packaged chip, that is, the chip under test includes a bare chip (that is, the chip itself) and a package body. The junction temperature of the chip under test refers to the temperature of the bare die in the chip under test.

The principle of the temperature control device provided by this application is as follows:

As the power consumption of the test vector increases, the chip under test generates more heat when executing the test vector. And because the power consumption of the test vector is positively correlated with the power of the test vector. Therefore, the more powerful the test vector, the more heat is generated when the chip under test executes the test vector.

The power of the test vector can be calculated by the following formula:

P _n is the power of test vector n, k _n is the constant of test vector n, V _n is the IO port voltage when the chip under test executes test vector n, f _n (k) is the operating frequency of test vector n, [fmin, fmax] is the operable frequency range of the test vector n, f _n (k)∈[fmin, fmax], fmin and fmax are determined by the chip under test.

It should be noted that different test vectors correspond to different k _n , different test vectors correspond to different V _n , and the operable frequency ranges [fmin, fmax] of different test vectors are the same.

Since the operating frequency of the test vector has an operable frequency range, the power of the test vector can be adjusted by adjusting the operating frequency of the test vector.

Based on this, the power of the test vector can be adjusted by adjusting the running frequency of the test vector, and then the power consumption of the test vector can be adjusted to control the power consumption of the test vector within a certain range and reduce the power consumption difference between different test vectors. This further reduces the heat fluctuations generated when the chip under test switches between different test vectors, thereby reducing the difficulty of controlling the junction temperature of the chip under test.

Next, a temperature control device constructed based on the above principles will be described.

FIG. 1 is a schematic structural diagram of a temperature control device provided by an embodiment of the present application. As shown in FIG. 1 , the temperature control device includes a processor 110 and a temperature compensation device 120 . in:

The processor 110 includes, but is not limited to, a central processing unit (CPU), a microcontroller (MCU), a digital signal processor (DSP), a neural processing unit (NPU), a microprocessor, etc. The processor 110 is configured to input the target operating frequency of the vector to be measured and the vector to be measured into the chip under test 130, and during the process of the chip under test 130 executing the vector to be measured at the target operating frequency, by controlling the temperature compensation device 120, The junction temperature of the chip under test 130 is controlled. The target operating frequency of the vector to be measured is determined based on the reference power. The vector to be tested is any test vector among multiple test vectors of the chip under test 130 . The reference power is used to indicate the fluctuation base of the power of the vector to be measured. The temperature compensation device 120 is used to compensate the junction temperature of the chip under test 130 . The specific implementation manner of the temperature compensation device 120 is determined according to the application scenario of the temperature control device. For example, the temperature compensation device 120 includes a heating device and a cooling device. For another example, the temperature compensation device 120 includes a cooling device. Heating devices include but are not limited to heating rods, etc., and cooling devices include but are not limited to fans, water cooling devices, etc.

It can be seen from the above that the target operating frequency of the vector to be measured is determined based on the reference power. The reference power is used to indicate the fluctuation baseline of the power of the vector to be measured. That is, the target operating frequency of the vector to be measured is determined based on the reference power to The power of the vector is limited to a range based on the reference power, thereby limiting the power consumption of the vector to be measured to a certain range, reducing the power consumption difference between different vectors to be measured, and thereby reducing the power consumption of the chip under test 130 in different to-be-tested vectors. When switching between measurement vectors, the heat generated fluctuates, thereby reducing the difficulty of controlling the junction temperature of the chip under test 130 .

Since the temperature control device controls the junction temperature of the chip under test 130 during the process of testing the chip under test 130, the relevant components for testing the chip under test 130 may be included in the temperature control device, or may not be included in the temperature control device. In the control device, this application does not impose special restrictions on this.

When controlling the junction temperature of the chip under test 130, the basic quantity used has the following two situations. in:

First, the basic data is the shell temperature of the chip under test 130 , that is, the shell temperature of the chip under test 130 is obtained, and the junction temperature of the chip under test 130 is controlled by the shell temperature of the chip under test 130 .

In the second method, the basic data is the junction temperature of the chip under test 130 , that is, the junction temperature of the chip under test 130 is obtained, and the junction temperature of the chip under test 130 is controlled by the junction temperature of the chip under test 130 .

When controlling the junction temperature of the chip under test 130, the temperature control targets include the following two situations. in:

The first method is to control the junction temperature of the chip under test 130 below the target temperature. The target temperature is determined according to the test item to which the vector to be measured belongs. The test items include but are not limited to: ATE test, functional test and other test items that need to control the junction temperature of the chip under test 130 under a certain temperature. For example, the target temperature is the irreversible failure temperature of the chip under test 130 .

The second method is to maintain the junction temperature of the chip under test 130 at the target temperature. The target temperature is determined according to the test item to which the vector to be measured belongs. Test items include but are not limited to: Burn-in test, aging test and other test items that require maintaining the junction temperature of the chip under test 130 at a certain temperature. For example, the target temperature is a temperature that can expose weak points of the chip under test 130 .

Due to the different basic data used, the relevant components for testing the chip under test 130 are different. In addition, due to different temperature control objectives, the reference power is determined in different ways, the specific implementation form of the temperature compensation device 120, and the target operating frequency of the vector to be measured are determined in different ways. Therefore, in the following, the structure and operation process of the temperature control device including the relevant components for testing the chip under test 130 will be described in detail under four application scenarios consisting of two basic data and two temperature control targets.

Figure 2 is a schematic structural diagram of the temperature control device in the first application scenario provided by the embodiment of the present application. In the first application scenario, the basic data used is the junction temperature of the chip under test 130, and the goal of temperature control is to control the junction temperature of the chip under test 130 below the target temperature.

Since the basic data used is the junction temperature of the chip under test 130, at least one temperature sensor (not shown in FIG. 2) needs to be provided in the chip under test 130 to obtain the junction temperature of the chip under test 130 through at least one temperature sensor. temperature. Implementations of temperature sensors include but are not limited to PN junctions. Since the goal of temperature control is to control the junction temperature of the chip under test 130 below the target temperature, the temperature compensation device 120 is a cooling device 121 .

As shown in FIG. 2 , the temperature control device includes: a processor 110 , a cooling device 121 , a test substrate 140 , a probe base 150 , a pressure block 160 and a heat sink 170 . in:

The probe holder 150 is disposed on the test substrate 140 . The probe holder 150 is used to place the chip under test 130 and electrically connect the pins of the chip under test 130 to the test substrate 140 through the probes in the probe holder 150 .

The pressure block 160 is located on the chip under test 130, and is used to apply pressure to the chip under test 130 to ensure that the pins of the chip under test 130 are in full contact with the probe.

The heat sink 170 is arranged on the pressure block 160. The heat sink 170 is used to bring out the temperature of the chip 130 to be tested, so as to exchange the brought out temperature with the cooling device 121 to play a cooling role.

The processor 110 is provided on the test substrate 140. The test substrate 140 is provided with a printed circuit (not shown in Figure 4), and the processor 110 is connected to the probes in the probe base 150 through the printed circuit on the test substrate 140. In this way, the processor 110 can be connected through the printed circuit and The probe communicates with the chip under test 130 and provides a power signal to the chip under test 130 . In addition, the cooling device 121 is connected to the printed circuit on the test substrate 140, so that the processor 110 can provide a power signal to the cooling device 121 through the printed circuit and control the cooling device 121.

It should be noted that in other embodiments, the processor 110 can also be disposed outside the test substrate 140 , and the processor 110 and the cooling device 121 can also be connected to the test substrate through electrical connectors disposed on the test substrate 140 . The electrical connectors are connected to the printed circuits on the test substrate 140 .

The processor 110 is used to provide a power signal to the chip under test 130, input the target operating frequency of the vector under test and the vector under test into the chip under test 130, and execute the chip under test 130 at the target operating frequency of the vector under test. During the process of measuring the vector, the junction temperature of the chip under test 130 is obtained from at least one temperature sensor in the chip under test 130. According to the obtained junction temperature of the chip under test 130, and by controlling the cooling device 121, the chip under test 130 is The junction temperature of 130 is controlled below the target temperature. The processor 110 is also used to provide a power signal to the cooling device 121 and control the cooling device 121 .

The determination methods of reference power include but are not limited to the following two methods:

First, the reference power may be the power of a reference vector, and the reference vector is one test vector among multiple test vectors of the chip under test 130 . Specifically, the reference vector may be any test vector among multiple test vectors of the chip under test 130 . The reference vector may also be a specified test vector among multiple test vectors of the chip under test 130, for example, the test vector with the highest power when the operating frequency is the smallest. The power of the reference vector can be obtained according to the power calculation formula of the test vector mentioned above. It should be noted that the operating frequency used when calculating the power of the reference vector may be an operating frequency within the operable frequency range of the reference vector.

Second, the reference power may be a power in the power range of multiple test vectors of the chip under test 130 . Specifically, the reference power may be any power in the power range of multiple test vectors of the chip under test 130 . The reference power may also be a specified power in the power ranges of multiple test vectors of the chip under test 130 , for example, the middle value of the power range. The process of determining the power range of multiple test vectors of the chip under test 130 is: calculating the power range of each test vector in the multiple test vectors, and performing a union of the power ranges of the test vectors to obtain the power of the multiple test vectors. scope. It should be noted that the above description of the reference power is only exemplary and is not intended to limit the present application.

The target operating frequency of the vector under test is determined by comparing the default power of the vector under test with the reference power. Among them, the default power of the vector to be measured is the power of the vector to be measured at the default operating frequency of the vector to be measured. The default operating frequency of the vector under test is an operating frequency within the operable frequency range of the vector under test. Specifically, the default operating frequency of the vector to be measured can be any operating frequency in the operable frequency range of the vector to be measured. The default operating frequency of the vector to be measured can also be an operating frequency specified in the operable frequency range of the vector to be measured, for example, the middle value or the minimum value of the operable frequency range. If the default power of the vector to be measured is less than or equal to the reference power, the target operating frequency of the vector to be measured is the default operating frequency of the vector to be measured. If the default power of the vector to be measured is greater than the reference power, the target operating frequency of the vector to be measured is the smallest operating frequency in the operable frequency range of the vector to be measured.

Below, an example is given to illustrate the testing and temperature control process. The specific process is as follows:

The processor 110 inputs the operating frequency of the vector 1 under test and the vector 1 under test into the chip 130 under test. The operating frequency of vector 1 to be measured is an operating frequency within the operable frequency range of vector 1 to be measured.

When the chip under test 130 executes the vector 1 under test at the operating frequency of the vector 1 under test, the processor 110 obtains the junction temperature of the chip under test 130 from at least one temperature sensor in the chip under test 130 .

The processor 110 compares the junction temperature of the chip under test 130 with the target temperature. If the junction temperature of the chip under test 130 is greater than the target temperature, the processor 110 increases the power of the cooling device 121 to enhance the cooling of the chip under test 130, for example, Increase the speed of the fan to accelerate heat dissipation until the junction temperature of the chip under test 130 is maintained below the target temperature. Use the vector 1 to be measured as the reference vector, calculate the power of the reference vector according to the above formula, and use the power of the reference vector as the reference power. Ways of increasing the power of the cooling device 121 include, but are not limited to, increasing the operating voltage and/or current of the cooling device 121 .

The processor 110 determines the target operating frequency of vector 2 under test. Specifically, if the default power of vector 2 to be measured is less than or equal to the reference power, the default operating frequency of vector 2 to be measured is determined as the target operating frequency of vector 2 to be measured. If the default power of vector 2 to be measured is greater than the reference power, the smallest operating frequency in the operable frequency range of vector 2 to be measured is determined as the target operating frequency of vector 2 to be measured.

The processor 110 inputs the target operating frequency of the vector 2 under test and the vector 2 under test into the chip 130 under test.

When the chip under test 130 executes the vector under test 2 at the target operating frequency of the vector under test 2, the processor 110 obtains the junction temperature of the chip under test 130 from at least one temperature sensor in the chip under test 130, and According to the junction temperature of the chip under test 130, combined with the PID algorithm, linear temperature control algorithm, etc., and by controlling the cooling device 121, the junction temperature of the chip under test 130 is dynamically adjusted, so that the junction temperature of the chip under test 130 is lower than the target temperature.

Based on the principle of executing vector 2 to be measured, the remaining vectors to be measured are executed.

It can be seen from the above that the calculation of the reference power and the target operating frequency of the vector to be measured is calculated in real time during the test and temperature control process. In other embodiments of the present application, the reference power and the target operating frequency of the vector to be measured can also be calculated in advance in an offline manner. That is, the reference power and the target operating frequency of each test vector in multiple test vectors are calculated in advance. In this way, during the test process, the target operating frequency of the vector to be measured can be obtained directly from the target operating frequencies of multiple test vectors. No online calculations required.

In order to increase the stability and accuracy of temperature control and ensure the stability of the temperature of the chip under test 130, the processor 110 can also calculate the vector under test before inputting the target operating frequency of the vector under test and the vector under test into the chip under test 130. For the power at the target operating frequency, the power of the vector to be measured at the target operating frequency is compared with the reference power. If the power of the vector to be measured at the target operating frequency is greater than the reference power, the power of the cooling device 121 is first increased, In order to increase the cooling intensity, the target operating frequency of the vector to be measured and the vector to be measured are input into the chip 130 to be tested. If the power of the vector to be measured at the target operating frequency is less than or equal to the reference power, the target operating frequency of the vector to be measured and the vector to be measured are input to the chip to be measured 130 without adjusting the power of the cooling device 121 .

Obviously, before inputting the vector to be measured into the chip under test 130, if the power of the vector to be measured at the target operating frequency is greater than the reference power, the power of the cooling device 121 is increased to increase the cooling intensity of the chip under test 130. That is, the power of the cooling device 121 is predicted in advance, and the power of the cooling device 121 is adjusted according to the prediction result to perform temperature compensation in advance, which improves the stability and accuracy of temperature control and ensures the stability of the temperature of the chip under test 130 sex.

It should be noted that the test substrate 140 , the probe holder 150 , the pressure block 160 and the heat sink 170 are relevant components for testing the chip under test 130 .

Figure 3 is a schematic structural diagram of the temperature control device in the second application scenario provided by the embodiment of the present application. In the second application scenario, the basic data used is the shell temperature of the chip under test 130, and the goal of temperature control is to control the junction temperature of the chip under test 130 below the target temperature.

The structural difference between the temperature control device in Figure 3 and the temperature control device in Figure 2 is that a thermal resistance module 180 and at least one temperature sensor 190 are added to the temperature control device shown in Figure 3 . Among them, the thermal resistance module 180 is located between the chip under test 130 and the pressure block 160. The thermal resistance module 180 balances the temperature between the chip under test 130 and the pressure block 160 to improve the measurement accuracy of the shell temperature of the chip under test 130. . The material of the thermal resistance module 180 may be, for example, indium, which is not limited in this application. Since in this scenario, the basic data used is the shell temperature of the chip under test 130, there is no need to set a temperature sensor in the chip under test 130. At least one temperature sensor 190 needs to be set on the package of the chip under test 130 to The shell temperature of the chip 130 under test is obtained through the at least one temperature sensor 190 . At least one temperature sensor 190 is connected to a printed circuit on the test substrate 140. The processor 110 is connected to the at least one temperature sensor 190 through the printed circuit to provide a power signal to the at least one temperature sensor 190 and obtain the desired temperature signal from the at least one temperature sensor 190. Measure the shell temperature of chip 130.

The difference in execution flow between the temperature control device in Figure 3 and the temperature control device in Figure 2 is that during the process of controlling the junction temperature of the chip under test 130, the processor 110 is in contact with the package of the chip under test 130. The shell temperature of the chip under test 130 is obtained from at least one temperature sensor 190, and the junction temperature of the chip under test 130 is estimated based on the shell temperature of the chip under test 130. Then, based on the estimated junction temperature of the chip under test 130, the temperature is reduced by controlling Device 121 controls the junction temperature of the chip under test 130 below the target temperature.

It should be noted that the test substrate 140 , the probe holder 150 , the pressure block 160 , the thermal resistance module 180 , at least one temperature sensor 190 and the heat sink 170 are relevant components for testing the chip under test 130 .

Figure 4 is a schematic structural diagram of the temperature control device in the third application scenario provided by the embodiment of the present application. In the third application scenario, the basic data used is the junction temperature of the chip under test 130, and the goal of temperature control is to maintain the junction temperature of the chip under test 130 at the target temperature. It should be noted that maintaining the junction temperature of the chip under test 130 at the target temperature means that the absolute value of the difference between the target temperature and the junction temperature of the chip under test 130 is less than a preset error value. The preset error value can be set according to design requirements. Certainly.

Since the goal of temperature control is to maintain the junction temperature of the chip under test 130 at the target temperature, the temperature compensation device 120 includes a cooling device 121 and a heating device 122 .

The structural difference between the temperature control device in Figure 4 and the temperature control device in Figure 2 is that a heating device 122 is added to the temperature control device shown in Figure 4 .

The positional relationship of the cooling device 121, the test substrate 140, the probe holder 150, the pressure block 160 and the heat sink 170 and the functions of each component have been explained in Figure 2 and will not be described again here. The heating device 122 is arranged in the pressing block 160 . It should be noted that in other embodiments, the heating device 122 can also be disposed between the pressure block 160 and the chip to be tested 130 , which is not specifically limited in this application. The heating device 122 is connected to the printed circuit on the test substrate 140 . The processor 110 provides a power signal to the heating device 122 through the printed circuit and controls the heating device 122, for example, increasing the power of the heating device 122 to increase the heating intensity of the chip under test 130, or, for example, reducing the power of the heating device 122. power to weaken the heating intensity of the chip 130 under test. Ways of increasing the power of the heating device 122 include, but are not limited to, increasing the operating voltage and/or current of the heating device 122 . Ways of reducing the power of the heating device 122 include, but are not limited to, reducing the operating voltage and/or current of the heating device 122 .

The processor 110 is used to provide a power signal to the chip under test 130, input the target operating frequency of the vector under test and the vector under test into the chip under test 130, and execute the chip under test 130 at the target operating frequency of the vector under test. During the process of measuring the vector, the junction temperature of the chip under test 130 is obtained from at least one temperature sensor in the chip under test 130 , and based on the obtained junction temperature of the chip under test 130 , the cooling device 121 and/or the heating device are controlled. 122. Control the junction temperature of the chip under test 130 to maintain the target temperature. The processor 110 is also used to provide power signals to the cooling device 121 and the heating device 122, and to control the cooling device 121 and the heating device 122.

The determination methods of reference power include but are not limited to the following three methods:

The first one is that the reference power is the power of the reference vector. The reference vector and the power of the reference vector have been explained above and will not be described in detail here.

Secondly, the reference power may also be a power in the power range of multiple test vectors of the chip under test 130 . The second method has been explained above and will not be described again here.

Third, the reference power is the total power, where the total power is the sum of the power of the test vector that the chip under test 130 is running and the power of the heating device 122 when the junction temperature of the chip under test 130 is maintained at the target temperature.

The method for determining the target operating frequency of the vector to be measured is: the target operating frequency of the vector to be measured is the first operating frequency in the operable frequency range of the vector to be measured; where the power of the vector to be measured at the first operating frequency is closest to the reference power.

Obviously, by determining the operating frequency when the power of the vector to be measured is closest to the reference power as the target operating frequency of the vector to be measured, the power of the vector to be measured at the target operating frequency is closest to the reference power, that is, by adjusting the target operating frequency, Make the power of the vector to be measured close to the reference power to control the power of the vector to be measured within a certain range, thereby controlling the power consumption of the vector to be measured within a certain range, reducing the power consumption difference between different vectors to be measured, and reducing When the chip under test 130 switches between different vectors under test, the heat generated fluctuates, thereby reducing the difficulty of controlling the junction temperature of the chip under test 130 .

Below, an example is given to illustrate the testing and temperature control process. The specific process is as follows:

The processor 110 inputs the operating frequency of the vector 1 under test and the vector 1 under test into the chip 130 under test. The operating frequency of vector 1 to be measured is an operating frequency within the operable frequency range of vector 1 to be measured.

When the chip under test 130 executes the vector 1 under test at the operating frequency of the vector 1 under test, the processor 110 obtains the junction temperature of the chip under test 130 from at least one temperature sensor in the chip under test 130 .

The processor 110 compares the junction temperature of the chip under test 130 with the target temperature. If the junction temperature of the chip under test 130 is greater than the target temperature, the processor 110 increases the power of the cooling device 121 to enhance the cooling intensity of the chip under test 130 and/or Reduce the power of the heating device 122 to reduce the heating intensity of the chip under test 130, for example, increase the speed of the fan to accelerate heat dissipation, reduce the power of the heating rod, and reduce the heating efficiency until the junction temperature of the chip under test 130 is maintained at the target temperature. If the junction temperature of the chip under test 130 is lower than the target temperature, increase the power of the heating device 122 to increase the heating intensity of the chip under test 130 and/or reduce the power of the cooling device 121 to reduce the cooling intensity of the chip under test 130. For example, increase the power of the heating rod to accelerate heating, reduce the fan speed, and reduce heat dissipation efficiency until the junction temperature of the chip under test 130 is maintained at the target temperature.

When the junction temperature of the chip under test 130 is maintained at the target temperature, the vector to be measured 1 is used as the reference vector, and the power of the reference vector is calculated according to the above formula, and the power of the reference vector is used as the reference power, or the vector to be measured is determined 1 and the power of the heating device 122, add the power of the vector 1 to be measured and the power of the heating device 122 to obtain the total power, and use the total power as the reference power.

The processor 110 determines the target operating frequency of the vector 2 to be measured, where the target operating frequency of the vector 2 to be measured is the first operating frequency in the operable frequency range of the vector 2 to be measured; wherein the vector 2 to be measured is in the first operating frequency range. The power at the frequency is closest to the reference power.

The processor 110 inputs the target operating frequency of the vector 2 under test and the vector 2 under test into the chip 130 under test.

During the process of the chip under test 130 executing vector 2, the processor 110 obtains the junction temperature of the chip under test 130 from at least one temperature sensor in the chip under test 130, and combines the PID algorithm, linear temperature control algorithm, etc., and by controlling the cooling device 121 and/or the heating device 122, the junction temperature of the chip under test 130 is dynamically adjusted to maintain the junction temperature of the chip under test 130 at the target temperature.

Based on the principle of executing vector 2 to be measured, the remaining vectors to be measured are executed.

It can be seen from the above that the calculation of the reference power and the target operating frequency of the vector to be measured is calculated in real time during the test and temperature control process. In other embodiments of the present application, the reference power and the target operating frequency of the vector to be measured can also be calculated in advance in an offline manner. That is, the reference power and the target operating frequency of each test vector in multiple test vectors are calculated in advance. In this way, during the test process, the target operating frequency of the vector to be measured can be obtained directly from the target operating frequencies of multiple test vectors. No online calculations required.

In order to increase the stability and accuracy of temperature control and ensure the stability of the temperature of the chip under test 130, before inputting the vector to be measured into the chip under test 130, the processor 110 can also determine the power of the heating device 122, and then set the heating device 122 of power, and then input the target operating frequency of the vector to be measured and the vector to be measured into the chip 130 to be tested.

The way to determine the power of the heating device 122 is: if the difference between the total power and the power of the vector to be measured at the target operating frequency is greater than 0, then the power of the heating device 122 is the difference. If the total power and the power of the vector to be measured are at the target operating frequency If the difference in power at the operating frequency is not greater than 0, then the power of the heating device 122 is 0.

Obviously, before inputting the vector to be measured into the chip 130 under test, the power of the heating device 122 is determined based on the power and total power of the vector to be measured at the target operating frequency, and the power of the heating device 122 is set, that is, the power of the heating device 122 is predicted in advance. The power of the heating device 122 is set according to the prediction result to perform temperature compensation in advance, which improves the stability and accuracy of temperature control and ensures the stability of the temperature of the chip 130 under test.

Figure 5 is a schematic structural diagram of a temperature control device in the fourth application scenario provided by the embodiment of the present application. In the fourth application scenario, the basic data used is the shell temperature of the chip under test 130, and the goal of temperature control is to maintain the junction temperature of the chip under test 130 at the target temperature.

The structural difference between the temperature control device in Figure 5 and the temperature control device in Figure 4 is that a thermal resistance module 180 and at least one temperature sensor 190 are added to the temperature control device shown in Figure 5 . Among them, the thermal resistance module 180 is located between the chip under test 130 and the pressure block 160. The thermal resistance module 180 is used to balance the temperature between the chip under test 130 and the pressure block 160 to improve the measurement accuracy of the shell temperature of the chip under test 130. Spend. The material of the thermal resistance module 180 has been described above and will not be described again here. Since in this scenario, the basic data used is the shell temperature of the chip under test 130, there is no need to set a temperature sensor in the chip under test 130. At least one temperature sensor 190 needs to be set on the package of the chip under test 130 to The shell temperature of the chip 130 under test is obtained through the at least one temperature sensor 190 . At least one temperature sensor 190 is connected to a printed circuit on the test substrate 140. The processor 110 is connected to the at least one temperature sensor 190 through the printed circuit to provide a power signal to the at least one temperature sensor 190 and obtain the desired temperature signal from the at least one temperature sensor 190. Measure the shell temperature of chip 130.

The difference in the execution flow between the temperature control device in Figure 5 and the temperature control device in Figure 4 is that during the process of controlling the junction temperature of the chip under test 130, the processor 110 is in contact with the package of the chip under test 130. Obtain the shell temperature of the chip under test 130 from at least one temperature sensor, estimate the junction temperature of the chip under test 130 based on the shell temperature of the chip under test 130, and then, based on the estimated junction temperature of the chip under test 130, control the cooling device 121 and/or heating device 122 to maintain the junction temperature of the chip under test 130 at the target temperature.

It can be seen from the above that in a scenario where the basic data used is the junction temperature of the chip under test 130, the components used to test the chip under test 130 are relatively simple and low in cost.

Figure 6 is a schematic structural diagram of a processor provided by an embodiment of the present application. As shown in FIG. 6 , the processor 110 includes: a test vector control circuit 111 , a temperature acquisition circuit 112 , a test vector sending circuit 113 and a temperature compensation control circuit 114 . Among them: the test vector control circuit 111 is used to determine the target operating frequency of the vector to be measured, and send the target operating frequency of the vector to be measured and the vector to be measured to the test vector sending circuit 113. The test vector sending circuit 113 is used to input the target operating frequency of the vector to be tested and the vector to be tested into the chip under test 130 . The temperature acquisition circuit 112 is used to obtain the junction temperature of the chip under test 130 or the shell temperature of the chip under test 130 , and transmit the junction temperature of the chip under test 130 or the shell temperature of the chip under test 130 to the test vector control circuit 111 . The test vector control circuit 111 is also used to generate a temperature control signal based on the junction temperature of the chip under test 130 or the shell temperature of the chip under test 130 combined with the target temperature, and transmit the temperature control signal to the temperature compensation control circuit 114 . The temperature compensation control circuit 114 is used to control the temperature compensation device 120 in response to the temperature control signal. For example, when the temperature compensation device 120 is the cooling device 121, increase or decrease the power of the cooling device 121 to strengthen or weaken the cooling device 121. For another example, when the temperature compensation device 120 is the heating device 122, the power of the heating device 122 is increased or decreased to enhance or weaken the heating intensity of the heating device 122.

It should be noted that the above description of the processor 110 is only exemplary and is not intended to limit this embodiment.

This application also provides a temperature control method, as shown in Figure 7. The temperature control method includes: 701. Input the target operating frequency of the vector to be measured and the vector to be measured into the chip to be tested. 702. In the process of the chip under test executing the vector under test at the target operating frequency, control the junction temperature of the chip under test by controlling the temperature compensation device; wherein the target operating frequency It is determined according to the reference power that the vector to be measured is any one of multiple test vectors of the chip under test, and the reference power is used to indicate the fluctuation standard of the power of the vector to be measured.

In a possible implementation, the controlling the junction temperature of the chip under test includes: controlling the junction temperature of the chip under test below a target temperature; wherein the target temperature is determined according to the The test item to which the measurement vector belongs is determined.

In a possible implementation, if the default power of the vector to be measured is less than or equal to the reference power, the target operating frequency is the default operating frequency of the vector to be measured; if the default power of the vector to be measured is If the default power is greater than the reference power, then the target operating frequency is the smallest operating frequency in the operable frequency range of the vector to be measured; wherein, the default power of the vector to be measured is the vector to be measured in the The power at the default operating frequency. The default operating frequency of the vector to be measured is an operating frequency in the operable frequency range of the vector to be measured.

In a possible implementation, the temperature compensation device includes a cooling device; inputting the target operating frequency of the vector to be measured and the vector to be measured into the chip to be measured includes: if the vector to be measured is in the target If the power at the operating frequency is greater than the reference power, increase the power of the cooling device, and input the target operating frequency of the vector to be measured and the vector to be measured into the chip to be tested; if the vector to be measured is If the power of the measured vector at the target operating frequency is less than or equal to the reference power, then the target operating frequency of the vector to be measured and the vector to be measured are input to the chip to be measured.

In a possible implementation, the reference power is the power of a reference vector, and the reference vector is one of multiple test vectors of the chip under test.

In a possible implementation, the controlling the junction temperature of the chip under test includes: maintaining the junction temperature of the chip under test at a target temperature; wherein the target temperature is determined according to the vector under test The test project to which it belongs is determined.

In a possible implementation, the target operating frequency is the first operating frequency in the operable frequency range of the vector to be measured; wherein the power of the vector to be measured at the first operating frequency is the highest. close to the reference power.

In a possible implementation, the temperature compensation device includes a heating device; inputting the target operating frequency of the vector to be measured and the vector to be measured into the chip to be measured includes: setting the power of the heating device, and, The target operating frequency of the vector to be measured and the vector to be measured are input into the chip to be measured; wherein the power of the heating device is determined based on the power and total power of the vector to be measured at the target operating frequency. ; The total power is the sum of the power of the test vector that the chip under test is running and the power of the heating device when the junction temperature of the chip under test is maintained at the target temperature.

In a possible implementation, the reference power is the power of a reference vector, and the reference vector is one of multiple test vectors of the chip under test; or the reference power is the total power, where The total power is the sum of the power of the test vector that the chip under test is running and the power of the heating device when the junction temperature of the chip under test is maintained at the target temperature.

In a possible implementation, controlling the junction temperature of the chip under test by controlling the temperature compensation device includes: obtaining the temperature sensor from at least one temperature sensor in contact with the package of the chip under test. The shell temperature of the chip under test; controlling the junction temperature of the chip under test according to the shell temperature of the chip under test and by controlling the temperature compensation device; or from at least one temperature sensor in the chip under test Obtain the junction temperature of the chip under test; control the junction temperature of the chip under test according to the junction temperature of the chip under test and by controlling the temperature compensation device.

The implementation principles and technical effects of the above temperature control method of the present application have been explained above and will not be described again here.

This application also provides a computer-readable storage medium. A computer program is stored in the computer storage medium. When the computer program is executed on a computer or processor, it causes the computer or processor to execute any of the above method embodiments. technical solutions.

This application also provides a computer program product, which when the computer program is executed by a computer, causes the computer or processor to execute the technical solutions of any of the above method embodiments.

The present application also provides an electronic device, including the temperature control device described above.

This application also provides a chip, which includes a processor and a memory. The processor is configured to execute the technical solutions of any of the above method embodiments.

Further, the chip may also include a memory and a communication interface. The communication interface may be an input/output interface, a pin or an input/output circuit, etc.

During the implementation process, each step of the above method embodiment can be completed through the integrated logic circuit of the hardware in the network card or instructions in the form of software. The processor may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other Programmed logic devices, discrete gate or transistor logic devices, discrete hardware components. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc. The steps of the methods disclosed in the embodiments of this application can be directly implemented by a hardware encoding processor, or executed by a combination of hardware and software modules in the encoding processor. The software module can be located in random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers and other mature storage media in this field. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

The memory mentioned in the above embodiments may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory can be read-only memory (ROM), programmable ROM (PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically removable memory. Erase programmable read-only memory (electrically EPROM, EEPROM) or flash memory. Volatile memory may be random access memory (RAM), which is used as an external cache. By way of illustration, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous link dynamic random access memory (synchlink DRAM, SLDRAM) ) and direct memory bus random access memory (direct rambus RAM, DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each specific application, but such implementations should not be considered beyond the scope of this application.

Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be described again here.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit.

If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk and other media that can store program code. .

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application. should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims (24)

A temperature control method, characterized by including: Input the target operating frequency of the vector to be measured and the vector to be measured into the chip to be tested; In the process of the chip under test executing the vector under test at the target operating frequency, the junction temperature of the chip under test is controlled by controlling a temperature compensation device; Wherein, the target operating frequency is determined based on a reference power, the vector to be measured is any one of multiple test vectors of the chip under test, and the reference power is used to indicate a fluctuation benchmark of the power of the vector to be measured. . The method of claim 1, wherein controlling the junction temperature of the chip under test includes: Control the junction temperature of the chip under test below the target temperature; Wherein, the target temperature is determined according to the test item to which the vector to be measured belongs. The method according to claim 2, characterized in that: If the default power of the vector to be measured is less than or equal to the reference power, then the target operating frequency is the default operating frequency of the vector to be measured; If the default power of the vector to be measured is greater than the reference power, the target operating frequency is the smallest operating frequency in the operable frequency range of the vector to be measured; Wherein, the default power of the vector to be measured is the power of the vector to be measured at the default operating frequency, and the default operating frequency of the vector to be measured is one of the operable frequency ranges of the vector to be measured. frequency. The method according to claim 2 or 3, characterized in that the temperature compensation device includes a cooling device; The input of the target operating frequency of the vector to be measured and the vector to be measured into the chip to be tested includes: If the power of the vector to be measured at the target operating frequency is greater than the reference power, increase the power of the cooling device, and input the target operating frequency of the vector to be measured and the vector to be measured. The chip to be tested; If the power of the vector to be measured at the target operating frequency is less than or equal to the reference power, the target operating frequency of the vector to be measured and the vector to be measured are input into the chip to be measured. The method according to any one of claims 2 to 4, characterized in that the reference power is the power of a reference vector, and the reference vector is one of a plurality of test vectors of the chip under test. The method of claim 1, wherein controlling the junction temperature of the chip under test includes: Maintain the junction temperature of the chip under test at the target temperature; Wherein, the target temperature is determined according to the test item to which the vector to be measured belongs. The method according to claim 6, wherein the target operating frequency is the first operating frequency in the operable frequency range of the vector to be measured; Wherein, the power of the vector to be measured at the first operating frequency is closest to the reference power. The method according to claim 6 or 7, characterized in that the temperature compensation device includes a heating device; The input of the target operating frequency of the vector to be measured and the vector to be measured into the chip to be tested includes: Set the power of the heating device, and input the target operating frequency of the vector to be measured and the vector to be measured into the chip to be tested; Wherein, the power of the heating device is determined based on the power of the vector to be measured at the target operating frequency and the total power; The total power is the sum of the power of the test vector that the chip under test is running and the power of the heating device when the junction temperature of the chip under test is maintained at the target temperature. The method according to any one of claims 6 to 8, characterized in that the reference power is the power of a reference vector, and the reference vector is one of a plurality of test vectors of the chip under test; or The reference power is the total power, where the total power is the power of the test vector that the chip under test is running and the power of the heating device when the junction temperature of the chip under test is maintained at the target temperature. sum of power. The method according to any one of claims 1 to 9, wherein controlling the junction temperature of the chip under test by controlling a temperature compensation device includes: Obtain the case temperature of the chip under test from at least one temperature sensor in contact with the package of the chip under test; Control the junction temperature of the chip under test according to the shell temperature of the chip under test and by controlling the temperature compensation device; or Obtain the junction temperature of the chip under test from at least one temperature sensor in the chip under test; The junction temperature of the chip under test is controlled according to the junction temperature of the chip under test and by controlling the temperature compensation device. A temperature control device, characterized by including: a processor and a temperature compensation device; wherein, The processor is configured to input the target operating frequency of the vector to be measured and the vector to be measured into the chip to be tested, and in the process of the chip under test executing the vector to be measured at the target operating frequency. , by controlling the temperature compensation device, the junction temperature of the chip under test is controlled; The temperature compensation device is used to compensate the junction temperature of the chip under test; The target operating frequency is determined based on a reference power. The vector to be measured is any one of multiple test vectors of the chip to be tested. The reference power is used to indicate a fluctuation benchmark of the power of the vector to be measured. The device according to claim 11, wherein the processor is specifically configured to control the junction temperature of the chip under test below a target temperature; Wherein, the target temperature is determined according to the test item to which the vector to be measured belongs. The device according to claim 12, characterized in that: If the default power of the vector to be measured is less than or equal to the reference power, then the target operating frequency is the default operating frequency of the vector to be measured; If the default power of the vector to be measured is greater than the reference power, the target operating frequency is the smallest operating frequency in the operable frequency range of the vector to be measured; Wherein, the default power of the vector to be measured is the power of the vector to be measured at the default operating frequency, and the default operating frequency of the vector to be measured is one of the operable frequency ranges of the vector to be measured. frequency. The device according to claim 12 or 13, characterized in that the temperature compensation device includes a cooling device; The processor is specifically configured to increase the power of the cooling device if the power of the vector to be measured at the target operating frequency is greater than the reference power, and to operate the target of the vector to be measured. The frequency and the vector to be measured are input into the chip to be measured; if the power of the vector to be measured at the target operating frequency is less than or equal to the reference power, the target operating frequency of the vector to be measured and the vector to be measured are The vector to be tested is input into the chip to be tested. The device according to any one of claims 12 to 14, wherein the reference power is the power of a reference vector, and the reference vector is one of a plurality of test vectors of the chip under test. The device according to claim 11, wherein the processor is specifically configured to maintain the junction temperature of the chip under test at a target temperature; Wherein, the target temperature is determined according to the test item to which the vector to be measured belongs. The device according to claim 16, wherein the target operating frequency is the first operating frequency in the operable frequency range of the vector to be measured; Wherein, the power of the vector to be measured at the first operating frequency is closest to the reference power. The device according to claim 16 or 17, characterized in that the temperature compensation device includes a heating device; The processor is specifically configured to set the power of the heating device, and input the target operating frequency of the vector to be measured and the vector to be measured into the chip to be tested; Wherein, the power of the heating device is determined based on the power of the vector to be measured at the target operating frequency and the total power; The total power is the sum of the power of the test vector that the chip under test is running and the power of the heating device when the junction temperature of the chip under test is maintained at the target temperature. The device according to any one of claims 16 to 18, wherein the reference power is the power of a reference vector, and the reference vector is one of a plurality of test vectors of the chip under test; or The reference power is the total power, where the total power is the power of the test vector that the chip under test is running and the power of the heating device when the junction temperature of the chip under test is maintained at the target temperature. sum of power. The device according to any one of claims 11 to 19, characterized in that at least one temperature sensor is provided in the chip to be tested; The device also includes: a test substrate, a probe holder, a pressure block and a heat sink, wherein: The probe holder is arranged on the test substrate for placing the chip under test, and electrically conducts electrical connection between the pins of the chip under test and the test substrate through the probes in the probe holder. connect; The pressure block is located on the chip to be tested and is used to apply pressure to the chip to be tested; The heat sink is provided on the pressure block and is used to bring out the temperature of the chip to be tested; The processor is specifically configured to input the target operating frequency of the vector to be measured and the vector to be measured into the chip to be tested through the test substrate, and, when the chip to be tested is running at the target During the process of executing the vector to be measured at a frequency, the junction temperature of the chip to be measured is adjusted according to the junction temperature of the chip to be measured obtained from the at least one temperature sensor and by controlling the temperature compensation device. Take control. The device according to any one of claims 11 to 19, characterized in that the device further includes: a test substrate, a probe holder, a pressure block, a thermal resistance module, at least one temperature sensor and a heat sink, wherein: The probe holder is arranged on the test substrate for placing the chip under test, and electrically conducts electrical connection between the pins of the chip under test and the test substrate through the probes in the probe holder. connect; The thermal resistance module is located on the chip to be tested and is used to balance the temperature between the chip to be tested and the pressure block; The pressure block is located on the thermal resistance module and is used to apply pressure to the chip under test; The at least one temperature sensor is in contact with the package of the chip under test and used to measure the shell temperature of the chip under test; The heat sink is provided on the pressure block and is used to bring out the temperature of the chip to be tested; The processor is specifically configured to input the target operating frequency of the vector to be measured and the vector to be measured into the chip to be tested through the test substrate, and, when the chip to be tested is running at the target During the process of executing the vector under test at a frequency, the junction temperature of the chip under test is adjusted according to the shell temperature of the chip under test obtained from the at least one temperature sensor and by controlling the temperature compensation device. Take control. A computer-readable storage medium includes a computer program. When the computer program is executed on a computer or processor, the computer or processor causes the computer or processor to execute the method described in any one of claims 1 to 10. A computer program, when the computer program is executed by a computer or processor, is used to perform the method described in any one of claims 1 to 10. An electronic device including the temperature control device according to any one of claims 11 to 21.