CN117083529A

CN117083529A - Temperature control device and method

Info

Publication number: CN117083529A
Application number: CN202180096226.4A
Authority: CN
Inventors: 王海峰; 黄俊林; 康文红; 钟进国
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-07-01
Filing date: 2021-07-01
Publication date: 2023-11-17
Also published as: WO2023272700A1

Abstract

A temperature control device, comprising: a processor (110) and a temperature compensation device (120); the processor (110) is configured to input a target operating frequency of a vector to be tested and the vector to be tested into the chip to be tested (130), and control a junction temperature of the chip to be tested (130) by controlling the temperature compensation device (120) in a process that the chip to be tested (130) executes the vector to be tested at the target operating frequency. And the temperature compensation device (120) is used for compensating the junction temperature of the chip (130) to be tested. The target operating frequency is determined based on a reference power, which is used to indicate a fluctuating basis for the power of the vector under test, the vector under test being any one of a plurality of test vectors for the chip under test (130). The difficulty in controlling the junction temperature of the chip (130) to be tested is reduced.

Description

Temperature control device and method

Technical Field

The application relates to the technical field of temperature control, in particular to a temperature control device and a temperature control method.

Background

Before leaving the factory, the chips need to be tested according to requirements, such as Burn-in test, ATE (Automatic Test Equipment ) test and the like, so as to ensure that the leaving the factory chips have no quality problems.

In the chip test process, the junction temperature of the chip needs to be controlled. For example, the junction temperature of the chip is controlled not to exceed the irreversible failure temperature of the chip, so as to avoid irreversible damage to the chip due to the junction temperature of the chip exceeding the irreversible failure temperature. For another example, the junction temperature of the chip is controlled to a temperature at which the weak point of the chip can be exposed, and the temperature at which the weak point of the chip can be exposed does not exceed the irreversible failure temperature of the chip, so that the defective chip can be effectively screened out without causing irreversible damage to the chip.

With the development of technology, the power consumption of the chip is increasing. For large power consumption chips, there is a large difference in power consumption between different test vectors. Because the chip generates heat when executing the test vector, the generated heat has a positive correlation with the power consumption of the test vector. Therefore, when the chip is switched between the test vectors with larger power consumption difference, larger heat fluctuation can be generated, and the control difficulty of the junction temperature of the chip is increased.

Disclosure of Invention

The application provides a temperature control method and a temperature control device, which are used for reducing the control difficulty of the junction temperature of a chip.

In a first aspect, the present application provides a temperature control method, comprising: inputting the target operating frequency of the vector to be tested and the vector to be tested into a chip to be tested; in the process that the chip to be tested executes the vector to be tested under the target operating frequency, controlling the junction temperature of the chip to be tested by controlling a temperature compensation device; the target operating frequency is determined according to reference power, the vector to be tested is any one of a plurality of test vectors of the chip to be tested, and the reference power is used for indicating a fluctuation standard of power of the vector to be tested.

The target operating frequency of the vector to be measured is determined according to the reference power, wherein the reference power is used for indicating the fluctuation standard of the power of the vector to be measured, namely, the reference power is used as a standard to determine the target operating frequency of the vector to be measured, so that the power of the vector to be measured is limited in a range taking the reference power as a standard, the power consumption of the vector to be measured is limited in a certain range, the power consumption difference among different vectors to be measured is reduced, and further, the heat fluctuation generated when the chip to be measured is switched among different vectors to be measured is reduced, and the difficulty in controlling the junction temperature of the chip to be measured is reduced.

In one possible implementation manner, the controlling the junction temperature of the chip to be tested includes: controlling the junction temperature of the chip to be tested below a target temperature; the target temperature is determined according to a test item to which the vector to be tested belongs.

In one possible implementation manner, if the default power of the vector to be tested is less than or equal to the reference power, the target operating frequency is the default operating frequency of the vector to be tested; if the default power of the vector to be tested is larger than the reference power, the target operating frequency is the minimum operating frequency in the operable frequency range of the vector to be tested; the default power of the to-be-measured vector is the power of the to-be-measured vector under the default operating frequency, and the default operating frequency of the to-be-measured vector is one operating frequency in the operable frequency range of the to-be-measured vector.

In one possible implementation, the temperature compensation device includes a cooling device; the inputting the target running frequency of the vector to be tested and the vector to be tested into the chip to be tested comprises: if the power of the vector to be tested under the target operating frequency is larger than the reference power, increasing the power of the cooling device, and inputting the target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested; and if the power of the vector to be tested under the target operating frequency is smaller than or equal to the reference power, inputting the target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested.

In one possible implementation, the reference power is a power of a reference vector, and the reference vector is one of a plurality of test vectors of the chip to be tested.

In one possible implementation manner, the controlling the junction temperature of the chip to be tested includes: maintaining the junction temperature of the chip to be tested at a target temperature; the target temperature is determined according to a test item to which the vector to be tested belongs.

In one possible implementation, the target operating frequency is a first operating frequency in an operable frequency range of the vector to be measured; wherein the power of the vector to be measured at the first operating frequency is closest to the reference power.

In one possible implementation, the temperature compensation device comprises a heating device; the inputting the target running frequency of the vector to be tested and the vector to be tested into the chip to be tested comprises: setting the power of the heating device, and inputting the target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested; the power of the heating device is determined according to the power and the total power of the vector to be measured under the target operating frequency; and the total power is the sum of the power of the test vector in which the chip to be tested is running and the power of the heating device when the junction temperature of the chip to be tested is maintained at the target temperature.

In one possible implementation manner, the reference power is the power of a reference vector, and the reference vector is one of a plurality of test vectors of the chip to be tested; or the reference power is total power, wherein the total power is the sum of the power of a test vector in which the chip to be tested is running and the power of the heating device when the junction temperature of the chip to be tested is maintained at the target temperature.

In one possible implementation manner, the controlling the junction temperature of the chip to be tested by controlling the temperature compensation device includes: obtaining the shell temperature of the chip to be tested from at least one temperature sensor in contact with the package of the chip to be tested; controlling the junction temperature of the chip to be tested by controlling a temperature compensation device according to the shell temperature of the chip to be tested; or obtaining the junction temperature of the chip to be tested from at least one temperature sensor in the chip to be tested; and controlling the junction temperature of the chip to be tested by controlling a temperature compensation device according to the junction temperature of the chip to be tested.

In a second aspect, the present application provides a temperature control apparatus comprising: a processor and a temperature compensation device; the processor is used for inputting the target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested, and controlling the junction temperature of the chip to be tested by controlling the temperature compensation device in the process that the chip to be tested executes the vector to be tested under the target operating frequency; the temperature compensation device is used for compensating the junction temperature of the chip to be tested; the target operating frequency is determined according to reference power, the vector to be tested is any one of a plurality of test vectors of the chip to be tested, and the reference power is used for indicating a fluctuation standard of power of the vector to be tested.

In one possible implementation manner, the processor is specifically configured to control the junction temperature of the chip to be tested below a target temperature; the target temperature is determined according to a test item to which the vector to be tested belongs.

In one possible implementation, the temperature compensation device includes a cooling device; the processor is specifically configured to increase the power of the cooling device if the power of the vector to be tested at the target operating frequency is greater than the reference power, and input the target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested; and if the power of the vector to be tested under the target operating frequency is smaller than or equal to the reference power, inputting the target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested.

In one possible implementation manner, the processor is specifically configured to maintain the junction temperature of the chip to be tested at a target temperature; the target temperature is determined according to a test item to which the vector to be tested belongs.

In one possible implementation, the temperature compensation device comprises a heating device; the processor is specifically configured to set power of the heating device, and input the target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested; the power of the heating device is determined according to the power and the total power of the vector to be measured under the target operating frequency; and the total power is the sum of the power of the test vector in which the chip to be tested is running and the power of the heating device when the junction temperature of the chip to be tested is maintained at the target temperature.

In one possible implementation manner, at least one temperature sensor is arranged in the chip to be tested; the apparatus further comprises: test base plate, probe seat, briquetting and radiator, wherein: the probe seat is arranged on the test substrate and used for placing the chip to be tested and electrically connecting pins of the chip to be tested with the test substrate through probes in the probe seat; the pressing block is positioned on the chip to be tested and is used for applying pressure to the chip to be tested; the radiator is arranged on the pressing block and used for taking out the temperature of the chip to be tested; the processor is specifically configured to input, through the test substrate, a target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested, and control, according to a junction temperature of the chip to be tested obtained from the at least one temperature sensor and by controlling the temperature compensation device, the junction temperature of the chip to be tested in a process that the chip to be tested executes the vector to be tested at the target operating frequency.

In one possible implementation, the apparatus further includes: test base plate, probe seat, briquetting, thermal resistance module, at least one temperature sensor and radiator, wherein: the probe seat is arranged on the test substrate and used for placing the chip to be tested and electrically connecting pins of the chip to be tested with the test substrate through probes in the probe seat; the thermal resistance module is positioned on the chip to be tested and used for balancing the temperature between the chip to be tested and the pressing block; the pressing block is positioned on the thermal resistance module and is used for applying pressure to the chip to be tested; the at least one temperature sensor is contacted with the packaging body of the chip to be tested and is used for measuring the shell temperature of the chip to be tested; the radiator is arranged on the pressing block and used for taking out the temperature of the chip to be tested; the processor is specifically configured to input, through the test substrate, a target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested, and control, according to a shell temperature of the chip to be tested obtained from the at least one temperature sensor and by controlling the temperature compensation device, a junction temperature of the chip to be tested in a process that the chip to be tested executes the vector to be tested at the target operating frequency.

In a third aspect, the application provides a computer readable storage medium comprising a computer program which, when executed on a computer or processor, causes the computer or processor to perform the method of any of the first aspects.

In a fourth aspect, the present application provides a computer program for performing the method of any of the first aspects when the computer program is executed by a computer or processor.

In a fifth aspect, the present application provides an electronic device comprising the temperature control apparatus of any one of the second aspects.

Drawings

Fig. 1 is a schematic structural diagram of a temperature control device according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a temperature control device in a first application scenario provided in an embodiment of the present application;

fig. 3 is a schematic structural diagram of a temperature control device in a second application scenario provided in an embodiment of the present application;

fig. 4 is a schematic structural diagram of a temperature control device in a third application scenario provided in an embodiment of the present application;

fig. 5 is a schematic structural diagram of a temperature control device in a fourth application scenario provided in an embodiment of the present application;

FIG. 6 is a schematic diagram of a processor according to an embodiment of the present application;

Fig. 7 is a schematic flow chart of a temperature control method according to an embodiment of the present application.

Detailed Description

The technical scheme of the application will be described below with reference to the accompanying drawings.

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terms "first," "second," and the like in the description and in the claims and drawings are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion, such as a series of steps or elements. The method, system, article, or apparatus is not necessarily limited to those explicitly listed but may include other steps or elements not explicitly listed or inherent to such process, method, article, or apparatus.

It should be understood that in the present application, "at least one (item)" means one or more, and "a plurality" means two or more. "and/or" for describing the association relationship of the association object, the representation may have three relationships, for example, "a and/or B" may represent: only a, only B and both a and B are present, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.

In order to solve the technical problems, the application provides a temperature control device, which can control the power consumption of test vectors within a certain range and reduce the power consumption difference between different test vectors, thereby reducing the heat fluctuation generated when a chip to be tested is switched between different test vectors and further reducing the difficulty in controlling the junction temperature of the chip to be tested.

It should be noted that, the chip to be tested herein refers to a packaged chip, that is, the chip to be tested includes a die (that is, the chip itself) and a package. The junction temperature of the die under test refers to the temperature of the die in the die under test.

The principle of the temperature control device provided by the application is as follows:

the greater the power consumption of the test vector, the more heat is generated when the chip under test executes the test vector. And the power consumption of the test vector and the power of the test vector are in positive correlation. Therefore, the higher the power of the test vector, the more heat is generated when the chip under test executes the test vector.

The power of the test vector can be calculated by the following formula:

P _n to test the power of vector n, k _n For the constant of the test vector n, V _n IO port voltage, f when test vector n is executed for chip to be tested _n (k) For the operating frequency of test vector n, [ fmin, fmax ]]For the operable frequency range of test vector n, f _n (k)∈[fmin，fmax]Fmin and fmax are determined by the chip under test.

Note that k corresponding to different test vectors _n Different, V corresponding to different test vectors _n Different, different test vectors can run frequency ranges [ fmin, fmax ]]The same applies.

Since the operating frequency of the test vector has an operable frequency range, the power of the test vector can be adjusted by adjusting the operating frequency of the test vector.

Based on the method, the power of the test vector can be adjusted by adjusting the operation frequency of the test vector, so that the power consumption of the test vector is adjusted, the power consumption of the test vector is controlled within a certain range, the power consumption difference between different test vectors is reduced, and further, the heat fluctuation generated when the chip to be tested is switched between different test vectors is reduced, so that the control difficulty of the junction temperature of the chip to be tested is reduced.

Next, a temperature control device constructed based on the above principle will be described.

Fig. 1 is a schematic structural diagram of a temperature control device according to an embodiment of the present application, as shown in fig. 1, where the temperature control device includes: a processor 110 and a temperature compensation device 120. Wherein:

the processor 110 includes, but is not limited to, a Central Processing Unit (CPU), a Microcontroller (MCU), a Digital Signal Processor (DSP), a Neural Processing Unit (NPU), or a microprocessor, etc. The processor 110 is configured to input the target operating frequency of the vector to be measured and the vector to be measured to the chip to be measured 130, and control the junction temperature of the chip to be measured 130 by controlling the temperature compensation device 120 during the process of executing the vector to be measured by the chip to be measured 130 at the target operating frequency. The target operating frequency of the vector to be measured is determined according to the reference power. The vector under test is any one of a plurality of test vectors of the chip under test 130. The reference power is used to indicate a fluctuating basis of the power of the vector to be measured. The temperature compensation device 120 is used for compensating the junction temperature of the chip 130 to be tested. The specific implementation manner of the temperature compensation device 120 is determined according to the application scenario of the temperature control device. For example, the temperature compensation device 120 includes a heating device and a cooling device. As another example, the temperature compensation device 120 includes a temperature reduction device. The heating device comprises but is not limited to a heating rod and the like, and the cooling device comprises but is not limited to a fan, a water cooling device and the like.

From the above, the target operating frequency of the to-be-measured vector is determined according to the reference power, where the reference power is used to indicate the fluctuation standard of the power of the to-be-measured vector, that is, the reference power is used as the reference to determine the target operating frequency of the to-be-measured vector, so that the power consumption of the to-be-measured vector is limited in a certain range, the power consumption difference between different to-be-measured vectors is reduced, and further, the heat fluctuation generated when the to-be-measured chip 130 switches between different to-be-measured vectors is reduced, thereby reducing the difficulty in controlling the junction temperature of the to-be-measured chip 130.

Since the temperature control device controls the junction temperature of the chip 130 to be tested in the process of testing the chip 130 to be tested, the related components for testing the chip 130 to be tested may be included in the temperature control device or not, and the application is not limited thereto.

In controlling the junction temperature of the chip 130 to be tested, the following two cases exist for the basic number to be adopted. Wherein:

first, the basic data is the shell temperature of the chip 130 to be tested, that is, the shell temperature of the chip 130 to be tested is obtained, and the junction temperature of the chip 130 to be tested is controlled by the shell temperature of the chip 130 to be tested.

Second, the base data is the junction temperature of the chip 130 to be tested, that is, the junction temperature of the chip 130 to be tested is obtained, and the junction temperature of the chip 130 to be tested is controlled by the junction temperature of the chip 130 to be tested.

In controlling the junction temperature of the chip 130 to be measured, the following two cases exist as targets of temperature control. Wherein:

first, the junction temperature of the chip under test 130 is controlled below the target temperature. The target temperature is determined according to the test item to which the vector to be tested belongs. Test items include, but are not limited to: ATE tests, functional tests, etc. require test items that control the junction temperature of the chip 130 under test to a certain temperature. For example, the target temperature is an irreversible failure temperature of the chip 130 under test.

Second, the junction temperature of the chip under test 130 is maintained at the target temperature. The target temperature is determined according to the test item to which the vector to be tested belongs. Test items include, but are not limited to: burn-in test, etc. require test items to maintain the junction temperature of the chip 130 to be tested at a certain temperature. For example, the target temperature is a temperature capable of exposing a weak spot of the chip 130 under test.

The relevant components to test the chip 130 under test are different due to the different underlying data employed. The determination mode of the reference power, the specific implementation mode of the temperature compensation device 120, and the determination mode of the target operating frequency of the vector to be measured are different due to different targets of temperature control. Accordingly, hereinafter, the structure and operation of the temperature control apparatus including the related components for testing the chip 130 to be tested will be described in detail in four application scenarios composed of two kinds of basic data and two kinds of temperature control targets.

Fig. 2 is a schematic structural diagram of a temperature control device in a first application scenario provided in an embodiment of the present application. In the first application scenario, the adopted basic data is the junction temperature of the chip 130 to be tested, and the temperature control target is to control the junction temperature of the chip 130 to be tested below the target temperature.

Since the basic data is the junction temperature of the chip 130 to be measured, at least one temperature sensor (not shown in fig. 2) is required to be disposed in the chip 130 to be measured, so as to obtain the junction temperature of the chip 130 to be measured through the at least one temperature sensor. Implementations of the temperature sensor include, but are not limited to, PN junctions. Since the temperature control is aimed at controlling the junction temperature of the chip 130 to be measured below the target temperature, the temperature compensation device 120 is a temperature reduction device 121.

As shown in fig. 2, the temperature control device includes: processor 110, cooling device 121, test substrate 140, probe mount 150, compact 160, and heat sink 170. Wherein:

the probe seat 150 is disposed on the test substrate 140, and the probe seat 150 is used for placing the chip 130 to be tested and electrically connecting pins of the chip 130 to be tested with the test substrate 140 through probes in the probe seat 150.

The pressing block 160 is located on the chip to be tested 130, and the pressing block 160 is used for applying pressure to the chip to be tested 130 so as to ensure that pins of the chip to be tested 130 are fully contacted with probes.

The radiator 170 is disposed on the pressing block 160, and the radiator 170 is used for taking out the temperature of the chip 130 to be tested, so as to exchange the taken-out temperature with the cooling device 121, and perform the function of cooling.

The processor 110 is disposed on a test substrate 140. The test substrate 140 is provided with a printed circuit (not shown in fig. 4), and the processor 110 is connected to the probes in the probe seats 150 through the printed circuit on the test substrate 140, so that the processor 110 can communicate with the chip 130 to be tested through the printed circuit and the probes and supply power signals to the chip 130 to be tested. In addition, the cooling device 121 is connected to the printed circuit on the test substrate 140, so that the processor 110 can provide a power signal to the cooling device 121 through the printed circuit and control the cooling device 121.

It should be noted that, in other embodiments, the processor 110 may be disposed outside the test substrate 140, and the processor 110 and the cooling device 121 may be connected to the test substrate through electrical connectors disposed on the test substrate 140. The electrical connectors are connected to printed circuits on the test substrate 140.

The processor 110 is configured to provide a power signal to the chip 130 to be tested, input a target operating frequency of the vector to be tested and the vector to be tested into the chip 130 to be tested, and obtain a junction temperature of the chip 130 to be tested from at least one temperature sensor in the chip 130 to be tested in a process that the chip 130 to be tested executes the vector to be tested at the target operating frequency of the vector to be tested, control the junction temperature of the chip 130 to be tested below the target temperature according to the obtained junction temperature of the chip 130 to be tested by controlling the cooling device 121. The processor 110 is also configured to provide a power signal to the temperature reduction device 121 and to control the temperature reduction device 121.

The reference power is determined in two ways including, but not limited to:

first, the reference power may be the power of a reference vector, which is one of a plurality of test vectors of the chip under test 130. Specifically, the reference vector may be any one of a plurality of test vectors of the chip under test 130. The reference vector may also be a specified one of a plurality of test vectors of the chip under test 130, such as a test vector with the lowest operating frequency and the highest power. The power of the reference vector can be obtained according to the power calculation formula of the test vector. It should be noted that the operating frequency used in calculating the power of the reference vector may be an operating frequency within the operable frequency range of the reference vector.

Second, the reference power may be one power in a power range of a plurality of test vectors of the chip under test 130. Specifically, the reference power may be any power in a power range of a plurality of test vectors of the chip under test 130. The reference power may also be a specified one of a range of powers for a plurality of test vectors for the chip under test 130, e.g., an intermediate value of the range of powers. The process of determining the power ranges of the plurality of test vectors for the chip under test 130 is: and calculating the power range of each test vector in the plurality of test vectors, and performing union on the power ranges of the test vectors to obtain the power ranges of the plurality of test vectors. It should be noted that the above description of the reference power is only exemplary and is not intended to limit the present application.

The mode of determining the target operating frequency of the vector to be measured is as follows: the default power of the vector to be measured is compared with the reference power. The default power of the vector to be measured is the power of the vector to be measured under the default operating frequency of the vector to be measured. The default operating frequency of the vector under test is one operating frequency in the operable frequency range of the vector under test. Specifically, the default operating frequency of the vector to be measured may be any operating frequency in an operable frequency range of the vector to be measured. The default operating frequency of the vector under test may also be a specified one of the operable frequency ranges of the vector under test, e.g., a median or minimum value of the operable frequency ranges. If the default power of the vector to be measured is smaller than or equal to the reference power, the target operating frequency of the vector to be measured is the default operating frequency of the vector to be measured. If the default power of the vector to be measured is greater than the reference power, the target operating frequency of the vector to be measured is the minimum operating frequency in the operable frequency range of the vector to be measured.

The test and temperature control process will be described below by way of example. The specific process is as follows:

the processor 110 inputs the operating frequency of the vector 1 to be tested and the vector 1 to be tested into the chip 130 to be tested. The operating frequency of the vector 1 to be measured is one operating frequency in the operable frequency range of the vector 1 to be measured.

During the execution of the vector 1 under test by the chip 130 under test at the operating frequency of the vector 1 under test, the processor 110 obtains the junction temperature of the chip 130 under test from at least one temperature sensor in the chip 130 under test.

The processor 110 compares the junction temperature of the chip 130 to be tested with the target temperature, and if the junction temperature of the chip 130 to be tested is greater than the target temperature, increases the power of the cooling device 121 to enhance the cooling strength of the chip 130 to be tested, for example, increases the rotation speed of the fan, accelerates heat dissipation until the junction temperature of the chip 130 to be tested is ensured to be maintained below the target temperature. Taking the vector 1 to be measured as a reference vector, calculating the power of the reference vector according to the formula, and taking the power of the reference vector as the reference power. Ways to increase the power of the temperature reduction device 121 include, but are not limited to, increasing the operating voltage and/or current of the temperature reduction device 121.

Processor 110 determines the target operating frequency of vector 2 under test. Specifically, if the default power of the to-be-measured vector 2 is less than or equal to the reference power, determining the default operating frequency of the to-be-measured vector 2 as the target operating frequency of the to-be-measured vector 2. If the default power of the to-be-measured vector 2 is greater than the reference power, determining the minimum operating frequency in the operable frequency range of the to-be-measured vector 2 as the target operating frequency of the to-be-measured vector 2.

The processor 110 inputs the target operating frequency of the vector 2 to be tested and the vector 2 to be tested into the chip 130 to be tested.

In the process that the chip to be tested 130 executes the vector to be tested 2 under the target operating frequency of the vector to be tested 2, the processor 110 obtains the junction temperature of the chip to be tested 130 from at least one temperature sensor in the chip to be tested 130, combines a PID algorithm, a linear temperature control algorithm and the like according to the junction temperature of the chip to be tested 130, and dynamically adjusts the junction temperature of the chip to be tested 130 by controlling the cooling device 121 so that the junction temperature of the chip to be tested 130 is smaller than the target temperature.

The remaining vectors to be measured are performed based on the principle of performing the vector to be measured 2.

From the above, the calculation of the reference power and the target operating frequency of the vector to be measured is calculated in real time during the test and temperature control processes. In other embodiments of the present application, the reference power and the target operating frequency of the vector to be measured may also be calculated in advance in an offline manner. The target operating frequency of each test vector in the reference power and the plurality of test vectors is calculated in advance, so that the target operating frequency of the vector to be tested is directly obtained from the target operating frequencies of the plurality of test vectors in the test process, and online calculation is not needed.

In order to increase the stability and accuracy of temperature control and ensure the stability of the temperature of the chip 130 to be measured, before inputting the target operating frequency of the vector to be measured and the vector to be measured into the chip 130 to be measured, the processor 110 may also calculate the power of the vector to be measured at the target operating frequency, compare the power of the vector to be measured at the target operating frequency with the reference power, and if the power of the vector to be measured at the target operating frequency is greater than the reference power, increase the power of the cooling device 121 first to increase the cooling force, and then input the target operating frequency of the vector to be measured and the vector to be measured into the chip 130 to be measured. If the power of the vector to be measured at the target operating frequency is less than or equal to the reference power, the target operating frequency of the vector to be measured and the vector to be measured are input to the chip to be measured 130 without adjusting the power of the cooling device 121.

Obviously, before the vector to be measured is input into the chip to be measured 130, if the power of the vector to be measured at the target operating frequency is greater than the reference power, the power of the cooling device 121 is increased to increase the cooling strength of the chip to be measured 130. That is, the power of the cooling device 121 is predicted in advance, and the power of the cooling device 121 is adjusted according to the prediction result, so as to perform temperature compensation in advance, improve the stability and accuracy of temperature control, and ensure the stability of the temperature of the chip 130 to be tested.

It should be noted that, the test substrate 140, the probe seat 150, the pressing block 160, and the heat sink 170 are related components for testing the chip 130 to be tested.

Fig. 3 is a schematic structural diagram of a temperature control device in a second application scenario provided in an embodiment of the present application. In the second application scenario, the basic data is the shell temperature of the chip 130 to be tested, and the temperature control is to control the junction temperature of the chip 130 to be tested below the target temperature.

The temperature control device in fig. 3 is structurally different from the temperature control device in fig. 2 in that: a thermal resistance module 180, at least one temperature sensor 190, is added to the temperature control device shown in fig. 3. The thermal resistance module 180 is located between the chip to be measured 130 and the pressing block 160, and the thermal resistance module 180 balances the temperature between the chip to be measured 130 and the pressing block 160 to improve the measurement accuracy of the shell temperature of the chip to be measured 130. The material of the thermal resistance module 180 may be, for example, indium, etc., which is not limited in the present application. Since the basic data adopted in this scenario is the shell temperature of the chip 130 to be tested, there is no need to provide a temperature sensor in the chip 130 to be tested, and at least one temperature sensor 190 needs to be provided on the package of the chip 130 to be tested, so as to obtain the shell temperature of the chip 130 to be tested through the at least one temperature sensor 190. The at least one temperature sensor 190 is connected to a printed circuit on the test substrate 140, and the processor 110 is connected to the at least one temperature sensor 190 through the printed circuit to provide a power signal to the at least one temperature sensor 190 and to obtain the case temperature of the chip 130 under test from the at least one temperature sensor 190.

The temperature control device in fig. 3 is different from the temperature control device in fig. 2 in the execution flow, in that: in the process of controlling the junction temperature of the chip to be measured 130, the processor 110 obtains the case temperature of the chip to be measured 130 from at least one temperature sensor 190 in contact with the package of the chip to be measured 130, estimates the junction temperature of the chip to be measured 130 according to the case temperature of the chip to be measured 130, and then controls the junction temperature of the chip to be measured 130 to be below the target temperature by controlling the cooling device 121 according to the estimated junction temperature of the chip to be measured 130.

It should be noted that the test substrate 140, the probe holder 150, the pressing block 160, the thermal resistance module 180, the at least one temperature sensor 190, and the heat sink 170 are related components for testing the chip 130 to be tested.

Fig. 4 is a schematic structural diagram of a temperature control device in a third application scenario provided in an embodiment of the present application. In the third application scenario, the adopted basic data is the junction temperature of the chip 130 to be tested, and the temperature control target is to maintain the junction temperature of the chip 130 to be tested at the target temperature. It should be noted that, maintaining the junction temperature of the chip 130 to be measured at the target temperature means that the absolute value of the difference between the target temperature and the junction temperature of the chip 130 to be measured is smaller than a preset error value, and the preset error value may be set according to design requirements.

Since the temperature control is aimed at maintaining the junction temperature of the chip 130 to be measured at the target temperature, the temperature compensating device 120 includes a cooling device 121 and a heating device 122.

The temperature control device in fig. 4 is structurally different from the temperature control device in fig. 2 in that: a heating device 122 is added to the temperature control device shown in fig. 4.

The positional relationship and the functions of the cooling device 121, the test substrate 140, the probe holder 150, the pressing block 160, and the heat sink 170 have been described in fig. 2, and are not repeated here. The heating device 122 is disposed in the briquette 160. It should be noted that, in other embodiments, the heating device 122 may also be disposed between the pressing block 160 and the chip 130 to be tested, which is not limited in particular by the present application. The heating device 122 is connected to a printed circuit on the test substrate 140. The processor 110 provides a power signal to the heating device 122 via the printed circuit and controls the heating device 122, for example, increases the power of the heating device 122 to increase the heating power of the chip 130 to be tested, and for example, decreases the power of the heating device 122 to decrease the heating power of the chip 130 to be tested. Ways to increase the power of the heating device 122 include, but are not limited to, increasing the operating voltage and/or current of the heating device 122. Ways to reduce the power of the heating device 122 include, but are not limited to, reducing the operating voltage and/or current of the heating device 122.

The processor 110 is configured to provide a power signal to the chip 130 to be tested, input a target operating frequency of the vector to be tested and the vector to be tested into the chip 130 to be tested, and obtain a junction temperature of the chip 130 to be tested from at least one temperature sensor in the chip 130 to be tested in a process that the chip 130 to be tested executes the vector to be tested at the target operating frequency of the vector to be tested, and control and maintain the junction temperature of the chip 130 to be tested at the target temperature by controlling the cooling device 121 and/or the heating device 122 according to the obtained junction temperature of the chip 130 to be tested. The processor 110 is also configured to provide power signals to the cooling device 121 and the heating device 122, and to control the cooling device 121 and the heating device 122.

The manner of determining the reference power includes, but is not limited to, the following three manners:

first, the reference power is the power of the reference vector, which has been described above and is not Zhu Zhuishu.

Second, the reference power may also be one power in a power range of a plurality of test vectors of the chip under test 130. The second way has been described above and will not be described here again.

Third, the reference power is the total power, where the total power is the sum of the power of the test vector in which the chip 130 under test is running and the power of the heating device 122 when the junction temperature of the chip 130 under test is maintained at the target temperature.

The method for determining the target operating frequency of the vector to be detected is as follows: the target operating frequency of the vector to be measured is a first operating frequency in the operable frequency range of the vector to be measured; wherein the power of the vector to be measured at the first operating frequency is closest to the reference power.

Obviously, by determining the operating frequency when the power of the to-be-measured vector is closest to the reference power as the target operating frequency of the to-be-measured vector, the power of the to-be-measured vector is closest to the reference power under the target operating frequency, namely, the power of the to-be-measured vector is close to the reference power by adjusting the target operating frequency, so that the power of the to-be-measured vector is controlled within a certain range, the power consumption difference among different to-be-measured vectors is reduced, the heat fluctuation generated when the to-be-measured chip 130 is switched among different to-be-measured vectors is reduced, and the junction temperature control difficulty of the to-be-measured chip 130 is reduced.

The processor 110 compares the junction temperature of the chip 130 to be tested with the target temperature, and if the junction temperature of the chip 130 to be tested is greater than the target temperature, increases the power of the cooling device 121 to strengthen the cooling strength of the chip 130 to be tested and/or decrease the power of the heating device 122 to decrease the heating strength of the chip 130 to be tested, for example, increase the rotation speed of the fan, accelerate heat dissipation, decrease the power of the heating rod, and decrease the heating efficiency until the junction temperature of the chip 130 to be tested is maintained at the target temperature. If the junction temperature of the chip 130 to be tested is less than the target temperature, the power of the heating device 122 is increased to increase the heating power of the chip 130 to be tested and/or decrease the power of the cooling device 121 to decrease the cooling power of the chip 130 to be tested, for example, increase the power of the heating rod, accelerate heating, decrease the rotation speed of the fan, decrease the heat dissipation efficiency, until the junction temperature of the chip 130 to be tested is maintained at the target temperature.

Under the condition that the junction temperature of the chip 130 to be tested is maintained at the target temperature, taking the vector 1 to be tested as a reference vector, calculating the power of the reference vector according to the formula, taking the power of the reference vector as the reference power, or determining the power of the vector 1 to be tested and the power of the heating device 122, adding the power of the vector 1 to be tested and the power of the heating device 122 to obtain the total power, and taking the total power as the reference power.

The processor 110 determines a target operating frequency of the vector to be measured 2, wherein the target operating frequency of the vector to be measured 2 is a first operating frequency in an operable frequency range of the vector to be measured 2; wherein the power of the vector to be measured 2 at the first operating frequency is closest to the reference power.

In the process of the chip 130 to be tested executing the vector 2 to be tested, the processor 110 obtains the junction temperature of the chip 130 to be tested from at least one temperature sensor in the chip 130 to be tested, combines a PID algorithm, a linear temperature control algorithm and the like according to the junction temperature of the chip 130 to be tested, and dynamically adjusts the junction temperature of the chip 130 to be tested by controlling the cooling device 121 and/or the heating device 122 so as to maintain the junction temperature of the chip 130 to be tested at the target temperature.

In order to increase the stability and accuracy of temperature control and ensure the stability of the temperature of the chip 130 to be measured, the processor 110 may further determine the power of the heating device 122 before inputting the vector to be measured into the chip 130 to be measured, then set the power of the heating device 122, and input the target operating frequency of the vector to be measured and the vector to be measured into the chip 130 to be measured.

The power of the heating device 122 is determined in the following manner: if the difference between the total power and the power of the vector to be measured at the target operating frequency is greater than 0, the power of the heating device 122 is the difference, and if the difference between the total power and the power of the vector to be measured at the target operating frequency is not greater than 0, the power of the heating device 122 is 0.

Obviously, before the vector to be measured is input into the chip 130 to be measured, the power of the heating device 122 is determined according to the power and the total power of the vector to be measured at the target operating frequency, and the power of the heating device 122 is set, that is, the power of the heating device 122 is predicted in advance, and the power of the heating device 122 is set according to the prediction result, so that temperature compensation is performed in advance, the stability and the accuracy of temperature control are improved, and the stability of the temperature of the chip 130 to be measured is ensured.

Fig. 5 is a schematic structural diagram of a temperature control device in a fourth application scenario provided in an embodiment of the present application. In the fourth application scenario, the basic data is the shell temperature of the chip 130 to be tested, and the temperature control is aimed at maintaining the junction temperature of the chip 130 to be tested at the target temperature.

The temperature control device in fig. 5 is structurally different from the temperature control device in fig. 4 in that: a thermal resistance module 180, at least one temperature sensor 190, is added to the temperature control device shown in fig. 5. The thermal resistance module 180 is located between the chip to be measured 130 and the pressing block 160, and the thermal resistance module 180 is used for equalizing the temperature between the chip to be measured 130 and the pressing block 160 so as to improve the measurement accuracy of the shell temperature of the chip to be measured 130. The materials of the thermal resistance module 180 have been described above and will not be described again here. Since the basic data adopted in this scenario is the shell temperature of the chip 130 to be tested, there is no need to provide a temperature sensor in the chip 130 to be tested, and at least one temperature sensor 190 needs to be provided on the package of the chip 130 to be tested, so as to obtain the shell temperature of the chip 130 to be tested through the at least one temperature sensor 190. The at least one temperature sensor 190 is connected to a printed circuit on the test substrate 140, and the processor 110 is connected to the at least one temperature sensor 190 through the printed circuit to provide a power signal to the at least one temperature sensor 190 and to obtain the case temperature of the chip 130 under test from the at least one temperature sensor 190.

The temperature control apparatus in fig. 5 is different from the temperature control apparatus in fig. 4 in the execution flow, in that: in the process of controlling the junction temperature of the chip to be measured 130, the processor 110 obtains the shell temperature of the chip to be measured 130 from at least one temperature sensor in contact with the package of the chip to be measured 130, estimates the junction temperature of the chip to be measured 130 according to the shell temperature of the chip to be measured 130, and then maintains the junction temperature of the chip to be measured 130 at the target temperature according to the estimated junction temperature of the chip to be measured 130 by controlling the cooling device 121 and/or the heating device 122.

In the above, in the scenario where the adopted basic data is the junction temperature of the chip 130 to be tested, the components for testing the chip 130 to be tested are relatively simple and have low cost.

Fig. 6 is a schematic structural diagram of a processor according to an embodiment of the present application. As shown in fig. 6, the processor 110 includes: a test vector control circuit 111, a temperature obtaining circuit 112, a test vector transmitting circuit 113, and a temperature compensation control circuit 114. Wherein: the test vector control circuit 111 is configured to determine a target operating frequency of the vector to be tested, and send the target operating frequency of the vector to be tested and the vector to be tested to the test vector sending circuit 113. The test vector transmitting circuit 113 is used for inputting the target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested 130. The temperature obtaining circuit 112 is configured to obtain a junction temperature of the chip to be tested 130 or a shell temperature of the chip to be tested 130, and transmit the junction temperature of the chip to be tested 130 or the shell temperature of the chip to be tested 130 to the test vector control circuit 111. The test vector control circuit 111 is further configured to generate a temperature control signal according to the junction temperature of the chip to be tested 130 or the shell temperature of the chip to be tested 130 in combination with the target temperature, and transmit the temperature control signal to the temperature compensation control circuit 114. The temperature compensation control circuit 114 is configured to control the temperature compensation device 120 in response to the temperature control signal, for example, when the temperature compensation device 120 is the temperature reduction device 121, increase or decrease the power of the temperature reduction device 121 to increase or decrease the temperature reduction force of the temperature reduction device 121, and for example, when the temperature compensation device 120 is the heating device 122, increase or decrease the power of the heating device 122 to increase or decrease the heating force of the heating device 122.

It should be noted that the above description about the processor 110 is only exemplary, and is not intended to limit the present embodiment.

The application also provides a temperature control method, as shown in fig. 7, comprising the following steps: 701. and inputting the target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested. 702. In the process that the chip to be tested executes the vector to be tested under the target operating frequency, controlling the junction temperature of the chip to be tested by controlling a temperature compensation device; the target operating frequency is determined according to reference power, the vector to be tested is any one of a plurality of test vectors of the chip to be tested, and the reference power is used for indicating a fluctuation standard of power of the vector to be tested.

The implementation principle and technical effects of the temperature control method of the present application have been described above, and are not repeated here.

The application also provides a computer readable storage medium, in which a computer program is stored, which when executed on a computer or a processor causes the computer or the processor to execute the technical solution of any one of the method embodiments.

The application also provides a computer program product which, when executed by a computer, causes the computer or processor to carry out the technical solutions of any of the method embodiments described above.

The application also provides electronic equipment comprising the temperature control device.

The application also provides a chip comprising a processor and a memory, wherein the processor is used for executing the technical scheme of any one of the method embodiments.

Further, the chip may also include a memory and a communication interface. The communication interface may be an input/output interface, a pin or an input/output circuit, etc.

In the implementation process, the steps of the method embodiment can be completed through an integrated logic circuit of hardware in a network card or instructions in a software form. The processor may be a general purpose processor, a digital signal processor (digital signal processor, DSP), an Application Specific Integrated Circuit (ASIC), a field programmable gate array (field programmable gate array, FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in the embodiment of the application can be directly embodied in a hardware encoding processor for execution or in a combination of hardware and software modules in the encoding processor for execution. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor reads the information in the memory and, in combination with its hardware, performs the steps of the above method.

The memory mentioned in the above embodiments may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. The volatile memory may be random access memory (random access memory, RAM) which acts as an external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (personal computer, server, network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a read-only memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A method of controlling temperature, comprising:

inputting the target operating frequency of the vector to be tested and the vector to be tested into a chip to be tested;

in the process that the chip to be tested executes the vector to be tested under the target operating frequency, controlling the junction temperature of the chip to be tested by controlling a temperature compensation device;

the target operating frequency is determined according to reference power, the vector to be tested is any one of a plurality of test vectors of the chip to be tested, and the reference power is used for indicating a fluctuation standard of power of the vector to be tested.
The method of claim 1, wherein controlling the junction temperature of the chip under test comprises:

controlling the junction temperature of the chip to be tested below a target temperature;

The target temperature is determined according to a test item to which the vector to be tested belongs.
The method of claim 2, wherein the step of determining the position of the substrate comprises,

if the default power of the vector to be tested is smaller than or equal to the reference power, the target operating frequency is the default operating frequency of the vector to be tested;

if the default power of the vector to be tested is larger than the reference power, the target operating frequency is the minimum operating frequency in the operable frequency range of the vector to be tested;

the default power of the to-be-measured vector is the power of the to-be-measured vector under the default operating frequency, and the default operating frequency of the to-be-measured vector is one operating frequency in the operable frequency range of the to-be-measured vector.
A method according to claim 2 or 3, wherein the temperature compensation means comprises a cooling means;

the inputting the target running frequency of the vector to be tested and the vector to be tested into the chip to be tested comprises:

if the power of the vector to be tested under the target operating frequency is larger than the reference power, increasing the power of the cooling device, and inputting the target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested;

And if the power of the vector to be tested under the target operating frequency is smaller than or equal to the reference power, inputting the target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested.
The method according to any one of claims 2-4, wherein the reference power is a power of a reference vector, the reference vector being one of a plurality of test vectors of the chip under test.
The method of claim 1, wherein controlling the junction temperature of the chip under test comprises:

maintaining the junction temperature of the chip to be tested at a target temperature;

the target temperature is determined according to a test item to which the vector to be tested belongs.
The method of claim 6, wherein the target operating frequency is a first operating frequency in an operable frequency range of the vector under test;

wherein the power of the vector to be measured at the first operating frequency is closest to the reference power.
The method according to claim 6 or 7, wherein the temperature compensation means comprises heating means;

the inputting the target running frequency of the vector to be tested and the vector to be tested into the chip to be tested comprises:

Setting the power of the heating device, and inputting the target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested;

the power of the heating device is determined according to the power and the total power of the vector to be measured under the target operating frequency;

and the total power is the sum of the power of the test vector in which the chip to be tested is running and the power of the heating device when the junction temperature of the chip to be tested is maintained at the target temperature.
The method according to any one of claims 6 to 8, wherein the reference power is the power of a reference vector, the reference vector being one of a plurality of test vectors of the chip under test; or alternatively

The reference power is total power, wherein the total power is the sum of the power of a test vector in which the chip to be tested is running and the power of the heating device when the junction temperature of the chip to be tested is maintained at the target temperature.
The method according to any one of claims 1 to 9, wherein controlling the junction temperature of the chip under test by controlling a temperature compensation device comprises:

obtaining the shell temperature of the chip to be tested from at least one temperature sensor in contact with the package of the chip to be tested;

Controlling the junction temperature of the chip to be tested by controlling a temperature compensation device according to the shell temperature of the chip to be tested; or alternatively

Obtaining the junction temperature of the chip to be tested from at least one temperature sensor in the chip to be tested;

and controlling the junction temperature of the chip to be tested by controlling a temperature compensation device according to the junction temperature of the chip to be tested.
A temperature control apparatus, comprising: a processor and a temperature compensation device; wherein,

the processor is used for inputting the target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested, and controlling the junction temperature of the chip to be tested by controlling the temperature compensation device in the process that the chip to be tested executes the vector to be tested under the target operating frequency;

the temperature compensation device is used for compensating the junction temperature of the chip to be tested;

the target operating frequency is determined according to reference power, the vector to be tested is any one of a plurality of test vectors of the chip to be tested, and the reference power is used for indicating a fluctuation standard of power of the vector to be tested.
The device according to claim 11, wherein the processor is specifically configured to control the junction temperature of the die under test below a target temperature;

The target temperature is determined according to a test item to which the vector to be tested belongs.
The apparatus of claim 12, wherein the device comprises a plurality of sensors,

if the default power of the vector to be tested is smaller than or equal to the reference power, the target operating frequency is the default operating frequency of the vector to be tested;

if the default power of the vector to be tested is larger than the reference power, the target operating frequency is the minimum operating frequency in the operable frequency range of the vector to be tested;

the default power of the to-be-measured vector is the power of the to-be-measured vector under the default operating frequency, and the default operating frequency of the to-be-measured vector is one operating frequency in the operable frequency range of the to-be-measured vector.
The apparatus of claim 12 or 13, wherein the temperature compensation means comprises a cooling means;

the processor is specifically configured to increase the power of the cooling device if the power of the vector to be tested at the target operating frequency is greater than the reference power, and input the target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested; and if the power of the vector to be tested under the target operating frequency is smaller than or equal to the reference power, inputting the target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested.
The apparatus of any of claims 12-14, wherein the reference power is a power of a reference vector, the reference vector being one of a plurality of test vectors of the chip under test.
The device of claim 11, wherein the processor is specifically configured to maintain a junction temperature of the chip under test at a target temperature;

the target temperature is determined according to a test item to which the vector to be tested belongs.
The apparatus of claim 16, wherein the target operating frequency is a first operating frequency in an operable frequency range of the vector under test;

wherein the power of the vector to be measured at the first operating frequency is closest to the reference power.
The apparatus according to claim 16 or 17, wherein the temperature compensation means comprises heating means;

the processor is specifically configured to set power of the heating device, and input the target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested;

the power of the heating device is determined according to the power and the total power of the vector to be measured under the target operating frequency;

And the total power is the sum of the power of the test vector in which the chip to be tested is running and the power of the heating device when the junction temperature of the chip to be tested is maintained at the target temperature.
The apparatus according to any one of claims 16 to 18, wherein the reference power is a power of a reference vector, the reference vector being one of a plurality of test vectors of the chip under test; or alternatively

The reference power is total power, wherein the total power is the sum of the power of a test vector in which the chip to be tested is running and the power of the heating device when the junction temperature of the chip to be tested is maintained at the target temperature.
The device according to any one of claims 11 to 19, wherein at least one temperature sensor is provided in the chip to be tested;

the apparatus further comprises: test base plate, probe seat, briquetting and radiator, wherein:

the probe seat is arranged on the test substrate and used for placing the chip to be tested and electrically connecting pins of the chip to be tested with the test substrate through probes in the probe seat;

the pressing block is positioned on the chip to be tested and is used for applying pressure to the chip to be tested;

The radiator is arranged on the pressing block and used for taking out the temperature of the chip to be tested;

the processor is specifically configured to input, through the test substrate, a target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested, and control, according to a junction temperature of the chip to be tested obtained from the at least one temperature sensor and by controlling the temperature compensation device, the junction temperature of the chip to be tested in a process that the chip to be tested executes the vector to be tested at the target operating frequency.
The apparatus according to any one of claims 11 to 19, further comprising: test base plate, probe seat, briquetting, thermal resistance module, at least one temperature sensor and radiator, wherein:

the probe seat is arranged on the test substrate and used for placing the chip to be tested and electrically connecting pins of the chip to be tested with the test substrate through probes in the probe seat;

the thermal resistance module is positioned on the chip to be tested and used for balancing the temperature between the chip to be tested and the pressing block;

the pressing block is positioned on the thermal resistance module and is used for applying pressure to the chip to be tested;

The at least one temperature sensor is contacted with the packaging body of the chip to be tested and is used for measuring the shell temperature of the chip to be tested;

the radiator is arranged on the pressing block and used for taking out the temperature of the chip to be tested;

the processor is specifically configured to input, through the test substrate, a target operating frequency of the vector to be tested and the vector to be tested into the chip to be tested, and control, according to a shell temperature of the chip to be tested obtained from the at least one temperature sensor and by controlling the temperature compensation device, a junction temperature of the chip to be tested in a process that the chip to be tested executes the vector to be tested at the target operating frequency.
A computer readable storage medium comprising a computer program which, when executed on a computer or processor, causes the computer or processor to perform the method of any of claims 1 to 10.
A computer program for performing the method of any one of claims 1 to 10 when the computer program is executed by a computer or processor.
An electronic device comprising the temperature control apparatus according to any one of claims 11 to 21.