CN114295955A - Chip screening method and device and chip screening equipment - Google Patents
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Abstract
The application provides a chip screening method, a chip screening device and chip screening equipment, wherein the method comprises the following steps: performing board-level test on the plurality of sample chips, determining the sample chips which normally work at the limiting temperature and have the junction temperature value within a first preset range as first target chips, acquiring static current values and oscillation frequency values of the plurality of first target chips, and determining static current threshold values and oscillation frequency threshold values; performing FT test on the first target chip, and determining the first target chip with the junction temperature rise value within a second preset range in preset time as a second target chip; performing board level test on the second target chip, determining the second target chip which normally works at the limit temperature as a third target chip, and acquiring a junction temperature rise value of the third target chip in the FT test to obtain a junction temperature rise threshold; and screening the chip to be tested according to the quiescent current threshold, the oscillation frequency threshold and the junction temperature rise threshold, so that the problem of low chip yield caused by low power consumption limitation of the screening is solved.
Description
Technical Field
The application relates to the technical field of chip testing, in particular to a chip screening method and device and chip screening equipment.
Background
As the power consumption of the chip is getting worse, the excessive power consumption of the chip is one of the main causes of yield loss in chip production. Different wafers and different batches have larger variation range of the MOSFETs parameters due to external factors such as doping, etching, temperature and the like, in order to reduce the design difficulty, the performance of the device needs to be limited within a certain range, and the chip beyond the range is discarded. Based on the two tests, a high-temperature reversal phenomenon exists in a part of chips near a power consumption boundary value, namely, the high-temperature power consumption of the part of chips in a power consumption limit range is abnormal, specifically, the junction temperature exceeds a preset value or the upper limit of the junction temperature of the chip specified by a manufacturer when the chip works, and the high-temperature performance of the part of chips outside the power consumption limit range is normal. If the chip with high temperature inversion phenomenon in the power consumption limit range is not allowed to enter the market, the power consumption limit must be continuously reduced, so that the yield loss of the mass production chip is huge.
Therefore, a new chip screening method is needed to solve the problem of low chip yield caused by low power consumption limitation in the chip mass production screening process.
Disclosure of Invention
The application mainly aims to provide a chip screening method, a chip screening device and chip screening equipment, so as to solve the problem that the chip yield is low due to low power consumption limitation of the chip screening method in the prior art.
According to an aspect of an embodiment of the present invention, there is provided a method of screening a chip, the method comprising: performing board-level test on a plurality of sample chips, wherein the environmental temperature of the board-level test is a limit temperature, determining the sample chip meeting a first preset condition as a first target chip, acquiring static current values and oscillation frequency values of the plurality of first target chips, and determining a static current threshold value and an oscillation frequency threshold value, wherein the limit temperature is the highest environmental temperature of an application scene of the sample chip, and the first preset condition is that the test chip normally works and a junction temperature value is within a first preset range; performing an FT test on the first target chip, and determining the first target chip meeting a second preset condition as a second target chip, wherein the second preset condition is that a junction temperature rise value of the test chip in a preset time is in a second preset range; performing board level test on the second target chip, wherein the environmental temperature of the board level test is the limit temperature, determining the second target chip meeting the first preset condition and the second preset condition as a third target chip, acquiring a junction temperature rise value of the third target chip in the FT test, and determining a junction temperature rise threshold; screening a chip to be tested according to the quiescent current threshold, the oscillation frequency threshold and the junction temperature rise threshold, wherein the chip to be tested and the sample chip are chips with the same model.
Optionally, before performing an FT test on the first target chip and determining the first target chip meeting a second predetermined condition as a second target chip, the method further includes: performing board-level test on the plurality of first target chips, wherein the environment temperature of the board-level test is a limit temperature, and detecting a junction temperature rise value of the first target chip within the preset time under the condition that the junction temperature value of the first target chip is the preset temperature to obtain a first junction temperature rise value; and determining the second preset range according to the first temperature rise value.
Optionally, performing an FT test on the first target chip, and determining the first target chip meeting a second predetermined condition as a second target chip, includes: under the conditions that the test temperature is set temperature and the test excitation is set test excitation, detecting a junction temperature rise value of the first target chip in the preset time to obtain a second junction temperature rise value, wherein the test temperature is the ambient temperature for performing the FT test on the first target chip, and the test excitation is the excitation for performing the FT test on the first target chip; and adjusting the set temperature and the set test excitation until the second target chip is obtained.
Optionally, screening the chip to be tested according to the quiescent current threshold, the oscillation frequency threshold, and the junction temperature rise threshold, including: under the condition that the environmental temperature is the production temperature, obtaining a static current value of the chip to be tested and an oscillation frequency value of an oscillation circuit of the chip to be tested to obtain a target static current value and a target oscillation frequency value, wherein the production temperature is the temperature of the environment where the chip to be tested is in production operation; under the condition that the junction temperature value of the chip to be tested is the preset temperature, detecting the junction temperature rise value of the chip to be tested in the preset time to obtain a target junction temperature rise value; and determining that the chip to be tested is qualified under the conditions that the target quiescent current value is less than or equal to the quiescent current threshold value, the target oscillation frequency value is less than or equal to the oscillation frequency threshold value and the target junction temperature rise value is less than or equal to the junction temperature rise threshold value.
Optionally, the predetermined temperature is between 110 ℃ and 120 ℃.
Optionally, the predetermined time is greater than or equal to 100 ms.
Optionally, the first predetermined range is 115 ℃ to 125 ℃.
Optionally, a minimum value of the second predetermined range is a first temperature rise value, a maximum value of the second predetermined range is a second temperature rise value, the first temperature rise value is 70% to 90% of the first temperature rise value, and the second temperature rise value is 110% to 130% of the first temperature rise value.
According to another aspect of an embodiment of the present invention, there is provided a screen device for a chip, the device including: the first testing unit is used for performing board level testing on a plurality of sample chips, the environmental temperature of the board level testing is a limit temperature, the sample chips meeting a first preset condition are determined as first target chips, quiescent current values and oscillation frequency values of the first target chips are obtained, quiescent current threshold values and oscillation frequency threshold values are determined, the limit temperature is the highest environmental temperature of an application scene of the sample chips, and the first preset condition is that the testing chips work normally and the junction temperature value is in a first preset range; the second testing unit is used for carrying out FT testing on the first target chip and determining the first target chip meeting a second preset condition as a second target chip, wherein the second preset condition is that the junction temperature rise value of the tested chip in a preset time is in a second preset range; a third testing unit, configured to perform a board level test on the second target chip, where an ambient temperature of the board level test is a limit temperature, determine the second target chip meeting the first predetermined condition and the second predetermined condition as a third target chip, obtain a junction temperature rise value of the third target chip in the FT test, and determine a junction temperature rise threshold; and the judging unit is used for screening the chip to be tested according to the quiescent current threshold value, the oscillation frequency threshold value and the junction temperature rising threshold value, and the chip to be tested and the sample chip are chips with the same model.
According to a further aspect of the embodiments of the present invention, there is also provided a slice screening apparatus, including a processor and a memory, where the processor is configured to execute a program, where the program executes any one of the above-mentioned slice screening methods.
In the embodiment of the invention, the chip screening method performs plate-level test on a plurality of sample chips at the limit temperature, selects the chips which can normally work at the limit temperature and have the junction temperature value within a first preset range, namely the chips which are first target chips, and obtains the quiescent current values and the oscillation frequency values of the first target chips to obtain the quiescent current threshold values and the oscillation frequency threshold values; performing FT test on the plurality of first target chips, selecting the chips with the junction temperature rise value within a second preset range within preset time, and determining the chips as second target chips; performing board-level test on the second target chip at the limit temperature, determining the second target chip which can normally work at the limit temperature, has the junction temperature value within a first preset range and has the junction temperature rise value within a second preset range within preset time as a third target chip, and acquiring the junction temperature rise value of the third target chip in the FT test to obtain a junction temperature rise threshold; the chips are screened according to three screening conditions of the quiescent current threshold, the oscillation frequency threshold and the junction temperature rise threshold, so that the phenomenon of high-temperature reversal of the chips meeting the power consumption limiting condition can be avoided, the power consumption limitation does not need to be reduced, namely the quiescent current threshold and the oscillation frequency threshold do not need to be reduced, the chip yield is improved, and the problem of low chip yield caused by low power consumption limitation of a screening method in the prior art is solved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 shows a flow diagram of a method of screening a chip according to an embodiment of the present application;
fig. 2 shows a schematic view of a screen device of a chip according to an embodiment of the present application.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
For convenience of description, some terms or expressions referred to in the embodiments of the present application are explained below:
the board level test is mainly applied to function test, a simulated chip working environment is built by using a PCB and a chip, interfaces of the chip are led out, the function of the chip is detected, or whether the chip can normally work is seen in various severe environments. The equipment to be applied is mainly an instrument and the EVB evaluation board is mainly manufactured.
And (3) CP testing: the test object is for each die in a wafer, and aims to ensure that each die in the wafer can basically meet the characteristics of a device or a design specification, which generally includes the verification of voltage, current, timing and function.
And (3) FT test: english is called Final Test, which is the last interception before the chip leaves factory. The test object is for a packaged chip, and the FT test is generally divided into two steps: 1) automatic test equipment; 2) and (5) testing the system level.
As mentioned in the background art, in the screening method in the prior art, a high temperature reversal phenomenon occurs within a power consumption limiting range, which results in a need of reducing power consumption limitation and thus results in low chip yield.
According to an embodiment of the present application, a method of screening a chip is provided.
FIG. 1 is a flow chart of a method of screening a chip according to an embodiment of the present application. As shown in fig. 1, the method comprises the steps of:
step S101, performing board level test on a plurality of sample chips, wherein the environmental temperature of the board level test is a limit temperature, determining the sample chips meeting a first preset condition as first target chips, acquiring quiescent current values and oscillation frequency values of the first target chips, and determining a quiescent current threshold value and an oscillation frequency threshold value, wherein the limit temperature is the highest environmental temperature of an application scene of the sample chips, and the first preset condition is that the test chips work normally and the junction temperature value is within a first preset range;
step S102, performing an FT test on the first target chip, and determining the first target chip meeting a second predetermined condition as a second target chip, wherein the second predetermined condition is that a junction temperature rise value of the test chip in a predetermined time is within a second predetermined range;
step S103, performing a board level test on the second target chip, where an ambient temperature of the board level test is a limit temperature, determining the second target chip meeting the first predetermined condition and the second predetermined condition as a third target chip, obtaining a junction temperature rise value of the third target chip in the FT test, and determining a junction temperature rise threshold;
and step S104, screening a chip to be tested according to the quiescent current threshold, the oscillation frequency threshold and the junction temperature rise threshold, wherein the chip to be tested and the sample chip are chips with the same model.
The screening method is used for carrying out plate-level test on a plurality of sample chips at the limiting temperature, selecting the chips which can normally work at the limiting temperature and have junction temperature values within a first preset range, namely first target chips, and obtaining static current values and oscillation frequency values of the plurality of first target chips to obtain static current threshold values and oscillation frequency threshold values; performing FT test on the plurality of first target chips, selecting the chips with the junction temperature rise value within a second preset range within preset time, and determining the chips as second target chips; performing board-level test on the second target chip at the limit temperature, determining the second target chip which can normally work at the limit temperature, has the junction temperature value within a first preset range and has the junction temperature rise value within a second preset range within preset time as a third target chip, and acquiring the junction temperature rise value of the third target chip in the FT test to obtain a junction temperature rise threshold; the chips are screened according to three screening conditions of the quiescent current threshold, the oscillation frequency threshold and the junction temperature rise threshold, so that the phenomenon of high-temperature reversal of the chips meeting the power consumption limiting condition can be avoided, the power consumption limitation does not need to be reduced, namely the quiescent current threshold and the oscillation frequency threshold do not need to be reduced, the chip yield is improved, and the problem of low chip yield caused by low power consumption limitation of a screening method in the prior art is solved.
Specifically, because the static current value and the oscillation frequency value are obtained in the CP test stage, after the first target chips are obtained in the board level test at the limit temperature, the static current value and the oscillation frequency value of the first target chips are directly read through the OTP, and the static current threshold value and the oscillation frequency threshold value can be determined according to the static current value and the oscillation frequency value of the first target chips. In a specific embodiment, when there are a plurality of the first target chips, the quiescent current threshold may be a quiescent current value of any one of the first target chips, or may be an average value or a maximum value of quiescent current values of the plurality of first target chips, the oscillation frequency threshold may be an oscillation frequency value of an oscillation circuit of any one of the first target chips, or may be an average value or a maximum value of oscillation frequency values of oscillation circuits of the plurality of first target chips, and when there are a plurality of the third target chips, the junction temperature rise threshold may be a junction temperature rise value of any one of the third target chips in the FT test, or may be an average value or a maximum value of junction temperature rise values of the plurality of third target chips in the FT test.
Preferably, the quiescent current threshold is a maximum value of quiescent current values of the plurality of first target chips, the oscillation frequency threshold is a maximum value of oscillation frequency values of oscillation circuits of the plurality of first target chips, and the junction temperature rise threshold is a maximum value of junction temperature rise values of the plurality of third target chips in the FT test. Specifically, the first target chip and the third target chip are multiple, the quiescent current threshold and the oscillation frequency threshold are the maximum values of quiescent current and oscillation frequency of the multiple first target chips, and the junction temperature rise threshold is the maximum value of junction temperature rise values of the multiple third target chips in the FT test, so that the chip yield is further improved.
It should also be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer-executable instructions and that, although a logical order is illustrated in the flowcharts, in some cases, the steps illustrated or described may be performed in an order different than presented herein.
In an embodiment of the application, before performing an FT test on the first target chip and determining the first target chip satisfying a second predetermined condition as a second target chip, the method further includes: performing board level test on a plurality of first target chips, wherein the environment temperature of the board level test is a limit temperature, and detecting a junction temperature rise value of the first target chip within the preset time under the condition that the junction temperature value of the first target chip is the preset temperature to obtain a first junction temperature rise value; and determining the second predetermined range according to the first temperature rise value.
Specifically, a junction temperature rise value of the first target chip within the predetermined time is detected to obtain a first junction temperature rise value, and a suitable second predetermined range is determined by taking the first junction temperature rise value as a standard.
In an embodiment of the present application, performing an FT test on the first target chip, and determining the first target chip satisfying a second predetermined condition as a second target chip includes: under the conditions that the test temperature is set temperature and the test excitation is set test excitation, detecting a junction temperature rise value of the first target chip in the preset time to obtain a second junction temperature rise value, wherein the test temperature is the ambient temperature for performing the FT test on the first target chip, and the test excitation is the excitation for performing the FT test on the first target chip; and adjusting the set temperature and the set test excitation until the second target chip is obtained.
Specifically, the cyclic calibration mode of the set test temperature and the set test stimulus is continuously adjusted, so that the second junction temperature rise value continuously approaches the second predetermined range until a chip, namely the second target chip, with the second junction temperature rise value in the second predetermined range is screened out, the test stimulus is test information input to the chip to be tested in the FT test, and different test information can enable the chip to operate in different working states.
In an embodiment of the present application, screening a chip to be tested according to the quiescent current threshold, the oscillation frequency threshold, and the junction temperature rise threshold includes: under the condition that the environmental temperature is the production temperature, obtaining the static current value of the chip to be tested and the oscillation frequency value of the oscillation circuit of the chip to be tested to obtain a target static current value and a target oscillation frequency value, wherein the production temperature is the temperature of the environment where the chip to be tested is in production operation; under the condition that the junction temperature value of the chip to be tested is the preset temperature, detecting the junction temperature rise value of the chip to be tested in the preset time to obtain a target junction temperature rise value; and determining that the chip to be tested is qualified under the conditions that the target quiescent current value is less than or equal to the quiescent current threshold value, the target oscillation frequency value is less than or equal to the oscillation frequency threshold value and the target junction temperature rise value is less than or equal to the junction temperature rise threshold value.
Specifically, the quiescent current of a chip to be tested and the oscillation frequency of an oscillation circuit of the chip to be tested are detected, and the junction temperature rise value in the preset time under the preset temperature is obtained, so as to obtain a target quiescent current, a target oscillation frequency and a target junction temperature rise value, screening is carried out according to three screening conditions of a quiescent current threshold value, an oscillation frequency threshold value and a junction temperature rise threshold value, namely, when the chip to be tested meets the conditions that the target quiescent current is less than or equal to the quiescent current threshold value, the target oscillation frequency is less than or equal to the oscillation frequency threshold value and the target junction temperature rise value is less than or equal to the junction temperature rise threshold value, the chip to be tested is qualified, so that the high-temperature reversal phenomenon of the chip meeting the power consumption limiting condition can be avoided, the power consumption limitation does not need to be reduced, namely, the quiescent current threshold value and the oscillation frequency threshold value do not need to be reduced, thereby improving the yield of chips.
In one embodiment of the present application, the predetermined temperature is between 110 ℃ and 120 ℃.
Specifically, the upper limit value of the junction temperature at which the chip can normally operate is 125 ℃, the predetermined temperature is set within the range, a certain junction temperature rise space is reserved, damage that the junction temperature of the chip exceeds the upper limit value in the process of detecting the junction temperature rise value is avoided, and the possibility of high-temperature reversal phenomenon after the junction temperature value of the chip reaches the predetermined temperature is avoided, and preferably, the predetermined temperature can be set to be 110 ℃. And setting a second preset range according to the junction temperature rise value of the chip reaching the preset temperature detection preset time, so as to screen out a second target chip according to the second preset range, thereby screening out the chip which is likely to have high-temperature reversal phenomenon through detecting the junction temperature rise threshold value obtained by the second target chip, and ensuring the quality of the chip.
In one embodiment of the present application, the predetermined time is greater than or equal to 100 ms.
Specifically, since the FT test is expensive, the predetermined time may be set to 100ms for cost saving, and of course, the longer the predetermined time, the smaller the error of the junction temperature rise value obtained, the smaller the error, the predetermined time may be greater than 100ms, so as to further improve the yield of the sieve sheet.
In one embodiment of the present application, the first predetermined range is 115 ℃ to 125 ℃.
Specifically, because the upper limit value of the junction temperature at which the chip can normally work is 125 ℃, the first predetermined range is set to be 115-125 ℃, and then the sample chip which normally works at the limit temperature and has the junction temperature value within the first predetermined range can be screened out to be used as a first target chip, so that the accuracy of measuring the junction temperature rise threshold value is improved, and the yield is further improved.
In one embodiment of the present application, a minimum value of the second predetermined range is a first temperature rise value, a maximum value of the second predetermined range is a second temperature rise value, the first temperature rise value is 70% to 90% of the first temperature rise value, and the second temperature rise value is 110% to 130% of the first temperature rise value.
Specifically, the first temperature rise value and the second temperature rise value may be selected according to actual conditions, and preferably, the first temperature rise value is set to be 80% of the first junction temperature rise value, and the second temperature rise value is set to be 120% of the first junction temperature rise value, because the upper limit of the junction temperature at which the chip can normally operate is 125 ℃, and the predetermined temperature is set to be between 110 ℃ and 120 ℃, which may cause inaccurate test, so the second predetermined range is set to be closer to the first junction temperature rise value, and yield of chip volume production is improved.
The embodiment of the present application further provides a chip screening device, and it should be noted that the chip screening device in the embodiment of the present application may be used to execute the chip screening method provided in the embodiment of the present application. The following describes a sieve piece device of a chip provided by the embodiment of the application.
Fig. 2 is a schematic view of a screen apparatus of a chip according to an embodiment of the present application. As shown in fig. 2, the apparatus includes:
a first testing unit 10, configured to perform board level testing on a plurality of sample chips, where an ambient temperature of the board level testing is a limit temperature, determine a sample chip that meets a first predetermined condition as a first target chip, obtain quiescent current values and oscillation frequency values of the plurality of first target chips, and determine a quiescent current threshold value and an oscillation frequency threshold value, where the limit temperature is a highest ambient temperature of an application scenario of the sample chip, and the first predetermined condition is that the testing chip normally operates and a junction temperature value is within a first predetermined range;
a second testing unit 20, configured to perform an FT test on the first target chip, and determine the first target chip meeting a second predetermined condition as a second target chip, where the second predetermined condition is that a junction temperature rise value of the test chip within a predetermined time is within a second predetermined range;
a third testing unit 30, configured to perform a board level test on the second target chip, where an ambient temperature of the board level test is a limit temperature, determine the second target chip that meets the first predetermined condition and the second predetermined condition as a third target chip, obtain a junction temperature rise value of the third target chip in the FT test, and determine a junction temperature rise threshold;
and the judging unit 40 is configured to sieve a chip to be tested according to the quiescent current threshold, the oscillation frequency threshold, and the junction temperature rise threshold, where the chip to be tested and the sample chip are chips of the same type.
The screening device carries out plate-level test on a plurality of sample chips at the limiting temperature, selects the chips which can normally work at the limiting temperature and have junction temperature values within a first preset range, namely the first target chips, and obtains quiescent current values and oscillation frequency values of the plurality of first target chips to obtain quiescent current threshold values and oscillation frequency threshold values; performing FT test on the plurality of first target chips, selecting the chips with the junction temperature rise value within a second preset range within preset time, and determining the chips as second target chips; performing board-level test on the second target chip at the limit temperature, determining the second target chip which can normally work at the limit temperature, has the junction temperature value within a first preset range and has the junction temperature rise value within a second preset range within preset time as a third target chip, and acquiring the junction temperature rise value of the third target chip in the FT test to obtain a junction temperature rise threshold; the chips are screened according to three screening conditions of the quiescent current threshold, the oscillation frequency threshold and the junction temperature rise threshold, so that the phenomenon of high-temperature reversal of the chips meeting the power consumption limiting condition can be avoided, the power consumption limitation does not need to be reduced, namely the quiescent current threshold and the oscillation frequency threshold do not need to be reduced, the chip yield is improved, and the problem of low chip yield caused by low power consumption limitation of a screening method in the prior art is solved.
In an embodiment of the present application, the apparatus further includes a fourth testing unit, and the fourth testing unit includes a first detecting module and a first determining module.
The first detection module is configured to perform a board level test on the plurality of first target chips, where an ambient temperature of the board level test is a limit temperature, and detect a junction temperature rise value of the first target chip within the predetermined time when a junction temperature value of the first target chip is the predetermined temperature, so as to obtain a first junction temperature rise value; the first determining module is used for determining the second preset range according to the first temperature rise value.
In an embodiment of the present application, the second testing unit further includes a second detecting module and an adjusting module.
The second detection module is configured to detect a junction temperature rise value of the first target chip at the predetermined time under the conditions that the test temperature is a set temperature and the test excitation is a set test excitation, to obtain a second junction temperature rise value, where the test temperature is an ambient temperature at which the FT test is performed on the first target chip, and the test excitation is an excitation at which the FT test is performed on the first target chip; the adjusting module is used for adjusting the set temperature and the set test excitation until the second target chip is obtained.
In an embodiment of the present application, the determining unit includes a third detecting module, a fourth detecting module, and a second determining module.
The third detection module is used for acquiring the static current value of the chip to be tested and the oscillation frequency value of the oscillation circuit of the chip to be tested under the condition that the environmental temperature is the production temperature, so as to obtain a target static current value and a target oscillation frequency value, wherein the production temperature is the temperature of the environment where the chip to be tested is located during production operation.
The fourth detection module is used for detecting the junction temperature rise value of the chip to be tested in the preset time under the condition that the junction temperature value of the chip to be tested is the preset temperature, so as to obtain the target junction temperature rise value.
The second determining module is used for determining that the chip to be tested is qualified under the condition that the target quiescent current value is smaller than or equal to the quiescent current threshold value, the target oscillation frequency value is smaller than or equal to the oscillation frequency threshold value and the target junction temperature rise value is smaller than or equal to the junction temperature rise threshold value.
In one embodiment of the present application, the predetermined temperature is between 110 ℃ and 120 ℃.
In one embodiment of the present application, the predetermined time is greater than or equal to 100 ms.
In one embodiment of the present application, a minimum value of the second predetermined range is a first temperature rise value, a maximum value of the second predetermined range is a second temperature rise value, the first temperature rise value is 70% to 90% of the first temperature rise value, and the second temperature rise value is 110% to 130% of the first temperature rise value.
In one embodiment of the present application, the first predetermined range is 115 ℃ to 125 ℃.
The screening device of the chip comprises a processor and a memory, wherein the first testing unit 10, the second testing unit 20, the third testing unit 30, the judging unit 40 and the like are stored in the memory as program units, and the processor executes the program units stored in the memory to realize corresponding functions.
The processor comprises a kernel, and the kernel calls the corresponding program unit from the memory. The kernel can be set to be one or more than one, and the problem of low chip yield caused by low power consumption limitation of a screening method in the prior art is solved by adjusting kernel parameters.
The memory may include volatile memory in a computer readable medium, Random Access Memory (RAM) and/or nonvolatile memory such as Read Only Memory (ROM) or flash memory (flash RAM), and the memory includes at least one memory chip.
The embodiment of the invention provides screening equipment, which comprises a processor, a memory and a program which is stored on the memory and can run on the processor, wherein when the processor executes the program, any one of the screening methods is realized:
the screening device in this context may be an electronic device such as a server, a PC, a PAD, a mobile phone, etc.
In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In order to make the technical solutions and technical effects of the present application more clear to those skilled in the art, the following description will be given with reference to specific embodiments.
Example 1
The chip to be tested is required to work normally at the temperature below 50 ℃, namely the limiting temperature is 50 ℃, and the screening method of the chip of the embodiment comprises the following steps:
step 1: performing board-level test on the plurality of sample chips at an ambient temperature of 50 ℃, recording the sample chips which can normally work at the temperature of 50 ℃ and have junction temperature values within a first preset range as first target chips, acquiring static current values and oscillation frequency values of the plurality of first target chips, taking the maximum value of the plurality of static current values as a static current threshold value, and taking the maximum value of the plurality of oscillation frequency values as an oscillation frequency threshold value;
step 2: monitoring a temperature sensor in the chip by a CPU (Central processing Unit), and testing a junction temperature rise value of a first target chip at a preset temperature of 110 ℃ within 100ms of a preset time to obtain a first junction temperature rise value;
and step 3: performing FT test on the first target chip, and detecting a junction temperature rise value of the first target chip within 100ms of preset time in the FT test through a temperature sensor inside the chip to obtain a second junction temperature rise value;
and 4, step 4: changing the set temperature and the set test excitation of the FT test to make the temperature rise value at the second junction temperature approach the temperature rise value at the first junction temperature;
and 5: repeating the step 4 until the first target chip with the second junction temperature rise value between 80% and 120% of the first junction temperature rise value is screened out, and obtaining a second target chip;
step 6: performing board-level test on the plurality of second target chips at an ambient temperature of 50 ℃, detecting a junction temperature value and a third junction temperature rise value within 100ms of a preset time, recording the second target chips which can normally work at the temperature of 50 ℃, have the junction temperature value within a first preset range and have the third junction temperature rise value between 80% and 120% of the first junction temperature rise value as third target chips, obtaining second junction temperature rise values of the plurality of third target chips, and taking the maximum value as a junction temperature rise threshold value;
and 7: and finally, screening the chip to be tested by taking the quiescent current threshold, the oscillation frequency threshold and the junction temperature rise threshold as the upper limit of the screening condition.
In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit may be stored in a computer-readable storage medium if it is implemented in the form of a software functional unit and sold or used as a separate product. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a computer-readable storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned computer-readable storage media comprise: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
the screening method, the screening device and the screening equipment carry out plate-level test on a plurality of sample chips, select a first target chip which can normally work at the maximum ambient temperature of an application scene and has a junction temperature value within a first preset range from the sample chips through limit temperature test, detect quiescent current and corresponding oscillation frequency of the first target chip at the limit temperature to obtain a quiescent current threshold value and an oscillation frequency threshold value, then carry out FT test on the first target chip, select a first target chip with the junction temperature rise value within a second preset range in the process of the FT test to obtain a second target chip, and detect the junction temperature rise value of the second target chip within the preset time under the condition that the junction temperature value of the second target chip is the preset temperature in the process of carrying out plate-level test on the second target chip, the junction temperature rise threshold can be obtained, and the chip can be screened according to three screening conditions of the quiescent current threshold, the oscillation frequency threshold and the junction temperature rise threshold, so that the high-temperature reversal phenomenon of the chip meeting the power consumption limiting condition can be avoided, the power consumption limitation does not need to be reduced, namely the quiescent current threshold and the oscillation frequency threshold do not need to be reduced, the yield of the chip is improved, and the problem that the yield of the chip is low due to the fact that the high-temperature reversal phenomenon occurs in the power consumption limiting range in the screening method in the prior art and the power consumption limitation needs to be reduced is solved.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A method of screening a chip, the method comprising:
performing board-level test on a plurality of sample chips, wherein the environmental temperature of the board-level test is a limit temperature, determining the sample chip meeting a first preset condition as a first target chip, acquiring static current values and oscillation frequency values of the plurality of first target chips, and determining a static current threshold value and an oscillation frequency threshold value, wherein the limit temperature is the highest environmental temperature of an application scene of the sample chip, and the first preset condition is that the test chip normally works and a junction temperature value is within a first preset range;
performing an FT test on the first target chip, and determining the first target chip meeting a second preset condition as a second target chip, wherein the second preset condition is that a junction temperature rise value of the test chip in a preset time is in a second preset range;
performing board level test on the second target chip, wherein the environmental temperature of the board level test is the limit temperature, determining the second target chip meeting the first preset condition and the second preset condition as a third target chip, acquiring a junction temperature rise value of the third target chip in the FT test, and determining a junction temperature rise threshold;
screening a chip to be tested according to the quiescent current threshold, the oscillation frequency threshold and the junction temperature rise threshold, wherein the chip to be tested and the sample chip are chips with the same model.
2. The method of claim 1, wherein before performing an FT test on the first target chip to determine the first target chip satisfying a second predetermined condition as a second target chip, the method further comprises:
performing board-level test on the plurality of first target chips, wherein the environment temperature of the board-level test is a limit temperature, and detecting a junction temperature rise value of the first target chip within the preset time under the condition that the junction temperature value of the first target chip is a preset temperature to obtain a first junction temperature rise value;
and determining the second preset range according to the first temperature rise value.
3. The method of claim 1, wherein performing an FT test on the first target chip, and determining the first target chip satisfying a second predetermined condition as a second target chip, comprises:
under the conditions that the test temperature is set temperature and the test excitation is set test excitation, detecting a junction temperature rise value of the first target chip in the preset time to obtain a second junction temperature rise value, wherein the test temperature is the ambient temperature for performing the FT test on the first target chip, and the test excitation is the excitation for performing the FT test on the first target chip;
and adjusting the set temperature and the set test excitation until the second target chip is obtained.
4. The method of claim 1, wherein screening the chips to be tested according to the quiescent current threshold, the oscillation frequency threshold, and the junction temperature rise threshold comprises:
under the condition that the environmental temperature is the production temperature, obtaining a static current value of the chip to be tested and an oscillation frequency value of an oscillation circuit of the chip to be tested to obtain a target static current value and a target oscillation frequency value, wherein the production temperature is the temperature of the environment where the chip to be tested is in production operation;
under the condition that the junction temperature value of the chip to be tested is a preset temperature, detecting the junction temperature rise value of the chip to be tested in the preset time to obtain a target junction temperature rise value;
and determining that the chip to be tested is qualified under the conditions that the target quiescent current value is less than or equal to the quiescent current threshold value, the target oscillation frequency value is less than or equal to the oscillation frequency threshold value and the target junction temperature rise value is less than or equal to the junction temperature rise threshold value.
5. The method according to claim 2, wherein the predetermined temperature is between 110 ℃ and 120 ℃.
6. The method of claim 1, wherein the predetermined time is greater than or equal to 100 ms.
7. The method of claim 1, wherein the first predetermined range is 115 ℃ to 125 ℃.
8. The method according to claim 2, wherein the minimum value of the second predetermined range is a first temperature rise value, the maximum value of the second predetermined range is a second temperature rise value, the first temperature rise value is 70-90% of the first temperature rise value, and the second temperature rise value is 110-130% of the first temperature rise value.
9. A screen apparatus for a chip, the apparatus comprising:
the first testing unit is used for performing board level testing on a plurality of sample chips, the environmental temperature of the board level testing is a limit temperature, the sample chips meeting a first preset condition are determined as first target chips, quiescent current values and oscillation frequency values of the first target chips are obtained, quiescent current threshold values and oscillation frequency threshold values are determined, the limit temperature is the highest environmental temperature of an application scene of the sample chips, and the first preset condition is that the testing chips work normally and the junction temperature value is in a first preset range;
the second testing unit is used for carrying out FT testing on the first target chip and determining the first target chip meeting a second preset condition as a second target chip, wherein the second preset condition is that the junction temperature rise value of the tested chip in a preset time is in a second preset range;
a third testing unit, configured to perform a board level test on the second target chip, where an ambient temperature of the board level test is a limit temperature, determine the second target chip meeting the first predetermined condition and the second predetermined condition as a third target chip, obtain a junction temperature rise value of the third target chip in the FT test, and determine a junction temperature rise threshold;
and the judging unit is used for screening the chip to be tested according to the quiescent current threshold value, the oscillation frequency threshold value and the junction temperature rising threshold value, and the chip to be tested and the sample chip are chips with the same model.
10. A slice apparatus comprising a processor and a memory, wherein the processor is configured to run a program, wherein the program when run performs the method of any one of claims 1 to 8.
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| CN116581043A (en) * | 2023-04-20 | 2023-08-11 | 深圳市晶存科技有限公司 | Chip classification method, device, electronic equipment and computer readable storage medium |
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