WO2023243470A1 - ウエハ構造および半導体装置の製造方法 - Google Patents

ウエハ構造および半導体装置の製造方法 Download PDF

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Publication number
WO2023243470A1
WO2023243470A1 PCT/JP2023/020891 JP2023020891W WO2023243470A1 WO 2023243470 A1 WO2023243470 A1 WO 2023243470A1 JP 2023020891 W JP2023020891 W JP 2023020891W WO 2023243470 A1 WO2023243470 A1 WO 2023243470A1
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Prior art keywords
electrode
wafer
film
plating
main surface
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PCT/JP2023/020891
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English (en)
French (fr)
Japanese (ja)
Inventor
貴晶 山中
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2024528731A priority Critical patent/JPWO2023243470A1/ja
Priority to DE112023002292.5T priority patent/DE112023002292T5/de
Priority to CN202380046937.XA priority patent/CN119384876A/zh
Publication of WO2023243470A1 publication Critical patent/WO2023243470A1/ja
Priority to US18/979,949 priority patent/US20250112080A1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/035—Etching a recess in the emitter region 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/232—Emitter electrodes for IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H10D64/2527—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body

Definitions

  • Patent Document 1 discloses a step of forming a first electrode on a first main surface of a semiconductor wafer, a step of forming a second electrode covering the entire second main surface of the semiconductor wafer, and a step of forming a second electrode covering the entire second main surface of the semiconductor wafer.
  • a method for manufacturing a semiconductor device is disclosed, which includes a step of forming a plating layer on a first electrode in a state where the first electrode is in a state where the plating layer is formed on the first electrode.
  • One embodiment provides a wafer structure and a method for manufacturing a semiconductor device that contribute to manufacturing a highly reliable semiconductor device.
  • One embodiment includes a wafer having a first surface on one side and a second surface on the other side, a first electrode that covers the first surface, and a second electrode that covers the second surface so as to expose a peripheral portion of the second surface. a second electrode covering an inner part of the surface; and a second electrode having a property that the adhesion force to the peripheral edge part of the second surface is higher than the adhesive force to the second electrode; a protective tape attached to a second electrode.
  • One embodiment includes providing a wafer structure including a wafer having a first surface on one side and a second surface on the other side, a first electrode covering the first surface, and a peripheral edge of the second surface. forming a second electrode covering an inner part of the second surface so as to expose an inner part of the second surface;
  • a method of manufacturing a semiconductor device comprising: adhering a protective tape having a protective tape to the peripheral portion of the second surface and the second electrode.
  • FIG. 1 is a plan view of the wafer structure according to the first embodiment, viewed from the first main surface side.
  • FIG. 2 is a sectional view taken along the line II-II shown in FIG.
  • FIG. 3 is a schematic cross-sectional view of the wafer structure shown in FIG.
  • FIG. 4 is a plan view of the wafer structure shown in FIG. 1 viewed from the second principal surface side.
  • FIG. 5 is a plan view showing an example of the layout of the second electrode shown in FIG. 3.
  • FIG. FIG. 6 is an enlarged sectional view showing the peripheral portion of the wafer structure shown in FIG. 1 together with the second electrode according to the first embodiment.
  • FIG. 7A is an enlarged sectional view showing a peripheral portion of the wafer structure shown in FIG.
  • FIG. 8A is a cross-sectional view showing a method for manufacturing a semiconductor device according to the wafer structure shown in FIG. 1.
  • FIG. 8B is a cross-sectional view showing a step after FIG. 8A.
  • FIG. 8C is a cross-sectional view showing a step after FIG. 8B.
  • FIG. 8D is a cross-sectional view showing a step after FIG. 8C.
  • FIG. 8E is a cross-sectional view showing a step after FIG. 8D.
  • FIG. 8F is a cross-sectional view showing a step after FIG. 8E.
  • FIG. 8G is a cross-sectional view showing a step after FIG. 8F.
  • FIG. 9A is a cross-sectional view showing the process of forming the second electrode.
  • FIG. 9B is a cross-sectional view showing a step after FIG. 9A.
  • FIG. 9C is a cross-sectional view showing a step after FIG. 9B.
  • FIG. 10 is a plan view of the wafer structure according to the second embodiment, viewed from the first main surface side.
  • FIG. 11 is a sectional view taken along the line XI-XI shown in FIG. 10.
  • FIG. 12 is an enlarged sectional view showing a main part of the functional device shown in FIG. 11.
  • FIG. 11 is a sectional view taken along the line XI-XI shown in FIG. 10.
  • FIG. 14A is a cross-sectional view showing a method for manufacturing a semiconductor device having the wafer structure shown in FIG.
  • FIG. 14B is a cross-sectional view showing a step after FIG. 14A.
  • FIG. 14C is a cross-sectional view showing a step after FIG. 14B.
  • FIG. 14D is a cross-sectional view showing a step after FIG. 14C.
  • FIG. 14E is a cross-sectional view showing a step after FIG. 14D.
  • FIG. 14F is a cross-sectional view showing a step after FIG. 14E.
  • FIG. 14G is a cross-sectional view showing a step after FIG. 14F.
  • FIG. 14A is a cross-sectional view showing a method for manufacturing a semiconductor device having the wafer structure shown in FIG.
  • FIG. 14B is a cross-sectional view showing a step after FIG. 14A.
  • FIG. 14C is a cross-sectional view showing a step after FIG. 14
  • FIG. 15 is a plan view showing a wafer according to a modified example.
  • FIG. 16 is a schematic cross-sectional view showing the process of forming the second electrode according to the first modification.
  • FIG. 17 is a schematic cross-sectional view showing the process of forming the second electrode according to the second modification.
  • FIG. 18 is a schematic cross-sectional view showing the process of forming the second electrode according to the third modification.
  • FIG. 1 is a plan view of a wafer structure 1A according to the first embodiment, viewed from the first principal surface 3 side.
  • FIG. 2 is a sectional view taken along the line II-II shown in FIG.
  • FIG. 3 is a schematic cross-sectional view of the wafer structure 1A shown in FIG.
  • FIG. 4 is a plan view of the wafer structure 1A shown in FIG. 1 viewed from the second main surface 4 side.
  • FIG. 5 is a plan view showing an example of the layout of the second electrode 24 shown in FIG.
  • FIG. 6 is an enlarged sectional view showing the peripheral portion of the wafer structure 1A shown in FIG. 1 together with the second electrode 24 according to the first embodiment.
  • FIG. 7A is an enlarged cross-sectional view showing the peripheral portion of the wafer structure 1A shown in FIG. 1 together with the second electrode 24 according to the second embodiment.
  • FIG. 7B is an enlarged cross-sectional view showing the peripheral portion of the wafer structure 1A shown in FIG. 1 together with the second electrode 24 according to the third embodiment.
  • a wafer structure 1A includes a wafer 2.
  • the wafer 2 is formed into a flat disk shape.
  • the wafer 2 may be formed into a flat rectangular parallelepiped shape.
  • the wafer 2 is made of a semiconductor single crystal having a plating reaction rate slower than that of a Si (silicon) single crystal.
  • the wafer 2 is made of a semiconductor single crystal whose redox reaction rate is slower than that of a Si single crystal. It is particularly preferable that the wafer 2 is made of a semiconductor single crystal having a Ni plating reaction rate slower than that of a Si single crystal.
  • the wafer 2 is most preferably made of a high-hardness semiconductor single crystal that has a hardness higher than that of a Si single crystal.
  • the wafer 2 is a wide bandgap semiconductor wafer containing a wide bandgap semiconductor single crystal. That is, the wafer structure 1A is preferably a wide bandgap semiconductor wafer structure.
  • a wide bandgap semiconductor is a semiconductor that has a higher bandgap than Si.
  • the wafer 2 is an SiC wafer containing a hexagonal SiC (silicon carbide) single crystal, which is an example of a wide bandgap semiconductor. That is, the wafer structure 1A is a SiC wafer structure.
  • the hexagonal SiC single crystal has multiple types of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like.
  • the wafer 2 includes a 4H-SiC single crystal, but the wafer 2 may include a SiC single crystal of other polytypes.
  • the wafer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and a side surface 5 connecting the first main surface 3 and the second main surface 4.
  • a first direction X one direction along the first main surface 3
  • a direction perpendicular to the first direction X along the first main surface 3 will be referred to as a second direction Y
  • the direction perpendicular to is called the vertical direction Z.
  • the first direction X may be the m-axis direction of the SiC single crystal
  • the second direction Y may be the a-axis direction of the SiC single crystal.
  • the first direction X may be the a-axis direction of the SiC single crystal
  • the second direction Y may be the m-axis direction of the SiC single crystal.
  • the first main surface 3 and the second main surface 4 face the c-plane of the SiC single crystal. It is preferable that the first principal surface 3 faces the silicon surface of the SiC single crystal, and the second principal surface 4 faces the carbon surface of the SiC single crystal.
  • the first main surface 3 is a device forming surface, and the second main surface 4 is a non-device forming surface.
  • the second main surface 4 is a flat surface extending horizontally from the inner part to the peripheral edge, and has no step at the peripheral edge.
  • the second main surface 4 is a ground surface having a plurality of grinding marks recessed toward the first main surface 3.
  • the depth of the grinding marks is preferably 0.5 ⁇ m or less. It is particularly preferable that the depth of the grinding marks is 0.1 ⁇ m or less.
  • the first main surface 3 and the second main surface 4 may have an off angle that is inclined at a predetermined angle in a predetermined off direction with respect to the c-plane. That is, the c-axis of the SiC single crystal may be inclined with respect to the vertical direction Z by an off-angle.
  • the off direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal.
  • the off angle may be greater than 0° and less than or equal to 10°.
  • the off angle is preferably 5° or less. It is particularly preferable that the off-angle is 2° or more and 4.5° or less.
  • the wafer 2 has a mark 6 on the side surface 5 that indicates the crystal orientation of the SiC single crystal.
  • the mark 6 includes an orientation flat cut out in a straight line in a plan view viewed from the vertical direction Z (hereinafter simply referred to as "plan view").
  • the orientation flat extends in the second direction Y in this form.
  • the orientation flat does not necessarily need to extend in the second direction Y, and may extend in the first direction X.
  • the landmark 6 may include a first orientation flat extending in the first direction X and a first orientation flat extending in the second direction Y.
  • the wafer 2 may have a diameter of 50 mm or more and 300 mm or less (that is, 2 inches or more and 12 inches or less) in plan view.
  • the diameter of the wafer 2 is defined by the length of the chord passing through the center of the wafer 2 outside the landmark 6.
  • the wafer 2 is preferably a thin wafer having a thickness of 30 ⁇ m or more and less than 200 ⁇ m.
  • the wafer 2 may be 30 ⁇ m to 50 ⁇ m, 50 ⁇ m to 75 ⁇ m, 75 ⁇ m to 100 ⁇ m, 100 ⁇ m to 125 ⁇ m, 125 ⁇ m to 150 ⁇ m, 150 ⁇ m to 175 ⁇ m, or 175 ⁇ m to 200 ⁇ m.
  • the thickness of the wafer 2 is preferably 160 ⁇ m or less.
  • the wafer structure 1A includes an n-type first region 7 (first semiconductor region) formed in a region (surface layer portion) on the first main surface 3 side in the wafer 2.
  • the first region 7 is formed in a layer shape extending along the first main surface 3 and is exposed from the first main surface 3 and the side surface 5.
  • the first region 7 is made of an epitaxial layer (SiC epitaxial layer).
  • the first region 7 may have a thickness of 1 ⁇ m or more and 50 ⁇ m or less.
  • the thickness of the first region 7 is preferably 5 ⁇ m or more and 30 ⁇ m or less. It is particularly preferable that the thickness of the first region 7 is 25 ⁇ m or less.
  • the wafer structure 1A includes an n-type second region 8 (second semiconductor region) formed in a region (surface layer portion) on the second main surface 4 side in the wafer 2.
  • the second region 8 has a higher n-type impurity concentration than the first region 7 and is electrically connected to the first region 7 within the wafer 2 .
  • the second region 8 is formed in a layer shape extending along the second main surface 4 and is exposed from the second main surface 4 and the side surface 5.
  • the second region 8 is made of a semiconductor substrate (SiC substrate). That is, the wafer 2 has a laminated structure including a substrate and an epitaxial layer.
  • the second region 8 may have a thickness of 1 ⁇ m or more and less than 200 ⁇ m.
  • the thickness of the second region 8 is preferably less than 160 ⁇ m.
  • the thickness of the second region 8 is preferably 10 ⁇ m or more.
  • the thickness of the second region 8 may exceed the thickness of the first region 7.
  • the thickness of the second region 8 may be less than the thickness of the first region 7.
  • the wafer structure 1A includes a plurality of device regions 10 provided on the first main surface 3.
  • Each device region 10 is a region corresponding to a semiconductor device (wide bandgap semiconductor device/SiC semiconductor device).
  • the plurality of device regions 10 are each set to have a rectangular shape in plan view.
  • the plurality of device regions 10 are arranged in a matrix along the first direction X and the second direction Y in plan view.
  • the plurality of device regions 10 are arranged at intervals inwardly from the periphery of the first main surface 3 in a plan view, and a space 11 in which the plurality of device regions 10 do not exist is provided at the periphery of the first main surface 3. It is divided. That is, the wafer 2 has an inner portion having a plurality of device regions 10 and a peripheral portion having no device regions 10.
  • the space 11 is formed in an annular shape surrounding the plurality of device regions 10 in a plan view.
  • the space 11 has a portion extending in an arc shape in a region outside the mark 6 in a plan view, and a portion extending linearly in a region along the mark 6.
  • the length of one side of each device region 10 may be 0.5 mm or more and 20 mm or less.
  • the length of one side of each device region 10 is preferably 1 mm or more. It is particularly preferable that the length of one side of each device region 10 is 2 mm or more. In this embodiment, the length of one side of each device region 10 is set in a range of 4 mm or more and 6 mm or less.
  • the wafer structure 1A includes a plurality of scheduled cutting lines 12 provided on the first main surface 3.
  • the plurality of scheduled cutting lines 12 are set in a lattice shape extending along the first direction X and the second direction Y so as to partition the plurality of device regions 10.
  • the wafer structure 1A further includes functional devices 13 formed in each device region 10 on the first main surface 3. Each functional device 13 is formed spaced inward from the periphery of each device region 10 . Each functional device 13 may include at least one of a switching device, a rectifying device, and a passive device.
  • the switching device may include at least one of MISFET (Metal Insulator Semiconductor Field Effect Transistor), BJT (Bipolar Junction Transistor), IGBT (Insulated Gate Bipolar Junction Transistor), and JFET (Junction Field Effect Transistor).
  • the rectifier device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, an SBD (Schottky Barrier Diode), and an FRD (Fast Recovery Diode).
  • the passive device may include at least one of a resistor, a capacitor, and a coil.
  • Each functional device 13 may include a circuit network (for example, an integrated circuit such as an LSI) in which at least two of a switching device, a rectifying device, and a passive device are combined.
  • Each functional device 13 includes an SBD in this form. Since the configurations of the plurality of device areas 10 (functional devices 13) are similar, the configuration of one device area 10 (functional device 13) will be explained below.
  • wafer structure 1A includes an n-type diode region 14 formed in the surface layer of first main surface 3 in device region 10.
  • the diode region 14 is formed using the first region 7.
  • Diode region 14 is formed spaced inward from the periphery of device region 10 .
  • the diode region 14 is formed into a polygonal shape (quadrangular in this embodiment) in plan view.
  • the wafer structure 1A includes a p-type (second conductivity type) guard region 15 formed in the surface layer portion of the first main surface 3 in the device region 10.
  • the guard region 15 is formed in the surface layer of the first region 7 at a distance inward from the periphery of the device region 10 .
  • Guard region 15 is formed in a polygonal ring shape (quadrangular ring shape in this embodiment) surrounding diode region 14 in plan view.
  • Guard region 15 has an inner edge on the inner side of device region 10 and an outer edge on the peripheral side of device region 10 .
  • the wafer structure 1A includes a main surface insulating film 16 that selectively covers the first main surface 3 in the device region 10.
  • Main surface insulating film 16 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the main surface insulating film 16 has a single layer structure including a silicon oxide film.
  • Main surface insulating film 16 has a contact opening 17 that exposes the inner edges of diode region 14 and guard region 15 .
  • the main surface insulating film 16 covers the inner part of the device region 10 at an inward distance from the periphery of the device region 10 and covers the first main surface 3 (first region 7 ) from the periphery of the device region 10 . It's exposed. That is, the main surface insulating film 16 exposes the boundaries (the plurality of planned cutting lines 12) between the plurality of device regions 10. Of course, the main surface insulating film 16 may cover the boundaries between the plurality of device regions 10 (the plurality of planned cutting lines 12).
  • the wafer structure 1A includes a first electrode 18 that covers the first main surface 3 in the device region 10.
  • the first electrode 18 is formed as an anode electrode.
  • the first electrode 18 is spaced inward from the periphery of the device region 10 .
  • the first electrode 18 is formed in a polygonal shape (quadrangular in this form) along the periphery of the device region 10 in plan view.
  • the first electrode 18 enters the contact opening 17 from above the main surface insulating film 16 and is electrically connected to the inner edges of the diode region 14 and the guard region 15 .
  • the first electrode 18 forms a Schottky junction with the diode region 14 .
  • the first electrode 18 may have a stacked structure including a Ti-based metal film and an Al-based metal film stacked in this order from the first main surface 3 side.
  • the Ti-based metal film may include at least one of a Ti film and a Ti alloy film.
  • the Al-based metal film is preferably thicker than the Ti-based metal film.
  • the Al-based metal film includes at least one of an Al film and an Al alloy film.
  • the Al-based metal film may include at least one of an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.
  • the wafer structure 1A includes an insulating film 19 that covers the first electrode 18 in the device region 10.
  • the insulating film 19 covers the periphery of the first electrode 18 at a distance inward from the periphery of the device region 10 .
  • the insulating film 19 defines a pad opening 20 in the inner part of the device region 10 and a street opening 21 in the peripheral part of the device region 10 .
  • the pad opening 20 exposes the inner part of the first electrode 18.
  • the pad opening 20 is formed in a polygonal shape (quadrangular in this form) along the periphery of the first electrode 18 in plan view.
  • the street opening 21 extends along the periphery of the device region 10 and exposes the first main surface 3. Specifically, the street openings 21 are divided into a lattice shape extending in the first direction X and the second direction Y by a plurality of insulating films 19 adjacent to each other in the first direction The boundary portion (a plurality of scheduled cutting lines 12) is exposed. Of course, when the main surface insulating film 16 covering the first main surface 3 is formed at the boundary between the plurality of device regions 10, the street opening 21 covers the main surface insulating film 16 at the border between the plurality of device regions 10. It may be left exposed.
  • the insulating film 19 is thicker than the first electrode 18.
  • the thickness of the insulating film 19 is preferably less than the thickness of the wafer 2.
  • the thickness of the insulating film 19 may be 3 ⁇ m or more and 35 ⁇ m or less.
  • the thickness of the insulating film 19 is preferably 25 ⁇ m or less.
  • the insulating film 19 has a stacked structure including an inorganic insulating film 22 (inorganic film) and an organic insulating film 23 (organic film) stacked in this order from the first electrode 18 side.
  • the inorganic insulating film 22 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the inorganic insulating film 22 includes an insulating material different from that of the main surface insulating film 16.
  • the inorganic insulating film 22 has a single layer structure including a silicon nitride film.
  • the thickness of the inorganic insulating film 22 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the organic insulating film 23 is thicker than the inorganic insulating film 22 and covers the inorganic insulating film 22.
  • the organic insulating film 23 is preferably made of a photosensitive resin film.
  • the organic insulating film 23 may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.
  • the thickness of the organic insulating film 23 may be 3 ⁇ m or more and 30 ⁇ m or less.
  • the thickness of the organic insulating film 23 is preferably 20 ⁇ m or less.
  • the organic insulating film 23 may expose either or both of the inner edge and outer edge of the inorganic insulating film 22. In this form, the organic insulating film 23 exposes both the inner and outer edges of the inorganic insulating film 22 and partitions the inorganic insulating film 22 into the pad opening 20 and the street opening 21 . Of course, the organic insulating film 23 may cover the entire area of the inorganic insulating film 22.
  • the wafer structure 1A includes a second electrode 24 that covers the second main surface 4.
  • the second electrode 24 is formed as a cathode electrode and is electrically connected to the second region 8 exposed from the second main surface 4 .
  • the second electrode 24 has a plating reaction rate faster than that of the wafer 2 .
  • the second electrode 24 includes an electrode material whose redox reaction rate is faster than that of the wafer 2 .
  • the second electrode 24 exposes at least a portion of the peripheral edge of the wafer 2 as a plating reaction inhibiting portion 25.
  • the plating reaction inhibiting portion 25 is an exposed portion of the second main surface 4 that is exposed from the second electrode 24 .
  • the second electrode 24 exposes the entire circumference of the wafer 2 as a plating reaction inhibiting portion 25 .
  • the plating reaction inhibiting portion 25 exposes the SiC single crystal (in this form, the carbon surface of the SiC single crystal) exposed from the peripheral edge of the second main surface 4. Further, the plating reaction inhibiting portion 25 exposes grinding marks formed on the peripheral edge of the second main surface 4. The portion of the second main surface 4 that forms the plating reaction inhibiting portion 25 is formed flush with the portion of the second main surface 4 that is hidden by the second electrode 24 . In other words, the plating reaction inhibiting portion 25 extends in the horizontal direction and does not form a stepped portion recessed toward the first main surface 3 on the second main surface 4 .
  • the plating reaction inhibiting portion 25 has a portion extending in an arc shape in a region outside the mark 6 in plan view, and a portion extending linearly in a region along the mark 6.
  • the plating reaction inhibiting portion 25 is formed in a region outside the plurality of device regions 10 in a plan view, and faces the space 11 in the thickness direction of the wafer 2. That is, the plating reaction inhibiting portion 25 is formed in an annular shape that collectively surrounds the plurality of device regions 10 in a plan view.
  • the exposed width W of the plating reaction inhibiting portion 25 is preferably larger than the thickness of the second electrode 24. It is preferable that the exposed width W is larger than the thickness of the first electrode 18.
  • the exposed width W is preferably larger than the thickness of the insulating film 19. It is particularly preferable that the exposure width W is larger than the thickness of the wafer 2.
  • the exposure width W may be 0.5 mm or more and 5 mm or less.
  • the exposure width W is preferably 1 mm or more and 2 mm or less. It is particularly preferable that the exposed width W is less than the length of one side of the device region 10. According to this configuration, it is possible to suppress a decrease in the number of the plurality of device regions 10 (that is, the number of semiconductor devices) due to the introduction of the plating reaction inhibiting portion 25.
  • the second electrode 24 may include at least one of an Al-based metal film, a Ti-based metal film, a Ni-based metal film, a Pd-based metal film, an Au-based metal film, and an Ag-based metal film.
  • the Al-based metal film may include at least one of an Al film and an Al alloy film.
  • the Al-based metal film may include at least one of an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.
  • the Ti-based metal film may include at least one of a Ti film and a Ti alloy film.
  • the Ni-based metal film may include at least one of a Ni film and a Ni alloy film.
  • the Pd-based metal film may include at least one of a Pd film and a Pd alloy film.
  • the Au-based metal film may include at least one of an Au film and an Au alloy film.
  • the Ag-based metal film may include at least one of an Ag film and an Ag alloy film.
  • the second electrode 24 has a stacked structure including a Ti film 31, a Ni film 32, and an Au film 33 stacked in this order from the second main surface 4 side.
  • the Ti film 31 directly covers the second main surface 4.
  • the Ti film 31 does not have a silicide (TiSi) layer formed on the surface layer of the second main surface 4.
  • the Ti film 31 may form a silicide layer in the surface layer portion of the second main surface 4.
  • the Ti film 31 may have a thickness of 500 ⁇ or more and 1000 ⁇ or less.
  • the Ni film 32 is thicker than the Ti film 31 and covers the Ti film 31.
  • the thickness of the Ni film 32 may be 5000 ⁇ or more and 20000 ⁇ or more.
  • the Au film 33 is thinner than the Ni film 32 and covers the Ni film 32.
  • the thickness of the Au film 33 may be greater than or equal to 500 ⁇ and less than or equal to 1000 ⁇ .
  • the second electrode 24 has a stacked structure including an AlSi alloy film 34, a Ti film 35, a Ni film 36, and an Au film 37 stacked in this order from the second main surface 4 side.
  • the AlSi alloy film 34 directly covers the second main surface 4.
  • the AlSi alloy film 34 does not form a silicide (AlSi) layer in the surface layer portion of the second main surface 4.
  • the AlSi alloy film 34 may form a silicide layer in the surface layer portion of the second main surface 4.
  • the AlSi alloy film 34 may have a thickness of 500 ⁇ or more and 2000 ⁇ or less.
  • the Ti film 35 is thinner than the AlSi alloy film 34 and covers the AlSi alloy film 34.
  • the thickness of the Ti film 35 may be greater than or equal to 500 ⁇ and less than or equal to 1000 ⁇ .
  • the Ni film 36 is thicker than the Ti film 35 and covers the Ti film 35.
  • the Ni film 36 may have a thickness of 5000 ⁇ or more and 20000 ⁇ or more.
  • the Au film 37 is thinner than the Ni film 36 and covers the Ni film 36.
  • the Au film 37 may have a thickness of 500 ⁇ or more and 1000 ⁇ or less.
  • the second electrode 24 may have a stacked structure including a Ti film 38, a Ni film 39, an Au film 40, and an Ag film 41 stacked in this order from the second main surface 4 side. good.
  • the Ti film 38 directly covers the second main surface 4. In this form, the Ti film 38 does not form a silicide (TiSi) layer in the surface layer portion of the second main surface 4. Of course, the Ti film 38 may form a silicide layer in the surface layer portion of the second main surface 4.
  • the Ti film 38 may have a thickness of 500 ⁇ or more and 1000 ⁇ or less.
  • the Ni film 39 is thicker than the Ti film 38 and covers the Ti film 38.
  • the thickness of the Ni film 39 may be 5000 ⁇ or more and 20000 ⁇ or more.
  • the Au film 40 is thinner than the Ni film 39 and covers the Ni film 39.
  • the thickness of the Au film 33 may be greater than or equal to 500 ⁇ and less than or equal to 1000 ⁇ .
  • the Ag film 41 is thicker than the Au film 40 and covers the Au film 40.
  • the thickness of the Ag film 41 may be greater than or equal to 1000 ⁇ and less than or equal to 3000 ⁇ .
  • the wafer structure 1A includes a protective tape 45 attached to the second electrode 24 of the wafer 2.
  • the protective tape 45 may be referred to as a "protective film,” “support tape,” “support film,” or the like. It is preferable that the protective tape 45 is thicker than the second electrode 24.
  • the thickness of the protective tape 45 is preferably greater than the thickness of the first electrode 18.
  • the thickness of the protective tape 45 is preferably greater than the thickness of the insulating film 19.
  • the thickness of the protective tape 45 is preferably less than the thickness of the wafer 2. Of course, the thickness of the protective tape 45 may be greater than the thickness of the wafer 2.
  • the protective tape 45 includes a base film 46 and an adhesive layer 47.
  • the base film 46 is made of an optically transparent organic film. It is preferable that the base film 46 has a planar shape corresponding to the planar shape of the wafer 2. In this embodiment, the base film 46 is formed into a circular shape in plan view. When a rectangular parallelepiped-shaped wafer 2 is employed, the base film 46 is preferably formed into a rectangular shape in plan view.
  • the base film 46 is preferably thicker than the second electrode 24.
  • the thickness of the base film 46 is preferably greater than the thickness of the first electrode 18.
  • the thickness of the base film 46 is preferably greater than the thickness of the insulating film 19.
  • the thickness of the base film 46 is preferably less than the thickness of the wafer 2.
  • the thickness of the base film 46 may be two or more wafers.
  • the thickness of the base film 46 may be 10 ⁇ m or more and 100 ⁇ m or less.
  • the thickness of the base film 46 is preferably 20 ⁇ m or more and 50 ⁇ m or less.
  • the adhesive layer 47 is provided on one side of the base film 46. It is preferable that the adhesive layer 47 is provided over the entire area on one side of the base film 46. It is preferable that the adhesive layer 47 is thicker than the second electrode 24. The thickness of the adhesive layer 47 is preferably greater than the thickness of the first electrode 18.
  • the thickness of the adhesive layer 47 is preferably greater than the thickness of the insulating film 19.
  • the thickness of the adhesive layer 47 is preferably less than the thickness of the wafer 2.
  • the thickness of the adhesive layer 47 may be two or more wafers.
  • the thickness of the adhesive layer 47 may be 10 ⁇ m or more and 100 ⁇ m or less.
  • the thickness of the adhesive layer 47 is preferably 20 ⁇ m or more and 50 ⁇ m or less.
  • the adhesive layer 47 may include, for example, a photocurable adhesive whose adhesive strength is reduced by irradiation with ultraviolet rays.
  • the adhesive layer 47 has a property that the adhesive force (adhesive strength) to the wafer 2 is higher than the adhesive force (adhesive strength) to the second electrode 24 .
  • the protective tape 45 has a property that the adhesion force to the plating reaction inhibiting portion 25 (periphery of the second main surface 4) is higher than the adhesion force to the second electrode 24.
  • the adhesive strength of the protective tape 45 (adhesive layer 47) to the wafer 2 is preferably greater than 14.1 N/25 mm.
  • the adhesive strength of the protective tape 45 to the SiC wafer is preferably greater than 14.4 N/25 mm.
  • the adhesive strength of the protective tape 45 to the second electrode 24 is 8 N/25 mm or more and less than 14 N/25 mm.
  • the adhesive strength of the protective tape 45 to the Au film 33 is about 8.9 N/25 mm.
  • the adhesive strength of the protective tape 45 to the Ag film 41 is about 10 N/25 mm.
  • the protective tape 45 is attached to the second main surface 4 side of the wafer 2 by adhering the adhesive layer 47 to the second electrode 24 and the plating reaction inhibiting portion 25 (periphery of the second main surface 4). ing.
  • the protective tape 45 covers the entire area of the second electrode 24 and extends in the form of a film from above the second electrode 24 to above the plating reaction inhibiting portion 25 .
  • the protective tape 45 covers the plating reaction inhibiting portion 25 all around the peripheral edge of the wafer 2 .
  • the protective tape 45 covers the SiC single crystal (in this embodiment, the carbon surface of the SiC single crystal) exposed as the plating reaction inhibiting portion 25. Further, the protective tape 45 covers the grinding marks formed on the plating reaction inhibiting portion 25. In this case, it is preferable that the adhesive layer 47 fills in the grinding marks.
  • the adhesive area of the protective tape 45 (adhesive layer 47) to the plating reaction inhibiting portion 25 (periphery of the second main surface 4) increases due to the grinding marks. Therefore, the adhesive force of the protective tape 45 to the plating reaction inhibiting portion 25 (periphery of the second main surface 4) increases. In other words, the grinding marks also function as anchor holes for the protective tape 45.
  • the adhesive portion of the protective tape 45 to the plating reaction inhibiting portion 25 has a portion extending in an arc shape in a region outside the mark 6 in a plan view, and a portion extending linearly in a region along the mark 6.
  • the adhesive portion of the protective tape 45 is formed in a region outside the plurality of device regions 10 in plan view, and faces the space 11 with the wafer 2 in between.
  • the adhesive portion of the protective tape 45 is formed in a ring shape that collectively surrounds the plurality of device regions 10 in plan view.
  • the protective tape 45 may form a gap 48 between the second main surface 4 and the edge of the second electrode 24. That is, the protective tape 45 may be attached to the second electrode 24 and the plating reaction inhibiting portion 25 so as to expose the edge of the second electrode 24.
  • the gap 48 may be formed on a part of the edge of the second electrode 24 or on the entire circumference.
  • the protective tape 45 may cover a portion of the edge of the second electrode 24 or the entire circumference of the second electrode 24 so that the gap 48 is not formed.
  • the edge of the protective tape 45 has a portion extending in an arc shape in a region outside the mark 6 in plan view, and a portion extending linearly in a region along the mark 6. It is preferable that the protective tape 45 extends from a region on the second main surface 4 to a region outside the second main surface 4 along the horizontal direction. According to this configuration, the entire second main surface 4 can be covered with the protective tape 45. In this case, a portion of the adhesive layer 47 that covers the peripheral edge of the base film 46 may be exposed from the wafer 2.
  • the protective tape 45 exposes the side surface 5 of the wafer 2. It is particularly preferable that the protective tape 45 exposes the entire side surface 5.
  • the fact that the protective tape 45 exposes the entire side surface 5 means that the base film 46 is not attached to the side surface 5 of the wafer 2 via the adhesive layer 47. Therefore, when the base film 46 does not face the side surface 5 with the adhesive layer 47 interposed in a configuration in which a part of the adhesive layer 47 overlaps the lower end of the side surface 5, the protective tape 45 This means that the entire side surface 5 is exposed.
  • the protrusion width Wo of the protective tape 45 may be larger than the thickness of the wafer 2.
  • the protrusion width Wo may be larger than the thickness of the second electrode 24.
  • the protrusion width Wo may be larger than the thickness of the first electrode 18.
  • the protrusion width Wo may be larger than the thickness of the insulating film 19.
  • the protrusion width Wo is preferably less than the exposed width W of the plating reaction inhibiting portion 25.
  • the protrusion width Wo may be 0.1 mm or more and 2 mm or less.
  • the protrusion width Wo is preferably 0.5 mm or more and 1 mm or less.
  • FIGS. 8A to 8F are cross-sectional views showing a method for manufacturing the semiconductor device SD1.
  • 9A to 9C are cross-sectional views showing the process of forming the second electrode 24.
  • 8A to 8F (FIGS. 9F to 9C) are also part of the manufacturing process of the wafer structure 1A.
  • a wafer structure 1A before the step of forming the second electrode 24 is prepared.
  • the wafer structure 1A includes a diode region 14, a guard region 15, a main surface insulating film 16, a first electrode 18, and an insulating film 19 in each device region 10.
  • the wafer structure 1A before the step of forming the second electrode 24 includes the wafer 2 having a thickness of 200 ⁇ m or more.
  • the wafer 2 may have a thickness of 200 ⁇ m or more and 1000 ⁇ m or less.
  • the wafer 2 preferably has a thickness of 250 ⁇ m or more and 500 ⁇ m or less.
  • the wafer 2 may be thinned from the second main surface 4 side by at least one of a grinding method and an etching method.
  • the wafer 2 is thinned by a grinding method on the second main surface 4.
  • the wafer 2 is ground in this configuration to a thickness of less than 200 ⁇ m. As a result, the wafer 2 is thinned, and at the same time, grinding marks are formed on the second main surface 4.
  • a step of forming the second electrode 24 is performed.
  • a mask jig 50 as a mask for the peripheral portion of the second main surface 4 is prepared.
  • the mask jig 50 may be made of an inorganic material such as metal (for example, stainless steel), glass, or ceramic, or may be made of an organic material such as a resin.
  • the mask jig 50 is configured to cover at least a portion of the peripheral edge of the second main surface 4 and expose the inner part of the second main surface 4.
  • the mask jig 50 is configured to cover the region of the peripheral edge of the second main surface 4 that is to be formed as the plating reaction inhibiting portion 25.
  • the mask jig 50 has an annular shape (specifically, an annular shape) in a plan view so as to cover the entire circumference of the peripheral edge of the second main surface 4 and expose the inner part of the second main surface 4. ) is configured.
  • the mask jig 50 may have a portion extending in an arc shape in a region outside the mark 6 in a plan view, and a portion extending linearly in a region along the mark 6. It is preferable that the mask jig 50 is thicker than the second electrode 24 to be formed.
  • the mask jig 50 is brought into contact with the peripheral edge of the second main surface 4.
  • the mask jig 50 is brought into contact with the SiC single crystal (in this embodiment, the carbon surface of the SiC single crystal) exposed from the peripheral edge of the second main surface 4 .
  • the mask jig 50 is arranged in a region outside the plurality of device regions 10 in plan view, and faces the space 11 with the wafer 2 in between. That is, the plating reaction inhibiting portion 25 is arranged so as to collectively surround the plurality of device regions 10 in a plan view.
  • the coverage width (width of contact) of the mask jig 50 with respect to the peripheral edge of the second main surface 4 corresponds to the exposed width W of the plating reaction inhibiting portion 25 .
  • the second electrode 24 is deposited on the second main surface 4 and the mask jig 50 by sputtering.
  • the thickness of the second electrode 24 is less than the thickness of the mask jig 50.
  • the second electrode 24 may include at least one of an Al-based metal film, a Ti-based metal film, a Ni-based metal film, a Pd-based metal film, an Au-based metal film, and an Ag-based metal film.
  • the Al-based metal film, Ti-based metal film, Ni-based metal film, Pd-based metal film, Au-based metal film, and Ag-based metal film can all be formed by a sputtering method.
  • the second electrode 24 (see FIGS. 6, 7A, and 7B) according to the first to third embodiments is formed by appropriately adjusting the order in which these metal films are formed.
  • the mask jig 50 is removed from the second main surface 4.
  • the portion of the second electrode 24 that covers the mask jig 50 is also removed, and the plating reaction inhibiting portion 25 having a layout corresponding to the layout of the mask jig 50 is formed on the peripheral edge of the second main surface 4. It is formed.
  • a protective tape 45 is attached to the second electrode 24 and the plating reaction inhibiting portion 25 (periphery of the second main surface 4). As a result, the wafer structure 1A shown in FIGS. 1 to 6 is manufactured. The wafer structure 1A is handled with the protective tape 45 attached.
  • a plating film 51 is formed on the first electrode 18 by a plating method.
  • the plating film 51 may be regarded as one component of the wafer structure 1A.
  • the entire wafer structure 1A is immersed in a plating solution, and a plating film 51 is formed on the first electrode 18.
  • This step may include a step of shaking the wafer structure 1A in the plating solution.
  • the rocking step includes a stirring step in which bubbles generated during the plating reaction are diffused into the liquid. According to this step, defects in the formation of the plating film 51 due to air bubbles are suppressed.
  • the protective tape 45 protects the second electrode 24 from the plating solution and at the same time suppresses deformation of the wafer 2 in the plating solution. Thereby, abnormal deposition of the plating film 51 on the second electrode 24 is suppressed, and at the same time, cracks in the wafer 2 are suppressed.
  • the second electrode 24 exposes the peripheral edge of the second main surface 4, and the protective tape 45 covers the peripheral edge of the second main surface 4.
  • the protective tape 45 has a property that the adhesion force to the peripheral edge of the second main surface 4 is higher than the adhesion force to the second electrode 24. According to this configuration, peeling of the protective tape 45 at the peripheral edge of the second main surface 4 is suppressed.
  • the peripheral edge portion of the second main surface 4 is exposed as a plating reaction inhibiting portion 25 that has a slow reaction rate to the plating solution.
  • the formation of the plating film 51 is inhibited. Therefore, even if the plating solution enters the region between the second main surface 4 and the protective tape 45, the plating reaction inhibiting portion 25 suppresses abnormal plating film formation.
  • the step of forming the plating film 51 includes the step of forming a Ni plating film 52, a Pd plating film 53, and an Au plating film 54 in this order from the first electrode 18 side.
  • the step of forming the Ni plating film 52 includes a step of forming the Ni plating film 52 on the first electrode 18 by electroless plating.
  • the step of forming the Ni plating film 52 includes the step of immersing the wafer structure 1A in a Ni plating solution. Further, the step of forming the Ni plating film 52 includes a step of shaking the wafer structure 1A in the Ni plating solution.
  • the peripheral edge of the second main surface 4 be exposed as a plating reaction inhibiting part 25 that has a slow reaction rate to at least the Ni plating solution.
  • the Ni plating film 52 is preferably thicker than the inorganic insulating film 22.
  • the Ni plating film 52 is preferably formed on the first electrode 18 so as to ride on the edge of the inorganic insulating film 22 within the pad opening 20 . It is preferable that the Ni plating film 52 is formed at intervals from the open end of the pad opening 20 toward the first electrode 18 in the vertical direction Z.
  • the Ni plating film 52 covers the first electrode 18 and the inorganic insulating film 22 within the pad opening 20 and is in contact with the organic insulating film 23.
  • the Ni plating film 52 may be formed within the pad opening 20 at a distance from the organic insulating film 23 and may cover the first electrode 18 and the edges of the inorganic insulating film 22 .
  • the Ni plating film 52 may have a thickness of 0.1 ⁇ m or more and 15 ⁇ m or less.
  • the thickness of the Ni plating film 52 may be 0.1 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 6 ⁇ m or less, 6 ⁇ m or more and 9 ⁇ m or less, 9 ⁇ m or more and 12 ⁇ m or less, or 12 ⁇ m or more and 15 ⁇ m or less.
  • the thickness of the Ni plating film 52 is preferably 2 ⁇ m or more and 8 ⁇ m or less.
  • the step of forming the Pd plating film 53 includes the step of forming the Pd plating film 53 on the Ni plating film 52 by electroless plating.
  • the step of forming the Pd plating film 53 includes the step of immersing the wafer structure 1A in a Pd plating solution. Further, the step of forming the Pd plating film 53 includes a step of shaking the wafer structure 1A in the Pd plating solution.
  • the peripheral edge of the second main surface 4 is preferably exposed as a plating reaction inhibiting portion 25 that has a slow reaction rate to the Pd plating solution.
  • the Pd plating film 53 is formed in a film shape along the outer surface of the Ni plating film 52. It is preferable that the Pd plating film 53 is formed at a distance from the open end of the pad opening 20 toward the Ni plating film 52 side. The Pd plating film 53 is in contact with the organic insulating film 23 within the pad opening 20 in the vertical direction Z. Of course, if the Ni plating film 52 is spaced apart from the organic insulating film 23, the Pd plating film 53 may cover the Ni plating film 52 at a distance from the organic insulating film 23. In this case, the Pd plating film 53 may cover the edge of the inorganic insulating film 22.
  • the Pd plating film 53 has a thickness less than the thickness of the Ni plating film 52.
  • the thickness of the Pd plating film 53 may be 0.01 ⁇ m or more and 1 ⁇ m or less.
  • the thickness of the Pd plating film 53 is 0.01 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 0.2 ⁇ m or less, 0.2 ⁇ m or more and 0.4 ⁇ m or less, 0.4 ⁇ m or more and 0.6 ⁇ m or less, and 0.6 ⁇ m or more and 0.6 ⁇ m or less. .8 ⁇ m or less, or 0.8 ⁇ m or more and 1 ⁇ m or less.
  • the step of forming the Au plating film 54 includes the step of forming the Au plating film 54 on the Pd plating film 53 by electroless plating.
  • the step of forming the Au plating film 54 includes the step of immersing the wafer structure 1A in an Au plating solution. Further, the step of forming the Au plating film 54 includes a step of shaking the wafer structure 1A in the Au plating solution.
  • the peripheral edge of the second main surface 4 is preferably exposed as a plating reaction inhibiting portion 25 that has a slow reaction rate to the Au plating solution.
  • the Au plating film 54 is formed in a film shape along the outer surface of the Pd plating film 53. It is preferable that the Au plating film 54 is formed at intervals from the open end of the pad opening 20 toward the Pd plating film 53 in the vertical direction Z. The Au plating film 54 is in contact with the organic insulating film 23 within the pad opening 20 . Of course, if the Ni plating film 52 and the Pd plating film 53 are spaced apart from the organic insulating film 23, the Au plating film 54 may cover the Pd plating film 53 at a distance from the organic insulating film 23. In this case, the Au plating film 54 may cover the edge of the inorganic insulating film 22.
  • the Au plating film 54 has a thickness less than the thickness of the Ni plating film 52.
  • the thickness of the Au plating film 54 may be 0.01 ⁇ m or more and 1 ⁇ m or less.
  • the thickness of the Au plating film 54 is 0.01 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 0.2 ⁇ m or less, 0.2 ⁇ m or more and 0.4 ⁇ m or less, 0.4 ⁇ m or more and 0.6 ⁇ m or less, and 0.6 ⁇ m or more and 0.6 ⁇ m or less. .8 ⁇ m or less, or 0.8 ⁇ m or more and 1 ⁇ m or less.
  • the plating film 51 includes a Ni plating film 52, a Pd plating film 53, and an Au plating film 54.
  • the plating film 51 may have a laminated structure including only the Ni plating film 52 and the Au plating film 54, which are laminated in this order from the first electrode 18 side.
  • the plating film 51 may have a single layer structure consisting of the Ni plating film 52, the Pd plating film 53, or the Au plating film 54.
  • the protective tape 45 is peeled off from the second main surface 4 and the second electrode 24.
  • This step includes a step of irradiating the adhesive layer 47 of the protective tape 45 with ultraviolet rays to reduce the adhesive strength of the adhesive layer 47. Further, this step includes a step of peeling the base film 46 together with the adhesive layer 47 from the second electrode 24 .
  • the wafer 2 is cut along a plurality of scheduled cutting lines 12.
  • the wafer 2 may be cut (cut) in the vertical direction Z by a dicing blade, or may be cut (cleaved) in the vertical direction Z by a cleavage method using a laser beam irradiation process.
  • a cleavage method a modified layer in which a part of the crystal structure is modified is formed inside the wafer 2 by laser beam irradiation, and the wafer 2 is cleaved in the vertical direction Z starting from the modified layer.
  • the semiconductor device SD1 SiC semiconductor device in this embodiment
  • the wafer structure 1A includes the wafer 2, the first electrode 18, the second electrode 24, and the protective tape 45.
  • the wafer 2 has a first main surface 3 on one side and a second main surface 4 on the other side.
  • the first electrode 18 covers the first main surface 3.
  • the second electrode 24 covers the inner part of the second main surface 4 so that the peripheral edge of the second main surface 4 is exposed.
  • the protective tape 45 is attached to the peripheral edge of the second main surface 4 and the second electrode 24 .
  • the protective tape 45 has a property that the adhesion force to the peripheral edge of the second main surface 4 is higher than the adhesion force to the second electrode 24.
  • peeling of the protective tape 45 from the second main surface 4 and the second electrode 24 can be suppressed.
  • the wafer structure 1A is subjected to the manufacturing method of the semiconductor device SD1
  • manufacturing defects due to peeling of the protective tape 45 can be suppressed. Therefore, it is possible to provide a wafer structure 1A that contributes to the manufacture of a highly reliable semiconductor device SD1.
  • the plating solution can be prevented from entering the area between the second main surface 4 and the protective tape 45. Thereby, abnormal plating film formation on the second electrode 24 is suppressed.
  • the second electrode 24 has a plating reaction rate higher than that of the wafer 2, it is preferable that the second electrode 24 exposes the peripheral edge of the wafer 2 as a plating reaction inhibiting part 25.
  • the peripheral portion of the wafer 2 is preferably made of a material that inhibits plating film formation.
  • the protective tape 45 is preferably attached to the plating reaction inhibiting portion 25. According to this configuration, it is possible to suppress the plating solution from entering the area between the plating reaction inhibiting portion 25 and the protective tape 45. Further, even if the plating solution invades the region between the second main surface 4 and the protective tape 45, the plating reaction inhibiting portion 25 can suppress abnormal plating film formation.
  • the wafer 2 includes SiC single crystal.
  • the second electrode 24 exposes the SiC single crystal from the periphery of the second main surface 4.
  • the protective tape 45 is preferably attached to the SiC single crystal at the peripheral edge of the second main surface 4. SiC single crystal has physical properties that make it difficult for metal to be deposited by plating. Therefore, even if the plating solution invades the region between the second principal surface 4 and the protective tape 45, abnormal plating film formation can be suppressed by the SiC single crystal.
  • the wafer 2 preferably has a thickness of less than 200 ⁇ m. According to this configuration, the on-resistance caused by the thickness of the wafer 2 can be reduced. Moreover, according to the protective tape 45, the wafer 2 can be handled while suppressing deformation of the relatively thin wafer 2.
  • the second electrode 24 exposes the entire periphery of the second main surface 4.
  • the protective tape 45 is preferably attached to the entire circumference of the second main surface 4. According to this configuration, peeling of the protective tape 45 from the second main surface 4 can be suppressed over the entire circumference of the peripheral edge of the second main surface 4. Further, it is possible to suppress the plating solution from entering the area between the second main surface 4 and the protective tape 45 around the entire circumference of the second main surface 4 .
  • the exposed width W of the plating reaction inhibiting portion 25 is larger than the thickness of the second electrode 24. It is preferable that the exposure width W is larger than the thickness of the wafer 2. According to these configurations, the risk of contact of the plating solution with the second electrode 24 can be appropriately reduced.
  • the second main surface 4 has grinding marks.
  • the second electrode 24 preferably has grinding marks exposed at the peripheral edge of the second main surface 4.
  • the protective tape 45 is attached to the peripheral edge portion having the grinding marks. According to this configuration, the adhesion of the protective tape 45 to the peripheral edge of the second main surface 4 can be increased by the grinding marks.
  • the second main surface 4 is preferably a flat surface. That is, it is preferable that the second main surface 4 does not have a stepped portion recessed toward the first main surface 3 side. According to this configuration, formation of a fragile portion of the wafer 2 on the second main surface 4 can be appropriately suppressed. In particular, such a configuration is preferably applied to wafers 2 of less than 200 ⁇ m.
  • the wafer structure 1A may include a plating film 51 that covers the first electrode 18.
  • the second electrode 24 exposes the peripheral edge of the wafer 2 as a plating reaction inhibiting portion 25 that inhibits the formation of the plating film 51.
  • the plating film 51 may include at least one of a Ni plating film 52, a Pd plating film 53, and an Au plating film 54.
  • the wafer structure 1A may include a plurality of device regions 10 set in the inner part of the first main surface 3.
  • the second electrode 24 exposes a region outside the plurality of device regions 10 in plan view. According to this configuration, the semiconductor device SD1 having the second electrode 24 can be appropriately manufactured.
  • the method for manufacturing the semiconductor device SD1 includes a step of preparing the wafer structure 1A, a step of forming the second electrode 24, and a step of attaching the protective tape 45.
  • the wafer structure 1A is prepared, which includes a wafer 2 having a first surface on one side and a second main surface 4 on the other side, and a first electrode 18 covering the first surface.
  • the second electrode 24 is formed to cover the inner part of the second main surface 4 so as to expose the peripheral edge of the second main surface 4.
  • the protective tape 45 which has a property that the adhesive force to the peripheral edge of the second main surface 4 is higher than the adhesive force to the second electrode 24, is attached to the peripheral edge of the second main surface 4 and the second electrode. It is attached to 24.
  • this manufacturing method peeling of the protective tape 45 from the second main surface 4 and the second electrode 24 can be suppressed. Thereby, manufacturing defects caused by peeling of the protective tape 45 can be suppressed. Therefore, it is possible to provide a manufacturing method that contributes to manufacturing the semiconductor device SD1 with high reliability. For example, when the wafer 2 is immersed in a plating solution with the protective tape 45 attached, the plating solution can be prevented from entering the area between the second main surface 4 and the protective tape 45. Thereby, abnormal plating film formation on the second electrode 24 is suppressed.
  • the second electrode 24 has a plating reaction rate higher than that of the wafer 2, it is preferable that the second electrode 24 exposes the peripheral edge of the wafer 2 as a plating reaction inhibiting part 25.
  • the peripheral portion of the wafer 2 is preferably made of a material that inhibits plating film formation.
  • the protective tape 45 is preferably attached to the plating reaction inhibiting portion 25. According to this manufacturing method, it is possible to suppress the plating solution from entering the area between the plating reaction inhibiting portion 25 and the protective tape 45. Further, even if the plating solution invades the region between the second main surface 4 and the protective tape 45, the plating reaction inhibiting portion 25 can suppress abnormal plating film formation.
  • the method for manufacturing the semiconductor device SD1 preferably further includes the step of immersing the wafer structure 1A in a plating solution with the protective tape 45 attached to form a plating film 51 on the first electrode 18. According to this manufacturing method, it is possible to suppress the plating solution from entering the area between the second main surface 4 and the protective tape 45. Thereby, abnormal plating film formation on the second electrode 24 can be suppressed.
  • the step of forming the plating film 51 includes a step of shaking the wafer structure 1A in the plating solution.
  • this manufacturing method bubbles generated during the plating reaction can be diffused into the liquid. Thereby, defects in film formation of the plating film 51 due to air bubbles can be suppressed.
  • the second electrode 24 can be protected from the plating solution by the protective tape 45, and at the same time, the deformation of the wafer 2 in the plating solution can be suppressed by the protective tape 45.
  • the step of forming the plating film 51 includes a step of immersing the wafer structure 1A in a Ni plating solution to form a Ni plating film 52, a step of immersing the wafer structure 1A in a Pd plating solution to form a Pd plating film 53, and , may include at least one step of immersing the wafer structure 1A in an Au plating solution to form the Au plating film 54.
  • the protective tape 45 removes at least one of the abnormal formation of the Ni plating film 52, the abnormal formation of the Pd plating film 53, and the abnormal film formation of the Au plating film 54 on the second main surface 4 side. can be suppressed by
  • the wafer 2 includes SiC single crystal.
  • the second electrode 24 is preferably formed so as to expose the SiC single crystal from the peripheral edge of the second main surface 4.
  • the protective tape 45 is preferably attached to the SiC single crystal at the peripheral edge of the second main surface 4.
  • SiC single crystal has physical properties that make it difficult for metal to be deposited by plating. Therefore, even if the plating solution invades the region between the second principal surface 4 and the protective tape 45, abnormal plating film formation can be suppressed by the SiC single crystal.
  • the wafer structure 1A including the wafer 2 having a thickness of 200 ⁇ m or more is prepared.
  • the method for manufacturing the semiconductor device SD1 preferably includes a step of thinning the wafer 2 to a thickness of less than 200 ⁇ m prior to the step of forming the second electrode 24.
  • the wafer 2 can be handled while suppressing deformation of the wafer 2 due to the relatively thick wafer 2 up to the thinning process of the wafer 2. Then, in the process of thinning the wafer 2, the on-resistance caused by the thickness of the wafer 2 can be reduced. After the step of attaching the protective tape 45, the wafer 2 can be handled while suppressing deformation of the relatively thin wafer 2 with the protective tape 45.
  • the process of thinning the wafer 2 may include a process of grinding the entire second main surface 4 by a grinding method.
  • the second electrode 24 is preferably formed so as to expose grinding marks at the peripheral edge of the second main surface 4.
  • the protective tape 45 be attached to the peripheral edge portion having the grinding marks. According to this manufacturing method, the adhesion of the protective tape 45 to the peripheral edge of the second main surface 4 can be increased by the grinding marks.
  • FIG. 10 is a plan view of the wafer structure 1B according to the second embodiment, viewed from the first main surface 3 side.
  • FIG. 11 is a sectional view taken along the line XI-XI shown in FIG. 10.
  • FIG. 12 is an enlarged sectional view showing a main part of the functional device 13 shown in FIG. 11.
  • FIG. 13 is a schematic cross-sectional view of the wafer structure 1B shown in FIG.
  • wafer structure 1B has a different configuration from wafer structure 1A described above in that functional device 13 includes a MISFET instead of an SBD.
  • the functional device 13 is shown in a simplified manner by broken lines.
  • the MISFET is a trench gate type.
  • the other configurations of the wafer structure 1B are substantially the same as those of the wafer structure 1A. Below, the differences between the wafer structure 1B and the wafer structure 1A will be explained. Further, below, the configuration of one device area 10 will be explained.
  • the wafer structure 1B includes a p-type body region 60 formed in the surface layer portion of the first main surface 3 in the device region 10.
  • the body region 60 is formed at intervals from the bottom of the first region 7 toward the first main surface 3 and extends in a layered manner on the surface layer of the first main surface 3.
  • the body region 60 may be formed over the entire first main surface 3.
  • the wafer structure 1B includes an n-type source region 61 formed in the surface layer of the body region 60 in the device region 10.
  • the source region 61 may be formed inside the device region 10 at a distance from the periphery of the device region 10 .
  • Source region 61 has a higher n-type impurity concentration than first region 7 .
  • the source region 61 is formed at intervals from the bottom of the body region 60 toward the first main surface 3 and extends in a layered manner on the surface layer of the first main surface 3 .
  • Source region 61 forms a channel with first region 7 within body region 60 .
  • the wafer structure 1B includes a plurality of first trench structures 62 formed on the first main surface 3 in the device region 10.
  • First trench structure 62 may be referred to as a "trench gate structure.”
  • the plurality of first trench structures 62 control channel inversion and non-inversion.
  • the plurality of first trench structures 62 penetrate the body region 60 and the source region 61 and reach the first region 7 .
  • the plurality of first trench structures 62 may be arranged at intervals in the first direction X in a plan view, and each may be formed in a band shape extending in the second direction Y.
  • the plurality of first trench structures 62 are formed at intervals from the bottom of the first region 7 toward the first main surface 3 side.
  • Each first trench structure 62 includes a first trench 63, a first insulating film 64, and a first buried electrode 65.
  • the first trench 63 is formed on the first main surface 3 and partitions a wall surface of the first trench 63.
  • the first insulating film 64 covers the wall surface of the first trench 63.
  • the first buried electrode 65 is buried in the first trench 63 with the first insulating film 64 interposed therebetween.
  • the first buried electrode 65 faces the channel with the first insulating film 64 in between.
  • the wafer structure 1B includes a plurality of second trench structures 66 formed on the first main surface 3 in the device region 10.
  • Second trench structure 66 may be referred to as a "trench source structure.”
  • the plurality of second trench structures 66 are each formed in a region between two adjacent first trench structures 62.
  • the plurality of second trench structures 66 may each be formed in a band shape extending in the second direction Y in plan view.
  • the plurality of second trench structures 66 penetrate the body region 60 and the source region 61 and reach the first region 7 .
  • the plurality of second trench structures 66 are formed at intervals from the bottom of the first region 7 toward the first main surface 3 side, and are formed deeper than the first trench structures 62 .
  • Each second trench structure 66 includes a second trench 67, a second insulating film 68, and a second buried electrode 69.
  • the second trench 67 is formed on the first main surface 3 and defines a wall surface of the second trench 67.
  • the second insulating film 68 covers the wall surface of the second trench 67.
  • the second buried electrode 69 is buried in the second trench 67 with the second insulating film 68 interposed therebetween.
  • the wafer structure 1B includes a plurality of p-type contact regions 70 formed in regions along the plurality of second trench structures 66 within the wafer 2 in the device region 10.
  • the plurality of contact regions 70 have a higher p-type impurity concentration than the body region 60.
  • Each contact region 70 covers the sidewalls and bottom wall of each second trench structure 66 and is electrically connected to body region 60 .
  • the wafer structure 1B includes a plurality of p-type well regions 71 formed in regions along the plurality of second trench structures 66 within the wafer 2 in the device region 10.
  • Each well region 71 has a p-type impurity concentration higher than that of body region 60 and lower than that of contact region 70.
  • Each well region 71 covers a corresponding second trench structure 66 with a corresponding contact region 70 in between.
  • Each well region 71 covers the side and bottom walls of the corresponding second trench structure 66 and is electrically connected to the body region 60 .
  • the wafer structure 1B includes a main surface insulating film 16 that covers the first main surface 3 in the device region 10.
  • the main surface insulating film 16 is continuous with the first insulating film 64 and the second insulating film 68, and exposes the first buried electrode 65 and the second buried electrode 69.
  • the main surface insulating film 16 covers the peripheral edge of the device region 10 (the boundary between the plurality of device regions 10). That is, the main surface insulating film 16 covers the entire first main surface 3.
  • the main surface insulating film 16 may expose the peripheral portion of the device region 10 (the boundary portion between the plurality of device regions 10).
  • the wafer structure 1B includes an interlayer insulating film 72 that covers the main surface insulating film 16 in the device region 10.
  • Interlayer insulating film 72 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the interlayer insulating film 72 covers the plurality of first trench structures 62 and the plurality of second trench structures 66.
  • the interlayer insulating film 72 covers the peripheral edge of the device region 10 (the boundary between the plurality of device regions 10) with the main surface insulating film 16 in between.
  • the interlayer insulating film 72 may cover the entire first main surface 3.
  • the interlayer insulating film 72 may expose the first main surface 3 at the periphery of the device region 10. .
  • the wafer structure 1B includes a first buried electrode 65 disposed on the interlayer insulating film 72 in the device region 10, as in the first embodiment.
  • the first electrode 18 may have a stacked structure including a Ti-based metal film and an Al-based metal film stacked in this order from the first main surface 3 side.
  • the first electrode 18 includes a gate electrode 73 and a source electrode 74.
  • the gate electrode 73 is arranged in a region close to the center of one side of the device region 10 in plan view.
  • the gate electrode 73 may be arranged at a corner of the device region 10 in a plan view.
  • the gate electrode 73 is formed into a rectangular shape in plan view.
  • the source electrode 74 is arranged on the interlayer insulating film 72 at a distance from the gate electrode 73.
  • the source electrode 74 is formed into a polygonal shape having a concave portion recessed along the gate electrode 73 in plan view.
  • the source electrode 74 may be formed into a rectangular shape in plan view.
  • the source electrode 74 penetrates the interlayer insulating film 72 and the main surface insulating film 16 and is electrically connected to the body region 60, the source region 61, and the plurality of second trench structures 66.
  • the wafer structure 1B includes a gate wiring electrode 75 drawn out from the gate electrode 73 onto the interlayer insulating film 72 in the device region 10.
  • the gate wiring electrode 75 may have a stacked structure including a Ti-based metal film and an Al-based metal film stacked in this order from the first main surface 3 side.
  • the gate wiring electrode 75 is formed in a band shape extending along the periphery of the device region 10 so as to intersect (specifically, perpendicularly intersect) with the ends of the plurality of first trench structures 62 in a plan view.
  • the gate wiring electrode 75 penetrates the interlayer insulating film 72 and is electrically connected to the plurality of first trench structures 62 .
  • the wafer structure 1B includes an insulating film 19 that covers the first electrode 18 in the device region 10.
  • the insulating film 19 has a laminated structure including an inorganic insulating film 22 and an organic insulating film 23 laminated in this order from the first electrode 18 side, as in the first embodiment.
  • the insulating film 19 covers the periphery of the gate electrode 73 and the source electrode 74 at a distance inward from the periphery of the device region 10 .
  • the insulating film 19 covers the entire gate wiring electrode 75.
  • the insulating film 19 defines a plurality of pad openings 20 that expose the inner part of the gate electrode 73 and the inner part of the source electrode 74, and defines street openings 21 that expose the interlayer insulating film 72 at the peripheral edge of the device region 10. It is divided.
  • the plurality of pad openings 20 include a gate pad opening 76 that exposes the inner part of the gate electrode 73 and a source pad opening 77 that exposes the inner part of the source electrode 74.
  • the gate pad opening 76 is divided into a rectangular shape along the periphery of the gate electrode 73 in plan view.
  • the source pad opening 77 is formed in a polygonal shape along the periphery of the source electrode 74 in plan view.
  • the street opening 21 is formed in the same manner as in the first embodiment.
  • the organic insulating film 23 may expose the edge of the inorganic insulating film 22 in the gate pad opening 76.
  • the organic insulating film 23 may expose the edge of the inorganic insulating film 22 in the source pad opening 77.
  • the organic insulating film 23 may expose the edge of the inorganic insulating film 22 in the street opening 21.
  • the organic insulating film 23 may cover the entire area of the inorganic insulating film 22.
  • the wafer structure 1B includes a second electrode 24 covering the second main surface 4.
  • the second electrode 24 is formed as a drain electrode and is electrically connected to the second region 8 exposed from the second main surface 4 .
  • the second electrode 24 is formed in the same manner as in the first embodiment. For other explanations of the second electrode 24, the explanations of the first embodiment apply.
  • 14A to 14G are cross-sectional views showing a method for manufacturing the semiconductor device SD2 according to the wafer structure 1B shown in FIG. 10. 14A to 14G are also part of the manufacturing process of wafer structure 1B.
  • the wafer structure 1B before the process of forming the second electrode 24 is prepared.
  • the wafer structure 1B includes, in each device region 10, a body region 60, a source region 61, a first trench structure 62, a second trench structure 66, a contact region 70, a well region 71, a main surface insulating film 16, an interlayer insulating film 72, It includes a gate electrode 73 (first electrode 18), a source electrode 74 (first electrode 18), a gate wiring electrode 75, and an insulating film 19.
  • the wafer structure 1A before the step of forming the second electrode 24 includes the wafer 2 having a thickness of 200 ⁇ m or more.
  • the wafer 2 may have a thickness of 200 ⁇ m or more and 1000 ⁇ m or less.
  • the wafer 2 preferably has a thickness of 250 ⁇ m or more and 500 ⁇ m or less.
  • the wafer 2 may be thinned from the second main surface 4 side by at least one of a grinding method and an etching method.
  • the wafer 2 is thinned by a grinding method on the second main surface 4.
  • the wafer 2 is ground in this configuration to a thickness of less than 200 ⁇ m. As a result, grinding marks are formed on the second main surface 4.
  • a step of forming the second electrode 24 is performed.
  • the second electrode 24 is formed through steps similar to those shown in FIGS. 9A to 9C described above.
  • the plating reaction inhibiting portion 25 having a layout corresponding to the layout of the mask jig 50 is formed at the peripheral portion of the second main surface 4.
  • a protective tape 45 is attached to the second electrode 24 and the plating reaction inhibiting portion 25 (periphery of the second main surface 4).
  • the wafer structure 1B shown in FIGS. 10 to 13 is manufactured.
  • the wafer structure 1B is handled with the protective tape 45 attached.
  • a plating film 51 is formed on the first electrode 18 by a plating method.
  • the step of forming plating film 51 includes the step of forming gate plating film 78 on gate electrode 73 and the step of forming source plating film 79.
  • the plating film 51 (gate plating film 78 and source plating film 79) may be regarded as one component of the wafer structure 1B.
  • the step of forming the plating film 51 includes the step of forming a Ni plating film 52, a Pd plating film 53, and an Au plating film 54 in this order from the first electrode 18 side, as in the first embodiment.
  • Ni plating film 52, Pd plating film 53, and Au plating film 54 are formed in pad opening 20 (gate pad opening 76 and source pad opening 77) in the same form as in the first embodiment.
  • the plating film 51 may have a laminated structure including only the Ni plating film 52 and the Au plating film 54, which are laminated in this order from the first electrode 18 side. Further, the plating film 51 may have a single layer structure consisting of a Ni plating film 52, a Pd plating film 53, or an Au plating film 54.
  • the protective tape 45 is peeled off from the second main surface 4 and the second electrode 24.
  • This step includes a step of irradiating the adhesive layer 47 of the protective tape 45 with ultraviolet rays to reduce the adhesive strength of the adhesive layer 47. Further, this step includes a step of peeling the base film 46 together with the adhesive layer 47 from the second electrode 24 .
  • the wafer 2 is cut along a plurality of scheduled cutting lines 12.
  • the wafer 2 may be cut (cut) with a dicing blade, or may be cut (cleaved) by a cleavage method using a laser beam irradiation process.
  • the semiconductor device SD2 SiC semiconductor device in this embodiment
  • the wafer structure 1B also provides the same effects as those described for the wafer structure 1A. Furthermore, the method for manufacturing the semiconductor device SD2 according to the wafer structure 1B also provides the same effects as those described for the method for manufacturing the semiconductor device SD2 according to the wafer structure 1A.
  • FIG. 15 is a plan view showing a wafer 2 according to a modification applied to each of the above-described embodiments.
  • the mark 6 on the wafer 2 according to each of the embodiments described above includes an orientation flat.
  • the mark 6 of the wafer 2 according to the modified example has an orientation concave in a tapered shape (tapered shape or triangular shape) toward the center of the first main surface 3 on the side surface 5. Including notch.
  • the orientation notch may be recessed in the first direction X or the second direction Y (a-axis direction or m-axis direction) in plan view.
  • the mark 6 may include a first orientation notch recessed in the first direction X and a first orientation notch recessed in the second direction Y.
  • the landmark 6 may also include at least one orientation flat and at least one orientation notch.
  • the second electrode 24 does not need to have a linearly extending portion along the orientation notch.
  • the second electrode 24 covers the second major surface 4 and is spaced inwardly from the orientation notch to expose the orientation notch.
  • the second electrode 24 may have a peripheral portion of the second main surface 4 exposed in an annular shape. That is, the plating reaction inhibiting portion 25 may expose the peripheral edge of the second main surface 4 in an annular shape in a region along the mark 6 and a region outside the mark 6.
  • the edge of the protective tape 45 does not need to have a linearly extending portion along the orientation notch.
  • the edge of the protective tape 45 may be formed in a circular shape over the entire circumference of the second main surface 4 in plan view.
  • FIG. 16 is a schematic cross-sectional view showing the formation process of the second electrode 24 according to the first modification applied to each of the above-described embodiments.
  • FIG. 17 is a schematic cross-sectional view showing a process of forming the second electrode 24 according to a second modification applied to each of the above-described embodiments.
  • FIG. 18 is a schematic cross-sectional view showing a process of forming the second electrode 24 according to a third modification applied to each of the above-described embodiments.
  • the process of forming the second electrode 24 using the mask jig 50 has been described.
  • the second electrode 24 may be formed on the second main surface 4 by a lift-off method.
  • a resist mask 81 may be formed on the second main surface 4 instead of the mask jig 50, and the resist mask 81 may be removed after the second electrode 24 is formed.
  • a process using the mask jig 50 is preferable.
  • the second electrode 24 may be formed into a predetermined layout by an etching method.
  • a resist mask 82 with a predetermined layout is formed on the second electrode 24, and the second electrode is etched by an etching method through the resist mask 82. 24 are formed into a predetermined layout. After the unnecessary portion of the second electrode 24 is removed, the resist mask 82 is removed. Considering the number of man-hours and the load on the wafer 2, a process using the mask jig 50 is preferable.
  • the second electrode 24 may be formed into a predetermined layout by a grinding method.
  • unnecessary portions of the second electrode 24 may be removed by a bevel grinding method for the peripheral edge of the second electrode 24 (the peripheral edge of the second main surface 4).
  • a portion of the wafer 2 may be removed along with a portion of the second electrode 24.
  • the plating reaction inhibiting portion 25 may have a stepped portion 83 that is sunken toward the first main surface 3 at the peripheral edge of the second main surface 4 .
  • a process using the mask jig 50 is preferable.
  • each embodiment may be implemented in other forms.
  • the second region 8 may be removed until the thickness becomes less than the thickness of the first region 7.
  • the entire second region 8 may be removed in the process of thinning the wafer 2 according to each of the embodiments described above. That is, the wafer 2 having a single layer structure including the first region 7 (SiC epitaxial layer) may be formed.
  • the protective tape 45 having a thickness greater than the thickness of the wafer 2 may be attached to the second main surface 4 side.
  • a protective tape 45 having a thickness smaller than the thickness of the wafer 2 may be attached to the second main surface 4 side.
  • the functional device 13 included either an SBD or a MISFET.
  • the functional device 13 may include both an SBD and a MISFET. That is, both the SBD and MISFET may be formed within the same device region 10.
  • the functional device 13 including the SBD and the functional device 13 including the MISFET may be formed in different device regions 10 on the same wafer 2.
  • the functional device 13 may include a planar gate type MISFET instead of a trench gate type MISFET.
  • a p-type second region 8 may be employed instead of the n-type second region 8.
  • the functional device 13 includes an IGBT (Insulated Gate Bipolar Transistor) instead of the MISFET.
  • IGBT Insulated Gate Bipolar Transistor
  • a wafer (2) having a first surface (3) on one side and a second surface (4) on the other side; a first electrode (18) covering the first surface (3); A second electrode (24) that covers the inner part of the second surface (4) so as to expose the peripheral edge of the second surface (4), and an adhesive force of the second surface (4) to the peripheral edge of the second surface (4).
  • a protective tape (45) having a property higher in adhesion to the second electrode (24) and attached to the peripheral edge of the second surface (4) and the second electrode (24); wafer structure (1A, 1B).
  • the second electrode (24) has a plating reaction rate higher than that of the wafer (2), and exposes the peripheral portion of the wafer (2) as a plating reaction inhibiting portion (25).
  • the wafer (2) includes a SiC single crystal
  • the second electrode (24) exposes the SiC single crystal from the peripheral edge of the second surface (4)
  • the protective tape (45) ) is the wafer structure (1A, 1B) according to A1 or A2, wherein the wafer structure (1A, 1B) is attached to the SiC single crystal at the peripheral edge of the second surface (4).
  • the second electrode (24) exposes the entire circumference of the peripheral edge, and the protective tape (45) is attached to the entire circumference of the peripheral edge.
  • the wafer (2) has the second surface (4) having grinding marks, and the second electrode (24) exposes the peripheral portion having the grinding marks, and the protective tape ( 45) is the wafer structure (1A, 1B) according to any one of A1 to A7, which is attached to the peripheral edge portion having the grinding marks.
  • A12 It further includes a plurality of device regions (10) set in the inner part of the first surface (3), and the second electrode (24) is arranged outside the plurality of device regions (10) in a plan view.
  • the wafer structure (1A, 1B) according to any one of A1 to A11, exposing a region of.
  • a wafer (2) having a first surface (3) on one side and a second surface (4) on the other side, and a wafer including a first electrode (18) covering the first surface (3).
  • a method for manufacturing a semiconductor device (SD1, SD2) the method comprising: adhering the second electrode (SD1, SD2) to the second electrode (24).
  • the second electrode (24) has a plating reaction rate higher than that of the wafer (2), and exposes the peripheral portion of the wafer (2) as a plating reaction inhibiting portion (25).
  • the step of forming the plating film (51) includes immersing the wafer structure (1A, 1B) in a Ni plating solution to form a Ni plating film (52), and immersing the wafer structure (1A, 1B) in a Pd plating solution. , 1B) to form a Pd plating film (53), and a step of immersing the wafer structure (1A, 1B) in an Au plating solution to form an Au plating film (54).
  • the wafer (2) includes a SiC single crystal
  • the second electrode (24) exposes the SiC single crystal from the peripheral edge of the second surface (4)
  • the protective tape (45) ) is a method for manufacturing a semiconductor device (SD1, SD2) according to any one of A13 to A17, wherein the semiconductor device (SD1, SD2) is attached to the SiC single crystal at the peripheral edge of the second surface (4).
  • A20 The method for manufacturing a semiconductor device (SD1, SD2) according to A19, wherein the step of thinning the wafer (2) includes a step of grinding the second surface (4) by a grinding method.

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PCT/JP2023/020891 2022-06-14 2023-06-05 ウエハ構造および半導体装置の製造方法 Ceased WO2023243470A1 (ja)

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DE112023002292.5T DE112023002292T5 (de) 2022-06-14 2023-06-05 Waferstruktur und verfahren zum herstellen von halbleitervorrichtungen
CN202380046937.XA CN119384876A (zh) 2022-06-14 2023-06-05 晶圆构造以及半导体装置的制造方法
US18/979,949 US20250112080A1 (en) 2022-06-14 2024-12-13 Wafer structure and method for manufacturing semiconductor devices

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JP2017135273A (ja) * 2016-01-28 2017-08-03 株式会社東芝 半導体装置およびその製造方法
JP2018204066A (ja) * 2017-06-02 2018-12-27 公益財団法人福岡県産業・科学技術振興財団 電極形成方法及び半導体素子電極構造
JP2022017930A (ja) * 2020-07-14 2022-01-26 富士電機株式会社 半導体装置の製造方法
JP2022069819A (ja) * 2020-10-26 2022-05-12 富士電機株式会社 半導体装置の製造方法及びホットプレート

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JP2009094287A (ja) * 2007-10-09 2009-04-30 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2017135273A (ja) * 2016-01-28 2017-08-03 株式会社東芝 半導体装置およびその製造方法
JP2018204066A (ja) * 2017-06-02 2018-12-27 公益財団法人福岡県産業・科学技術振興財団 電極形成方法及び半導体素子電極構造
JP2022017930A (ja) * 2020-07-14 2022-01-26 富士電機株式会社 半導体装置の製造方法
JP2022069819A (ja) * 2020-10-26 2022-05-12 富士電機株式会社 半導体装置の製造方法及びホットプレート

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