WO2023243343A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2023243343A1
WO2023243343A1 PCT/JP2023/019328 JP2023019328W WO2023243343A1 WO 2023243343 A1 WO2023243343 A1 WO 2023243343A1 JP 2023019328 W JP2023019328 W JP 2023019328W WO 2023243343 A1 WO2023243343 A1 WO 2023243343A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
die pad
main surface
semiconductor element
terminal lead
Prior art date
Application number
PCT/JP2023/019328
Other languages
French (fr)
Japanese (ja)
Inventor
英俊 安部
景 千賀
Original Assignee
ローム株式会社
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Filing date
Publication date
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Publication of WO2023243343A1 publication Critical patent/WO2023243343A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Definitions

  • the present disclosure relates to a semiconductor device.
  • Patent Document 1 semiconductor devices are known in which semiconductor elements such as diodes or transistors are covered with resin packages (for example, Patent Document 1).
  • the semiconductor device described in Patent Document 1 includes a semiconductor element, a lead frame, and a resin package.
  • the lead frame includes a plurality of leads, one of which includes a die bonding pad.
  • a semiconductor element is mounted on a die bonding pad.
  • the resin package covers the semiconductor element and also partially covers each of the plurality of leads. The portion of each lead exposed from the resin package is a terminal of the semiconductor device.
  • Such a semiconductor device is mounted on a circuit board of, for example, an electronic device and used in a power supply circuit.
  • the power supply circuit includes, for example, a DC/DC converter such as a half bridge circuit and a chopper circuit.
  • a DC/DC converter such as a half bridge circuit and a chopper circuit.
  • An object of the present disclosure is to provide a semiconductor device that is improved over conventional ones.
  • an object of the present disclosure is to provide a semiconductor device that can reduce the mounting area on a circuit board.
  • a semiconductor device provided by a first aspect of the present disclosure includes a first semiconductor element having a first main surface facing one side in the thickness direction and a first main surface electrode disposed on the first main surface; a second semiconductor element having a second main surface facing in the same direction as the first main surface and a second main surface electrode disposed on the second main surface; a first die pad on which the first semiconductor element is mounted; A second die pad, which is arranged on one side of the first die pad in a first direction perpendicular to the thickness direction and on which the second semiconductor element is mounted, is spaced apart from the first die pad and the second die pad.
  • FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment.
  • FIG. 2 is a plan view showing the semiconductor device according to the first embodiment.
  • FIG. 3 is a diagram showing the sealing resin with imaginary lines in the plan view of FIG. 2.
  • FIG. 4 is a partially enlarged view of FIG. 3.
  • FIG. 5 is a bottom view showing the semiconductor device according to the first embodiment.
  • FIG. 6 is a front view showing the semiconductor device according to the first embodiment.
  • FIG. 7 is a right side view showing the semiconductor device according to the first embodiment.
  • FIG. 8 is a partially enlarged view of FIG. 7, showing the sealing resin with imaginary lines.
  • FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 3.
  • FIG. 10 is a sectional view taken along line XX in FIG.
  • FIG. 11 is a partially enlarged view of FIG. 9 .
  • FIG. 12 is a partially enlarged view of FIG. 9 .
  • FIG. 13 is a partially enlarged view of FIG. 9 .
  • FIG. 14 is a partially enlarged view of FIG. 10.
  • FIG. 15 is a partial enlarged view of a part of FIG. 3.
  • FIG. 16 is a partially enlarged view of FIG. 3.
  • FIG. 17 is a partially enlarged view of FIG. 3.
  • FIG. 18 is a partially enlarged view of FIG. 3.
  • FIG. 19 is a diagram showing an example of the circuit configuration of the semiconductor device according to the first embodiment.
  • FIG. 20 is a plan view showing a semiconductor device according to a first modification of the first embodiment, in which a sealing resin is shown with imaginary lines.
  • FIG. 20 is a plan view showing a semiconductor device according to a first modification of the first embodiment, in which a sealing resin is shown with imaginary lines.
  • FIG. 20 is a plan view showing a semiconductor device according
  • FIG. 26 is a plan view showing the semiconductor device according to the second embodiment, in which the sealing resin is shown with imaginary lines.
  • FIG. 27 is a plan view showing a semiconductor device according to a first modification of the second embodiment, in which a sealing resin is shown with imaginary lines.
  • FIG. 28 is a plan view showing the semiconductor device according to the third embodiment, in which the sealing resin is shown with imaginary lines.
  • FIG. 29 is a plan view showing the semiconductor device according to the fourth embodiment, in which the sealing resin is shown with imaginary lines.
  • 30 is a cross-sectional view taken along the line XXX-XXX in FIG. 29, and corresponds to the cross-section in FIG. 9.
  • FIG. 29 is a cross-sectional view taken along the line XXX-XXX in FIG. 29, and corresponds to the cross-section in FIG. 9.
  • FIG. 31 is a cross-sectional view showing a semiconductor device according to a first modification of the fourth embodiment, and corresponds to the cross-section of FIG. 30.
  • FIG. 32 is a cross-sectional view showing a semiconductor device according to a second modification of the fourth embodiment, and corresponds to the cross-section of FIG. 30.
  • a thing A is formed on a thing B" and "a thing A is formed on a thing B” mean “a thing A is formed on a thing B" unless otherwise specified.
  • A is formed directly on something B
  • a thing A is formed on something B, with another thing interposed between them.” including.
  • "a certain thing A is placed on a certain thing B” and "a certain thing A is placed on a certain thing B” are used as "a certain thing A is placed on a certain thing B” unless otherwise specified.
  • ⁇ It is placed directly on something B,'' and ⁇ A thing A is placed on something B, with another thing interposed between them.'' include.
  • an object A is located on an object B
  • an object A is in contact with an object B, and an object A is located on an object B.
  • an object A overlaps an object B when viewed in a certain direction means, unless otherwise specified, “an object A overlaps all of an object B" and "a certain object A overlaps an object B".
  • a certain thing A (the material of the thing) includes a certain material C” means "a case where the thing A (the material of the thing A) consists of a certain material C" and "the main component of the thing A (the material of the thing)”. "is a certain material C”.
  • the semiconductor device A10 includes a first die pad 10A, a second die pad 10B, a plurality of terminal leads 13, a first semiconductor element 21, a second semiconductor element 22, a first conductive member 31, a second conductive member 32, and a pair of first connections. It includes members 41A and 41B, a pair of second connection members 42A and 42B, and a sealing resin 50.
  • the plurality of terminal leads 13 include a first terminal lead 14, a second terminal lead 15, a third terminal lead 16, a fourth terminal lead 171, a fifth terminal lead 172, a sixth terminal lead 181, and a seventh terminal lead 182. .
  • the thickness direction of the semiconductor device A10 will be referred to as the "thickness direction z.”
  • one side of the thickness direction z may be referred to as upper side, and the other side may be referred to as lower side.
  • descriptions such as “upper”, “lower”, “upper”, “lower”, “upper surface”, and “lower surface” indicate the relative positional relationship of each component etc. in the thickness direction z, and do not necessarily mean It is not a term that defines the relationship with the direction of gravity.
  • “planar view” refers to when viewed in the thickness direction z.
  • One direction perpendicular to the thickness direction z is referred to as a "first direction x.”
  • a direction perpendicular to the thickness direction z and the first direction x is referred to as a "second direction y.”
  • the first die pad 10A and the second die pad 10B each have a main surface 101 and a back surface 102.
  • the main surface 101 and the back surface 102 described below are common to the first die pad 10A and the second die pad 10B unless otherwise specified.
  • the main surface 101 faces in the thickness direction z (upward).
  • the main surface 101 is covered with a sealing resin 50.
  • a first semiconductor element 21 is mounted on the main surface 101 of the first die pad 10A.
  • the back surface 102 of the first die pad 10A faces the opposite side to the side where the first semiconductor element 21 is located in the thickness direction z.
  • a second semiconductor element 22 is mounted on the main surface 101 of the second die pad 10B.
  • the sealing resin 50 has a resin main surface 51, a resin back surface 52, a pair of first side surfaces 53, a second side surface 54, a third side surface 55, a plurality of recesses 56, a groove 57, and a plurality of recesses 581, 582.
  • the resin main surface 51 faces the same side as each main surface 101 of the first die pad 10A and the second die pad 10B in the thickness direction z.
  • the resin back surface 52 faces the opposite side from the resin main surface 51 in the thickness direction z.
  • each back surface 102 of the first die pad 10A and the second die pad 10B is exposed from the resin back surface 52.
  • the pair of first side surfaces 53 are located apart from each other in the first direction x.
  • the pair of first side surfaces 53 face in the first direction x and extend in the second direction y.
  • the pair of first side surfaces 53 are connected to the resin main surface 51 and the resin back surface 52.
  • the second side surface 54 and the third side surface 55 are located apart from each other in the second direction y.
  • the second side surface 54 and the third side surface 55 face oppositely to each other in the second direction y and extend in the first direction x.
  • the second side surface 54 and the third side surface 55 are connected to the resin main surface 51 and the resin back surface 52.
  • a plurality of terminal leads 13 are exposed from the third side surface 55.
  • the plurality of recesses 56 are recessed from the third side surface 55 in the second direction y, and extend from the resin main surface 51 to the resin back surface 52 in the thickness direction z. In the first direction They are located individually between the terminal lead 15 and between the second terminal lead 15 and the sixth terminal lead 181.
  • the groove portion 57 is recessed from the resin back surface 52 in the thickness direction z and extends along the second direction y. Both sides of the groove portion 57 in the second direction y are connected to the second side surface 54 and the third side surface 55. When viewed along the thickness direction z, the groove portion 57 separates the back surface 102 of the first die pad 10A and the back surface 102 of the second die pad 10B.
  • each of the plurality of recesses 581, 582 is recessed from the main resin surface 51 in the thickness direction z.
  • the plan view shape of each of the plurality of recesses 581 and 582 is not particularly limited, in the illustrated example, it is circular.
  • Each of the plurality of recesses 581 overlaps the first die pad 10A in plan view.
  • the plurality of recesses 581 are individually located near the four corners of the first die pad 10A in plan view.
  • Each of the plurality of recesses 582 overlaps the second die pad 10B in plan view.
  • the plurality of recesses 582 are individually located near the four corners of the second die pad 10B in plan view.
  • Each of the plurality of recesses 581 and 582 does not overlap with either the first conductive member 31 or the second conductive member 32 in plan view. Furthermore, each of the plurality of recesses 581, 582 does not overlap with either the pair of first connecting members 41A, 41B or the pair of second connecting members 42A, 42B in plan view.
  • the plurality of recesses 581 are formed by pins for fixing the first die pad 10A during manufacturing of the semiconductor device A10. The pin is pressed against the first die pad 10A before forming the sealing resin 50, and fixes the first die pad 10A. In this state, formation of the sealing resin 50 is started. Then, the pin is pulled out before the formation of the sealing resin 50 is completed.
  • the sealing resin 50 is formed in at least a portion of the area where the pin was arranged, so that the main surface 101 of the first die pad 10A is covered with the sealing resin 50.
  • the plurality of recesses 581 are marks formed by such a molding process of the sealing resin 50.
  • the plurality of recesses 582 are formed by pins for fixing the second die pad 10B during manufacturing of the semiconductor device A10.
  • the plurality of recesses 582 are marks formed by the molding process of the sealing resin 50.
  • the sealing resin 50 further has a plurality of traces 589, as shown in FIGS. 1, 2, and 5.
  • the plurality of marks 589 are, for example, marks caused by pressing an ejector pin for ejecting the sealing resin 50 from the mold when the sealing resin 50 was formed.
  • Each of the plurality of traces 589 is depressed from either the resin main surface 51 or the resin back surface 52. Note that none of the plurality of traces 589 may be formed on the sealing resin 50.
  • the back surface 102 of the first die pad 10A and the back surface 102 of the second die pad 10B each have a trace 109.
  • the traces 109 formed on the first die pad 10A and the traces 109 formed on the second die pad 10B are traces where the ejector pins described above were pressed.
  • the trace 109 formed on the first die pad 10A is depressed from the back surface 102 of the first die pad 10A, and the trace 109 formed on the second die pad 10B is depressed from the back surface 102 of the second die pad 10B. Note that the trace 109 does not need to be formed on either the first die pad 10A or the second die pad 10B.
  • the depths of the plurality of traces 589 and the plurality of traces 109 are, for example, smaller than the depths of the plurality of recesses 581, but may be larger or the same.
  • the first die pad 10A and the second die pad 10B have a first end surface 111, a second end surface 112, a third end surface 113, and a fourth end surface 114.
  • the first end surface 111, the second end surface 112, the third end surface 113, and the fourth end surface 114 are covered with a sealing resin 50.
  • the first end surface 111 faces in the first direction x and extends in the second direction y.
  • the first end surface 111 is located closest to the pair of first side surfaces 53 of the sealing resin 50.
  • the second end surface 112 faces in the second direction y and extends in the first direction x.
  • the second end surface 112 is located closest to the second side surface 54 of the sealing resin 50.
  • the third end surface 113 faces opposite to the second end surface 112 in the second direction y, and extends in the first direction x.
  • the third end surface 113 is located closest to the third side surface 55 of the sealing resin 50.
  • the fourth end surface 114 faces opposite to the first end surface 111 in the first direction x, and extends in the second direction y.
  • a groove 57 is located between the fourth end surface 114 of the first die pad 10A and the fourth end surface 114 of the second die pad 10B.
  • the distance P2 between the third end surface 113 and the third side surface 55 is longer than the distance P1 between the second end surface 112 and the second side surface 54.
  • the first die pad 10A and the second die pad 10B have a first corner end surface 121.
  • the first corner end surface 121 is located between the first end surface 111 and the second end surface 112, and is located at the corner of either the first die pad 10A or the second die pad 10B.
  • the first corner end surface 121 is a plane that is covered with the sealing resin 50 and is inclined with respect to the first end surface 111 and the second end surface 112. Either the first inclination angle ⁇ 1 of the first corner end face 121 with respect to the first end face 111 shown in FIG. 15 and the second inclination angle ⁇ 2 of the first corner end face 121 with respect to the second end face 112 shown in FIG. ° or less.
  • One of the plurality of recesses 581 is located near the first corner end surface 121 of the first die pad 10A in plan view, and one of the plurality of recesses 582 is located near the second die pad 10B in plan view. It is located near the first corner end face 121 of.
  • the longest normal line Nmax of the first corner end face 121 is set.
  • the longest normal Nmax is the closest from the first corner end surface 121 of either the first die pad 10A or the second die pad 10B to the first corner end surface 121 of the pair of first side surfaces 53 of the sealing resin 50. This is the maximum value of the normal line of the first corner end surface 121 that reaches the first side surface 53 located therein.
  • the longest normal Nmax is 1.0 times or more the length of the intersection line C (see FIG. 15) between the first corner end surface 121 and a virtual plane whose in-plane directions are the first direction x and the second direction y. It is 1.5 times or less.
  • One of the plurality of recesses 581 is located near the second corner end surface 122 of the first die pad 10A in plan view, and one of the plurality of recesses 582 is located near the second die pad 10B in plan view. It is located near the second corner end face 122 of.
  • the first die pad 10A and the second die pad 10B have a third corner end surface 123.
  • the third corner end surface 123 is located between the second end surface 112 and the fourth end surface 114, and is located at the corner of either the first die pad 10A or the second die pad 10B.
  • the third corner end surface 123 is a plane that is covered with the sealing resin 50 and is inclined with respect to the second end surface 112 and the fourth end surface 114. Either the fifth inclination angle ⁇ 5 of the third corner end face 123 with respect to the fourth end face 114 and the sixth inclination angle ⁇ 6 of the third corner end face 123 with respect to the second end face 112 shown in FIG. ° or less.
  • One of the plurality of recesses 581 is located near the fourth corner end surface 124 of the first die pad 10A in plan view, and one of the plurality of recesses 582 is located near the second die pad 10B in plan view. It is located near the fourth corner end face 124 of.
  • the first semiconductor element 21 has a first main surface 21a and a first back surface 21b.
  • the first main surface 21a and the first back surface 21b are spaced apart from each other in the thickness direction z.
  • the first main surface 21a faces the same direction as the main surface 101 of the first die pad 10A.
  • the first back surface 21b faces opposite to the first main surface 21a in the thickness direction z, and faces the main surface 101 of the first die pad 10A.
  • the first main surface electrode 211 is arranged on the first main surface 21a. A current corresponding to the power converted by the first semiconductor element 21 flows through the first main surface electrode 211 .
  • the first main surface electrode 211 is, for example, a source electrode.
  • the first main surface electrode 211 includes a plurality of metal plating layers.
  • the first main surface electrode 211 includes a nickel (Ni) plating layer and a gold (Au) plating layer laminated on the nickel plating layer.
  • the first main surface electrode 211 may include a nickel plating layer, a palladium (Pd) plating layer laminated on the nickel plating layer, and a gold plating layer laminated on the palladium plating layer. But that's fine.
  • the second semiconductor element 22 is mounted on the main surface 101 of the second die pad 10B.
  • the center of gravity of the second semiconductor element 22 overlaps the center of the second die pad 10B in plan view.
  • the center of the second die pad 10B is the center when the second die pad 10B is divided into Lx (Lx is a positive odd number) in the first direction x, and the center of the second die pad 10B is divided into Ly (Ly) in the second direction y. is a positive odd number) This is the area corresponding to the center when divided.
  • Lx and Ly are each 3 or 5, for example, although there are no limitations.
  • the second semiconductor element 22 has a second main surface 22a and a second back surface 22b.
  • the second main surface 22a and the second back surface 22b are spaced apart from each other in the thickness direction z.
  • the second main surface 22a faces the same direction as the main surface 101 of the second die pad 10B.
  • the second back surface 22b faces the opposite side from the second main surface 22a in the thickness direction z, and faces the main surface 101 of the second die pad 10B.
  • the second semiconductor element 22 is mounted on the second die pad 10B, as shown in FIGS. 3 and 9. As shown in FIG. 12, the second semiconductor element 22 has a second main surface electrode 221, a main surface electrode 222, and a back electrode 223.
  • the second principal surface electrode 221 may include a nickel plating layer, a palladium (Pd) plating layer laminated on the nickel plating layer, and a gold plating layer laminated on the palladium plating layer. But that's fine.
  • the back electrode 223 is arranged on the second back surface 22b. Back electrode 223 is provided facing main surface 101 of second die pad 10B. A current corresponding to the power before being converted by the second semiconductor element 22 flows through the back electrode 223 .
  • the back electrode 223 is, for example, a drain electrode.
  • the second terminal lead 15 includes a portion extending along the second direction y, and is connected to the first die pad 10A. Therefore, the second terminal lead 15 is electrically connected to the back electrode 213 of the first semiconductor element 21 via the first die pad 10A.
  • the second terminal lead 15 is a P terminal (positive electrode) to which a DC power supply voltage to be subjected to power conversion is applied.
  • the second terminal lead 15 includes a covering portion 15A and an exposed portion 15B. As shown in FIG. 8, the covering portion 15A is connected to the third end surface 113 of the first die pad 10A, and is covered with the sealing resin 50. The covering portion 15A is bent when viewed along the first direction x. As shown in FIGS.
  • the seventh terminal lead 182 is electrically connected to the second main surface electrode 221 (source electrode) of the second semiconductor element 22 .
  • a voltage corresponding to the current flowing through the second main surface electrode 221 (source electrode) of the second semiconductor element 22 is applied to the seventh terminal lead 182.
  • the sixth terminal lead 181 includes a covering portion 181A and an exposed portion 181B.
  • the covering portion 181A is covered with a sealing resin 50.
  • the exposed portion 181B is connected to the covering portion 181A and exposed from the third side surface 55 of the sealing resin 50.
  • the exposed portion 181B extends away from the first die pad 10A in the second direction y. For example, tin plating is applied to the surface of the exposed portion 181B.
  • the second joint portion 313 is joined to the first seat surface 103 of the second die pad 10B.
  • the second joint 313 extends in the second direction y. At least a portion of the second joint portion 313 is accommodated in a region defined by the first seat surface 103 and the first upright surface 104 of the second die pad 10B.
  • the second joint portion 313 is connected to the first main body portion 311 .
  • the second joint portion 313 is located on the opposite side of the first joint portion 312 with the first main body portion 311 in between.
  • the fourth bonding portion 323 is bonded to the second main surface electrode 221 of the second semiconductor element 22.
  • the fourth joint portion 323 includes two second strip portions 323a. As shown in FIGS. 3 and 10, the two second strip portions 323a are located apart from each other in the second direction y. Each of the two second strip portions 323a has the first direction x as its longitudinal direction. The two second strip portions 323a are arranged parallel to each other in plan view. In the illustrated example, the end portion of the second main body portion 321 connected to the fourth joint portion 323 is bifurcated and connected to a corresponding one of the two second band portions 323a.
  • the end of the second main body part 321 connected to the fourth joint part 323 is not divided into two, and the fourth joint part 323 is one rectangular part (the two second strip parts 323a are (concatenated configuration).
  • the area of the fourth joint portion 323 (the total area of the two second strip portions 323a) in plan view is, for example, 10% or more and 100% or less of the area of the second main surface electrode 221 in plan view.
  • the semiconductor device A10 further includes a third bonding layer 35, as shown in FIGS. 9 and 14.
  • the third bonding layer 35 is interposed between the second seating surface 14C of the first terminal lead 14 and the third bonding portion 322.
  • the third bonding layer 35 bonds the covering portion 14A of the first terminal lead 14 and the third bonding portion 322.
  • the third bonding layer 35 has conductivity.
  • the third bonding layer 35 is, for example, solder.
  • the third bonding layer 35 may be made of sintered metal.
  • Each of the pair of first connecting members 41A, 41B and the pair of second connecting members 42A, 42B is, for example, a bonding wire.
  • Each composition of the pair of first connecting members 41A, 41B and the pair of second connecting members 42A, 42B includes gold.
  • the compositions of the pair of first connecting members 41A, 41B and the pair of second connecting members 42A, 42B may include copper or aluminum (Al).
  • the first connecting member 41A is joined to the main surface electrode 212 of the first semiconductor element 21 and the covering portion 171A of the fourth terminal lead 171.
  • the fourth terminal lead 171 is electrically connected to the main surface electrode 212 of the first semiconductor element 21 .
  • the first connecting member 41B is joined to the main surface electrode 222 of the second semiconductor element 22 and the covering portion 172A of the fifth terminal lead 172, as shown in FIG. Thereby, the fifth terminal lead 172 is electrically connected to the main surface electrode 222 of the second semiconductor element 22.
  • the second connecting member 42A is joined to the first main surface electrode 211 of the first semiconductor element 21 and the covering portion 181A of the sixth terminal lead 181.
  • the sixth terminal lead 181 is electrically connected to the first main surface electrode 211 of the first semiconductor element 21 .
  • the second connecting member 42B is joined to the second main surface electrode 221 of the second semiconductor element 22 and the covering portion 182A of the seventh terminal lead 182, as shown in FIG. Thereby, the seventh terminal lead 182 is electrically connected to the second main surface electrode 221 of the second semiconductor element 22 .
  • the semiconductor device A10 configured as above, as shown in FIG. 19, the first main surface electrode 211 of the first semiconductor element 21 and the back surface electrode 223 of the second semiconductor element 22 are electrically connected. There is. Therefore, the semiconductor device A10 forms a half-bridge circuit including two transistors (the first semiconductor element 21 and the second semiconductor element 22).
  • the functions and effects of the semiconductor device A10 according to the first embodiment are as follows.
  • the sealing resin 50 has a plurality of recesses 581.
  • Each of the plurality of recesses 581 is recessed from the main resin surface 51 in the thickness direction z.
  • the plurality of recesses 581 overlap the first die pad 10A in plan view.
  • the plurality of recesses 581 are marks formed by fixing the first die pad 10A with a plurality of pins during manufacturing of the semiconductor device A10. Therefore, since the first die pad 10A is held down by the plurality of pins during the manufacture of the semiconductor device A10, it is possible to suppress the first die pad 10A from swinging during the manufacture. Thereby, it is possible to suppress the generation of a gap between the back surface 102 of the first die pad 10A and the mold for forming the sealing resin 50, so it is possible to suppress the generation of resin burrs on the sealing resin 50. .
  • the sealing resin 50 has a plurality of recesses 582.
  • Each of the plurality of recesses 582 is recessed from the main resin surface 51 in the thickness direction z.
  • the plurality of recesses 582 overlap the second die pad 10B in plan view.
  • the plurality of recesses 582 are marks formed by fixing the second die pad 10B with a plurality of pins during manufacturing of the semiconductor device A10. Therefore, since the second die pad 10B is held down by the plurality of pins during the manufacture of the semiconductor device A10, it is possible to suppress the second die pad 10B from swinging during the manufacture. Thereby, it is possible to suppress the generation of a gap between the back surface 102 of the second die pad 10B and the mold for forming the sealing resin 50, so it is possible to suppress the generation of resin burrs on the sealing resin 50. .
  • the second conductive member 32 includes a second main body portion 321 that connects a third joint portion 322 and a fourth joint portion 323.
  • the second main body portion 321 is bent in plan view.
  • the second main body part 321 will be located at one of the four corners of the second die pad 10B in plan view. (the fourth corner end surface 124 of the second die pad 10B). In this case, it is difficult for the pins that fix the second die pad 10B to press the four corners of the second die pad 10B during manufacturing of the semiconductor device A10.
  • the semiconductor device A10 by bending the second body part 321, the second body part 321 can be bent at one of the four corners of the second die pad 10B (the fourth corner end face of the second die pad 10B) in plan view. 124) so that they do not overlap.
  • the semiconductor device A10 is preferable in terms of suppressing the swinging of the second die pad 10B during manufacturing.
  • the semiconductor device A10 by bending the second body portion 321 multiple times in plan view, the four corners of the second die pad 10B can be fixed with a plurality of pins during manufacturing as described above. It becomes possible to form the first main body part 311 linearly between the first semiconductor element 21 and the second semiconductor element 22.
  • the semiconductor device A11 differs from the semiconductor device A10 in the following points. That is, the first semiconductor element 21 of the semiconductor device A11 is not a transistor but a diode.
  • the first semiconductor element 21 of the semiconductor device A11 has a first main surface electrode 211 and a back surface electrode 213.
  • the first semiconductor element 21 of the semiconductor device A11 does not have the main surface electrode 212, as shown in FIG.
  • the first semiconductor element 21 of the semiconductor device A11 is a diode
  • the first main surface electrode 211 is, for example, an anode electrode
  • the back surface electrode 213 is, for example, a cathode electrode.
  • the semiconductor device A11 does not include either the first connection member 41A or the pair of second connection members 42A and 42B.
  • the fourth terminal lead 171, the sixth terminal lead 181, and the seventh terminal lead 182 are electrically connected to both the first semiconductor element 21 and the second semiconductor element 22, respectively. do not. Therefore, in the semiconductor device A11, the fourth terminal lead 171, the sixth terminal lead 181, and the seventh terminal lead 182 are each non-connect terminals.
  • the semiconductor device A11 does not include either of the pair of second connection members 42A, 42B, but in a configuration different from this example, the semiconductor device A11 has the same structure as the semiconductor device A10.
  • a pair of second connection members 42A and 42B may be provided.
  • FIGS. 22 and 23 show a semiconductor device A12 according to a second modification of the first embodiment.
  • the semiconductor device A12 differs from the semiconductor device A10 in the following points. That is, the second semiconductor element 22 of the semiconductor device A12 is not a transistor but a diode.
  • the second semiconductor element 22 of the semiconductor device A12 has a second main surface electrode 221 and a back surface electrode 223.
  • the second semiconductor element 22 of the semiconductor device A12 does not have the main surface electrode 222, as shown in FIG.
  • the second semiconductor element 22 of the semiconductor device A12 is a diode
  • the second main surface electrode 221 is, for example, an anode electrode
  • the back surface electrode 223 is, for example, a cathode electrode.
  • the semiconductor device A12 does not include either the first connection member 41B or the pair of second connection members 42A, 42B.
  • the fifth terminal lead 172, the sixth terminal lead 181, and the seventh terminal lead 182 are electrically connected to both the first semiconductor element 21 and the second semiconductor element 22, respectively. do not. Therefore, in the semiconductor device A12, the fifth terminal lead 172, the sixth terminal lead 181, and the seventh terminal lead 182 are each non-connect terminals.
  • the semiconductor device A12 does not include either of the pair of second connection members 42A, 42B, but in a configuration different from this example, the semiconductor device A12 has the same structure as the semiconductor device A10.
  • a pair of second connection members 42A and 42B may be provided.
  • the semiconductor device A12 As shown in FIG. 23, the first main surface electrode 211 (source electrode) of the first semiconductor element 21 and the back surface electrode 223 (cathode electrode) of the second semiconductor element 22 are electrically connected. ing.
  • the high voltage side is a transistor and the low voltage side is a diode.
  • the semiconductor device A12 is used, for example, as a step-down chopper circuit.
  • each of the first semiconductor element 21 and the second semiconductor element 22 of the semiconductor device A13 is a diode instead of a transistor.
  • the first semiconductor element 21 of the semiconductor device A13 has a first main surface electrode 211 and a back surface electrode 213.
  • the first semiconductor element 21 of the semiconductor device A13 does not have the main surface electrode 212, as shown in FIG.
  • the first semiconductor element 21 of the semiconductor device A13 is a diode
  • the first main surface electrode 211 is an anode electrode
  • the back surface electrode 213 is a cathode electrode.
  • the second semiconductor element 22 of the semiconductor device A13 has a second main surface electrode 221 and a back surface electrode 223.
  • the second semiconductor element 22 of the semiconductor device A13 does not have the main surface electrode 222, as shown in FIG.
  • the second semiconductor element 22 of the semiconductor device A13 is a diode
  • the second main surface electrode 221 is an anode electrode
  • the back surface electrode 223 is a cathode electrode.
  • the semiconductor device A13 does not include either the pair of first connecting members 41A, 41B and the pair of second connecting members 42A, 42B.
  • the fourth terminal lead 171, the fifth terminal lead 172, the sixth terminal lead 181, and the seventh terminal lead 182 are connected to the first semiconductor element 21 and the second semiconductor element, respectively. There is no conduction to any of 22. Therefore, in the semiconductor device A13, the fourth terminal lead 171, the fifth terminal lead 172, the sixth terminal lead 181, and the seventh terminal lead 182 are each non-connect terminals.
  • the semiconductor device A13 does not include either of the pair of second connection members 42A, 42B, but in a configuration different from this example, the semiconductor device A13 has the same structure as the semiconductor device A10.
  • a pair of second connection members 42A and 42B may be provided.
  • the semiconductor device A13 As shown in FIG. 25, the first main surface electrode 211 (anode electrode) of the first semiconductor element 21 and the back surface electrode 223 (cathode electrode) of the second semiconductor element 22 are electrically connected. ing. In the semiconductor device A13, both the high voltage side and the low voltage side with respect to the power supply voltage (DC voltage) applied between the first terminal lead 14 and the second terminal lead 15 are diodes.
  • the semiconductor device A13 is a diode bridge circuit.
  • the semiconductor device of the present disclosure can be used in four types of power conversion circuits (a bridge circuit using transistors, a boost type It can be configured as a chopper circuit, a step-down chopper circuit, or a bridge circuit using diodes.
  • the configurations of each terminal lead 13, sealing resin 50, etc. are common to each of the semiconductor devices A10 to A13. Therefore, the semiconductor device of the present disclosure can configure any of four types of power conversion circuits while keeping the package appearance the same.
  • the semiconductor device of the present disclosure even if each of the first semiconductor element 21 and the second semiconductor element 22 is a transistor or a diode, the configuration of each terminal lead 13 and the sealing resin 50 can be maintained as is. Can be used.
  • the semiconductor device of the present disclosure can use a common package structure for any of the four types of power conversion circuits described above, which is preferable for improving productivity.
  • the semiconductor device of the present disclosure is arranged such that the center of gravity of the first semiconductor element 21 overlaps the center of the first die pad 10A in plan view. This configuration is preferable in making the first conductive member 31 common.
  • the semiconductor device of the present disclosure is arranged such that the center of gravity of the second semiconductor element 22 overlaps the center of the second die pad 10B in plan view. This configuration is preferable in making the second conductive member 32 common.
  • FIG. 26 shows a semiconductor device A20 according to the second embodiment.
  • the semiconductor device A20 differs from the semiconductor device A10 in the following points. That is, the size of the first semiconductor element 21 of the semiconductor device A20 in plan view is smaller than the size of the first semiconductor element 21 of the semiconductor device A10 in plan view. Further, the size of the second semiconductor element 22 of the semiconductor device A20 in plan view is smaller than the size of the second semiconductor element 22 of the semiconductor device A10 in plan view.
  • the size of the first semiconductor element 21 in plan view is reduced compared to the semiconductor device A10, the size of the first joint portion 312 of the first conductive member 31 in plan view is reduced.
  • the area of the first joint portion 312 in plan view is equal to the area of the first main surface electrode 211 in plan view. For example, it is 10% or more and 100% or less of the area.
  • the width of the first main body portion 311 of the first conductive member 31 is the same as that of the semiconductor device A10.
  • the size of the fourth joint 323 of the second conductive member 32 in plan view is reduced.
  • the area of the fourth joint portion 323 in plan view is equal to the area of the second main surface electrode 221 in plan view. For example, it is 10% or more and 100% or less of the area.
  • the width of the second main body portion 321 of the second conductive member 32 is the same as that of the semiconductor device A10.
  • FIG. 27 shows a semiconductor device A21 according to a modification of the second embodiment.
  • the semiconductor device A21 differs from the semiconductor device A10 in the following points.
  • the size of the first semiconductor element 21 of the semiconductor device A21 in plan view is larger than the size of the first semiconductor element 21 of the semiconductor device A10 in plan view.
  • the size of the second semiconductor element 22 of the semiconductor device A21 in plan view is larger than the size of the second semiconductor element 22 of the semiconductor device A10 in plan view.
  • the size of the first semiconductor element 21 in plan view is enlarged compared to the semiconductor device A10, the size of the first joint portion 312 of the first conductive member 31 in plan view is enlarged.
  • the area of the first joint portion 312 in plan view is equal to the area of the first main surface electrode 211 in plan view. For example, it is 10% or more and 100% or less of the area.
  • the width of the first main body portion 311 of the first conductive member 31 is the same as that of the semiconductor device A10.
  • the size of the fourth joint 323 of the second conductive member 32 in plan view is enlarged.
  • the area of the fourth joint portion 323 in plan view is equal to the area of the second main surface electrode 221 in plan view. For example, it is 10% or more and 100% or less of the area.
  • the width of the second main body portion 321 of the second conductive member 32 is the same as that of the semiconductor device A10.
  • each of the semiconductor devices A20 and A21 according to the second embodiment and its modification, two semiconductor elements (the first semiconductor element 21 and the second semiconductor element 22) are formed by one sealing resin 50, similarly to the semiconductor device A10. 1 package. Therefore, similarly to the semiconductor device A10, each of the semiconductor devices A20 and A21 can reduce the mounting area on the circuit board on which the semiconductor devices A20 and A21 are mounted. In addition, each of the semiconductor devices A20 and A21 has the same configuration as the semiconductor device A10, and thus achieves the same effects as the semiconductor device A10.
  • the area of the first joint portion 312 in plan view (the total area of the two first strip portions 312a) is For example, it is 10% or more and 100% or less of the area of the first main surface electrode 211 in .
  • the size of the first joint portion 312 in plan view can be set to an appropriate size according to the size of the first semiconductor element 21 in plan view.
  • the area of the fourth joint portion 323 in plan view (the total area of the two second strip portions 323a) is, for example, 10 times the area of the second main surface electrode 221 in plan view. % or more and 100% or less. According to this configuration, the size of the fourth joint portion 323 in plan view can be set to an appropriate size according to the size of the second semiconductor element 22 in plan view.
  • the first conductive member 31 As understood from the semiconductor devices A10, A20, and A21, in the semiconductor device of the present disclosure, even if the first semiconductor element 21 and the second semiconductor element 22 have different sizes in plan view, the first conductive member 31 The first body part 311 of and the second body part 321 of the second conductive member 32 have the same width. When transporting the first conductive member 31, the first conductive member 31 may be held by a transporting hand or the like. In this case, by sandwiching the first main body part 311 in the width direction of the first main body part 311, adjustment of the conveying hand or the like becomes unnecessary. This means that even if the first semiconductor element 21 and the second semiconductor element 22 have different sizes in plan view, it is possible to use a common transport device such as a transport hand, which improves productivity. preferable.
  • FIG. 28 shows a semiconductor device A30 according to the third embodiment.
  • the semiconductor device A30 differs from the semiconductor device A10 in the following points. That is, the semiconductor device A30 includes a plurality of first semiconductor elements 21 and a plurality of second semiconductor elements 22. Note that in the example shown in FIG. 28, the semiconductor device A30 includes two first semiconductor elements 21 and two second semiconductor elements 22.
  • Each of the two first semiconductor elements 21 is mounted on the first die pad 10A.
  • Each of the two first semiconductor elements 21 is, for example, a transistor.
  • the two first semiconductor elements 21 are lined up along the second direction y.
  • the centers of gravity of the two first semiconductor elements 21 overlap the center of the first die pad 10A in plan view.
  • the two first semiconductor elements 21 have the same size in plan view, but may be different from each other.
  • the semiconductor device A30 includes two first semiconductor elements 21, it also differs from the semiconductor device A10 in the following points.
  • the first conductive member 31 of the semiconductor device A30 includes two first joints 312.
  • the two first joint parts 312 are connected to the first main body part 311.
  • the end portion of the first main body portion 311 that connects to the two first joint portions 312 is bifurcated.
  • Each of the two first bonding parts 312 is bonded to a corresponding one of the two first semiconductor elements 21 .
  • each first bonding portion 312 has a rectangular shape in plan view, but may be divided into two first strip portions 312a, similar to the first bonding portion 312 of the semiconductor device A10. .
  • the first connecting member 41A of the semiconductor device A30 covers the main surface electrode 212 of one first semiconductor element 21, the main surface electrode 212 of the other first semiconductor element 21, and the fourth terminal lead 171. 171A.
  • the first connecting member 41A is joined to the main surface electrode 212 of the first semiconductor element 21 on the side closer to the plurality of terminal leads 13 in the second direction y, of the two first semiconductor elements 21, for example by stitch joining. ing.
  • the second connection member 42A of the semiconductor device A30 connects the first main surface electrode 211 of one first semiconductor element 21, the first main surface electrode 211 of the other first semiconductor element 21, and the sixth terminal. It is joined to the covering portion 181A of the lead 181.
  • the second connecting member 42A is connected to the first main surface electrode 211 of the first semiconductor element 21 on the side closer to the plurality of terminal leads 13 in the second direction y, of the two first semiconductor elements 21, for example by stitch bonding. It is joined. Note that in the semiconductor device A30, the first connecting member 41A and the second connecting member 42A are formed first, but on the contrary, the second connecting member 42A may be formed first.
  • Each of the two second semiconductor elements 22 is mounted on the second die pad 10B.
  • Each of the two second semiconductor elements 22 is, for example, a transistor.
  • the two second semiconductor elements 22 are lined up along the second direction y.
  • the centers of gravity of the two second semiconductor elements 22 overlap the center of the second die pad 10B in plan view.
  • the two second semiconductor elements 22 have the same planar size, but may be different from each other.
  • the semiconductor device A30 includes two second semiconductor elements 22, it also differs from the semiconductor device A10 in the following points.
  • the second conductive member 32 of the semiconductor device A30 includes two fourth joints 323.
  • the two fourth joint parts 323 are connected to the second main body part 321.
  • the two fourth joint portions 323 are each connected to the third extension portion 321e.
  • Each of the two fourth bonding parts 323 is bonded to a corresponding one of the two second semiconductor elements 22 .
  • each fourth joint portion 323 has a rectangular shape in plan view, but may be divided into two second strip portions 323a, similar to the fourth joint portion 323 of the semiconductor device A10. .
  • the second connecting member 42B is connected to the second main surface electrode 221 of the second semiconductor element 22 on the side closer to the plurality of terminal leads 13 in the second direction y, of the two second semiconductor elements 22, for example by stitch bonding. It is joined. Note that in the semiconductor device A30, the first connecting member 41B and the second connecting member 42B are formed first, but on the contrary, the second connecting member 42B may be formed first.
  • the semiconductor device A30 may be configured as follows. That is, the semiconductor device A30 includes two first connection members 41A, and one of the first connection members 41A connects to the main surface electrode 212 of one of the first semiconductor elements 21 and the covering portion 171A of the fourth terminal lead 171. The other first connecting member 41A may be joined to the main surface electrode 212 of the other first semiconductor element 21 and the covering portion 171A of the fourth terminal lead 171. Similarly, the semiconductor device A30 includes two second connection members 42A, and one of the second connection members 42A connects the first main surface electrode 211 of the first semiconductor element 21 and the covering portion of the sixth terminal lead 181.
  • the semiconductor device A30 includes two first connection members 41B, and one of the first connection members 41B is connected to the main surface electrode 222 of one of the second semiconductor elements 22 and the covering portion 172A of the fifth terminal lead 172.
  • the other first connecting member 41B may be joined to the main surface electrode 222 of the other second semiconductor element 22 and the covering portion 172A of the fifth terminal lead 172.
  • the semiconductor device A30 includes two second connection members 42B, and one of the second connection members 42B connects the second main surface electrode 221 of one of the second semiconductor elements 22 and the covering portion 182A of the seventh terminal lead 182.
  • the other second connecting member 42B may be joined to the second main surface electrode 221 of the other second semiconductor element 22 and the covering portion 182A of the seventh terminal lead 182.
  • the semiconductor device A30 In the semiconductor device A30 according to the third embodiment, two semiconductor elements (the first semiconductor element 21 and the second semiconductor element 22) are packaged into one package using one sealing resin 50, similarly to the semiconductor device A10. Therefore, like the semiconductor device A10, the semiconductor device A30 can reduce the mounting area on the circuit board on which the semiconductor device A30 is mounted. In addition, the semiconductor device A30 has the same configuration as the semiconductor device A10, and thus achieves the same effects as the semiconductor device A10.
  • the semiconductor device A40 differs from the semiconductor device A10 in the following points. That is, the semiconductor device A40 further includes a support substrate 6.
  • the support substrate 6 supports the first die pad 10A and the second die pad 10B.
  • the support substrate 6 is, for example, a DBC (Direct Bonded Copper) substrate or an AMB (Active Matal Brazing) substrate, but is not limited thereto.
  • Support substrate 6 includes an insulating layer 61 and a pair of metal layers 62 and 63.
  • the metal layer 62 is formed on the upper surface of the insulating layer 61 (the surface facing upward in the thickness direction z).
  • Metal layer 62 includes, for example, copper or a copper alloy. Note that the metal layer 62 may contain other metals such as gold, silver, and aluminum in addition to copper or a copper alloy. As shown in FIGS. 29 and 30, metal layer 62 includes two pad portions 621 and 622.
  • the two pad parts 621 and 622 are spaced apart from each other.
  • the two pad parts 621 and 622 are arranged along the first direction x.
  • the first die pad 10A is bonded to the pad portion 621 with a bonding material 69.
  • the second die pad 10B is bonded to the pad portion 622 with a bonding material 69.
  • Each bonding material 69 is a conductive bonding material such as solder or sintered metal. Unlike this example, each bonding material 69 may be an insulating bonding material.
  • the pad portion 621 and the first die pad 10A and the pad portion 622 and the second die pad 10B may be bonded together by solid phase diffusion bonding, for example, instead of being bonded with the bonding material 69.
  • the pad portion 621 is one size larger than the first die pad 10A
  • the pad portion 622 is one size larger than the second die pad 10B.
  • metal layer 63 is formed on the lower surface of the insulating layer 61 (the surface facing downward in the thickness direction z). Like metal layer 62, metal layer 63 includes, for example, copper or a copper alloy. Note that the metal layer 63 may contain other metals such as gold, silver, and aluminum in addition to copper or a copper alloy. Metal layer 63 includes two pad portions 631 and 632.
  • the two pad parts 631 and 632 are spaced apart from each other.
  • the two pad parts 631 and 632 are arranged along the first direction x.
  • Pad portion 631 overlaps pad portion 621 in plan view.
  • Pad portion 632 overlaps pad portion 622 in plan view.
  • the two pad portions 631 and 632 (metal layer 63) are exposed on the resin back surface 52.
  • the lower surfaces of the two pad portions 631 and 632 are flush with the resin back surface 52; however, unlike this example, , may be located above in the thickness direction z, or may be located below in the thickness direction z.
  • the thickness (dimension in the thickness direction z) of the sealing resin 50 of the semiconductor device A40 is approximately the same as the thickness (dimension in the thickness direction z) of the sealing resin 50 of the semiconductor device A10.
  • the respective thicknesses (dimensions in the thickness direction z) of the first die pad 10A and the second die pad 10B of the semiconductor device A40 are the same as those of the first die pad 10A and the second die pad 10B of the semiconductor device A10. dimension in direction z).
  • the sum of the thickness of the first die pad 10A (second die pad 10B) and the thickness of the support substrate 6 in the semiconductor device A40 corresponds to the thickness of the first die pad 10A (second die pad 10B) in the semiconductor device A10.
  • the semiconductor device A40 In the semiconductor device A40 according to the fourth embodiment, two semiconductor elements (the first semiconductor element 21 and the second semiconductor element 22) are packaged into one package using one sealing resin 50, similarly to the semiconductor device A10. Therefore, like the semiconductor device A10, the semiconductor device A40 can reduce the mounting area on the circuit board on which the semiconductor device A40 is mounted. In addition, the semiconductor device A40 has the same configuration as the semiconductor device A10, and has the same effects as the semiconductor device A10.
  • the semiconductor device A40 includes a support substrate 6 that supports the first die pad 10A and the second die pad 10B.
  • Support substrate 6 includes an insulating layer 61 made of ceramics.
  • the first semiconductor element 21 and the second semiconductor element 22 generate heat as the first semiconductor element 21 and the second semiconductor element 22 are driven. This heat generation thermally expands the first die pad 10A and the second die pad 10B.
  • Such thermal expansion applies thermal stress to other components (eg, the first semiconductor element 21 and the second semiconductor element 22).
  • the thermal expansion of the first die pad 10A and the second die pad 10B is limited by the support substrate 6 (particularly the insulating layer 61 made of ceramic).
  • thermal stress caused by thermal expansion of the first die pad 10A and the second die pad 10B can be alleviated.
  • thermal stress applied to the first semiconductor element 21 and the second semiconductor element 22 is relaxed, and internal destruction (for example, internal interface peeling) of the first semiconductor element 21 and the second semiconductor element 22 is suppressed. Ru.
  • the respective thicknesses (dimensions in the thickness direction z) of the first die pad 10A and the second die pad 10B are equal to the respective thicknesses (dimensions in the thickness direction z) of the first die pad 10A and the second die pad 10B of the semiconductor device A10. dimensions).
  • the thermal expansion of the first die pad 10A and the second die pad 10B is suppressed compared to the semiconductor device A10. Therefore, the semiconductor device A40 can alleviate the thermal stress caused by the thermal expansion of the first die pad 10A and the second die pad 10B more than the semiconductor device A10.
  • FIG. 32 shows a semiconductor device A42 according to a second modification of the fourth embodiment.
  • the semiconductor device A42 differs from the semiconductor device A40 in the following points. The point is that the insulating layer 61 is separated into two plate members 611 and 612. A pad portion 621 is formed on the upper surface of the plate material 611, and a pad portion 631 is formed on the lower surface of the plate material 611. A pad portion 622 is formed on the upper surface of the plate material 612, and a pad portion 632 is formed on the lower surface of the plate material 612.
  • a first die pad 10A and a second die pad 10B are individually bonded to two DBC substrates or AMB substrates.
  • each of the semiconductor devices A41 and A42 can reduce the mounting area on the circuit board on which the semiconductor devices A41 and A42 are mounted.
  • each of the semiconductor devices A41 and A42 has the same configuration as the semiconductor device A40, and thus achieves the same effects as the semiconductor device A40.
  • the package structure of the semiconductor device of the present disclosure is not limited to those exemplified in the first to fourth embodiments (including variations thereof).
  • the semiconductor device of the present disclosure can also be applied to other TO (Transistor Outline) packages.
  • each of the semiconductor devices A10, A20, A30, and A40 according to the first to fourth embodiments is an expanded package structure called TO-247, but TO-220, TO-252 , TO263, etc. may be an extension of other package structures.
  • the semiconductor device of the present disclosure can package a plurality of semiconductor elements (first semiconductor element 21 and second semiconductor element 22) with one sealing resin 50 while maintaining an appearance similar to a conventional TO package. enable.
  • the semiconductor device according to the present disclosure is not limited to the embodiments described above.
  • the specific configuration of each part of the semiconductor device of the present disclosure can be modified in various ways.
  • the present disclosure includes the embodiments described in the appendix below. Additional note 1.
  • a first semiconductor element having a first main surface facing one side in the thickness direction and a first main surface electrode disposed on the first main surface;
  • a second semiconductor element having a second main surface facing in the same direction as the first main surface and a second main surface electrode disposed on the second main surface; a first die pad on which the first semiconductor element is mounted; a second die pad arranged on one side of the first die pad in a first direction perpendicular to the thickness direction, and on which the second semiconductor element is mounted; a first terminal lead spaced apart from the first die pad and the second die pad;
  • a first conductive member that electrically connects the first main surface electrode and the second die pad;
  • a second conductive member that electrically connects the second main surface electrode and the first terminal lead;
  • the first conductive member connects a first joint part joined to the first main surface electrode, a second joint part joined to the second die pad, and a first joint part and the second joint part.
  • the semiconductor device according to supplementary note 1 including a first main body portion that connects the semiconductor device.
  • Appendix 3. The semiconductor device according to appendix 2, wherein the first main body portion extends along the first direction when viewed in the thickness direction.
  • Appendix 4. Supplementary Note 2 or 3, wherein the area of the first joint when viewed in the thickness direction is 10% or more and 100% or less of the area of the first main surface electrode when viewed in the thickness direction.
  • the first joint portion includes two first strip portions, The semiconductor device according to any one of appendices 2 to 4, wherein an edge of the first body portion that is connected to the first joint portion is bifurcated and connected to the two first band portions, respectively.
  • the second conductive member includes a third joint part joined to the first terminal lead, a fourth joint part joined to the second main surface electrode, and the third joint part and the fourth joint part. and a second main body portion that connects the semiconductor device according to any one of Supplementary Notes 1 to 5.
  • Appendix 7. The semiconductor device according to appendix 6, wherein the second main body portion is bent when viewed in the thickness direction.
  • the second main body part has a first extending part that extends from the first base end in a second direction perpendicular to the thickness direction and the first direction, with an edge connected to the third joint part as a first base end. a second extending portion extending in the first direction from the second base end with the edge connected to the first extending portion as a second base end; and a third extending portion extending from the second base end in the first direction; a third extending portion extending in the second direction from the third base end as a base end,
  • the fourth joint portion includes two second strip portions, The semiconductor device according to any one of appendices 6 to 9, wherein an edge of the second main body portion that is connected to the fourth joint portion is bifurcated and connected to the two second band portions, respectively.
  • Appendix 11 a second terminal lead connected to the first die pad; further comprising a third terminal lead connected to the second die pad, The semiconductor device according to any one of appendices 1 to 10, wherein the first terminal lead, the second terminal lead, and the third terminal lead are spaced apart from each other.
  • Appendix 12 The semiconductor device according to attachment 11, wherein the first terminal lead is located between the second terminal lead and the third terminal lead in the first direction. Appendix 13. Further comprising a fourth terminal lead, a fifth terminal lead, a sixth terminal lead, and a seventh terminal lead, each spaced apart from the first terminal lead, the second terminal lead, and the third terminal lead, and spaced apart from each other. , the semiconductor device according to appendix 11 or appendix 12. Appendix 14.
  • the sealing resin has a resin main surface facing in the same direction as the first main surface, and at least one recess depressed from the resin main surface,
  • Appendix 15. The semiconductor device according to appendix 14, wherein each of the at least one recessed portion does not overlap with either the first conductive member or the second conductive member when viewed in the thickness direction.
  • Appendix 16 The semiconductor device according to any one of appendices 1 to 15, wherein the center of gravity of the first semiconductor element overlaps the center of the first die pad when viewed in the thickness direction. Appendix 17.
  • the semiconductor device according to any one of attachments 1 to 16, wherein the center of gravity of the second semiconductor element overlaps the center of the second die pad when viewed in the thickness direction.
  • Appendix 18. further comprising a support substrate that supports the first die pad and the second die pad, The first die pad and the second die pad are supported in the thickness direction by the supporting substrate from a side opposite to a side on which the first semiconductor element and the second semiconductor element are mounted,
  • Appendix 19 The first semiconductor element is either a transistor or a diode,
  • the semiconductor device according to any one of attachments 1 to 18, wherein the second semiconductor element is either a transistor or a diode.
  • A10 to A13, A20, A21, A30, A40 to A42 Semiconductor device 10A: First die pad 10B: Second die pad 101: Main surface 102: Back surface 103: First seating surface 104: First upright surface 109: Trace 111: First end face 112: Second end face 113: Third end face 114: Fourth end face 121: First corner end face 122: Second corner end face 123: Third corner end face 124: Fourth corner end face 13: Terminal lead 14: First terminal lead 14A: Covering portion 14B: Exposed portion 14C: Second seating surface 14D: Second upright surface 15: Second terminal lead 15A: Covering portion 15B: Exposed portion 16: Third terminal lead 16A: Covering portion 16B: Exposed part 171: Fourth terminal lead 171A: Covering part 171B: Exposed part 172: Fifth terminal lead 172A: Covering part 172B: Exposed part 181: Sixth terminal lead 181A: Covering part 181B: Exposed part 182: Seventh Terminal lead 182A:

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Abstract

This semiconductor device comprises: a first semiconductor element having a first main surface directed in the thickness direction and a first main surface electrode disposed on the first main surface; a second semiconductor element having a second main surface directed in the same direction as that of the first main surface and a second main surface electrode disposed on the second main surface; a first die pad on which the first semiconductor element is mounted; a second die pad on which the second semiconductor element is mounted; a first terminal lead separated from the first and second die pads; a first conductive member that electrically connects the first main surface electrode to the second die pad; a second conductive member that electrically connects the second main surface electrode to the first terminal lead; and a sealing resin that covers the first and second semiconductor elements.

Description

半導体装置semiconductor equipment
　本開示は、半導体装置に関する。 The present disclosure relates to a semiconductor device.
　従来、ダイオードまたはトランジスタなどの半導体素子を樹脂パッケージで覆った半導体装置が知られている（たとえば特許文献１）。特許文献１に記載の半導体装置は、半導体素子と、リードフレームと、樹脂パッケージとを備える。リードフレームは、複数のリードを含んでおり、複数のリードのうちの１つは、ダイボンディングパッドを含む。半導体素子は、ダイボンディングパッドに搭載されている。樹脂パッケージは、半導体素子を覆うとともに、複数のリードの一部ずつを覆っている。各リードにおいて、樹脂パッケージから露出する部分は、半導体装置の端子である。 Conventionally, semiconductor devices are known in which semiconductor elements such as diodes or transistors are covered with resin packages (for example, Patent Document 1). The semiconductor device described in Patent Document 1 includes a semiconductor element, a lead frame, and a resin package. The lead frame includes a plurality of leads, one of which includes a die bonding pad. A semiconductor element is mounted on a die bonding pad. The resin package covers the semiconductor element and also partially covers each of the plurality of leads. The portion of each lead exposed from the resin package is a terminal of the semiconductor device.
　このような半導体装置は、たとえば電子機器などの回路基板に実装され、電源回路に用いられている。当該電源回路には、たとえばハーフブリッジ回路およびチョッパー回路などのＤＣ／ＤＣコンバータがある。特許文献１に記載の半導体装置を、たとえばハーフブリッジ回路に用いる場合、２つの半導体装置を回路基板に実装する。 Such a semiconductor device is mounted on a circuit board of, for example, an electronic device and used in a power supply circuit. The power supply circuit includes, for example, a DC/DC converter such as a half bridge circuit and a chopper circuit. When the semiconductor device described in Patent Document 1 is used, for example, in a half-bridge circuit, two semiconductor devices are mounted on a circuit board.
特開２０１１－８２５２３号公報Japanese Patent Application Publication No. 2011-82523
　近年、電子機器の小型化に伴い、電子機器に搭載される回路基板の小型化が求められる。しかしながら、先述のように２つの半導体装置を回路基板に実装する構成では、回路基板への実装面積が大きくなるので、回路基板の小型化を図るのは容易ではない。 In recent years, as electronic devices have become smaller, there has been a demand for smaller circuit boards mounted on electronic devices. However, in the configuration in which two semiconductor devices are mounted on a circuit board as described above, the mounting area on the circuit board becomes large, so it is not easy to reduce the size of the circuit board.
　本開示は、従来よりも改良が施された半導体装置を提供することを一の課題とする。特に本開示は、上記事情に鑑み、回路基板への実装面積を削減することが可能な半導体装置を提供することを一の課題とする。 An object of the present disclosure is to provide a semiconductor device that is improved over conventional ones. In particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that can reduce the mounting area on a circuit board.
　本開示の第１の側面によって提供される半導体装置は、厚さ方向の一方を向く第１主面および前記第１主面に配置された第１主面電極を有する第１半導体素子と、前記第１主面と同じ方向を向く第２主面および前記第２主面に配置された第２主面電極を有する第２半導体素子と、前記第１半導体素子が搭載された第１ダイパッドと、前記第１ダイパッドに対して前記厚さ方向に直交する第１方向の一方側に配置され、前記第２半導体素子が搭載された第２ダイパッドと、前記第１ダイパッドおよび前記第２ダイパッドから離間する第１端子リードと、前記第１主面電極と前記第２ダイパッドとを電気的に接続する第１導通部材と、前記第２主面電極と前記第１端子リードとを電気的に接続する第２導通部材と、前記第１半導体素子および前記第２半導体素子を覆う封止樹脂と、を備える。 A semiconductor device provided by a first aspect of the present disclosure includes a first semiconductor element having a first main surface facing one side in the thickness direction and a first main surface electrode disposed on the first main surface; a second semiconductor element having a second main surface facing in the same direction as the first main surface and a second main surface electrode disposed on the second main surface; a first die pad on which the first semiconductor element is mounted; A second die pad, which is arranged on one side of the first die pad in a first direction perpendicular to the thickness direction and on which the second semiconductor element is mounted, is spaced apart from the first die pad and the second die pad. A first terminal lead, a first conductive member that electrically connects the first main surface electrode and the second die pad, and a first conductive member that electrically connects the second main surface electrode and the first terminal lead. and a sealing resin that covers the first semiconductor element and the second semiconductor element.
　上記構成によれば、回路基板に対する半導体装置の実装面積を削減することが可能となる。 According to the above configuration, it is possible to reduce the mounting area of the semiconductor device on the circuit board.
図１は、第１実施形態にかかる半導体装置を示す斜視図である。FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment. 図２は、第１実施形態にかかる半導体装置を示す平面図である。FIG. 2 is a plan view showing the semiconductor device according to the first embodiment. 図３は、図２の平面図において、封止樹脂を想像線で示した図である。FIG. 3 is a diagram showing the sealing resin with imaginary lines in the plan view of FIG. 2. 図４は、図３の一部を拡大した部分拡大図である。FIG. 4 is a partially enlarged view of FIG. 3. 図５は、第１実施形態にかかる半導体装置を示す底面図である。FIG. 5 is a bottom view showing the semiconductor device according to the first embodiment. 図６は、第１実施形態にかかる半導体装置を示す正面図である。FIG. 6 is a front view showing the semiconductor device according to the first embodiment. 図７は、第１実施形態にかかる半導体装置を示す右側面図である。FIG. 7 is a right side view showing the semiconductor device according to the first embodiment. 図８は、図７の一部を拡大した部分拡大図であって、封止樹脂を想像線で示した図である。FIG. 8 is a partially enlarged view of FIG. 7, showing the sealing resin with imaginary lines. 図９は、図３のＩＸ－ＩＸ線に沿う断面図である。FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 3. 図１０は、図３のＸ－Ｘ線に沿う断面図である。FIG. 10 is a sectional view taken along line XX in FIG. 3. 図１１は、図９の一部を拡大した部分拡大図である。FIG. 11 is a partially enlarged view of FIG. 9 . 図１２は、図９の一部を拡大した部分拡大図である。FIG. 12 is a partially enlarged view of FIG. 9 . 図１３は、図９の一部を拡大した部分拡大図である。FIG. 13 is a partially enlarged view of FIG. 9 . 図１４は、図１０の一部を拡大した部分拡大図である。FIG. 14 is a partially enlarged view of FIG. 10. 図１５は、図３の一部を拡大した部分拡大図である。FIG. 15 is a partial enlarged view of a part of FIG. 3. 図１６は、図３の一部を拡大した部分拡大図である。FIG. 16 is a partially enlarged view of FIG. 3. 図１７は、図３の一部を拡大した部分拡大図である。FIG. 17 is a partially enlarged view of FIG. 3. 図１８は、図３の一部を拡大した部分拡大図である。FIG. 18 is a partially enlarged view of FIG. 3. 図１９は、第１実施形態にかかる半導体装置の回路構成例を示す図である。FIG. 19 is a diagram showing an example of the circuit configuration of the semiconductor device according to the first embodiment. 図２０は、第１実施形態の第１変形例にかかる半導体装置を示す平面図であって、封止樹脂を想像線で示した図である。FIG. 20 is a plan view showing a semiconductor device according to a first modification of the first embodiment, in which a sealing resin is shown with imaginary lines. 図２１は、第１実施形態の第１変形例にかかる半導体装置の回路構成例を示す図である。FIG. 21 is a diagram illustrating an example of a circuit configuration of a semiconductor device according to a first modification of the first embodiment. 図２２は、第１実施形態の第２変形例にかかる半導体装置を示す平面図であって、封止樹脂を想像線で示した図である。FIG. 22 is a plan view showing a semiconductor device according to a second modification of the first embodiment, in which the sealing resin is shown with imaginary lines. 図２３は、第１実施形態の第２変形例にかかる半導体装置の回路構成例を示す図である。FIG. 23 is a diagram illustrating an example of a circuit configuration of a semiconductor device according to a second modification of the first embodiment. 図２４は、第１実施形態の第３変形例にかかる半導体装置を示す平面図であって、封止樹脂を想像線で示した図である。FIG. 24 is a plan view showing a semiconductor device according to a third modification of the first embodiment, in which the sealing resin is shown with imaginary lines. 図２５は、第１実施形態の第３変形例にかかる半導体装置の回路構成例を示す図である。FIG. 25 is a diagram illustrating an example of a circuit configuration of a semiconductor device according to a third modification of the first embodiment. 図２６は、第２実施形態にかかる半導体装置を示す平面図であって、封止樹脂を想像線で示した図である。FIG. 26 is a plan view showing the semiconductor device according to the second embodiment, in which the sealing resin is shown with imaginary lines. 図２７は、第２実施形態の第１変形例にかかる半導体装置を示す平面図であって、封止樹脂を想像線で示した図である。FIG. 27 is a plan view showing a semiconductor device according to a first modification of the second embodiment, in which a sealing resin is shown with imaginary lines. 図２８は、第３実施形態にかかる半導体装置を示す平面図であって、封止樹脂を想像線で示した図である。FIG. 28 is a plan view showing the semiconductor device according to the third embodiment, in which the sealing resin is shown with imaginary lines. 図２９は、第４実施形態にかかる半導体装置を示す平面図であって、封止樹脂を想像線で示した図である。FIG. 29 is a plan view showing the semiconductor device according to the fourth embodiment, in which the sealing resin is shown with imaginary lines. 図３０は、図２９のＸＸＸ－ＸＸＸ線に沿う断面図であって、図９の断面に対応する。30 is a cross-sectional view taken along the line XXX-XXX in FIG. 29, and corresponds to the cross-section in FIG. 9. 図３１は、第４実施形態の第１変形例にかかる半導体装置を示す断面図であって、図３０の断面に対応する。FIG. 31 is a cross-sectional view showing a semiconductor device according to a first modification of the fourth embodiment, and corresponds to the cross-section of FIG. 30. 図３２は、第４実施形態の第２変形例にかかる半導体装置を示す断面図であって、図３０の断面に対応する。FIG. 32 is a cross-sectional view showing a semiconductor device according to a second modification of the fourth embodiment, and corresponds to the cross-section of FIG. 30.
　本開示の半導体装置の好ましい実施の形態について、図面を参照して、以下に説明する。以下では、同一あるいは類似の構成要素に、同じ符号を付して、重複する説明を省略する。本開示における「第１」、「第２」、「第３」等の用語は、単にラベルとして用いたものであり、必ずしもそれらの対象物に順列を付することを意図していない。 Preferred embodiments of the semiconductor device of the present disclosure will be described below with reference to the drawings. Hereinafter, the same or similar components will be denoted by the same reference numerals, and redundant explanation will be omitted. Terms such as "first", "second", "third", etc. in this disclosure are used merely as labels and are not necessarily intended to attach a permutation to those objects.
　本開示において、「ある物Ａがある物Ｂに形成されている」および「ある物Ａがある物Ｂ（の）上に形成されている」とは、特段の断りのない限り、「ある物Ａがある物Ｂに直接形成されていること」、および、「ある物Ａとある物Ｂとの間に他の物を介在させつつ、ある物Ａがある物Ｂに形成されていること」を含む。同様に、「ある物Ａがある物Ｂに配置されている」および「ある物Ａがある物Ｂ（の）上に配置されている」とは、特段の断りのない限り、「ある物Ａがある物Ｂに直接配置されていること」、および、「ある物Ａとある物Ｂとの間に他の物を介在させつつ、ある物Ａがある物Ｂに配置されていること」を含む。同様に、「ある物Ａがある物Ｂ（の）上に位置している」とは、特段の断りのない限り、「ある物Ａがある物Ｂに接して、ある物Ａがある物Ｂ（の）上に位置していること」、および、「ある物Ａとある物Ｂとの間に他の物が介在しつつ、ある物Ａがある物Ｂ（の）上に位置していること」を含む。また、「ある方向に見てある物Ａがある物Ｂに重なる」とは、特段の断りのない限り、「ある物Ａがある物Ｂのすべてに重なること」、および、「ある物Ａがある物Ｂの一部に重なること」を含む。また、「ある物Ａ（の材料）がある材料Ｃを含む」とは、「ある物Ａ（の材料）がある材料Ｃからなる場合」、および、「ある物Ａ（の材料）の主成分がある材料Ｃである場合」を含む。 In the present disclosure, "a thing A is formed on a thing B" and "a thing A is formed on a thing B" mean "a thing A is formed on a thing B" unless otherwise specified. "A is formed directly on something B," and "A thing A is formed on something B, with another thing interposed between them." including. Similarly, "a certain thing A is placed on a certain thing B" and "a certain thing A is placed on a certain thing B" are used as "a certain thing A is placed on a certain thing B" unless otherwise specified. ``It is placed directly on something B,'' and ``A thing A is placed on something B, with another thing interposed between them.'' include. Similarly, "an object A is located on an object B" means, unless otherwise specified, "an object A is in contact with an object B, and an object A is located on an object B". ``Being located on (above) something'' and ``A thing A being located on (above) a thing B while another thing is intervening between the thing A and the thing B.'' Including "thing". In addition, "an object A overlaps an object B when viewed in a certain direction" means, unless otherwise specified, "an object A overlaps all of an object B" and "a certain object A overlaps an object B". This includes "overlapping a part of something B." In addition, "a certain thing A (the material of the thing) includes a certain material C" means "a case where the thing A (the material of the thing A) consists of a certain material C" and "the main component of the thing A (the material of the thing)". "is a certain material C".
　図１～図１９は、第１実施形態にかかる半導体装置Ａ１０を示している。半導体装置Ａ１０は、第１ダイパッド１０Ａ、第２ダイパッド１０Ｂ、複数の端子リード１３、第１半導体素子２１、第２半導体素子２２、第１導通部材３１、第２導通部材３２、一対の第１接続部材４１Ａ，４１Ｂ、一対の第２接続部材４２Ａ，４２Ｂ、および封止樹脂５０を備える。複数の端子リード１３は、第１端子リード１４、第２端子リード１５、第３端子リード１６、第４端子リード１７１、第５端子リード１７２、第６端子リード１８１および第７端子リード１８２を含む。 1 to 19 show a semiconductor device A10 according to the first embodiment. The semiconductor device A10 includes a first die pad 10A, a second die pad 10B, a plurality of terminal leads 13, a first semiconductor element 21, a second semiconductor element 22, a first conductive member 31, a second conductive member 32, and a pair of first connections. It includes members 41A and 41B, a pair of second connection members 42A and 42B, and a sealing resin 50. The plurality of terminal leads 13 include a first terminal lead 14, a second terminal lead 15, a third terminal lead 16, a fourth terminal lead 171, a fifth terminal lead 172, a sixth terminal lead 181, and a seventh terminal lead 182. .
　説明の便宜上、半導体装置Ａ１０の厚さ方向を「厚さ方向ｚ」という。以下の説明では、厚さ方向ｚの一方を上方といい、他方を下方ということがある。なお、「上」、「下」、「上方」、「下方」、「上面」および「下面」などの記載は、厚さ方向ｚにおける各部品等の相対的位置関係を示すものであり、必ずしも重力方向との関係を規定する用語ではない。また、「平面視」とは、厚さ方向ｚに見たときをいう。厚さ方向ｚに対して直交する１つの方向を「第１方向ｘ」という。厚さ方向ｚおよび第１方向ｘに直交する方向を「第２方向ｙ」という。 For convenience of explanation, the thickness direction of the semiconductor device A10 will be referred to as the "thickness direction z." In the following description, one side of the thickness direction z may be referred to as upper side, and the other side may be referred to as lower side. Note that descriptions such as "upper", "lower", "upper", "lower", "upper surface", and "lower surface" indicate the relative positional relationship of each component etc. in the thickness direction z, and do not necessarily mean It is not a term that defines the relationship with the direction of gravity. Moreover, "planar view" refers to when viewed in the thickness direction z. One direction perpendicular to the thickness direction z is referred to as a "first direction x." A direction perpendicular to the thickness direction z and the first direction x is referred to as a "second direction y."
　半導体装置Ａ１０は、複数の端子リード１３のうちの第１端子リード１４および第２端子リード１５に印加された直流の電源電圧を、第１半導体素子２１および第２半導体素子２２により交流電圧に変換する。変換された交流電圧は、複数の端子リード１３のうちの第３端子リード１６からモータなどの電力供給対象に入力される。半導体装置Ａ１０は、たとえばインバータといった電力変換回路に使用される。 The semiconductor device A10 converts a DC power supply voltage applied to a first terminal lead 14 and a second terminal lead 15 of the plurality of terminal leads 13 into an AC voltage by a first semiconductor element 21 and a second semiconductor element 22. do. The converted AC voltage is inputted from the third terminal lead 16 of the plurality of terminal leads 13 to a power supply target such as a motor. The semiconductor device A10 is used, for example, in a power conversion circuit such as an inverter.
　第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂは、図３および図９に示すように、第１方向ｘにおいて互いに離れて位置する。第１ダイパッド１０Ａは、第２ダイパッド１０Ｂ、および複数の端子リード１３とともに、同一のリードフレームから構成されている。当該リードフレームは、銅（Ｃｕ）、または銅合金である。このため、第１ダイパッド１０Ａ、第２ダイパッド１０Ｂ、および複数の端子リード１３の組成は、銅を含む。第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂの各々は、たとえば平面視において矩形状である。 The first die pad 10A and the second die pad 10B are located apart from each other in the first direction x, as shown in FIGS. 3 and 9. The first die pad 10A, along with the second die pad 10B and the plurality of terminal leads 13, are configured from the same lead frame. The lead frame is made of copper (Cu) or a copper alloy. Therefore, the compositions of the first die pad 10A, the second die pad 10B, and the plurality of terminal leads 13 include copper. Each of the first die pad 10A and the second die pad 10B has a rectangular shape in plan view, for example.
　第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂはそれぞれ、主面１０１および裏面１０２を有する。以下で説明する主面１０１および裏面１０２は、特段の断りがない限り、第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂで共通する。主面１０１は、厚さ方向ｚ（上方）を向く。主面１０１は、封止樹脂５０に覆われている。第１ダイパッド１０Ａの主面１０１には、第１半導体素子２１が搭載されている。第１ダイパッド１０Ａの裏面１０２は、厚さ方向ｚにおいて第１半導体素子２１が位置する側とは反対側を向く。第２ダイパッド１０Ｂの主面１０１には、第２半導体素子２２が搭載されている。第２ダイパッド１０Ｂの裏面１０２は、厚さ方向ｚにおいて第２半導体素子２２が位置する側とは反対側を向く。裏面１０２は、封止樹脂５０から露出している。裏面１０２には、たとえば錫（Ｓｎ）めっきが施されている。 The first die pad 10A and the second die pad 10B each have a main surface 101 and a back surface 102. The main surface 101 and the back surface 102 described below are common to the first die pad 10A and the second die pad 10B unless otherwise specified. The main surface 101 faces in the thickness direction z (upward). The main surface 101 is covered with a sealing resin 50. A first semiconductor element 21 is mounted on the main surface 101 of the first die pad 10A. The back surface 102 of the first die pad 10A faces the opposite side to the side where the first semiconductor element 21 is located in the thickness direction z. A second semiconductor element 22 is mounted on the main surface 101 of the second die pad 10B. The back surface 102 of the second die pad 10B faces the opposite side to the side where the second semiconductor element 22 is located in the thickness direction z. The back surface 102 is exposed from the sealing resin 50. The back surface 102 is plated with tin (Sn), for example.
　封止樹脂５０は、図３および図８～図１０に示すように、第１半導体素子２１と、第２半導体素子２２と、第１導通部材３１と、第２導通部材３２と、第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂの各々の少なくとも一部ずつとを覆う。さらに封止樹脂５０は、複数の端子リード１３の各々の一部を覆う。封止樹脂５０は、電気絶縁性を有する。封止樹脂５０は、たとえば黒色のエポキシ樹脂を含む。図２に示すように、第１方向ｘにおける封止樹脂５０の寸法Ｌ１は、第２方向ｙにおける封止樹脂５０の寸法Ｌ２よりも長い。封止樹脂５０は、樹脂主面５１、樹脂裏面５２、一対の第１側面５３、第２側面５４、第３側面５５、複数の凹部５６、溝部５７および複数の凹部５８１，５８２を有する。 As shown in FIG. 3 and FIGS. 8 to 10, the sealing resin 50 connects the first semiconductor element 21, the second semiconductor element 22, the first conductive member 31, the second conductive member 32, and the first die pad. 10A and at least a portion of each of second die pad 10B. Further, the sealing resin 50 covers a portion of each of the plurality of terminal leads 13. The sealing resin 50 has electrical insulation properties. The sealing resin 50 includes, for example, black epoxy resin. As shown in FIG. 2, a dimension L1 of the sealing resin 50 in the first direction x is longer than a dimension L2 of the sealing resin 50 in the second direction y. The sealing resin 50 has a resin main surface 51, a resin back surface 52, a pair of first side surfaces 53, a second side surface 54, a third side surface 55, a plurality of recesses 56, a groove 57, and a plurality of recesses 581, 582.
　図９に示すように、樹脂主面５１は、厚さ方向ｚにおいて第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂの各主面１０１と同じ側を向く。図９および図１０に示すように、樹脂裏面５２は、厚さ方向ｚにおいて樹脂主面５１とは反対側を向く。図５に示すように、樹脂裏面５２から、第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂの各裏面１０２が露出している。 As shown in FIG. 9, the resin main surface 51 faces the same side as each main surface 101 of the first die pad 10A and the second die pad 10B in the thickness direction z. As shown in FIGS. 9 and 10, the resin back surface 52 faces the opposite side from the resin main surface 51 in the thickness direction z. As shown in FIG. 5, each back surface 102 of the first die pad 10A and the second die pad 10B is exposed from the resin back surface 52.
　図２、図５および図６に示すように、一対の第１側面５３は、第１方向ｘにおいて互いに離れて位置する。一対の第１側面５３は、第１方向ｘを向き、かつ第２方向ｙに延びている。一対の第１側面５３は、樹脂主面５１および樹脂裏面５２に繋がる。 As shown in FIGS. 2, 5, and 6, the pair of first side surfaces 53 are located apart from each other in the first direction x. The pair of first side surfaces 53 face in the first direction x and extend in the second direction y. The pair of first side surfaces 53 are connected to the resin main surface 51 and the resin back surface 52.
　図２、図５および図７に示すように、第２側面５４および第３側面５５は、第２方向ｙにおいて互いに離れて位置する。第２側面５４および第３側面５５は、第２方向ｙにおいて互いに反対側を向き、かつ第１方向ｘに延びている。第２側面５４および第３側面５５は、樹脂主面５１および樹脂裏面５２に繋がる。図６に示すように、第３側面５５から複数の端子リード１３が露出している。 As shown in FIGS. 2, 5, and 7, the second side surface 54 and the third side surface 55 are located apart from each other in the second direction y. The second side surface 54 and the third side surface 55 face oppositely to each other in the second direction y and extend in the first direction x. The second side surface 54 and the third side surface 55 are connected to the resin main surface 51 and the resin back surface 52. As shown in FIG. 6, a plurality of terminal leads 13 are exposed from the third side surface 55.
　図２、図５および図６に示すように、複数の凹部５６は、第３側面５５から第２方向ｙに凹むとともに、厚さ方向ｚにおいて樹脂主面５１から樹脂裏面５２に至っている。第１方向ｘにおいて、複数の凹部５６は、第７端子リード１８２と第３端子リード１６との間、第３端子リード１６と第１端子リード１４との間、第１端子リード１４と第２端子リード１５との間、および、第２端子リード１５と第６端子リード１８１との間に対して個別に位置する。 As shown in FIGS. 2, 5, and 6, the plurality of recesses 56 are recessed from the third side surface 55 in the second direction y, and extend from the resin main surface 51 to the resin back surface 52 in the thickness direction z. In the first direction They are located individually between the terminal lead 15 and between the second terminal lead 15 and the sixth terminal lead 181.
　図５、図６、図９および図１０に示すように、溝部５７は、樹脂裏面５２から厚さ方向ｚに凹むとともに、第２方向ｙに沿って延びる。溝部５７の第２方向ｙの両側は、第２側面５４および第３側面５５に繋がる。厚さ方向ｚに沿って視て、溝部５７は、第１ダイパッド１０Ａの裏面１０２と、第２ダイパッド１０Ｂの裏面１０２とを分断する。 As shown in FIGS. 5, 6, 9, and 10, the groove portion 57 is recessed from the resin back surface 52 in the thickness direction z and extends along the second direction y. Both sides of the groove portion 57 in the second direction y are connected to the second side surface 54 and the third side surface 55. When viewed along the thickness direction z, the groove portion 57 separates the back surface 102 of the first die pad 10A and the back surface 102 of the second die pad 10B.
　図６、図７、図９および図１０に示すように、複数の凹部５８１，５８２の各々は、樹脂主面５１から厚さ方向ｚに凹む。複数の凹部５８１，５８２の各平面視形状は、特に限定されないが、図示された例では、円形である。複数の凹部５８１の各々は、平面視において、第１ダイパッド１０Ａに重なる。図示された例では、複数の凹部５８１は、平面視における第１ダイパッド１０Ａの四隅近傍にそれぞれ個別に位置する。複数の凹部５８２の各々は、平面視において、第２ダイパッド１０Ｂに重なる。図示された例では、複数の凹部５８２は、平面視における第２ダイパッド１０Ｂの四隅近傍にそれぞれ個別に位置する。複数の凹部５８１，５８２の各々は、平面視において、第１導通部材３１および第２導通部材３２のいずれにも重ならない。さらに、複数の凹部５８１，５８２の各々は、平面視において、一対の第１接続部材４１Ａ，４１Ｂおよび一対の第２接続部材４２Ａ，４２Ｂのいずれにも重ならない。複数の凹部５８１は、半導体装置Ａ１０の製造時において、第１ダイパッド１０Ａを固定するためのピンによって形成されるものである。当該ピンは、封止樹脂５０を形成する前の段階において、第１ダイパッド１０Ａに押し当てられ、第１ダイパッド１０Ａを固定する。この状態で、封止樹脂５０の形成が開始される。そして、当該ピンは、封止樹脂５０の形成が完了する前に引き抜かれる。これにより、当該ピンが配置されていた領域の少なくとも一部に封止樹脂５０が形成されるので、第１ダイパッド１０Ａの主面１０１が封止樹脂５０に覆われる。複数の凹部５８１は、このような封止樹脂５０の成形過程によって形成される痕である。複数の凹部５８２も同様に、半導体装置Ａ１０の製造時において、第２ダイパッド１０Ｂを固定するためのピンによって形成されるものである。複数の凹部５８２は、封止樹脂５０の成形過程によって形成される痕である。 As shown in FIGS. 6, 7, 9, and 10, each of the plurality of recesses 581, 582 is recessed from the main resin surface 51 in the thickness direction z. Although the plan view shape of each of the plurality of recesses 581 and 582 is not particularly limited, in the illustrated example, it is circular. Each of the plurality of recesses 581 overlaps the first die pad 10A in plan view. In the illustrated example, the plurality of recesses 581 are individually located near the four corners of the first die pad 10A in plan view. Each of the plurality of recesses 582 overlaps the second die pad 10B in plan view. In the illustrated example, the plurality of recesses 582 are individually located near the four corners of the second die pad 10B in plan view. Each of the plurality of recesses 581 and 582 does not overlap with either the first conductive member 31 or the second conductive member 32 in plan view. Furthermore, each of the plurality of recesses 581, 582 does not overlap with either the pair of first connecting members 41A, 41B or the pair of second connecting members 42A, 42B in plan view. The plurality of recesses 581 are formed by pins for fixing the first die pad 10A during manufacturing of the semiconductor device A10. The pin is pressed against the first die pad 10A before forming the sealing resin 50, and fixes the first die pad 10A. In this state, formation of the sealing resin 50 is started. Then, the pin is pulled out before the formation of the sealing resin 50 is completed. As a result, the sealing resin 50 is formed in at least a portion of the area where the pin was arranged, so that the main surface 101 of the first die pad 10A is covered with the sealing resin 50. The plurality of recesses 581 are marks formed by such a molding process of the sealing resin 50. Similarly, the plurality of recesses 582 are formed by pins for fixing the second die pad 10B during manufacturing of the semiconductor device A10. The plurality of recesses 582 are marks formed by the molding process of the sealing resin 50.
　封止樹脂５０は、図１、図２および図５に示すように、さらに複数の痕跡５８９を有する。複数の痕跡５８９は、たとえば封止樹脂５０の形成時において、封止樹脂５０を金型から取り出すためのエジェクタピンが押し付けられた痕である。複数の痕跡５８９はそれぞれ、樹脂主面５１または樹脂裏面５２のいずれかから窪む。なお、封止樹脂５０に、複数の痕跡５８９のいずれも形成されていなくてもよい。また、図５に示すように、第１ダイパッド１０Ａの裏面１０２および第２ダイパッド１０Ｂの裏面１０２はそれぞれ、痕跡１０９を有する。第１ダイパッド１０Ａに形成された痕跡１０９および第２ダイパッド１０Ｂに形成された痕跡１０９はそれぞれ、先述のエジェクタピンが押し付けられた痕である。第１ダイパッド１０Ａに形成された痕跡１０９は、第１ダイパッド１０Ａの裏面１０２から窪み、第２ダイパッド１０Ｂに形成された痕跡１０９は、第２ダイパッド１０Ｂの裏面１０２から窪む。なお、第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂのいずれにも、痕跡１０９が形成されていなくてもよい。複数の痕跡５８９および複数の痕跡１０９の各深さはそれぞれ、たとえば、複数の凹部５８１の各深さよりも小さいが、反対に大きくてもよいし、同じであってもよい。 The sealing resin 50 further has a plurality of traces 589, as shown in FIGS. 1, 2, and 5. The plurality of marks 589 are, for example, marks caused by pressing an ejector pin for ejecting the sealing resin 50 from the mold when the sealing resin 50 was formed. Each of the plurality of traces 589 is depressed from either the resin main surface 51 or the resin back surface 52. Note that none of the plurality of traces 589 may be formed on the sealing resin 50. Further, as shown in FIG. 5, the back surface 102 of the first die pad 10A and the back surface 102 of the second die pad 10B each have a trace 109. The traces 109 formed on the first die pad 10A and the traces 109 formed on the second die pad 10B are traces where the ejector pins described above were pressed. The trace 109 formed on the first die pad 10A is depressed from the back surface 102 of the first die pad 10A, and the trace 109 formed on the second die pad 10B is depressed from the back surface 102 of the second die pad 10B. Note that the trace 109 does not need to be formed on either the first die pad 10A or the second die pad 10B. The depths of the plurality of traces 589 and the plurality of traces 109 are, for example, smaller than the depths of the plurality of recesses 581, but may be larger or the same.
　図３および図５に示すように、第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂは、第１端面１１１、第２端面１１２、第３端面１１３および第４端面１１４を有する。第１端面１１１、第２端面１１２、第３端面１１３および第４端面１１４は、封止樹脂５０に覆われている。第１端面１１１は、第１方向ｘを向き、かつ第２方向ｙに延びている。第１端面１１１は、封止樹脂５０の一対の第１側面５３から最も近くに位置する。第２端面１１２は、第２方向ｙを向き、かつ第１方向ｘに延びている。第２端面１１２は、封止樹脂５０の第２側面５４から最も近くに位置する。第３端面１１３は、第２方向ｙにおいて第２端面１１２とは反対側を向き、かつ第１方向ｘに延びている。第３端面１１３は、封止樹脂５０の第３側面５５から最も近くに位置する。第４端面１１４は、第１方向ｘにおいて第１端面１１１とは反対側を向き、かつ第２方向ｙに延びている。図９に示すように、第１ダイパッド１０Ａの第４端面１１４と、第２ダイパッド１０Ｂの第４端面１１４との間には、溝部５７が位置する。 As shown in FIGS. 3 and 5, the first die pad 10A and the second die pad 10B have a first end surface 111, a second end surface 112, a third end surface 113, and a fourth end surface 114. The first end surface 111, the second end surface 112, the third end surface 113, and the fourth end surface 114 are covered with a sealing resin 50. The first end surface 111 faces in the first direction x and extends in the second direction y. The first end surface 111 is located closest to the pair of first side surfaces 53 of the sealing resin 50. The second end surface 112 faces in the second direction y and extends in the first direction x. The second end surface 112 is located closest to the second side surface 54 of the sealing resin 50. The third end surface 113 faces opposite to the second end surface 112 in the second direction y, and extends in the first direction x. The third end surface 113 is located closest to the third side surface 55 of the sealing resin 50. The fourth end surface 114 faces opposite to the first end surface 111 in the first direction x, and extends in the second direction y. As shown in FIG. 9, a groove 57 is located between the fourth end surface 114 of the first die pad 10A and the fourth end surface 114 of the second die pad 10B.
　図５および図８に示すように、第３端面１１３と第３側面５５との間隔Ｐ２は、第２端面１１２と第２側面５４との間隔Ｐ１よりも長い。 As shown in FIGS. 5 and 8, the distance P2 between the third end surface 113 and the third side surface 55 is longer than the distance P1 between the second end surface 112 and the second side surface 54.
　図３、図５および図８に示すように、第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂは、第１隅部端面１２１を有する。第１隅部端面１２１は、第１端面１１１と第２端面１１２との間に位置し、かつ第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂのいずれかの隅部に位置する。第１隅部端面１２１は、封止樹脂５０に覆われ、かつ第１端面１１１および第２端面１１２に対して傾斜した平面である。図１５に示す第１端面１１１に対する第１隅部端面１２１の第１傾斜角α１と、第２端面１１２に対する第１隅部端面１２１の第２傾斜角α２と、のいずれかが６０°以上８５°以下である。複数の凹部５８１のうちの１つは、平面視において、第１ダイパッド１０Ａの第１隅部端面１２１近辺に位置し、複数の凹部５８２のうちの１つは、平面視において、第２ダイパッド１０Ｂの第１隅部端面１２１近辺に位置する。 As shown in FIGS. 3, 5, and 8, the first die pad 10A and the second die pad 10B have a first corner end surface 121. The first corner end surface 121 is located between the first end surface 111 and the second end surface 112, and is located at the corner of either the first die pad 10A or the second die pad 10B. The first corner end surface 121 is a plane that is covered with the sealing resin 50 and is inclined with respect to the first end surface 111 and the second end surface 112. Either the first inclination angle α1 of the first corner end face 121 with respect to the first end face 111 shown in FIG. 15 and the second inclination angle α2 of the first corner end face 121 with respect to the second end face 112 shown in FIG. ° or less. One of the plurality of recesses 581 is located near the first corner end surface 121 of the first die pad 10A in plan view, and one of the plurality of recesses 582 is located near the second die pad 10B in plan view. It is located near the first corner end face 121 of.
　さらに図１５に示すように、第１隅部端面１２１の最長法線Ｎｍａｘを設定する。最長法線Ｎｍａｘは、第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂのいずれかの第１隅部端面１２１から、封止樹脂５０の一対の第１側面５３のうち第１隅部端面１２１から最も近くに位置する第１側面５３に至る第１隅部端面１２１の法線の最大値である。最長法線Ｎｍａｘは、第１方向ｘおよび第２方向ｙを面内方向とする仮想平面と、第１隅部端面１２１との交線Ｃ（図１５参照）の長さの１．０倍以上１．５倍以下である。 Further, as shown in FIG. 15, the longest normal line Nmax of the first corner end face 121 is set. The longest normal Nmax is the closest from the first corner end surface 121 of either the first die pad 10A or the second die pad 10B to the first corner end surface 121 of the pair of first side surfaces 53 of the sealing resin 50. This is the maximum value of the normal line of the first corner end surface 121 that reaches the first side surface 53 located therein. The longest normal Nmax is 1.0 times or more the length of the intersection line C (see FIG. 15) between the first corner end surface 121 and a virtual plane whose in-plane directions are the first direction x and the second direction y. It is 1.5 times or less.
　図３、図５および図８に示すように、第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂは、第２隅部端面１２２を有する。第２隅部端面１２２は、第１端面１１１と第３端面１１３との間に位置し、かつ第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂのいずれかの隅部に位置する。第２隅部端面１２２は、封止樹脂５０に覆われ、かつ第１端面１１１および第３端面１１３に対して傾斜した平面である。図１６に示す第１端面１１１に対する第２隅部端面１２２の第３傾斜角α３と、第３端面１１３に対する第２隅部端面１２２の第４傾斜角α４と、のいずれかが６０°以上８５°以下である。複数の凹部５８１のうちの１つは、平面視において、第１ダイパッド１０Ａの第２隅部端面１２２近辺に位置し、複数の凹部５８２のうちの１つは、平面視において、第２ダイパッド１０Ｂの第２隅部端面１２２近辺に位置する。 As shown in FIGS. 3, 5, and 8, the first die pad 10A and the second die pad 10B have a second corner end surface 122. The second corner end surface 122 is located between the first end surface 111 and the third end surface 113, and is located at the corner of either the first die pad 10A or the second die pad 10B. The second corner end surface 122 is a plane that is covered with the sealing resin 50 and is inclined with respect to the first end surface 111 and the third end surface 113. Either the third inclination angle α3 of the second corner end face 122 with respect to the first end face 111 shown in FIG. 16 and the fourth inclination angle α4 of the second corner end face 122 with respect to the third end face 113 shown in FIG. ° or less. One of the plurality of recesses 581 is located near the second corner end surface 122 of the first die pad 10A in plan view, and one of the plurality of recesses 582 is located near the second die pad 10B in plan view. It is located near the second corner end face 122 of.
　図３および図５に示すように、第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂは、第３隅部端面１２３を有する。第３隅部端面１２３は、第２端面１１２と第４端面１１４との間に位置し、かつ第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂのいずれかの隅部に位置する。第３隅部端面１２３は、封止樹脂５０に覆われ、かつ第２端面１１２および第４端面１１４に対して傾斜した平面である。図１７に示す第４端面１１４に対する第３隅部端面１２３の第５傾斜角α５と、第２端面１１２に対する第３隅部端面１２３の第６傾斜角α６と、のいずれかが６０°以上８５°以下である。複数の凹部５８１のうちの１つは、平面視において、第１ダイパッド１０Ａの第３隅部端面１２３近辺に位置し、複数の凹部５８２のうちの１つは、平面視において、第２ダイパッド１０Ｂの第３隅部端面１２３近辺に位置する。 As shown in FIGS. 3 and 5, the first die pad 10A and the second die pad 10B have a third corner end surface 123. The third corner end surface 123 is located between the second end surface 112 and the fourth end surface 114, and is located at the corner of either the first die pad 10A or the second die pad 10B. The third corner end surface 123 is a plane that is covered with the sealing resin 50 and is inclined with respect to the second end surface 112 and the fourth end surface 114. Either the fifth inclination angle α5 of the third corner end face 123 with respect to the fourth end face 114 and the sixth inclination angle α6 of the third corner end face 123 with respect to the second end face 112 shown in FIG. ° or less. One of the plurality of recesses 581 is located near the third corner end surface 123 of the first die pad 10A in plan view, and one of the plurality of recesses 582 is located near the second die pad 10B in plan view. It is located near the third corner end face 123 of.
　図３および図５に示すように、第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂは、第４隅部端面１２４を有する。第４隅部端面１２４は、第３端面１１３と第４端面１１４との間に位置し、かつ第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂのいずれかの隅部に位置する。第４隅部端面１２４は、封止樹脂５０に覆われ、かつ第３端面１１３および第４端面１１４に対して傾斜した平面である。図１８に示す第４端面１１４に対する第４隅部端面１２４の第７傾斜角α７と、第３端面１１３に対する第４隅部端面１２４の第８傾斜角α８と、のいずれかが６０°以上８５°以下である。複数の凹部５８１のうちの１つは、平面視において、第１ダイパッド１０Ａの第４隅部端面１２４近辺に位置し、複数の凹部５８２のうちの１つは、平面視において、第２ダイパッド１０Ｂの第４隅部端面１２４近辺に位置する。 As shown in FIGS. 3 and 5, the first die pad 10A and the second die pad 10B have a fourth corner end surface 124. The fourth corner end surface 124 is located between the third end surface 113 and the fourth end surface 114, and is located at the corner of either the first die pad 10A or the second die pad 10B. The fourth corner end surface 124 is a plane that is covered with the sealing resin 50 and is inclined with respect to the third end surface 113 and the fourth end surface 114. Either the seventh inclination angle α7 of the fourth corner end face 124 with respect to the fourth end face 114 and the eighth inclination angle α8 of the fourth corner end face 124 with respect to the third end face 113 shown in FIG. ° or less. One of the plurality of recesses 581 is located near the fourth corner end surface 124 of the first die pad 10A in plan view, and one of the plurality of recesses 582 is located near the second die pad 10B in plan view. It is located near the fourth corner end face 124 of.
　図１３に示すように、第２ダイパッド１０Ｂは、第１座面１０３および第１起立面１０４を有する。第１座面１０３は、厚さ方向ｚにおいて主面１０１と同じ側を向き、かつ厚さ方向ｚにおいて主面１０１と裏面１０２との間に位置する。第１座面１０３は、第４端面１１４に繋がる。第１起立面１０４は、厚さ方向ｚに対して直交する方向を向き、かつ第１座面１０３および主面１０１に繋がる。第１座面１０３および第１起立面１０４は、第２ダイパッド１０Ｂにおいて段差をなしている。 As shown in FIG. 13, the second die pad 10B has a first seat surface 103 and a first upright surface 104. The first seat surface 103 faces the same side as the main surface 101 in the thickness direction z, and is located between the main surface 101 and the back surface 102 in the thickness direction z. The first seat surface 103 is connected to a fourth end surface 114. The first upright surface 104 faces in a direction perpendicular to the thickness direction z, and is connected to the first seat surface 103 and the main surface 101. The first seat surface 103 and the first upright surface 104 form a step difference in the second die pad 10B.
　第１半導体素子２１および第２半導体素子２２の各々は、たとえばトランジスタである。図１９に示すように、半導体装置Ａ１０における当該トランジスタは、ＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）であるが、この他、バイポーラトランジスタおよびＩＧＢＴ（Insulated Gate Bipolar Transistor）などであってもよい。なお、図１９の回路においては、第１半導体素子２１および第２半導体素子２２の各々に内蔵される寄生ダイオード成分も図示している。第１半導体素子２１および第２半導体素子２２の各々は、たとえば、ｎチャネル型であるが、ｐチャネル型であってもよい。第１半導体素子２１および第２半導体素子２２の各々は、化合物半導体基板を含む。当該化合物半導体基板の組成は、ケイ素（Ｓｉ）または炭化ケイ素（ＳｉＣ）を含む。 Each of the first semiconductor element 21 and the second semiconductor element 22 is, for example, a transistor. As shown in FIG. 19, the transistor in the semiconductor device A10 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), but may also be a bipolar transistor, an IGBT (Insulated Gate Bipolar Transistor), etc. . In the circuit of FIG. 19, parasitic diode components built into each of the first semiconductor element 21 and the second semiconductor element 22 are also illustrated. Each of the first semiconductor element 21 and the second semiconductor element 22 is, for example, an n-channel type, but may be a p-channel type. Each of the first semiconductor element 21 and the second semiconductor element 22 includes a compound semiconductor substrate. The composition of the compound semiconductor substrate includes silicon (Si) or silicon carbide (SiC).
　第１半導体素子２１は、図３および図９に示すように、第１ダイパッド１０Ａに搭載される。好ましくは、平面視において、第１半導体素子２１の重心は、第１ダイパッド１０Ａの中心部に重なる。第１ダイパッド１０Ａの中心部とは、第１ダイパッド１０Ａを第１方向ｘにＮｘ（Ｎｘは正の奇数）分割した時の中央であり、かつ第１ダイパッド１０Ａを第２方向ｙにＮｙ（Ｎｙは正の奇数）分割した時の中央に相当する領域である。Ｎｘ，Ｎｙはそれぞれ、何ら限定されないが、たとえば３または５である。 The first semiconductor element 21 is mounted on the first die pad 10A, as shown in FIGS. 3 and 9. Preferably, in plan view, the center of gravity of the first semiconductor element 21 overlaps with the center of the first die pad 10A. The center of the first die pad 10A is the center when the first die pad 10A is divided into Nx (Nx is a positive odd number) in the first direction x, and the center of the first die pad 10A is divided into Ny (Ny is a positive odd number) This is the area corresponding to the center when divided. Nx and Ny are each 3 or 5, for example, although they are not limited in any way.
　第１半導体素子２１は、第１主面２１ａおよび第１裏面２１ｂを有する。第１主面２１ａおよび第１裏面２１ｂは、厚さ方向ｚに互いに離間する。第１主面２１ａは、第１ダイパッド１０Ａの主面１０１と同じ方向を向く。第１裏面２１ｂは、厚さ方向ｚにおいて第１主面２１ａと反対側を向き、第１ダイパッド１０Ａの主面１０１に対向する。 The first semiconductor element 21 has a first main surface 21a and a first back surface 21b. The first main surface 21a and the first back surface 21b are spaced apart from each other in the thickness direction z. The first main surface 21a faces the same direction as the main surface 101 of the first die pad 10A. The first back surface 21b faces opposite to the first main surface 21a in the thickness direction z, and faces the main surface 101 of the first die pad 10A.
　第１半導体素子２１は、図３および図９に示すように、第１ダイパッド１０Ａに搭載されている。図１１に示すように、第１半導体素子２１は、第１主面電極２１１、主面電極２１２および裏面電極２１３を有する。 The first semiconductor element 21 is mounted on the first die pad 10A, as shown in FIGS. 3 and 9. As shown in FIG. 11, the first semiconductor element 21 has a first main surface electrode 211, a main surface electrode 212, and a back surface electrode 213.
　第１主面電極２１１は、第１主面２１ａに配置される。第１主面電極２１１には、第１半導体素子２１により変換された後の電力に対応する電流が流れる。第１半導体素子２１がＭＯＳＦＥＴである例において、第１主面電極２１１は、たとえばソース電極である。第１主面電極２１１は、複数の金属めっき層を含む。第１主面電極２１１は、ニッケル（Ｎｉ）めっき層と、当該ニッケルめっき層の上に積層された金（Ａｕ）めっき層を含む。この他、第１主面電極２１１は、ニッケルめっき層と、当該ニッケルめっき層の上に積層されたパラジウム（Ｐｄ）めっき層と、当該パラジウムめっき層の上に積層された金めっき層を含む場合でもよい。 The first main surface electrode 211 is arranged on the first main surface 21a. A current corresponding to the power converted by the first semiconductor element 21 flows through the first main surface electrode 211 . In an example where the first semiconductor element 21 is a MOSFET, the first main surface electrode 211 is, for example, a source electrode. The first main surface electrode 211 includes a plurality of metal plating layers. The first main surface electrode 211 includes a nickel (Ni) plating layer and a gold (Au) plating layer laminated on the nickel plating layer. In addition, the first main surface electrode 211 may include a nickel plating layer, a palladium (Pd) plating layer laminated on the nickel plating layer, and a gold plating layer laminated on the palladium plating layer. But that's fine.
　主面電極２１２は、第１主面２１ａに配置される。主面電極２１２には、第１半導体素子２１を駆動するための第１駆動信号（ゲート電圧）が印加される。第１半導体素子２１がＭＯＳＦＥＴである例において、主面電極２１２は、たとえばゲート電極である。平面視において、主面電極２１２の面積は、第１主面電極２１１の面積よりも小である。 The main surface electrode 212 is arranged on the first main surface 21a. A first drive signal (gate voltage) for driving the first semiconductor element 21 is applied to the main surface electrode 212 . In an example where the first semiconductor element 21 is a MOSFET, the main surface electrode 212 is, for example, a gate electrode. In plan view, the area of the main surface electrode 212 is smaller than the area of the first main surface electrode 211.
　裏面電極２１３は、第１裏面２１ｂに配置される。裏面電極２１３は、第１ダイパッド１０Ａの主面１０１に対向して設けられている。裏面電極２１３には、第１半導体素子２１により変換される前の電力に対応する電流が流れる。第１半導体素子２１がＭＯＳＦＥＴである例において、裏面電極２１３は、たとえばドレイン電極である。 The back electrode 213 is arranged on the first back surface 21b. The back electrode 213 is provided facing the main surface 101 of the first die pad 10A. A current corresponding to the power before being converted by the first semiconductor element 21 flows through the back electrode 213 . In an example where the first semiconductor element 21 is a MOSFET, the back electrode 213 is, for example, a drain electrode.
　第２半導体素子２２は、第２ダイパッド１０Ｂの主面１０１に搭載される。好ましくは、平面視において、第２半導体素子２２の重心は、第２ダイパッド１０Ｂの中心部に重なる。第２ダイパッド１０Ｂの中心部とは、第２ダイパッド１０Ｂを第１方向ｘにＬｘ（Ｌｘは正の奇数）分割した時の中央であり、かつ第２ダイパッド１０Ｂを第２方向ｙにＬｙ（Ｌｙは正の奇数）分割した時の中央に相当する領域である。Ｌｘ，Ｌｙはそれぞれ、何ら限定されないが、たとえば３または５である。 The second semiconductor element 22 is mounted on the main surface 101 of the second die pad 10B. Preferably, the center of gravity of the second semiconductor element 22 overlaps the center of the second die pad 10B in plan view. The center of the second die pad 10B is the center when the second die pad 10B is divided into Lx (Lx is a positive odd number) in the first direction x, and the center of the second die pad 10B is divided into Ly (Ly) in the second direction y. is a positive odd number) This is the area corresponding to the center when divided. Lx and Ly are each 3 or 5, for example, although there are no limitations.
　第２半導体素子２２は、第２主面２２ａおよび第２裏面２２ｂを有する。第２主面２２ａおよび第２裏面２２ｂは、厚さ方向ｚに互いに離間する。第２主面２２ａは、第２ダイパッド１０Ｂの主面１０１と同じ方向を向く。第２裏面２２ｂは、厚さ方向ｚにおいて第２主面２２ａと反対側を向き、第２ダイパッド１０Ｂの主面１０１に対向する。 The second semiconductor element 22 has a second main surface 22a and a second back surface 22b. The second main surface 22a and the second back surface 22b are spaced apart from each other in the thickness direction z. The second main surface 22a faces the same direction as the main surface 101 of the second die pad 10B. The second back surface 22b faces the opposite side from the second main surface 22a in the thickness direction z, and faces the main surface 101 of the second die pad 10B.
　第２半導体素子２２は、図３および図９に示すように、第２ダイパッド１０Ｂに搭載されている。図１２に示すように、第２半導体素子２２は、第２主面電極２２１、主面電極２２２および裏面電極２２３を有する。 The second semiconductor element 22 is mounted on the second die pad 10B, as shown in FIGS. 3 and 9. As shown in FIG. 12, the second semiconductor element 22 has a second main surface electrode 221, a main surface electrode 222, and a back electrode 223.
　第２主面電極２２１は、第２主面２２ａに配置される。第２主面電極２２１には、第２半導体素子２２により変換された後の電力に対応する電流が流れる。第２半導体素子２２がＭＯＳＦＥＴである例において、第２主面電極２２１は、たとえばソース電極である。第２主面電極２２１は、第１主面電極２１１と同様に、複数の金属めっき層を含む。第２主面電極２２１は、ニッケル（Ｎｉ）めっき層と、当該ニッケルめっき層の上に積層された金（Ａｕ）めっき層を含む。この他、第２主面電極２２１は、ニッケルめっき層と、当該ニッケルめっき層の上に積層されたパラジウム（Ｐｄ）めっき層と、当該パラジウムめっき層の上に積層された金めっき層を含む場合でもよい。 The second main surface electrode 221 is arranged on the second main surface 22a. A current corresponding to the power converted by the second semiconductor element 22 flows through the second main surface electrode 221 . In an example where the second semiconductor element 22 is a MOSFET, the second main surface electrode 221 is, for example, a source electrode. Like the first main surface electrode 211, the second main surface electrode 221 includes a plurality of metal plating layers. The second main surface electrode 221 includes a nickel (Ni) plating layer and a gold (Au) plating layer laminated on the nickel plating layer. In addition, the second principal surface electrode 221 may include a nickel plating layer, a palladium (Pd) plating layer laminated on the nickel plating layer, and a gold plating layer laminated on the palladium plating layer. But that's fine.
　主面電極２２２は、第２主面２２ａに配置される。主面電極２２２には、第２半導体素子２２を駆動するための第２駆動信号（ゲート電圧）が印加される。第２半導体素子２２がＭＯＳＦＥＴである例において、主面電極２２２は、たとえばゲート電極である。平面視において、主面電極２２２の面積は、第２主面電極２２１の面積よりも小である。 The main surface electrode 222 is arranged on the second main surface 22a. A second drive signal (gate voltage) for driving the second semiconductor element 22 is applied to the main surface electrode 222 . In an example where the second semiconductor element 22 is a MOSFET, the main surface electrode 222 is, for example, a gate electrode. In plan view, the area of the main surface electrode 222 is smaller than the area of the second main surface electrode 221.
　裏面電極２２３は、第２裏面２２ｂに配置される。裏面電極２２３は、第２ダイパッド１０Ｂの主面１０１に対向して設けられている。裏面電極２２３には、第２半導体素子２２により変換される前の電力に対応する電流が流れる。第２半導体素子２２がＭＯＳＦＥＴである例において、裏面電極２２３は、たとえばドレイン電極である。 The back electrode 223 is arranged on the second back surface 22b. Back electrode 223 is provided facing main surface 101 of second die pad 10B. A current corresponding to the power before being converted by the second semiconductor element 22 flows through the back electrode 223 . In an example where the second semiconductor element 22 is a MOSFET, the back electrode 223 is, for example, a drain electrode.
　半導体装置Ａ１０は、２つのダイボンディング層２３１，２３２をさらに備える。２つのダイボンディング層２３１，２３２の各々は、導電性を有する。各ダイボンディング層２３１，２３２は、たとえばはんだである。この他、各ダイボンディング層２３１，２３２は、焼結金属でもよい。 The semiconductor device A10 further includes two die bonding layers 231 and 232. Each of the two die bonding layers 231 and 232 has conductivity. Each die bonding layer 231, 232 is, for example, solder. In addition, each die bonding layer 231, 232 may be made of sintered metal.
　ダイボンディング層２３１は、図９および図１１に示すように、第１ダイパッド１０Ａの主面１０１と第１半導体素子２１の裏面電極２１３との間に介在する。ダイボンディング層２３１は、第１ダイパッド１０Ａの主面１０１と、第１半導体素子２１の裏面電極２１３とを接合する。これにより、第１半導体素子２１の裏面電極２１３は、第１ダイパッド１０Ａに導通する。 The die bonding layer 231 is interposed between the main surface 101 of the first die pad 10A and the back electrode 213 of the first semiconductor element 21, as shown in FIGS. 9 and 11. The die bonding layer 231 bonds the main surface 101 of the first die pad 10A and the back electrode 213 of the first semiconductor element 21. Thereby, the back electrode 213 of the first semiconductor element 21 is electrically connected to the first die pad 10A.
　ダイボンディング層２３２は、図９、図１０および図１２に示すように、第２ダイパッド１０Ｂの主面１０１と第２半導体素子２２の裏面電極２２３との間に介在する。ダイボンディング層２３２は、第２ダイパッド１０Ｂの主面１０１と第２半導体素子２２の裏面電極２２３とを接合する。これにより、第２半導体素子２２の裏面電極２２３は、第２ダイパッド１０Ｂに導通する。 The die bonding layer 232 is interposed between the main surface 101 of the second die pad 10B and the back electrode 223 of the second semiconductor element 22, as shown in FIGS. 9, 10, and 12. The die bonding layer 232 bonds the main surface 101 of the second die pad 10B and the back electrode 223 of the second semiconductor element 22. Thereby, the back electrode 223 of the second semiconductor element 22 is electrically connected to the second die pad 10B.
　複数の端子リード１３は、図３に示すように、第２方向ｙにおいて第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂに対して第２端面１１２が向く側とは反対側に位置する。複数の端子リード１３の少なくともいずれかは、第１半導体素子２１または第２半導体素子２２のいずれかに導通している。複数の端子リード１３は、第１方向ｘに沿って配列されている。複数の端子リード１３は、第１端子リード１４、第２端子リード１５、第３端子リード１６、第４端子リード１７１、第５端子リード１７２、第６端子リード１８１および第７端子リード１８２を含む。 As shown in FIG. 3, the plurality of terminal leads 13 are located on the opposite side of the second end surface 112 with respect to the first die pad 10A and the second die pad 10B in the second direction y. At least one of the plurality of terminal leads 13 is electrically connected to either the first semiconductor element 21 or the second semiconductor element 22. The plurality of terminal leads 13 are arranged along the first direction x. The plurality of terminal leads 13 include a first terminal lead 14, a second terminal lead 15, a third terminal lead 16, a fourth terminal lead 171, a fifth terminal lead 172, a sixth terminal lead 181, and a seventh terminal lead 182. .
　第１端子リード１４は、図３に示すように、第２方向ｙにおいて第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂから離れて位置し、かつ第１方向ｘにおいて第２端子リード１５と第３端子リード１６との間に位置する。第１端子リード１４は、第２方向ｙに沿って延びている。第１端子リード１４は、第２半導体素子２２の第２主面電極２２１に導通している。第１端子リード１４は、被覆部１４Ａおよび露出部１４Ｂを含む。図１０に示すように、被覆部１４Ａは、封止樹脂５０に覆われている。図２、図３、図５および図６に示すように、露出部１４Ｂは、被覆部１４Ａに繋がり、且つ封止樹脂５０の第３側面５５から露出している。露出部１４Ｂは、第２方向ｙにおいて第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂから遠ざかる側に延びている。露出部１４Ｂの表面には、たとえば錫めっきが施されている。 As shown in FIG. 3, the first terminal lead 14 is located apart from the first die pad 10A and the second die pad 10B in the second direction y, and the second terminal lead 15 and the third terminal lead in the first direction x. It is located between 16 and 16. The first terminal lead 14 extends along the second direction y. The first terminal lead 14 is electrically connected to the second main surface electrode 221 of the second semiconductor element 22 . The first terminal lead 14 includes a covering portion 14A and an exposed portion 14B. As shown in FIG. 10, the covering portion 14A is covered with a sealing resin 50. As shown in FIGS. 2, 3, 5, and 6, the exposed portion 14B is connected to the covering portion 14A and exposed from the third side surface 55 of the sealing resin 50. The exposed portion 14B extends in the second direction y away from the first die pad 10A and the second die pad 10B. The surface of the exposed portion 14B is plated with tin, for example.
　図１４に示すように、第１端子リード１４の被覆部１４Ａは、第２座面１４Ｃおよび第２起立面１４Ｄを有する。第２座面１４Ｃは、厚さ方向ｚにおいて第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂの各主面１０１と同じ側を向き、かつ被覆部１４Ａの上面（厚さ方向ｚ上方を向く面）よりも厚さ方向ｚの下方側に位置する。第２起立面１４Ｄは、厚さ方向ｚに対して直交する方向を向くとともに、第２座面１４Ｃ、および被覆部１４Ａの上面に繋がる。第２座面１４Ｃおよび第２起立面１４Ｄは、第１端子リード１４の被覆部１４Ａにおいて段差をなしている。 As shown in FIG. 14, the covering portion 14A of the first terminal lead 14 has a second seat surface 14C and a second upright surface 14D. The second seat surface 14C faces the same side as each main surface 101 of the first die pad 10A and the second die pad 10B in the thickness direction z, and is lower than the upper surface of the covering portion 14A (the surface facing upward in the thickness direction z). It is located on the lower side in the thickness direction z. The second upright surface 14D faces in a direction perpendicular to the thickness direction z, and is connected to the second seating surface 14C and the upper surface of the covering portion 14A. The second seat surface 14C and the second upright surface 14D form a step difference in the covering portion 14A of the first terminal lead 14.
　第２端子リード１５は、図３に示すように、第２方向ｙに沿って延びる部分を含むとともに、第１ダイパッド１０Ａに繋がっている。このため、第２端子リード１５は、第１ダイパッド１０Ａを介して、第１半導体素子２１の裏面電極２１３に導通する。第２端子リード１５は、電力変換対象となる直流の電源電圧が印加されるＰ端子（正極）である。第２端子リード１５は、被覆部１５Ａおよび露出部１５Ｂを含む。図８に示すように、被覆部１５Ａは、第１ダイパッド１０Ａの第３端面１１３に繋がっており、かつ封止樹脂５０に覆われている。第１方向ｘに沿って視て、被覆部１５Ａは、屈曲している。図２、図３、図５および図６に示すように、露出部１５Ｂは、被覆部１５Ａに繋がり、かつ封止樹脂５０の第３側面５５から露出している。露出部１５Ｂは、第２方向ｙにおいて第１ダイパッド１０Ａから遠ざかる側に延びている。露出部１５Ｂの表面には、たとえば錫めっきが施されている。 As shown in FIG. 3, the second terminal lead 15 includes a portion extending along the second direction y, and is connected to the first die pad 10A. Therefore, the second terminal lead 15 is electrically connected to the back electrode 213 of the first semiconductor element 21 via the first die pad 10A. The second terminal lead 15 is a P terminal (positive electrode) to which a DC power supply voltage to be subjected to power conversion is applied. The second terminal lead 15 includes a covering portion 15A and an exposed portion 15B. As shown in FIG. 8, the covering portion 15A is connected to the third end surface 113 of the first die pad 10A, and is covered with the sealing resin 50. The covering portion 15A is bent when viewed along the first direction x. As shown in FIGS. 2, 3, 5, and 6, the exposed portion 15B is connected to the covering portion 15A and exposed from the third side surface 55 of the sealing resin 50. The exposed portion 15B extends away from the first die pad 10A in the second direction y. The surface of the exposed portion 15B is plated with tin, for example.
　第３端子リード１６は、図３に示すように、第２方向ｙに沿って延びる部分を含むとともに、第２ダイパッド１０Ｂに繋がっている。このため、第３端子リード１６は、第２ダイパッド１０Ｂを介して第２半導体素子２２の裏面電極２２３に導通する。第３端子リード１６から、第１半導体素子２１および第２半導体素子２２により変換された交流電力が出力される。第３端子リード１６は、被覆部１６Ａおよび露出部１６Ｂを含む。被覆部１６Ａは、第２ダイパッド１０Ｂの第３端面１１３に繋がり、かつ封止樹脂５０に覆われている。第１方向ｘに沿って視て、被覆部１６Ａは、第２端子リード１５の被覆部１５Ａと同様に屈曲している。図２、図３、図５および図６に示すように、露出部１６Ｂは、被覆部１６Ａに繋がり、かつ封止樹脂５０の第３側面５５から露出している。露出部１６Ｂは、第２方向ｙにおいて第２ダイパッド１０Ｂから遠ざかる側に延びている。露出部１６Ｂの表面には、たとえば錫めっきが施されている。 As shown in FIG. 3, the third terminal lead 16 includes a portion extending along the second direction y, and is connected to the second die pad 10B. Therefore, the third terminal lead 16 is electrically connected to the back electrode 223 of the second semiconductor element 22 via the second die pad 10B. AC power converted by the first semiconductor element 21 and the second semiconductor element 22 is output from the third terminal lead 16 . The third terminal lead 16 includes a covering portion 16A and an exposed portion 16B. The covering portion 16A is connected to the third end surface 113 of the second die pad 10B and is covered with the sealing resin 50. When viewed along the first direction x, the covering portion 16A is bent similarly to the covering portion 15A of the second terminal lead 15. As shown in FIGS. 2, 3, 5, and 6, the exposed portion 16B is connected to the covering portion 16A and exposed from the third side surface 55 of the sealing resin 50. The exposed portion 16B extends away from the second die pad 10B in the second direction y. For example, tin plating is applied to the surface of the exposed portion 16B.
　第４端子リード１７１は、図３に示すように、第２方向ｙにおいて第１ダイパッド１０Ａから離れて位置し、かつ第１方向ｘの一方側に位置する。第５端子リード１７２は、図３に示すように、第２方向ｙにおいて第２ダイパッド１０Ｂから離れて位置し、且つ第１方向ｘの他方側に位置する。第４端子リード１７１は、第１半導体素子２１の主面電極２１２（ゲート電極）に導通している。第４端子リード１７１には、第１半導体素子２１が駆動するための駆動信号（ゲート電圧）が印加される。第５端子リード１７２は、第２半導体素子２２の主面電極２２２（ゲート電極）に導通している。第５端子リード１７２には、第２半導体素子２２が駆動するための駆動信号（ゲート電圧）が印加される。 As shown in FIG. 3, the fourth terminal lead 171 is located away from the first die pad 10A in the second direction y and on one side in the first direction x. As shown in FIG. 3, the fifth terminal lead 172 is located away from the second die pad 10B in the second direction y and on the other side in the first direction x. The fourth terminal lead 171 is electrically connected to the main surface electrode 212 (gate electrode) of the first semiconductor element 21 . A drive signal (gate voltage) for driving the first semiconductor element 21 is applied to the fourth terminal lead 171 . The fifth terminal lead 172 is electrically connected to the main surface electrode 222 (gate electrode) of the second semiconductor element 22 . A drive signal (gate voltage) for driving the second semiconductor element 22 is applied to the fifth terminal lead 172.
　図３に示すように、第４端子リード１７１は、被覆部１７１Ａおよび露出部１７１Ｂを含む。被覆部１７１Ａは、封止樹脂５０に覆われている。図２、図３、図５および図６に示すように、露出部１７１Ｂは、被覆部１７１Ａに繋がり、かつ封止樹脂５０の第３側面５５から露出している。露出部１７１Ｂは、第２方向ｙにおいて第１ダイパッド１０Ａから遠ざかる側に延びている。露出部１７１Ｂの表面には、たとえば錫めっきが施されている。 As shown in FIG. 3, the fourth terminal lead 171 includes a covering portion 171A and an exposed portion 171B. The covering portion 171A is covered with a sealing resin 50. As shown in FIGS. 2, 3, 5, and 6, the exposed portion 171B is connected to the covering portion 171A and exposed from the third side surface 55 of the sealing resin 50. The exposed portion 171B extends away from the first die pad 10A in the second direction y. The surface of the exposed portion 171B is plated with tin, for example.
　図３に示すように、第５端子リード１７２は、被覆部１７２Ａおよび露出部１７２Ｂを含む。被覆部１７２Ａは、封止樹脂５０に覆われている。図２、図３、図５および図６に示すように、露出部１７２Ｂは、被覆部１７２Ａにつながり、かつ封止樹脂５０から露出している。露出部１７２Ｂは、第２方向ｙにおいて第２ダイパッド１０Ｂから遠ざかる側に延びている。露出部１７２Ｂの表面には、たとえば錫めっきが施されている。 As shown in FIG. 3, the fifth terminal lead 172 includes a covered portion 172A and an exposed portion 172B. The covering portion 172A is covered with a sealing resin 50. As shown in FIGS. 2, 3, 5, and 6, the exposed portion 172B is connected to the covering portion 172A and is exposed from the sealing resin 50. The exposed portion 172B extends away from the second die pad 10B in the second direction y. The surface of the exposed portion 172B is plated with tin, for example.
　第６端子リード１８１は、図３に示すように、第２方向ｙにおいて第１ダイパッド１０Ａから離れて位置し、かつ第１方向ｘにおいて第２端子リード１５と第４端子リード１７１との間に位置する。第７端子リード１８２は、図３に示すように、第２方向ｙにおいて第２ダイパッド１０Ｂから離れて位置し、かつ第１方向ｘにおいて第３端子リード１６と第５端子リード１７２との間に位置する。第６端子リード１８１は、第１半導体素子２１の第１主面電極２１１（ソース電極）に導通している。第６端子リード１８１には、第１半導体素子２１の第１主面電極２１１に流れる電流に応じた電圧が印加される。第７端子リード１８２は、第２半導体素子２２の第２主面電極２２１（ソース電極）に導通している。第７端子リード１８２には、第２半導体素子２２の第２主面電極２２１（ソース電極）に流れる電流に応じた電圧が印加される。 As shown in FIG. 3, the sixth terminal lead 181 is located away from the first die pad 10A in the second direction y, and between the second terminal lead 15 and the fourth terminal lead 171 in the first direction x. To position. As shown in FIG. 3, the seventh terminal lead 182 is located away from the second die pad 10B in the second direction y, and between the third terminal lead 16 and the fifth terminal lead 172 in the first direction x. To position. The sixth terminal lead 181 is electrically connected to the first main surface electrode 211 (source electrode) of the first semiconductor element 21 . A voltage corresponding to the current flowing through the first main surface electrode 211 of the first semiconductor element 21 is applied to the sixth terminal lead 181 . The seventh terminal lead 182 is electrically connected to the second main surface electrode 221 (source electrode) of the second semiconductor element 22 . A voltage corresponding to the current flowing through the second main surface electrode 221 (source electrode) of the second semiconductor element 22 is applied to the seventh terminal lead 182.
　図３に示すように、第６端子リード１８１は、被覆部１８１Ａおよび露出部１８１Ｂを含む。被覆部１８１Ａは、封止樹脂５０に覆われている。図２、図３、図５および図６に示すように、露出部１８１Ｂは、被覆部１８１Ａにつながり、かつ封止樹脂５０の第３側面５５から露出している。露出部１８１Ｂは、第２方向ｙにおいて第１ダイパッド１０Ａから遠ざかる側に延びている。露出部１８１Ｂの表面には、たとえば錫めっきが施されている。 As shown in FIG. 3, the sixth terminal lead 181 includes a covering portion 181A and an exposed portion 181B. The covering portion 181A is covered with a sealing resin 50. As shown in FIGS. 2, 3, 5, and 6, the exposed portion 181B is connected to the covering portion 181A and exposed from the third side surface 55 of the sealing resin 50. The exposed portion 181B extends away from the first die pad 10A in the second direction y. For example, tin plating is applied to the surface of the exposed portion 181B.
　図３に示すように、第７端子リード１８２は、被覆部１８２Ａおよび露出部１８２Ｂを含む。被覆部１８２Ａは、封止樹脂５０に覆われている。図２、図３、図５および図６に示すように、露出部１８２Ｂは、被覆部１８２Ａにつながり、かつ封止樹脂５０の第３側面５５から露出している。露出部１８２Ｂは、第２方向ｙにおいて第２ダイパッド１０Ｂから遠ざかる側に延びている。露出部１８２Ｂの表面には、たとえば錫めっきが施されている。 As shown in FIG. 3, the seventh terminal lead 182 includes a covered portion 182A and an exposed portion 182B. The covering portion 182A is covered with a sealing resin 50. As shown in FIGS. 2, 3, 5, and 6, the exposed portion 182B is connected to the covering portion 182A and exposed from the third side surface 55 of the sealing resin 50. The exposed portion 182B extends away from the second die pad 10B in the second direction y. For example, tin plating is applied to the surface of the exposed portion 182B.
　図６に示すように、半導体装置Ａ１０において、第１端子リード１４の露出部１４Ｂ、第２端子リード１５の露出部１５Ｂおよび第３端子リード１６の露出部１６Ｂの各高さｈは、いずれも同一である。さらに、これらの各厚さは、いずれも同一である。このため、第１方向ｘに沿って視て、第１端子リード１４の少なくとも一部（露出部１４Ｂ）が、第２端子リード１５および第３端子リード１６の各々に重なる（図７参照）。 As shown in FIG. 6, in the semiconductor device A10, each height h of the exposed portion 14B of the first terminal lead 14, the exposed portion 15B of the second terminal lead 15, and the exposed portion 16B of the third terminal lead 16 is are the same. Furthermore, each of these thicknesses are the same. Therefore, when viewed along the first direction x, at least a portion (exposed portion 14B) of the first terminal lead 14 overlaps each of the second terminal lead 15 and the third terminal lead 16 (see FIG. 7).
　第１導通部材３１は、図３に示すように、第１半導体素子２１の第１主面電極２１１と第２ダイパッド１０Ｂとに接合されている。これにより、第１主面電極２１１は、第２ダイパッド１０Ｂ、および第２半導体素子２２の裏面電極２２３に導通している。第１導通部材３１の組成は、銅を含む。半導体装置Ａ１０においては、第１導通部材３１は、金属クリップである。第１導通部材３１は、第１本体部３１１、第１接合部３１２、および第２接合部３１３を有する。 As shown in FIG. 3, the first conductive member 31 is joined to the first main surface electrode 211 of the first semiconductor element 21 and the second die pad 10B. Thereby, the first main surface electrode 211 is electrically connected to the second die pad 10B and the back surface electrode 223 of the second semiconductor element 22. The composition of the first conductive member 31 includes copper. In the semiconductor device A10, the first conductive member 31 is a metal clip. The first conductive member 31 has a first main body portion 311 , a first joint portion 312 , and a second joint portion 313 .
　図３に示すように、第１本体部３１１は、第１導通部材３１の主要部をなしている。第１本体部３１１は、第１方向ｘに延びている。図示された例では、第１本体部３１１は、平面視において、第１半導体素子２１と第２半導体素子２２との間で直線状に延びる。図８に示すように、第１本体部３１１は、第１ダイパッド１０Ａと第２ダイパッド１０Ｂとの間を跨いでいる。図示された例では、第１本体部３１１の第１接合部３１２に繋がる側の端部は、二股に分かれている。 As shown in FIG. 3, the first main body portion 311 constitutes the main part of the first conductive member 31. The first main body portion 311 extends in the first direction x. In the illustrated example, the first main body portion 311 extends linearly between the first semiconductor element 21 and the second semiconductor element 22 in plan view. As shown in FIG. 8, the first main body portion 311 straddles between the first die pad 10A and the second die pad 10B. In the illustrated example, the end of the first main body portion 311 on the side connected to the first joint portion 312 is bifurcated.
　図３、図４および図１１に示すように、第１接合部３１２は、第１半導体素子２１の第１主面電極２１１に接合されている。第１接合部３１２は、２つの第１帯状部３１２ａを含む。図３、図４および図８に示すように、２つの第１帯状部３１２ａは、第２方向ｙにおいて互いに離れて位置する。２つの第１帯状部３１２ａの各々は、第１方向ｘを長手方向とする。２つの第１帯状部３１２ａは、平面視において、互いに平行に配置される。図示された例では、先述の第１本体部３１１の第１接合部３１２に繋がる端部は、二股に分かれて、２つの第１帯状部３１２ａのうちの対応する１つにそれぞれ繋がる。この例とは異なり、第１本体部３１１の第１接合部３１２に繋がる端部が二股に分かれておらず、第１接合部３１２が１つの矩形状の部位（２つの第１帯状部３１２ａが連結された構成）であってもよい。平面視における第１接合部３１２の面積（２つの第１帯状部３１２ａの各面積合計）は、平面視における第１主面電極２１１の面積のたとえば１０％以上１００％以下である。 As shown in FIGS. 3, 4, and 11, the first bonding portion 312 is bonded to the first main surface electrode 211 of the first semiconductor element 21. The first joint portion 312 includes two first strip portions 312a. As shown in FIGS. 3, 4, and 8, the two first strip portions 312a are located apart from each other in the second direction y. Each of the two first strip portions 312a has the first direction x as its longitudinal direction. The two first strip portions 312a are arranged parallel to each other in plan view. In the illustrated example, the end portion of the first main body portion 311 connected to the first joint portion 312 is bifurcated and connected to a corresponding one of the two first strip portions 312a. Unlike this example, the end portion of the first main body portion 311 connected to the first joint portion 312 is not divided into two, and the first joint portion 312 is a single rectangular portion (the two first strip portions 312a are (concatenated configuration). The area of the first joint portion 312 in plan view (the total area of the two first strip portions 312a) is, for example, 10% or more and 100% or less of the area of the first main surface electrode 211 in plan view.
　図３および図１３に示すように、第２接合部３１３は、第２ダイパッド１０Ｂの第１座面１０３に接合されている。第２接合部３１３は、第２方向ｙに延びている。第２接合部３１３の少なくとも一部が、第１座面１０３と、第２ダイパッド１０Ｂの第１起立面１０４とにより規定された領域に収納されている。第２接合部３１３は、第１本体部３１１に繋がる。第２接合部３１３は、第１本体部３１１を間に挟んで第１接合部３１２とは反対側に位置する。 As shown in FIGS. 3 and 13, the second joint portion 313 is joined to the first seat surface 103 of the second die pad 10B. The second joint 313 extends in the second direction y. At least a portion of the second joint portion 313 is accommodated in a region defined by the first seat surface 103 and the first upright surface 104 of the second die pad 10B. The second joint portion 313 is connected to the first main body portion 311 . The second joint portion 313 is located on the opposite side of the first joint portion 312 with the first main body portion 311 in between.
　半導体装置Ａ１０は、図９および図１１に示すように、第１接合層３３をさらに備える。第１接合層３３は、第１半導体素子２１の第１主面電極２１１と、第１接合部３１２の２つの第１帯状部３１２ａとの間に介在している。第１接合層３３は、第１主面電極２１１と、第１接合部３１２（２つの第１帯状部３１２ａ）とを接合する。第１接合層３３は、導電性を有する。第１接合層３３は、たとえばはんだである。この他、第１接合層３３は、焼結金属でもよい。 The semiconductor device A10 further includes a first bonding layer 33, as shown in FIGS. 9 and 11. The first bonding layer 33 is interposed between the first main surface electrode 211 of the first semiconductor element 21 and the two first strips 312a of the first bonding portion 312. The first bonding layer 33 bonds the first main surface electrode 211 and the first bonding portion 312 (the two first strip portions 312a). The first bonding layer 33 has conductivity. The first bonding layer 33 is, for example, solder. In addition, the first bonding layer 33 may be made of sintered metal.
　一対の第１帯状部３１２ａの各々の厚さｔは、０．１ｍｍ以上、かつ第１接合層３３の最大厚さＴmaxの２倍以下である。第１接合層３３の最大厚さＴmaxは、第１半導体素子２１の厚さよりも大きい。 The thickness t of each of the pair of first strip portions 312a is at least 0.1 mm and at most twice the maximum thickness Tmax of the first bonding layer 33. The maximum thickness Tmax of the first bonding layer 33 is greater than the thickness of the first semiconductor element 21.
　半導体装置Ａ１０は、図９および図１３に示すように、第２接合層３４をさらに備える。第２接合層３４は、第２ダイパッド１０Ｂの第１座面１０３と、第２接合部３１３との間に介在している。第２接合層３４は、第２ダイパッド１０Ｂと第２接合部３１３とを接合する。第２接合層３４は、導電性を有する。第２接合層３４は、たとえばはんだである。この他、第２接合層３４は、焼結金属でもよい。 The semiconductor device A10 further includes a second bonding layer 34, as shown in FIGS. 9 and 13. The second bonding layer 34 is interposed between the first seat surface 103 of the second die pad 10B and the second bonding portion 313. The second bonding layer 34 bonds the second die pad 10B and the second bonding portion 313. The second bonding layer 34 has conductivity. The second bonding layer 34 is, for example, solder. In addition, the second bonding layer 34 may be made of sintered metal.
　第２導通部材３２は、図３に示すように、第２半導体素子２２の第２主面電極２２１と、第１端子リード１４の被覆部１４Ａとに接合されている。これにより、第２主面電極２２１は、第１端子リード１４に導通している。第２導通部材３２の組成は、銅を含む。半導体装置Ａ１０においては、第２導通部材３２は、金属クリップである。第２導通部材３２は、第２本体部３２１、第３接合部３２２、および第４接合部３２３を有する。 As shown in FIG. 3, the second conductive member 32 is joined to the second main surface electrode 221 of the second semiconductor element 22 and the covering portion 14A of the first terminal lead 14. Thereby, the second main surface electrode 221 is electrically connected to the first terminal lead 14. The composition of the second conductive member 32 includes copper. In the semiconductor device A10, the second conductive member 32 is a metal clip. The second conductive member 32 has a second main body portion 321 , a third joint portion 322 , and a fourth joint portion 323 .
　図３に示すように、第２本体部３２１は、第２導通部材３２の主要部をなしている。厚さ方向ｚに沿って視て、第２本体部３２１は、鉤状に屈曲している。厚さ方向ｚに沿って視て、第１本体部３１１は、第２ダイパッド１０Ｂの主面１０１に重なっている。 As shown in FIG. 3, the second main body portion 321 constitutes the main part of the second conductive member 32. The second main body portion 321 is bent into a hook shape when viewed along the thickness direction z. When viewed along the thickness direction z, the first main body portion 311 overlaps the main surface 101 of the second die pad 10B.
　図４に示すように、第２本体部３２１は、第１延出部３２１ａ、第２延出部３２１ｃ、および第３延出部３２１ｅを含む。第１延出部３２１ａは、第１基端３２１ｂを有する。第１基端３２１ｂは、第３接合部３２２に繋がる端縁である。第１延出部３２１ａは、第１基端３２１ｂから第２方向ｙに延びる。本実施形態では、第１延出部３２１ａの一部（第１基端３２１ｂを含む端部）は、厚さ方向ｚに屈曲する。第２延出部３２１ｃは、第２基端３２１ｄを有する。第２基端３２１ｄは、第１延出部３２１ａに繋がる端縁である。第２延出部３２１ｃは、第２基端３２１ｄから第１方向ｘに延びる。図４に示すように、第２延出部３２１ｃは、平面視において、第２ダイパッド１０Ｂの第４端面１１４に交差する。このような構成により、第２導通部材３２は、平面視において、第２ダイパッド１０Ｂの第４隅部端面１２４に重ならない。第３延出部３２１ｅは、第３基端３２１ｆを有する。第３基端３２１ｆは、第３延出部３２１ｅに繋がる端縁である。第３延出部３２１ｅは、第３基端３２１ｆから第２方向ｙに延びる。本実施形態では、第３延出部３２１ｅの一部（第３基端３２１ｆと反対側の端部）は、厚さ方向ｚに屈曲する。 As shown in FIG. 4, the second main body portion 321 includes a first extending portion 321a, a second extending portion 321c, and a third extending portion 321e. The first extending portion 321a has a first base end 321b. The first base end 321b is an edge connected to the third joint portion 322. The first extending portion 321a extends in the second direction y from the first base end 321b. In this embodiment, a part of the first extending portion 321a (the end including the first base end 321b) is bent in the thickness direction z. The second extending portion 321c has a second base end 321d. The second base end 321d is an edge connected to the first extension portion 321a. The second extending portion 321c extends in the first direction x from the second base end 321d. As shown in FIG. 4, the second extending portion 321c intersects with the fourth end surface 114 of the second die pad 10B in plan view. With such a configuration, the second conductive member 32 does not overlap the fourth corner end surface 124 of the second die pad 10B in plan view. The third extending portion 321e has a third base end 321f. The third base end 321f is an edge connected to the third extending portion 321e. The third extending portion 321e extends in the second direction y from the third base end 321f. In this embodiment, a part of the third extending portion 321e (the end opposite to the third base end 321f) is bent in the thickness direction z.
　図３および図１４に示すように、第３接合部３２２は、第１端子リード１４の第２座面１４Ｃに接合されている。第３接合部３２２は、第１方向ｘに延びている。第３接合部３２２の少なくとも一部が、第２座面１４Ｃと、第１端子リード１４の第２起立面１４Ｄとにより規定された領域に収納されている。第３接合部３２２は、第２本体部３２１（第１延出部３２１ａ）に繋がる。第３接合部３２２は、第２本体部３２１を間に挟んで第４接合部３２３とは反対側に位置する。 As shown in FIGS. 3 and 14, the third joint portion 322 is joined to the second bearing surface 14C of the first terminal lead 14. The third joint portion 322 extends in the first direction x. At least a portion of the third joint portion 322 is accommodated in a region defined by the second seat surface 14C and the second upright surface 14D of the first terminal lead 14. The third joint portion 322 is connected to the second main body portion 321 (first extension portion 321a). The third joint portion 322 is located on the opposite side of the fourth joint portion 323 with the second main body portion 321 in between.
　図３および図１２に示すように、第４接合部３２３は、第２半導体素子２２の第２主面電極２２１に接合されている。第４接合部３２３は、２つの第２帯状部３２３ａを含む。図３および図１０に示すように、２つの第２帯状部３２３ａは、第２方向ｙにおいて互いに離れて位置する。２つの第２帯状部３２３ａの各々は、第１方向ｘを長手方向とする。２つの第２帯状部３２３ａは、平面視において、互いに平行に配置される。図示された例では、先述の第２本体部３２１の第４接合部３２３に繋がる端部は、二股に分かれて、２つの第２帯状部３２３ａのうちの対応する１つにそれぞれ繋がる。この例とは異なり、第２本体部３２１の第４接合部３２３に繋がる端部が二股に分かれておらず、第４接合部３２３が１つの矩形状の部位（２つの第２帯状部３２３ａが連結された構成）であってもよい。平面視における第４接合部３２３の面積（２つの第２帯状部３２３ａの各面積合計）は、平面視における第２主面電極２２１の面積のたとえば１０％以上１００％以下である。 As shown in FIGS. 3 and 12, the fourth bonding portion 323 is bonded to the second main surface electrode 221 of the second semiconductor element 22. The fourth joint portion 323 includes two second strip portions 323a. As shown in FIGS. 3 and 10, the two second strip portions 323a are located apart from each other in the second direction y. Each of the two second strip portions 323a has the first direction x as its longitudinal direction. The two second strip portions 323a are arranged parallel to each other in plan view. In the illustrated example, the end portion of the second main body portion 321 connected to the fourth joint portion 323 is bifurcated and connected to a corresponding one of the two second band portions 323a. Unlike this example, the end of the second main body part 321 connected to the fourth joint part 323 is not divided into two, and the fourth joint part 323 is one rectangular part (the two second strip parts 323a are (concatenated configuration). The area of the fourth joint portion 323 (the total area of the two second strip portions 323a) in plan view is, for example, 10% or more and 100% or less of the area of the second main surface electrode 221 in plan view.
　半導体装置Ａ１０は、図９および図１４に示すように、第３接合層３５をさらに備える。第３接合層３５は、第１端子リード１４の第２座面１４Ｃと、第３接合部３２２との間に介在している。第３接合層３５は、第１端子リード１４の被覆部１４Ａと、第３接合部３２２とを接合する。第３接合層３５は、導電性を有する。第３接合層３５は、たとえばはんだである。この他、第３接合層３５は、焼結金属でもよい。 The semiconductor device A10 further includes a third bonding layer 35, as shown in FIGS. 9 and 14. The third bonding layer 35 is interposed between the second seating surface 14C of the first terminal lead 14 and the third bonding portion 322. The third bonding layer 35 bonds the covering portion 14A of the first terminal lead 14 and the third bonding portion 322. The third bonding layer 35 has conductivity. The third bonding layer 35 is, for example, solder. In addition, the third bonding layer 35 may be made of sintered metal.
　半導体装置Ａ１０は、図９および図１２に示すように、第４接合層３６をさらに備える。第４接合層３６は、第２半導体素子２２の第２主面電極２２１と、第４接合部３２３の２つの第２帯状部３２３ａとの間に介在している。第４接合層３６は、第２半導体素子２２の第２主面電極２２１と、第４接合部３２３（２つの第２帯状部３２３ａの各々）とを接合する。第４接合層３６は、導電性を有する。第４接合層３６は、たとえばはんだである。この他、第４接合層３６は、焼結金属でもよい。 The semiconductor device A10 further includes a fourth bonding layer 36, as shown in FIGS. 9 and 12. The fourth bonding layer 36 is interposed between the second main surface electrode 221 of the second semiconductor element 22 and the two second strips 323a of the fourth bonding portion 323. The fourth bonding layer 36 bonds the second main surface electrode 221 of the second semiconductor element 22 and the fourth bonding portion 323 (each of the two second strip portions 323a). The fourth bonding layer 36 has conductivity. The fourth bonding layer 36 is, for example, solder. In addition, the fourth bonding layer 36 may be made of sintered metal.
　第４接合部３２３（２つの第２帯状部３２３ａの各々）厚さｔは、０．１ｍｍ以上、かつ第４接合層３６の最大厚さＴmaxの２倍以下である。第４接合層３６の最大厚さＴmaxは、第２半導体素子２２の厚さよりも大きい。 The thickness t of the fourth bonding portion 323 (each of the two second strip portions 323a) is 0.1 mm or more and twice the maximum thickness Tmax of the fourth bonding layer 36 or less. The maximum thickness Tmax of the fourth bonding layer 36 is greater than the thickness of the second semiconductor element 22.
　一対の第１接続部材４１Ａ，４１Ｂおよび一対の第２接続部材４２Ａ，４２Ｂの各々は、たとえばボンディングワイヤである。一対の第１接続部材４１Ａ，４１Ｂおよび一対の第２接続部材４２Ａ，４２Ｂの各組成は、金を含む。この他、一対の第１接続部材４１Ａ，４１Ｂおよび一対の第２接続部材４２Ａ，４２Ｂの各組成は、銅を含む場合でもよいし、アルミニウム（Ａｌ）を含む場合でもよい。 Each of the pair of first connecting members 41A, 41B and the pair of second connecting members 42A, 42B is, for example, a bonding wire. Each composition of the pair of first connecting members 41A, 41B and the pair of second connecting members 42A, 42B includes gold. In addition, the compositions of the pair of first connecting members 41A, 41B and the pair of second connecting members 42A, 42B may include copper or aluminum (Al).
　第１接続部材４１Ａは、図３に示すように、第１半導体素子２１の主面電極２１２と、第４端子リード１７１の被覆部１７１Ａとに接合されている。これにより、第４端子リード１７１は、第１半導体素子２１の主面電極２１２に導通する。第１接続部材４１Ｂは、図３に示すように、第２半導体素子２２の主面電極２２２と、第５端子リード１７２の被覆部１７２Ａとに接合されている。これにより、第５端子リード１７２は、第２半導体素子２２の主面電極２２２に導通する。 As shown in FIG. 3, the first connecting member 41A is joined to the main surface electrode 212 of the first semiconductor element 21 and the covering portion 171A of the fourth terminal lead 171. Thereby, the fourth terminal lead 171 is electrically connected to the main surface electrode 212 of the first semiconductor element 21 . The first connecting member 41B is joined to the main surface electrode 222 of the second semiconductor element 22 and the covering portion 172A of the fifth terminal lead 172, as shown in FIG. Thereby, the fifth terminal lead 172 is electrically connected to the main surface electrode 222 of the second semiconductor element 22.
　第２接続部材４２Ａは、図３に示すように、第１半導体素子２１の第１主面電極２１１と、第６端子リード１８１の被覆部１８１Ａとに接合されている。これにより、第６端子リード１８１は、第１半導体素子２１の第１主面電極２１１に導通する。第２接続部材４２Ｂは、図３に示すように、第２半導体素子２２の第２主面電極２２１と、第７端子リード１８２の被覆部１８２Ａとに接合されている。これにより、第７端子リード１８２は、第２半導体素子２２の第２主面電極２２１に導通する。 As shown in FIG. 3, the second connecting member 42A is joined to the first main surface electrode 211 of the first semiconductor element 21 and the covering portion 181A of the sixth terminal lead 181. Thereby, the sixth terminal lead 181 is electrically connected to the first main surface electrode 211 of the first semiconductor element 21 . The second connecting member 42B is joined to the second main surface electrode 221 of the second semiconductor element 22 and the covering portion 182A of the seventh terminal lead 182, as shown in FIG. Thereby, the seventh terminal lead 182 is electrically connected to the second main surface electrode 221 of the second semiconductor element 22 .
　以上のように構成された半導体装置Ａ１０は、図１９に示すように、第１半導体素子２１の第１主面電極２１１と第２半導体素子２２の裏面電極２２３とが、電気的に接続されている。したがって、半導体装置Ａ１０は、２つのトランジスタ（第１半導体素子２１および第２半導体素子２２）によるハーフブリッジ回路を構成する。 In the semiconductor device A10 configured as above, as shown in FIG. 19, the first main surface electrode 211 of the first semiconductor element 21 and the back surface electrode 223 of the second semiconductor element 22 are electrically connected. There is. Therefore, the semiconductor device A10 forms a half-bridge circuit including two transistors (the first semiconductor element 21 and the second semiconductor element 22).
　第１実施形態にかかる半導体装置Ａ１０の作用および効果は、次の通りである。 The functions and effects of the semiconductor device A10 according to the first embodiment are as follows.
　半導体装置Ａ１０は、第１半導体素子２１、第２半導体素子２２、および、封止樹脂５０を備える。封止樹脂５０は、第１半導体素子２１および第２半導体素子２２を覆う。この構成によれば、半導体装置Ａ１０は、２つの半導体素子（第１半導体素子２１および第２半導体素子２２）が１つの封止樹脂５０により１パッケージ化される。したがって、半導体装置Ａ１０は、当該半導体装置Ａ１０を実装する回路基板への実装面積を削減することが可能となる。 The semiconductor device A10 includes a first semiconductor element 21, a second semiconductor element 22, and a sealing resin 50. The sealing resin 50 covers the first semiconductor element 21 and the second semiconductor element 22. According to this configuration, in the semiconductor device A10, two semiconductor elements (the first semiconductor element 21 and the second semiconductor element 22) are packaged with one sealing resin 50. Therefore, the semiconductor device A10 can reduce the mounting area on the circuit board on which the semiconductor device A10 is mounted.
　半導体装置Ａ１０では、封止樹脂５０は、複数の凹部５８１を有する。複数の凹部５８１の各々は、樹脂主面５１から厚さ方向ｚに凹む。複数の凹部５８１は、平面視において、第１ダイパッド１０Ａに重なる。複数の凹部５８１は、上述の通り、半導体装置Ａ１０の製造時において、第１ダイパッド１０Ａを複数のピンで固定することによって形成される痕である。したがって、半導体装置Ａ１０の製造時において、複数のピンで第１ダイパッド１０Ａが押さえられているので、当該製造時に第１ダイパッド１０Ａが揺動することを抑制できる。これにより、第１ダイパッド１０Ａの裏面１０２と封止樹脂５０を形成するための金型との間に隙間が発生することを抑制できるので、封止樹脂５０に樹脂バリが発生することを抑制できる。 In the semiconductor device A10, the sealing resin 50 has a plurality of recesses 581. Each of the plurality of recesses 581 is recessed from the main resin surface 51 in the thickness direction z. The plurality of recesses 581 overlap the first die pad 10A in plan view. As described above, the plurality of recesses 581 are marks formed by fixing the first die pad 10A with a plurality of pins during manufacturing of the semiconductor device A10. Therefore, since the first die pad 10A is held down by the plurality of pins during the manufacture of the semiconductor device A10, it is possible to suppress the first die pad 10A from swinging during the manufacture. Thereby, it is possible to suppress the generation of a gap between the back surface 102 of the first die pad 10A and the mold for forming the sealing resin 50, so it is possible to suppress the generation of resin burrs on the sealing resin 50. .
　半導体装置Ａ１０では、封止樹脂５０は、複数の凹部５８２を有する。複数の凹部５８２の各々は、樹脂主面５１から厚さ方向ｚに凹む。複数の凹部５８２は、平面視において、第２ダイパッド１０Ｂに重なる。複数の凹部５８２は、上述の通り、半導体装置Ａ１０の製造時において、第２ダイパッド１０Ｂを複数のピンで固定することによって形成される痕である。したがって、半導体装置Ａ１０の製造時において、複数のピンで第２ダイパッド１０Ｂが押さえられているので、当該製造時に第２ダイパッド１０Ｂが揺動することを抑制できる。これにより、第２ダイパッド１０Ｂの裏面１０２と封止樹脂５０を形成するための金型との間に隙間が発生することを抑制できるので、封止樹脂５０に樹脂バリが発生することを抑制できる。 In the semiconductor device A10, the sealing resin 50 has a plurality of recesses 582. Each of the plurality of recesses 582 is recessed from the main resin surface 51 in the thickness direction z. The plurality of recesses 582 overlap the second die pad 10B in plan view. As described above, the plurality of recesses 582 are marks formed by fixing the second die pad 10B with a plurality of pins during manufacturing of the semiconductor device A10. Therefore, since the second die pad 10B is held down by the plurality of pins during the manufacture of the semiconductor device A10, it is possible to suppress the second die pad 10B from swinging during the manufacture. Thereby, it is possible to suppress the generation of a gap between the back surface 102 of the second die pad 10B and the mold for forming the sealing resin 50, so it is possible to suppress the generation of resin burrs on the sealing resin 50. .
　半導体装置Ａ１０では、第２導通部材３２は、第３接合部３２２と第４接合部３２３とを繋ぐ第２本体部３２１を含む。そして、第２本体部３２１は、平面視において屈曲する。図３から理解されるように、仮に、第３接合部３２２と第４接合部３２３とを直線的に接続すると、平面視において、第２本体部３２１が、第２ダイパッド１０Ｂの四隅の一つ（第２ダイパッド１０Ｂの第４隅部端面１２４）に重なる。この場合、半導体装置Ａ１０の製造時において第２ダイパッド１０Ｂを固定するピンが、第２ダイパッド１０Ｂの四隅を押さえることが困難である。なお、ピンにより、第２ダイパッド１０Ｂの四隅を押さえることは、上記第２ダイパッド１０Ｂの揺動を抑制する上で好ましい。一方で、半導体装置Ａ１０では、第２本体部３２１を屈曲させることで、平面視において、第２本体部３２１を、第２ダイパッド１０Ｂの四隅の一つ（第２ダイパッド１０Ｂの第４隅部端面１２４）に重ならなくすることが可能となる。つまり、半導体装置Ａ１０は、製造時における第２ダイパッド１０Ｂの揺動を抑制する上で好ましい。 In the semiconductor device A10, the second conductive member 32 includes a second main body portion 321 that connects a third joint portion 322 and a fourth joint portion 323. The second main body portion 321 is bent in plan view. As can be understood from FIG. 3, if the third joint part 322 and the fourth joint part 323 are connected linearly, the second main body part 321 will be located at one of the four corners of the second die pad 10B in plan view. (the fourth corner end surface 124 of the second die pad 10B). In this case, it is difficult for the pins that fix the second die pad 10B to press the four corners of the second die pad 10B during manufacturing of the semiconductor device A10. Note that it is preferable to press the four corners of the second die pad 10B with pins in order to suppress the swinging of the second die pad 10B. On the other hand, in the semiconductor device A10, by bending the second body part 321, the second body part 321 can be bent at one of the four corners of the second die pad 10B (the fourth corner end face of the second die pad 10B) in plan view. 124) so that they do not overlap. In other words, the semiconductor device A10 is preferable in terms of suppressing the swinging of the second die pad 10B during manufacturing.
　半導体装置Ａ１０では、第２導通部材３２の第２本体部３２１は、第１延出部３２１ａ、第２延出部３２１ｃおよび第３延出部３２１ｅを含む。第１延出部３２１ａは、第３接合部３２２から第２方向ｙに延び、第２延出部３２１ｃは、第１延出部３２１ａから第１方向ｘに延び、第３延出部３２１ｅは、第２延出部３２１ｃから第２方向ｙに延びる。半導体装置Ａ１０では、このように、第２本体部３２１を、平面視において、複数回屈曲させることで、先述のように、製造時において、第２ダイパッド１０Ｂの四隅を複数のピンで固定することが可能となるとともに、第１本体部３１１を、第１半導体素子２１と第２半導体素子２２との間に直線的に形成することが可能となる。 In the semiconductor device A10, the second main body portion 321 of the second conductive member 32 includes a first extending portion 321a, a second extending portion 321c, and a third extending portion 321e. The first extending portion 321a extends from the third joint portion 322 in the second direction y, the second extending portion 321c extends from the first extending portion 321a in the first direction x, and the third extending portion 321e extends from the first extending portion 321a in the first direction x. , extending in the second direction y from the second extending portion 321c. In the semiconductor device A10, by bending the second body portion 321 multiple times in plan view, the four corners of the second die pad 10B can be fixed with a plurality of pins during manufacturing as described above. It becomes possible to form the first main body part 311 linearly between the first semiconductor element 21 and the second semiconductor element 22.
　以下に、本開示の半導体装置の他の実施形態および変形例について、説明する。各実施形態および各変形例における各部の構成は、技術的な矛盾が生じない範囲において相互に組み合わせ可能である。 Other embodiments and modifications of the semiconductor device of the present disclosure will be described below. The configurations of each part in each embodiment and each modification can be combined with each other within a range that does not cause technical contradiction.
　図２０および図２１は、第１実施形態の第１変形例にかかる半導体装置Ａ１１を示している。半導体装置Ａ１１は、半導体装置Ａ１０と比較して、次の点で異なる。それは、半導体装置Ａ１１の第１半導体素子２１は、トランジスタではなくダイオードである。 20 and 21 show a semiconductor device A11 according to a first modification of the first embodiment. The semiconductor device A11 differs from the semiconductor device A10 in the following points. That is, the first semiconductor element 21 of the semiconductor device A11 is not a transistor but a diode.
　半導体装置Ａ１１の第１半導体素子２１は、第１主面電極２１１および裏面電極２１３を有する。半導体装置Ａ１１の第１半導体素子２１は、図２０に示すように、主面電極２１２を有していない。図２１に示すように、半導体装置Ａ１１の第１半導体素子２１は、ダイオードであって、第１主面電極２１１は、たとえばアノード電極であり、裏面電極２１３は、たとえばカソード電極である。 The first semiconductor element 21 of the semiconductor device A11 has a first main surface electrode 211 and a back surface electrode 213. The first semiconductor element 21 of the semiconductor device A11 does not have the main surface electrode 212, as shown in FIG. As shown in FIG. 21, the first semiconductor element 21 of the semiconductor device A11 is a diode, the first main surface electrode 211 is, for example, an anode electrode, and the back surface electrode 213 is, for example, a cathode electrode.
　図２０に示すように、半導体装置Ａ１１は、第１接続部材４１Ａおよび一対の第２接続部材４２Ａ，４２Ｂのいずれも備えていない。この構成では、図２０および図２１に示すように、第４端子リード１７１、第６端子リード１８１および第７端子リード１８２はそれぞれ、第１半導体素子２１および第２半導体素子２２のいずれにも導通しない。したがって、半導体装置Ａ１１では、第４端子リード１７１、第６端子リード１８１および第７端子リード１８２はそれぞれ、ノンコネクト端子である。なお、図２０に示す例では、半導体装置Ａ１１は、一対の第２接続部材４２Ａ，４２Ｂのいずれも備えていないが、この例とは異なる構成において、半導体装置Ａ１１は、半導体装置Ａ１０と同様の一対の第２接続部材４２Ａ，４２Ｂを備えていてもよい。 As shown in FIG. 20, the semiconductor device A11 does not include either the first connection member 41A or the pair of second connection members 42A and 42B. In this configuration, as shown in FIGS. 20 and 21, the fourth terminal lead 171, the sixth terminal lead 181, and the seventh terminal lead 182 are electrically connected to both the first semiconductor element 21 and the second semiconductor element 22, respectively. do not. Therefore, in the semiconductor device A11, the fourth terminal lead 171, the sixth terminal lead 181, and the seventh terminal lead 182 are each non-connect terminals. Note that in the example shown in FIG. 20, the semiconductor device A11 does not include either of the pair of second connection members 42A, 42B, but in a configuration different from this example, the semiconductor device A11 has the same structure as the semiconductor device A10. A pair of second connection members 42A and 42B may be provided.
　半導体装置Ａ１１は、図２１に示すように、第１半導体素子２１の第１主面電極２１１（アノード電極）と第２半導体素子２２の裏面電極２２３（ドレイン電極）とが、電気的に接続されている。半導体装置Ａ１１では、第１端子リード１４および第２端子リード１５間に印加される電源電圧（直流電圧）に対して、高電圧側がダイオード、低電圧側がトランジスタとなる。半導体装置Ａ１１は、たとえば昇圧型のチョッパー回路として用いられる。 In the semiconductor device A11, as shown in FIG. 21, the first main surface electrode 211 (anode electrode) of the first semiconductor element 21 and the back surface electrode 223 (drain electrode) of the second semiconductor element 22 are electrically connected. ing. In the semiconductor device A11, with respect to the power supply voltage (DC voltage) applied between the first terminal lead 14 and the second terminal lead 15, the high voltage side is a diode and the low voltage side is a transistor. The semiconductor device A11 is used, for example, as a step-up chopper circuit.
　図２２および図２３は、第１実施形態の第２変形例にかかる半導体装置Ａ１２を示している。半導体装置Ａ１２は、半導体装置Ａ１０と比較して、次の点で異なる。それは、半導体装置Ａ１２の第２半導体素子２２は、トランジスタではなくダイオードである。 FIGS. 22 and 23 show a semiconductor device A12 according to a second modification of the first embodiment. The semiconductor device A12 differs from the semiconductor device A10 in the following points. That is, the second semiconductor element 22 of the semiconductor device A12 is not a transistor but a diode.
　半導体装置Ａ１２の第２半導体素子２２は、第２主面電極２２１および裏面電極２２３を有する。半導体装置Ａ１２の第２半導体素子２２は、図２２に示すように、主面電極２２２を有していない。図２３に示すように、半導体装置Ａ１２の第２半導体素子２２は、ダイオードであって、第２主面電極２２１は、たとえばアノード電極であり、裏面電極２２３は、たとえばカソード電極である。 The second semiconductor element 22 of the semiconductor device A12 has a second main surface electrode 221 and a back surface electrode 223. The second semiconductor element 22 of the semiconductor device A12 does not have the main surface electrode 222, as shown in FIG. As shown in FIG. 23, the second semiconductor element 22 of the semiconductor device A12 is a diode, the second main surface electrode 221 is, for example, an anode electrode, and the back surface electrode 223 is, for example, a cathode electrode.
　図２２に示すように、半導体装置Ａ１２は、第１接続部材４１Ｂおよび一対の第２接続部材４２Ａ，４２Ｂのいずれも備えていない。この構成では、図２２および図２３に示すように、第５端子リード１７２、第６端子リード１８１および第７端子リード１８２はそれぞれ、第１半導体素子２１および第２半導体素子２２のいずれにも導通しない。したがって、半導体装置Ａ１２では、第５端子リード１７２、第６端子リード１８１および第７端子リード１８２はそれぞれ、ノンコネクト端子である。なお、図２２に示す例では、半導体装置Ａ１２は、一対の第２接続部材４２Ａ，４２Ｂのいずれも備えていないが、この例とは異なる構成において、半導体装置Ａ１２は、半導体装置Ａ１０と同様の一対の第２接続部材４２Ａ，４２Ｂを備えていてもよい。 As shown in FIG. 22, the semiconductor device A12 does not include either the first connection member 41B or the pair of second connection members 42A, 42B. In this configuration, as shown in FIGS. 22 and 23, the fifth terminal lead 172, the sixth terminal lead 181, and the seventh terminal lead 182 are electrically connected to both the first semiconductor element 21 and the second semiconductor element 22, respectively. do not. Therefore, in the semiconductor device A12, the fifth terminal lead 172, the sixth terminal lead 181, and the seventh terminal lead 182 are each non-connect terminals. Note that in the example shown in FIG. 22, the semiconductor device A12 does not include either of the pair of second connection members 42A, 42B, but in a configuration different from this example, the semiconductor device A12 has the same structure as the semiconductor device A10. A pair of second connection members 42A and 42B may be provided.
　半導体装置Ａ１２は、図２３に示すように、第１半導体素子２１の第１主面電極２１１（ソース電極）と第２半導体素子２２の裏面電極２２３（カソード電極）とが、電気的に接続されている。半導体装置Ａ１２では、第１端子リード１４および第２端子リード１５間に印加される直流電圧に対して、高電圧側がトランジスタ、低電圧側がダイオードとなる。半導体装置Ａ１２は、たとえば降圧型のチョッパー回路として用いられる。 In the semiconductor device A12, as shown in FIG. 23, the first main surface electrode 211 (source electrode) of the first semiconductor element 21 and the back surface electrode 223 (cathode electrode) of the second semiconductor element 22 are electrically connected. ing. In the semiconductor device A12, with respect to the DC voltage applied between the first terminal lead 14 and the second terminal lead 15, the high voltage side is a transistor and the low voltage side is a diode. The semiconductor device A12 is used, for example, as a step-down chopper circuit.
　図２４および図２５は、第１実施形態の第３変形例にかかる半導体装置Ａ１３を示している。半導体装置Ａ１３は、半導体装置Ａ１０と比較して、次の点で異なる。それは、半導体装置Ａ１３の第１半導体素子２１および第２半導体素子２２の各々が、トランジスタではなくダイオードである。 24 and 25 show a semiconductor device A13 according to a third modification of the first embodiment. The semiconductor device A13 differs from the semiconductor device A10 in the following points. That is, each of the first semiconductor element 21 and the second semiconductor element 22 of the semiconductor device A13 is a diode instead of a transistor.
　半導体装置Ａ１３の第１半導体素子２１は、第１主面電極２１１および裏面電極２１３を有する。半導体装置Ａ１３の第１半導体素子２１は、図２４に示すように、主面電極２１２を有していない。図２５に示すように、半導体装置Ａ１３の第１半導体素子２１は、ダイオードであって、第１主面電極２１１は、アノード電極であり、裏面電極２１３は、カソード電極である。また、半導体装置Ａ１３の第２半導体素子２２は、第２主面電極２２１および裏面電極２２３を有する。半導体装置Ａ１３の第２半導体素子２２は、図２４に示すように、主面電極２２２を有していない。図２５に示すように、半導体装置Ａ１３の第２半導体素子２２は、ダイオードであって、第２主面電極２２１は、アノード電極であり、裏面電極２２３は、カソード電極である。 The first semiconductor element 21 of the semiconductor device A13 has a first main surface electrode 211 and a back surface electrode 213. The first semiconductor element 21 of the semiconductor device A13 does not have the main surface electrode 212, as shown in FIG. As shown in FIG. 25, the first semiconductor element 21 of the semiconductor device A13 is a diode, the first main surface electrode 211 is an anode electrode, and the back surface electrode 213 is a cathode electrode. Further, the second semiconductor element 22 of the semiconductor device A13 has a second main surface electrode 221 and a back surface electrode 223. The second semiconductor element 22 of the semiconductor device A13 does not have the main surface electrode 222, as shown in FIG. As shown in FIG. 25, the second semiconductor element 22 of the semiconductor device A13 is a diode, the second main surface electrode 221 is an anode electrode, and the back surface electrode 223 is a cathode electrode.
　図２４に示すように、半導体装置Ａ１３は、一対の第１接続部材４１Ａ，４１Ｂおよび一対の第２接続部材４２Ａ，４２Ｂのいずれも備えていない。この構成では、図２４および図２５に示すように、第４端子リード１７１、第５端子リード１７２、第６端子リード１８１および第７端子リード１８２はそれぞれ、第１半導体素子２１および第２半導体素子２２のいずれにも導通しない。したがって、半導体装置Ａ１３では、第４端子リード１７１、第５端子リード１７２、第６端子リード１８１および第７端子リード１８２はそれぞれ、ノンコネクト端子である。なお、図２４に示す例では、半導体装置Ａ１３は、一対の第２接続部材４２Ａ，４２Ｂのいずれも備えていないが、この例とは異なる構成において、半導体装置Ａ１３は、半導体装置Ａ１０と同様の一対の第２接続部材４２Ａ，４２Ｂを備えていてもよい。 As shown in FIG. 24, the semiconductor device A13 does not include either the pair of first connecting members 41A, 41B and the pair of second connecting members 42A, 42B. In this configuration, as shown in FIGS. 24 and 25, the fourth terminal lead 171, the fifth terminal lead 172, the sixth terminal lead 181, and the seventh terminal lead 182 are connected to the first semiconductor element 21 and the second semiconductor element, respectively. There is no conduction to any of 22. Therefore, in the semiconductor device A13, the fourth terminal lead 171, the fifth terminal lead 172, the sixth terminal lead 181, and the seventh terminal lead 182 are each non-connect terminals. Note that in the example shown in FIG. 24, the semiconductor device A13 does not include either of the pair of second connection members 42A, 42B, but in a configuration different from this example, the semiconductor device A13 has the same structure as the semiconductor device A10. A pair of second connection members 42A and 42B may be provided.
　半導体装置Ａ１３は、図２５に示すように、第１半導体素子２１の第１主面電極２１１（アノード電極）と第２半導体素子２２の裏面電極２２３（カソード電極）とが、電気的に接続されている。半導体装置Ａ１３では、第１端子リード１４および第２端子リード１５間に印加される電源電圧（直流電圧）に対して、高電圧側および低電圧側の両方がダイオードである。半導体装置Ａ１３は、ダイオードのブリッジ回路である。 In the semiconductor device A13, as shown in FIG. 25, the first main surface electrode 211 (anode electrode) of the first semiconductor element 21 and the back surface electrode 223 (cathode electrode) of the second semiconductor element 22 are electrically connected. ing. In the semiconductor device A13, both the high voltage side and the low voltage side with respect to the power supply voltage (DC voltage) applied between the first terminal lead 14 and the second terminal lead 15 are diodes. The semiconductor device A13 is a diode bridge circuit.
　第１実施形態の各変形例にかかる半導体装置Ａ１１～Ａ１３は、半導体装置Ａ１０と同様に、２つの半導体素子（第１半導体素子２１および第２半導体素子２２）が１つの封止樹脂５０により１パッケージ化される。したがって、各半導体装置Ａ１１～Ａ１３は、半導体装置Ａ１０と同様に、当該半導体装置Ａ１１～Ａ１３を実装する回路基板への実装面積を削減することが可能となる。その他、各半導体装置Ａ１１～Ａ１３は、半導体装置Ａ１０と共通する構成により、半導体装置Ａ１０と同様の効果を奏する。 In the semiconductor devices A11 to A13 according to each modification of the first embodiment, two semiconductor elements (the first semiconductor element 21 and the second semiconductor element 22) are sealed together by one sealing resin 50, similarly to the semiconductor device A10. Packaged. Therefore, similarly to the semiconductor device A10, each of the semiconductor devices A11 to A13 can reduce the mounting area on the circuit board on which the semiconductor devices A11 to A13 are mounted. In addition, each of the semiconductor devices A11 to A13 has the same configuration as the semiconductor device A10, and thus achieves the same effects as the semiconductor device A10.
　上記半導体装置Ａ１０～Ａ１３から理解されるように、本開示の半導体装置は、第１半導体素子２１と第２半導体素子２２と組み合わせにより、４種類の電力変換回路（トランジスタによるブリッジ回路、昇圧型のチョッパー回路、降圧型のチョッパー回路、ダイオードによりブリッジ回路）を構成できる。一方で、各端子リード１３および封止樹脂５０などの構成は、各半導体装置Ａ１０～Ａ１３で共通する。したがって、本開示の半導体装置は、パッケージの外観が同じまま、４種類の電力変換回路のいずれかを構成することが可能である。また、本開示の半導体装置は、第１半導体素子２１および第２半導体素子２２の各々がトランジスタであるかダイオードであるかで異なっていても、各端子リード１３および封止樹脂５０の構成をそのまま活用できる。これにより、本開示の半導体装置は、先述の４種類の電力変換回路のいずれであっても、パッケージ構造を共通化することができるので、生産性の向上において、好ましい。 As understood from the above semiconductor devices A10 to A13, the semiconductor device of the present disclosure can be used in four types of power conversion circuits (a bridge circuit using transistors, a boost type It can be configured as a chopper circuit, a step-down chopper circuit, or a bridge circuit using diodes. On the other hand, the configurations of each terminal lead 13, sealing resin 50, etc. are common to each of the semiconductor devices A10 to A13. Therefore, the semiconductor device of the present disclosure can configure any of four types of power conversion circuits while keeping the package appearance the same. Further, in the semiconductor device of the present disclosure, even if each of the first semiconductor element 21 and the second semiconductor element 22 is a transistor or a diode, the configuration of each terminal lead 13 and the sealing resin 50 can be maintained as is. Can be used. As a result, the semiconductor device of the present disclosure can use a common package structure for any of the four types of power conversion circuits described above, which is preferable for improving productivity.
　上記半導体装置Ａ１０～Ａ１３から理解されるように、本開示の半導体装置は、平面視において、第１半導体素子２１の重心が第１ダイパッド１０Ａの中心部に重なるように配置されている。この構成は、第１導通部材３１の共通化において好ましい。同様に、本開示の半導体装置は、平面視において、第２半導体素子２２の重心が第２ダイパッド１０Ｂの中心部に重なるように配置されている。この構成は、第２導通部材３２の共通化において好ましい。 As understood from the semiconductor devices A10 to A13 above, the semiconductor device of the present disclosure is arranged such that the center of gravity of the first semiconductor element 21 overlaps the center of the first die pad 10A in plan view. This configuration is preferable in making the first conductive member 31 common. Similarly, the semiconductor device of the present disclosure is arranged such that the center of gravity of the second semiconductor element 22 overlaps the center of the second die pad 10B in plan view. This configuration is preferable in making the second conductive member 32 common.
　図２６は、第２実施形態にかかる半導体装置Ａ２０を示している。半導体装置Ａ２０は、半導体装置Ａ１０と比較して、次の点で異なる。それは、半導体装置Ａ２０の第１半導体素子２１の平面視サイズが、半導体装置Ａ１０の第１半導体素子２１の平面視サイズよりも小さい。また、半導体装置Ａ２０の第２半導体素子２２の平面視サイズが、半導体装置Ａ１０の第２半導体素子２２の平面視サイズよりも小さい。 FIG. 26 shows a semiconductor device A20 according to the second embodiment. The semiconductor device A20 differs from the semiconductor device A10 in the following points. That is, the size of the first semiconductor element 21 of the semiconductor device A20 in plan view is smaller than the size of the first semiconductor element 21 of the semiconductor device A10 in plan view. Further, the size of the second semiconductor element 22 of the semiconductor device A20 in plan view is smaller than the size of the second semiconductor element 22 of the semiconductor device A10 in plan view.
　半導体装置Ａ２０では、半導体装置Ａ１０と比較して、第１半導体素子２１の平面視サイズが縮小化されたことから、第１導通部材３１の第１接合部３１２の平面視サイズが縮小化されている。なお、半導体装置Ａ２０においても、半導体装置Ａ１０と同様に、平面視における第１接合部３１２の面積（２つの第１帯状部３１２ａの各面積合計）は、平面視における第１主面電極２１１の面積のたとえば１０％以上１００％以下である。一方で、第１導通部材３１の第１本体部３１１の幅は、半導体装置Ａ１０と同じである。 In the semiconductor device A20, since the size of the first semiconductor element 21 in plan view is reduced compared to the semiconductor device A10, the size of the first joint portion 312 of the first conductive member 31 in plan view is reduced. There is. Note that in the semiconductor device A20 as well, similarly to the semiconductor device A10, the area of the first joint portion 312 in plan view (the total area of the two first strip portions 312a) is equal to the area of the first main surface electrode 211 in plan view. For example, it is 10% or more and 100% or less of the area. On the other hand, the width of the first main body portion 311 of the first conductive member 31 is the same as that of the semiconductor device A10.
　また、半導体装置Ａ２０では、半導体装置Ａ１０と比較して、第２半導体素子２２の平面視サイズが縮小化されていることから、第２導通部材３２の第４接合部３２３の平面視サイズが縮小化されている。なお、半導体装置Ａ２０においても、半導体装置Ａ１０と同様に、平面視における第４接合部３２３の面積（２つの第２帯状部３２３ａの各面積合計）は、平面視における第２主面電極２２１の面積のたとえば１０％以上１００％以下である。一方で、第２導通部材３２の第２本体部３２１の幅は、半導体装置Ａ１０と同じである。 In addition, in the semiconductor device A20, since the size of the second semiconductor element 22 in plan view is reduced compared to the semiconductor device A10, the size of the fourth joint 323 of the second conductive member 32 in plan view is reduced. has been made into Note that in the semiconductor device A20 as well, similarly to the semiconductor device A10, the area of the fourth joint portion 323 in plan view (the total area of the two second strip portions 323a) is equal to the area of the second main surface electrode 221 in plan view. For example, it is 10% or more and 100% or less of the area. On the other hand, the width of the second main body portion 321 of the second conductive member 32 is the same as that of the semiconductor device A10.
　図２７は、第２実施形態の変形例にかかる半導体装置Ａ２１を示している。半導体装置Ａ２１は、半導体装置Ａ１０と比較して、次の点で異なる。それは、半導体装置Ａ２１の第１半導体素子２１の平面視サイズが、半導体装置Ａ１０の第１半導体素子２１の平面視サイズよりも大きい。また、半導体装置Ａ２１の第２半導体素子２２の平面視サイズが、半導体装置Ａ１０の第２半導体素子２２の平面視サイズよりも大きい。 FIG. 27 shows a semiconductor device A21 according to a modification of the second embodiment. The semiconductor device A21 differs from the semiconductor device A10 in the following points. The size of the first semiconductor element 21 of the semiconductor device A21 in plan view is larger than the size of the first semiconductor element 21 of the semiconductor device A10 in plan view. Further, the size of the second semiconductor element 22 of the semiconductor device A21 in plan view is larger than the size of the second semiconductor element 22 of the semiconductor device A10 in plan view.
　半導体装置Ａ２１では、半導体装置Ａ１０と比較して、第１半導体素子２１の平面視サイズが拡大化されたことから、第１導通部材３１の第１接合部３１２の平面視サイズが拡大化されている。なお、半導体装置Ａ２１においても、半導体装置Ａ１０と同様に、平面視における第１接合部３１２の面積（２つの第１帯状部３１２ａの各面積合計）は、平面視における第１主面電極２１１の面積のたとえば１０％以上１００％以下である。一方で、第１導通部材３１の第１本体部３１１の幅は、半導体装置Ａ１０と同じである。 In the semiconductor device A21, since the size of the first semiconductor element 21 in plan view is enlarged compared to the semiconductor device A10, the size of the first joint portion 312 of the first conductive member 31 in plan view is enlarged. There is. Note that in the semiconductor device A21 as well, similarly to the semiconductor device A10, the area of the first joint portion 312 in plan view (the total area of the two first strip portions 312a) is equal to the area of the first main surface electrode 211 in plan view. For example, it is 10% or more and 100% or less of the area. On the other hand, the width of the first main body portion 311 of the first conductive member 31 is the same as that of the semiconductor device A10.
　また、半導体装置Ａ２１では、半導体装置Ａ１０と比較して、第２半導体素子２２の平面視サイズが拡大化されていることから、第２導通部材３２の第４接合部３２３の平面視サイズが拡大化されている。なお、半導体装置Ａ２１においても、半導体装置Ａ１０と同様に、平面視における第４接合部３２３の面積（２つの第２帯状部３２３ａの各面積合計）は、平面視における第２主面電極２２１の面積のたとえば１０％以上１００％以下である。一方で、第２導通部材３２の第２本体部３２１の幅は、半導体装置Ａ１０と同じである。 Furthermore, in the semiconductor device A21, since the size of the second semiconductor element 22 in plan view is enlarged compared to the semiconductor device A10, the size of the fourth joint 323 of the second conductive member 32 in plan view is enlarged. has been made into Note that in the semiconductor device A21 as well, similarly to the semiconductor device A10, the area of the fourth joint portion 323 in plan view (the total area of the two second strip portions 323a) is equal to the area of the second main surface electrode 221 in plan view. For example, it is 10% or more and 100% or less of the area. On the other hand, the width of the second main body portion 321 of the second conductive member 32 is the same as that of the semiconductor device A10.
　第２実施形態およびその変形例にかかる各半導体装置Ａ２０，Ａ２１は、半導体装置Ａ１０と同様に、２つの半導体素子（第１半導体素子２１および第２半導体素子２２）が１つの封止樹脂５０により１パッケージ化される。したがって、各半導体装置Ａ２０，Ａ２１は、半導体装置Ａ１０と同様に、当該半導体装置Ａ２０，Ａ２１を実装する回路基板への実装面積を削減することが可能となる。その他、各半導体装置Ａ２０，Ａ２１は、半導体装置Ａ１０と共通する構成により、半導体装置Ａ１０と同様の効果を奏する。 In each of the semiconductor devices A20 and A21 according to the second embodiment and its modification, two semiconductor elements (the first semiconductor element 21 and the second semiconductor element 22) are formed by one sealing resin 50, similarly to the semiconductor device A10. 1 package. Therefore, similarly to the semiconductor device A10, each of the semiconductor devices A20 and A21 can reduce the mounting area on the circuit board on which the semiconductor devices A20 and A21 are mounted. In addition, each of the semiconductor devices A20 and A21 has the same configuration as the semiconductor device A10, and thus achieves the same effects as the semiconductor device A10.
　上記半導体装置Ａ１０，Ａ２０，Ａ２１から理解されるように、本開示の半導体装置においては、平面視における第１接合部３１２の面積（２つの第１帯状部３１２ａの各面積合計）は、平面視における第１主面電極２１１の面積のたとえば１０％以上１００％以下である。この構成によると、第１接合部３１２の平面視サイズを、第１半導体素子２１の平面視サイズに応じた適度な大きさにすることができる。同様に、本開示の半導体装置においては、平面視における第４接合部３２３の面積（２つの第２帯状部３２３ａの各面積合計）は、平面視における第２主面電極２２１の面積のたとえば１０％以上１００％以下である。この構成によると、第４接合部３２３の平面視サイズを、第２半導体素子２２の平面視サイズに応じた適度な大きさにすることができる。 As understood from the semiconductor devices A10, A20, and A21, in the semiconductor device of the present disclosure, the area of the first joint portion 312 in plan view (the total area of the two first strip portions 312a) is For example, it is 10% or more and 100% or less of the area of the first main surface electrode 211 in . According to this configuration, the size of the first joint portion 312 in plan view can be set to an appropriate size according to the size of the first semiconductor element 21 in plan view. Similarly, in the semiconductor device of the present disclosure, the area of the fourth joint portion 323 in plan view (the total area of the two second strip portions 323a) is, for example, 10 times the area of the second main surface electrode 221 in plan view. % or more and 100% or less. According to this configuration, the size of the fourth joint portion 323 in plan view can be set to an appropriate size according to the size of the second semiconductor element 22 in plan view.
　上記半導体装置Ａ１０，Ａ２０，Ａ２１から理解されるように、本開示の半導体装置においては、第１半導体素子２１および第２半導体素子２２の各平面視サイズが異なっていても、第１導通部材３１の第１本体部３１１および第２導通部材３２の第２本体部３２１は、同じ幅である。第１導通部材３１を搬送する際に、搬送用ハンドなどで第１導通部材３１を挟持することがある。この場合、第１本体部３１１を、当該第１本体部３１１の幅方向に挟むことで、搬送用ハンドの調整などが不要となる。このことは、第１半導体素子２１および第２半導体素子２２の各平面視サイズが異なる場合であっても、搬送用ハンドなどの搬送装置を共通化することができるので、生産性の向上において、好ましい。 As understood from the semiconductor devices A10, A20, and A21, in the semiconductor device of the present disclosure, even if the first semiconductor element 21 and the second semiconductor element 22 have different sizes in plan view, the first conductive member 31 The first body part 311 of and the second body part 321 of the second conductive member 32 have the same width. When transporting the first conductive member 31, the first conductive member 31 may be held by a transporting hand or the like. In this case, by sandwiching the first main body part 311 in the width direction of the first main body part 311, adjustment of the conveying hand or the like becomes unnecessary. This means that even if the first semiconductor element 21 and the second semiconductor element 22 have different sizes in plan view, it is possible to use a common transport device such as a transport hand, which improves productivity. preferable.
　図２８は、第３実施形態にかかる半導体装置Ａ３０を示している。半導体装置Ａ３０は、半導体装置Ａ１０と比較して、次の点で異なる。それは、半導体装置Ａ３０は、複数の第１半導体素子２１および複数の第２半導体素子２２を備える。なお、図２８に示す例では、半導体装置Ａ３０は、２つの第１半導体素子２１および２つの第２半導体素子２２を備える。 FIG. 28 shows a semiconductor device A30 according to the third embodiment. The semiconductor device A30 differs from the semiconductor device A10 in the following points. That is, the semiconductor device A30 includes a plurality of first semiconductor elements 21 and a plurality of second semiconductor elements 22. Note that in the example shown in FIG. 28, the semiconductor device A30 includes two first semiconductor elements 21 and two second semiconductor elements 22.
　２つの第１半導体素子２１の各々は、第１ダイパッド１０Ａに搭載される。２つの第１半導体素子２１はそれぞれ、たとえばトランジスタである。２つの第１半導体素子２１は、第２方向ｙに沿って、並んでいる。半導体装置Ａ３０では、平面視において、２つの第１半導体素子２１の重心（合成重心）が、第１ダイパッド１０Ａの中心部に重なる。図２８に示す例では、２つの第１半導体素子２１の各平面視サイズが同じであるが、互いに異なっていてもよい。 Each of the two first semiconductor elements 21 is mounted on the first die pad 10A. Each of the two first semiconductor elements 21 is, for example, a transistor. The two first semiconductor elements 21 are lined up along the second direction y. In the semiconductor device A30, the centers of gravity of the two first semiconductor elements 21 (combined center of gravity) overlap the center of the first die pad 10A in plan view. In the example shown in FIG. 28, the two first semiconductor elements 21 have the same size in plan view, but may be different from each other.
　半導体装置Ａ３０は、２つの第１半導体素子２１を備えることから、半導体装置Ａ１０と比較して、次の点も異なる。第１に、半導体装置Ａ３０の第１導通部材３１は、２つの第１接合部３１２を含む。２つの第１接合部３１２は、第１本体部３１１に繋がる。第１本体部３１１のうちの２つの第１接合部３１２に繋がる端部は、二股に分かれている。２つの第１接合部３１２はそれぞれ、２つの第１半導体素子２１のうちの対応する１つに接合される。図示された例では、各第１接合部３１２は、平面視において矩形状であるが、半導体装置Ａ１０の第１接合部３１２と同様に、２つの第１帯状部３１２ａに分割されていてもよい。第２に、半導体装置Ａ３０の第１接続部材４１Ａは、一方の第１半導体素子２１の主面電極２１２と、他方の第１半導体素子２１の主面電極２１２と、第４端子リード１７１の被覆部１７１Ａとに接合される。当該第１接続部材４１Ａは、たとえばステッチ接合により、２つの第１半導体素子２１のうち、第２方向ｙにおいて複数の端子リード１３に近い側の第１半導体素子２１の主面電極２１２に接合されている。第３に、半導体装置Ａ３０の第２接続部材４２Ａは、一方の第１半導体素子２１の第１主面電極２１１と、他方の第１半導体素子２１の第１主面電極２１１と、第６端子リード１８１の被覆部１８１Ａとに接合されている。当該第２接続部材４２Ａは、たとえばステッチ接合により、２つの第１半導体素子２１のうち、第２方向ｙにおいて複数の端子リード１３に近い側の第１半導体素子２１の第１主面電極２１１に接合されている。なお、半導体装置Ａ３０において、第１接続部材４１Ａと第２接続部材４２Ａとでは、第１接続部材４１Ａが先に形成されるが、反対に第２接続部材４２Ａが先に形成されてもよい。 Since the semiconductor device A30 includes two first semiconductor elements 21, it also differs from the semiconductor device A10 in the following points. First, the first conductive member 31 of the semiconductor device A30 includes two first joints 312. The two first joint parts 312 are connected to the first main body part 311. The end portion of the first main body portion 311 that connects to the two first joint portions 312 is bifurcated. Each of the two first bonding parts 312 is bonded to a corresponding one of the two first semiconductor elements 21 . In the illustrated example, each first bonding portion 312 has a rectangular shape in plan view, but may be divided into two first strip portions 312a, similar to the first bonding portion 312 of the semiconductor device A10. . Second, the first connecting member 41A of the semiconductor device A30 covers the main surface electrode 212 of one first semiconductor element 21, the main surface electrode 212 of the other first semiconductor element 21, and the fourth terminal lead 171. 171A. The first connecting member 41A is joined to the main surface electrode 212 of the first semiconductor element 21 on the side closer to the plurality of terminal leads 13 in the second direction y, of the two first semiconductor elements 21, for example by stitch joining. ing. Thirdly, the second connection member 42A of the semiconductor device A30 connects the first main surface electrode 211 of one first semiconductor element 21, the first main surface electrode 211 of the other first semiconductor element 21, and the sixth terminal. It is joined to the covering portion 181A of the lead 181. The second connecting member 42A is connected to the first main surface electrode 211 of the first semiconductor element 21 on the side closer to the plurality of terminal leads 13 in the second direction y, of the two first semiconductor elements 21, for example by stitch bonding. It is joined. Note that in the semiconductor device A30, the first connecting member 41A and the second connecting member 42A are formed first, but on the contrary, the second connecting member 42A may be formed first.
　２つの第２半導体素子２２の各々は、第２ダイパッド１０Ｂに搭載される。２つの第２半導体素子２２はそれぞれ、たとえばトランジスタである。２つの第２半導体素子２２は、第２方向ｙに沿って、並んでいる。半導体装置Ａ３０では、平面視において、２つの第２半導体素子２２の重心（合成重心）が、第２ダイパッド１０Ｂの中心部に重なる。図２８に示す例では、２つの第２半導体素子２２の各平面視サイズは、同じであるが、互いに異なっていてもよい。 Each of the two second semiconductor elements 22 is mounted on the second die pad 10B. Each of the two second semiconductor elements 22 is, for example, a transistor. The two second semiconductor elements 22 are lined up along the second direction y. In the semiconductor device A30, the centers of gravity of the two second semiconductor elements 22 (combined center of gravity) overlap the center of the second die pad 10B in plan view. In the example shown in FIG. 28, the two second semiconductor elements 22 have the same planar size, but may be different from each other.
　半導体装置Ａ３０は、２つの第２半導体素子２２を備えることから、半導体装置Ａ１０と比較して、次の点も異なる。第１に、半導体装置Ａ３０の第２導通部材３２は、２つの第４接合部３２３を含む。２つの第４接合部３２３は、第２本体部３２１に繋がる。２つの第４接合部３２３はそれぞれ、第３延出部３２１ｅに繋がる。２つの第４接合部３２３はそれぞれ、２つの第２半導体素子２２のうちの対応する１つに接合される。図示された例では、各第４接合部３２３は、平面視において矩形状であるが、半導体装置Ａ１０の第４接合部３２３と同様に、２つの第２帯状部３２３ａに分割されていてもよい。第２に、半導体装置Ａ３０の第１接続部材４１Ｂは、他方の第２半導体素子２２の主面電極２２２と、他方の第２半導体素子２２の主面電極２２２と、第５端子リード１７２の被覆部１７２Ａとに接合される。当該第１接続部材４１Ｂは、たとえばステッチ接合により、２つの第２半導体素子２２のうち、第２方向ｙにおいて複数の端子リード１３に近い側の第２半導体素子２２の主面電極２２２に接合されている。第３に、半導体装置Ａ３０の第２接続部材４２Ｂは、一方の第２半導体素子２２の第２主面電極２２１と、他方の第２半導体素子２２の第２主面電極２２１と、第７端子リード１８２の被覆部１８２Ａとに接合されている。当該第２接続部材４２Ｂは、たとえばステッチ接合により、２つの第２半導体素子２２のうち、第２方向ｙにおいて複数の端子リード１３に近い側の第２半導体素子２２の第２主面電極２２１に接合されている。なお、半導体装置Ａ３０において、第１接続部材４１Ｂと第２接続部材４２Ｂとでは、第１接続部材４１Ｂが先に形成されるが、反対に第２接続部材４２Ｂが先に形成されてもよい。 Since the semiconductor device A30 includes two second semiconductor elements 22, it also differs from the semiconductor device A10 in the following points. First, the second conductive member 32 of the semiconductor device A30 includes two fourth joints 323. The two fourth joint parts 323 are connected to the second main body part 321. The two fourth joint portions 323 are each connected to the third extension portion 321e. Each of the two fourth bonding parts 323 is bonded to a corresponding one of the two second semiconductor elements 22 . In the illustrated example, each fourth joint portion 323 has a rectangular shape in plan view, but may be divided into two second strip portions 323a, similar to the fourth joint portion 323 of the semiconductor device A10. . Second, the first connecting member 41B of the semiconductor device A30 covers the main surface electrode 222 of the other second semiconductor element 22, the main surface electrode 222 of the other second semiconductor element 22, and the fifth terminal lead 172. 172A. The first connecting member 41B is joined to the main surface electrode 222 of the second semiconductor element 22 on the side closer to the plurality of terminal leads 13 in the second direction y, of the two second semiconductor elements 22, for example by stitch joining. ing. Thirdly, the second connection member 42B of the semiconductor device A30 connects the second main surface electrode 221 of one second semiconductor element 22, the second main surface electrode 221 of the other second semiconductor element 22, and the seventh terminal. It is joined to the covering portion 182A of the lead 182. The second connecting member 42B is connected to the second main surface electrode 221 of the second semiconductor element 22 on the side closer to the plurality of terminal leads 13 in the second direction y, of the two second semiconductor elements 22, for example by stitch bonding. It is joined. Note that in the semiconductor device A30, the first connecting member 41B and the second connecting member 42B are formed first, but on the contrary, the second connecting member 42B may be formed first.
　なお、図２８に示す例とは異なり、半導体装置Ａ３０において、次のように構成してもよい。それは、半導体装置Ａ３０が２つの第１接続部材４１Ａを備え、一方の第１接続部材４１Ａが、一方の第１半導体素子２１の主面電極２１２と、第４端子リード１７１の被覆部１７１Ａとに接合され、他方の第１接続部材４１Ａが、他方の第１半導体素子２１の主面電極２１２と、第４端子リード１７１の被覆部１７１Ａとに接合されていてもよい。同様に、半導体装置Ａ３０が２つの第２接続部材４２Ａを備え、一方の第２接続部材４２Ａが、一方の第１半導体素子２１の第１主面電極２１１と、第６端子リード１８１の被覆部１８１Ａとに接合され、他方の第２接続部材４２Ａが、他方の第１半導体素子２１の第１主面電極２１１と、第６端子リード１８１の被覆部１８１Ａとに接合されていてもよい。また、半導体装置Ａ３０が２つの第１接続部材４１Ｂを備え、一方の第１接続部材４１Ｂが、一方の第２半導体素子２２の主面電極２２２と、第５端子リード１７２の被覆部１７２Ａとに接合され、他方の第１接続部材４１Ｂが、他方の第２半導体素子２２の主面電極２２２と、第５端子リード１７２の被覆部１７２Ａとに接合されていてもよい。また、半導体装置Ａ３０が２つの第２接続部材４２Ｂを備え、一方の第２接続部材４２Ｂが、一方の第２半導体素子２２の第２主面電極２２１と、第７端子リード１８２の被覆部１８２Ａとに接合され、他方の第２接続部材４２Ｂが、他方の第２半導体素子２２の第２主面電極２２１と、第７端子リード１８２の被覆部１８２Ａとに接合されていてもよい。 Note that, unlike the example shown in FIG. 28, the semiconductor device A30 may be configured as follows. That is, the semiconductor device A30 includes two first connection members 41A, and one of the first connection members 41A connects to the main surface electrode 212 of one of the first semiconductor elements 21 and the covering portion 171A of the fourth terminal lead 171. The other first connecting member 41A may be joined to the main surface electrode 212 of the other first semiconductor element 21 and the covering portion 171A of the fourth terminal lead 171. Similarly, the semiconductor device A30 includes two second connection members 42A, and one of the second connection members 42A connects the first main surface electrode 211 of the first semiconductor element 21 and the covering portion of the sixth terminal lead 181. 181A, and the other second connecting member 42A may be joined to the first main surface electrode 211 of the other first semiconductor element 21 and the covering portion 181A of the sixth terminal lead 181. Further, the semiconductor device A30 includes two first connection members 41B, and one of the first connection members 41B is connected to the main surface electrode 222 of one of the second semiconductor elements 22 and the covering portion 172A of the fifth terminal lead 172. The other first connecting member 41B may be joined to the main surface electrode 222 of the other second semiconductor element 22 and the covering portion 172A of the fifth terminal lead 172. Further, the semiconductor device A30 includes two second connection members 42B, and one of the second connection members 42B connects the second main surface electrode 221 of one of the second semiconductor elements 22 and the covering portion 182A of the seventh terminal lead 182. The other second connecting member 42B may be joined to the second main surface electrode 221 of the other second semiconductor element 22 and the covering portion 182A of the seventh terminal lead 182.
　第３実施形態にかかる半導体装置Ａ３０は、半導体装置Ａ１０と同様に、２つの半導体素子（第１半導体素子２１および第２半導体素子２２）が１つの封止樹脂５０により１パッケージ化される。したがって、半導体装置Ａ３０は、半導体装置Ａ１０と同様に、当該半導体装置Ａ３０を実装する回路基板への実装面積を削減することが可能となる。その他、半導体装置Ａ３０は、半導体装置Ａ１０と共通する構成により、半導体装置Ａ１０と同様の効果を奏する。 In the semiconductor device A30 according to the third embodiment, two semiconductor elements (the first semiconductor element 21 and the second semiconductor element 22) are packaged into one package using one sealing resin 50, similarly to the semiconductor device A10. Therefore, like the semiconductor device A10, the semiconductor device A30 can reduce the mounting area on the circuit board on which the semiconductor device A30 is mounted. In addition, the semiconductor device A30 has the same configuration as the semiconductor device A10, and thus achieves the same effects as the semiconductor device A10.
　上記半導体装置Ａ１０，Ａ３０から理解されるように、本開示の半導体装置においては、第１半導体素子２１および第２半導体素子２２の各個数が異なっても、第１ダイパッド１０Ａ、第２ダイパッド１０Ｂ、複数の端子リード１３および封止樹脂５０などの構成は同じである。したがって、本開示の半導体装置は、第１半導体素子２１および第２半導体素子２２の各個数が異なっても、各端子リード１３および封止樹脂５０の構成をそのまま活用できる。これにより、本開示の半導体装置は、第１半導体素子２１および第２半導体素子２２の各個数に関わらず、パッケージ構造を共通化することができるので、生産性の向上において、好ましい。 As understood from the semiconductor devices A10 and A30, in the semiconductor device of the present disclosure, even if the numbers of the first semiconductor elements 21 and the second semiconductor elements 22 are different, the first die pad 10A, the second die pad 10B, The configurations of the plurality of terminal leads 13, sealing resin 50, etc. are the same. Therefore, in the semiconductor device of the present disclosure, even if the numbers of the first semiconductor elements 21 and the second semiconductor elements 22 are different, the configurations of the terminal leads 13 and the sealing resin 50 can be used as they are. As a result, the semiconductor device of the present disclosure can share a package structure regardless of the number of first semiconductor elements 21 and second semiconductor elements 22, which is preferable for improving productivity.
　上記半導体装置Ａ１０，Ａ２０，Ａ３０から理解されるように、本開示の半導体装置においては、第１半導体素子２１および第２半導体素子２２の種類（トランジスタであるかダイオードであるか）、平面視サイズおよび個数などが異なっていても、第１導通部材３１の一部（たとえば第１接合部３１２）および第２導通部材３２の一部（たとえば第４接合部３２３）を変えるだけで、第１ダイパッド１０Ａ、第２ダイパッド１０Ｂ、複数の端子リード１３および封止樹脂５０を共通化することが可能である。 As understood from the semiconductor devices A10, A20, and A30, in the semiconductor device of the present disclosure, the type (transistor or diode) of the first semiconductor element 21 and the second semiconductor element 22, the planar view size, Even if the number and number of pieces are different, the first die pad 10A, the second die pad 10B, the plurality of terminal leads 13, and the sealing resin 50 can be made common.
　半導体装置Ａ３０では、２つの第１半導体素子２１がともにトランジスタである例を示したが、これに限定されず、２つの第１半導体素子２１のうちの一方がトランジスタで、他方がダイオードであってもよい。この場合、２つの第１半導体素子２１において、ダイオードは、トランジスタに対して逆並列に接続される。当該逆並列では、トランジスタがＭＯＳＦＥＴである例において、ドレイン電極とカソード電極とが接続され、かつソース電極とアノード電極とが接続されている。同様に、２つの第２半導体素子２２の一方がトランジスタで他方がダイオードであってもよい。 In the semiconductor device A30, an example has been shown in which the two first semiconductor elements 21 are both transistors; however, the present invention is not limited to this, and one of the two first semiconductor elements 21 may be a transistor and the other may be a diode. Good too. In this case, in the two first semiconductor elements 21, the diodes are connected antiparallel to the transistors. In the antiparallel arrangement, in an example where the transistor is a MOSFET, a drain electrode and a cathode electrode are connected, and a source electrode and an anode electrode are connected. Similarly, one of the two second semiconductor elements 22 may be a transistor and the other may be a diode.
　図２９および図３０は、第４実施形態にかかる半導体装置Ａ４０を示している。半導体装置Ａ４０は、半導体装置Ａ１０と比較して、次の点で異なる。それは、半導体装置Ａ４０は、支持基板６をさらに備える。 29 and 30 show a semiconductor device A40 according to the fourth embodiment. The semiconductor device A40 differs from the semiconductor device A10 in the following points. That is, the semiconductor device A40 further includes a support substrate 6.
　支持基板６は、第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂを支持する。支持基板６は、たとえばＤＢＣ（Direct Bonded Copper）基板またはＡＭＢ（Active Matal Brazing）基板であるが、これらに限定されない。支持基板６は、絶縁層６１および一対の金属層６２，６３を含む。 The support substrate 6 supports the first die pad 10A and the second die pad 10B. The support substrate 6 is, for example, a DBC (Direct Bonded Copper) substrate or an AMB (Active Matal Brazing) substrate, but is not limited thereto. Support substrate 6 includes an insulating layer 61 and a pair of metal layers 62 and 63.
　絶縁層６１は、厚さ方向ｚにおいて、一対の金属層６２，６３の間に介在する。絶縁層６１は、たとえばセラミックスからなる板材である。当該セラミックスの組成は、たとえばアルミナ（Ａｌ2Ｏ3）、窒化アルミニウム（ＡｌＮ）、または、窒化ケイ素（ＳｉＮ，Ｓｉ3Ｎ4）などである。絶縁層６１は、平面視において、金属層６２を内方する。 The insulating layer 61 is interposed between the pair of metal layers 62 and 63 in the thickness direction z. The insulating layer 61 is, for example, a plate made of ceramics. The composition of the ceramic is, for example, alumina (Al 2 O 3 ), aluminum nitride (AlN), or silicon nitride (SiN, Si 3 N 4 ). The insulating layer 61 faces the metal layer 62 inward in plan view.
　金属層６２は、絶縁層６１の上面（厚さ方向ｚ上方を向く面）に形成される。金属層６２は、たとえば銅または銅合金を含む。なお、金属層６２は、銅または銅合金の他、金、銀、アルミニウムなどの他の金属を含んでいてもよい。図２９および図３０に示すように、金属層６２は、２つのパッド部６２１，６２２を含む。 The metal layer 62 is formed on the upper surface of the insulating layer 61 (the surface facing upward in the thickness direction z). Metal layer 62 includes, for example, copper or a copper alloy. Note that the metal layer 62 may contain other metals such as gold, silver, and aluminum in addition to copper or a copper alloy. As shown in FIGS. 29 and 30, metal layer 62 includes two pad portions 621 and 622.
　２つのパッド部６２１，６２２は、互いに離間する。２つのパッド部６２１，６２２は、第１方向ｘに沿って配置される。パッド部６２１には、接合材６９により、第１ダイパッド１０Ａが接合される。パッド部６２２には、接合材６９により、第２ダイパッド１０Ｂが接合される。各接合材６９は、たとえばはんだまたは焼結金属などの導電性の接合材である。この例と異なり、各接合材６９は、絶縁性の接合材であってもよい。なお、パッド部６２１と第１ダイパッド１０Ａとが、パッド部６２２と第２ダイパッド１０Ｂとが、接合材６９で接合されるのではなく、たとえば固相拡散接合されていてもよい。図２９に示す例では、平面視において、パッド部６２１は、第１ダイパッド１０Ａよりも一回り大きく、パッド部６２２は、第２ダイパッド１０Ｂよりもひと回り大きい。 The two pad parts 621 and 622 are spaced apart from each other. The two pad parts 621 and 622 are arranged along the first direction x. The first die pad 10A is bonded to the pad portion 621 with a bonding material 69. The second die pad 10B is bonded to the pad portion 622 with a bonding material 69. Each bonding material 69 is a conductive bonding material such as solder or sintered metal. Unlike this example, each bonding material 69 may be an insulating bonding material. Note that the pad portion 621 and the first die pad 10A and the pad portion 622 and the second die pad 10B may be bonded together by solid phase diffusion bonding, for example, instead of being bonded with the bonding material 69. In the example shown in FIG. 29, in plan view, the pad portion 621 is one size larger than the first die pad 10A, and the pad portion 622 is one size larger than the second die pad 10B.
　金属層６３は、絶縁層６１の下面（厚さ方向ｚ下方を向く面）に形成される。金属層６３は、金属層６２と同様に、たとえば銅または銅合金を含む。なお、金属層６３は、銅または銅合金の他、金、銀、アルミニウムなどの他の金属を含んでいてもよい。金属層６３は、２つのパッド部６３１，６３２を含む。 The metal layer 63 is formed on the lower surface of the insulating layer 61 (the surface facing downward in the thickness direction z). Like metal layer 62, metal layer 63 includes, for example, copper or a copper alloy. Note that the metal layer 63 may contain other metals such as gold, silver, and aluminum in addition to copper or a copper alloy. Metal layer 63 includes two pad portions 631 and 632.
　２つのパッド部６３１，６３２は、互いに離間する。２つのパッド部６３１，６３２は、第１方向ｘに沿って配置される。パッド部６３１は、平面視において、パッド部６２１に重なる。パッド部６３２は、平面視において、パッド部６２２に重なる。２つのパッド部６３１，６３２（金属層６３）は、樹脂裏面５２において露出する。図示された例では、２つのパッド部６３１，６３２の各下面（厚さ方向ｚ下方を向く面）は、樹脂裏面５２と面一であるが、この例とは異なり、樹脂裏面５２に対して、厚さ方向ｚ上方に位置していてもよいし、厚さ方向ｚ下方に位置していてもよい。 The two pad parts 631 and 632 are spaced apart from each other. The two pad parts 631 and 632 are arranged along the first direction x. Pad portion 631 overlaps pad portion 621 in plan view. Pad portion 632 overlaps pad portion 622 in plan view. The two pad portions 631 and 632 (metal layer 63) are exposed on the resin back surface 52. In the illustrated example, the lower surfaces of the two pad portions 631 and 632 (the surfaces facing downward in the thickness direction z) are flush with the resin back surface 52; however, unlike this example, , may be located above in the thickness direction z, or may be located below in the thickness direction z.
　半導体装置Ａ４０の封止樹脂５０の厚さ（厚さ方向ｚの寸法）は、半導体装置Ａ１０の封止樹脂５０の厚さ（厚さ方向ｚの寸法）とほぼ同じである。一方で、半導体装置Ａ４０の第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂの各厚さ（厚さ方向ｚの寸法）は、半導体装置Ａ１０の第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂの各厚さ（厚さ方向ｚの寸法）よりも小さい。半導体装置Ａ４０での第１ダイパッド１０Ａ（第２ダイパッド１０Ｂ）の厚さと支持基板６の厚さとの和が、半導体装置Ａ１０での第１ダイパッド１０Ａ（第２ダイパッド１０Ｂ）の厚さに相当する。 The thickness (dimension in the thickness direction z) of the sealing resin 50 of the semiconductor device A40 is approximately the same as the thickness (dimension in the thickness direction z) of the sealing resin 50 of the semiconductor device A10. On the other hand, the respective thicknesses (dimensions in the thickness direction z) of the first die pad 10A and the second die pad 10B of the semiconductor device A40 are the same as those of the first die pad 10A and the second die pad 10B of the semiconductor device A10. dimension in direction z). The sum of the thickness of the first die pad 10A (second die pad 10B) and the thickness of the support substrate 6 in the semiconductor device A40 corresponds to the thickness of the first die pad 10A (second die pad 10B) in the semiconductor device A10.
　図示された例では、半導体装置Ａ４０の封止樹脂５０は、溝部５７を有していない。この例と異なる構成において、封止樹脂５０は、溝部５７を有していてもよい。ただし、溝部５７は、半導体装置Ａ１０における溝部５７よりも浅く、絶縁層６１の下面より厚さ方向ｚ下方に位置する。 In the illustrated example, the sealing resin 50 of the semiconductor device A40 does not have the groove portion 57. In a configuration different from this example, the sealing resin 50 may have a groove 57. However, the groove portion 57 is shallower than the groove portion 57 in the semiconductor device A10 and is located below the lower surface of the insulating layer 61 in the thickness direction z.
　第４実施形態にかかる半導体装置Ａ４０は、半導体装置Ａ１０と同様に、２つの半導体素子（第１半導体素子２１および第２半導体素子２２）が１つの封止樹脂５０により１パッケージ化される。したがって、半導体装置Ａ４０は、半導体装置Ａ１０と同様に、当該半導体装置Ａ４０を実装する回路基板への実装面積を削減することが可能となる。その他、半導体装置Ａ４０は、半導体装置Ａ１０と共通する構成により、半導体装置Ａ１０と同様の効果を奏する。 In the semiconductor device A40 according to the fourth embodiment, two semiconductor elements (the first semiconductor element 21 and the second semiconductor element 22) are packaged into one package using one sealing resin 50, similarly to the semiconductor device A10. Therefore, like the semiconductor device A10, the semiconductor device A40 can reduce the mounting area on the circuit board on which the semiconductor device A40 is mounted. In addition, the semiconductor device A40 has the same configuration as the semiconductor device A10, and has the same effects as the semiconductor device A10.
　半導体装置Ａ４０は、第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂを支持する支持基板６を備える。支持基板６は、セラミックスからなる絶縁層６１を含む。半導体装置Ａ４０は、第１半導体素子２１および第２半導体素子２２の駆動に伴い、第１半導体素子２１および第２半導体素子２２が発熱する。この発熱により、第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂが熱膨張する。このような熱膨張は、他の構成要素（たとえば第１半導体素子２１および第２半導体素子２２）に熱応力を加える。しかしながら、半導体装置Ａ４０では、支持基板６（特にセラミックスからなる絶縁層６１）により、第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂの熱膨張が制限される。したがって、半導体装置Ａ４０では、第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂの熱膨張に起因する熱応力を緩和できる。たとえば、半導体装置Ａ４０では、第１半導体素子２１および第２半導体素子２２に加わる熱応力が緩和され、第１半導体素子２１および第２半導体素子２２の内部破壊（たとえば内部の界面剥離）が抑制される。 The semiconductor device A40 includes a support substrate 6 that supports the first die pad 10A and the second die pad 10B. Support substrate 6 includes an insulating layer 61 made of ceramics. In the semiconductor device A40, the first semiconductor element 21 and the second semiconductor element 22 generate heat as the first semiconductor element 21 and the second semiconductor element 22 are driven. This heat generation thermally expands the first die pad 10A and the second die pad 10B. Such thermal expansion applies thermal stress to other components (eg, the first semiconductor element 21 and the second semiconductor element 22). However, in the semiconductor device A40, the thermal expansion of the first die pad 10A and the second die pad 10B is limited by the support substrate 6 (particularly the insulating layer 61 made of ceramic). Therefore, in the semiconductor device A40, thermal stress caused by thermal expansion of the first die pad 10A and the second die pad 10B can be alleviated. For example, in the semiconductor device A40, thermal stress applied to the first semiconductor element 21 and the second semiconductor element 22 is relaxed, and internal destruction (for example, internal interface peeling) of the first semiconductor element 21 and the second semiconductor element 22 is suppressed. Ru.
　半導体装置Ａ４０では、第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂの各厚さ（厚さ方向ｚの寸法）は、半導体装置Ａ１０の第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂの各厚さ（厚さ方向ｚの寸法）よりも小さい。この構成によれば、半導体装置Ａ４０は、半導体装置Ａ１０と比較して、第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂの各熱膨張が抑制される。したがって、半導体装置Ａ４０は、半導体装置Ａ１０よりも、第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂの各熱膨張に起因する熱応力を緩和できる。 In the semiconductor device A40, the respective thicknesses (dimensions in the thickness direction z) of the first die pad 10A and the second die pad 10B are equal to the respective thicknesses (dimensions in the thickness direction z) of the first die pad 10A and the second die pad 10B of the semiconductor device A10. dimensions). According to this configuration, in the semiconductor device A40, the thermal expansion of the first die pad 10A and the second die pad 10B is suppressed compared to the semiconductor device A10. Therefore, the semiconductor device A40 can alleviate the thermal stress caused by the thermal expansion of the first die pad 10A and the second die pad 10B more than the semiconductor device A10.
　図３１は、第４実施形態の第１変形例にかかる半導体装置Ａ４１を示している。半導体装置Ａ４１は、半導体装置Ａ４０と比較して、次の点で異なる。それは、金属層６３が、２つのパッド部６３１，６３２に分離されていない点である。半導体装置Ａ４１の金属層６３は、半導体装置Ａ４０における２つのパッド部６３１，６３２が連結されたものに相当する。 FIG. 31 shows a semiconductor device A41 according to a first modification of the fourth embodiment. The semiconductor device A41 differs from the semiconductor device A40 in the following points. That is, the metal layer 63 is not separated into two pad parts 631 and 632. The metal layer 63 of the semiconductor device A41 corresponds to the two pad portions 631 and 632 connected to each other in the semiconductor device A40.
　図３２は、第４実施形態の第２変形例にかかる半導体装置Ａ４２を示している。半導体装置Ａ４２は、半導体装置Ａ４０と比較して、次の点で異なる。それは、絶縁層６１が２つの板材６１１，６１２に分離されている点である。板材６１１の上面には、パッド部６２１が形成され、板材６１１の下面には、パッド部６３１が形成される。板材６１２の上面には、パッド部６２２が形成され、板材６１２の下面には、パッド部６３２が形成されている。半導体装置Ａ４２では、２つのＤＢＣ基板またはＡＭＢ基板に、第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂがそれぞれ個別に接合されている。 FIG. 32 shows a semiconductor device A42 according to a second modification of the fourth embodiment. The semiconductor device A42 differs from the semiconductor device A40 in the following points. The point is that the insulating layer 61 is separated into two plate members 611 and 612. A pad portion 621 is formed on the upper surface of the plate material 611, and a pad portion 631 is formed on the lower surface of the plate material 611. A pad portion 622 is formed on the upper surface of the plate material 612, and a pad portion 632 is formed on the lower surface of the plate material 612. In the semiconductor device A42, a first die pad 10A and a second die pad 10B are individually bonded to two DBC substrates or AMB substrates.
　第４実施形態の各変形例にかかる半導体装置Ａ４１，Ａ４２は、半導体装置Ａ４０と同様に、２つの半導体素子（第１半導体素子２１および第２半導体素子２２）が１つの封止樹脂５０により１パッケージ化される。したがって、各半導体装置Ａ４１，Ａ４２は、半導体装置Ａ４０と同様に、当該半導体装置Ａ４１，Ａ４２を実装する回路基板への実装面積を削減することが可能となる。その他、各半導体装置Ａ４１，Ａ４２は、半導体装置Ａ４０と共通する構成により、半導体装置Ａ４０と同様の効果を奏する。たとえば、各半導体装置Ａ４１，Ａ４２は、セラミックスからなる絶縁層６１（２つの板材６１１，６１２）により、第１ダイパッド１０Ａおよび第２ダイパッド１０Ｂの熱膨張を抑制して、他の構成要素（たとえば第１半導体素子２１および第２半導体素子２２）に加わる熱応力を緩和できる。 In the semiconductor devices A41 and A42 according to each modification of the fourth embodiment, two semiconductor elements (the first semiconductor element 21 and the second semiconductor element 22) are integrated by one sealing resin 50, similarly to the semiconductor device A40. Packaged. Therefore, similarly to the semiconductor device A40, each of the semiconductor devices A41 and A42 can reduce the mounting area on the circuit board on which the semiconductor devices A41 and A42 are mounted. In addition, each of the semiconductor devices A41 and A42 has the same configuration as the semiconductor device A40, and thus achieves the same effects as the semiconductor device A40. For example, each of the semiconductor devices A41 and A42 suppresses the thermal expansion of the first die pad 10A and the second die pad 10B by using the insulating layer 61 (two plate materials 611 and 612) made of ceramics, and suppresses the thermal expansion of the other components (for example, the second die pad 10B). Thermal stress applied to the first semiconductor element 21 and the second semiconductor element 22) can be alleviated.
　本開示の半導体装置のパッケージ構造は、上記第１実施形態ないし第４実施形態（これらの変形例も含む）で例示したものに限定されない。たとえば、本開示の半導体装置は、他のＴＯ（Transistor Outline）パッケージに対して、適用することも可能である。具体的には、第１実施形態ないし第４実施形態にかかる各半導体装置Ａ１０，Ａ２０，Ａ３０，Ａ４０は、ＴＯ－２４７と呼ばれるパッケージ構造を拡張したものであるが、ＴＯ－２２０、ＴＯ－２５２、ＴＯ２６３などと呼ばれる他のパッケージ構造を拡張したものでもよい。つまり、本開示の半導体装置は、従来のＴＯパッケージと類似の外観を持ったまま、複数の半導体素子（第１半導体素子２１および第２半導体素子２２）を１つの封止樹脂５０によりパッケージすることを可能にする。 The package structure of the semiconductor device of the present disclosure is not limited to those exemplified in the first to fourth embodiments (including variations thereof). For example, the semiconductor device of the present disclosure can also be applied to other TO (Transistor Outline) packages. Specifically, each of the semiconductor devices A10, A20, A30, and A40 according to the first to fourth embodiments is an expanded package structure called TO-247, but TO-220, TO-252 , TO263, etc. may be an extension of other package structures. In other words, the semiconductor device of the present disclosure can package a plurality of semiconductor elements (first semiconductor element 21 and second semiconductor element 22) with one sealing resin 50 while maintaining an appearance similar to a conventional TO package. enable.
　本開示にかかる半導体装置は、上記した実施形態に限定されるものではない。本開示の半導体装置の各部の具体的な構成は、種々に設計変更自在である。本開示は、以下の付記に記載された実施形態を含む。
　付記１．
　厚さ方向の一方を向く第１主面および前記第１主面に配置された第１主面電極を有する第１半導体素子と、
　前記第１主面と同じ方向を向く第２主面および前記第２主面に配置された第２主面電極を有する第２半導体素子と、
　前記第１半導体素子が搭載された第１ダイパッドと、
　前記第１ダイパッドに対して前記厚さ方向に直交する第１方向の一方側に配置され、前記第２半導体素子が搭載された第２ダイパッドと、
　前記第１ダイパッドおよび前記第２ダイパッドから離間する第１端子リードと、
　前記第１主面電極と前記第２ダイパッドとを電気的に接続する第１導通部材と、
　前記第２主面電極と前記第１端子リードとを電気的に接続する第２導通部材と、
　前記第１半導体素子および前記第２半導体素子を覆う封止樹脂と、を備える半導体装置。
　付記２．
　前記第１導通部材は、前記第１主面電極に接合された第１接合部と、前記第２ダイパッドに接合された第２接合部と、前記第１接合部と前記第２接合部とを繋ぐ第１本体部とを含む、付記１に記載の半導体装置。
　付記３．
　前記第１本体部は、前記厚さ方向に見て、前記第１方向に沿って延びる、付記２に記載の半導体装置。
　付記４．
　前記厚さ方向に見たときの前記第１接合部の面積は、前記厚さ方向に見たときの前記第１主面電極の面積の１０％以上１００％以下である、付記２または付記３に記載の半導体装置。
　付記５．
　前記第１接合部は、２つの第１帯状部を含み、
　前記第１本体部のうちの前記第１接合部に繋がる端縁は、二股に分かれて前記２つの第１帯状部にそれぞれ繋がる、付記２ないし付記４のいずれかに記載の半導体装置。
　付記６．
　前記第２導通部材は、前記第１端子リードに接合された第３接合部と、前記第２主面電極に接合された第４接合部と、前記第３接合部と前記第４接合部とを繋ぐ第２本体部とを含む、付記１ないし付記５のいずれかに記載の半導体装置。
　付記７．
　前記第２本体部は、前記厚さ方向に見て屈曲する、付記６に記載の半導体装置。
　付記８．
　前記第２本体部は、前記第３接合部に繋がる端縁を第１基端として当該第１基端から前記厚さ方向および前記第１方向に直交する第２方向に延びる第１延出部と、前記第１延出部に繋がる端縁を第２基端として当該第２基端から前記第１方向に延びる第２延出部と、前記第２延出部に繋がる端縁を第３基端として当該第３基端から前記第２方向に延びる第３延出部と、を含み、
　前記第３延出部は、前記第４接合部に繋がる、付記７に記載の半導体装置。
　付記９．
　前記厚さ方向に見たときの前記第４接合部の面積は、前記厚さ方向に見たときの前記第２主面電極の面積の１０％以上１００％以下である、付記６ないし付記８のいずれかに記載の半導体装置。
　付記１０．
　前記第４接合部は、２つの第２帯状部を含み、
　前記第２本体部のうちの前記第４接合部に繋がる端縁は、二股に分かれて前記２つの第２帯状部にそれぞれ繋がる、付記６ないし付記９のいずれかに記載の半導体装置。
　付記１１．
　前記第１ダイパッドに繋がる第２端子リードと、
　前記第２ダイパッドに繋がる第３端子リードと、をさらに備え、
　前記第１端子リード、前記第２端子リードおよび前記第３端子リードは、互いに離間する、付記１ないし付記１０のいずれかに記載の半導体装置。
　付記１２．
　前記第１端子リードは、前記第１方向において、前記第２端子リードと前記第３端子リードとの間に位置する、付記１１に記載の半導体装置。
　付記１３．
　各々が前記第１端子リード、前記第２端子リードおよび前記第３端子リードから離間し、且つ、互いに離間する第４端子リード、第５端子リード、第６端子リードおよび第７端子リードをさらに備える、付記１１または付記１２に記載の半導体装置。
　付記１４．
　前記封止樹脂は、前記第１主面と同じ方向を向く樹脂主面と、前記樹脂主面から窪む少なくとも１つの凹部とを有し、
　前記少なくとも１つの凹部の各々は、前記厚さ方向に見て、前記第１ダイパッドおよび前記第２ダイパッドのいずれかに重なる、付記１ないし付記１３のいずれかに記載の半導体装置。
　付記１５．
　前記少なくとも１つの凹部の各々は、前記厚さ方向に見て、前記第１導通部材および前記第２導通部材のいずれにも重ならない、付記１４に記載の半導体装置。
　付記１６．
　前記厚さ方向に見て、前記第１半導体素子の重心は、前記第１ダイパッドの中心部に重なる、付記１ないし付記１５のいずれかに記載の半導体装置。
　付記１７．
　前記厚さ方向に見て、前記第２半導体素子の重心は、前記第２ダイパッドの中心部に重なる、付記１ないし付記１６のいずれかに記載の半導体装置。
　付記１８．
　前記第１ダイパッドおよび前記第２ダイパッドを支持する支持基板をさらに備え、
　前記第１ダイパッドおよび前記第２ダイパッドは、前記厚さ方向において、前記支持基板に、前記第１半導体素子および前記第２半導体素子が搭載された側と反対側から支持されており、
　前記支持基板は、セラミックスと、当該セラミックスの前記厚さ方向の両面に形成された一対の金属層とを含む、付記１ないし付記１７のいずれかに記載の半導体装置。
　付記１９．
　前記第１半導体素子は、トランジスタまたはダイオードのいずれかであり、
　前記第２半導体素子は、トランジスタまたはダイオードのいずれかである、付記１ないし付記１８のいずれかに記載の半導体装置。 The semiconductor device according to the present disclosure is not limited to the embodiments described above. The specific configuration of each part of the semiconductor device of the present disclosure can be modified in various ways. The present disclosure includes the embodiments described in the appendix below.
Additional note 1.
a first semiconductor element having a first main surface facing one side in the thickness direction and a first main surface electrode disposed on the first main surface;
a second semiconductor element having a second main surface facing in the same direction as the first main surface and a second main surface electrode disposed on the second main surface;
a first die pad on which the first semiconductor element is mounted;
a second die pad arranged on one side of the first die pad in a first direction perpendicular to the thickness direction, and on which the second semiconductor element is mounted;
a first terminal lead spaced apart from the first die pad and the second die pad;
a first conductive member that electrically connects the first main surface electrode and the second die pad;
a second conductive member that electrically connects the second main surface electrode and the first terminal lead;
A semiconductor device comprising: a sealing resin that covers the first semiconductor element and the second semiconductor element.
Appendix 2.
The first conductive member connects a first joint part joined to the first main surface electrode, a second joint part joined to the second die pad, and a first joint part and the second joint part. The semiconductor device according to supplementary note 1, including a first main body portion that connects the semiconductor device.
Appendix 3.
The semiconductor device according to appendix 2, wherein the first main body portion extends along the first direction when viewed in the thickness direction.
Appendix 4.
Supplementary Note 2 or 3, wherein the area of the first joint when viewed in the thickness direction is 10% or more and 100% or less of the area of the first main surface electrode when viewed in the thickness direction. The semiconductor device described in .
Appendix 5.
The first joint portion includes two first strip portions,
The semiconductor device according to any one of appendices 2 to 4, wherein an edge of the first body portion that is connected to the first joint portion is bifurcated and connected to the two first band portions, respectively.
Appendix 6.
The second conductive member includes a third joint part joined to the first terminal lead, a fourth joint part joined to the second main surface electrode, and the third joint part and the fourth joint part. and a second main body portion that connects the semiconductor device according to any one of Supplementary Notes 1 to 5.
Appendix 7.
The semiconductor device according to appendix 6, wherein the second main body portion is bent when viewed in the thickness direction.
Appendix 8.
The second main body part has a first extending part that extends from the first base end in a second direction perpendicular to the thickness direction and the first direction, with an edge connected to the third joint part as a first base end. a second extending portion extending in the first direction from the second base end with the edge connected to the first extending portion as a second base end; and a third extending portion extending from the second base end in the first direction; a third extending portion extending in the second direction from the third base end as a base end,
The semiconductor device according to appendix 7, wherein the third extension part is connected to the fourth joint part.
Appendix 9.
Supplementary notes 6 to 8, wherein the area of the fourth joint when viewed in the thickness direction is 10% or more and 100% or less of the area of the second main surface electrode when viewed in the thickness direction. The semiconductor device according to any one of the above.
Appendix 10.
The fourth joint portion includes two second strip portions,
The semiconductor device according to any one of appendices 6 to 9, wherein an edge of the second main body portion that is connected to the fourth joint portion is bifurcated and connected to the two second band portions, respectively.
Appendix 11.
a second terminal lead connected to the first die pad;
further comprising a third terminal lead connected to the second die pad,
The semiconductor device according to any one of appendices 1 to 10, wherein the first terminal lead, the second terminal lead, and the third terminal lead are spaced apart from each other.
Appendix 12.
The semiconductor device according to attachment 11, wherein the first terminal lead is located between the second terminal lead and the third terminal lead in the first direction.
Appendix 13.
Further comprising a fourth terminal lead, a fifth terminal lead, a sixth terminal lead, and a seventh terminal lead, each spaced apart from the first terminal lead, the second terminal lead, and the third terminal lead, and spaced apart from each other. , the semiconductor device according to appendix 11 or appendix 12.
Appendix 14.
The sealing resin has a resin main surface facing in the same direction as the first main surface, and at least one recess depressed from the resin main surface,
The semiconductor device according to any one of attachments 1 to 13, wherein each of the at least one recess overlaps either the first die pad or the second die pad when viewed in the thickness direction.
Appendix 15.
15. The semiconductor device according to appendix 14, wherein each of the at least one recessed portion does not overlap with either the first conductive member or the second conductive member when viewed in the thickness direction.
Appendix 16.
The semiconductor device according to any one of appendices 1 to 15, wherein the center of gravity of the first semiconductor element overlaps the center of the first die pad when viewed in the thickness direction.
Appendix 17.
The semiconductor device according to any one of attachments 1 to 16, wherein the center of gravity of the second semiconductor element overlaps the center of the second die pad when viewed in the thickness direction.
Appendix 18.
further comprising a support substrate that supports the first die pad and the second die pad,
The first die pad and the second die pad are supported in the thickness direction by the supporting substrate from a side opposite to a side on which the first semiconductor element and the second semiconductor element are mounted,
The semiconductor device according to any one of attachments 1 to 17, wherein the support substrate includes a ceramic and a pair of metal layers formed on both sides of the ceramic in the thickness direction.
Appendix 19.
The first semiconductor element is either a transistor or a diode,
The semiconductor device according to any one of attachments 1 to 18, wherein the second semiconductor element is either a transistor or a diode.
Ａ１０～Ａ１３，Ａ２０，Ａ２１，Ａ３０，Ａ４０～Ａ４２：半導体装置
１０Ａ：第１ダイパッド　　　　１０Ｂ：第２ダイパッド
１０１：主面　　　　１０２：裏面
１０３：第１座面　　　　１０４：第１起立面
１０９：痕跡　　　　１１１：第１端面
１１２：第２端面　　　　１１３：第３端面
１１４：第４端面　　　　１２１：第１隅部端面
１２２：第２隅部端面　　　　１２３：第３隅部端面
１２４：第４隅部端面　　　　１３：端子リード
１４：第１端子リード　　　　１４Ａ：被覆部
１４Ｂ：露出部　　　　１４Ｃ：第２座面
１４Ｄ：第２起立面　　　　１５：第２端子リード
１５Ａ：被覆部　　　　１５Ｂ：露出部
１６：第３端子リード　　　　１６Ａ：被覆部
１６Ｂ：露出部　　　　１７１：第４端子リード
１７１Ａ：被覆部　　　　１７１Ｂ：露出部
１７２：第５端子リード　　　　１７２Ａ：被覆部
１７２Ｂ：露出部　　　　１８１：第６端子リード
１８１Ａ：被覆部　　　　１８１Ｂ：露出部
１８２：第７端子リード　　　　１８２Ａ：被覆部
１８２Ｂ：露出部　　　　２１：第１半導体素子
２１ａ：第１主面　　　　２１ｂ：第１裏面
２１１：第１主面電極　　　　２１２：主面電極
２１３：裏面電極　　　　２２：第２半導体素子
２２ａ：第２主面　　　　２２ｂ：第２裏面
２２１：第２主面電極　　　　２２２：主面電極
２２３：裏面電極　　　　２３１，２３２：ダイボンディング層
３１：第１導通部材　　　　３１１：第１本体部
３１２：第１接合部　　　　３１２ａ：第１帯状部
３１３：第２接合部　　　　３２：第２導通部材
３２１：第２本体部　　　　３２１ａ：第１延出部
３２１ｂ：第１基端　　　　３２１ｃ：第２延出部
３２１ｄ：第２基端　　　　３２１ｅ：第３延出部
３２１ｆ：第３基端　　　　３２２：第３接合部
３２３：第４接合部　　　　３２３ａ：第２帯状部
３３：第１接合層　　　　３４：第２接合層
３５：第３接合層　　　　３６：第４接合層
４１Ａ，４１Ｂ：第１接続部材　　　　４２Ａ，４２Ｂ：第２接続部材
５０：封止樹脂　　　　５１：樹脂主面
５２：樹脂裏面　　　　５３：第１側面
５４：第２側面　　　　５５：第３側面
５６：凹部　　　　５７：溝部
５８１，５８２：凹部　　　　５８９：痕跡
６：支持基板　　　　６１：絶縁層
６１１，６１２：板材　　　　６２：金属層
６２１，６２２：パッド部　　　　６３：金属層
６３１，６３２：パッド部　　　　６９：接合材 A10 to A13, A20, A21, A30, A40 to A42: Semiconductor device 10A: First die pad 10B: Second die pad 101: Main surface 102: Back surface 103: First seating surface 104: First upright surface 109: Trace 111: First end face 112: Second end face 113: Third end face 114: Fourth end face 121: First corner end face 122: Second corner end face 123: Third corner end face 124: Fourth corner end face 13: Terminal lead 14: First terminal lead 14A: Covering portion 14B: Exposed portion 14C: Second seating surface 14D: Second upright surface 15: Second terminal lead 15A: Covering portion 15B: Exposed portion 16: Third terminal lead 16A: Covering portion 16B: Exposed part 171: Fourth terminal lead 171A: Covering part 171B: Exposed part 172: Fifth terminal lead 172A: Covering part 172B: Exposed part 181: Sixth terminal lead 181A: Covering part 181B: Exposed part 182: Seventh Terminal lead 182A: Covering portion 182B: Exposed portion 21: First semiconductor element 21a: First main surface 21b: First back surface 211: First main surface electrode 212: Main surface electrode 213: Back electrode 22: Second semiconductor element 22a : Second main surface 22b: Second back surface 221: Second main surface electrode 222: Main surface electrode 223: Back electrode 231, 232: Die bonding layer 31: First conductive member 311: First main body part 312: First bonding Part 312a: First band-shaped part 313: Second joint part 32: Second conductive member 321: Second main body part 321a: First extending part 321b: First base end 321c: Second extending part 321d: Second base End 321e: Third extending portion 321f: Third base end 322: Third bonding portion 323: Fourth bonding portion 323a: Second strip portion 33: First bonding layer 34: Second bonding layer 35: Third bonding layer 36: Fourth bonding layer 41A, 41B: First connection member 42A, 42B: Second connection member 50: Sealing resin 51: Resin main surface 52: Resin back surface 53: First side surface 54: Second side surface 55: Third side surface Side surface 56: Recess 57: Groove 581, 582: Recess 589: Trace 6: Support substrate 61: Insulating layer 611, 612: Plate material 62: Metal layer 621, 622: Pad portion 63: Metal layer 631, 632: Pad portion 69: Bonding material

Claims (19)

  1. 　厚さ方向の一方を向く第１主面および前記第１主面に配置された第１主面電極を有する第１半導体素子と、
    　前記第１主面と同じ方向を向く第２主面および前記第２主面に配置された第２主面電極を有する第２半導体素子と、
    　前記第１半導体素子が搭載された第１ダイパッドと、
    　前記第１ダイパッドに対して前記厚さ方向に直交する第１方向の一方側に配置され、前記第２半導体素子が搭載された第２ダイパッドと、
    　前記第１ダイパッドおよび前記第２ダイパッドから離間する第１端子リードと、
    　前記第１主面電極と前記第２ダイパッドとを電気的に接続する第１導通部材と、
    　前記第２主面電極と前記第１端子リードとを電気的に接続する第２導通部材と、
    　前記第１半導体素子および前記第２半導体素子を覆う封止樹脂と、を備える半導体装置。     a first semiconductor element having a first main surface facing one side in the thickness direction and a first main surface electrode disposed on the first main surface;
    a second semiconductor element having a second main surface facing in the same direction as the first main surface and a second main surface electrode disposed on the second main surface;
    a first die pad on which the first semiconductor element is mounted;
    a second die pad arranged on one side of the first die pad in a first direction perpendicular to the thickness direction, and on which the second semiconductor element is mounted;
    a first terminal lead spaced apart from the first die pad and the second die pad;
    a first conductive member that electrically connects the first main surface electrode and the second die pad;
    a second conductive member that electrically connects the second main surface electrode and the first terminal lead;
    A semiconductor device comprising: a sealing resin that covers the first semiconductor element and the second semiconductor element.
  2. 　前記第１導通部材は、前記第１主面電極に接合された第１接合部と、前記第２ダイパッドに接合された第２接合部と、前記第１接合部と前記第２接合部とを繋ぐ第１本体部とを含む、請求項１に記載の半導体装置。 The first conductive member connects a first joint part joined to the first main surface electrode, a second joint part joined to the second die pad, and a first joint part and the second joint part. 2. The semiconductor device according to claim 1, further comprising a first main body portion that connects the first main body portion.
  3. 　前記第１本体部は、前記厚さ方向に見て、前記第１方向に沿って延びる、請求項２に記載の半導体装置。 The semiconductor device according to claim 2, wherein the first main body portion extends along the first direction when viewed in the thickness direction.
  4. 　前記厚さ方向に見たときの前記第１接合部の面積は、前記厚さ方向に見たときの前記第１主面電極の面積の１０％以上１００％以下である、請求項２または請求項３に記載の半導体装置。 2 or 3, wherein the area of the first joint when viewed in the thickness direction is 10% or more and 100% or less of the area of the first main surface electrode when viewed in the thickness direction. The semiconductor device according to item 3.
  5. 　前記第１接合部は、２つの第１帯状部を含み、
    　前記第１本体部のうちの前記第１接合部に繋がる端縁は、二股に分かれて前記２つの第１帯状部にそれぞれ繋がる、請求項２ないし請求項４のいずれかに記載の半導体装置。     The first joint portion includes two first strip portions,
    5. The semiconductor device according to claim 2, wherein an edge of the first main body portion connected to the first joint portion is bifurcated and connected to the two first band portions, respectively.
  6. 　前記第２導通部材は、前記第１端子リードに接合された第３接合部と、前記第２主面電極に接合された第４接合部と、前記第３接合部と前記第４接合部とを繋ぐ第２本体部とを含む、請求項１ないし請求項５のいずれかに記載の半導体装置。 The second conductive member includes a third joint part joined to the first terminal lead, a fourth joint part joined to the second main surface electrode, and the third joint part and the fourth joint part. 6. The semiconductor device according to claim 1, further comprising a second main body portion connecting the semiconductor device.
  7. 　前記第２本体部は、前記厚さ方向に見て屈曲する、請求項６に記載の半導体装置。 The semiconductor device according to claim 6, wherein the second main body portion is bent when viewed in the thickness direction.
  8. 　前記第２本体部は、前記第３接合部に繋がる端縁を第１基端として当該第１基端から前記厚さ方向および前記第１方向に直交する第２方向に延びる第１延出部と、前記第１延出部に繋がる端縁を第２基端として当該第２基端から前記第１方向に延びる第２延出部と、前記第２延出部に繋がる端縁を第３基端として当該第３基端から前記第２方向に延びる第３延出部と、を含み、
    　前記第３延出部は、前記第４接合部に繋がる、請求項７に記載の半導体装置。     The second main body part has a first extending part that extends from the first base end in a second direction perpendicular to the thickness direction and the first direction, with an edge connected to the third joint part as a first base end. a second extending portion extending in the first direction from the second base end with the edge connected to the first extending portion as a second base end; and a third extending portion extending from the second base end in the first direction; a third extending portion extending in the second direction from the third base end as a base end,
    8. The semiconductor device according to claim 7, wherein the third extension part is connected to the fourth junction part.
  9. 　前記厚さ方向に見たときの前記第４接合部の面積は、前記厚さ方向に見たときの前記第２主面電極の面積の１０％以上１００％以下である、請求項６ないし請求項８のいずれかに記載の半導体装置。 The area of the fourth joint when viewed in the thickness direction is 10% or more and 100% or less of the area of the second main surface electrode when viewed in the thickness direction. The semiconductor device according to any one of Item 8.
  10. 　前記第４接合部は、２つの第２帯状部を含み、
    　前記第２本体部のうちの前記第４接合部に繋がる端縁は、二股に分かれて前記２つの第２帯状部にそれぞれ繋がる、請求項６ないし請求項９のいずれかに記載の半導体装置。     The fourth joint portion includes two second strip portions,
    10. The semiconductor device according to claim 6, wherein an edge of the second main body part connected to the fourth joint part is bifurcated and connected to each of the two second band parts.
  11. 　前記第１ダイパッドに繋がる第２端子リードと、
    　前記第２ダイパッドに繋がる第３端子リードと、をさらに備え、
    　前記第１端子リード、前記第２端子リードおよび前記第３端子リードは、互いに離間する、請求項１ないし請求項１０のいずれかに記載の半導体装置。     a second terminal lead connected to the first die pad;
    further comprising a third terminal lead connected to the second die pad,
    11. The semiconductor device according to claim 1, wherein the first terminal lead, the second terminal lead, and the third terminal lead are spaced apart from each other.
  12. 　前記第１端子リードは、前記第１方向において、前記第２端子リードと前記第３端子リードとの間に位置する、請求項１１に記載の半導体装置。 The semiconductor device according to claim 11, wherein the first terminal lead is located between the second terminal lead and the third terminal lead in the first direction.
  13. 　各々が前記第１端子リード、前記第２端子リードおよび前記第３端子リードから離間し、且つ、互いに離間する第４端子リード、第５端子リード、第６端子リードおよび第７端子リードをさらに備える、請求項１１または請求項１２に記載の半導体装置。 Further comprising a fourth terminal lead, a fifth terminal lead, a sixth terminal lead, and a seventh terminal lead, each spaced apart from the first terminal lead, the second terminal lead, and the third terminal lead, and spaced apart from each other. , the semiconductor device according to claim 11 or claim 12.
  14. 　前記封止樹脂は、前記第１主面と同じ方向を向く樹脂主面と、前記樹脂主面から窪む少なくとも１つの凹部とを有し、
    　前記少なくとも１つの凹部の各々は、前記厚さ方向に見て、前記第１ダイパッドおよび前記第２ダイパッドのいずれかに重なる、請求項１ないし請求項１３のいずれかに記載の半導体装置。     The sealing resin has a resin main surface facing in the same direction as the first main surface, and at least one recess depressed from the resin main surface,
    14. The semiconductor device according to claim 1, wherein each of the at least one recess overlaps either the first die pad or the second die pad when viewed in the thickness direction.
  15. 　前記少なくとも１つの凹部の各々は、前記厚さ方向に見て、前記第１導通部材および前記第２導通部材のいずれにも重ならない、請求項１４に記載の半導体装置。 The semiconductor device according to claim 14, wherein each of the at least one recessed portion does not overlap either the first conductive member or the second conductive member when viewed in the thickness direction.
  16. 　前記厚さ方向に見て、前記第１半導体素子の重心は、前記第１ダイパッドの中心部に重なる、請求項１ないし請求項１５のいずれかに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 15, wherein the center of gravity of the first semiconductor element overlaps the center of the first die pad when viewed in the thickness direction.
  17. 　前記厚さ方向に見て、前記第２半導体素子の重心は、前記第２ダイパッドの中心部に重なる、請求項１ないし請求項１６のいずれかに記載の半導体装置。 17. The semiconductor device according to claim 1, wherein the center of gravity of the second semiconductor element overlaps the center of the second die pad when viewed in the thickness direction.
  18. 　前記第１ダイパッドおよび前記第２ダイパッドを支持する支持基板をさらに備え、
    　前記第１ダイパッドおよび前記第２ダイパッドは、前記厚さ方向において、前記支持基板に、前記第１半導体素子および前記第２半導体素子が搭載された側と反対側から支持されており、
    　前記支持基板は、セラミックスと、当該セラミックスの前記厚さ方向の両面に形成された一対の金属層とを含む、請求項１ないし請求項１７のいずれかに記載の半導体装置。     further comprising a support substrate that supports the first die pad and the second die pad,
    The first die pad and the second die pad are supported in the thickness direction by the supporting substrate from a side opposite to a side on which the first semiconductor element and the second semiconductor element are mounted,
    18. The semiconductor device according to claim 1, wherein the support substrate includes a ceramic and a pair of metal layers formed on both sides of the ceramic in the thickness direction.
  19. 　前記第１半導体素子は、トランジスタまたはダイオードのいずれかであり、
    　前記第２半導体素子は、トランジスタまたはダイオードのいずれかである、請求項１ないし請求項１８のいずれかに記載の半導体装置。     The first semiconductor element is either a transistor or a diode,
    19. The semiconductor device according to claim 1, wherein the second semiconductor element is either a transistor or a diode.
PCT/JP2023/019328 2022-06-15 2023-05-24 Semiconductor device WO2023243343A1 (en)

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JPH09129799A (en) * 1995-10-31 1997-05-16 Rohm Co Ltd Manufacture of semiconductor device and lead frame used therefor
JPH11111746A (en) * 1997-10-07 1999-04-23 Miyazaki Oki Electric Co Ltd Method and device for manufacturing semiconductor device
JP2010003718A (en) * 2008-06-18 2010-01-07 Panasonic Corp Heat-dissipating substrate and its manufacturing method, and module using heat-dissipating substrate
WO2021131611A1 (en) * 2019-12-25 2021-07-01 ローム株式会社 Semiconductor module
WO2022019023A1 (en) * 2020-07-20 2022-01-27 ローム株式会社 Semiconductor device

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JPH05326587A (en) * 1992-05-20 1993-12-10 Sony Corp Method and device for sealing resin-sealed-type semiconductor device
JPH09129799A (en) * 1995-10-31 1997-05-16 Rohm Co Ltd Manufacture of semiconductor device and lead frame used therefor
JPH11111746A (en) * 1997-10-07 1999-04-23 Miyazaki Oki Electric Co Ltd Method and device for manufacturing semiconductor device
JP2010003718A (en) * 2008-06-18 2010-01-07 Panasonic Corp Heat-dissipating substrate and its manufacturing method, and module using heat-dissipating substrate
WO2021131611A1 (en) * 2019-12-25 2021-07-01 ローム株式会社 Semiconductor module
WO2022019023A1 (en) * 2020-07-20 2022-01-27 ローム株式会社 Semiconductor device

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