WO2023232077A1

WO2023232077A1 - Display substrate and preparation method therefor, display panel, and display apparatus

Info

Publication number: WO2023232077A1
Application number: PCT/CN2023/097438
Authority: WO
Inventors: 王东方; 王利忠; 宁策; 袁广才
Original assignee: 京东方科技集团股份有限公司
Priority date: 2022-06-01
Filing date: 2023-05-31
Publication date: 2023-12-07
Also published as: CN115268155A; CN115268155B

Abstract

A display substrate (10) and a preparation method therefor, a display panel, and a display apparatus. A first thin film transistor (200a) is provided on a base substrate (100), and a first via hole (510a) corresponding to the first thin film transistor (200a) is provided in a first insulation layer (500a); a first connection electrode layer (710a) is provided on a first color resist (320a) corresponding to the first thin film transistor (200a); a second insulation layer (600a) is provided with a second via hole (620a) corresponding to the first thin film transistor (200a); and therefore a first pixel electrode (410a) can be electrically connected to the first connection electrode layer (710a) by means of the second via hole (620a), and the first connection electrode layer (710a) can be electrically connected to the source electrode of the first thin film transistor (200a) by means of the first via hole (510a).

Description

Display substrate and preparation method thereof, display panel and display device

This application claims priority to the Chinese patent application submitted to the China Patent Office on June 1, 2022, with the application number 202210621901.7 and the invention title "Display substrate and preparation method thereof, display panel and display device", and its content should be understood as Incorporated into this application by reference.

Technical field

Embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular, to a display substrate and a preparation method thereof, a display panel, and a display device.

Background technique

With the development of Augmented Reality (AR) products and Virtual Reality (VR) products, the number of pixels per inch of a Liquid Crystal Display (LCD), that is, high pixel density (Pixels Per Inch, PPI) demand is getting higher and higher. If the LCD display PPI increases, the pixel aperture rate will further decrease.

Contents of the invention

The following is an overview of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.

An embodiment of the present disclosure provides a display substrate, including:

base substrate; and

A plurality of pixel units are arranged in an array on the substrate;

Wherein, at least one of the plurality of pixel units includes:

A thin film transistor arranged on the base substrate;

a first insulating layer disposed on the thin film transistor, including a first via hole;

Color resistor, which is arranged on the first insulating layer;

a second insulating layer, which is disposed on the color resistor and includes a second via hole;

a pixel electrode, which is disposed on the second insulating layer; wherein the pixel electrode is electrically connected to a connection electrode layer disposed between the first insulating layer and the second insulating layer through the second via hole; connection, the source electrode of the thin film transistor is electrically connected to the first connection electrode layer through the first via hole.

In an exemplary embodiment, the plurality of pixel units include a first pixel unit, the thin film transistor is a first thin film transistor, the color resistor is a first color resistor, and the pixel electrode is a first pixel electrode. , and the connection electrode layer is the first connection electrode layer;

Wherein, the first connection electrode layer includes a first connection electrode part and a second connection electrode part connected in sequence;

The first connection electrode portion is disposed on a surface of the first color resistor away from the base substrate, and is electrically connected to the first pixel electrode through the second via hole;

The second connection electrode portion is disposed on a surface of the first insulating layer away from the base substrate, and is electrically connected to the source of the first thin film transistor through the first via hole.

In an exemplary embodiment, the plurality of pixel units further include a second pixel unit, the thin film transistor is a second thin film transistor, the color resistor is a second color resistor, and the pixel electrode is a second pixel electrode, and the connecting electrode layer is a second connecting electrode layer,

Wherein, the second connection electrode layer at least includes a third connection electrode portion disposed on a surface of the second color resistor close to the base substrate, and the third connection electrode portion is disposed on a surface close to the second color resistor. The surface of the base substrate.

In an exemplary embodiment, the second connection electrode layer further includes a fourth connection electrode part connected to the third connection electrode part; the fourth connection electrode part is disposed away from the second color resistor. The surface of the base substrate.

In an exemplary embodiment, the plurality of pixel units further include a third pixel unit, the thin film transistor is a third thin film transistor, the color resistor is a third color resistor, and the pixel electrode is a third pixel electrode, and the connection electrode layer is a third connection electrode layer;

Wherein, the orthographic projection of the second color resistor on the base substrate partially overlaps the orthographic projection of the third color resistor on the base substrate.

In an exemplary embodiment, the second via hole of the second pixel unit is provided at an end of the second connection electrode layer away from the third connection electrode layer;

The second via hole of the third pixel unit is provided at an end of the third connection electrode layer away from the second connection electrode layer.

In an exemplary embodiment, the second via hole is filled with a filter material that has the same color as the color resist.

In an exemplary embodiment, the method further includes: a black matrix layer disposed between adjacent pixel units, the black matrix layer being filled with a filter material having the same color as the color resistor.

In an exemplary embodiment, the thin film transistor includes a drain layer, a source layer and a gate layer sequentially arranged in a direction away from the base substrate,

Wherein, the source layer includes a first source electrode and a second source electrode, the first source electrode and the second source electrode are symmetrically arranged on both sides of the thin film transistor, and the first source electrode and the second source electrode are The second sources are arranged in the same layer.

In an exemplary embodiment, the thin film transistor further includes a drain insulating layer, an oxide semiconductor layer and a source insulating layer,

Wherein, the drain insulation layer is provided between the drain layer and the source layer;

The oxide semiconductor layer and the source insulating layer are arranged between the source layer and the gate layer, and are arranged in sequence in a direction away from the base substrate.

In an exemplary embodiment, the first insulating layer is a passivation layer, and the first via hole is filled with connection metal.

In an exemplary embodiment, the second via hole of the second insulating layer is filled with an insulating layer material, and the insulating layer material is in the orthographic projection of the base substrate and the connecting metal is in the Orthographic projections of the base substrate do not overlap.

In an exemplary embodiment, the first color resistor of the first pixel unit, the second color resistor of the second pixel unit and the third color resistor of the third pixel unit The color resistors are arranged at intervals on the first insulating layer, or there is overlap between adjacent color resistors.

In an exemplary embodiment, the first color resistor, the second color resistor and the third color resistor have different colors.

In an exemplary embodiment, the plurality of pixel units further includes a fourth pixel unit, and the connection method between the pixel electrode of the pixel unit and the source electrode of the corresponding thin film transistor is different from that of the fourth pixel unit. The connection method between the first pixel electrode and the source electrode of the first thin film transistor.

Embodiments of the present disclosure provide a display panel, including: a display substrate, an opposite substrate, and a liquid crystal layer located between the display substrate and the opposite substrate;

Wherein, the display substrate is any of the above display substrates.

An embodiment of the present disclosure also provides a display device, including: the above display panel.

An embodiment of the present disclosure also provides a method for preparing a display substrate, including:

Provide base substrate;

A plurality of pixel units are formed on the base substrate, and an array is arranged on the base substrate;

Wherein, at least one of the plurality of pixel units includes:

A thin film transistor arranged on the base substrate;

Color resistor, which is arranged on the first insulating layer;

A pixel electrode arranged on the second insulating layer;

Wherein, the pixel electrode is electrically connected to the connection electrode layer provided between the first insulating layer and the second insulating layer through the second via hole, and the source electrode of the thin film transistor passes through the first insulating layer. The via hole is electrically connected to the first connection electrode layer.

In an exemplary implementation, forming a plurality of pixel units on the base substrate includes:

Form a first color resistor on the surface of the first insulating layer away from the base substrate;

forming a first connection electrode layer;

A second color resistor is formed, and the second color resistor is spaced apart from the first color resistor.

In an exemplary embodiment, after forming the second color resistor, the method further includes:

A fourth connection electrode portion is formed on a surface of the second color resistor away from the base substrate.

Other aspects will be apparent after reading and understanding the drawings and detailed description.

Description of the drawings

Figure 1 shows an exemplary cross-sectional structural diagram of a liquid crystal display substrate;

FIG. 2 shows an exemplary planar structural diagram of a liquid crystal display substrate.

FIG. 3A shows a schematic cross-sectional structural diagram of an exemplary display substrate according to an embodiment of the present disclosure.

FIG. 3B shows a schematic cross-sectional structural diagram of the first pixel unit of an exemplary display substrate according to an embodiment of the present disclosure.

FIG. 4 shows a simplified cross-sectional structural diagram of an exemplary display substrate according to an embodiment of the present disclosure.

FIG. 5 shows another structural schematic diagram of an exemplary display substrate according to an embodiment of the present disclosure.

FIG. 6 shows another structural schematic diagram of an exemplary display substrate according to an embodiment of the present disclosure.

FIG. 7 shows yet another structural schematic diagram of an exemplary display substrate according to an embodiment of the present disclosure.

FIG. 8 shows yet another structural schematic diagram of an exemplary display substrate according to an embodiment of the present disclosure.

FIG. 9 shows yet another structural schematic diagram of an exemplary display substrate according to an embodiment of the present disclosure.

FIG. 10 shows yet another structural schematic diagram of an exemplary display substrate according to the disclosed embodiments.

FIG. 11 shows a schematic structural diagram of an exemplary display panel according to an embodiment of the present disclosure.

FIG. 12 illustrates an exemplary display substrate preparation method according to an embodiment of the present disclosure.

Figure 13a shows a schematic diagram of an intermediate structure during preparation of an exemplary display substrate according to an embodiment of the present disclosure;

Figure 13b shows a schematic diagram of another intermediate structure during preparation of an exemplary display substrate according to an embodiment of the present disclosure;

Figure 13c shows a schematic diagram of another intermediate structure during preparation of an exemplary display substrate according to an embodiment of the present disclosure;

Figure 13d shows a schematic diagram of another intermediate structure during preparation of an exemplary display substrate according to an embodiment of the present disclosure;

Figure 13e shows a schematic diagram of another intermediate structure during preparation of an exemplary display substrate according to an embodiment of the present disclosure;

Figure 13f shows yet another intermediate structure during preparation of an exemplary display substrate according to an embodiment of the present disclosure. structural diagram;

Figure 13g shows a schematic diagram of another intermediate structure during preparation of an exemplary display substrate according to an embodiment of the present disclosure;

Figure 13h shows a schematic diagram of another intermediate structure during preparation of an exemplary display substrate according to an embodiment of the present disclosure;

Figure 13i shows a schematic diagram of another intermediate structure during preparation of an exemplary display substrate according to an embodiment of the present disclosure;

Figure 13j shows a schematic diagram of another intermediate structure during preparation of an exemplary display substrate according to an embodiment of the present disclosure;

Figure 13k shows a schematic diagram of another intermediate structure during preparation of an exemplary display substrate according to an embodiment of the present disclosure;

Figure 13m shows another structural schematic diagram of an exemplary display substrate according to an embodiment of the present disclosure;

FIG. 13n shows another structural schematic diagram of an exemplary display substrate according to an embodiment of the present disclosure.

Detailed ways

Specific implementations of the present disclosure will be described in further detail below with reference to the accompanying drawings and examples. The following examples are used to illustrate the present disclosure and are exemplary only, but are not intended to limit the scope of the present disclosure. The embodiments and features in the embodiments of the present disclosure may be arbitrarily combined with each other unless there is any conflict.

It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of this disclosure should have the usual meanings understood by those with ordinary skills in the field to which this disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprising" mean that the elements or things appearing before the word include the elements or things listed after the word and their equivalents, without excluding other elements or things. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", etc. are only used to express relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. As the current mainstream display device, liquid crystal display devices have the advantages of low power consumption, small size, and low radiation. The LCD panel is a non-self-luminous panel and needs to be used with a backlight module. The imaging principle of the liquid crystal display device is to place the liquid crystal between the color filter substrate and the thin film transistor array substrate. By applying a driving voltage on the two substrates, the electric field effect of distorting the liquid crystal molecules is caused to control the backlight transmission or Masking function to display the image.

COA (Color Filter on Array) technology is a technology that prepares the color filter layer on the array substrate, which can increase the aperture ratio and eliminate the later alignment process of the color filter substrate and the thin film transistor array substrate.

The display substrate provided by the embodiment of the present disclosure is a liquid crystal display substrate. The liquid crystal display substrate can be used in a passive display mode and can be applied to high PPI displays, such as virtual reality (Virtual Reality, referred to as VR), augmented reality (Augmented Reality, referred to as AR) ), mixed reality (MR) and other thin and light near-eye displays, light field displays, and vehicle-mounted displays.

FIG. 1 shows an exemplary cross-sectional structural diagram of a liquid crystal display substrate.

As shown in FIG. 1 , the liquid crystal display substrate includes a plurality of thin film transistors 200 , a plurality of color resistors 310 and a plurality of pixel electrodes 400 . The plurality of color resistors 310 and the plurality of pixel electrodes 400 are arranged in one-to-one correspondence with the plurality of thin film transistors 200 . The pixel electrode 400 is electrically connected to the thin film transistor 200 (for example, the source) through a via hole 311 that penetrates the color resistor. The via hole 311 is filled with connection metal (for example, metal material for pixel electrodes).

As shown in FIG. 2 , the color resistor 310 is provided with a via hole 311 penetrating the color resistor 310 . For high PPI display substrates, the PPI can reach 2000PPI to 3000PPI, and the size of a single pixel is often small. At this time, a via hole is opened on the color resistor 310. Due to the characteristics of the organic material of the color resistor 310, the aperture of the via hole 311 is larger. , which will result in reduced light efficiency. Therefore, the improvement in aperture ratio and transmittance achieved by the COA process will not be reflected due to the increase in the area occupied by the via holes of the color resistor.

Embodiments of the present disclosure provide for connecting the pixel electrode and the thin film transistor through the side of the color resistor, or filling the holes of the color resistor, which can solve the problem of reduced light efficiency caused by the color resistor via hole to a certain extent.

3A, 3B, and 4 show schematic structural diagrams of an exemplary display substrate according to embodiments of the present disclosure. 3A is a schematic cross-sectional structural diagram of an exemplary display substrate according to an embodiment of the present disclosure. FIG. 3B is a schematic cross-sectional structural diagram of a pixel unit of an exemplary display substrate according to an embodiment of the present disclosure. FIG. 4 is a simplified cross-sectional structural diagram of an exemplary display substrate according to an embodiment of the present disclosure.

As shown in FIG. 3A and FIG. 4 , the display substrate 10 provided by the embodiment of the present disclosure may include:

Base substrate 100; a plurality of pixel units may be provided on the base substrate 100, such as a first pixel unit 100a, a second pixel unit 100b and a third pixel unit 100c. In some embodiments, these pixel units may be arranged in an array on the base substrate 100, and may further include the following structures. In an exemplary implementation, the first pixel unit 100a, the second pixel unit 100b and the third pixel unit 100c may all be sub-pixel units. For example, the first pixel unit 100a may be a red sub-pixel unit, a second pixel unit The unit 100b can be a green sub-pixel unit, and the third pixel unit 100c can be a blue sub-pixel unit to emit light of different colors to form a color pixel. The following takes the first pixel unit 100a as an example to describe the structure of the pixel unit. The structures of the second pixel unit 100b and the third pixel unit 100c may be the same as the structure of the first pixel unit 100a.

Referring to FIG. 3B , the first pixel unit 100a according to the embodiment of the present disclosure may include:

The first thin film transistor 200a is provided on the base substrate;

A first insulating layer 500a is provided on the first thin film transistor 200a and includes a first via hole 510a;

A first color resistor 320a is provided on the first insulating layer 500a;

The second insulating layer 600a is provided on the first color resistor 320a and includes a second via hole 620a;

The first pixel electrode 410a is provided on the second insulation layer 600a.

Wherein, the first pixel electrode 410a is electrically connected to the first connection electrode layer 710a provided between the first insulating layer 500a and the second insulating layer 600a through the second via hole 620a. The source electrode of a thin film transistor 200a is electrically connected to the first connection electrode layer 710a through the first via hole 510a. In an exemplary implementation, as shown in FIG. 4 , the color resistors and pixel electrodes in the display substrate provided by embodiments of the present disclosure are arranged corresponding to the thin film transistors.

In the display substrate 10 provided by the embodiment of the present disclosure, a first thin film transistor 200a is provided on the base substrate 100, and a first via hole 510a corresponding to the first thin film transistor 200a is opened in the first insulating layer 500a. The first connection electrode layer 710a is provided between the first insulating layer 500a and the second insulating layer 600a. A second via hole 620a is provided in the second insulating layer 600a. In this way, the first pixel electrode can be 410a is electrically connected to the first connection electrode layer 710a through the second via hole 620a, and the first connection electrode layer 710a is in turn electrically connected to the source of the first thin film transistor 200a through the first via hole 510a. In this way, the electrical connection between the first pixel electrode 410a and the source of the first thin film transistor 200a is realized, without the need to provide a via hole on the first color resistor 320a, and the problem caused by providing a via hole on the first color resistor 320a is avoided. Loss of aperture ratio or light efficiency, etc.

In some embodiments, the base substrate 100 may be a transparent substrate. For example, the base substrate 100 may be a glass substrate and has the function of supporting and carrying.

In some embodiments, the first thin film transistor 200a may be a vertical thin film transistor. For example, as shown in FIG. 3B , it may include a drain layer 210a, a drain insulating layer 220a, a source layer 230a, an oxide semiconductor layer 240a, a source insulating layer 250a and a gate layer that are sequentially arranged in a direction away from the base substrate 100. 260a. Wherein, the source layer 230a may include a first source electrode and a second source electrode, the first source electrode and the second source electrode are symmetrically arranged on both sides of the thin film transistor, and the first source electrode and the second source electrode are The second sources are arranged in the same layer. In this way, by arranging vertical thin film transistors, the aperture ratio of the display substrate can be increased to a certain extent, for example by about 10%, compared to ordinary thin film transistors in which the source layer and drain layer are arranged in the same layer.

In some embodiments, the structures of the first thin film transistor of the first pixel unit 100a, the second thin film transistor of the second pixel unit 100b, and the third thin film transistor of the third pixel unit 100c may be the same, for example, they may all be as shown in FIG. 3B. shows the structure of a vertical thin film transistor. The structures of the first insulating layer and the second insulating layer in the first pixel unit 100a, the second pixel unit 100b and the third pixel unit 100c may also be the same.

In some embodiments, the first insulating layer 500a may be a passivation layer, and the passivation layer may be an oxide, a nitride, an oxygen-nitride compound, or the like. The passivation layer can be a single layer or multiple layers. The passivation layer can protect the thin film transistor. The first via hole 510a penetrates the first insulating layer 500a and is electrically connected to the source of the first thin film transistor 200a. In an exemplary embodiment, the via holes are filled with connection metal.

In some embodiments, returning to FIG. 3B, the second insulating layer 600a can cover the first color resistor 320a in the first pixel unit 100a, that is, the second insulating layer 600a can be disposed away from the first color resistor 320a. one side of the base substrate 100 .

In some embodiments, the second via hole 620a of the second insulating layer 600a may be filled with There is a second insulating layer of material. The orthographic projection of the second insulating layer material on the base substrate 100 does not overlap with the orthographic projection of the connection metal on the base substrate 100 . In this way, the gaps in the via holes in the second insulating layer 600a can be filled, which is beneficial to reducing the loss of light efficiency.

In some embodiments, the second via hole 620a of the second insulating layer may also be filled with a filter material that has the same color as the first color resistor. In this way, the gap in the second via hole 620a in the second insulating layer 600a can be filled, which is beneficial to reducing the loss of light efficiency.

In some embodiments, the display substrate may further include a black matrix layer disposed between adjacent pixel units, and a via coaxial with the second via hole may be disposed in the black matrix layer. hole and fill it with a filter material of the same color as the color resist. In this way, the gaps in the via holes in the second insulating layer 600a can be filled in the periphery, which is beneficial to reducing the loss of light efficiency.

In an exemplary embodiment, the color of the first color resistor 320a may be any one of red, green, or blue. The embodiments of the present disclosure do not limit this.

In some embodiments, the first color resistor of the first pixel unit, the second color resistor of the second pixel unit, and the third color resistor of the third pixel unit may be arranged at intervals on the first insulating layer, or may be in phase. There is an overlapping arrangement between adjacent color resistors (for example, Figure 6), as long as the subsequent process can make the overlapping portion flat.

In some embodiments, in the first pixel unit 100a, the first connection electrode layer 710a disposed on the surface of the first color resistor 320a may include a first connection electrode part 711a and a second connection electrode part 712a connected in sequence. The first connection electrode portion 711a is disposed on a surface of the first color resistor 320a away from the base substrate 100 and is electrically connected to the first pixel electrode 410a through the second via hole 620a. The second connection electrode portion 712a is disposed on a surface of the first insulating layer 500a away from the base substrate 100, and is electrically connected to the source of the first thin film transistor 200a through the first via hole 510a. In an exemplary embodiment, as shown in FIG. 5 , the first connection electrode part 711 a may be disposed on a surface of the color resistor 320 a away from the base substrate 100 (that is, on the surface of the first color resistor 320 a surface) and two side surfaces of the first color resistor 320a (that is, the two surfaces adjacent to the upper surface). In this way, the first connection electrode layer 710a can be electrically connected to the second via hole 620a through the first connection electrode part 711a, and can be electrically connected to the pixel electrode 410a through the second via hole 620a. The second connection electrode portion 712a may be disposed on the first insulating layer 500a away from the base substrate. 100, and the surface of the second connection electrode portion 712a close to the first edge layer 500a can be electrically connected to the first via hole 510a. In this way, the first connection electrode layer 710a can be electrically connected to the first via hole 510a through the second connection electrode portion 712a, and can be electrically connected to the source of the first thin film transistor 200a through the first via hole 510a.

That is to say, in the embodiment of the present disclosure, the first color resistor 320a can be connected from the first color resistor 320a through the first connection electrode layer 710a provided on the side of the first color resistor 320a away from the base substrate 100 and the side of the first color resistor 320a. The side part of the first thin film transistor 200a is electrically connected to the source of the thin film transistor 200a. There is no need to set a color resistor opening in the first color resistor 320a to realize the electrical connection between the first pixel electrode 410a and the source of the first thin film transistor 200a, effectively improving the light efficiency. .

In some embodiments, the connection methods between the corresponding pixel electrodes and the source electrodes of the corresponding thin film transistors in the first pixel unit 100a, the second pixel unit 100b, and the third pixel unit 100d may be the same, for example, The connection method between the first pixel electrode 410a and the source electrode of the first thin film transistor 200a is the same. For example, as shown in Figure 3a. In some embodiments, the color resistors in the second pixel unit 100b and the third pixel unit 100c may be provided with corresponding second connection electrode layers having the same structure as the first connection electrode layer 710a. In the third pixel unit 100c, The color resistor may be provided with a corresponding third connection electrode layer having the same structure as the first connection electrode layer 710a, for example, as shown in FIG. 5 . In an exemplary embodiment, the structures of the second connection electrode layer and the third connection electrode layer may also be different from the structure of the first connection electrode layer 710a.

In some embodiments, the second pixel unit 100b may further include a second connection electrode layer having a different structure from the first connection electrode layer 710a. In some embodiments, the second connection electrode layer includes at least a third connection electrode portion 711b. The third connection electrode part 711b is provided on the surface of the color resistor 320b close to the base substrate 100 . For example, as shown in FIG. 6 , the third connection electrode part 711b is provided on the surface of the second color resistor 320b close to the base substrate 100 . In this way, there is no need to provide color resistor openings for the second color resistor 320b. Moreover, the second connection electrode layer of this structure can be arranged at the same layer interval as the first connection electrode layer 710a, so that the first connection electrode layer 710a can be formed at the same time after one deposition and patterning process, thereby simplifying the process. In an exemplary embodiment, the structure of the third connection electrode layer of the third pixel unit 100c may be the same as the structure of the second connection electrode layer of the pixel unit 100b.

In some embodiments, in the third pixel unit 100c, the third color resistor 320c may be overlapped with the second color resistor 320b in the second pixel unit 100b. In an exemplary embodiment, the orthographic projection of the third color resistor 320c on the base substrate may partially overlap with the orthographic projection of the second color resistor 320b on the base substrate to prevent the second color resistor 320b and the third color resistor from 320c has light leakage at the edges. The second via hole 620b in the second pixel unit 100b is provided at an end of the second connection electrode layer away from the third connection electrode layer in the third pixel unit 100c. The second via hole 620c of the third pixel unit 100c is provided at an end of the third connection electrode layer away from the second connection electrode layer.

In some embodiments, the second connection electrode layer may further include a fourth connection electrode part 712b connected to the third connection electrode part 711b. The fourth connection electrode part 712b is disposed on the surface of the color resistor 320b away from the base substrate 100; the third connection electrode part 711b is electrically connected to the second via hole 620b through the fourth connection electrode part 712b. . Referring to FIG. 7 , the fourth connecting electrode portion 712 b may be electrically connected to the second via hole 620 b through a middle portion close to the surface of the second insulating layer 600 . In an exemplary embodiment, the structures of the third connection electrode layer of the third pixel unit 100c and the second connection electrode layer of the second pixel unit 100b may be the same.

Referring to FIG. 6 , the second color resistor 320b, the third color resistor 320c, and the first color resistor 320a are arranged adjacent to each other. In an exemplary embodiment, the colors of the first color resistor 320a, the second color resistor 320b and the third color resistor 320c are all different. For example, the first color resistor 320a can be red and the second color resistor 320b can be blue. The color and the third color resistor 320c can be green; or the first color resistor 320a can be green, the second color resistor 320b can be blue, and the third color resistor 320c can be red; or the first color resistor 320a can be green. , the second color resistor 320b can be red, and the third color resistor 320c can be blue; or the first color resistor 320a can be blue, the second color resistor 320b can be red, and the third color resistor 320c can be Green etc. In this way, the three can form a colored pixel unit.

In some embodiments, the display substrate may further include a fourth pixel unit, the connection between the pixel electrode 410d and the source of the thin film transistor 200d is different from the connection between the first pixel electrode 410a and the source of the thin film transistor 200a. Connection method.

For example, as shown in FIG. 8 , the display substrate may further include a fourth color resistor 320d having a different structure from the first color resistor 320a. A color resist via hole 321 may be provided on the fourth color resistor 320d. Among them, the A light-absorbing material 322 may be disposed in the color resist via hole 321 to block the fourth opening and reduce the aperture of the via hole.

In some embodiments, the light-absorbing material 322 may be filled in the fourth color resist via hole 321 . For example, the light-absorbing material 322 may be a color resist material of the same color as the fourth color resist 320d, as shown in FIG. 8 . Or the light-absorbing material 322 can be a black light-shielding material (such as BM material), as shown in FIG. 9 .

In other embodiments, the light-absorbing material 322 may be disposed around the via hole of the fourth color resistor 320d, for example, as shown in FIG. 10 . At this time, the light-absorbing material 322 may be a black light-shielding material (such as BM material).

In some embodiments, a third insulating layer may be disposed on a side of the plurality of pixel electrodes away from the base substrate 100 , and a common electrode may be disposed on the third insulating layer.

An embodiment of the present disclosure also provides a display panel. FIG. 11 shows a schematic structural diagram of an exemplary display panel according to an embodiment of the present disclosure.

As shown in Figure 11, the display panel of the embodiment of the present disclosure may include a display substrate 10, an opposite side substrate 30, and a liquid crystal molecule layer 20 located between the display substrate 10 and the opposite side substrate 30; the display substrate 10 is the aforementioned display substrate Display substrate 10 in the embodiment.

The display panel of the above embodiments can include the corresponding display substrate 10 in any of the above embodiments, and can achieve the beneficial effects of the corresponding display substrate embodiments, which will not be described again here.

An embodiment of the present disclosure also provides a display device. The display device includes a display panel in any of the aforementioned display substrate embodiments.

In an exemplary implementation, the display device may be a mobile phone, a television, a personal digital assistant, a digital camera, a notebook computer, a desktop computer, etc. This embodiment is not limited here.

The display device of the above embodiments may include the display substrate in any of the foregoing embodiments, and may achieve the beneficial effects of the corresponding display substrate embodiments, which will not be described again here.

Embodiments of the present disclosure also provide a method of manufacturing the display substrate 10 . FIG. 12 illustrates an exemplary preparation method of the display substrate 10 according to an embodiment of the present disclosure.

Referring to FIG. 12 , in step S1010 , the base substrate 100 may be obtained first.

In some embodiments, if the display substrate is a common display device, the substrate substrate 100 can be made of glass or other rigid materials. If the display substrate is a flexible display device, the substrate substrate 100 can be made of polyimide (PI) or other rigid materials. Other flexible materials.

In step S1020, a plurality of pixel units arranged in an array may be formed on the base substrate 100. The description takes the first pixel unit, for example, the first pixel unit 100a as an example.

In some embodiments, standard methods may be used to clean the base substrate 100 first. Then, a drain layer (for example, the drain layer 210a) is formed on the base substrate 100 by sputtering, chemical vapor deposition (CVD), etc., and is patterned, and a signal line (for example, Date line), forming a structure as shown in Figure 13a.

In some embodiments, a drain insulating layer (eg, drain insulating layer 220a) and The source layer (for example, source layer 230a) is patterned, and signal lines (for example, Date lines) are drawn out to form a structure as shown in Figure 13b. The drain insulating layer 220 may be made of silicon oxide, aluminum oxide, or the like. Thickness can be from 1000 to 10000A.

In some embodiments, the source layer (for example, the source layer 230a) and the drain insulation layer (for example, the drain insulation layer 220a) can be etched sequentially through patterning processing to form a channel, which is formed on the thin film. The first source electrode and the second source electrode are symmetrically arranged on both sides of the transistor, and the first source electrode and the second source electrode are arranged in the same layer, that is, a structure as shown in Figure 13c is obtained.

In some embodiments, an oxide semiconductor layer (eg, oxide semiconductor layer 240a) may be deposited on the source layer (eg, source layer 230a) by means of chemical vapor deposition (CVD) or atomic layer deposition (ALD). ), and perform graphic processing to obtain the structure shown in Figure 13d. The material of the oxide semiconductor layer 240 may be IGZO, ITZO, IAZO, etc.

In some embodiments, a source insulating layer (eg, source insulating layer) may be sequentially deposited on the oxide semiconductor layer source layer (eg, oxide semiconductor layer 240a) by means of chemical vapor deposition (CVD) or atomic layer deposition (ALD). Insulating layer 250a) and gate layer (for example, gate layer 260a), and Shaping process, the structure shown in Figure 13e is obtained. In this way, a thin film transistor is prepared. The material of the source insulating layer 250a may be SiOx, or other insulating materials compatible with oxide semiconductors may also be used. The thickness of the SiOx layer can be from 200 to 3000A.

In some embodiments, a first insulating layer (such as a first insulating layer 500a) is formed on the thin film transistor; the first insulating layer 500a is provided with a first via hole 510a corresponding to the first thin film transistor 200a. . For example, the first insulating layer 500a can be deposited on the gate layer 260a by chemical vapor deposition (CVD) or atomic layer deposition (ALD) to obtain the structure shown in FIG. 13f. The first insulating layer 500a may be a SiOx or SiOx/SiNx composite film layer with a thickness of about 1000 to 10000A.

In some embodiments, a plurality of color resistors are formed on the first insulating layer 500a, including a first color resistor 320a corresponding to the first thin film transistor 200a; a connection electrode layer is formed on the first color resistor 320a. ; The connection electrode layer extends from the first color resistor 320a layer to the first via hole 510a, and is connected to the source of the thin film transistor.

In some embodiments, a first color resistor 320a is formed on the surface of the first insulating layer 500a away from the base substrate 100, and the first color resistor 320a can be coated on the first insulating layer 500a, as shown in Figure 13g. Structure. The first color resistor 320a can be one of RGB CF, with a thickness of 1.2 to 3um, and can be patterned as needed.

In some embodiments, the first connection electrode layer is formed on a surface of the first color resistor 320a away from the base substrate 100 . In an exemplary embodiment, ITO or other transparent electrodes 300 to 1000A may be deposited on the first color resistor 320a to form a first connection electrode layer and a third connection electrode portion of the second connection electrode layer. Pattern as needed, bringing all electrodes connecting the electrode layer to the color resistor surface.

In some embodiments, a second color resistor is formed on a surface of the first electrical connection layer away from the base substrate 100 , and the second color resistor is arranged adjacent to or spaced apart from the first color resistor 320a. In an exemplary embodiment, another two types of RGB CF can be coated with a thickness of 1.2 to 3um and patterned as needed to obtain the structure shown in Figure 13h.

In some embodiments, it may also include forming a fourth connection electrode portion on a surface of the second color resistor away from the base substrate 100 to obtain the structure shown in FIG. 13i. In an exemplary embodiment, ITO or other transparent electrodes 300 to 1000A may be deposited and patterned as needed, and the fourth connection electrode part 712b or the fourth connection electrode part 712c will be led to the respective upper surfaces of the color resistors. .

In some embodiments, it also includes forming a second insulating layer 600a on the first color resistor, the second color resistor and the third color resistor; the second insulating layer 600a is provided with a layer corresponding to the thin film transistor 200a. For the second via hole, the structure shown in Figure 13j or Figure 13k is obtained. In an exemplary embodiment, a PLN layer with a thickness of 2 to 4 μm can be applied, the CF is planarized, and patterned as needed.

In some embodiments, a plurality of pixel electrodes are formed on the second insulating layer 600a, and the plurality of pixel electrodes are arranged in one-to-one correspondence with the plurality of color resistors; the pixel electrodes include those connected to the first thin film transistor 200a. With the correspondingly provided first pixel electrode 410a, the display substrate shown in FIG. 6 or 7 is obtained. In an exemplary embodiment, pixel electrodes ITO 300 to 1000A may be deposited and patterned as needed.

In some embodiments, it may also include coating a PLN layer with a thickness of 2 to 4 μm on the pixel electrode, flattening the PLN holes, and patterning as needed. and deposit the common electrode. Finally, the display substrate shown in Figure 13m or Figure 13n is obtained.

Persons of ordinary skill in the art of source insulating layers should understand that the above discussion of any embodiments is only illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples; under the spirit of the present disclosure, The technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes in different aspects of the embodiments of the present disclosure as described above, which are not included in the details for the sake of simplicity. supply.

Additionally, to simplify illustration and discussion, and so as not to obscure embodiments of the present disclosure, well-known power supplies/components with integrated circuit (IC) chips and other components may or may not be shown in the provided figures. Ground connection. Furthermore, devices may be shown in block diagram form in order to avoid obscuring the embodiments of the present disclosure, and this also takes into account the fact that details regarding the implementation of these block diagram devices are highly dependent on the implementation of the disclosed embodiments. platform (i.e., these details should be well within the understanding of those skilled in the art). Where details (eg, circuitry) are set forth to describe exemplary embodiments of the present disclosure, it will be apparent to those skilled in the art that the present invention may be practiced without these details or with changes in these details. Disclosed Examples. Accordingly, these descriptions should be considered illustrative rather than restrictive.

Although the present disclosure has been described in conjunction with its embodiments, many substitutions, modifications and variations of these embodiments will become apparent to those of ordinary skill in the art in light of the foregoing description. Obvious. For example, other memory architectures such as dynamic RAM (DRAM) may use the discussed embodiments.

The disclosed embodiments are intended to embrace all such alternatives, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

A display substrate includes:

base substrate; and

A plurality of pixel units are arranged in an array on the substrate;

Wherein, at least one of the plurality of pixel units includes:

A thin film transistor arranged on the base substrate;

a first insulating layer disposed on the thin film transistor, including a first via hole;

Color resistor, which is arranged on the first insulating layer;

a second insulating layer, which is disposed on the color resistor and includes a second via hole;

a pixel electrode, which is disposed on the second insulating layer; wherein the pixel electrode is electrically connected to a connection electrode layer disposed between the first insulating layer and the second insulating layer through the second via hole; connection, the source electrode of the thin film transistor is electrically connected to the first connection electrode layer through the first via hole.
The display substrate according to claim 1, wherein the plurality of pixel units include a first pixel unit, the thin film transistor is a first thin film transistor, the color resistor is a first color resistor, and the pixel electrode is a first color resistor. a pixel electrode, and the connection electrode layer is a first connection electrode layer;

Wherein, the first connection electrode layer includes a first connection electrode part and a second connection electrode part connected in sequence;

The first connection electrode portion is disposed on a surface of the first color resistor away from the base substrate, and is electrically connected to the first pixel electrode through the second via hole;

The second connection electrode portion is disposed on a surface of the first insulating layer away from the base substrate, and is electrically connected to the source of the first thin film transistor through the first via hole.
The display substrate according to claim 2, wherein the plurality of pixel units further includes a second pixel unit, the thin film transistor is a second thin film transistor, the color resistor is a second color resistor, and the pixel electrode is a second pixel electrode, and the connection electrode layer is a second connection electrode layer,

Wherein, the second connection electrode layer at least includes a third connection electrode portion disposed on a surface of the second color resistor close to the base substrate, and the third connection electrode portion is disposed on a surface of the second color resistor. close to the surface of the substrate.
The display substrate according to claim 3, wherein the second connection electrode layer further includes a fourth connection electrode part connected to the third connection electrode part; the fourth connection electrode part is disposed on the second connection electrode layer. The color resist is away from the surface of the base substrate.
The display substrate according to claim 3, wherein the plurality of pixel units further includes a third pixel unit, the thin film transistor is a third thin film transistor, the color resistor is a third color resistor, and the pixel electrode is a third pixel electrode, and the connection electrode layer is a third connection electrode layer;

Wherein, the orthographic projection of the second color resistor on the base substrate partially overlaps the orthographic projection of the third color resistor on the base substrate.
The display substrate according to claim 5, wherein

The second via hole of the second pixel unit is provided at an end of the second connection electrode layer away from the third connection electrode layer;

The second via hole of the third pixel unit is provided at an end of the third connection electrode layer away from the second connection electrode layer.
The display substrate according to claim 1, wherein the second via hole is filled with a filter material having the same color as the color resistor.
The display substrate according to claim 1, further comprising: a black matrix layer disposed between adjacent pixel units, the black matrix layer being filled with a filter material having the same color as the color resistor.
The display substrate according to claim 1, wherein the thin film transistor includes a drain layer, a source layer and a gate layer sequentially arranged in a direction away from the base substrate,

Wherein, the source layer includes a first source electrode and a second source electrode, the first source electrode and the second source electrode are symmetrically arranged on both sides of the thin film transistor, and the first source electrode and the second source electrode are The second sources are arranged in the same layer.
The display substrate according to claim 9, wherein the thin film transistor further includes a drain insulating layer, an oxide semiconductor layer and a source insulating layer,

Wherein, the drain insulation layer is provided between the drain layer and the source layer;

The oxide semiconductor layer and the source insulating layer are provided between the source layer and the gate layer, and are arranged sequentially in a direction away from the base substrate.
The display substrate according to claim 1, wherein the first insulating layer is a passivation layer, and the first via hole is filled with connection metal.
The display substrate according to claim 11, wherein

The second via hole of the second insulating layer is filled with an insulating layer material, and the orthographic projection of the insulating layer material on the base substrate does not overlap with the orthographic projection of the connection metal on the base substrate. .
The display substrate according to claim 5, wherein the first color resistor of the first pixel unit, the second color resistor of the second pixel unit and the third color resistor of the third pixel unit Three color resistors are arranged at intervals on the first insulating layer, or adjacent color resistors overlap.
The display substrate according to claim 13, wherein the first color resistor, the second color resistor and the third color resistor have different colors.
The display substrate according to claim 5, wherein the plurality of pixel units further includes a fourth pixel unit, and the connection method between the pixel electrode of the fourth pixel unit and the source electrode of the corresponding thin film transistor is different from The connection method between the first pixel electrode and the source electrode of the first thin film transistor.
A display panel, including: a display substrate, an opposite substrate, and a liquid crystal layer located between the display substrate and the opposite substrate;

Wherein, the display substrate is the display substrate according to any one of claims 1 to 15.
A display device, comprising: the display panel according to claim 16.
A preparation method for a display substrate, including:

Provide base substrate;

A plurality of pixel units are formed on the base substrate, and an array is arranged on the base substrate;

Wherein, at least one of the plurality of pixel units includes:

A thin film transistor arranged on the base substrate;

a first insulating layer disposed on the thin film transistor, including a first via hole;

Color resistor, which is arranged on the first insulating layer;

a second insulating layer, which is disposed on the color resistor and includes a second via hole;

A pixel electrode arranged on the second insulating layer;

Wherein, the pixel electrode is electrically connected to the connection electrode layer provided between the first insulating layer and the second insulating layer through the second via hole, and the source electrode of the thin film transistor passes through the first insulating layer. The via hole is electrically connected to the first connection electrode layer.
The method of preparing a display substrate according to claim 18, wherein forming a plurality of pixel units on the base substrate includes:

Form a first color resistor on the surface of the first insulating layer away from the base substrate;

forming a first connection electrode layer;

A second color resistor is formed, and the second color resistor is spaced apart from the first color resistor.
The method for preparing a display substrate according to claim 19, wherein after forming the second color resistor, it further includes:

A fourth connection electrode portion is formed on a surface of the second color resistor away from the base substrate.