CN115268155A - Display substrate, preparation method thereof, display panel and display device - Google Patents
Display substrate, preparation method thereof, display panel and display device Download PDFInfo
- Publication number
- CN115268155A CN115268155A CN202210621901.7A CN202210621901A CN115268155A CN 115268155 A CN115268155 A CN 115268155A CN 202210621901 A CN202210621901 A CN 202210621901A CN 115268155 A CN115268155 A CN 115268155A
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- thin film
- insulating layer
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 168
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 239000010409 thin film Substances 0.000 claims abstract description 68
- 239000010410 layer Substances 0.000 claims description 183
- 239000000463 material Substances 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 239000004973 liquid crystal related substance Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 13
- 239000011159 matrix material Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 23
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 238000000231 atomic layer deposition Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 8
- 239000011358 absorbing material Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000001795 light effect Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 230000003190 augmentative effect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000002052 molecular layer Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136222—Colour filters incorporated in the active matrix substrate
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
Abstract
The application provides a display substrate, a preparation method of the display substrate, a display panel and a display device. Arranging a first thin film transistor on a substrate, and forming a first through hole corresponding to the first thin film transistor on a first insulating layer; arranging a first connecting electrode layer on a first color resistor corresponding to the first thin film transistor; arranging a second through hole corresponding to the first thin film transistor on the second insulating layer; the first pixel electrode can be enabled to pass through the second via hole and be electrically connected with the first connecting electrode layer, and the first connecting electrode layer is further electrically connected with the source electrode of the first thin film transistor through the second via hole, so that the first pixel electrode is electrically connected with the source electrode of the first thin film transistor without arranging a via hole in the first color resistor, and the aperture opening ratio or the light efficiency loss and the like caused by arranging the via hole in the first color resistor are avoided.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a display substrate, a manufacturing method thereof, a display panel, and a display device.
Background
With the development of Augmented Reality (AR) products and Virtual Reality (VR) products, the demand for the number of Pixels Per Inch, i.e., high pixel density (PPI), of a Liquid Crystal Display (LCD) device is increasing. If the LCD shows an increase in PPI, the pixel aperture ratio is further reduced. Therefore, how to improve the light efficiency and reduce the power consumption is one of the problems that need to be solved urgently at present.
Disclosure of Invention
In view of the above, an object of the present application is to provide a display substrate, a method for manufacturing the display substrate, a display panel and a display device.
In view of the above object, the present application provides a display substrate comprising:
a base substrate;
the pixel units are arranged on the substrate in an array manner;
wherein the pixel unit includes:
a thin film transistor disposed on the substrate base plate;
a first insulating layer disposed on the thin film transistor, including a first via hole;
a color resistor disposed on the first insulating layer;
the second insulating layer is arranged on the color resistor and comprises a second through hole;
a pixel electrode disposed on the second insulating layer;
wherein the pixel electrode and the source electrode of the thin film transistor are electrically connected to a connection electrode layer disposed between the first insulating layer and the second insulating layer through the second via hole and the first via hole, respectively.
The embodiment of the application also provides a display panel, which comprises a display substrate, an opposite side substrate and a liquid crystal molecular layer positioned between the display substrate and the opposite side substrate; the display substrate is the display substrate as described in any of the previous items.
An embodiment of the present application further provides a display device, including the display panel as described above.
The embodiment of the present application further provides a method for manufacturing a display substrate, including:
providing a substrate base plate;
forming a plurality of pixel units on the substrate base plate, wherein the pixel units are arranged on the substrate base plate in an array manner;
wherein the pixel unit includes:
a thin film transistor disposed on the substrate base plate;
a first insulating layer disposed on the thin film transistor, including a first via hole;
a color resistor disposed on the first insulating layer;
the second insulating layer is arranged on the color resistor and comprises a second through hole;
a pixel electrode disposed on the second insulating layer;
the pixel electrode and the source electrode of the thin film transistor are electrically connected to a connection electrode layer disposed between the first insulating layer and the second insulating layer through the second via hole and the first via hole, respectively.
As can be seen from the foregoing, the display substrate provided in the embodiments of the present application provided in the present application is formed by providing a substrate; the pixel units are arranged on the substrate in an array manner; wherein the pixel unit includes: a thin film transistor disposed on the substrate base plate; a first insulating layer disposed on the thin film transistor, including a first via hole; a color resistor disposed on the first insulating layer; the second insulating layer is arranged on the color resistor and comprises a second through hole; a pixel electrode disposed on the second insulating layer; the pixel electrode and the source electrode of the thin film transistor are electrically connected to a connection electrode layer disposed between the first insulating layer and the second insulating layer through the second via hole and the first via hole, respectively. Therefore, the pixel electrode can be electrically connected with the source electrode of the thin film transistor without arranging a via hole on the color resistor, and the aperture opening ratio or the light effect loss and the like caused by arranging the via hole on the color resistor are avoided.
Drawings
In order to more clearly illustrate the technical solutions in the present application or the related art, the drawings needed to be used in the description of the embodiments or the related art will be briefly introduced below, and it is obvious that the drawings in the following description are only embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic cross-sectional view illustrating an exemplary liquid crystal display substrate in the related art;
fig. 2 shows an exemplary plan structure diagram of a liquid crystal display substrate in the related art.
Fig. 3 (a) is a schematic cross-sectional structure diagram of an exemplary display substrate according to an embodiment of the present disclosure.
Fig. 3 (B) is a schematic cross-sectional structure diagram of a first pixel unit of an exemplary display substrate according to an embodiment of the present disclosure.
Fig. 4 is a simplified cross-sectional structure diagram of an exemplary display substrate according to an embodiment of the present disclosure.
Fig. 5 is a schematic view showing another structure of an exemplary display substrate according to an embodiment of the present application.
Fig. 6 shows another schematic structural diagram of an exemplary display substrate according to an embodiment of the present application.
Fig. 7 is a schematic view showing another structure of an exemplary display substrate according to an embodiment of the present application.
Fig. 8 is a schematic view of another exemplary display substrate according to an embodiment of the present application.
Fig. 9 shows a further schematic structural diagram of an exemplary display substrate according to an embodiment of the present application.
Fig. 10 is a schematic view showing another structure of an exemplary display substrate according to an embodiment of the present application.
Fig. 11 shows a schematic structural diagram of an exemplary display panel according to an embodiment of the present application.
Fig. 12 illustrates a method of manufacturing an exemplary display substrate according to an embodiment of the present application.
FIG. 13 (a) is a schematic illustration of an intermediate structure during fabrication of an exemplary display substrate according to an embodiment of the present application;
FIG. 13 (b) is a schematic diagram of yet another intermediate structure in the fabrication of an exemplary display substrate according to an embodiment of the present application;
FIG. 13 (c) is a schematic illustration of yet another intermediate structure in the fabrication of an exemplary display substrate according to an embodiment of the present application;
FIG. 13 (d) is a schematic diagram of yet another intermediate structure in the preparation of an exemplary display substrate according to an embodiment of the present application;
FIG. 13 (e) is a schematic illustration of yet another intermediate structure in the fabrication of an exemplary display substrate according to an embodiment of the present application;
FIG. 13 (f) is a schematic diagram of yet another intermediate structure in the preparation of an exemplary display substrate according to an embodiment of the present application;
FIG. 13 (g) is a schematic diagram of yet another intermediate structure in the preparation of an exemplary display substrate according to an embodiment of the present application;
FIG. 13 (h) is a schematic illustration of yet another intermediate structure in the fabrication of an exemplary display substrate according to embodiments of the present application;
FIG. 13 (i) is a schematic view of yet another intermediate structure in the fabrication of an exemplary display substrate according to an embodiment of the present application;
FIG. 13 (j) is a schematic diagram of yet another intermediate structure in the fabrication of an exemplary display substrate according to an embodiment of the present application;
FIG. 13 (k) is a schematic diagram of yet another intermediate structure in the fabrication of an exemplary display substrate according to an embodiment of the present application;
FIG. 13 (l) is a schematic view of another exemplary display substrate according to an embodiment of the present application;
fig. 13 (m) is a schematic view of another exemplary structure of the display substrate according to the embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described in detail below with reference to specific embodiments and the accompanying drawings.
It should be noted that technical terms or scientific terms used in the embodiments of the present application should have a general meaning as understood by those having ordinary skill in the art to which the present application belongs, unless otherwise defined. The use of "first," "second," and similar terms in the embodiments of the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item preceding the word comprises the element or item listed after the word and its equivalent, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used only to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
As a mainstream display device at present, a liquid crystal display device has advantages of low power consumption, small size, low radiation, and the like. The liquid crystal display panel is a non-self-luminous panel and needs to be matched with a backlight module for use. The liquid crystal display device adopts the developing principle that liquid crystal is arranged between a color filter substrate and a thin film transistor array substrate, and the liquid crystal molecules are distorted by applying driving voltage on the two substrates to control the transmission or shielding function of a backlight source so as to display an image.
The COA (Color Filter on Array) technique is a technique for preparing a Color Filter layer on an Array substrate, which can improve an aperture ratio and omit a post alignment process of the Color Filter substrate and a tft Array substrate.
The display substrate provided by the embodiment of the application is a liquid crystal display substrate, and the liquid crystal display substrate can be used in a passive display mode, and can be applied to high PPI display, such as the fields of light and thin near-eye display such as Virtual Reality (VR), augmented Reality (AR), mixed Reality (MR), and vehicle-mounted display for light field display.
Fig. 1 is a schematic cross-sectional view illustrating an exemplary liquid crystal display substrate in the related art.
As shown in fig. 1, the liquid crystal display substrate includes a plurality of thin film transistors 200, a plurality of color resistors 310, and a plurality of pixel electrodes 400. The color resistors 310 and the pixel electrodes 400 are respectively disposed in one-to-one correspondence with the thin film transistors 200. The pixel electrode 400 is electrically connected to the thin film transistor 200 (e.g., a source) through a via 311 penetrating through the color resistor. The via hole 311 is filled with a connection metal (e.g., a metal material for a pixel electrode).
Fig. 2 shows an exemplary plan structure diagram of a liquid crystal display substrate in the related art.
As shown in fig. 2, the color resistor 310 is provided with a via hole 311 penetrating through the color resistor 310. For the display substrate with high PPI, the PPI can reach 2000PPI to 3000PPI, the size of a single pixel is often small, at this time, a via hole is formed on the color resistor 310, and due to the characteristics of the organic material of the color resistor 310, the aperture of the via hole 311 is large, so that the light efficiency is reduced. Therefore, the improvement of the opening ratio and the transmittance by the COA process cannot be realized due to the increase of the occupied area ratio of the color-resistant via hole.
Based on this, this application embodiment provides side connection pixel electrode and thin film transistor through the color resistance, perhaps carries out the pore-filling at the trompil to the color resistance, can solve the problem that the light efficiency that the color resistance goes through the hole light efficiency reduction reduces to a certain extent.
Fig. 3 (a) and 3 (B), and fig. 4 respectively show schematic structural diagrams of an exemplary display substrate according to an embodiment of the present application. Fig. 3 (a) is a schematic cross-sectional structure diagram of an exemplary display substrate according to an embodiment of the present disclosure. Fig. 3 (B) is a schematic cross-sectional structure diagram of a pixel unit of an exemplary display substrate according to an embodiment of the present disclosure. Fig. 4 is a simplified cross-sectional structure diagram of an exemplary display substrate according to an embodiment of the present disclosure.
As shown in fig. 3 (a) and 4, the display substrate 10 provided in the embodiment of the present application may include:
a base substrate 100; the substrate 100 may have a plurality of pixel units (e.g., a first pixel unit 100a, a second pixel unit 100b, and a third pixel unit 100 c) disposed thereon. In some embodiments, the pixel units may be arranged in an array on the substrate base plate 100, and may further include the following structures. It should be understood that the first pixel unit 100a, the second pixel unit 100b and the third pixel unit 100c may be all sub-pixel units, such as a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit, respectively, to emit light of different colors to form a color pixel. The structure of the pixel unit will be described below by taking the first pixel unit 100a as an example.
Referring to fig. 3 (B), the first pixel unit 100a may include a first thin film transistor 200a disposed on the substrate. The first insulating layer 500a, disposed on the first thin film transistor 200a, includes a first via 510a. A first color resist 320a disposed on the first insulating layer 500 a. The second insulating layer 600a is disposed on the first color resist 320a and includes a second via 620a. And a first pixel electrode 410a disposed on the second insulating layer 600 a.
Wherein the first pixel electrode 410a and the source electrode of the first thin film transistor 200a are electrically connected to the first connection electrode layer 710a disposed on the first insulating layer 500a and the second insulating layer 600a through the second via hole 620a and the first via hole 510a, respectively. It can be understood that, as shown in fig. 4, the color resistors and the pixel electrodes in the display substrate provided in the embodiment of the present application are respectively disposed corresponding to the thin film transistors.
In the display substrate 10 provided in the embodiment of the present application, the first thin film transistor 200a is disposed on the substrate 100, and the first insulating layer 500a is provided with the first via 510a corresponding to the first thin film transistor 200 a; a first connection electrode layer 710a is disposed between the first insulating layer 500a and the second insulating layer 600a; providing a second via 620a in the second insulating layer 600a; the first pixel electrode 410a can be electrically connected with the first connecting electrode layer 710a through the second via hole 620a, and the first connecting electrode layer 710a is electrically connected with the source of the first thin film transistor 200a through the second via hole 620a, so that the first pixel electrode 410a is electrically connected with the source of the first thin film transistor 200a without arranging a via hole in the first color resistor 320a, and the aperture ratio or the light efficiency loss and the like caused by arranging a via hole in the first color resistor 320a are avoided.
In some embodiments, the substrate 100 may be a transparent substrate, for example, the substrate 100 is a glass substrate, and has a supporting and bearing function.
In some embodiments, the first thin film transistor 200a may be a vertical thin film transistor. For example, as shown in fig. 3 (B), the semiconductor device may specifically include a drain layer 210a, a drain insulating layer 220a, a source layer 230a, an oxide semiconductor layer 240a, a source insulating layer 250a, and a gate layer 260a, which are sequentially disposed in a direction away from the substrate 100. The source layer 230a may include a first source and a second source, the first source and the second source are symmetrically disposed on two sides of the thin film transistor, and the first source and the second source are disposed on the same layer. In this way, by providing the vertical thin film transistor, the aperture ratio of the display substrate can be increased to a certain extent, for example, by about 10%, compared to a conventional thin film transistor in which the source layer and the drain layer are provided in the same layer.
In some embodiments, the structures of the first thin film transistor of the first pixel unit 100a, the second thin film transistor of the second pixel unit 100B, and the third thin film transistor of the third pixel unit 100c may be the same, for example, all of the structures of the vertical thin film transistors shown in fig. 3 (B) may be the same. The first insulating layer and the second insulating layer in the first pixel unit 100a, the second pixel unit 100b, and the third pixel unit 100c may also have the same structure.
In some embodiments, the first insulating layer 500a may be a passivation layer, and the passivation layer may be an oxide, a nitride, an oxynitride, or the like. The passivation layer may be a single layer or a plurality of layers. The passivation layer may function to protect the thin film transistor. The first via 510a penetrates the first insulating layer 500a on the first insulating layer 500a, and is electrically connected to the source of the first thin film transistor 200a correspondingly. It should be understood that the vias are filled with a connecting metal.
In some embodiments, referring back to fig. 3 (B), the second insulating layer 600a may cover the first color resist 320a in the first pixel unit 100a, i.e., be disposed on a side of the first color resist 320a away from the substrate 100.
In some embodiments, the second via 620a of the second insulating layer 600a may be filled with a second insulating layer material. The orthographic projection of the second insulating layer material on the substrate 100 and the orthographic projection of the connecting metal on the substrate 100 are not overlapped. Thus, the gap in the via hole in the second insulating layer 600a can be filled, which is beneficial to reducing the light effect loss.
In some embodiments, the second via 620a of the second insulating layer may be further filled with a filter material having the same color as the first color resistance. Thus, the gap in the second via hole 620a in the second insulating layer 600a can be filled, which is beneficial to reducing light efficiency loss.
In some embodiments, the display substrate further includes a black matrix layer disposed between the adjacent pixel units, a via hole coaxial with the second via hole may be disposed in the black matrix layer, and a filter material filled with a color same as that of the color resists. Therefore, the gap in the through hole in the second insulating layer 600a can be filled at the periphery, and the reduction of the light effect loss is facilitated.
It is understood that the color of the first color resistor 320a may be any one of red, green or blue. The embodiment of the present application does not limit this.
In some embodiments, the first color resistor of the first pixel unit, the second color resistor of the second pixel unit, and the third color resistor of the third pixel unit may be disposed at intervals on the first insulating layer, or may be disposed with an overlap between adjacent color resistors (for example, fig. 6), as long as the subsequent processes can make the overlap portion flat.
Fig. 5 shows a further schematic structural diagram of an exemplary display substrate according to an embodiment of the present application.
In some embodiments, in the first pixel unit 100a, the first connection electrode layer 710a disposed on the surface of the first color resistor 320a may include a first connection electrode part 711a and a second connection electrode part 712a connected in sequence. The first connection electrode part 711a is disposed on the surface of the first color resistor 320a away from the substrate 100, and is electrically connected to the first pixel electrode 410a through the second via 620a; the second connection electrode portion 712a is disposed on a surface of the first insulating layer 500a away from the base substrate 100, and is electrically connected to the source of the first thin film transistor 200a through the first via 510a. Specifically, referring to fig. 5, the first connecting electrode part 711a may be disposed on a surface of the color resistor 320a away from the substrate base 100 (i.e., an upper surface of the first color resistor 320 a) and two side surfaces of the first color resistor 320a (i.e., two surfaces adjacent to the upper surface), respectively. In this way, the first connection electrode layer 710a may be electrically connected to the second via hole 620a through the first connection electrode part 711a and electrically connected to the pixel electrode 410a through the second via hole 620a. The second connection electrode part 712a may be disposed on a surface of the first insulating layer 500a away from the substrate 100, and a surface of the second connection electrode part 712a close to the first insulating layer 500a may be electrically connected to the first via 510a. In this way, the first connection electrode layer 710a may be electrically connected to the first via hole 510a through the second connection electrode portion 712a, and electrically connected to the source electrode of the first thin film transistor 200a through the first via hole 510a.
Thus, the first connection electrode layer 710a disposed on the side of the first color resistor 320a away from the substrate 100 and the side of the first color resistor 320a can electrically connect the source of the thin film transistor 200a from the side of the first color resistor 320a, and the first pixel electrode 410a can be electrically connected to the source of the first thin film transistor 200a without disposing a color resistor opening in the first color resistor 320a, thereby effectively improving the light efficiency.
In some embodiments, the connection manner between the corresponding pixel electrodes in the first pixel unit 100a, the second pixel unit 100b and the third pixel unit 100d and the source electrode of the corresponding thin film transistor may be the same, for example, the connection manner between the first pixel electrode 410a and the source electrode of the first thin film transistor 200a is the same. For example, as shown in FIG. 3 (A). In some embodiments, corresponding second and third connection electrode layers having the same structure as the first connection electrode layer 710a may be disposed on the color resistors in the second and third pixel units 100b and 100c, respectively, as shown in fig. 5, for example. Or may be different from the structure of the first connection electrode layer 710 a.
Fig. 6 shows another schematic structural diagram of an exemplary display substrate according to an embodiment of the present application.
In some embodiments, the second pixel unit 100b may further include a second connection electrode layer having a different structure from the first connection electrode layer 710 a. In some embodiments, the second connection electrode layer includes at least a third connection electrode portion 711b. The third connection electrode portion 711b is disposed on the surface of the color resist 320b near the substrate 100. For example, as shown in fig. 6, the third connection electrode portion 711b is disposed on the surface of the second color resist 320b close to the substrate 100. Thus, a color resist hole without providing the second color resist 320b is realized. Meanwhile, the second connection electrode layer of the structure may be disposed at an interval in the same layer as the first connection electrode layer 710a, so that the first connection electrode layer 710a may be simultaneously formed after one deposition and patterning, thereby simplifying the process. The third connection electrode layer of the third pixel unit 100c may have the same structure as the second connection electrode layer of the pixel unit 100 b.
In some embodiments, in the third pixel unit 100c, the third color resistor 320c may be disposed to overlap with the second color resistor 320b in the second pixel unit 100 b. Specifically, an orthogonal projection of the third color resistor 320c on the substrate may partially overlap an orthogonal projection of the second color resistor 320b on the substrate. To prevent light leakage at the edges of the second and third color resists 320b and 320 c. The second via 620b in the second pixel cell 100b is disposed at an end of the second connection electrode layer away from the third connection electrode layer in the third pixel cell 100 c; the second via 620c of the third pixel cell 100c is disposed at an end of the third connection electrode layer remote from the second connection electrode layer.
Fig. 7 is a schematic view showing another structure of an exemplary display substrate according to an embodiment of the present application.
In some embodiments, the second connection electrode layer further includes a fourth connection electrode portion 712b connected to the third connection electrode portion 711 b; the fourth connection electrode portion 712b is disposed on the surface of the color resist 320b away from the substrate 100; the third connection electrode portion 711b is electrically connected to the second via 620b through the fourth connection electrode portion 712 b. Referring to fig. 7, the second via hole 620b may be electrically connected through the fourth connection electrode part 712b near the middle of the surface of the second insulating layer 600. In the third pixel unit 100c, the third connection electrode layer and the second connection electrode layer may have the same structure.
Referring to fig. 6, the second color resistor 320b is disposed adjacent to the third color resistor 320c and the first color resistor 320a, respectively. It should be understood that the first color resistor 320a, the second color resistor 320b and the third color resistor 320c are different in color, and may be, for example, red, blue and green respectively, or green, blue and red respectively, or green, red and blue respectively, or blue, red and green respectively, etc. Thus, the three can form a colorful pixel unit.
Fig. 8 is a schematic view of another exemplary display substrate according to an embodiment of the present application.
In some embodiments, a fourth pixel unit may be further included, in which the connection manner between the pixel electrode 410d and the source electrode of the thin film transistor 200d is different from the connection manner between the pixel electrode 410a and the source electrode of the thin film transistor 200 a.
For example, as shown in fig. 8, a fourth color resist 320d having a different structure from the first color resist 320a may be further included. A color resistor through hole 321 may be formed on the fourth color resistor 320d. And a light absorbing material 322 may be disposed in the color-blocking via hole 321 to shield the fourth aperture, so as to reduce the aperture of the via hole.
In some embodiments, the light absorbing material 322 may be filled in the fourth color blocking hole 321. For example, the light absorbing material 322 can be a color resist material having the same color as the fourth color resist 320d, as shown in FIG. 8. Or the light absorbing material 322 may be a black light blocking material (e.g., BM material) as shown in fig. 9.
In other embodiments, the light absorbing material 322 may be disposed at the periphery of the via hole of the fourth color filter 320d, for example, as shown in fig. 10. The light absorbing material 322 may be a black light blocking material (e.g., BM material) at this time.
In some embodiments, a third insulating layer may be further disposed on a side of the plurality of pixel electrodes away from the base substrate 100, and a common electrode may be further disposed on the third insulating layer.
Based on the same inventive concept, the present application also provides a display panel corresponding to the display substrate 10 of any of the above embodiments. Fig. 11 shows a schematic structural diagram of an exemplary display panel according to an embodiment of the present application.
As shown in fig. 11, the display panel of the embodiment of the present application may include a display substrate 10, a counter substrate 30, and a liquid crystal molecular layer 20 between the display substrate 10 and the counter substrate 30; the display substrate 10 is the display substrate 10 in the foregoing display substrate embodiment.
The display panel of the above embodiment has the display substrate 10 corresponding to any one of the embodiments, and has the beneficial effects of the corresponding display substrate embodiment, which are not described herein again.
Based on the same inventive concept, the present application also provides a display device corresponding to the display substrate 10 of any of the above embodiments. The display device comprises the display panel in the display substrate embodiment.
Specifically, the display device may be a mobile phone, a television, a personal digital assistant, a digital camera, a notebook computer, a desktop computer, or the like. The present embodiment is not limited thereto.
The display device of the above embodiment has the display substrate corresponding to any one of the embodiments, and has the beneficial effects of the corresponding display substrate embodiment, which are not described herein again.
Based on the same inventive concept, the present application also provides a method for manufacturing the display substrate 10, corresponding to any of the embodiments of the display substrate 10 described above. Fig. 12 illustrates a method of manufacturing an exemplary display substrate 10 according to an embodiment of the present application.
Referring to fig. 12, in step S1010, the base substrate 100 may be first acquired.
In some embodiments, if the display substrate is a normal display device, the substrate 100 may be a glass material or other rigid material, and if the display substrate is a flexible display device, the substrate 100 may be a Polyimide (PI) material or other flexible material.
In step S1020, a plurality of pixel units arranged in an array may be formed on the substrate 100. The first pixel unit (e.g., the first pixel unit 100 a) is taken as an example for explanation.
In some embodiments, the substrate 100 may be cleaned first using standard methods. Then, a drain layer (for example, the drain layer 210 a) is formed on the base substrate 100 by sputtering, chemical Vapor Deposition (CVD), or the like on the base substrate 100, patterning is performed, and a signal line (for example, a Date line) is led out, thereby forming a structure shown in fig. 13 (a).
In some embodiments, the drain insulating layer (e.g., the drain insulating layer 220 a) and the source layer (e.g., the source layer 230 a) may be sequentially deposited on the drain layer (e.g., the drain layer 210 a) by Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), or the like, and then patterned, and signal lines (e.g., date lines) are led out, thereby forming the structure shown in fig. 13 (b). The material of the drain insulating layer 220 may be silicon oxide, aluminum oxide, or the like. The thickness may be 1000 to 10000A.
In some embodiments, a source layer (for example, the source layer 230 a) and a drain insulating layer (for example, the drain insulating layer 220 a) may be sequentially etched through a patterning process, etc., to form a channel, and form a first source and a second source symmetrically disposed on two sides of the thin film transistor, and the first source and the second source are disposed on the same layer, that is, the structure shown in fig. 13 (c) is obtained.
In some embodiments, an oxide semiconductor layer source layer (e.g., the oxide semiconductor layer 240 a) may be deposited on the source layer (e.g., the source layer 230 a) by Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), or the like, and then patterned, resulting in the structure shown in fig. 13 (d). Here, the material of the oxide semiconductor layer 240 may be IGZO, ITZO, IAZO, or the like.
In some embodiments, a source insulating layer (e.g., the source insulating layer 250 a) and a gate layer (e.g., the gate layer 260 a) may be sequentially deposited on a source layer (e.g., the oxide semiconductor layer 240 a) of the oxide semiconductor layer by Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), or the like, and then patterned, thereby obtaining the structure shown in fig. 13 (e). Thus, a thin film transistor was prepared and formed. The material of the source insulating layer 250a may be SiOx, or another insulating material compatible with oxide semiconductor may be used. The thickness of the SiOx layer may be 200 to 3000A.
In some embodiments, a first insulating layer (e.g., first insulating layer 500 a) is formed on the thin film transistor; the first insulating layer 500a is opened with a first via 510a corresponding to the first thin film transistor 200 a. For example, the first insulating layer 500a may be deposited on the gate layer 260a by Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), or the like, resulting in the structure shown in fig. 13 (f). The first insulating layer 500A may be a SiOx or SiOx/SiNx composite film with a thickness of about 1000 to 10000A.
In some embodiments, a plurality of color resistors are formed on the first insulating layer 500a, including a first color resistor 320a corresponding to the first thin film transistor 200 a; a connecting electrode layer is formed on the first color resistor 320a; the connection electrode layer extends from the first color resistor 320a layer to the first via 510a and is connected to the source of the thin film transistor.
In some embodiments, a first color resist 320a is formed on the surface of the first insulating layer 500a away from the base substrate 100, and the first color resist 320a may be coated on the first insulating layer 500a, so as to obtain the structure shown in fig. 13 (g). The first color resist 320a may be one of RGB CF, may have a thickness of 1.2-3 um, and may be patterned as needed.
In some embodiments, the first connection electrode layer is formed on the surface of the first color resistor 320a away from the substrate base plate 100. Specifically, ITO or other transparent electrodes 300 to 1000A may be deposited on the first color resist 320A to form a first connection electrode layer and a third connection electrode portion of the second connection electrode layer. And patterning according to the requirement, and leading all electrodes connected with the electrode layer to the color resistance surface respectively.
In some embodiments, a second color resist is formed on the surface of the first electrical connection layer away from the substrate base plate 100, and the second color resist is disposed adjacent to or spaced apart from the first color resist 320 a. Specifically, the other 2 RGB CFs may be coated to a thickness of 1.2 to 3um, and patterned as necessary to obtain the structure shown in fig. 13 (h).
In some embodiments, forming a fourth connection electrode portion on the surface of the second color resist away from the substrate 100 may be further included, resulting in the structure shown in fig. 13 (i). Specifically, ITO or other transparent electrodes 300 to 1000A may be deposited and patterned as needed, and the fourth connection electrode portion 712b or the fourth connection electrode portion 712c may be respectively led to the upper surfaces of the corresponding color resists.
In some embodiments, further comprising forming a second insulating layer 600a on the first color resist, the second color resist and the third color resist; the second insulating layer 600a is provided with a second via hole corresponding to the thin film transistor 200a, so as to obtain the structure shown in fig. 13 (j) or fig. 13 (k). Specifically, a PLN layer with a thickness of 2-4 um may be coated, the CF planarized, and patterned as desired.
In some embodiments, a plurality of pixel electrodes are formed on the second insulating layer 600a, and are respectively disposed in one-to-one correspondence with the plurality of color resistors; the pixel electrode includes a first pixel electrode 410a disposed corresponding to the first thin film transistor 200a, so as to obtain the display substrate shown in fig. 6 or fig. 7. Specifically, 300-1000A of pixel electrode ITO can be deposited and patterned as required.
In some embodiments, the method may further include coating a PLN layer with a thickness of 2 to 4um on the pixel electrode, planarizing the PLN hole, and patterning as needed. And a common electrode is deposited. The display substrate shown in fig. 13 (l) or 13 (m) is finally obtained.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the context of the present application, features from the above embodiments or from different embodiments may also be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of brevity.
In addition, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown in the provided figures for simplicity of illustration and discussion, and so as not to obscure the embodiments of the application. Furthermore, devices may be shown in block diagram form in order to avoid obscuring embodiments of the application, and this also takes into account the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the embodiments of the application are to be implemented (i.e., specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the application, it should be apparent to one skilled in the art that the embodiments of the application can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative instead of restrictive.
While the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures, such as Dynamic RAM (DRAM), may use the discussed embodiments.
The present embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalents, improvements, and the like that may be made without departing from the spirit or scope of the embodiments of the present application are intended to be included within the scope of the claims.
Claims (14)
1. A display substrate, comprising:
a substrate base plate; and
the pixel units are arranged on the substrate base plate in an array mode;
wherein the pixel unit includes:
a thin film transistor disposed on the substrate base plate;
a first insulating layer disposed on the thin film transistor, including a first via hole;
a color resistor disposed on the first insulating layer;
the second insulating layer is arranged on the color resistor and comprises a second through hole;
a pixel electrode disposed on the second insulating layer;
wherein the pixel electrode and the source electrode of the thin film transistor are electrically connected to a connection electrode layer disposed between the first insulating layer and the second insulating layer through the second via hole and the first via hole, respectively.
2. The display substrate according to claim 1, wherein the plurality of pixel units include a first pixel unit including a first thin film transistor, a first color resistor, a first pixel electrode, and a first connection electrode layer; the first connecting electrode layer comprises a first connecting electrode part and a second connecting electrode part which are connected in sequence;
the first connecting electrode part is arranged on the surface of the first color resistor, which is far away from the substrate base plate, and is electrically connected with the first pixel electrode through the second through hole; the second connection electrode part is arranged on the surface, far away from the substrate base plate, of the first insulating layer and is electrically connected with the source electrode of the first thin film transistor through the first through hole.
3. The display substrate according to claim 2, wherein the plurality of pixel units further comprises a second pixel unit, the second pixel unit comprises a second thin film transistor, a second color resistor, a second pixel electrode and a second connection electrode layer, and the second connection electrode layer at least comprises a third connection electrode portion arranged on the surface of the second color resistor close to the substrate.
4. The display substrate according to claim 3, wherein the second connection electrode layer further comprises a fourth connection electrode portion connected to the third connection electrode portion; the fourth connection electrode portion is disposed on a surface of the second color resist remote from the base substrate.
5. The display substrate according to claim 3, further comprising a third pixel unit, wherein the third pixel unit comprises a third thin film transistor, a third color resistor, a third pixel electrode, and a third connection electrode layer; the orthographic projection of the second color resistor on the substrate is partially overlapped with the orthographic projection of the third color resistor on the substrate.
6. The display substrate according to claim 5, wherein the second via hole of the second pixel unit is disposed at an end portion of the second connection electrode layer away from the third connection electrode layer; the second via hole of the third pixel unit is arranged at the end part of the third connection electrode layer far away from the second connection electrode layer.
7. The display substrate of claim 1, wherein the second via hole is filled with a filter material having a color same as that of the color resist.
8. The display substrate according to claim 1, further comprising a black matrix layer disposed between the adjacent pixel units, wherein the black matrix layer is filled with a filter material having a color same as that of the color resists.
9. The display substrate according to claim 1, wherein the thin film transistor comprises a drain layer, a source layer and a gate layer arranged in this order in a direction away from the substrate base plate; the source layer comprises a first source electrode and a second source electrode, the first source electrode and the second source electrode are symmetrically arranged on two sides of the thin film transistor, and the first source electrode and the second source electrode are arranged on the same layer.
10. A display panel is characterized by comprising a display substrate, a counter substrate and a liquid crystal layer positioned between the display substrate and the counter substrate; the display substrate is according to any one of claims 1 to 9.
11. A display device characterized by comprising the display panel according to claim 9.
12. A method for manufacturing a display substrate, comprising:
providing a substrate base plate;
forming a plurality of pixel units on the substrate base plate, and arranging the pixel units on the substrate base plate in an array manner;
wherein the pixel unit includes:
a thin film transistor disposed on the substrate base plate;
a first insulating layer disposed on the thin film transistor, including a first via hole;
a color resistor disposed on the first insulating layer;
the second insulating layer is arranged on the color resistor and comprises a second through hole;
a pixel electrode disposed on the second insulating layer;
the pixel electrode and the source electrode of the thin film transistor are electrically connected to a connection electrode layer disposed between the first insulating layer and the second insulating layer through the second via hole and the first via hole, respectively.
13. The method of manufacturing a display substrate according to claim 12, wherein the forming a plurality of pixel units on the substrate comprises:
forming a first color resistor on the surface of the first insulating layer far away from the substrate base plate;
forming a first connection electrode layer;
and forming a second color resistor, wherein the second color resistor and the first color resistor are arranged at intervals.
14. The method for manufacturing a display substrate according to claim 13, further comprising, after forming the second color resist:
and forming a fourth connection electrode part on the surface of the second color resistor, which is far away from the substrate base plate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210621901.7A CN115268155B (en) | 2022-06-01 | 2022-06-01 | Display substrate, preparation method thereof, display panel and display device |
| PCT/CN2023/097438 WO2023232077A1 (en) | 2022-06-01 | 2023-05-31 | Display substrate and preparation method therefor, display panel, and display apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210621901.7A CN115268155B (en) | 2022-06-01 | 2022-06-01 | Display substrate, preparation method thereof, display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115268155A true CN115268155A (en) | 2022-11-01 |
| CN115268155B CN115268155B (en) | 2023-10-27 |
Family
ID=83759570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210621901.7A Active CN115268155B (en) | 2022-06-01 | 2022-06-01 | Display substrate, preparation method thereof, display panel and display device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN115268155B (en) |
| WO (1) | WO2023232077A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023232077A1 (en) * | 2022-06-01 | 2023-12-07 | 京东方科技集团股份有限公司 | Display substrate and preparation method therefor, display panel, and display apparatus |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140081662A (en) * | 2012-12-21 | 2014-07-01 | 엘지디스플레이 주식회사 | Organic electro luminescent device and method of fabricating the same |
| US20150227013A1 (en) * | 2014-02-12 | 2015-08-13 | Boe Technology Group Co., Ltd. | Display substrate and method of manufacturing the same, and display device |
| CN109634014A (en) * | 2019-02-22 | 2019-04-16 | 鄂尔多斯市源盛光电有限责任公司 | A kind of display base plate and preparation method thereof, display panel, display device |
| WO2021184426A1 (en) * | 2020-03-16 | 2021-09-23 | Tcl华星光电技术有限公司 | Array substrate and liquid crystal display panel |
| CN114280868A (en) * | 2022-01-04 | 2022-04-05 | 京东方科技集团股份有限公司 | Display substrate, display panel and display device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103700669A (en) * | 2013-12-19 | 2014-04-02 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof as well as display device |
| CN105527767B (en) * | 2016-01-25 | 2019-05-03 | 武汉华星光电技术有限公司 | A kind of array substrate and liquid crystal display |
| CN106483726B (en) * | 2016-12-21 | 2023-07-25 | 昆山龙腾光电股份有限公司 | Thin film transistor array substrate, manufacturing method and liquid crystal display panel |
| KR20210119598A (en) * | 2020-03-24 | 2021-10-06 | 삼성디스플레이 주식회사 | Display device |
| CN115268155B (en) * | 2022-06-01 | 2023-10-27 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof, display panel and display device |
-
2022
- 2022-06-01 CN CN202210621901.7A patent/CN115268155B/en active Active
-
2023
- 2023-05-31 WO PCT/CN2023/097438 patent/WO2023232077A1/en unknown
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140081662A (en) * | 2012-12-21 | 2014-07-01 | 엘지디스플레이 주식회사 | Organic electro luminescent device and method of fabricating the same |
| US20150227013A1 (en) * | 2014-02-12 | 2015-08-13 | Boe Technology Group Co., Ltd. | Display substrate and method of manufacturing the same, and display device |
| CN109634014A (en) * | 2019-02-22 | 2019-04-16 | 鄂尔多斯市源盛光电有限责任公司 | A kind of display base plate and preparation method thereof, display panel, display device |
| WO2021184426A1 (en) * | 2020-03-16 | 2021-09-23 | Tcl华星光电技术有限公司 | Array substrate and liquid crystal display panel |
| CN114280868A (en) * | 2022-01-04 | 2022-04-05 | 京东方科技集团股份有限公司 | Display substrate, display panel and display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023232077A1 (en) * | 2022-06-01 | 2023-12-07 | 京东方科技集团股份有限公司 | Display substrate and preparation method therefor, display panel, and display apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2023232077A1 (en) | 2023-12-07 |
| CN115268155B (en) | 2023-10-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100858005B1 (en) | Liquid crystal display device and manufacturing method thereof | |
| US8803153B2 (en) | Fringe field switching liquid crystal display device and method of fabricating the same | |
| KR100864798B1 (en) | Semiconductor device | |
| US8610861B2 (en) | Liquid crystal display device and method of manufacturing the same | |
| US9874795B2 (en) | Array substrate, manufacturing method, and display device thereof | |
| US20040095521A1 (en) | Four color liquid crystal display and panel therefor | |
| CN101868755A (en) | Liquid crystal panel, liquid crystal display unit, liquid crystal display device, and television receiver | |
| CN115268155B (en) | Display substrate, preparation method thereof, display panel and display device | |
| EP3690927B1 (en) | Manufacturing method of tft array substrate and structure of tft array substrate | |
| KR100252650B1 (en) | Liquid crystal display device | |
| JP2002055360A (en) | Liquid crystal display device and method of manufacture thereof | |
| US10718982B2 (en) | Liquid crystal display devices | |
| US20040046918A1 (en) | In-plane switching mode liquid crystal display device and fabrication method thereof | |
| KR101366537B1 (en) | Array substrate in liquid crystal display device and Method for fabricating the same | |
| US10345664B2 (en) | Liquid crystal display panel, array substrate and methods for manufacturing the same | |
| KR101067947B1 (en) | Vertical alignment mode liquid crystal display device and method of fabricating thereof | |
| KR100729775B1 (en) | Liquid crystal display | |
| US20120236225A1 (en) | Display device substrate, manufacturing method of display device substrate, display device, and manufacturing method of display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |