WO2023231462A1 - 微型发光二极管芯片、其制作方法、显示面板及电子设备 - Google Patents

微型发光二极管芯片、其制作方法、显示面板及电子设备 Download PDF

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Publication number
WO2023231462A1
WO2023231462A1 PCT/CN2023/077492 CN2023077492W WO2023231462A1 WO 2023231462 A1 WO2023231462 A1 WO 2023231462A1 CN 2023077492 W CN2023077492 W CN 2023077492W WO 2023231462 A1 WO2023231462 A1 WO 2023231462A1
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Prior art keywords
semiconductor layer
layer
light
emitting
electrode
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PCT/CN2023/077492
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English (en)
French (fr)
Inventor
陈明辉
周泉斌
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华为技术有限公司
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Publication of WO2023231462A1 publication Critical patent/WO2023231462A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements

Definitions

  • the present application relates to the field of display technology, and in particular to a micro light-emitting diode chip, a manufacturing method thereof, a display panel and electronic equipment.
  • Micro LED micro light-emitting diode chips
  • Micro LED display panels have the characteristics of fast response, autonomous emission, high brightness, low power consumption, ultra-high resolution and color saturation. It has the advantages of high strength, flexible display and long life.
  • micro-LED chips can also be used as pixelated array light sources for applications in photosensitivity, projection, optical communications and other fields.
  • micro-LED chips are required to have a smaller luminous angle and higher normal brightness.
  • the luminous angle of the micro-LED chip is expected to be Less than 120° or even up to about 60°, in this way, the crosstalk between adjacent micro-light-emitting diode chips can be smaller to ensure sufficient light energy utilization.
  • the side area of the micro light-emitting diode chip accounts for a large proportion, and the light emission ratio from the side is large, and the light is inside the micro light-emitting diode chip. Emitted, part of the light is prone to total reflection on the light-emitting surface.
  • the luminous angle of the micro light-emitting diode chip is relatively large, and the actual luminous angle is generally in the range of 140° to 160°.
  • the normal brightness of the micro light-emitting diode chip is low, so that the light energy of the micro light-emitting diode chip is low. Utilization is low.
  • Embodiments of the present application provide a micro light-emitting diode chip, a manufacturing method thereof, a display panel, and electronic equipment to solve the problem of low light energy utilization of micro light-emitting diode chips in related technologies.
  • micro light-emitting diode chip may include: a first semiconductor layer, a second semiconductor layer, a light-emitting layer located between the first semiconductor layer and the second semiconductor layer, one electrode, and a second electrode.
  • the first electrode is located on the side of the first semiconductor layer away from the light-emitting layer
  • the second electrode is located on the side of the second semiconductor layer close to the light-emitting layer
  • the first electrode is electrically connected to the first semiconductor layer
  • the second electrode is electrically connected to the second semiconductor layer. connect.
  • the light-emitting layer is located between the first semiconductor layer and the second semiconductor layer.
  • the first semiconductor layer and the second semiconductor layer may include different types of semiconductor materials, so that the first semiconductor layer and the second semiconductor layer may Different types of carriers are provided respectively, for example, the first semiconductor layer can provide electrons and the second semiconductor layer can provide holes, or the first semiconductor layer can provide holes and the second semiconductor layer can provide electrons.
  • the first electrode and the One semiconductor layer is electrically connected, and the second electrode is electrically connected to the second semiconductor layer. When a voltage is applied to the first electrode and the second electrode, electrons and holes can be driven to move, so that the electrons and holes recombine and emit light in the light-emitting layer.
  • the light-emitting layer may be a multi-quantum well, thereby improving the luminous efficiency of the light-emitting layer.
  • the first electrode is located on the side of the first semiconductor layer away from the light-emitting layer
  • the second electrode is located on the side of the second semiconductor layer close to the light-emitting layer. That is, the first electrode and the second electrode are located on the micro light-emitting diode chip.
  • the micro light-emitting diode chip in the embodiment of the present application is applied to a display panel or electronic device to facilitate binding the micro light-emitting diode chip to the substrate.
  • the second semiconductor layer has a first surface and a second surface arranged oppositely.
  • the first surface is a surface of the second semiconductor layer close to the light-emitting layer
  • the second surface is a surface of the second semiconductor layer away from the light-emitting layer.
  • the orthographic projection of the second surface on the plane of the first surface is within the range of the first surface. That is to say, the area of the second surface of the second semiconductor layer is smaller than the area of the first surface, and the orthographic projection of the second surface on the plane of the first surface does not exceed the range of the first surface.
  • the second semiconductor layer can have inclined side surfaces, so that the second semiconductor layer is equivalent to a microlens, and the microlens can condense the light emitted from the light-emitting layer.
  • the second semiconductor layer can be equivalent to Microlens, which can use the structure of the micro-LED chip itself to form a micro-lens.
  • the micro-lens can converge the light emitted from the luminescent layer, thereby reducing the luminous angle of the micro-LED chip and increasing the normal brightness of the micro-LED chip. .
  • the size of the micro light-emitting diode chip remains basically unchanged, which does not affect the active area area of the micro light-emitting diode chip, and therefore does not affect the luminous efficiency of the micro light-emitting diode chip. Therefore, the light energy utilization efficiency of the micro light-emitting diode chip can be improved.
  • the structure of the micro light-emitting diode chip itself is used to form the microlens, without adding other additional components.
  • the second semiconductor layer patterning process parameters can be adjusted to obtain the second semiconductor layer.
  • the structure of the semiconductor layer and the manufacturing process are relatively simple and will not increase the manufacturing cost.
  • the cross-sectional area of the second semiconductor layer in the direction parallel to the second surface shows a gradually decreasing trend, that is, In the direction in which the first semiconductor layer points to the second semiconductor layer, the second semiconductor layer is tapered.
  • the shape of the cross section of the second semiconductor layer in a direction perpendicular to the second surface may be a trapezoid.
  • the angle between the side surface of the second semiconductor layer and the first surface can be set in the range of 30° to 85°, preferably in the range of 40° to 60°, so that the second semiconductor layer can be The second semiconductor layer has a better light converging effect, making the normal brightness of the miniature light-emitting diode chip higher.
  • the side surfaces of the second semiconductor layer may also have other shapes, as long as the orthographic projection of the second surface of the second semiconductor layer on the plane of the first surface is within the range of the first surface.
  • the side of the second semiconductor layer may have a certain curvature.
  • the cross-sectional area of the second semiconductor layer in the direction parallel to the second surface may be in the shape of A tendency that gradually increases first and then decreases (or decreases first and then increases).
  • the micro light-emitting diode chip in the embodiment of the present application may further include: a first reflective layer covering at least part of the side surfaces of the second semiconductor layer.
  • the first reflective layer can reflect the light emitted toward the side of the micro LED chip, thereby reducing the light emitted from the side, and the first reflective layer can reflect the light back to the inside of the micro LED chip, allowing this part of the light to pass through multiple times After reflection, it can be emitted in the normal direction, which can effectively constrain the luminous angle of the micro light-emitting diode chip (for example, the luminous angle of the micro light-emitting diode chip can be made less than 120°), and further improve the normal brightness.
  • the second semiconductor layer by arranging the second semiconductor layer so that the orthographic projection of the second surface on the plane of the first surface is located within the range of the first surface, the second semiconductor layer has an inclined side surface, which provides the basis for subsequent processing of the second surface.
  • side of semiconductor layer It provides the necessary conditions to form the first reflective layer on the surface.
  • the material of the first reflective layer can be effectively attached to the side of the second semiconductor layer, so that the thickness uniformity of the manufactured first reflective layer is better.
  • the first reflective layer may include a thin film material with high reflectivity.
  • the first reflective layer may be a distributed Bragg reflection layer (DBR).
  • the distributed Bragg reflection layer is a non-conductive material.
  • the reflective layer can keep the first reflective layer and the second semiconductor layer insulated.
  • the first reflective layer may also be a stacked structure of an insulating layer-metal layer-insulating layer.
  • the insulating layer may include a transparent material such as silicon dioxide.
  • the first reflective layer can also adopt other structures or materials, which are not limited here. In the actual process, evaporation or thin film growth process can be used to make the first reflective layer.
  • the first semiconductor layer has a third surface and a fourth surface arranged oppositely.
  • the third surface is a surface of the first semiconductor layer away from the light-emitting layer
  • the fourth surface is a surface of the first semiconductor layer close to the light-emitting layer.
  • the orthographic projection of the fourth surface on the plane of the third surface is located within the range of the third surface. That is to say, the area of the fourth surface of the first semiconductor layer is smaller than the area of the third surface, and the orthographic projection of the fourth surface on the plane where the third surface is located does not exceed the range of the third surface.
  • the first semiconductor layer can also have inclined side surfaces, so that the first semiconductor layer is equivalent to a microlens, and the microlens can condense light.
  • the cross-sectional area of the first semiconductor layer in the direction parallel to the fourth surface gradually decreases. That is to say, in the direction of the first semiconductor layer
  • the first semiconductor layer is pointed in the direction of the second semiconductor layer, and the first semiconductor layer is tapered.
  • the shape of the cross section of the first semiconductor layer in the direction perpendicular to the fourth surface can be a trapezoid, so that the first semiconductor layer can have a better convergence effect.
  • the angle between the side surface of the first semiconductor layer and the third surface can be set in the range of 30° to 85°, preferably in the range of 40° to 60°, so that the third surface can be A semiconductor layer has a better light concentration effect.
  • the side surfaces of the first semiconductor layer can also have other shapes, as long as the orthographic projection of the fourth surface on the plane of the third surface is within the range of the third surface.
  • the side of the first semiconductor layer may have a certain curvature.
  • the cross-sectional area of the first semiconductor layer in the direction parallel to the fourth surface may be A tendency that gradually increases first and then decreases (or decreases first and then increases).
  • the light-emitting layer can also be configured to have an inclined side, that is, the orthogonal projection of the surface of the side of the light-emitting layer close to the second semiconductor layer on the fourth surface, which can be located on the side of the light-emitting layer close to the first semiconductor layer. Orthographic projection of the surface onto the fourth surface.
  • the entire epitaxial layer (the epitaxial layer includes the first semiconductor layer, the second semiconductor layer and the light-emitting layer) has inclined side surfaces.
  • the second semiconductor layer, the light-emitting layer and the first semiconductor layer can be patterned together. Compared with patterning separately, the number of patterning times can be reduced and the cost of the manufacturing process can be reduced.
  • the mask of the patterning process can be reduced.
  • the opening area (or light-shielding area) of the mask corresponds to the area of the entire epitaxial layer.
  • the larger area of the opening area (or light-shielding area) can reduce the accuracy requirements of the mask and reduce the process difficulty.
  • the total thickness of the first semiconductor layer, the light-emitting layer and the second semiconductor layer can be set to less than 8 ⁇ m.
  • the first reflective layer may cover the side surfaces of the first semiconductor layer, the light-emitting layer and the second semiconductor layer.
  • the first reflective layer can cover most or even the entire side of the epitaxial layer.
  • the first reflective layer covers a larger area. Therefore, the first reflective layer can reflect more light, preventing the light from emitting from the side, and the light After multiple reflections by the first reflective layer, the light can be emitted in the normal direction, further reducing the luminous angle of the micro-LED chip and further increasing the normal brightness.
  • the first semiconductor layer, the light-emitting layer and the second semiconductor layer all have inclined side surfaces, which provides necessary conditions for the subsequent formation of the first reflective layer on the side surfaces of the epitaxial layer. During the manufacturing process, the material of the first reflective layer can be effectively adhered to the side of the epitaxial layer, so that the thickness uniformity of the manufactured first reflective layer is better.
  • the above-mentioned micro light-emitting diode chip may also include: a passivation layer, a passivation layer On the side of the first semiconductor layer away from the light-emitting layer, the passivation layer can protect the first semiconductor layer.
  • the above-mentioned micro light-emitting diode chip may further include: a second reflective layer located on the side of the first semiconductor layer away from the light-emitting layer.
  • the second reflective layer can reflect the light emitted from the light-emitting layer towards the first semiconductor layer. Most of the light reflected by the second reflective layer can be emitted from the normal direction after being converged by the first semiconductor layer and the second semiconductor layer.
  • the reflected light that deviates from the normal direction at a larger angle can be reflected back to the interior of the epitaxial layer by the first reflective layer, and can also be emitted from the normal direction after multiple reflections and convergence. Therefore, in the embodiment of the present application, the normal brightness can be further increased by providing a second reflective layer, and the second reflective layer can also protect the first semiconductor layer.
  • the second reflective layer may include a thin film material with high reflectivity.
  • the second reflective layer may be a distributed Bragg reflection layer (DBR).
  • the distributed Bragg reflection layer is a non-conductive material.
  • the reflective layer can keep the second reflective layer insulated from the first semiconductor layer.
  • the second reflective layer may also be a stacked structure of an insulating layer-metal layer-insulating layer.
  • the insulating layer may include transparent materials such as silicon dioxide.
  • the second reflective layer can also adopt other structures or materials, which are not limited here.
  • the cross-sectional areas of the light-emitting layer and the first semiconductor layer in the direction parallel to the second surface are consistent.
  • the consistency of each cross-sectional area means that the cross-sectional areas are basically consistent within a certain error range.
  • the thickness of the second semiconductor layer can be set to less than 5 ⁇ m.
  • the edges of the first semiconductor layer and the light-emitting layer are approximately vertical, which can make the area of the side of the light-emitting layer smaller, thereby reducing leakage on the side of the light-emitting layer.
  • two patterning processes can be used to pattern the epitaxial layer.
  • the first semiconductor layer and the light-emitting layer can be patterned first, and then the micro-LED chip is turned over, and then the third layer can be patterned.
  • the second semiconductor layer is patterned, so that the etching depth of each patterning process can be smaller and the difficulty of the patterning process can be reduced.
  • the first reflective layer may cover only the side surfaces of the second semiconductor layer. The first reflective layer can reflect the light emitted toward the side of the micro LED chip, thereby reducing the light emitted from the side, and the first reflective layer can reflect the light back to the inside of the micro LED chip, allowing this part of the light to pass through multiple times After reflection, it can be emitted in the normal direction, which can effectively constrain the luminous angle of the micro-LED chip and further enhance the normal brightness.
  • the micro light-emitting diode chip in the embodiment of the present application may also include: a passivation layer, the passivation layer is located on the side of the first semiconductor layer away from the light-emitting layer, and the passivation layer wraps the light-emitting layer and side surface of the first semiconductor layer.
  • the passivation layer can protect the first semiconductor layer, and the passivation layer wraps the sides of the light-emitting layer, which can further reduce leakage of the light-emitting layer.
  • the micro light-emitting diode chip in the embodiment of the present application may further include: a second reflective layer located on the side of the first semiconductor layer away from the light-emitting layer.
  • the second reflective layer can reflect the light emitted from the light-emitting layer towards the first semiconductor layer. Most of the light reflected by the second reflective layer can be emitted from the normal direction after being converged by the first semiconductor layer and the second semiconductor layer.
  • the reflected light that deviates from the normal direction at a larger angle can be reflected back to the interior of the epitaxial layer by the first reflective layer, and can also be emitted from the normal direction after multiple reflections and convergence.
  • the normal brightness can be further increased by providing a second reflective layer, and the second reflective layer can also protect the first semiconductor layer.
  • the second reflective layer can be arranged to wrap the side surfaces of the light-emitting layer and the first semiconductor layer. Therefore, by wrapping the side surfaces of the light-emitting layer with the second reflective layer, leakage of the light-emitting layer can be further reduced.
  • the second reflective layer may include a thin film material with high reflectivity.
  • the second reflective layer may be a distributed Bragg reflection layer (DBR).
  • the distributed Bragg reflection layer is a non-conductive material.
  • the reflective layer can keep the second reflective layer insulated from the first semiconductor layer and the light-emitting layer.
  • the second reflective layer may also be a stacked structure of an insulating layer-metal layer-insulating layer.
  • the insulating layer may include a transparent layer such as silicon dioxide. Material.
  • the second reflective layer can also adopt other structures or materials, which are not limited here.
  • the light-emitting surface of the micro-LED chip can be located on the side of the second semiconductor layer away from the light-emitting layer, and the first reflective layer can cover the edge of the second surface to form a light-emitting aperture on the light-emitting surface.
  • the light-emitting aperture The area is smaller than the area of the second surface. Therefore, the light exit aperture can constrain the light spot, and can effectively control the shape and size of the light spot, making the light spot of the micro light-emitting diode chip controllable.
  • the first reflective layer covering the second surface can be patterned according to actual needs to change the size and shape of the light exit aperture.
  • the shape of the light exit aperture can be square, circular, or polygonal. Of course, the light exit aperture can also be in other shapes, which is not limited here.
  • the geometric center of the light-emitting aperture can be set to be substantially aligned with the geometric center of the light-emitting layer.
  • the micro light-emitting diode chip in order to realize the electrical connection between the second electrode and the second semiconductor layer, can adopt a mesa structure, that is, the first semiconductor layer and the light-emitting layer can be corresponding to the second electrode. Partially removed, the second electrode can be directly electrically connected to the second semiconductor layer.
  • the pattern of the light-emitting layer is located in the area outside the second electrode, and the light-emitting aperture can also be set in the area corresponding to the area other than the second electrode, so that the geometric center of the light-emitting aperture is basically aligned with the geometric center of the light-emitting layer, thereby improving the micro-LED chip.
  • the light extraction efficiency in order to realize the electrical connection between the second electrode and the second semiconductor layer, the micro light-emitting diode chip can adopt a mesa structure, that is, the first semiconductor layer and the light-emitting layer can be corresponding to the second electrode. Partially removed, the second electrode can be directly electrically connected to the second semiconductor
  • the first semiconductor layer and the light-emitting layer have a mesa structure, there is a large height difference between the third surface of the first semiconductor layer and the first surface of the second semiconductor layer at a position corresponding to the second electrode, As a result, the thickness uniformity of the subsequently coated film layer is poor, and there is a gap between the second electrode and the edge of the first semiconductor layer and the light-emitting layer. Foreign matter such as glue during the process is easy to remain in the gap. In addition, in In subsequent processes, some processes require applying pressure to the micro-LED chip, and the micro-LED chip is easily broken at the gap.
  • the micro light-emitting diode chip may further include: a through hole penetrating the first semiconductor layer and the light-emitting layer, and the second electrode is electrically connected to the second semiconductor layer through the through hole.
  • a through hole penetrating the first semiconductor layer and the light-emitting layer
  • the second electrode is electrically connected to the second semiconductor layer through the through hole.
  • the area of the light-emitting layer can reduce the area loss of the active area in the light-emitting layer, maximize the use of the area of the light-emitting layer, significantly increase the normal brightness, and improve the luminous efficiency of the micro-light-emitting diode chip.
  • An insulating isolation layer is provided between the second electrode, the first semiconductor layer and the luminescent layer.
  • the second electrode is insulated from the first semiconductor layer and the luminescent layer through the insulating isolation layer, so that the second electrode can be insulated from the first semiconductor layer and emit light. Maintain insulation between layers.
  • the second electrode is electrically connected to the second semiconductor layer through the through hole. There is no gap between the second electrode and the edge of the first semiconductor layer and the light-emitting layer. In this way, no foreign matter such as glue will remain during the process, and the micro-luminescence will be emitted.
  • the micro light-emitting diode chip is not easily broken when pressure is applied to the diode chip, thereby improving the reliability of the micro light-emitting diode chip.
  • the through hole can be filled with the material of the second electrode first, so that the third surface of the first semiconductor layer has better flatness, and the subsequently coated film layer (such as the passivation layer or the second reflective layer)
  • the subsequently coated film layer such as the passivation layer or the second reflective layer
  • the thickness uniformity of the film layer is good, making the process more stable and controllable, and the surface before forming the first electrode and the remaining second electrode is relatively flat, which reduces the process difficulty and improves the product yield.
  • ion implantation can be used to form a high-resistance region in the first semiconductor layer and the light-emitting layer.
  • the position of the high-resistance region corresponds to the position of the second electrode to be formed.
  • the high-resistance region can be formed toward the second electrode. Inject nitrogen or hydrogen into a semiconductor layer and the light-emitting layer to change the lattice structure of the first semiconductor layer and the light-emitting layer, so that the first semiconductor layer and the light-emitting layer are insulated in the high-resistance region.
  • the first semiconductor layer and the light-emitting layer are etched to form a through hole penetrating the first semiconductor layer and the light-emitting layer in the high resistance area, and an insulating isolation layer is formed around the through hole, that is, the insulating isolation layer is the high resistance area. Obtained after removing through holes. After that, a first electrode and a second electrode are formed, the second electrode fills the through hole, and the second electrode is insulated from the first semiconductor layer and the light-emitting layer through the insulating isolation layer.
  • ion implantation is used to form a high-resistance region in the first semiconductor layer and the light-emitting layer, and a through hole is formed in the high-resistance region to realize the second electrode.
  • the electrical connection with the second semiconductor layer will not directly etch the first semiconductor layer and the light-emitting layer, causing less damage to the first semiconductor layer and the light-emitting layer, and will not affect the luminous efficiency of the micro light-emitting diode chip.
  • the insulating isolation layer can also be made of other insulating materials.
  • the insulating isolation layer can be made of SiO 2 , SiN, Al 2 O 3 and other insulating materials.
  • an opening with a size larger than the through hole can be formed at a position corresponding to the second electrode to be formed, and then the opening is filled with insulating material, and the insulating material in the opening is etched to form Through holes, and an insulating isolation layer is formed around the through holes, that is, the insulating isolation layer is obtained after the insulating material in the opening is removed from the through holes.
  • a first electrode and a second electrode are formed, the second electrode fills the through hole, and the second electrode is insulated from the first semiconductor layer and the light-emitting layer through the insulating isolation layer.
  • the second semiconductor layer is provided with a groove corresponding to the position of the through hole on the first surface, and part of the second electrode is located in the groove.
  • the first semiconductor layer, the light emitting layer and part of the second semiconductor layer can be etched to form a through hole penetrating the first semiconductor layer and the light emitting layer, and form a through hole on the first surface of the second semiconductor layer.
  • the groove corresponding to the through hole can ensure that the subsequently formed second electrode can be electrically connected to the second semiconductor layer, thereby improving the process yield.
  • the first semiconductor layer and the light-emitting layer can be etched to leak the first surface of the second semiconductor layer, as long as the second electrode and the second The semiconductor layer only needs to be electrically connected.
  • inventions of the present application also provide a display panel.
  • the display panel may include any of the above-mentioned micro light-emitting diode chips and a substrate.
  • the micro light-emitting diode chip is located on the substrate.
  • a driving circuit can be formed on the surface of the base substrate, and the micro light-emitting diode chip can be electrically connected to the driving circuit on the surface of the base substrate through the solder joint 1 .
  • a large number of micro light-emitting diode chips can be transferred in batches through mass transfer, and then the micro light-emitting diode chips are fixed on the substrate through bonding.
  • the display panel including any of the above-mentioned micro light-emitting diode chips has a better display effect.
  • inventions of the present application also provide an electronic device.
  • the electronic device may include: any of the above display panels and a casing.
  • the casing wraps the display panel. That is to say, the micro light-emitting diodes in the embodiments of the present application
  • the chip can be used as a display pixel and used in various display electronic devices.
  • the electronic devices can be display products such as mobile phones, watches, and computers.
  • the electronic device includes: any of the above-mentioned micro-light-emitting diode chips.
  • the micro-light-emitting diode chip can also be used as a pixelated array light source to be used in fields such as photosensitivity, projection, optical communication, and printing, that is, electronics
  • the equipment can also be photosensitive equipment, projection equipment, optical communication equipment, printing equipment or lighting equipment, etc.
  • embodiments of the present application also provide a method for manufacturing a micro light-emitting diode chip.
  • the method of manufacturing a micro light-emitting diode chip may include:
  • a first electrode electrically connected to the first semiconductor layer is formed on a side of the first semiconductor layer away from the light-emitting layer, and a second electrode electrically connected to the second semiconductor layer is formed on a side of the second semiconductor layer close to the first light-emitting layer;
  • the second semiconductor layer is processed so that the second surface of the second semiconductor layer is directly on the plane of the first surface.
  • the projection is located within the range of the first surface; the first surface is the surface of the second semiconductor layer close to the light-emitting layer, and the second surface is the surface of the second semiconductor layer far away from the light-emitting layer.
  • the second semiconductor layer is processed so that the orthographic projection of the second surface of the second semiconductor layer on the plane of the first surface is located within the range of the first surface.
  • the second semiconductor layer can be equivalent to a microlens, so that the structure of the micro-LED chip itself can be used to form a micro-lens.
  • the micro-lens can converge the light emitted from the luminescent layer, thereby reducing the luminous angle of the micro-LED chip. , and improve the normal brightness of the miniature light-emitting diode chip.
  • the size of the micro light-emitting diode chip remains basically unchanged, which does not affect the active area area of the micro light-emitting diode chip, and therefore does not affect the luminous efficiency of the micro light-emitting diode chip. Therefore, the light energy utilization efficiency of the micro light-emitting diode chip can be improved.
  • the structure of the micro light-emitting diode chip itself is used to form the microlens, without adding other additional components.
  • the second semiconductor layer patterning process parameters can be adjusted to obtain the second semiconductor layer.
  • the structure of the semiconductor layer and the manufacturing process are relatively simple and will not increase the manufacturing cost.
  • the implementation of the manufacturing method can refer to the implementation of the above-mentioned micro light-emitting diode chip, and there will be no duplication. Again.
  • Figure 1 is a schematic structural diagram of a micro light-emitting diode chip provided by an embodiment of the present application
  • Figure 2 is another structural schematic diagram of a micro light-emitting diode chip provided by an embodiment of the present application.
  • Figure 3 is another structural schematic diagram of a micro light-emitting diode chip provided by an embodiment of the present application.
  • Figure 4 is another structural schematic diagram of a micro light-emitting diode chip provided by an embodiment of the present application.
  • Figure 5 is another structural schematic diagram of a micro light-emitting diode chip provided by an embodiment of the present application.
  • Figure 6 is another structural schematic diagram of a micro light-emitting diode chip provided by an embodiment of the present application.
  • Figure 7 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • Figure 8 is a flow chart of a manufacturing method of a micro light-emitting diode chip provided by an embodiment of the present application.
  • 9 to 16 are schematic structural diagrams corresponding to each step in the manufacturing method of a micro light-emitting diode chip provided by embodiments of the present application.
  • 10-Micro light-emitting diode chip 11-First semiconductor layer; 12-Second semiconductor layer; 13-Light-emitting layer; 14-First electrode; 15-Second electrode; 16-First reflective layer; 17-Passivation layer ; 18-Second reflective layer; 19-Insulating isolation layer; 20-Substrate substrate; 401-Substrate; 402-First substrate; 403-Sacrificial layer; 404-First bonding layer; 405-Second bonding Layer; 406-second substrate; S1-first surface; S2-second surface; S3-third surface; S4-fourth surface; T-through hole; U-groove; W-gap; Q-high resistance district.
  • Embodiments of the present application provide a micro light-emitting diode chip, a manufacturing method thereof, a display panel and electronic equipment.
  • the micro light-emitting diode chip can be a Micro LED.
  • the micro light-emitting diode chip can also be a Mini LED or other size light-emitting diode chips.
  • the micro-LED chips in the embodiments of the present application can be used in various electronic devices.
  • the micro-LED chips can be used as display pixels and used in various display-type electronic devices.
  • the electronic devices can be mobile phones and watches. , computers and other display products, or micro-LED chips can be used as pixelated array light sources to be used in fields such as photosensitivity, projection, optical communication, printing, etc. That is, electronic equipment can also be photosensitive equipment, projection equipment, optical communication equipment , printing equipment or lighting equipment, etc.
  • FIG 1 is a schematic structural diagram of a micro light-emitting diode chip provided by an embodiment of the present application.
  • the micro light-emitting diode chip provided by an embodiment of the present application may include: a first semiconductor layer 11, a second semiconductor layer 12 located on the third The light-emitting layer 13, the first electrode 14, and the second electrode 15 are between a semiconductor layer 11 and a second semiconductor layer 12.
  • the first electrode 14 is located on the side of the first semiconductor layer 11 away from the light-emitting layer 13.
  • the second electrode 15 is located on the side of the second semiconductor layer 12 close to the light-emitting layer 13.
  • the first electrode 14 is electrically connected to the first semiconductor layer 11.
  • the two electrodes 15 are electrically connected to the second semiconductor layer 12 .
  • the light-emitting layer 13 is located between the first semiconductor layer 11 and the second semiconductor layer 12.
  • the first semiconductor layer 11 and the second semiconductor layer 12 may include different types of semiconductor materials, so that the first semiconductor layer 11
  • the first semiconductor layer 11 and the second semiconductor layer 12 can respectively provide different types of carriers.
  • the first semiconductor layer 11 can provide electrons
  • the second semiconductor layer 12 can provide holes
  • the first semiconductor layer 11 can provide holes
  • the second semiconductor layer 12 can provide holes.
  • the second semiconductor layer 12 can provide electrons.
  • the first electrode 14 is electrically connected to the first semiconductor layer 11, and the second electrode 15 is electrically connected to the second semiconductor layer 12.
  • the light-emitting layer 13 may be a multi-quantum well, thereby improving the luminous efficiency of the light-emitting layer 13 .
  • the first electrode 14 is located on the side of the first semiconductor layer 11 away from the light-emitting layer 13
  • the second electrode 15 is located on the side of the second semiconductor layer 12 close to the light-emitting layer 13 , that is, the first electrode 14 and the second electrode 15 are located on the side of the second semiconductor layer 12 close to the light-emitting layer 13 .
  • the two electrodes 15 are located on the same side of the micro light-emitting diode chip. In this way, when the micro light-emitting diode chip in the embodiment of the present application is used in a display panel or electronic device, it is convenient to bind the micro light-emitting diode chip to the substrate.
  • the second semiconductor layer 12 has a first surface S1 and a second surface S2 arranged oppositely.
  • the first surface S1 is the surface of the second semiconductor layer 12 close to the light-emitting layer 13
  • the second surface S2 is The surface of the second semiconductor layer 12 is far away from the light-emitting layer 13
  • the orthographic projection of the second surface S2 on the plane of the first surface S1 is located within the range of the first surface S1 . That is to say, the area of the second surface S2 of the second semiconductor layer 12 is smaller than the area of the first surface S1, and the orthographic projection of the second surface S2 on the plane of the first surface S1 does not exceed the range of the first surface S1.
  • the second semiconductor layer 12 can have inclined side surfaces, so that the second semiconductor layer 12 is equivalent to a microlens, and the microlens can condense the light emitted from the light-emitting layer 13 .
  • the second semiconductor layer can be equivalent to Microlens, which can use the structure of the micro-LED chip itself to form a micro-lens.
  • the micro-lens can converge the light emitted from the luminescent layer, thereby reducing the luminous angle of the micro-LED chip and increasing the normal brightness of the micro-LED chip.
  • the size of the micro light-emitting diode chip remains basically unchanged, which will not affect the active power of the micro light-emitting diode chip.
  • the structure of the micro light-emitting diode chip itself is used to form the microlens, without adding other additional components.
  • the second semiconductor layer patterning process parameters can be adjusted to obtain the second semiconductor layer.
  • the structure of the semiconductor layer and the manufacturing process are relatively simple and will not increase the manufacturing cost.
  • the second semiconductor layer 12 in the direction in which the first semiconductor layer 11 points to the second semiconductor layer 12 (for example, the direction shown by arrow F1 in the figure), the second semiconductor layer 12 is parallel to the direction of the second semiconductor layer 12 .
  • the cross-sectional area in the direction of the two surfaces S2 has a gradually decreasing trend, that is, in the direction in which the first semiconductor layer 11 points to the second semiconductor layer 12, the second semiconductor layer 12 has a tapered shape.
  • the shape of the cross section of the second semiconductor layer 12 in the direction perpendicular to the second surface S2 (for example, the cross section shown in FIG. 1 ) may be a trapezoid.
  • the angle between the side surface of the second semiconductor layer 12 and the first surface S1 can be set in the range of 30° to 85°, preferably in the range of 40° to 60°.
  • the second semiconductor layer 12 has a better light condensing effect, so that the normal brightness of the micro light-emitting diode chip is higher.
  • the side surfaces of the second semiconductor layer 12 may also have other shapes, as long as the orthographic projection of the second surface S2 of the second semiconductor layer 12 on the plane of the first surface S1 is located on the first surface. It can be within the range of S1.
  • the side surfaces of the second semiconductor layer 12 may have a certain curvature.
  • the second semiconductor layer 12 may have a certain curvature in the direction parallel to the second surface S2.
  • the cross-sectional area may gradually increase first and then decrease (or decrease first and then increase).
  • FIG 2 is another structural schematic diagram of a micro light-emitting diode chip provided by an embodiment of the present application.
  • the micro light-emitting diode chip in an embodiment of the present application may also include: a first reflective layer 16; Cover at least part of the side surfaces of the second semiconductor layer 12 .
  • the first reflective layer 16 can reflect the light emitted toward the side of the micro LED chip, thereby reducing the light emitted from the side, and the first reflective layer 16 can reflect the light back to the inside of the micro LED chip, so that this part of the light passes through After multiple reflections, it can be emitted in the normal direction, which can effectively constrain the luminous angle of the micro-LED chip (for example, the luminous angle of the micro-LED chip can be made less than 120°), and further improve the normal brightness.
  • the second semiconductor layer 12 by arranging the second semiconductor layer 12 so that the orthographic projection of the second surface S2 on the plane of the first surface S1 is located within the range of the first surface S1, the second semiconductor layer 12 has an inclined side surface, This provides necessary conditions for subsequent formation of the first reflective layer 16 on the side of the second semiconductor layer 12 .
  • the material of the first reflective layer 16 can be effectively adhered to the side surface of the second semiconductor layer 12, so that the thickness uniformity of the manufactured first reflective layer 16 is better.
  • the first reflective layer 16 may include a thin film material with high reflectivity.
  • the first reflective layer 16 may be a distributed Bragg reflection layer (DBR).
  • the distributed Bragg reflection layer is a
  • the non-conductive reflective layer can keep the first reflective layer 16 and the second semiconductor layer 12 insulated.
  • the first reflective layer 16 may also be a stacked structure of an insulating layer-a metal layer-an insulating layer.
  • the insulating layer may include a transparent material such as silicon dioxide.
  • the first reflective layer 16 can also adopt other structures or materials, which are not limited here. In the actual process, evaporation or thin film growth process can be used to make the first reflective layer 16 .
  • the first semiconductor layer 11 has a third surface S3 and a fourth surface S4 arranged oppositely.
  • the third surface S3 is the side of the first semiconductor layer 11 away from the light-emitting layer 13
  • the fourth surface S4 is the surface of the first semiconductor layer 11 close to the light-emitting layer 13 .
  • the orthographic projection of the fourth surface S4 on the plane of the third surface S3 is located within the range of the third surface S3 . That is to say, the area of the fourth surface S4 of the first semiconductor layer 11 is smaller than the area of the third surface S3, and the orthographic projection of the fourth surface S4 on the plane of the third surface S3 does not exceed the range of the third surface S3.
  • the first semiconductor layer 11 can also have inclined side surfaces, so that the first semiconductor layer 11 can also have inclined side surfaces.
  • the semiconductor layer 11 is equivalent to a microlens, and the microlens can condense light.
  • the cross-sectional area of the first semiconductor layer 11 in the direction parallel to the fourth surface S4 It has a gradually decreasing trend, that is, in the direction in which the first semiconductor layer 11 points to the second semiconductor layer 12 , the first semiconductor layer 11 has a tapered shape.
  • the shape of the cross section of the first semiconductor layer 11 in the direction perpendicular to the fourth surface S4 may be a trapezoid, so that the first semiconductor layer 11 can have a better convergence effect.
  • the angle between the side surface of the first semiconductor layer 11 and the third surface S3 can be set in the range of 30° to 85°, preferably in the range of 40° to 60°. In this way, The first semiconductor layer 11 has a better light condensing effect.
  • the side surfaces of the first semiconductor layer 11 may also have other shapes, as long as the orthographic projection of the fourth surface S4 on the plane of the third surface S3 is located within the range of the third surface S3.
  • the side surfaces of the first semiconductor layer 11 may have a certain curvature.
  • the first semiconductor layer 11 may have a certain curvature in the direction parallel to the fourth surface S4 .
  • the cross-sectional area may gradually increase first and then decrease (or decrease first and then increase).
  • the light-emitting layer 13 can also be configured to have an inclined side, that is, the orthographic projection of the surface of the light-emitting layer 13 close to the second semiconductor layer 12 on the fourth surface S4 can be located near the first surface S4 of the light-emitting layer 13 .
  • the opening area (or light-shielding area) of the mask in the process corresponds to the area of the entire epitaxial layer.
  • the larger area of the opening area (or light-shielding area) can reduce the accuracy requirements of the mask and reduce the difficulty of the process.
  • the total thickness of the first semiconductor layer 11, the light-emitting layer 13 and the second semiconductor layer 12 can be set to less than 8 ⁇ m.
  • the first reflective layer 16 may cover the sides of the first semiconductor layer 11 , the light emitting layer 13 and the second semiconductor layer 12 . In this way, the first reflective layer 16 can cover most or even the entire side of the epitaxial layer. The first reflective layer 16 covers a larger area. Therefore, the first reflective layer 16 can reflect more light, preventing light from emitting from the side. Moreover, the light can be emitted in the normal direction after being reflected multiple times by the first reflective layer 16 , further reducing the luminous angle of the micro light-emitting diode chip and further increasing the normal brightness.
  • the first semiconductor layer 11 , the light-emitting layer 13 and the second semiconductor layer 12 all have inclined side surfaces, which provides necessary conditions for the subsequent formation of the first reflective layer 16 on the side surfaces of the epitaxial layer.
  • the material of the first reflective layer 16 can be effectively adhered to the side of the epitaxial layer, so that the thickness of the manufactured first reflective layer 16 has good uniformity.
  • the above-mentioned micro light-emitting diode chip may also include: a passivation layer 17 located on the side of the first semiconductor layer 11 away from the light-emitting layer 13 . 17 can protect the first semiconductor layer 11 .
  • Figure 3 is another structural schematic diagram of a micro light-emitting diode chip provided by an embodiment of the present application.
  • the above-mentioned micro light-emitting diode chip may also include: located on the first semiconductor layer 11
  • the second reflective layer 18 is on the side away from the light-emitting layer 13 .
  • the second reflective layer 18 can reflect the light emitted from the light-emitting layer 13 towards the first semiconductor layer 11. Most of the light reflected by the second reflective layer 18 can be emitted from the normal direction after being converged by the first semiconductor layer 11 and the second semiconductor layer 12.
  • the normal brightness can be further increased by providing the second reflective layer 18, and the second reflective layer 18 It can also play a protective role on the first semiconductor layer 11 .
  • the second reflective layer 18 may include a thin film material with high reflectivity.
  • the second reflective layer 18 may be a distributed Bragg reflection layer (DBR).
  • the distributed Bragg reflection layer is a
  • the non-conductive reflective layer can keep the second reflective layer 18 insulated from the first semiconductor layer 11 .
  • the second reflective layer 18 may also have a stacked structure of an insulating layer-a metal layer-an insulating layer.
  • the insulating layer may include a transparent material such as silicon dioxide.
  • the second reflective layer 18 can also adopt other structures or materials, which are not limited here.
  • Figure 4 is another structural schematic diagram of a micro light-emitting diode chip provided by an embodiment of the present application
  • the cross-sectional areas of the light-emitting layer 13 and the first semiconductor layer 11 in the direction parallel to the second surface S2 are consistent. It can be understood that here, the cross-sectional areas are consistent.
  • the cross-sectional areas are basically the same within a certain error range. That is to say, in the embodiment shown in FIG. 4 , only the second semiconductor layer 12 has inclined side surfaces.
  • the thickness of the second semiconductor layer 12 can be set to less than 5 ⁇ m.
  • the edges of the first semiconductor layer 11 and the light-emitting layer 13 are approximately vertical, which can make the area of the side of the light-emitting layer 13 smaller, thereby reducing leakage on the side of the light-emitting layer 13 .
  • two patterning processes can be used to pattern the epitaxial layer.
  • the first semiconductor layer 11 and the light-emitting layer 13 can be patterned first, and then the micro light-emitting diode chip is turned over, and then the epitaxial layer can be patterned.
  • Patterning the second semiconductor layer 12 can make the etching depth of each patterning process smaller and reduce the difficulty of the patterning process.
  • the first reflective layer 16 may only cover the side surfaces of the second semiconductor layer 12 .
  • the first reflective layer 16 can reflect the light emitted toward the side of the micro LED chip, thereby reducing the light emitted from the side, and the first reflective layer 16 can reflect the light back to the inside of the micro LED chip, so that this part of the light passes through After multiple reflections, it can be emitted in the normal direction, which can effectively constrain the luminous angle of the micro-LED chip and further enhance the normal brightness.
  • the micro light-emitting diode chip in the embodiment of the present application may also include: a passivation layer 17, the passivation layer 17 is located on the side of the first semiconductor layer 11 away from the light-emitting layer 13, and the passivation layer 17 17 wraps the side surfaces of the light-emitting layer 13 and the first semiconductor layer 11 .
  • the passivation layer 17 can protect the first semiconductor layer 11 , and the passivation layer 17 wraps the side of the light-emitting layer 13 to further reduce leakage of the light-emitting layer 13 .
  • Figure 5 is another structural schematic diagram of a micro light-emitting diode chip provided in an embodiment of the present application.
  • the micro light-emitting diode chip in the embodiment of the present application may also include:
  • the first semiconductor layer 11 is away from the second reflective layer 18 on the side of the light-emitting layer 13 .
  • the second reflective layer 18 can reflect the light emitted from the light-emitting layer 13 towards the first semiconductor layer 11. Most of the light reflected by the second reflective layer 18 can be emitted from the normal direction after being converged by the first semiconductor layer 11 and the second semiconductor layer 12.
  • the normal brightness can be further increased by providing the second reflective layer 18 , and the second reflective layer 18 can also protect the first semiconductor layer 11 .
  • the second reflective layer 18 can be arranged to wrap the side surfaces of the light-emitting layer 13 and the first semiconductor layer 11 . Therefore, by wrapping the side surfaces of the light-emitting layer 13 with the second reflective layer 18 , leakage of the light-emitting layer 13 can be further reduced.
  • the second reflective layer 18 may include a thin film material with high reflectivity.
  • the second reflective layer 18 may be a distributed Bragg reflection layer (DBR).
  • the distributed Bragg reflection layer is a
  • the non-conductive reflective layer can keep the second reflective layer 18 insulated from the first semiconductor layer 11 and the light-emitting layer 13 .
  • the second reflective layer 18 may also be a stacked structure of an insulating layer-metal layer-insulating layer.
  • the insulating layer may include Including transparent materials such as silica.
  • the second reflective layer 18 can also adopt other structures or materials, which are not limited here.
  • the light-emitting surface of the micro-LED chip can be located on the side of the second semiconductor layer 12 away from the light-emitting layer 13 , and the first reflective layer 16 can cover the second surface S2 edge to form a light-emitting aperture on the light-emitting surface.
  • the area of the light-emitting aperture is smaller than the area of the second surface S2. Therefore, the light-emitting aperture can constrain the light spot, and can effectively control the shape and size of the light spot, making the light spot of the micro-LED chip controllable. .
  • the display effect can be improved.
  • the first reflective layer 16 covering the second surface S2 can be patterned according to actual needs to change the size and shape of the light exit aperture.
  • the shape of the light exit aperture can be square, circular, or polygonal.
  • the light exit aperture can also be in other shapes, which is not limited here.
  • the geometric center of the light-emitting aperture can be set to be substantially aligned with the geometric center of the light-emitting layer 13 .
  • FIG. 6 is another structural schematic diagram of a micro light-emitting diode chip provided by an embodiment of the present application.
  • the micro light-emitting diode chip in order to realize the electrical connection between the second electrode 15 and the second semiconductor layer 12
  • the micro light-emitting diode chip can adopt a mesa structure, that is, the portions of the first semiconductor layer 11 and the light-emitting layer 13 corresponding to the second electrode 15 can be removed, so that the second electrode 15 can be directly electrically connected to the second semiconductor layer 12 .
  • the pattern of the light-emitting layer 13 is located in the area outside the second electrode 15 , that is, the pattern of the light-emitting layer 13 is located in the left area in FIG.
  • the light-emitting aperture can also be set to correspond to the second electrode 15 .
  • the area outside the electrode 15, for example, the light exit aperture is located in the left area in FIG. 6, so that the geometric center of the light exit aperture is basically aligned with the geometric center of the light emitting layer 13, thereby improving the light extraction efficiency of the micro light emitting diode chip.
  • the third surface S3 of the first semiconductor layer 11 is in contact with the second semiconductor layer 11 .
  • There is a large height difference between the first surfaces S1 of the layer 12, resulting in poor thickness uniformity of the subsequently coated film layer, and between the second electrode 15 and the edges of the first semiconductor layer 11 and the light-emitting layer 13 There is a gap W, and foreign matter such as glue during the process is easy to remain in the gap W.
  • some processes need to apply pressure to the micro light-emitting diode chip, and the micro light-emitting diode chip is easy to break at the gap W.
  • the micro light-emitting diode chip may also include: a through hole T penetrating the first semiconductor layer 11 and the light emitting layer 13 , and the second electrode 15 passes through the through hole T. It is electrically connected to the second semiconductor layer 12, so that there is no need to dig out a large area of the luminescent layer 13, which can reduce the area loss of the active area in the luminescent layer 13, maximize the use of the area of the luminescent layer 13, and significantly improve the normal brightness. , improve the luminous efficiency of micro light-emitting diode chips.
  • An insulating isolation layer 19 is provided between the second electrode 15 and the first semiconductor layer 11 and the luminescent layer 13.
  • the second electrode 15 is insulated from the first semiconductor layer 11 and the luminescent layer 13 through the insulating isolation layer 19, so that the second electrode 15 can be insulated from the first semiconductor layer 11 and the luminescent layer 13.
  • the electrode 15 is insulated from the first semiconductor layer 11 and the light emitting layer 13 .
  • the material of the second electrode 15 can be used to fill the through hole T first, so that the third surface S3 of the first semiconductor layer 11 has better flatness, and the subsequently coated film layer (such as a passivation layer or second reflective layer) has better thickness uniformity, making the process more stable and controllable, and the surface before forming the first electrode 14 and the remaining second electrode 15
  • the surface is relatively flat, which reduces process difficulty and improves product yield.
  • the effective area of the luminescent layer 13 in the structure shown in Figure 5 is larger, and the geometric center of the luminescent layer 13 is closer to the center of the entire micro-LED chip.
  • the geometric center of the light exit aperture is Arranged to be substantially aligned with the geometric center of the light-emitting layer 13, the light emitted from the micro-LED chip can be more concentrated at the center position, so that the luminous efficiency of the micro-LED chip is higher.
  • ion implantation can be used to form a high-resistance region in the first semiconductor layer 11 and the light-emitting layer 13.
  • the position of the high-resistance region corresponds to the position of the second electrode 15 to be formed.
  • Nitrogen element or hydrogen element can be injected into the first semiconductor layer 11 and the light-emitting layer 13 to change the lattice structure in the first semiconductor layer 11 and the light-emitting layer 13, so that the first semiconductor layer 11 and the light-emitting layer 13 have high resistance. Area insulation.
  • the first semiconductor layer 11 and the light-emitting layer 13 are etched to form a through hole T penetrating the first semiconductor layer 11 and the light-emitting layer 13 in the high resistance area, and an insulating isolation layer 19 is formed around the through hole T, that is, The insulating isolation layer 19 is obtained by removing the through hole T in the high resistance region.
  • the first electrode 14 and the second electrode 15 are formed, the second electrode 15 fills the through hole T, and the second electrode 15 is insulated from the first semiconductor layer 11 and the light-emitting layer 13 by the insulating isolation layer 19 .
  • ion implantation is used to form a high-resistance region in the first semiconductor layer 11 and the light-emitting layer 13, and a through hole T is formed in the high-resistance region to realize the second electrode 15 and the second semiconductor layer 12.
  • the electrical connection between the first semiconductor layer 11 and the light-emitting layer 13 will not be directly etched, causing less damage to the first semiconductor layer 11 and the light-emitting layer 13, and will not affect the luminous efficiency of the micro light-emitting diode chip.
  • the insulating isolation layer 19 can also be made of other insulating materials.
  • the insulating isolation layer 19 can be made of SiO 2 , SiN, Al 2 O 3 and other insulating materials.
  • an opening with a size larger than the through hole T can be formed at a position corresponding to the second electrode 15 to be formed, and then the opening is filled with insulating material, and the insulating material in the opening is engraved.
  • the through hole T is formed by etching, and an insulating isolation layer 19 is formed around the through hole T. That is, the insulating isolation layer 19 is obtained after the insulating material in the opening is removed from the through hole T.
  • the first electrode 14 and the second electrode 15 are formed, the second electrode 15 fills the through hole T, and the second electrode 15 is insulated from the first semiconductor layer 11 and the light-emitting layer 13 by the insulating isolation layer 19 .
  • the second semiconductor layer 12 is provided with a groove U corresponding to the position of the through hole T on the first surface S1 , and part of the second electrode 15 is located in the groove U.
  • the first semiconductor layer 11, the light emitting layer 13 and part of the second semiconductor layer 12 can be etched to form the through hole T penetrating the first semiconductor layer 11 and the light emitting layer 13, and in the second
  • the first surface S1 of the semiconductor layer 12 forms a groove U corresponding to the through hole T. This ensures that the subsequently formed second electrode 15 can be electrically connected to the second semiconductor layer 12 and improves the process yield.
  • the first semiconductor layer 11 and the light-emitting layer 13 may be etched to leak the first surface S1 of the second semiconductor layer 12, as long as the first surface S1 of the second semiconductor layer 12 is exposed. It is sufficient that the two electrodes 15 and the second semiconductor layer 12 can be electrically connected.
  • FIG. 7 is a schematic structural diagram of the display panel provided by the embodiment of the present application.
  • the display panel may include: any of the above-mentioned micro light-emitting diode chips. 10 and a base substrate 20 on which the micro-LED chip 10 is located.
  • a driving circuit can be formed on the surface of the base substrate 20 , and the micro light-emitting diode chip can be electrically connected to the driving circuit on the surface of the base substrate 20 through the solder joints 201 .
  • a large number of micro-LED chips can be transferred in batches through mass transfer, and then the micro-LED chips 10 are fixed on the substrate 20 through bonding.
  • the display panel including any of the above-mentioned micro light-emitting diode chips has a better display effect.
  • inventions of the present application also provide an electronic device.
  • the electronic device may include: any of the above display panels and a casing.
  • the casing wraps the display panel. That is to say, the micro-luminescent device in the embodiment of the present application Diode chips can be used as display pixels in various display electronic devices.
  • the electronic devices can be display products such as mobile phones, watches, and computers.
  • the electronic device includes: any of the above-mentioned micro-light-emitting diode chips.
  • the micro-light-emitting diode chip can also be used as a pixelated array light source to be used in fields such as photosensitivity, projection, optical communication, and printing, that is, electronics
  • the equipment can also be photosensitive equipment, projection equipment, optical communication equipment, printing equipment or lighting equipment, etc.
  • an embodiment of the present application also provides a method for manufacturing a micro light-emitting diode chip.
  • Figure 8 is a flow chart of a method of manufacturing a micro light-emitting diode chip provided by an embodiment of the application. As shown in Figure 8, the micro light-emitting diode Chip manufacturing methods may include:
  • S304 Process the second semiconductor layer so that the orthographic projection of the second surface of the second semiconductor layer on the plane of the first surface is within the range of the first surface; the first surface is the area where the second semiconductor layer is close to the light-emitting layer. The second surface is the surface on the side of the second semiconductor layer away from the light-emitting layer.
  • the second semiconductor layer is processed so that the orthographic projection of the second surface of the second semiconductor layer on the plane of the first surface is located within the range of the first surface.
  • the second semiconductor layer can be equivalent to a microlens, so that the structure of the micro-LED chip itself can be used to form a micro-lens.
  • the micro-lens can converge the light emitted from the luminescent layer, thereby reducing the luminous angle of the micro-LED chip. , and improve the normal brightness of the miniature light-emitting diode chip.
  • the size of the micro light-emitting diode chip remains basically unchanged, which does not affect the active area area of the micro light-emitting diode chip, and therefore does not affect the luminous efficiency of the micro light-emitting diode chip. Therefore, the light energy utilization efficiency of the micro light-emitting diode chip can be improved.
  • the structure of the micro light-emitting diode chip itself is used to form the microlens, without adding other additional components.
  • the second semiconductor layer patterning process parameters can be adjusted to obtain the second semiconductor layer.
  • the structure of the semiconductor layer and the manufacturing process are relatively simple and will not increase the manufacturing cost.
  • Figures 9 to 16 are schematic structural diagrams corresponding to each step in the manufacturing method of the micro light-emitting diode chip provided by the embodiment of the present application. The following is a detailed description of the manufacturing method of the micro light-emitting diode chip provided by the embodiment of the present application with reference to Figures 9 to 16 illustrate.
  • the second semiconductor layer 12, the light emitting layer 13 and the first semiconductor layer 11 are sequentially formed on the substrate 401.
  • the above step S302 may include:
  • ion implantation is used to form a high-resistance region Q in the first semiconductor layer 11 and the light-emitting layer 13 .
  • the position of the high-resistance region Q corresponds to the position of the second electrode to be formed.
  • nitrogen element or hydrogen element can be injected into the first semiconductor layer 11 and the light-emitting layer 13 to change the lattice structure of the first semiconductor layer 11 and the light-emitting layer 13 so that the first semiconductor layer 11 and the light-emitting layer 13 Q is insulated in the high resistance area.
  • the implantation depth of the high-resistance region Q It is necessary to reach the surface of the second semiconductor layer 12 through the first semiconductor layer 11 and the light-emitting layer 13.
  • the depth of ion implantation can be increased so that the surface of the second semiconductor layer 12 also has a thin high-resistance region Q.
  • the area of the high-resistance region Q is slightly larger than the area of the second electrode to be formed, which facilitates the subsequent formation of an insulating isolation layer around the second electrode.
  • the first semiconductor layer 11 and the light-emitting layer 13 are etched, for example, a photolithography process can be used to form a through hole T penetrating the first semiconductor layer 11 and the light-emitting layer 13 in the high resistance area, and in the An insulating isolation layer 19 is formed around the through hole T. That is to say, the insulating isolation layer 19 is obtained after removing the through hole T in the high resistance region.
  • the first semiconductor layer 11, the light emitting layer 13 and part of the second semiconductor layer 12 can be etched to form the through hole T penetrating the first semiconductor layer 11 and the light emitting layer 13, and in the second The first surface S of the semiconductor layer 12 forms a groove U corresponding to the through hole T.
  • only the first semiconductor layer 11 and the light-emitting layer 13 may be etched to leak the first surface S1 of the second semiconductor layer 12, as long as the first surface S1 of the second semiconductor layer 12 is exposed. It is sufficient that the two electrodes 15 and the second semiconductor layer 12 can be electrically connected.
  • a first electrode 14 and a second electrode 15 are formed.
  • the first electrode 14 is electrically connected to the first semiconductor layer 11.
  • the second electrode 15 fills the through hole T.
  • the second electrode 15 communicates with the second electrode through the through hole T.
  • the semiconductor layer 12 is electrically connected, and the second electrode 15 is insulated from the first semiconductor layer 11 and the light-emitting layer 13 by the insulating isolation layer 19 .
  • a second reflective layer 18 (or passivation layer) may be formed on the surface of the first semiconductor layer 11 away from the light-emitting layer 13 .
  • the structure after forming the first electrode 14 and the second electrode 15 (for example, the structure shown in FIG. 12) is bonded to the first substrate 402 with the side having the first electrode 14.
  • a sacrificial layer 403 covering the first electrode 14 and the second electrode 15 can be formed first.
  • the sacrificial layer 403 can protect the first electrode 14 and the second electrode 15 and prevent the first electrode 14 and the second electrode 15 from being contaminated or contaminated. Scratches etc.
  • the structure after forming the first electrode 14 and the second electrode 15 is bonded to the first substrate 402 through the first bonding layer 404 .
  • the substrate is peeled off and the structure after peeling off the substrate is turned over to obtain the structure shown in Figure 13.
  • the second semiconductor layer 12 is processed, for example, a dry etching process may be used, so that the second surface S2 of the second semiconductor layer 12 is on the plane where the first surface S1 is located.
  • the orthographic projection of is located within the range of the first surface S1, where the first surface S1 is the surface of the second semiconductor layer 12 close to the light-emitting layer 13, and the second surface S2 is the surface of the second semiconductor layer 12 away from the light-emitting layer 13. surface.
  • the second semiconductor layer 12 , the light-emitting layer 13 and the first semiconductor layer 11 may be etched together, so that the second semiconductor layer 12 , the light-emitting layer 13 and the first semiconductor layer 11 all have Sloped sides.
  • step S304 may also include:
  • the first reflective layer 16 is formed to cover at least part of the side surface of the second semiconductor layer 12 . In one possible implementation, the first reflective layer 16 may only cover the side of the second semiconductor layer 12 . In another possible implementation, the first reflective layer 16 may cover the first semiconductor layer 11 and the light-emitting layer. 13 and the side surface of the second semiconductor layer 12 .
  • the second semiconductor layer 12 can also be bonded to the second substrate 406 through the second bonding layer 405, and then flipped over again, peeling off the first substrate and removing the sacrificial layer, to obtain The structure shown in Figure 16.
  • the structure shown in Figure 16 can be transferred to the base substrate through a transfer process.
  • the structure shown in Figure 7 can be obtained, thereby applying the micro light-emitting diode chip in the embodiment of the present application. in various electronic devices.

Abstract

本申请提供一种微型发光二极管芯片、其制作方法、显示面板及电子设备。微型发光二极管芯片可以包括：第一半导体层，第二半导体层，位于第一半导体层与第二半导体层之间的发光层，第一电极，以及第二电极。第一电极位于第一半导体层远离发光层的一侧，第二电极位于第二半导体层靠近发光层的一侧，第一电极与第一半导体层电连接，第二电极与第二半导体层电连接。第二半导体层中第二表面在第一表面所在平面上的正投影位于第一表面的范围内。这样可以使第二半导体层等效为微透镜，利用微型发光二极管芯片自身的结构形成微透镜，从而减小微型发光二极管芯片的发光角，并提高微型发光二极管芯片的法向亮度，提高微型发光二极管芯片的光能利用率。

Description

微型发光二极管芯片、其制作方法、显示面板及电子设备
相关申请的交叉引用
本申请要求在2022年05月30日提交中国专利局、申请号为202210597469.2、申请名称为“微型发光二极管芯片、其制作方法、显示面板及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种微型发光二极管芯片、其制作方法、显示面板及电子设备。
背景技术
随着显示技术的不断发展，微型发光二极管芯片(Micro LED)成为新一代显示技术的研究热点，Micro LED显示面板具有响应快、自主发光、高亮度、低功耗、超高解析度与色彩饱和度、可柔性显示及高寿命等优点。并且，微型发光二极管芯片也可作为像素化的阵列式光源，以应用于感光、投影、光通信等领域。
在大量的应用场景中，例如手表、手机显示，尤其是感光、投影类应用中，需要微型发光二极管芯片具有较小的发光角和较高的法向亮度，一般期望微型发光二极管芯片的发光角小于120°甚至达到60°左右，这样，可以使相邻的微型发光二极管芯片之间的串扰较小，以保证足够的光能利用率。
然而，在相关技术中，由于微型发光二极管芯片的尺寸较小、厚度相对较大，使得微型发光二极管芯片的侧面面积占比较大，侧面出光比例较大，并且，光线在微型发光二极管芯片的内部发出，部分光线在出光面容易发生全反射。从而，导致微型发光二极管芯片的发光角较大，实际发光角一般在140°～160°的范围内，另外，还导致微型发光二极管芯片的法向亮度较低，使得微型发光二极管芯片的光能利用率较低。
发明内容
本申请实施例提供一种微型发光二极管芯片、其制作方法、显示面板及电子设备，用以解决相关技术中微型发光二极管芯片的光能利用率较低的问题。
第一方面，本申请实施例提供一种微型发光二极管芯片，微型发光二极管芯片可以包括：第一半导体层，第二半导体层，位于第一半导体层与第二半导体层之间的发光层，第一电极，以及第二电极。第一电极位于第一半导体层远离发光层的一侧，第二电极位于第二半导体层靠近发光层的一侧，第一电极与第一半导体层电连接，第二电极与第二半导体层电连接。
在微型发光二极管芯片中，发光层位于第一半导体层和第二半导体层之间，第一半导体层和第二半导体层可以包括不同类型的半导体材料，使第一半导体层和第二半导体层可以分别提供不同类型的载流子，例如，第一半导体层可以提供电子，第二半导体层可以提供空穴，或者，第一半导体层可以提供空穴，第二半导体层可以提供电子。第一电极与第 一半导体层电连接，第二电极与第二半导体层电连接，向第一电极和第二电极施加电压时，可以驱动电子和空穴移动，使电子和空穴在发光层中复合发光。在具体实施时，发光层可以为多量子阱，从而提高发光层的发光效率。在本申请实施例中，第一电极位于第一半导体层远离发光层的一侧，第二电极位于第二半导体层靠近发光层的一侧，即第一电极和第二电极位于微型发光二极管芯片的同一侧，这样，将本申请实施例中的微型发光二极管芯片应用于显示面板或电子设备中，便于将微型发光二极管芯片绑定于衬底基板上。
在本申请实施例中，第二半导体层具有相对设置的第一表面和第二表面，第一表面为第二半导体层靠近发光层一侧的表面，第二表面为第二半导体层远离发光层一侧的表面，第二表面在第一表面所在平面上的正投影位于第一表面的范围内。也就是说，第二半导体层的第二表面的面积小于第一表面的面积，并且，第二表面在第一表面所在平面上的正投影未超出第一表面的范围。这样设置，可以使第二半导体层具有倾斜的侧面，从而使第二半导体层等效为微透镜，微透镜可以对发光层出射的光线进行汇聚。
本申请实施例提供的微型发光二极管芯片中，通过将第二半导体层设置为第二表面在第一表面所在平面上的正投影位于第一表面的范围内，可以使第二半导体层等效为微透镜，这样可以利用微型发光二极管芯片自身的结构形成微透镜，微透镜可以对发光层出射的光线进行汇聚，从而减小微型发光二极管芯片的发光角，并提高微型发光二极管芯片的法向亮度。并且，微型发光二极管芯片的尺寸基本不变，不会影响微型发光二极管芯片的有源区面积，因而不会影响微型发光二极管芯片的发光效率。因此，可以提高微型发光二极管芯片的光能利用率。此外，本申请实施例中，利用微型发光二极管芯片自身的结构形成微透镜，无需额外增加其他部件，在制作工艺过程中，可以通过调整第二半导体层图形化工艺的参数，就能够得到第二半导体层的结构，制作工艺较简单，不会增加制作成本。
在本申请的一些实施例中，在第一半导体层指向第二半导体层的方向上，第二半导体层在平行于第二表面的方向上的截面面积呈逐渐减小的趋势，也就是说，在第一半导体层指向第二半导体层的方向上，第二半导体层呈渐缩状。第二半导体层在垂直于第二表面的方向上的截面的形状可以为梯形。在具体实施时，第二半导体层的侧面与第一表面之间的夹角可以设置为在30°～85°的范围内，优选为在40°～60°的范围内，这样，可以使第二半导体层对光线的汇聚效果更好，使微型发光二极管芯片的法向亮度较高。在本申请的另一些实施例中，第二半导体层的侧面也可以为其他形状，只要满足第二半导体层中第二表面在第一表面所在平面上的正投影位于第一表面的范围内即可。例如，第二半导体层的侧面可以具有一定的弧度，举例来说，在第一半导体层指向第二半导体层的方向上，第二半导体层在平行于第二表面的方向上的截面面积可以呈逐渐先增大后减小(或者先减小后增大)的趋势。
本申请实施例中的微型发光二极管芯片还可以包括：第一反射层，第一反射层至少覆盖第二半导体层的部分侧面。第一反射层可以反射朝向微型发光二极管芯片侧面出射的光线，从而可以减少从侧面出射的光线，并且，第一反射层可以将光线反射回微型发光二极管芯片的内部，使这部分光线经多次反射后可以朝向法向出射，从而可以有效约束微型发光二极管芯片的发光角(例如，可以使微型发光二极管芯片的发光角小于120°)，并进一步提升法向亮度。
本申请实施例中，通过将第二半导体层设置为第二表面在第一表面所在平面上的正投影位于第一表面的范围内，使第二半导体层具有倾斜的侧面，为后续在第二半导体层的侧 面形成第一反射层提供了必要条件。在制作工艺过程中，可以使第一反射层的材料有效附着在第二半导体层的侧面，使制作得到的第一反射层的厚度均一性较好。
在具体实施时，第一反射层可以包括具有高反射率的薄膜材料，例如，第一反射层可以为分布式布拉格反射层(distributed bragg reflection，DBR)，分布式布拉格反射层是一种不导电的反射层，可以使第一反射层与第二半导体层保持绝缘。或者，第一反射层也可以为绝缘层-金属层-绝缘层的叠层结构，例如，该绝缘层可以包括二氧化硅等透明材料。当然，第一反射层也可以采用其他结构或材料，此处不做限定。在实际工艺过程中，可以采用蒸镀或者薄膜生长工艺制作第一反射层。
在本申请的一些实施例中，第一半导体层具有相对设置的第三表面和第四表面，第三表面为第一半导体层远离发光层一侧的表面，第四表面为第一半导体层靠近发光层一侧的表面，第四表面在第三表面所在平面上的正投影位于第三表面的范围内。也就是说，第一半导体层的第四表面的面积小于第三表面的面积，并且，第四表面在第三表面所在平面上的正投影未超出第三表面的范围。这样设置，可以使第一半导体层也具有倾斜的侧面，从而使第一半导体层等效为微透镜，微透镜可以对光线进行汇聚。
在具体实施时，在第一半导体层指向第二半导体层的方向上，第一半导体层在平行于第四表面的方向上的截面面积呈逐渐减小的趋势，也就是说，在第一半导体层指向第二半导体层的方向上，第一半导体层呈渐缩状。第一半导体层在垂直于第四表面的方向上的截面的形状可以为梯形，这样，可以使第一半导体层的汇聚效果较好。在具体实施时，第一半导体层的侧面与第三表面之间的夹角可以设置为在30°～85°的范围内，优选为在40°～60°的范围内，这样，可以使第一半导体层对光线的汇聚效果更好。当然，第一半导体层的侧面也可以为其他形状，只要满足第四表面在第三表面所在平面上的正投影位于第三表面的范围内即可。例如，第一半导体层的侧面可以具有一定的弧度，举例来说，在第一半导体层指向第二半导体层的方向上，第一半导体层在平行于第四表面的方向上的截面面积可以呈逐渐先增大后减小(或者先减小后增大)的趋势。
在实际应用中，可以将发光层也设置为具有倾斜的侧面，即发光层靠近第二半导体层一侧的表面在第四表面上的正投影，可以位于发光层靠近第一半导体层一侧的表面在第四表面上的正投影。这样设置，可以使外延层(外延层包括第一半导体层、第二半导体层和发光层)整体具有倾斜的侧面。在制作工艺过程中，可以对第二半导体层、发光层和第一半导体层一起进行图形化，相比于分别图形化可以减少图形化的次数，降低制作工艺成本，并且，图形化工艺的掩膜版的开口区域(或遮光区域)对应于整个外延层的区域，开口区域(或遮光区域)的面积较大，可以降低掩膜版的精度要求，降低工艺难度。在具体设置时，可以将第一半导体层、发光层和第二半导体层的总厚度设置为小于8μm。
在一种可能的实现方式中，第一反射层可以覆盖第一半导体层、发光层和第二半导体层的侧面。这样，第一反射层可以覆盖大部分甚至整个外延层的侧面，第一反射层覆盖的面积较大，因而，第一反射层可以反射更多的光线，使光线无法从侧面出射，并且，光线经第一反射层多次反射后可以朝向法向出射，进一步减小了微型发光二极管芯片的发光角，并进一步提升了法向亮度。第一半导体层、发光层和第二半导体层均具有倾斜的侧面，为后续在外延层的侧面形成第一反射层提供了必要条件。在制作工艺过程中，第一反射层的材料可以有效附着在外延层的侧面，使制作得到的第一反射层的厚度均一性较好。
在一种可能的实现方式中，上述微型发光二极管芯片还可以包括：钝化层，钝化层位 于第一半导体层远离发光层的一侧，钝化层可以对第一半导体层起到保护作用。
在另一种可能的实现方式中，上述微型发光二极管芯片还可以包括：位于第一半导体层远离发光层一侧的第二反射层。第二反射层可以反射发光层朝向第一半导体层出射的光线，第二反射层反射的大部分光线经第一半导体层和第二半导体层的汇聚后可以从法向出射，对于第二反射层反射的偏离法向角度较大的光线，可以被第一反射层反射回外延层内部，经多次反射和汇聚后也可以从法向出射。因此，本申请实施例中，通过设置第二反射层可以进一步增大法向亮度，并且，第二反射层也可以对第一半导体层起到保护作用。
在具体实施时，第二反射层可以包括具有高反射率的薄膜材料，例如，第二反射层可以为分布式布拉格反射层(distributed bragg reflection，DBR)，分布式布拉格反射层是一种不导电的反射层，可以使第二反射层与第一半导体层保持绝缘。或者，第二反射层也可以为绝缘层-金属层-绝缘层的叠层结构，例如，该绝缘层可以包括二氧化硅等透明材料。当然，第二反射层也可以采用其他结构或材料，此处不做限定。
在本申请的另一些实施例中，在第一半导体层指向第二半导体层的方向上，发光层和第一半导体层在平行于第二表面的方向上的各截面面积一致，可以理解的是，此处各截面面积一致指的是：各截面面积在一定误差范围内基本一致。在具体设置时，可以将第二半导体层的厚度设置为小于5μm。第一半导体层和发光层的边缘近似竖直，可以使发光层的侧面的面积较小，从而，可以减少发光层侧面的漏电现象。在制作工艺过程层中，可以采用两次图形化工艺对外延层进行图形化，例如，可以先对第一半导体层和发光层进行图形化，然后将微型发光二极管芯片翻面后，再对第二半导体层进行图形化，这样，可以使每次图形化工艺的刻蚀深度较小，降低图形化工艺的难度。第一反射层可以仅覆盖第二半导体层的侧面。第一反射层可以反射朝向微型发光二极管芯片侧面出射的光线，从而可以减少从侧面出射的光线，并且，第一反射层可以将光线反射回微型发光二极管芯片的内部，使这部分光线经多次反射后可以朝向法向出射，从而可以有效约束微型发光二极管芯片的发光角，并进一步提升法向亮度。
在一种可能的实现方式中，本申请实施例中的微型发光二极管芯片还可以包括：钝化层，钝化层位于第一半导体层远离发光层的一侧，且钝化层包裹发光层和第一半导体层的侧面。钝化层可以对第一半导体层起到保护作用，并且，钝化层包裹发光层的侧面，可以进一步减少发光层的漏电现象。
在另一种可能的实现方式中，本申请实施例中的微型发光二极管芯片还可以包括：位于第一半导体层远离发光层一侧的第二反射层。第二反射层可以反射发光层朝向第一半导体层出射的光线，第二反射层反射的大部分光线经第一半导体层和第二半导体层的汇聚后可以从法向出射，对于第二反射层反射的偏离法向角度较大的光线，可以被第一反射层反射回外延层内部，经多次反射和汇聚后也可以从法向出射。因此，本申请实施例中，通过设置第二反射层可以进一步增大法向亮度，并且，第二反射层也可以对第一半导体层起到保护作用。此外，可以将第二反射层设置为包裹发光层和第一半导体层的侧面，因而，通过第二反射层包裹发光层的侧面，可以进一步减少发光层的漏电现象。
在具体实施时，第二反射层可以包括具有高反射率的薄膜材料，例如，第二反射层可以为分布式布拉格反射层(distributed bragg reflection，DBR)，分布式布拉格反射层是一种不导电的反射层，可以使第二反射层与第一半导体层和发光层保持绝缘。或者，第二反射层也可以为绝缘层-金属层-绝缘层的叠层结构，例如，该绝缘层可以包括二氧化硅等透明 材料。当然，第二反射层也可以采用其他结构或材料，此处不做限定。
在本申请实施例中，微型发光二极管芯片的出光面可以位于第二半导体层远离发光层的一侧，第一反射层可以覆盖第二表面的边缘，以在出光面形成出光孔径，该出光孔径的面积小于第二表面的面积，因而，该出光孔径可以约束光斑，可以有效控制光斑的形状和大小，使微型发光二极管芯片的光斑可控。将微型发光二极管芯片应用于显示设备时，可以提高显示效果。在具体实施时，可以根据实际需要，对覆盖第二表面的第一反射层进行图形化，以改变出光孔径的尺寸和形状。举例来说，出光孔径的形状可以为方形、圆形或多边形等，当然，出光孔径也可以为其他形状，此处不做限定。
在一种可能的实现方式中，为了使微型发光二极管芯片的出光效率较高，可以将出光孔径的几何中心设置为与发光层的几何中心基本对齐。
在本申请的一些实施例中，为了实现第二电极与第二半导体层之间的电连接，微型发光二极管芯片可以采用台面结构，即可以将第一半导体层和发光层对应于第二电极的部分去除，使第二电极可以直接与第二半导体层电连接。发光层的图形位于第二电极以外的区域，可以将出光孔径也设置于对应于第二电极以外的区域，以使出光孔径的几何中心与发光层的几何中心基本对齐，从而提高微型发光二极管芯片的出光效率。然而，由于第一半导体层和发光层具有台面结构，在对应于第二电极的位置处，第一半导体层的第三表面与第二半导体层的第一表面之间具有很大的高度差，导致后续涂布的膜层的厚度均一性较差，并且，第二电极与第一半导体层和发光层的边缘之间具有间隙，该间隙中容易残留工艺过程中的胶水等异物，此外，在后续工艺过程中，有一些工艺需要向微型发光二极管芯片施加压力，微型发光二极管芯片容易在该间隙处断裂。
在本申请的另一些实施例中，微型发光二极管芯片还可以包括：贯穿第一半导体层和发光层的通孔，第二电极通过通孔与第二半导体层电连接，这样，无需挖掉大面积的发光层，可以减少发光层中有源区域的面积损失，可以最大程度的利用发光层的面积，明显提升法向亮度，提升微型发光二极管芯片的发光效率。第二电极与第一半导体层和发光层之间设有绝缘隔离层，第二电极通过绝缘隔离层与第一半导体层和发光层绝缘，从而，可以使第二电极与第一半导体层和发光层之间保持绝缘。第二电极通过通孔与第二半导体层电连接，第二电极与第一半导体层和发光层的边缘之间没有间隙，这样，在工艺过程中不会残留胶水等异物，并且，向微型发光二极管芯片施加压力时，微型发光二极管芯片不容易断裂，从而提高了微型发光二极管芯片的可靠性。此外，在制作工艺过程中，可以先采用第二电极的材料填充通孔，使得第一半导体层的第三表面的平整性较好，后续涂布的膜层(例如钝化层或第二反射层等膜层)的厚度均一性较好，使工艺制程更稳定可控，并且，在形成第一电极和剩余的第二电极之前的表面较平坦，降低了工艺难度，提高了产品良率。
在制作工艺过程中，可以采用离子注入的方式，在第一半导体层和发光层中形成高阻区，高阻区的位置对应于将要形成的第二电极的位置，举例来说，可以向第一半导体层和发光层中注入氮元素或氢元素等，以改变第一半导体层和发光层中的晶格结构，使第一半导体层和发光层在高阻区绝缘化。然后，对第一半导体层和发光层进行刻蚀，以在高阻区形成贯穿第一半导体层和发光层的通孔，并在通孔周围形成绝缘隔离层，即绝缘隔离层是高阻区中去除通孔之后得到的。之后，形成第一电极和第二电极，第二电极填充通孔，且第二电极通过绝缘隔离层与第一半导体层和发光层绝缘。本申请实施例中，采用离子注入的方式在第一半导体层和发光层中形成高阻区，并在高阻区内形成通孔，以实现第二电极 与第二半导体层之间的电连接，不会直接刻蚀第一半导体层和发光层，对第一半导体层和发光层的损伤较小，不会影响微型发光二极管芯片的发光效率。
在具体实施时，绝缘隔离层也可以采用其他绝缘材料制作，例如，绝缘隔离层可以采用SiO2、SiN、Al2O3等绝缘材料制作。在制作工艺过程中，可以在对应于将要形成的第二电极的位置形成尺寸大于通孔的开孔，然后，在该开孔中填充绝缘材料，对该开孔中的绝缘材料进行刻蚀形成通孔，并在通孔周围形成绝缘隔离层，即绝缘隔离层是开孔中的绝缘材料去除通孔之后得到的。之后，形成第一电极和第二电极，第二电极填充通孔，且第二电极通过绝缘隔离层与第一半导体层和发光层绝缘。
在一种可能的实现方式中，第二半导体层在第一表面设有与通孔位置对应的凹槽，部分第二电极位于凹槽内。在形成通孔的过程中，可以刻蚀第一半导体层、发光层以及部分第二半导体层，以形成贯穿第一半导体层和发光层的通孔，并在第二半导体层的第一表面形成与通孔对应的凹槽，这样，可以保证后续形成的第二电极能够与第二半导体层实现电连接，提高工艺良率。当然，本申请的一些实施例中，在形成通孔的过程中，也可以仅刻蚀第一半导体层和发光层，以漏出第二半导体层的第一表面，只要保证第二电极与第二半导体层能够实现电连接即可。
第二方面，本申请实施例还提供了一种显示面板，显示面板可以包括：上述任一微型发光二极管芯片以及衬底基板，微型发光二极管芯片位于衬底基板之上。在具体实施时，为了驱动微型发光二极管芯片发光，可以在衬底基板的表面形成驱动电路，微型发光二极管芯片可以通过焊点1与衬底基板表面的驱动电路实现电连接。在实际工艺过程中，大量的微型发光二极管芯片可以通过巨量转移的方式实现批量转移，之后通过绑定(Bonding)将微型发光二极管芯片固定于衬底基板之上。
由于本申请实施例中的微型发光二极管芯片的光能利用率较高，因而包括上述任一微型发光二极管芯片的显示面板的显示效果较好。
第三方面，本申请实施例还提供了一种电子设备，该电子设备可以包括：上述任一显示面板以及壳体，壳体包裹显示面板，也就是说，本申请实施例中的微型发光二极管芯片可以作为显示像素，应用于各种显示类的电子设备中，例如，电子设备可以为手机、手表、电脑等显示产品。
或者，电子设备包括：上述任一微型发光二极管芯片，在一些应用场景中，微型发光二极管芯片也可作为像素化的阵列式光源，以应用于感光、投影、光通信、打印等领域，即电子设备也可以为感光设备、投影设备、光通信设备、打印设备或照明设备等。
由于上述微型发光二极管芯片的光能利用率较高，因而包括上述任一微型发光二极管芯片的电子设备的性能较好。
第四方面，本申请实施例还提供了一种微型发光二极管芯片的制作方法，微型发光二极管芯片的制作方法可以包括：
在衬底之上依次形成第二半导体层、发光层和第一半导体层；
在第一半导体层远离发光层的一侧形成与第一半导体层电连接的第一电极，在第二半导体层靠近第一发光层的一侧形成与第二半导体层电连接的第二电极；
将形成第一电极和第二电极后的结构具有第一电极的一面键合于第一基板上，剥离衬底；
对第二半导体层进行处理，以使第二半导体层的第二表面在第一表面所在平面上的正 投影位于第一表面的范围内；第一表面为第二半导体层靠近发光层一侧的表面，第二表面为第二半导体层远离发光层一侧的表面。
本申请实施例提供的微型发光二极管芯片的制作方法中，通过对第二半导体层进行处理，以使第二半导体层的第二表面在第一表面所在平面上的正投影位于第一表面的范围内，可以使第二半导体层等效为微透镜，这样可以利用微型发光二极管芯片自身的结构形成微透镜，微透镜可以对发光层出射的光线进行汇聚，从而减小微型发光二极管芯片的发光角，并提高微型发光二极管芯片的法向亮度。并且，微型发光二极管芯片的尺寸基本不变，不会影响微型发光二极管芯片的有源区面积，因而不会影响微型发光二极管芯片的发光效率。因此，可以提高微型发光二极管芯片的光能利用率。此外，本申请实施例中，利用微型发光二极管芯片自身的结构形成微透镜，无需额外增加其他部件，在制作工艺过程中，可以通过调整第二半导体层图形化工艺的参数，就能够得到第二半导体层的结构，制作工艺较简单，不会增加制作成本。
由于本申请实施例中的微型二极管芯片的制作方法解决问题的原理与上述微型发光二极管芯片解决问题的原理相似，因此，该制作方法的实施可以参照上述微型发光二极管芯片的实施，重复之处不再赘述。
附图说明
图1为本申请实施例提供的微型发光二极管芯片的结构示意图；
图2为本申请实施例提供的微型发光二极管芯片的另一结构示意图；
图3为本申请实施例提供的微型发光二极管芯片的另一结构示意图；
图4为本申请实施例提供的微型发光二极管芯片的另一结构示意图；
图5为本申请实施例提供的微型发光二极管芯片的另一结构示意图；
图6为本申请实施例提供的微型发光二极管芯片的另一结构示意图；
图7为本申请实施例提供的显示面板的结构示意图；
图8为本申请实施例提供的微型发光二极管芯片的制作方法流程图；
图9至图16为本申请实施例提供的微型发光二极管芯片的制作方法中各步骤对应的结构示意图。
附图标记：
10-微型发光二极管芯片；11-第一半导体层；12-第二半导体层；13-发光层；14-第一电极；15-第二电极；16-第一反射层；17-钝化层；18-第二反射层；19-绝缘隔离层；20-衬底基板；401-衬底；402-第一基板；403-牺牲层；404-第一键合层；405-第二键合层；406-第二基板；S1-第一表面；S2-第二表面；S3-第三表面；S4-第四表面；T-通孔；U-凹槽；W-间隙；Q-高阻区。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
应注意的是，本申请的附图中相同的附图标记表示相同或类似的结构，因而将省略对它们的重复描述。本申请中所描述的表达位置与方向的词，均是以附图为例进行的说明， 但根据需要也可以做出改变，所做改变均包含在本申请保护范围内。本申请的附图仅用于示意相对位置关系不代表真实比例。
为了解决微型发光二极管芯片的发光角较大、法向亮度较低，导致微型发光二极管芯片的光能利用率较低的问题。本申请实施例提供了一种微型发光二极管芯片、其制作方法、显示面板及电子设备。微型发光二极管芯片可以为Micro LED，此外，微型发光二极管芯片也可以为Mini LED或其他尺寸的发光二极管芯片，此处不做限定。本申请实施例中的微型发光二极管芯片可以应用于各种电子设备中，例如，微型发光二极管芯片可以作为显示像素，应用于各种显示类的电子设备中，例如，电子设备可以为手机、手表、电脑等显示产品，或者，微型发光二极管芯片可作为像素化的阵列式光源，以应用于感光、投影、光通信、打印等领域，即电子设备也可以为感光设备、投影设备、光通信设备、打印设备或照明设备等。
图1为本申请实施例提供的微型发光二极管芯片的结构示意图，如图1所示，本申请实施例提供的微型发光二极管芯片可以包括：第一半导体层11，第二半导体层12，位于第一半导体层11与第二半导体层12之间的发光层13，第一电极14，以及第二电极15。第一电极14位于第一半导体层11远离发光层13的一侧，第二电极15位于第二半导体层12靠近发光层13的一侧，第一电极14与第一半导体层11电连接，第二电极15与第二半导体层12电连接。
在微型发光二极管芯片中，发光层13位于第一半导体层11和第二半导体层12之间，第一半导体层11和第二半导体层12可以包括不同类型的半导体材料，使第一半导体层11和第二半导体层12可以分别提供不同类型的载流子，例如，第一半导体层11可以提供电子，第二半导体层12可以提供空穴，或者，第一半导体层11可以提供空穴，第二半导体层12可以提供电子。第一电极14与第一半导体层11电连接，第二电极15与第二半导体层12电连接，向第一电极14和第二电极15施加电压时，可以驱动电子和空穴移动，使电子和空穴在发光层13中复合发光。在具体实施时，发光层13可以为多量子阱，从而提高发光层13的发光效率。在本申请实施例中，第一电极14位于第一半导体层11远离发光层13的一侧，第二电极15位于第二半导体层12靠近发光层13的一侧，即第一电极14和第二电极15位于微型发光二极管芯片的同一侧，这样，将本申请实施例中的微型发光二极管芯片应用于显示面板或电子设备中，便于将微型发光二极管芯片绑定于衬底基板上。
在本申请实施例中，第二半导体层12具有相对设置的第一表面S1和第二表面S2，第一表面S1为第二半导体层12靠近发光层13一侧的表面，第二表面S2为第二半导体层12远离发光层13一侧的表面，第二表面S2在第一表面S1所在平面上的正投影位于第一表面S1的范围内。也就是说，第二半导体层12的第二表面S2的面积小于第一表面S1的面积，并且，第二表面S2在第一表面S1所在平面上的正投影未超出第一表面S1的范围。这样设置，可以使第二半导体层12具有倾斜的侧面，从而使第二半导体层12等效为微透镜，微透镜可以对发光层13出射的光线进行汇聚。
本申请实施例提供的微型发光二极管芯片中，通过将第二半导体层设置为第二表面在第一表面所在平面上的正投影位于第一表面的范围内，可以使第二半导体层等效为微透镜，这样可以利用微型发光二极管芯片自身的结构形成微透镜，微透镜可以对发光层出射的光线进行汇聚，从而减小微型发光二极管芯片的发光角，并提高微型发光二极管芯片的法向亮度。并且，微型发光二极管芯片的尺寸基本不变，不会影响微型发光二极管芯片的有源 区面积，因而不会影响微型发光二极管芯片的发光效率。因此，可以提高微型发光二极管芯片的光能利用率。此外，本申请实施例中，利用微型发光二极管芯片自身的结构形成微透镜，无需额外增加其他部件，在制作工艺过程中，可以通过调整第二半导体层图形化工艺的参数，就能够得到第二半导体层的结构，制作工艺较简单，不会增加制作成本。
继续参照图1，在本申请的一些实施例中，在第一半导体层11指向第二半导体层12的方向(例如图中箭头F1所示的方向)上，第二半导体层12在平行于第二表面S2的方向上的截面面积呈逐渐减小的趋势，也就是说，在第一半导体层11指向第二半导体层12的方向上，第二半导体层12呈渐缩状。第二半导体层12在垂直于第二表面S2的方向上的截面(例如图1所示的截面)的形状可以为梯形。在具体实施时，第二半导体层12的侧面与第一表面S1之间的夹角可以设置为在30°～85°的范围内，优选为在40°～60°的范围内，这样，可以使第二半导体层12对光线的汇聚效果更好，使微型发光二极管芯片的法向亮度较高。在本申请的另一些实施例中，第二半导体层12的侧面也可以为其他形状，只要满足第二半导体层12中第二表面S2在第一表面S1所在平面上的正投影位于第一表面S1的范围内即可。例如，第二半导体层12的侧面可以具有一定的弧度，举例来说，在第一半导体层11指向第二半导体层12的方向上，第二半导体层12在平行于第二表面S2的方向上的截面面积可以呈逐渐先增大后减小(或者先减小后增大)的趋势。
图2为本申请实施例提供的微型发光二极管芯片的另一结构示意图，如图2所示，本申请实施例中的微型发光二极管芯片还可以包括：第一反射层16，第一反射层16至少覆盖第二半导体层12的部分侧面。第一反射层16可以反射朝向微型发光二极管芯片侧面出射的光线，从而可以减少从侧面出射的光线，并且，第一反射层16可以将光线反射回微型发光二极管芯片的内部，使这部分光线经多次反射后可以朝向法向出射，从而可以有效约束微型发光二极管芯片的发光角(例如，可以使微型发光二极管芯片的发光角小于120°)，并进一步提升法向亮度。
本申请实施例中，通过将第二半导体层12设置为第二表面S2在第一表面S1所在平面上的正投影位于第一表面S1的范围内，使第二半导体层12具有倾斜的侧面，为后续在第二半导体层12的侧面形成第一反射层16提供了必要条件。在制作工艺过程中，可以使第一反射层16的材料有效附着在第二半导体层12的侧面，使制作得到的第一反射层16的厚度均一性较好。
在具体实施时，第一反射层16可以包括具有高反射率的薄膜材料，例如，第一反射层16可以为分布式布拉格反射层(distributed bragg reflection，DBR)，分布式布拉格反射层是一种不导电的反射层，可以使第一反射层16与第二半导体层12保持绝缘。或者，第一反射层16也可以为绝缘层-金属层-绝缘层的叠层结构，例如，该绝缘层可以包括二氧化硅等透明材料。当然，第一反射层16也可以采用其他结构或材料，此处不做限定。在实际工艺过程中，可以采用蒸镀或者薄膜生长工艺制作第一反射层16。
在本申请的一些实施例中，如图2所示，第一半导体层11具有相对设置的第三表面S3和第四表面S4，第三表面S3为第一半导体层11远离发光层13一侧的表面，第四表面S4为第一半导体层11靠近发光层13一侧的表面，第四表面S4在第三表面S3所在平面上的正投影位于第三表面S3的范围内。也就是说，第一半导体层11的第四表面S4的面积小于第三表面S3的面积，并且，第四表面S4在第三表面S3所在平面上的正投影未超出第三表面S3的范围。这样设置，可以使第一半导体层11也具有倾斜的侧面，从而使第一 半导体层11等效为微透镜，微透镜可以对光线进行汇聚。
在具体实施时，在第一半导体层11指向第二半导体层12的方向(例如图中箭头F1所示的方向)上，第一半导体层11在平行于第四表面S4的方向上的截面面积呈逐渐减小的趋势，也就是说，在第一半导体层11指向第二半导体层12的方向上，第一半导体层11呈渐缩状。第一半导体层11在垂直于第四表面S4的方向上的截面(例如图2所示的截面)的形状可以为梯形，这样，可以使第一半导体层11的汇聚效果较好。在具体实施时，第一半导体层11的侧面与第三表面S3之间的夹角可以设置为在30°～85°的范围内，优选为在40°～60°的范围内，这样，可以使第一半导体层11对光线的汇聚效果更好。当然，第一半导体层11的侧面也可以为其他形状，只要满足第四表面S4在第三表面S3所在平面上的正投影位于第三表面S3的范围内即可。例如，第一半导体层11的侧面可以具有一定的弧度，举例来说，在第一半导体层11指向第二半导体层12的方向上，第一半导体层11在平行于第四表面S4的方向上的截面面积可以呈逐渐先增大后减小(或者先减小后增大)的趋势。
在实际应用中，可以将发光层13也设置为具有倾斜的侧面，即发光层13靠近第二半导体层12一侧的表面在第四表面S4上的正投影，可以位于发光层13靠近第一半导体层11一侧的表面在第四表面S4上的正投影。这样设置，可以使外延层(外延层包括第一半导体层11、第二半导体层12和发光层13)整体具有倾斜的侧面。在制作工艺过程中，可以对第二半导体层12、发光层13和第一半导体层11一起进行图形化，相比于分别图形化可以减少图形化的次数，降低制作工艺成本，并且，图形化工艺的掩膜版的开口区域(或遮光区域)对应于整个外延层的区域，开口区域(或遮光区域)的面积较大，可以降低掩膜版的精度要求，降低工艺难度。在具体设置时，可以将第一半导体层11、发光层13和第二半导体层12的总厚度设置为小于8μm。
继续参照图2，第一反射层16可以覆盖第一半导体层11、发光层13和第二半导体层12的侧面。这样，第一反射层16可以覆盖大部分甚至整个外延层的侧面，第一反射层16覆盖的面积较大，因而，第一反射层16可以反射更多的光线，使光线无法从侧面出射，并且，光线经第一反射层16多次反射后可以朝向法向出射，进一步减小了微型发光二极管芯片的发光角，并进一步提升了法向亮度。第一半导体层11、发光层13和第二半导体层12均具有倾斜的侧面，为后续在外延层的侧面形成第一反射层16提供了必要条件。在制作工艺过程中，第一反射层16的材料可以有效附着在外延层的侧面，使制作得到的第一反射层16的厚度均一性较好。
在一种可能的实现方式中，如图2所示，上述微型发光二极管芯片还可以包括：钝化层17，钝化层17位于第一半导体层11远离发光层13的一侧，钝化层17可以对第一半导体层11起到保护作用。
图3为本申请实施例提供的微型发光二极管芯片的另一结构示意图，如图3所示，在另一种可能的实现方式中，上述微型发光二极管芯片还可以包括：位于第一半导体层11远离发光层13一侧的第二反射层18。第二反射层18可以反射发光层13朝向第一半导体层11出射的光线，第二反射层18反射的大部分光线经第一半导体层11和第二半导体层12的汇聚后可以从法向出射，对于第二反射层18反射的偏离法向角度较大的光线，可以被第一反射层16反射回外延层内部，经多次反射和汇聚后也可以从法向出射。因此，本申请实施例中，通过设置第二反射层18可以进一步增大法向亮度，并且，第二反射层18 也可以对第一半导体层11起到保护作用。
继续参照图3，第二反射层18可以包括具有高反射率的薄膜材料，例如，第二反射层18可以为分布式布拉格反射层(distributed bragg reflection，DBR)，分布式布拉格反射层是一种不导电的反射层，可以使第二反射层18与第一半导体层11保持绝缘。或者，第二反射层18也可以为绝缘层-金属层-绝缘层的叠层结构，例如，该绝缘层可以包括二氧化硅等透明材料。当然，第二反射层18也可以采用其他结构或材料，此处不做限定。
在本申请的另一些实施例中，如图4所示，图4为本申请实施例提供的微型发光二极管芯片的另一结构示意图，在第一半导体层11指向第二半导体层12的方向(例如图中箭头F1所示的方向)上，发光层13和第一半导体层11在平行于第二表面S2的方向上的各截面面积一致，可以理解的是，此处各截面面积一致指的是：各截面面积在一定误差范围内基本一致。也就是说，在图4所示的实施例中，仅第二半导体层12具有倾斜的侧面，在具体设置时，可以将第二半导体层12的厚度设置为小于5μm。第一半导体层11和发光层13的边缘近似竖直，可以使发光层13的侧面的面积较小，从而，可以减少发光层13侧面的漏电现象。在制作工艺过程层中，可以采用两次图形化工艺对外延层进行图形化，例如，可以先对第一半导体层11和发光层13进行图形化，然后将微型发光二极管芯片翻面后，再对第二半导体层12进行图形化，这样，可以使每次图形化工艺的刻蚀深度较小，降低图形化工艺的难度。
继续参照图4，第一反射层16可以仅覆盖第二半导体层12的侧面。第一反射层16可以反射朝向微型发光二极管芯片侧面出射的光线，从而可以减少从侧面出射的光线，并且，第一反射层16可以将光线反射回微型发光二极管芯片的内部，使这部分光线经多次反射后可以朝向法向出射，从而可以有效约束微型发光二极管芯片的发光角，并进一步提升法向亮度。
在一种可能的实现方式中，本申请实施例中的微型发光二极管芯片还可以包括：钝化层17，钝化层17位于第一半导体层11远离发光层13的一侧，且钝化层17包裹发光层13和第一半导体层11的侧面。钝化层17可以对第一半导体层11起到保护作用，并且，钝化层17包裹发光层13的侧面，可以进一步减少发光层13的漏电现象。
在另一种可能的实现方式中，如图5所示，图5为本申请实施例提供的微型发光二极管芯片的另一结构示意图，本申请实施例中的微型发光二极管芯片还可以包括：位于第一半导体层11远离发光层13一侧的第二反射层18。第二反射层18可以反射发光层13朝向第一半导体层11出射的光线，第二反射层18反射的大部分光线经第一半导体层11和第二半导体层12的汇聚后可以从法向出射，对于第二反射层18反射的偏离法向角度较大的光线，可以被第一反射层16反射回外延层内部，经多次反射和汇聚后也可以从法向出射。因此，本申请实施例中，通过设置第二反射层18可以进一步增大法向亮度，并且，第二反射层18也可以对第一半导体层11起到保护作用。此外，可以将第二反射层18设置为包裹发光层13和第一半导体层11的侧面，因而，通过第二反射层18包裹发光层13的侧面，可以进一步减少发光层13的漏电现象。
继续参照图5，第二反射层18可以包括具有高反射率的薄膜材料，例如，第二反射层18可以为分布式布拉格反射层(distributed bragg reflection，DBR)，分布式布拉格反射层是一种不导电的反射层，可以使第二反射层18与第一半导体层11和发光层13保持绝缘。或者，第二反射层18也可以为绝缘层-金属层-绝缘层的叠层结构，例如，该绝缘层可以包 括二氧化硅等透明材料。当然，第二反射层18也可以采用其他结构或材料，此处不做限定。
如图2至图5所示，在本申请实施例中，微型发光二极管芯片的出光面可以位于第二半导体层12远离发光层13的一侧，第一反射层16可以覆盖第二表面S2的边缘，以在出光面形成出光孔径，该出光孔径的面积小于第二表面S2的面积，因而，该出光孔径可以约束光斑，可以有效控制光斑的形状和大小，使微型发光二极管芯片的光斑可控。将微型发光二极管芯片应用于显示设备时，可以提高显示效果。在具体实施时，可以根据实际需要，对覆盖第二表面S2的第一反射层16进行图形化，以改变出光孔径的尺寸和形状。举例来说，出光孔径的形状可以为方形、圆形或多边形等，当然，出光孔径也可以为其他形状，此处不做限定。
在一种可能的实现方式中，为了使微型发光二极管芯片的出光效率较高，可以将出光孔径的几何中心设置为与发光层13的几何中心基本对齐。
图6为本申请实施例提供的微型发光二极管芯片的另一结构示意图，如图6所示，在本申请的一些实施例中，为了实现第二电极15与第二半导体层12之间的电连接，微型发光二极管芯片可以采用台面结构，即可以将第一半导体层11和发光层13对应于第二电极15的部分去除，使第二电极15可以直接与第二半导体层12电连接。在图6所示的结构中，发光层13的图形位于第二电极15以外的区域，即发光层13的图形位于图6中靠左的区域中，可以将出光孔径也设置于对应于第二电极15以外的区域，例如图6中出光孔径位于靠左的区域中，以使出光孔径的几何中心与发光层13的几何中心基本对齐，从而提高微型发光二极管芯片的出光效率。
然而，在图6所示的结构中，由于第一半导体层11和发光层13具有台面结构，在对应于第二电极15的位置处，第一半导体层11的第三表面S3与第二半导体层12的第一表面S1之间具有很大的高度差，导致后续涂布的膜层的厚度均一性较差，并且，第二电极15与第一半导体层11和发光层13的边缘之间具有间隙W，该间隙W中容易残留工艺过程中的胶水等异物，此外，在后续工艺过程中，有一些工艺需要向微型发光二极管芯片施加压力，微型发光二极管芯片容易在该间隙W处断裂。
在本申请的另一些实施例中，如图1至图5所示，微型发光二极管芯片还可以包括：贯穿第一半导体层11和发光层13的通孔T，第二电极15通过通孔T与第二半导体层12电连接，这样，无需挖掉大面积的发光层13，可以减少发光层13中有源区域的面积损失，可以最大程度的利用发光层13的面积，明显提升法向亮度，提升微型发光二极管芯片的发光效率。第二电极15与第一半导体层11和发光层13之间设有绝缘隔离层19，第二电极15通过绝缘隔离层19与第一半导体层11和发光层13绝缘，从而，可以使第二电极15与第一半导体层11和发光层13之间保持绝缘。
对比图5和图6可以明显看出，在图5所示的结构中，第二电极15通过通孔T与第二半导体层12电连接，第二电极15与第一半导体层11和发光层13的边缘之间没有间隙，这样，在工艺过程中不会残留胶水等异物，并且，向微型发光二极管芯片施加压力时，微型发光二极管芯片不容易断裂，从而提高了微型发光二极管芯片的可靠性。此外，在制作工艺过程中，可以先采用第二电极15的材料填充通孔T，使得第一半导体层11的第三表面S3的平整性较好，后续涂布的膜层(例如钝化层或第二反射层等膜层)的厚度均一性较好，使工艺制程更稳定可控，并且，在形成第一电极14和剩余的第二电极15之前的表 面较平坦，降低了工艺难度，提高了产品良率。
对比图5和图6所示的结构，图5所示的结构中发光层13的有效面积更大，发光层13的几何中心更靠近微型发光二极管芯片整体的中心位置，将出光孔径的几何中心设置为与发光层13的几何中心基本对齐，可以使微型发光二极管芯片出射的光线更集中于中心位置，使微型发光二极管芯片的发光效率较高。
在制作工艺过程中，可以采用离子注入的方式，在第一半导体层11和发光层13中形成高阻区，高阻区的位置对应于将要形成的第二电极15的位置，举例来说，可以向第一半导体层11和发光层13中注入氮元素或氢元素等，以改变第一半导体层11和发光层13中的晶格结构，使第一半导体层11和发光层13在高阻区绝缘化。然后，对第一半导体层11和发光层13进行刻蚀，以在高阻区形成贯穿第一半导体层11和发光层13的通孔T，并在通孔T周围形成绝缘隔离层19，即绝缘隔离层19是高阻区中去除通孔T之后得到的。之后，形成第一电极14和第二电极15，第二电极15填充通孔T，且第二电极15通过绝缘隔离层19与第一半导体层11和发光层13绝缘。本申请实施例中，采用离子注入的方式在第一半导体层11和发光层13中形成高阻区，并在高阻区内形成通孔T，以实现第二电极15与第二半导体层12之间的电连接，不会直接刻蚀第一半导体层11和发光层13，对第一半导体层11和发光层13的损伤较小，不会影响微型发光二极管芯片的发光效率。
在具体实施时，绝缘隔离层19也可以采用其他绝缘材料制作，例如，绝缘隔离层19可以采用SiO2、SiN、Al2O3等绝缘材料制作。在制作工艺过程中，可以在对应于将要形成的第二电极15的位置形成尺寸大于通孔T的开孔，然后，在该开孔中填充绝缘材料，对该开孔中的绝缘材料进行刻蚀形成通孔T，并在通孔T周围形成绝缘隔离层19，即绝缘隔离层19是开孔中的绝缘材料去除通孔T之后得到的。之后，形成第一电极14和第二电极15，第二电极15填充通孔T，且第二电极15通过绝缘隔离层19与第一半导体层11和发光层13绝缘。
继续参照图1至图5，第二半导体层12在第一表面S1设有与通孔T位置对应的凹槽U，部分第二电极15位于凹槽U内。在形成通孔T的过程中，可以刻蚀第一半导体层11、发光层13以及部分第二半导体层12，以形成贯穿第一半导体层11和发光层13的通孔T，并在第二半导体层12的第一表面S1形成与通孔T对应的凹槽U，这样，可以保证后续形成的第二电极15能够与第二半导体层12实现电连接，提高工艺良率。当然，本申请的一些实施例中，在形成通孔T的过程中，也可以仅刻蚀第一半导体层11和发光层13，以漏出第二半导体层12的第一表面S1，只要保证第二电极15与第二半导体层12能够实现电连接即可。
基于同一技术构思，本申请实施例还提供了一种显示面板，图7为本申请实施例提供的显示面板的结构示意图，如图7所示，显示面板可以包括：上述任一微型发光二极管芯片10以及衬底基板20，微型发光二极管芯片10位于衬底基板20之上。在具体实施时，为了驱动微型发光二极管芯片发光，可以在衬底基板20的表面形成驱动电路，微型发光二极管芯片可以通过焊点201与衬底基板20表面的驱动电路实现电连接。在实际工艺过程中，大量的微型发光二极管芯片可以通过巨量转移的方式实现批量转移，之后通过绑定(Bonding)将微型发光二极管芯片10固定于衬底基板20之上。
由于本申请实施例中的微型发光二极管芯片的光能利用率较高，因而包括上述任一微型发光二极管芯片的显示面板的显示效果较好。
基于同一技术构思，本申请实施例还提供了一种电子设备，该电子设备可以包括：上述任一显示面板以及壳体，壳体包裹显示面板，也就是说，本申请实施例中的微型发光二极管芯片可以作为显示像素，应用于各种显示类的电子设备中，例如，电子设备可以为手机、手表、电脑等显示产品。
或者，电子设备包括：上述任一微型发光二极管芯片，在一些应用场景中，微型发光二极管芯片也可作为像素化的阵列式光源，以应用于感光、投影、光通信、打印等领域，即电子设备也可以为感光设备、投影设备、光通信设备、打印设备或照明设备等。
由于上述微型发光二极管芯片的光能利用率较高，因而包括上述任一微型发光二极管芯片的电子设备的性能较好。
基于同一技术构思，本申请实施例还提供了一种微型发光二极管芯片的制作方法，图8为本申请实施例提供的微型发光二极管芯片的制作方法流程图，如图8所示，微型发光二极管芯片的制作方法可以包括：
S301、在衬底之上依次形成第二半导体层、发光层和第一半导体层；
S302、在第一半导体层远离发光层的一侧形成与第一半导体层电连接的第一电极，在第二半导体层靠近第一发光层的一侧形成与第二半导体层电连接的第二电极；
S303、将形成第一电极和第二电极后的结构具有第一电极的一面键合于第一基板上，剥离衬底；
S304、对第二半导体层进行处理，以使第二半导体层的第二表面在第一表面所在平面上的正投影位于第一表面的范围内；第一表面为第二半导体层靠近发光层一侧的表面，第二表面为第二半导体层远离发光层一侧的表面。
本申请实施例提供的微型发光二极管芯片的制作方法中，通过对第二半导体层进行处理，以使第二半导体层的第二表面在第一表面所在平面上的正投影位于第一表面的范围内，可以使第二半导体层等效为微透镜，这样可以利用微型发光二极管芯片自身的结构形成微透镜，微透镜可以对发光层出射的光线进行汇聚，从而减小微型发光二极管芯片的发光角，并提高微型发光二极管芯片的法向亮度。并且，微型发光二极管芯片的尺寸基本不变，不会影响微型发光二极管芯片的有源区面积，因而不会影响微型发光二极管芯片的发光效率。因此，可以提高微型发光二极管芯片的光能利用率。此外，本申请实施例中，利用微型发光二极管芯片自身的结构形成微透镜，无需额外增加其他部件，在制作工艺过程中，可以通过调整第二半导体层图形化工艺的参数，就能够得到第二半导体层的结构，制作工艺较简单，不会增加制作成本。
图9至图16为本申请实施例提供的微型发光二极管芯片的制作方法中各步骤对应的结构示意图，以下结合图9至图16，对本申请实施例提供的微型发光二极管芯片的制作方法进行详细说明。
在上述步骤S301中，如图9所示，在衬底401之上依次形成第二半导体层12、发光层13和第一半导体层11。
上述步骤S302可以包括：
如图10所示，采用离子注入的方式，在第一半导体层11和发光层13中形成高阻区Q，高阻区Q的位置对应于将要形成的第二电极的位置。举例来说，可以向第一半导体层11和发光层13中注入氮元素或氢元素等，以改变第一半导体层11和发光层13中的晶格结构，使第一半导体层11和发光层13在高阻区Q绝缘化。在具体实施时，高阻区Q的注入深度 需要透过第一半导体层11和发光层13，达到第二半导体层12的表面，或者，也可以增大离子注入的深度，使第二半导体层12的表面也具有较薄的高阻区Q。高阻区Q的面积稍大于将要形成的第二电极的面积，便于后续在第二电极的周围形成绝缘隔离层。
如图11所示，对第一半导体层11和发光层13进行刻蚀，例如可以采用光刻工艺，以在高阻区形成贯穿第一半导体层11和发光层13的通孔T，并在通孔T周围形成绝缘隔离层19，也就是说，绝缘隔离层19是高阻区中去除通孔T之后得到的。在形成通孔T的过程中，可以刻蚀第一半导体层11、发光层13以及部分第二半导体层12，以形成贯穿第一半导体层11和发光层13的通孔T，并在第二半导体层12的第一表面S形成与通孔T对应的凹槽U，这样，可以保证后续形成的第二电极15能够与第二半导体层12实现电连接，提高工艺良率。当然，本申请的一些实施例中，在形成通孔T的过程中，也可以仅刻蚀第一半导体层11和发光层13，以漏出第二半导体层12的第一表面S1，只要保证第二电极15与第二半导体层12能够实现电连接即可。
如图12所示，形成第一电极14和第二电极15，第一电极14与第一半导体层11电连接，第二电极15填充通孔T，第二电极15通过通孔T与第二半导体层12电连接，且第二电极15通过绝缘隔离层19与第一半导体层11和发光层13绝缘。此外，在形成第一电极14和第二电极15之前或之后，还可以在第一半导体层11远离发光层13一侧的表面形成第二反射层18(或钝化层)。
在上述步骤S303中，参照图13，将形成第一电极14和第二电极15后的结构(例如图12所示的结构)具有第一电极14的一面键合于第一基板402上，在具体实施时，可以先形成覆盖第一电极14和第二电极15的牺牲层403，牺牲层403可以保护第一电极14和第二电极15，防止第一电极14和第二电极15被污染或刮伤等。然后，通过第一键合层404将形成第一电极14和第二电极15后的结构与第一基板402键合。之后，剥离衬底，并翻转剥离衬底后的结构，得到图13所示的结构。
在上述步骤S304中，如图14所示，对第二半导体层12进行处理，例如可以采用干法刻蚀工艺，以使第二半导体层12的第二表面S2在第一表面S1所在平面上的正投影位于第一表面S1的范围内，其中，第一表面S1为第二半导体层12靠近发光层13一侧的表面，第二表面S2为第二半导体层12远离发光层13一侧的表面。在本申请的一些实施例中，可以对第二半导体层12、发光层13和第一半导体层11一起进行刻蚀，以使第二半导体层12、发光层13和第一半导体层11均具有倾斜的侧面。
上述步骤S304之后，如图15所示，还可以包括：
形成至少覆盖第二半导体层12的部分侧面的第一反射层16。在一种可能的实现方式中，第一反射层16可以仅覆盖第二半导体层12的侧面，在另一种可能的实现方式中，第一反射层16可以覆盖第一半导体层11、发光层13和第二半导体层12的侧面。
参照图16，形成第一反射层16之后，还可以将第二半导体层12通过第二键合层405与第二基板406键合，之后，再次翻转，剥离第一基板并去除牺牲层，得到图16所示的结构。
在具体实施时，可以通过转移工艺，将图16所示的结构转移到衬底基板之上，例如可以得到如图7所示的结构，从而，将本申请实施例中的微型发光二极管芯片应用于各种电子设备中。
由于本申请实施例中的微型二极管芯片的制作方法解决问题的原理与上述微型发光 二极管芯片解决问题的原理相似，因此，该制作方法的实施可以参照上述微型发光二极管芯片的实施，重复之处不再赘述。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的精神和范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (18)

  1. 一种微型发光二极管芯片，其特征在于，包括：第一半导体层，第二半导体层，位于所述第一半导体层与所述第二半导体层之间的发光层，第一电极，以及第二电极；
    所述第一电极位于所述第一半导体层远离所述发光层的一侧，所述第二电极位于所述第二半导体层靠近所述发光层的一侧；所述第一电极与所述第一半导体层电连接，所述第二电极与所述第二半导体层电连接；
    所述第二半导体层具有相对设置的第一表面和第二表面，所述第一表面为所述第二半导体层靠近所述发光层一侧的表面，所述第二表面为所述第二半导体层远离所述发光层一侧的表面；
    所述第二表面在所述第一表面所在平面上的正投影位于所述第一表面的范围内。
  2. 如权利要求1所述的微型发光二极管芯片，其特征在于，在所述第一半导体层指向所述第二半导体层的方向上，所述第二半导体层在平行于所述第二表面的方向上的截面面积呈逐渐减小的趋势。
  3. 如权利要求1或2所述的微型发光二极管芯片，其特征在于，还包括：第一反射层；
    所述第一反射层至少覆盖所述第二半导体层的部分侧面。
  4. 如权利要求3所述的微型发光二极管芯片，其特征在于，所述第一半导体层具有相对设置的第三表面和第四表面，所述第三表面为所述第一半导体层远离所述发光层一侧的表面，所述第四表面为所述第一半导体层靠近所述发光层一侧的表面；
    所述第四表面在所述第三表面所在平面上的正投影位于所述第三表面的范围内。
  5. 如权利要求4所述的微型发光二极管芯片，其特征在于，所述第一反射层覆盖所述第一半导体层、所述发光层和所述第二半导体层的侧面。
  6. 如权利要求1～5任一项所述的微型发光二极管芯片，其特征在于，还包括：钝化层；
    所述钝化层位于所述第一半导体层远离所述发光层的一侧。
  7. 如权利要求3所述的微型发光二极管芯片，其特征在于，在所述第一半导体层指向所述第二半导体层的方向上，所述发光层和所述第一半导体层在平行于所述第二表面的方向上的各截面面积一致。
  8. 如权利要求7所述的微型发光二极管芯片，其特征在于，所述第一反射层仅覆盖所述第二半导体层的侧面。
  9. 如权利要求8所述的微型发光二极管芯片，其特征在于，还包括：钝化层；
    所述钝化层位于所述第一半导体层远离所述发光层的一侧，且所述钝化层包裹所述发光层和所述第一半导体层的侧面。
  10. 如权利要求3～5、7或8任一项所述的微型发光二极管芯片，其特征在于，还包括：位于所述第一半导体层远离所述发光层一侧的第二反射层。
  11. 如权利要求3～10任一项所述的微型发光二极管芯片，其特征在于，所述第一反射层覆盖所述第二表面的边缘。
  12. 如权利要求1～11任一项所述的微型发光二极管芯片，其特征在于，还包括：贯穿所述第一半导体层和所述发光层的通孔；
    所述第二电极通过所述通孔与所述第二半导体层电连接；
    所述第二电极与所述第一半导体层和所述发光层之间设有绝缘隔离层，所述第二电极 通过所述绝缘隔离层与所述第一半导体层和所述发光层绝缘。
  13. 如权利要求12所述的微型发光二极管芯片，其特征在于，所述第二半导体层在所述第一表面设有与所述通孔位置对应的凹槽，部分所述第二电极位于所述凹槽内。
  14. 一种显示面板，其特征在于，包括：如权利要求1～13任一项所述的微型发光二极管芯片以及衬底基板，所述微型发光二极管芯片位于所述衬底基板之上。
  15. 一种电子设备，其特征在于，包括：如权利要求14所述的显示面板以及壳体，所述壳体包裹所述显示面板；或者，所述电子设备包括：如权利要求1～13任一项所述的微型发光二极管芯片。
  16. 一种微型发光二极管芯片的制作方法，其特征在于，包括：
    在衬底之上依次形成第二半导体层、发光层和第一半导体层；
    在所述第一半导体层远离所述发光层的一侧形成与所述第一半导体层电连接的第一电极，在所述第二半导体层靠近所述第一发光层的一侧形成与所述第二半导体层电连接的第二电极；
    将形成所述第一电极和所述第二电极后的结构具有所述第一电极的一面键合于第一基板上，剥离所述衬底；
    对所述第二半导体层进行处理，以使所述第二半导体层的第二表面在第一表面所在平面上的正投影位于所述第一表面的范围内；所述第一表面为所述第二半导体层靠近所述发光层一侧的表面，所述第二表面为所述第二半导体层远离所述发光层一侧的表面。
  17. 如权利要求16所述的制作方法，其特征在于，所述在所述第一半导体层远离所述发光层的一侧形成与所述第一半导体层电连接的第一电极，在所述第二半导体层靠近所述第一发光层的一侧形成与所述第二半导体层电连接的第二电极，包括：
    采用离子注入的方式，在所述第一半导体层和发光层中形成高阻区，所述高阻区的位置对应于将要形成的所述第二电极的位置；
    对所述第一半导体层和所述发光层进行刻蚀，以在所述高阻区形成贯穿所述第一半导体层和所述发光层的通孔，并在所述通孔周围形成绝缘隔离层；
    形成所述第一电极和所述第二电极，所述第二电极填充所述通孔，且所述第二电极通过所述绝缘隔离层与所述第一半导体层和所述发光层绝缘。
  18. 如权利要求16或17所述的制作方法，其特征在于，所述对所述第二半导体层进行处理，以使所述第二半导体层的第二表面在第一表面所在平面上的正投影位于所述第一表面的范围内之后，还包括：
    形成至少覆盖所述第二半导体层的部分侧面的第一反射层。
PCT/CN2023/077492 2022-05-30 2023-02-21 微型发光二极管芯片、其制作方法、显示面板及电子设备 WO2023231462A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107680960A (zh) * 2017-09-26 2018-02-09 上海天马微电子有限公司 一种显示面板及其制造方法、显示装置
CN108649046A (zh) * 2018-05-08 2018-10-12 厦门乾照光电股份有限公司 半导体发光微显示器件及其制造方法以及衬底剥离方法
CN110491974A (zh) * 2019-08-16 2019-11-22 錼创显示科技股份有限公司 微型发光元件及微型发光二极管元件基板
CN112997323A (zh) * 2018-11-16 2021-06-18 三星电子株式会社 发光二极管、发光二极管的制造方法以及包括发光二极管的显示设备
US20210367105A1 (en) * 2020-05-19 2021-11-25 PlayNitride Display Co., Ltd. Micro light-emitting diode chip

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107680960A (zh) * 2017-09-26 2018-02-09 上海天马微电子有限公司 一种显示面板及其制造方法、显示装置
CN108649046A (zh) * 2018-05-08 2018-10-12 厦门乾照光电股份有限公司 半导体发光微显示器件及其制造方法以及衬底剥离方法
CN112997323A (zh) * 2018-11-16 2021-06-18 三星电子株式会社 发光二极管、发光二极管的制造方法以及包括发光二极管的显示设备
CN110491974A (zh) * 2019-08-16 2019-11-22 錼创显示科技股份有限公司 微型发光元件及微型发光二极管元件基板
US20210367105A1 (en) * 2020-05-19 2021-11-25 PlayNitride Display Co., Ltd. Micro light-emitting diode chip

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