WO2023228552A1 - リニアレギュレータ、半導体装置、スイッチング電源 - Google Patents

リニアレギュレータ、半導体装置、スイッチング電源 Download PDF

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Publication number
WO2023228552A1
WO2023228552A1 PCT/JP2023/012464 JP2023012464W WO2023228552A1 WO 2023228552 A1 WO2023228552 A1 WO 2023228552A1 JP 2023012464 W JP2023012464 W JP 2023012464W WO 2023228552 A1 WO2023228552 A1 WO 2023228552A1
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Prior art keywords
transistor
current
bias current
voltage
linear regulator
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Ceased
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PCT/JP2023/012464
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English (en)
French (fr)
Japanese (ja)
Inventor
健一 岡島
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2024522940A priority Critical patent/JPWO2023228552A1/ja
Publication of WO2023228552A1 publication Critical patent/WO2023228552A1/ja
Priority to US18/937,282 priority patent/US20250060770A1/en
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

Definitions

  • the present disclosure relates to a linear regulator, a semiconductor device, and a switching power supply.
  • Linear regulators are used as power sources for various devices.
  • Patent Document 1 can be mentioned as an example of the conventional technology related to the above.
  • the linear regulator disclosed herein includes a first N-channel transistor configured to be connected between an input voltage application end and a stabilization voltage application end, and the first transistor and an N-channel type second transistor configured to form a current mirror type output stage to generate an output current flowing to the first transistor by mirroring the bias current flowing through itself, and the stabilizing voltage.
  • a feedback control section configured to control the bias current according to a difference between a feedback voltage corresponding to the feedback voltage and a predetermined reference voltage; and a load configured to draw 1 leakage current.
  • FIG. 1 is a diagram showing the overall configuration of a switching power supply.
  • FIG. 2 is a diagram showing a schematic configuration of a linear regulator.
  • FIG. 3 is a diagram showing a first embodiment (comparative example) of a linear regulator.
  • FIG. 4 is a diagram showing a second embodiment of the linear regulator.
  • FIG. 5 is a diagram showing temperature characteristics of source voltage and gate voltage.
  • FIG. 6 is a diagram showing the temperature characteristics of circuit current.
  • FIG. 1 is a diagram showing the overall configuration of a switching power supply.
  • the switching power supply X of this configuration example is a step-down DC/DC converter that steps down the input voltage Vin to generate a desired output voltage Vout.
  • the switching power supply X includes a semiconductor device 10 and various discrete components externally attached to the semiconductor device 10 (capacitors C1 and C2, inductor L1, and resistors R1 and R2).
  • the semiconductor device 10 is a main body (so-called power supply control IC [integrated circuit]) that centrally controls the operation of the switching power supply X.
  • the semiconductor device 10 includes a plurality of external terminals (pins 1 to 6 in the figure) as means for establishing electrical connection with the outside of the device.
  • pin 1 is an enable input terminal EN.
  • the 2nd pin is a power good output terminal PGD.
  • the third pin is a feedback input terminal FB.
  • the 4th pin is a ground terminal GND.
  • the 5th pin is a switch output terminal SW.
  • the 6th pin is a power supply terminal VIN to which the input voltage Vin is applied.
  • a first end of the capacitor C1 is connected to a power supply terminal VIN.
  • a second end of the capacitor C1 is connected to a ground end.
  • a first end of the inductor L1 is connected to the switch output terminal SW.
  • the second end of the inductor L1 and the first ends of the resistor R1 and capacitor C2 are all connected to the application end of the output voltage Vout.
  • the second terminals of the capacitor C2 and the resistor R2 are both connected to a ground terminal.
  • the inductor L1 and capacitor C2 function as an LC filter that rectifies and smoothes the rectangular waveform switch voltage Vsw to generate the output voltage Vout.
  • a speed-up capacitor may be connected in parallel between both ends of the resistor R1 so that the switching power supply X starts up smoothly. If the output voltage Vout is within the input dynamic range of the semiconductor device 10, the resistors R1 and R2 may be omitted and the output voltage Vout may be directly input to the feedback input terminal FB.
  • the semiconductor device 10 of this configuration example includes an error amplifier 11, a comparator 12, an on-time setting circuit 13, a ripple generation circuit 14, an addition circuit 15, a drive control circuit 16, a soft start circuit 17, and a reference circuit.
  • a linear regulator 20 a capacitor C3, an output element M1, a synchronous rectifier M2, transistors M3 and M4, and a resistor R3 are integrated.
  • the error amplifier 11 operates according to the difference between the lower of the reference voltage Vref and soft start voltage Vss inputted to two non-inverting input terminals (+) and the feedback voltage Vfb inputted to the inverting input terminal (-). Error voltage Vc is generated. Note that the error voltage Vc rises when the feedback voltage Vfb is lower than the lower one of the reference voltage Vref and the soft start voltage Vss, and rises when the feedback voltage Vfb is higher than the lower one of the reference voltage Vref and the soft start voltage Vss. descend.
  • the comparator 12 compares the slope voltage Vslp input to the inverting input terminal (-) and the error voltage Vc input to the non-inverting input terminal (+) to generate a comparison signal Sc.
  • the comparison signal Sc becomes a high level when the slope voltage Vslp is lower than the error voltage Vc, and becomes a low level when the slope voltage Vslp is higher than the error voltage Vc.
  • the comparator 12 may have hysteresis characteristics.
  • the on-time setting circuit 13 generates the switch control signal S0 to maintain the output element M1 in the on-state for the on-time Ton after the comparison signal Sc rises to a high level.
  • the ripple generation circuit 14 generates a ripple voltage Vr that simulates the ripple component of the output voltage Vout in synchronization with the switch control signal S0.
  • Adder circuit 15 adds ripple voltage Vr to feedback voltage Vfb to generate slope voltage Vslp.
  • the drive control circuit 16 includes a controller 161 and drivers 162 and 163 as its components.
  • the controller 161 As basic output feedback control, the controller 161 generates gate control signals S1 and S2 so that the output voltage Vout matches a desired target value using a bottom detection type on-time fixed method according to the switch control signal S0. do.
  • controller 161 performs switching drive for each of the output element M1 and the synchronous rectifier M2 in accordance with the low input protection signal SA, overheat protection signal SB, overvoltage protection signal SC, short circuit protection signal SD, and overcurrent protection signal SE. It has a function to forcefully stop.
  • the controller 161 also has a function of stopping the switching drive of each of the output element M1 and the synchronous rectifier M2 during light loads in response to the zero-crossing detection signal SF. For example, when the zero-cross detection signal SF rises to a high level when the output element M1 is in the off state and the synchronous rectifier M2 is in the on state, the controller 161 detects that the switch voltage Vsw is at the zero-cross detection value (for example, GND ), the synchronous rectifier M2 may be turned off.
  • the zero-cross detection signal SF rises to a high level when the output element M1 is in the off state and the synchronous rectifier M2 is in the on state
  • the controller 161 detects that the switch voltage Vsw is at the zero-cross detection value (for example, GND ), the synchronous rectifier M2 may be turned off.
  • controller 161 also has a function of generating a gate drive signal G3 for the transistor M3 in response to an enable signal SEN externally input to the enable input terminal EN.
  • the driver 162 drives the output element M1 by generating a gate drive signal G1 according to the gate control signal S1.
  • the gate drive signal G1 becomes high level when the gate control signal S1 is high level, and becomes low level when the gate control signal S1 is low level.
  • the driver 163 drives the synchronous rectifier M2 by generating a gate drive signal G2 according to the gate control signal S2.
  • the gate drive signal G2 becomes high level when the gate control signal S2 is high level, and becomes low level when the gate control signal S2 is low level.
  • the soft start circuit 17 generates a soft start voltage Vss that gradually increases after the semiconductor device 10 starts up.
  • the power good detection circuit 19 detects whether the feedback voltage Vfb exceeds a predetermined power good detection threshold and generates the gate drive signal G4.
  • the low input protection circuit 1A detects whether the input voltage Vin exceeds a predetermined low input protection threshold and generates the low input protection signal SA.
  • the overheat protection circuit 1B detects whether the junction temperature Tj of the semiconductor device 10 (particularly the output element M1) exceeds a predetermined overheat protection threshold and generates an overheat protection signal SB.
  • the overvoltage protection circuit 1C detects whether the feedback voltage Vfb exceeds a predetermined overvoltage protection threshold and generates an overvoltage protection signal SC.
  • the short circuit protection circuit 1D monitors the feedback voltage Vfb and generates the short circuit protection signal SD.
  • the overcurrent protection circuit 1E generates the overcurrent protection signal SE by monitoring the switch voltage Vsw.
  • the capacitor C3 is connected between the output end of the error amplifier 11 and the ground end as a phase compensation means for preventing the error amplifier 11 from oscillating.
  • the output element M1 (for example, NMOSFET [N-channel type metal oxide semiconductor field effect transistor]) functions as an upper switch of the switch output stage SWO that generates the switch voltage Vsw from the input voltage Vin.
  • the drain of the output element M1 is connected to the power supply terminal VIN.
  • the source of the output element M1 is connected to the switch output terminal SW.
  • the gate of the output element M1 is connected to the application end of the gate drive signal G1.
  • the output element M1 is turned on when the gate drive signal G1 is at a high level, and is turned off when the gate drive signal G1 is at a low level.
  • the synchronous rectifier M2 (eg, NMOSFET) functions as a lower switch of the switch output stage SWO.
  • the drain of the synchronous rectifier M2 is connected to the switch output terminal SW.
  • the source of the synchronous rectifier M2 is connected to the ground terminal GND.
  • the gate of the synchronous rectifier M2 is connected to the application end of the gate drive signal G2.
  • the synchronous rectifier M2 is turned on when the gate drive signal G2 is at a high level, and is turned off when the gate drive signal G2 is at a low level.
  • a rectifier diode for example, a Schottky barrier diode whose cathode is connected to the switch output terminal SW and whose anode is connected to the ground terminal GND may be used instead of the synchronous rectifier M2.
  • the output element M1 and the synchronous rectifier M2 may be externally attached to the semiconductor device 10.
  • an external input terminal for the switch voltage Vsw and an external output terminal for each of the gate drive signals G1 and G2 are required.
  • a high voltage element such as an IGBT [insulated gate bipolar transistor], a SiC device, or a GaN device is used as the output element M1 and the synchronous rectifier M2. Good too.
  • the switch output stage SWO is driven in pulses between the input voltage Vin and the ground voltage PGND by complementarily turning on and off the output element M1 and the synchronous rectifier M2 connected to form a half bridge.
  • a rectangular waveform switch voltage Vsw is generated.
  • the word "complementary" in this specification refers to cases where the on/off states of output element M1 and synchronous rectifier M2 are completely reversed, as well as cases where there is a delay in the on/off transition timing of each.
  • the first end of the resistor R3 is connected to the switch output terminal SW.
  • a second end of the resistor R3 is connected to the drain of the transistor M3.
  • the source of transistor M3 is connected to ground terminal GND.
  • the gate of transistor M3 is connected to the application terminal of gate drive signal G3.
  • the transistor M3 is turned on when the gate drive signal G3 is at a high level, and is turned off when the gate drive signal G3 is at a low level.
  • the resistor R3 and transistor M3 connected in this manner function as a pull-down circuit for fixing the switch output terminal SW to the same potential as the ground terminal GND when the enable signal SEN is at the disabled logic level.
  • Transistor M4 functions as an open-drain output stage.
  • the source of transistor M4 is connected to the ground terminal.
  • the gate of transistor M4 is connected to the application terminal of gate drive signal G4. The transistor M4 is turned on when the gate drive signal G4 is at a high level, and is turned off when the gate drive signal G4 is at a low level.
  • the linear regulator 20 generates a stabilized voltage VREG by stepping down the input voltage Vin.
  • the linear regulator 20 for example, an LDO [low drop out] regulator can be suitably used.
  • the stabilized voltage VREG is used, for example, as an internal power supply voltage of the semiconductor device 10.
  • FIG. 2 is a diagram showing a schematic configuration of the linear regulator 20.
  • the linear regulator 20 of this configuration example includes a stabilizing voltage generation circuit 21 and resistors 22 and 23.
  • the stabilized voltage generation circuit 21 operates an output stage (not shown) so that the reference voltage VREF input to the non-inverting input terminal (+) and the feedback voltage VFB input to the inverting input terminal (-) match. By controlling, the input voltage Vin is stepped down to generate the stabilized voltage VREG. Note that in the stabilizing voltage generation circuit 21, enable/disable of the bias current generation operation is switched according to the bias enable signal ENBIAS.
  • VFB feedback voltage of the stabilized voltage VREG
  • FIG. 3 is a diagram showing a first embodiment of the linear regulator 20 (corresponding to a comparative example compared to a second embodiment described later).
  • the stabilizing voltage generation circuit 21 includes, for example, transistors M11 and M12 (for example, NMOSFET), transistors M21 to M23 (for example, NMOSFET), transistors M24 and M25 (for example, PMOSFET), and an operational amplifier.
  • AMP current sources CS1 and CS2, and a resistor R4.
  • the drain of the transistor M11 is connected to the application terminal of the input voltage Vin.
  • the gates of transistors M11 and M12 are both connected to the drain of transistor M12.
  • the source of transistor M12 is connected to the first end of resistor R4.
  • the drain of the transistor M11 and the second end of the resistor R4 are both connected to the application end of the stabilizing voltage VREG.
  • a current mirror type output stage 201 is formed.
  • the transistor M11 corresponds to an N-channel type first transistor configured to be connected between the application end of the input voltage Vin and the application end of the stabilizing voltage VREG.
  • the transistor M12 forms a current mirror type output stage 201 together with the transistor M11, thereby mirroring the bias current Ib flowing through itself to generate an output current Io flowing through the transistor M11. This corresponds to 2 transistors.
  • the first end of the current source CS1 is connected to the power supply end.
  • the second end of current source CS1 is connected to the drains of transistors M21 and M23.
  • the current source CS1 connected in this manner functions as a first bias current generation circuit configured to generate the first bias current I1.
  • the gate of the transistor M23 is connected to the output end of the operational amplifier AMP (corresponding to the application end of the gate drive signal G23).
  • the source of transistor M23 is connected to the ground terminal.
  • the operational amplifier AMP generates a gate drive signal G23 according to a reference voltage VREF input to an inverting input terminal (-) and a feedback voltage VFB input to a non-inverting input terminal (+).
  • the second bias current I2 decreases when the feedback voltage VFB is lower than the reference voltage VREF, and increases when the feedback voltage VFB is higher than the reference voltage VREF.
  • the gates of transistors M21 and M22 are both connected to the drain of transistor M21.
  • the sources of transistors M21 and M22 are both connected to a ground terminal.
  • the gates of transistors M24 and M25 are both connected to the drain of transistor M24.
  • the sources of the transistors M24 and M25 are both connected to the application terminal of the input voltage Vin.
  • the drain of transistor M25 is connected to the drain of transistor M12.
  • the transistors M24 and M25 connected in this way are configured to generate a bias current Ib flowing through the transistor M25 by mirroring the fifth bias current I5 flowing through the transistor M24 at a mirror ratio ⁇ (however, ⁇ 1).
  • the current mirror CM2 functions as a second current mirror CM2.
  • the fifth bias current I5 is ⁇ times the fourth bias current I4 (however, ⁇ 1).
  • the bias current Ib flowing through the transistor M12 is expressed as (I1-I2) ⁇ .
  • the first bias current I1 is a fixed value
  • the current source CS1, the transistors M21 to M25, and the operational amplifier AMP are configured to control the bias current Ib according to the difference between the feedback voltage VFB according to the stabilizing voltage VREG and the predetermined reference voltage VREF.
  • a feedback control section 202 is formed.
  • the first end of the current source CS2 is connected to the application end of the stabilizing voltage VREG.
  • a second end of current source CS2 is connected to a ground terminal.
  • the current source CS2 connected in this manner functions as a sink current generation circuit configured to draw a predetermined sink current Is from the application end of the stabilizing voltage VREG.
  • an element with a low on-threshold voltage Vth (so-called low Vth element) may be used as the transistor M11.
  • the current source CS2 is used to extract the sink current Is from the application terminal of the stabilizing voltage VREG, even if the output leakage current of the transistor M11 increases at high temperatures, the rise in the stabilizing voltage VREG can be suppressed. can. However, in this configuration, since the output leakage current itself is not suppressed, the increase in the circuit current Ic consumed by the linear regulator 20 cannot be eliminated.
  • FIG. 4 is a diagram showing a second embodiment of the linear regulator 20.
  • the stabilizing voltage generation circuit 21 further includes a load 203 and a bias current adjustment section 204 in addition to the above-mentioned components.
  • the load 203 is configured to draw the first leakage current ILK1 from the gate common to both transistors M11 and M12.
  • the load 203 includes a transistor M31 (for example, an NMOSFET).
  • the drain of the transistor M31 is connected to the gates of each of the transistors M11 and M12.
  • the source and gate of the transistor M31 are both connected to the ground terminal. That is, the transistor M31 is always in a fully off state.
  • the transistor M31 corresponds to an N-channel type third transistor configured to have the same leakage current characteristics as the transistor M11.
  • the output current Io flowing through the transistor M11 is narrowed to a small value, so the ratio of the output leak current to the circuit current Ic of the linear regulator 20 increases. Therefore, by introducing the load 203 and suppressing an increase in output leakage current, it is possible to increase efficiency at high temperatures in a light load state.
  • the bias current adjustment unit 204 is configured to increase the bias current Ib by at least the same amount as the first leakage current ILK1 when turning on the transistor M11.
  • the bias current adjustment section 204 includes a transistor M41 (for example, NMOSFET) and transistors M42 and M43 (for example, PMOSFET).
  • a transistor M41 for example, NMOSFET
  • transistors M42 and M43 for example, PMOSFET
  • the drain of the transistor M41 is connected to the drain of the transistor M42.
  • the source and gate of the transistor M41 are both connected to the ground terminal. In other words, the transistor M41 is always in a fully off state.
  • the transistor M41 corresponds to an N-channel type fourth transistor configured to have the same leakage current characteristics as the transistor M31 (and by extension, the transistor M11).
  • the gates of transistors M42 and M43 are both connected to the drain of transistor M42.
  • the sources of transistors M42 and M43 are both connected to the power supply terminal.
  • the drain of transistor M43 is connected to the drains of transistors M21 and M23.
  • the transistors M42 and M43 connected in this way form a third current mirror configured to generate a mirror current I6 flowing through the transistor M43 by mirroring the second leakage current ILK2 flowing through the transistor M42 at a mirror ratio ⁇ .
  • the mirror ratio ⁇ depends on the element size of each of the transistors M31 and M41. When the element sizes of transistors M31 and M41 are the same, ⁇ 1/( ⁇ ). It is necessary to set the mirror ratio ⁇ relatively large in consideration of variations in the transistors M31 and M41 and variations in the third current mirror CM3.
  • the maximum value Ibmax of the bias current Ib becomes (I1+ILK2 ⁇ ) ⁇ . . That is, by introducing the bias current adjustment unit 204, the maximum value Ibmax of the bias current Ib is increased by an additional amount ILK2 ⁇ ( ⁇ ILK1) corresponding to the second leakage current ILK2.
  • the second leak current ILK2 when the first leak current ILK1 increases at high temperatures, the second leak current ILK2 also increases in the same manner as this, so the maximum value Ibmax of the bias current Ib is increased. Therefore, with the minimum required mirror current I6, it is possible to prevent the first leakage current ILK1 from becoming larger than the maximum value Ibmax of the bias current Ib due to device variations or the like. That is, there is an advantage that unnecessary current does not flow at a temperature where the first leakage current ILK1 is small.
  • the bias current Ib required to turn on the transistor M11 is There is no shortage. Therefore, no problem occurs in the on-transition of the transistor M11, and the output current supply capability of the linear regulator 20 is not impaired.
  • the gate voltage Vg of the transistor M11 decreases only to the source voltage Vs.
  • FIG. 6 is a diagram showing the temperature characteristics of the circuit current Ic of the linear regulator 20. Note that the horizontal axis of this figure indicates temperature, and the vertical axis of this figure indicates current. Moreover, the solid line shows the behavior of the second embodiment (FIG. 4), and the broken line shows the behavior of the first embodiment (FIG. 3).
  • the circuit current Ic of the linear regulator 20 at high temperatures can be suppressed to a smaller value than in the first embodiment (broken line).
  • the linear regulator disclosed herein includes a first N-channel transistor configured to be connected between an input voltage application end and a stabilization voltage application end, and the first transistor and an N-channel type second transistor configured to form a current mirror type output stage to generate an output current flowing to the first transistor by mirroring the bias current flowing through itself, and the stabilizing voltage.
  • a feedback control section configured to control the bias current according to a difference between a feedback voltage corresponding to the feedback voltage and a predetermined reference voltage;
  • the first configuration includes a load configured to draw out one leakage current (first configuration).
  • the load may include a third N-channel transistor configured to have the same leakage current characteristics as the first transistor (second configuration). good.
  • the linear regulator according to the first or second configuration further includes a bias current adjustment section configured to increase the bias current by at least the same amount as the first leakage current when turning on the first transistor. (Third configuration) may also be used.
  • the bias current adjustment section has a configuration (fourth configuration) including an N-channel type fourth transistor configured to have the same leakage current characteristics as the load. Good too.
  • the feedback control section includes a first bias current generation circuit configured to generate a predetermined first bias current, a first bias current generation circuit configured to generate a predetermined first bias current, a first bias current generation circuit configured to generate a predetermined first bias current, a first bias current generation circuit configured to generate a predetermined first bias current, a second bias current generation circuit configured to generate a second bias current according to a difference from a reference voltage; and a second bias current generating circuit configured to generate a second bias current according to a difference from a reference voltage;
  • a configuration (fifth configuration) including a current mirror configured to generate a bias current may also be used.
  • the feedback control section includes a first bias current generation circuit configured to generate a predetermined first bias current, and a difference between the feedback voltage and the reference voltage.
  • a second bias current generation circuit configured to generate a second bias current according to the second bias current; and a second bias current generation circuit configured to generate a second bias current according to A configuration (sixth configuration) including a current mirror configured to generate the bias current by mirroring a differential current obtained by subtracting two bias currents may be adopted.
  • the linear regulator according to any one of the first to sixth configurations has a configuration (seventh configuration) that further includes a sink current generation circuit configured to extract a predetermined sink current from the stabilizing voltage application terminal. Good too.
  • the output stage may have a mirror ratio of 10 or more (eighth configuration).
  • the semiconductor device disclosed in this specification has a configuration (ninth configuration) including a linear regulator according to any one of the first to eighth configurations described above.
  • the switching power supply disclosed in this specification includes a semiconductor device according to the ninth configuration, and has a configuration (tenth configuration) that drives a switch output stage to generate a desired output voltage from the input voltage. composition).

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PCT/JP2023/012464 2022-05-24 2023-03-28 リニアレギュレータ、半導体装置、スイッチング電源 Ceased WO2023228552A1 (ja)

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US18/937,282 US20250060770A1 (en) 2022-05-24 2024-11-05 Linear regulator, semiconductor device, and switching power supply

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CN117908607A (zh) * 2023-12-15 2024-04-19 无锡赛米垦拓微电子股份有限公司 电子雷管中继电路的动态电流反馈电路
CN118300607A (zh) * 2024-05-27 2024-07-05 深圳市电科星拓科技有限公司 包含低压差线性稳压器和tdc的电路系统

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JP2000322136A (ja) * 1999-05-10 2000-11-24 Sharp Corp 直流安定化電源回路の保護回路
JP2010211721A (ja) * 2009-03-12 2010-09-24 Rohm Co Ltd レギュレータ回路
US20190179398A1 (en) * 2017-12-12 2019-06-13 Texas Instruments Incorporated Signal powered energy detect and wakeup system
JP2020071710A (ja) * 2018-10-31 2020-05-07 ローム株式会社 リニア電源回路

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JP2000322136A (ja) * 1999-05-10 2000-11-24 Sharp Corp 直流安定化電源回路の保護回路
JP2010211721A (ja) * 2009-03-12 2010-09-24 Rohm Co Ltd レギュレータ回路
US20190179398A1 (en) * 2017-12-12 2019-06-13 Texas Instruments Incorporated Signal powered energy detect and wakeup system
JP2020071710A (ja) * 2018-10-31 2020-05-07 ローム株式会社 リニア電源回路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117908607A (zh) * 2023-12-15 2024-04-19 无锡赛米垦拓微电子股份有限公司 电子雷管中继电路的动态电流反馈电路
CN118300607A (zh) * 2024-05-27 2024-07-05 深圳市电科星拓科技有限公司 包含低压差线性稳压器和tdc的电路系统

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