WO2023226497A1 - 总线仲裁方法和装置、计算机可读存储介质及主控芯片 - Google Patents

总线仲裁方法和装置、计算机可读存储介质及主控芯片 Download PDF

Info

Publication number
WO2023226497A1
WO2023226497A1 PCT/CN2023/078646 CN2023078646W WO2023226497A1 WO 2023226497 A1 WO2023226497 A1 WO 2023226497A1 CN 2023078646 W CN2023078646 W CN 2023078646W WO 2023226497 A1 WO2023226497 A1 WO 2023226497A1
Authority
WO
WIPO (PCT)
Prior art keywords
access
host
slave
counter
priority
Prior art date
Application number
PCT/CN2023/078646
Other languages
English (en)
French (fr)
Inventor
杨宇
Original Assignee
上海美仁半导体有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 上海美仁半导体有限公司 filed Critical 上海美仁半导体有限公司
Publication of WO2023226497A1 publication Critical patent/WO2023226497A1/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/366—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a centralised polling arbiter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3027—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3089—Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents

Definitions

  • the present disclosure relates to the technical field of integrated circuit design, and in particular to a bus arbitration method, a computer-readable storage medium, a bus arbitration device, a bus arbiter and a main control chip.
  • a bus arbiter is needed to coordinate the order in which multiple hosts access the slave, that is, first respond to a host's request to access the slave, and wait for requests from other hosts. ; Wait until the current host's access ends, and then another host accesses, and so on, until all hosts' access to the slave ends. Since the host has different response requirements for slave access in different time periods, whether the bus arbiter can respond to the preemption requests of many hosts in a timely manner has become a key indicator of the performance of the SOC (System On Chip) chip.
  • SOC System On Chip
  • the present disclosure aims to solve one of the technical problems in the related art, at least to a certain extent.
  • the first purpose of this disclosure is to propose a bus arbitration method that determines the access priority of the host based on the number of times the host continuously accesses the slave, achieving dynamic adjustment of the access priority, and avoiding the need for fixed priorities. It is unfair and can adjust the priority of each host according to the actual access status of the slave, which can be applied to application scenarios that require high real-time response from the system.
  • a second object of the present disclosure is to provide a computer-readable storage medium.
  • the third object of the present disclosure is to provide a bus arbitration device.
  • the fourth object of the present disclosure is to propose a bus arbiter.
  • the fifth object of the present disclosure is to provide a main control chip.
  • the first embodiment of the present disclosure proposes a bus arbitration method, which includes: receiving access request signals from multiple hosts; determining when multiple hosts access the same slave machine at the same time based on the access request signals of multiple hosts. , control the counter corresponding to each host in the slave to start counting; when the count value continuously counted by one of the multiple counters exceeds the preset threshold, the access priority of the host corresponding to the counter is set to the highest priority class.
  • the bus arbitration method of the embodiment of the present disclosure first, access request signals from multiple hosts are received, and then, when it is determined based on the access request signals of multiple hosts that multiple hosts access the same slave machine at the same time, control the slave machine and each slave machine.
  • a counter corresponding to a host starts counting.
  • the access priority of the host corresponding to the counter is set to the highest priority. Therefore, this method determines the host's access priority based on the number of times the host continuously accesses the slave, and realizes dynamic adjustment of the host's access priority, which not only avoids the unfairness of fixed priorities, but also can be based on the actual reception of the slave.
  • the access status adjusts the priority of each host, which can be applied to application scenarios that require high real-time response from the system.
  • the bus arbitration method may also have the following additional technical features: According to an embodiment of the present disclosure, during a process in which the count value of one of the counters in the plurality of counters continuously counts exceeds the preset threshold, if the count values of the remaining counters in the plurality of counters are zero, it is determined that the counter is continuously counting. .
  • the count values of the remaining counters in the plurality of counters are not zero, the count values of the plurality of counters are cleared to zero.
  • the method further includes: controlling the count value of the counter to be cleared and restarting counting; within a preset time, if the If the continuous counting value of the counter is less than the preset threshold, the access priorities of multiple hosts are determined in a round-robin arbitration manner.
  • the method further includes: determining the access priorities of the remaining hosts among the multiple hosts in a round-robin arbitration manner.
  • the second embodiment of the present disclosure provides a computer-readable storage medium on which a bus arbitration method program is stored.
  • the bus arbitration method program is executed by a processor, the above bus arbitration method is implemented.
  • the processor executes the bus arbitration method program stored thereon, the above-mentioned bus arbitration method is implemented.
  • the dynamic adjustment of the access priority is realized, that is, It avoids the unfairness of fixed priority and can adjust the priority of each host according to the actual access status of the slave. It can be suitable for application scenarios that require high real-time response from the system.
  • a bus arbitration device proposed by the third embodiment of the present disclosure includes: a receiving unit for receiving access request signals from multiple hosts; and a control module for determining based on the access request signals of multiple hosts When multiple hosts access the same slave at the same time, control the counter corresponding to each host in the slave to start counting; the control module is also used to control the continuous counting value of one of the multiple counters to exceed the preset threshold. , set the access priority of the host corresponding to the counter to the highest priority.
  • the receiving unit receives access request signals from multiple hosts, and the control module determines based on the access request signals of multiple hosts that when multiple hosts access the same slave machine at the same time, it controls the slave machine and The counter corresponding to each host starts counting, and when the continuously counted value of one of the multiple counters exceeds a preset threshold, the control module sets the access priority of the host corresponding to the counter to the highest priority.
  • the fourth embodiment of the present disclosure proposes a bus arbiter, which includes a memory, a processor, and a bus arbitration program stored in the memory and runable on the processor.
  • the processor executes the bus arbitration program, Implement the above bus arbitration method.
  • the fifth embodiment of the present disclosure proposes a main control chip, which includes a memory, a processor and a bus arbitration program stored in the memory and runable on the processor.
  • the processor executes the bus arbitration program, Implement the above bus arbitration method.
  • Figure 1 is a flow chart of a bus arbitration method according to an embodiment of the present disclosure
  • Figure 2 is a block diagram of a bus arbiter according to an embodiment of the present disclosure
  • Figure 3 is a waveform diagram when two hosts use a polling arbitration strategy to access the same slave machine according to an embodiment of the present disclosure
  • Figure 4 is the waveform diagram when host 0 is forcibly upgraded to the highest priority in Figure 3
  • Figure 5 is a waveform diagram showing host 1 being forcibly upgraded to the highest priority in Figure 3
  • Figure 6 is a flow chart of a bus arbitration method according to a specific embodiment of the present disclosure
  • Figure 7 is a block diagram of a bus arbitration device according to an embodiment of the present disclosure
  • Figure 8 is a block diagram of a bus arbiter according to an embodiment of the present disclosure
  • FIG. 9 is a block diagram of a main control chip according to an embodiment of the present disclosure.
  • bus arbiters In related technologies, commonly used bus arbiters are divided into polling arbiters and fixed priority arbiters.
  • the principle of the polling arbiter is: initially, MASTER0 (host 0) has the highest priority, MASTER1 (host 1) has the second priority, MASTER2 (host 2) has the third priority...; when the response After MASTER0's request, MASTER0's priority becomes the lowest, MASTER1's priority becomes the highest, MASTER2's priority becomes the second...
  • the advantage of the polling arbiter is that the priority of each host changes cyclically, and the overall fairness is well guaranteed.
  • the disadvantage is that when a master frequently accesses the slave within a specific period of time and hopes to get the fastest response, the highest priority of the master is not guaranteed, reducing bus utilization.
  • the principle of the fixed priority arbiter is: MASTER0 has the highest priority, MASTER1 has the second priority, MASTER2 has the third priority...; after responding to MASTER0's request, MASTER0's priority remains the highest, MASTER1's The priority is second, and MASTER2 has the third priority. That is, the access priority of all hosts to the same slave is fixed.
  • the advantage of the fixed priority arbiter is that according to the actual application requirements, the host with the fastest response requirements to the slave can be set to the highest priority, thus avoiding the performance loss of the host. At the same time, it can simplify the design, reduce the chip area and cut costs.
  • the disadvantage is that it cannot dynamically adjust the priority order of each host and lacks flexibility.
  • Figure 1 is a flow chart of a bus arbitration method according to an embodiment of the present disclosure.
  • the bus arbitration method may be implemented through a bus arbiter as shown in FIG. 2 .
  • the bus arbiter includes three modules: a slave access times counter 10, an arbitration state machine 20 and an output control module 30.
  • the slave access times counter 10 is responsible for accumulating the number of times each host accesses the slave and generating a flag signal to provide Arbitration state machine
  • arbitration state 20 is responsible for processing the timing of bus access and assigning priorities
  • the output control module, 30, is responsible for generating the control signals required to access the slave.
  • the following is a detailed explanation of the bus president method by taking two hosts accessing the same slave A as an example. The two hosts are host 0 and host 1 respectively.
  • the bus arbitration method may include the following steps: S1, receives access request signals from multiple hosts. That is to say, slave A receives the access request signal of host 0 through the host 0 bus, and receives the access request signal of host 1 through the host 1 bus.
  • slave A when slave A only receives the access request signal from host 0 or host 1, it is determined that a single master corresponds to the signal access process of one slave. No priority setting is required, and the corresponding host is directly controlled to perform the access request on slave A. Access, the counter corresponding to each master in slave A does not work.
  • slave A receives the access request signals from master 0 and master 1 at the same time, it is determined that multiple masters correspond to the signal access process of the same slave, and the priority needs to be set. At this time, the bus arbiter can follow the preset Assume that the policy determines the access priority of host 0 and host 1, and accesses slave A.
  • the counter corresponding to each host in slave A starts counting, that is, the slave access counter 1 in slave A counts the number of accesses to host 1. From Machine access counter 0 counts the number of accesses to host 0.
  • the access priority of host 0 will be forcibly upgraded to the highest priority.
  • the output control module first sends the access request signal of host 0 to slave A, and then Send the access request signal of host 1 to slave A. Therefore, in the initial state of this method, each host uses a preset strategy to determine the access priority of the host. At the same time, the counter corresponding to each host in the slave starts counting.
  • the priority of the host is forcibly upgraded to the highest priority.
  • the access rights of the host that needs to frequently access the slave in a short period of time are configured with the highest priority, thus avoiding the loss of host performance.
  • the counter when only one master accesses the slave, the counter does not work.
  • the counters corresponding to the multiple masters in the slave start counting, and one counter realizes continuous operation.
  • the access priority of the host corresponding to the counter is set to the highest priority.
  • Other hosts can access the slave according to the preset access policy after the host completes the access to the slave.
  • this method determines the access priority of the host based on the number of times the host continuously accesses the slave, and realizes dynamic adjustment of the access priority, which not only avoids the unfairness of fixed priority, but also can be based on the actual access of the slave. Adjusting the priority of each host according to the situation can be suitable for application scenarios that require high real-time response from the system.
  • the count value of one of the counters in the plurality of counters continuously counts exceeds the preset threshold, if the count values of the remaining counters in the plurality of counters are zero, it is determined that the counter is continuously counting.
  • the counter is deemed to be continuous counting, that is, during the access process of the master to the slave machine corresponding to the counter, no other master machine accesses the slave machine. .
  • the slave access counter 1 has no counting operation during this process. That is to say, in this stage, slave A only receives the access request signal sent by host 0. , the host 1 does not send an access request signal to the slave A, so it is determined that the slave access counter 0 is counting continuously.
  • the count values of the remaining counters in the plurality of counters are not zero, the count values of the plurality of counters are cleared to zero.
  • slave access counter 0 counts the number of accesses to host 0
  • slave access counter 1 counts the number of accesses to host 1. It can be understood that when it is determined that both host 0 and host 1 access slave A, the slave access counter 0 and the slave access counter 1 are controlled to be set to zero, and then the counting operation is started.
  • slave access counter 0 when host 0 sends an access request signal to slave A, slave access counter 0 counts as 1 and slave access counter 1 counts as 0; when the next access request signal sent to slave A is still sent by host 0 , then the slave access counter 0 counts to 2, the slave access counter 1 counts to 0; and so on, until the slave access counter 0 counts to M+1, and when it exceeds the preset threshold M, the count of the slave access counter 1 If it is still 0, it is determined that the slave access counter 0 is a continuous count.
  • the next access signal is the access request signal sent by the master 1 to the slave A, then the slave access counter 0 counts 2, and the slave Access counter 1 counts 1, indicating that host 0 has not implemented continuous access. At this time, the count values of slave access counter 0 and slave access counter 1 are all cleared, and it will be determined next time that multiple hosts access the same slave at the same time. When machine A is turned on, restart the counting operation.
  • the method further includes: controlling the count value of the counter to be cleared and restarting counting; within a preset time, if the If the continuous counting value of the counter is less than the preset threshold, the access priorities of multiple hosts are determined in a round-robin arbitration manner.
  • the preset time can be set according to the actual situation.
  • the count value of slave access counter 0 is cleared to zero, and then the slave access counter 0 is controlled to perform the counting operation again. If within the preset time, the continuous count value of slave access counter 0 exceeds the preset threshold M, continue to set the access priority of host 0 to the highest priority, otherwise, control host 0 and host 1 to poll Determine the priority of access through arbitration, access slave A, and control slave access counter 0 and slave access counter 1 to count again according to the above method until the continuous counting value of a certain counter exceeds the preset threshold M , for details, please refer to the above method description and will not be described again here.
  • the above polling arbitration method can be that when host 1 and host 0 access slave machine A at the same time for the first time, control host 1 first accesses slave machine A, and host 0 waits. After host 1's access is completed, host 0 then controls the slave machine. A to visit. The next time host 1 and host 0 access slave A at the same time, host 0 will access slave A first, and host 1 will wait. After host 0's access is completed, host 1 will access slave A again, and so on, to achieve Access control for polling arbitration.
  • the waveforms when host 0 and host 1 use polling arbitration to access slave 0 are shown in Figure 3, where HCLK represents the clock signal.
  • M0_VALD indicates the signal for host 0 to access slave A.
  • the high level indicates that host 0 sends an access request signal to slave A.
  • MI_VALD indicates the signal for host 1 to access slave A.
  • the high level indicates that host 1 sends an access request signal to slave A.
  • STATE indicates status, IDIE indicates idle state, M0 indicates that host 0 is accessing slave machine A, MISTER indicates that M1 is waiting when MO accesses; M1 indicates that host 1 is accessing slave A, and MISTER indicates that M0 is waiting when M1 accesses.
  • M1_HREADYOUT represents the level signal during M1's access to slave A
  • M0_HREADYOUT represents the level signal during M0's access to slave A.
  • a reset preset period can also be set, and the reset preset period is used as the highest priority maintenance period.
  • polling arbitration is resumed.
  • the timing starts after the access priority of host 0 is set to the highest priority.
  • the access priority of host 0 is set to the highest priority.
  • the timing exceeds the reset preset period, , automatically reverts to polling arbitration to determine the priority of the host. It can be understood that when the priority confirmation method of polling arbitration is restored, the counter is cleared and counting is restarted. Then, when the continuously counted value of one of the counters exceeds the preset threshold M, the access priority of the corresponding host is continued. level is the highest priority.
  • this method can quickly revert to the round-robin arbitration method after a period of time after frequent access requests to the host with the highest priority end, so that it can still take into account the fairness of the access priorities of each host.
  • this method can achieve the purpose of improving bus performance by using as little software configuration as possible and only adding a few timer resources.
  • the bus arbitration method further includes: determining the access priorities of the remaining hosts among the multiple hosts in a round-robin arbitration manner. .
  • host 0 Take the example of host 0, host 1 and host 2 accessing slave A at the same time. Based on the continuous counting value of the counter, the access priority of host 0 is determined to be the highest priority. Then host 0 is first controlled to access slave A. Host 1 and Host 2 wait, and after Host 0 finishes accessing Slave A, Host 1 and Host 2 access Slave A according to the round-robin arbitration method.
  • the access sequence determined by this round-robin arbitration is Host 2 and Host 1, after determining that Host 0's access to Slave A is completed, control Host 2 to access Slave A, Host 1 continues to wait, and after determining that Host 2's access to Slave A is completed, Host 2 will Access slave A.
  • the method before setting the access priority of the host corresponding to the counter to the highest priority, the method further includes: determining the access priorities of the multiple hosts in a round-robin arbitration manner.
  • the method after receiving access request signals from multiple hosts, if it is determined that multiple hosts are accessing the same slave machine at the same time, the method first determines the access priorities of the multiple hosts in a round-robin arbitration manner, and at the same time controls the slave machine.
  • the counter in the machine corresponding to each host starts counting. Until the continuous counting value of a certain counter is greater than the preset threshold M, the access priority of the host corresponding to the counter is set to the highest level. Otherwise, the access priority of the host continues to be determined by polling arbitration.
  • each host uses polling arbitration to determine its own priority.
  • the internal slave access counter starts counting.
  • the threshold is set to M times, the priority of the host will be forcibly upgraded to the highest priority.
  • this method dynamically monitors the slave access counter and configures the access rights of the host that needs to frequently access the slave in a short period of time to the highest priority, thus avoiding the performance loss of the host.
  • the bus signals of host 0 and host 1 are input to the three modules of the bus arbiter for calculation.
  • the output signal MST0_EN of the slave access counter 0 is high level, indicating that the access priority of the host 0 is forced to the highest priority.
  • the waveform is shown in Figure 4, in which MST0_EN becomes high level. This is the moment when host 0 is forced to have the highest priority. After that, it is determined that host 1 and host 0 are accessing at the same time.
  • the output control module 30 controls host 0 to access slave A first, and host 1 waits for host 0 to be determined. After the access is completed, the output control module 30 controls the host 1 to access the slave A again.
  • the output signal MST1_EN of slave access counter 1 is high level, indicating the access priority of host 1 Forced to the highest priority, the waveform is shown in Figure 5.
  • MST1_EN becomes high level, it is the moment when host 1 is forced to the highest priority. After that, it is determined that host 1 and host 0 are accessed at the same time, through the output
  • the control module 30 controls the host 1 to access the slave A first, and the host 0 waits. After it is determined that the access of the host 1 is completed, the output control module 30 controls the host 0 to access the slave A again.
  • the arbitration state machine control output control module 30 adopts polling arbitration.
  • the waveform diagram is as follows As shown in Figure 3. Specifically, the arbitration state machine connects the host 0 bus and the host 1 bus and determines the access time of the host 1 and the host 0. If it is determined that the host 1 and the host 0 are accessing at the same time, the output control module 30 controls the host 1 to the slave. A accesses first, and the host 0 waits. After it is determined that the access of the host 1 is completed, the output control module 30 controls the host 0 to access the slave A again.
  • the arbitration state machine determines that the count values of the two counters are still less than the preset threshold M, then the arbitration state machine will continue to execute the polling arbitration mode and control host 0 through the output control module 30
  • the slave machine A is first accessed, and the host machine 1 waits. After it is determined that the access of the master machine 0 is completed, the output control module 30 controls the host machine 1 to access the slave machine A again.
  • the execution steps of the bus arbitration method may include: S101. Receive access request signals from multiple hosts.
  • step S104 Determine whether the continuous counting value of the counter is less than or equal to the preset threshold M. If yes, execute step S102; if not, execute step S105.
  • S105 Set the access priority of the host corresponding to the counter to the highest priority, and use polling arbitration for the other hosts. Wherein, the counter continuously counts a count value greater than the preset threshold M.
  • the bus arbitration method of the embodiment of the present disclosure first, access request signals from multiple hosts are received, and then, based on the access request signals of multiple hosts, it is determined that when multiple hosts access the same slave machine at the same time, the slave machine is controlled.
  • the counter corresponding to each host starts counting, and when the continuously counted value of one of the multiple counters exceeds the preset threshold, the access priority of the host corresponding to the counter is set to the highest priority. Therefore, this method determines the access priority of the host based on the number of times the host continuously accesses the slave, and realizes dynamic adjustment of the access priority, which not only avoids the unfairness of fixed priority, but also can be based on the actual access of the slave. Adjusting the priority of each host according to the situation can be suitable for application scenarios that require high real-time response from the system.
  • the present disclosure also provides a computer-readable storage medium.
  • the computer-readable storage medium of the embodiment of the present disclosure stores a bus arbitration method program thereon, and when the bus arbitration method program is executed by the processor, the above-mentioned bus arbitration method is implemented.
  • the processor executes the bus arbitration method program stored thereon, the above-mentioned bus arbitration method is implemented, and the access priority is dynamically adjusted, which avoids the fixed priority. It is unfair and can adjust the priority of each host according to the actual access status of the slave, which can be applied to application scenarios that require high real-time response from the system.
  • the present disclosure also proposes a bus arbitration device.
  • the bus arbitration device may include: a receiving unit 40 and a control module 50 .
  • the receiving unit 40 is used to receive access request signals from multiple hosts.
  • the control module 50 is used to control the counter corresponding to each host in the slave to start counting when it is determined based on the access request signals of multiple hosts that multiple hosts access the same slave at the same time.
  • the control module 50 is also configured to set the access priority of the host corresponding to the counter to the highest priority when the continuously counted value of one of the multiple counters exceeds a preset threshold.
  • control module 50 is also configured to: when the count value continuously counted by one of the multiple counters exceeds the preset threshold, if the count values of the remaining counters in the multiple counters are zero, Then it is determined that the counter is continuous counting.
  • control module 50 is further configured to clear the count values of the multiple counters if the count values of the remaining counters in the multiple counters are not zero.
  • control module 50 sets the access priority of the host corresponding to the counter to the highest priority, it is also specifically configured to: clear the count value of the counter to zero, and after a preset time delay , controls the counter to start counting; if the continuous counting value of the counter is less than the preset threshold, the access priorities of multiple hosts are determined according to the round-robin arbitration method.
  • control module 50 sets the access priority of the host corresponding to the counter to the highest priority, it is also specifically configured to: determine the access priority of the remaining hosts among the multiple hosts in a round-robin arbitration manner. class.
  • the receiving unit receives the access request signals of multiple hosts, and the control module determines based on the access request signals of the multiple hosts that when multiple hosts access the same slave machine at the same time, it controls the slave machine.
  • the counter corresponding to each host in the machine starts counting.
  • the control module sets the access priority of the host corresponding to the counter to the highest priority.
  • the device determines the access priority of the host based on the number of times the host continuously accesses the slave, and realizes dynamic adjustment of the access priority, which not only avoids the unfairness of fixed priority, but also adjusts each access priority according to the actual access status of the slave.
  • the priority of the host can be applied to application scenarios that require high real-time response from the system.
  • the present disclosure also proposes a bus arbiter.
  • the bus controller 100 in the embodiment of the present disclosure includes a memory 110, a processor 120, and a bus arbitration program stored in the memory 110 and executable on the processor 120.
  • the processor 120 executes the bus arbitration program , implement the above bus arbitration method.
  • the processor 120 may be configured to execute the above method embodiments according to instructions in the computer program.
  • the processor 120 may include but is not limited to: General processor, Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA) or other programmable logic devices, discrete gates Or transistor logic devices, discrete hardware components, etc.
  • DSP Digital Signal Processor
  • ASIC Application Specific Integrated Circuit
  • FPGA Field Programmable Gate Array
  • the memory 110 includes but is not limited to: Volatile memory and/or non-volatile memory.
  • non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), electrically removable memory. Erase electrically programmable read-only memory (EEPROM, EEPROM) or flash memory.
  • Volatile memory may be Random Access Memory (RAM), which is used as an external cache.
  • RAM static random access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • DDR SDRAM double data rate synchronous dynamic random access memory
  • Enhanced SDRAM ESDRAM
  • SLDRAM synchronous link dynamic random access memory
  • DR RAM Direct Rambus RAM
  • the computer program can be divided into one or more modules, and the one or more modules are stored in the memory 110 and executed by the processor 120 to complete the tasks provided by the present application.
  • the one or more modules may be a series of computer program instruction segments capable of completing specific functions. The instruction segments are used to describe the execution process of the computer program in the bus arbiter 100 .
  • the bus arbiter 100 may also include: Transceiver 130 , the transceiver 130 may be connected to the processor 120 or the memory 110 .
  • the processor 120 can control the transceiver 130 to communicate with other devices. Specifically, it can send information or data to other devices, or receive information or data sent by other devices.
  • Transceiver 130 may include a transmitter and a receiver.
  • the transceiver 130 may further include an antenna, and the number of antennas may be one or more.
  • bus arbiter 100 various components of the bus arbiter 100 are connected through a bus system, where in addition to the data bus, the bus system also includes a power bus, a control bus and a status signal bus.
  • the bus arbiter realizes dynamic adjustment of access priority based on the above bus arbitration method, which not only avoids the unfairness of fixed priority, but also adjusts each master according to the actual access status of the slave.
  • the priority can be applied to application scenarios that require high real-time response from the system.
  • the present disclosure also proposes a main control chip.
  • the main control chip 200 of the embodiment of the present disclosure includes a memory 210, a processor 220, and a bus arbitration program stored in the memory 210 and executable on the processor 220.
  • the processor 220 executes the bus arbitration program, Implement the above bus arbitration method.
  • the processor 220 may be configured to execute the above method embodiments according to instructions in the computer program.
  • the processor 220 may include but is not limited to: General processor, Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA) or other programmable logic devices, discrete gates Or transistor logic devices, discrete hardware components, etc.
  • DSP Digital Signal Processor
  • ASIC Application Specific Integrated Circuit
  • FPGA Field Programmable Gate Array
  • the memory 210 includes but is not limited to: Volatile memory and/or non-volatile memory.
  • non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), electrically removable memory. Erase electrically programmable read-only memory (EEPROM, EEPROM) or flash memory.
  • Volatile memory may be Random Access Memory (RAM), which is used as an external cache.
  • RAM static random access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • DDR SDRAM double data rate synchronous dynamic random access memory
  • Enhanced SDRAM ESDRAM
  • SLDRAM synchronous link dynamic random access memory
  • DR RAM Direct Rambus RAM
  • the computer program can be divided into one or more modules, and the one or more modules are stored in the memory 210 and executed by the processor 220 to complete the tasks provided by the present application.
  • the one or more modules may be a series of computer program instruction segments capable of completing specific functions. The instruction segments are used to describe the execution process of the computer program in the main control chip 200 .
  • the main control chip 200 may also include: Transceiver 230 , the transceiver 230 may be connected to the processor 220 or the memory 210 .
  • the processor 220 can control the transceiver 230 to communicate with other devices. Specifically, it can send information or data to other devices, or receive information or data sent by other devices.
  • Transceiver 230 may include a transmitter and a receiver.
  • the transceiver 230 may further include an antenna, and the number of antennas may be one or more.
  • bus system where in addition to the data bus, the bus system also includes a power bus, a control bus and a status signal bus.
  • the main control chip realizes dynamic adjustment of access priority based on the above-mentioned bus arbitration method, which not only avoids the unfairness of fixed priority, but also adjusts each slave according to the actual access status of the slave.
  • the priority of the host can be applied to application scenarios that require high real-time response from the system.
  • a "computer-readable medium” may be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
  • Non-exhaustive list of computer readable media include the following: electrical connection with one or more wires (electronic device), portable computer disk cartridge (magnetic device), random access memory (RAM), Read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable compact disc read-only memory (CDROM).
  • the computer-readable medium may even be paper or other suitable medium on which the program may be printed, as the paper or other medium may be optically scanned, for example, and subsequently edited, interpreted, or otherwise suitable as necessary. process to obtain the program electronically and then store it in computer memory.
  • various parts of the present disclosure may be implemented in hardware, software, firmware, or combinations thereof.
  • various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system.
  • a logic gate circuit with a logic gate circuit for implementing a logic function on a data signal.
  • Discrete logic circuits application specific integrated circuits with suitable combinational logic gates, programmable gate arrays (PGA), field programmable gate arrays (FPGA), etc.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include at least one of these features.
  • “plurality” means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.
  • connection In this disclosure, unless otherwise explicitly stated and limited, the terms “installation”, “connection”, “connection”, “fixing” and other terms should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. , or integrated into one; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an internal connection between two elements or an interactive relationship between two elements, unless otherwise specified limitations. For those of ordinary skill in the art, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Quality & Reliability (AREA)
  • Mathematical Physics (AREA)
  • Bus Control (AREA)

Abstract

本公开公开了一种总线仲裁方法和装置、计算机可读存储介质及主控芯片，其中，方法包括：接收多个主机的访问请求信号（S1）；根据多个主机的访问请求信号确定多个主机同时访问同一个从机时，控制该从机中与每个主机对应的计数器开始计数（S2）；在多个计数器中的其中一个计数器连续计数的计数值超过预设阈值时，将该计数器对应的主机的访问优先级设置为最高优先级（S3）。

Description

总线仲裁方法和装置、计算机可读存储介质及主控芯片
相关申请的交叉引用
本公开要求于2022年05月26日提交的申请号为202210590188.4，名称为“总线仲裁方法和装置、计算机可读存储介质及主控芯片”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及集成电路设计技术领域，尤其涉及一种总线仲裁方法、一种计算机可读存储介质、一种总线仲裁装置、一种总线仲裁器和一种主控芯片。
 背景技术
在通用MCU（Micro Controller Unit，微控制单元）设计中，通常有两个或多个主机，比如CPU（Central Processing Unit，中央处理器）和DMA（Direct Memory Access，直接存储器访问）等，这些主机通常通过同一根AHB（Advanced High Performance Bus，高级高性能总线）总线对挂在总线上的从机(各种外设接口或定时器)进行访问。由于存在多个主机同时对同一个从机进行访问的情况，因此需要一个总线仲裁器来协调多个主机访问从机的顺序，即先响应一个主机访问从机的请求，其他主机的请求进行等待；等到当前主机访问结束后，另一个主机进行访问，以此类推，直到所有主机对该从机的访问结束。由于主机在不同时间段对于从机的访问有不同的响应要求，因此总线仲裁器能否及时响应众多主机的抢占请求成为了SOC（System On Chip，系统级芯片）芯片工作性能的一个关键指标。
公开内容
本公开旨在至少在一定程度上解决相关技术中的技术问题之一。为此，本公开的第一个目的在于提出一种总线仲裁方法,根据主机连续访问从机的次数确定主机的访问优先级，实现了对访问优先级的动态调整，既避免了固定优先级的非公平性，又可以根据从机的实际受访问情况调整各个主机的优先级，能够适用于对系统实时响应要求较高的应用场景。
本公开的第二个目的在于提出一种计算机可读存储介质。
本公开的第三个目的在于提出一种总线仲裁装置。
本公开的第四个目的在于提出一种总线仲裁器。
本公开的第五个目的在于提出一种主控芯片。
为达到上述目的，本公开第一方面实施例提出了一种总线仲裁方法，包括：接收多个主机的访问请求信号；根据多个主机的访问请求信号确定多个主机同时访问同一个从机时，控制该从机中与每个主机对应的计数器开始计数；在多个计数器中的其中一个计数器连续计数的计数值超过预设阈值时，将该计数器对应的主机的访问优先级设置为最高优先级。
根据本公开实施例的总线仲裁方法，首先，接收多个主机的访问请求信号，然后，根据多个主机的访问请求信号确定多个主机同时访问同一个从机时，控制该从机中与每个主机对应的计数器开始计数，在多个计数器中的其中一个计数器连续计数的计数值超过预设阈值时，将该计数器对应的主机的访问优先级设置为最高优先级。由此，该方法根据主机连续访问从机的次数确定主机的访问优先级，实现了对主机访问优先级的动态调整，既避免了固定优先级的非公平性，又可以根据从机的实际受访问情况调整各个主机的优先级，能够适用于对系统实时响应要求较高的应用场景。
另外，根据本公开上述实施例的总线仲裁方法，还可以具有如下的附加技术特征：
根据本公开的一个实施例，在多个计数器中的其中一个计数器连续计数的计数值超过预设阈值的过程中，若多个计数器中其余计数器的计数值为零，则确定该计数器为连续计数。
根据本公开的一个实施例，若多个计数器中其余计数器的计数值不为零，则将多个计数器的计数值清零。
根据本公开的一个实施例，将该计数器对应的主机的访问优先级设置为最高优先级之后，方法还包括：控制该计数器的计数值清零后重新开始计数；在预设时间内，若该计数器连续计数的计数值小于预设阈值，则按照轮询仲裁的方式确定多个主机的访问优先级。
根据本公开的一个实施例，将该计数器对应的主机的访问优先级设置为最高优先级之后，方法还包括：按照轮询仲裁的方式确定多个主机中的其余主机的访问优先级。
为达到上述目的，本公开第二方面实施例提出了一种计算机可读存储介质，其上存储有总线仲裁方法程序，该总线仲裁方法程序被处理器执行时实现上述的总线仲裁方法。
根据本公开实施例的计算机可读存储介质，通过处理器执行其上存储的总线仲裁方法程序时，实现上述的总线仲裁方法，基于上述总线总裁方法，实现了对访问优先级的动态调整，既避免了固定优先级的非公平性，又可以根据从机的实际受访问情况调整各个主机的优先级，能够适用于对系统实时响应要求较高的应用场景。
为达到上述目的，本公开第三方面实施例提出的一种总线仲裁装置，包括：接收单元，用于接收多个主机的访问请求信号；控制模块，用于根据多个主机的访问请求信号确定多个主机同时访问同一个从机时，控制该从机中与每个主机对应的计数器开始计数；控制模块，还用于在多个计数器中的其中一个计数器连续计数的计数值超过预设阈值时，将该计数器对应的主机的访问优先级设置为最高优先级。
根据本公开实施例的总线仲裁装置，通过接收单元接收多个主机的访问请求信号，控制模块根据多个主机的访问请求信号确定多个主机同时访问同一个从机时，控制该从机中与每个主机对应的计数器开始计数，控制模块在多个计数器中的其中一个计数器连续计数的计数值超过预设阈值时，将该计数器对应的主机的访问优先级设置为最高优先级。
为达到上述目的，本公开第四方面实施例提出了一种总线仲裁器，包括存储器、处理器及存储在存储器上并可在处理器上运行的总线仲裁程序，处理器执行总线仲裁程序时，实现上述的总线仲裁方法。
为达到上述目的，本公开第五方面实施例提出了一种主控芯片，包括存储器、处理器及存储在存储器上并可在处理器上运行的总线仲裁程序，处理器执行总线仲裁程序时，实现上述的总线仲裁方法。
本公开附加的方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本公开的实践了解到。
 附图说明
图1为根据本公开实施例的总线仲裁方法的流程图；
图2为根据本公开一个实施例的总线仲裁器的方框示意图；
图3为根据本公开一个实施例的两个主机采用轮询仲裁策略访问同一从机时的波形图；
图4为图3中主机0被强制升级为最高优先级时的波形图；
图5为图3中主机1被强制升级为最高优先级的波形图；
图6为根据本公开一个具体实施例的总线仲裁方法的流程图；
图7为根据本公开实施例的总线仲裁装置的方框示意图；
图8为根据本公开实施例的总线仲裁器的方框示意图；
图9为根据本公开实施例的主控芯片的方框示意图。
具体实施方式
下面详细描述本公开的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本公开，而不能理解为对本公开的限制。
下面参考附图描述本公开实施例提出的总线仲裁方法、计算机可读存储介质、总线仲裁装置和主控芯片。
在相关技术中，常用的总线仲裁器分为轮询仲裁器和固定优先级仲裁器。
其中，轮询仲裁器的原理是：初始情况下MASTER0（主机0）的优先级最高，MASTER1（主机1）的优先级第二，MASTER2（主机2）的优先级第三……；当响应了MASTER0的请求后，MASTER0的优先级变成最低，MASTER1的优先级变为最高，MASTER2的优先级变为第二 ……。轮询仲裁器的优点是每个主机的优先级循环变化，整体的公平性得到很好的保证。缺点是当某个主机在特定时间内频繁访问从机并希望得到最快响应时，该主机的最高优先级得不到保证，降低了总线利用率。
而固定优先级仲裁器的原理是：MASTER0的优先级最高，MASTER1的优先级第二，MASTER2的优先级第三……；当响应了MASTER0的请求后，MASTER0的优先级仍然保持最高，MASTER1的优先级第二，MASTER2的优先级第三。即所有主机对于同一个从机的访问优先级是固定的。固定优先级仲裁器的优点是：可以根据实际应用的需求，把对从机响应要求最快的主机设置成最高优先级，从而避免了该主机的性能损失，同时可以简化设计，减少芯片面积并节省成本。缺点是不能动态调节各个主机的优先级次序，欠缺灵活性。
图1为根据本公开实施例的总线仲裁方法的流程图。
在本公开的一个实施例中，该总线仲裁方法可通过如图2所示的总线仲裁器实现。该总线仲裁器包括从机受访次数计数器10、仲裁状态机20和输出控制模块30三个模块，从机受访次数计数器10负责累计每个主机访问从机的次数，并产生标志信号提供给仲裁状态机，仲裁状态,20负责处理总线访问的时序和分配优先级，输出控制模,30负责产生访问从机所需的控制信号。下面以两个主机访问同一个从机A为例对该总线总裁方法进行详细说明，其中两个主机分别为主机0和主机1。
如图1所示，本公开实施例的总线仲裁方法，可包括以下步骤：
S1，接收多个主机的访问请求信号。也就是说，从机A通过主机0总线接收主机0的访问请求信号，通过主机1总线接收主机1的访问请求信号。
S2，根据多个主机的访问请求信号确定多个主机同时访问同一个从机时，控制该从机中与每个主机对应的计数器开始计数。
具体地，当从机A只接收到主机0或主机1的访问请求信号时，认定为单一主机对应一个从机的信号访问过程，不需要优先权的设置，直接控制相应主机对从机A进行访问，从机A中与每个主机对应的计数器不工作。当从机A同时接收到主机0和主机1的访问请求信号时，判定为多个主机对应同一个从机的信号访问过程，则需要进行优先权的设置，此时，总线仲裁器可按照预设策略确定主机0和主机1的访问优先权，并对从机A进行访问。当主判定主机0和主机1对从机A结束访问后，从机A中与每个主机对应的计数器开始计数，即从机A内的从机访问计数器1对主机1的访问次数进行计数，从机受访计数器0对主机0的访问次数进行计数。
S3，在多个计数器中的其中一个计数器连续计数的计数值超过预设阈值时，将该计数器对应的主机的访问优先级设置为最高优先级。其中，预设阈值可根据实际情况进行设定。
具体而言，以预设阈值为M为例，若当前从机A内的从机访问计数器0连续计数的计数值大于预设阈值M，那么将主机0的访问优先级强制升级为最高优先级。在主机0的访问优先级设置为最高优先级后，在主机0和主机1同时向从机A发送访问请求信号时，输出控制模块首先将主机0的访问请求信号发送给从机A，然后再将主机1的访问请求信号发送给从机A。由此，该方法在初始状态时，各个主机采用预设策略决定主机的访问优先级，同时从机中与每个主机对应的计数器开始计数，当某一个主机独立访问同一个从机的连续次数超过预设阈值，则把该主机的优先级强制升级为最高优先级。也就是说，通过对主机访问从机的次数进行动态监控，将短时间内需要频繁访问从机的主机的访问权限配置为最高优先级，避免了主机性能的损失。
该总线仲裁方法在仅有一个主机访问从机时，计数器不工作，当判定有多个主机同时访问从机时，从机内多个主机分别对应的计数器开始计数工作，并在一个计数器实现连续计数的计数值大于预设阈值时，将该计数器对应的主机的访问优先级设置为最高优先级，在后续多个主机对从机的访问过程中，若该主机与其他主机发生访问冲突，均将该主机设置为第一访问位，首先对从机进行访问，其他主机可在该主机对从机访问结束后，再按照预设访问策略进行访问操作。由此，该方法根据主机连续访问从机的次数确定主机的访问优先级，实现了对访问优先级的动态调整，既避免了固定优先级的非公平性，又可以根据从机的实际受访问情况调整各个主机的优先级，能够适用于对系统实时响应要求较高的应用场景。
可以理解的是，在判定当前时间节点仅一个主机对从机进行访问时，无需受优先级访问策略的影响，当前主机直接对从机进行访问。
根据本公开的一个实施例，在多个计数器中的其中一个计数器连续计数的计数值超过预设阈值的过程中，若多个计数器中其余计数器的计数值为零，则确定该计数器为连续计数。
也就是说，在该计数器连续计数过程中，其他计数器未进行计数，则认定该计数器为连续计数，即在该计数器对应的主机对从机的访问过程中，其他主机均未对从机进行访问。举例来说，上述从机访问计数器0实现连续计数，则从机访问计数器1在该过程中没有计数操作，也就是说，在该阶段中，从机A仅接收到主机0发送的访问请求信号，主机1未向从机A发送访问请求信号，以此认定为从机访问计数器0为连续计数。
根据本公开的一个实施例，若多个计数器中其余计数器的计数值不为零，则将多个计数器的计数值清零。
具体地，若判定主机0和主机1对从机A进行访问，则通过从机访问计数器0对主机0的访问次数进行计数，从机访问计数器1对主机1的访问次数进行计数。可以理解的是，当判定主机0和主机1都对从机A进行访问时，控制从机访问计数器0和从机访问计数器1置零，然后开始计数操作。举例来说，当主机0向从机A发送访问请求信号时，从机访问计数器0计数为1，从机访问计数器1计数为0；当下一发送给从机A的访问请求信号还是主机0发送的，则从机访问计数器0计数为2，从机访问计数器1计数为0；依次类推，直至从机访问计数器0计数为M+1，超过预设阈值M时，从机访问计数器1的计数仍为0，则判定从机访问计数器0为连续计数。若从机访问计数器0计数为2，从机访问计数器1计数为0后，下一访问信号为主机1发送给从机A的访问请求信号，则从机访问计数器0计数值为2，从机访问计数器1计数为1，判定，主机0未实现连续访问，此时，将从机访问计数器0和从机访问计数器1的计数值全部清零，待下一次确定多个主机同时访问同一个从机A时，再重新进行计数操作。
也就是说，在从机中一个计数器连续计数的计数值未达到预设阈值时，若另一个计数器也被触发计数，则前一个计数器的计数值将被清零，必须重新开始计数，从而保证只出现一个计数器连续计数的计数值超过预设阈值的情况。
根据本公开的一个实施例，将该计数器对应的主机的访问优先级设置为最高优先级之后，方法还包括：控制该计数器的计数值清零后重新开始计数；在预设时间内，若该计数器连续计数的计数值小于预设阈值，则按照轮询仲裁的方式确定多个主机的访问优先级。其中，预设时间可根据实际情况进行设定。
具体地，当根据上述计数器的连续计数操作确定主机0的优先级为最高优先级后，将从机访问计数器0的计数值清零，然后控制从机访问计数器0重新进行计数操作。若在预设时间内，从机访问计数器0连续计数的计数值超过了预设阈值M，则继续将主机0的访问优先级设置为最高优先级，否则，控制主机0和主机1以轮询仲裁的方式确定访问的优先权，对从机A进行访问，同时控制从机访问计数器0和从机访问计数器1重新按照上述方法进行计数，直至某一计数器连续计数的计数值超过预设阈值M，具体可参照上述方法描述，此处不再赘述。
上述轮询仲裁的方式可以为第一次主机1和主机0同时访问从机A时，控制主机1先访问从机A，主机0进行等待，待主机1访问完成后，主机0再对从机A进行访问。在下一次主机1和主机0同时访问从机A时，使主机0先访问从机A，主机1进行等待，待主机0访问完成后，主机1再对从机A进行访问，以此类推，实现轮询仲裁的访问控制。主机0和主机1采用轮询仲裁的方式访问从机0时的波形如图3所示，其中，HCLK表示时钟信号。M0_VALD表示主机0访问从机A的信号，高电平表示主机0向从机A发出访问请求信号。MI_VALD表示主机1访问从机A的信号，高电平表示主机1向从机A发出访问请求信号。STATE表示状态，IDIE表示空闲状态，M0表示主机0正在访问从机A，MISTER表示MO访问时，M1等待；M1表示主机1正在访问从机A，MISTER表示M1访问时，M0等待。M1_HREADYOUT表示M1访问从机A期间的电平信号，M0_HREADYOUT表示M0访问从机A期间的电平信号。
进一步地，除上述是否维持主机最高优先级的确定方法，还可以设置重置预设周期，以该重置预设周期作为最高优先级的维持周期，当主机的最高优先级持续时间满足重置预设周期时，则恢复轮询仲裁。举例来说，在主机0的访问优先级设置为最高优先级后开始计时，在重置预设周期内均将主机0的访问优先级设置为最高优先级，当计时超过重置预设周期时，自动恢复为轮询仲裁的方式来确定主机的优先级。可以理解的是，当恢复为轮询仲裁的优先级确认方式时，计数器清零重新开始计数，然后当其中一个计数器连续计数的计数值超过预设阈值M后，继续认定对应的主机的访问优先级为最高优先级。
由此，该方法可以在访问优先级为最高优先级的主机的频繁访问请求结束一段时间后，迅速恢复为轮询仲裁的方式，使其仍可兼顾各个主机访问优先级的公平性。此外，该方法通过尽量少的软件配置，仅增加少数的定时器资源，就可以达到总线性能提升的目的。
根据本公开的一个实施例，将该计数器对应的主机的访问优先级设置为最高优先级之后，该总线仲裁方法还包括：按照轮询仲裁的方式确定多个主机中的其余主机的访问优先级。
以主机0、主机1和主机2同时对从机A进行访问为例，根据计数器连续计数的计数值确定主机0的访问优先级为最高优先级，则首先控制主机0对从机A进行访问，主机1和主机2等待，并在主机0对从机A访问结束后，主机1和主机2按照轮询仲裁的方式进行对从机A的访问，例如，该次轮询仲裁确定的访问顺序为主机2、主机1，则在确定主机0对从机A访问结束后，控制主机2对从机A进行访问，主机1继续等待，并在确定主机2对从机A访问结束后，主机2再对从机A进行访问。
根据本公开的一个实施例，在将该计数器对应的主机的访问优先级设置为最高优先级之前，方法还包括：按照轮询仲裁的方式确定多个主机的访问优先级。
具体地，该方法在接收多个主机的访问请求信号后，若确定为多个主机同时访问同一个从机，则首先以轮询仲裁的方式确定该多个主机的访问优先级，同时控制从机中与每个主机对应的计数器开始计数。直至出现某一计数器连续计数的计数值大于预设阈值M，将该计数器对应的主机的访问优先级设置为最高级，否则，继续以轮询仲裁的方式确定主机的访问优先级。
进一步地，该总线总裁方法在初始状态时，各个主机采用轮询仲裁的方式决定自身优先级，同时内部的从机受访计数器开始计数，当某个主机访问同一从机的连续次数超过了预设阈值M次，则把该主机的优先级强制升级为最高优先级。该方法在采用轮询仲裁方式的前提下，通过对从机访问计数器进行动态监控，将短时间内需要频繁访问从机的主机的访问权限配置为最高优先级，避免了该主机的性能损失。
以图2为例，主机0和主机1的总线信号分别输入到总线仲裁器的三个模块进行运算，当主机0连续访问从机A的次数大于预设阈值M，且期间没有主机1的访问请求信号发生时，则从机访问计数器0的输出信号MST0_EN为高电平，表示主机0的访问优先级强制为最高优先级，波形图如图4所示，其中，MST0_EN变为高电平的时候为主机0被强制为最高优先级的时刻，之后在判定主机1和主机0为同时访问，通过输出控制模块30控制主机0对从机A先进行访问，主机1进行等待，待判断主机0访问完成后，输出控制模块30控制主机1再对从机A进行访问。
当主机1连续访问从机A的次数大于预设阈值M，且期间没有主机0的访问请求信号发生时，则从机访问计数器1的输出信号MST1_EN为高电平，表示主机1的访问优先级强制为最高优先级，波形图如图5所示，其中，MST1_EN变为高电平的时候为主机1被强制为最高优先级的时刻，之后在判定主机1和主机0为同时访问，通过输出控制模块30控制主机1对从机A先进行访问，主机0进行等待，待判断主机1访问完成后，输出控制模块30控制主机0再对从机A进行访问。
当主机0和主机1连续访问从机A的次数小于等于预设阈值M，则输出信号MST0_EN、MST1_EN均为低高电，仲裁状态机控制输出控制模块30采用轮询仲裁的方式，波形图如图3所示。具体来说，仲裁状态机连接主机0总线和主机1总线并对主机1和主机0的访问时间进行判断，若判定主机1和主机0为同时访问，通过输出控制模块30控制主机1对从机A先进行访问，主机0进行等待，待判断主机1访问完成后，输出控制模块30控制主机0再对从机A进行访问。若在下次判定主机1和主机0为同时访问时，仲裁状态机判定两个计数器的计数值仍小于预设阈值M，则仲裁状态机继续执行轮询仲裁模式，通过输出控制模块30控制主机0对从机A先进行访问，主机1进行等待，待判断主机0访问完成后，输出控制模块30控制主机1再对从机A进行访问。
作为本申请的一个具体实施例，如图6所示，该总线仲裁方法，执行步骤可包括：
S101，接收多个主机的访问请求信号。
S102，确定多个主机同时访问同一个从机时，所有主机采用轮询仲裁方式。
S103，控制与每个主机对应的计数器开始计数。
S104，判断计数器连续计数的计数值是否小于等于预设阈值M。若是，执行步骤S102；若否，执行步骤S105。
S105，将该计数器对应的主机的访问优先级设置为最高优先级，其余主机采用轮询仲裁方式。其中，该计数器为连续计数的计数值大于预设阈值M。
S106，将该计数器的计数值清零。
S107，判断预设时间内，该计数器连续计数的计数值是否小于预设阈值M。若是，执行步骤S102；若否，执行步骤S105。
综上，根据本公开实施例的总线仲裁方法，首先，接收多个主机的访问请求信号，然后，根据多个主机的访问请求信号确定多个主机同时访问同一个从机时，控制该从机中与每个主机对应的计数器开始计数，在多个计数器中的其中一个计数器连续计数的计数值超过预设阈值时，将该计数器对应的主机的访问优先级设置为最高优先级。由此，该方法根据主机连续访问从机的次数确定主机的访问优先级，实现了对访问优先级的动态调整，既避免了固定优先级的非公平性，又可以根据从机的实际受访问情况调整各个主机的优先级，能够适用于对系统实时响应要求较高的应用场景。
对应上述实施例，本公开还提出了一种计算机可读存储介质。
本公开实施例的计算机可读存储介质，其上存储有总线仲裁方法程序，该总线仲裁方法程序被处理器执行时实现上述的总线仲裁方法。
根据本公开实施例的计算机可读存储介质，通过处理器执行其上存储的总线仲裁方法程序时，实现上述的总线仲裁方法，实现了对访问优先级的动态调整，既避免了固定优先级的非公平性，又可以根据从机的实际受访问情况调整各个主机的优先级，能够适用于对系统实时响应要求较高的应用场景。
对应上述实施例，本公开还提出了一种总线仲裁装置。
如图7所示，本公开实施例的总线仲裁装置，可包括：接收单元40和控制模块50。
其中，接收单元40用于接收多个主机的访问请求信号。控制模块50用于根据多个主机的访问请求信号确定多个主机同时访问同一个从机时，控制该从机中与每个主机对应的计数器开始计数。控制模块50还用于在多个计数器中的其中一个计数器连续计数的计数值超过预设阈值时，将该计数器对应的主机的访问优先级设置为最高优先级。
根据本公开的一个实施例，控制模块50还用于，在多个计数器中的其中一个计数器连续计数的计数值超过预设阈值的过程中，若多个计数器中其余计数器的计数值为零，则确定该计数器为连续计数。
根据本公开的一个实施例，控制模块50还用于，若多个计数器中其余计数器的计数值不为零，则将多个计数器的计数值清零。
根据本公开的一个实施例，控制模块50将该计数器对应的主机的访问优先级设置为最高优先级之后，具体还用于：将该计数器的计数值清零，并在延时预设时间后，控制该计数器开始计数；若该计数器连续计数的计数值小于预设阈值，则按照轮询仲裁的方式确定多个主机的访问优先级。
根据本公开的一个实施例，控制模块50将该计数器对应的主机的访问优先级设置为最高优先级之后，具体还用于：按照轮询仲裁的方式确定多个主机中的其余主机的访问优先级。
需要说明的是，本公开实施例的总线仲裁装置中未披露的细节，请参照本公开上述实施例的总线仲裁方法中所披露的细节，具体这里不再赘述。
综上，根据本公开实施例的总线仲裁装置，通过接收单元接收多个主机的访问请求信号，控制模块根据多个主机的访问请求信号确定多个主机同时访问同一个从机时，控制该从机中与每个主机对应的计数器开始计数，控制模块在多个计数器中的其中一个计数器连续计数的计数值超过预设阈值时，将该计数器对应的主机的访问优先级设置为最高优先级。该装置根据主机连续访问从机的次数确定主机的访问优先级，实现了对访问优先级的动态调整，既避免了固定优先级的非公平性，又可以根据从机的实际受访问情况调整各个主机的优先级，能够适用于对系统实时响应要求较高的应用场景。
对应上述实施例，本公开还提出了一种总线仲裁器。
如图8所示，本公开实施例的总线总裁器100，包括存储器110、处理器120及存储在存储器110上并可在处理器120上运行的总线仲裁程序，处理器120执行总线仲裁程序时，实现上述的总线仲裁方法。
例如，该处理器120可用于根据该计算机程序中的指令执行上述方法实施例。
在本申请的一些实施例中，该处理器120可以包括但不限于：
通用处理器、数字信号处理器（Digital Signal Processor，DSP）、专用集成电路（Application Specific Integrated Circuit，ASIC）、现场可编程门阵列（Field Programmable Gate Array，FPGA）或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等等。
在本申请的一些实施例中，该存储器110包括但不限于：
易失性存储器和/或非易失性存储器。其中，非易失性存储器可以是只读存储器（Read-Only Memory，ROM）、可编程只读存储器（Programmable ROM，PROM）、可擦除可编程只读存储器（Erasable PROM，EPROM）、电可擦除可编程只读存储器（Electrically EPROM，EEPROM）或闪存。易失性存储器可以是随机存取存储器（Random Access Memory，RAM），其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器（Static RAM，SRAM）、动态随机存取存储器（Dynamic RAM，DRAM）、同步动态随机存取存储器（Synchronous DRAM，SDRAM）、双倍数据速率同步动态随机存取存储器（Double Data Rate SDRAM，DDR SDRAM）、增强型同步动态随机存取存储器（Enhanced SDRAM，ESDRAM）、同步连接动态随机存取存储器（synch link DRAM，SLDRAM）和直接内存总线随机存取存储器（Direct Rambus RAM，DR RAM）。
在本申请的一些实施例中，该计算机程序可以被分割成一个或多个模块，该一个或者多个模块被存储在该存储器110中，并由该处理器120执行，以完成本申请提供的方法。该一个或多个模块可以是能够完成特定功能的一系列计算机程序指令段，该指令段用于描述该计算机程序在该总线仲裁器100中的执行过程。
如图8所示，该总线仲裁器100还可包括：
收发器130，该收发器130可连接至该处理器120或存储器110。
其中，处理器120可以控制该收发器130与其他设备进行通信，具体地，可以向其他设备发送信息或数据，或接收其他设备发送的信息或数据。收发器130可以包括发射机和接收机。收发器130还可以进一步包括天线，天线的数量可以为一个或多个。
应当理解，该总线仲裁器100的各个组件通过总线系统相连，其中，总线系统除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。
根据本公开实施例的总线仲裁器，基于上述总线仲裁方法，实现了对访问优先级的动态调整，既避免了固定优先级的非公平性，又可以根据从机的实际受访问情况调整各个主机的优先级，能够适用于对系统实时响应要求较高的应用场景。
对应上述实施例，本公开还提出了一种主控芯片。
如图9所示，本公开实施例的主控芯片200包括存储器210、处理器220及存储在存储器210上并可在处理器220上运行的总线仲裁程序，处理器220执行总线仲裁程序时，实现上述的总线仲裁方法。
例如，该处理器220可用于根据该计算机程序中的指令执行上述方法实施例。
在本申请的一些实施例中，该处理器220可以包括但不限于：
通用处理器、数字信号处理器（Digital Signal Processor，DSP）、专用集成电路（Application Specific Integrated Circuit，ASIC）、现场可编程门阵列（Field Programmable Gate Array，FPGA）或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等等。
在本申请的一些实施例中，该存储器210包括但不限于：
易失性存储器和/或非易失性存储器。其中，非易失性存储器可以是只读存储器（Read-Only Memory，ROM）、可编程只读存储器（Programmable ROM，PROM）、可擦除可编程只读存储器（Erasable PROM，EPROM）、电可擦除可编程只读存储器（Electrically EPROM，EEPROM）或闪存。易失性存储器可以是随机存取存储器（Random Access Memory，RAM），其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器（Static RAM，SRAM）、动态随机存取存储器（Dynamic RAM，DRAM）、同步动态随机存取存储器（Synchronous DRAM，SDRAM）、双倍数据速率同步动态随机存取存储器（Double Data Rate SDRAM，DDR SDRAM）、增强型同步动态随机存取存储器（Enhanced SDRAM，ESDRAM）、同步连接动态随机存取存储器（synch link DRAM，SLDRAM）和直接内存总线随机存取存储器（Direct Rambus RAM，DR RAM）。
在本申请的一些实施例中，该计算机程序可以被分割成一个或多个模块，该一个或者多个模块被存储在该存储器210中，并由该处理器220执行，以完成本申请提供的方法。该一个或多个模块可以是能够完成特定功能的一系列计算机程序指令段，该指令段用于描述该计算机程序在该主控芯片200中的执行过程。
如图9所示，该主控芯片200还可包括：
收发器230，该收发器230可连接至该处理器220或存储器210。
其中，处理器220可以控制该收发器230与其他设备进行通信，具体地，可以向其他设备发送信息或数据，或接收其他设备发送的信息或数据。收发器230可以包括发射机和接收机。收发器230还可以进一步包括天线，天线的数量可以为一个或多个。
应当理解，该主控芯片200的各个组件通过总线系统相连，其中，总线系统除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。
根据本公开实施例的主控芯片，基于上述的总线仲裁方法，实现了对访问优先级的动态调整，既避免了固定优先级的非公平性，又可以根据从机的实际受访问情况调整各个主机的优先级，能够适用于对系统实时响应要求较高的应用场景。
需要说明的是，在流程图中表示或在此以其他方式描述的逻辑和/或步骤，例如，可以被认为是用于实现逻辑功能的可执行指令的定序列表，可以具体实现在任何计算机可读介质中，以供指令执行系统、装置或设备（如基于计算机的系统、包括处理器的系统或其他可以从指令执行系统、装置或设备取指令并执行指令的系统）使用，或结合这些指令执行系统、装置或设备而使用。就本说明书而言，"计算机可读介质"可以是任何可以包含、存储、通信、传播或传输程序以供指令执行系统、装置或设备或结合这些指令执行系统、装置或设备而使用的装置。计算机可读介质的更具体的示例（非穷尽性列表）包括以下：具有一个或多个布线的电连接部（电子装置），便携式计算机盘盒（磁装置），随机存取存储器（RAM），只读存储器（ROM），可擦除可编辑只读存储器（EPROM或闪速存储器），光纤装置，以及便携式光盘只读存储器（CDROM）。另外，计算机可读介质甚至可以是可在其上打印所述程序的纸或其他合适的介质，因为可以例如通过对纸或其他介质进行光学扫描，接着进行编辑、解译或必要时以其他合适方式进行处理来以电子方式获得所述程序，然后将其存储在计算机存储器中。
应当理解，本公开的各部分可以用硬件、软件、固件或它们的组合来实现。在上述实施方式中，多个步骤或方法可以用存储在存储器中且由合适的指令执行系统执行的软件或固件来实现。例如，如果用硬件来实现，和在另一实施方式中一样，可用本领域公知的下列技术中的任一项或他们的组合来实现：具有用于对数据信号实现逻辑功能的逻辑门电路的离散逻辑电路，具有合适的组合逻辑门电路的专用集成电路，可编程门阵列（PGA），现场可编程门阵列（FPGA）等。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本公开的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系，除非另有明确的限定。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (10)

  1. 总线仲裁方法，包括：
    接收多个主机的访问请求信号；
    根据所述多个主机的访问请求信号确定所述多个主机同时访问同一个从机时，控制该从机中与每个主机对应的计数器开始计数；
    在多个计数器中的其中一个计数器连续计数的计数值超过预设阈值时，将该计数器对应的主机的访问优先级设置为最高优先级。
  2. 根据权利要求1所述的方法，其中，在所述多个计数器中的其中一个计数器连续计数的计数值超过所述预设阈值的过程中，若所述多个计数器中其余计数器的计数值为零，则确定所述该计数器为连续计数。
  3. 根据权利要求2所述的方法，其中，若所述多个计数器中其余计数器的计数值不为零，则将所述多个计数器的计数值清零。
  4. 根据权利要求1-3中任一项所述的方法，其中，将该计数器对应的主机的访问优先级设置为最高优先级之后，所述方法还包括：
    控制所述该计数器的计数值清零后重新开始计数；
    在预设时间内，若所述该计数器连续计数的计数值小于所述预设阈值，则按照轮询仲裁的方式确定所述多个主机的访问优先级。
  5. 根据权利要求1-4中任一项所述的方法，其中，将该计数器对应的主机的访问优先级设置为最高优先级之后，所述方法还包括：
    按照轮询仲裁的方式确定所述多个主机中的其余主机的访问优先级。
  6. 根据权利要求1-5中任一项所述的方法，其中，在将该计数器对应的主机的访问优先级设置为最高优先级之前，所述方法还包括：
    按照轮询仲裁的方式确定所述多个主机的访问优先级。
  7. 计算机可读存储介质，其上存储有总线仲裁方法程序，该总线仲裁方法程序被处理器执行时实现根据权利要求1-6中任一项所述的总线仲裁方法。
  8. 总线仲裁装置，包括：
    接收单元，用于接收多个主机的访问请求信号；
    控制模块，用于根据所述多个主机的访问请求信号确定所述多个主机同时访问同一个从机时，控制该从机中与每个主机对应的计数器开始计数；
    所述控制模块，还用于在多个计数器中的其中一个计数器连续计数的计数值超过预设阈值时，将该计数器对应的主机的访问优先级设置为最高优先级。
  9. 总线仲裁器，包括存储器、处理器及存储在存储器上并可在处理器上运行的总线仲裁程序，所述处理器执行所述总线仲裁程序时，实现根据权利要求1-6中任一项所述的总线仲裁方法。
  10. 主控芯片，包括存储器、处理器及存储在存储器上并可在处理器上运行的总线仲裁程序，所述处理器执行所述总线仲裁程序时，实现根据权利要求1-6中任一项所述的总线仲裁方法。
PCT/CN2023/078646 2022-05-26 2023-02-28 总线仲裁方法和装置、计算机可读存储介质及主控芯片 WO2023226497A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210590188.4 2022-05-26
CN202210590188.4A CN114911727A (zh) 2022-05-26 2022-05-26 总线仲裁方法和装置、计算机可读存储介质及主控芯片

Publications (1)

Publication Number Publication Date
WO2023226497A1 true WO2023226497A1 (zh) 2023-11-30

Family

ID=82768813

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/078646 WO2023226497A1 (zh) 2022-05-26 2023-02-28 总线仲裁方法和装置、计算机可读存储介质及主控芯片

Country Status (2)

Country Link
CN (1) CN114911727A (zh)
WO (1) WO2023226497A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114911727A (zh) * 2022-05-26 2022-08-16 上海美仁半导体有限公司 总线仲裁方法和装置、计算机可读存储介质及主控芯片
CN117807000A (zh) * 2024-02-29 2024-04-02 浪潮电子信息产业股份有限公司 通道总线仲裁电路、加速装置、方法、系统、装置及介质

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115129645B (zh) * 2022-08-31 2023-01-24 苏州浪潮智能科技有限公司 一种基于总线的事务处理方法、系统、存储介质及设备
CN115834282B (zh) * 2022-11-07 2024-08-06 交控科技股份有限公司 一种can总线通信方法、装置、设备及可读存储介质
CN115858430B (zh) * 2023-02-02 2023-05-09 摩尔线程智能科技(北京)有限责任公司 图形处理器的访存优化方法、设备及计算机可读介质
CN116225995B (zh) * 2023-05-08 2023-08-04 苏州浪潮智能科技有限公司 一种总线系统及芯片
CN117880364B (zh) * 2024-03-12 2024-06-11 苏州仰思坪半导体有限公司 一种数据传输方法、系统以及相关装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1096387A1 (en) * 1999-10-26 2001-05-02 Bull S.A. An arbitration unit for a bus
JP2007094579A (ja) * 2005-09-27 2007-04-12 Casio Electronics Co Ltd メモリ制御装置
JP2011076160A (ja) * 2009-09-29 2011-04-14 Nec Corp 調停優位性の切り替え方法、調停装置、及びプロセッサ
US20130073773A1 (en) * 2011-09-15 2013-03-21 Yuuji Matsuda Access control apparatus, image forming apparatus, and access control method
CN114185823A (zh) * 2022-02-17 2022-03-15 深圳比特微电子科技有限公司 仲裁器、仲裁方法、控制器和芯片
CN114911727A (zh) * 2022-05-26 2022-08-16 上海美仁半导体有限公司 总线仲裁方法和装置、计算机可读存储介质及主控芯片

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11250005A (ja) * 1998-03-05 1999-09-17 Nec Corp バス制御方法、バス制御装置及びバス制御プログラムを記憶した記憶媒体
US7284080B2 (en) * 2003-07-07 2007-10-16 Sigmatel, Inc. Memory bus assignment for functional devices in an audio/video signal processing system
JP4907166B2 (ja) * 2005-01-12 2012-03-28 パナソニック株式会社 リソース管理装置
JP4847036B2 (ja) * 2005-03-30 2011-12-28 キヤノン株式会社 バスアクセスを調停する制御装置およびデータ処理装置の制御方法
JP2007241918A (ja) * 2006-03-13 2007-09-20 Fujitsu Ltd プロセッサ装置
JP4847615B2 (ja) * 2011-01-31 2011-12-28 キヤノン株式会社 バスアクセスを調停する制御装置およびその方法
JP2019113917A (ja) * 2017-12-21 2019-07-11 ルネサスエレクトロニクス株式会社 データ処理装置、及びデータ処理装置の制御方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1096387A1 (en) * 1999-10-26 2001-05-02 Bull S.A. An arbitration unit for a bus
JP2007094579A (ja) * 2005-09-27 2007-04-12 Casio Electronics Co Ltd メモリ制御装置
JP2011076160A (ja) * 2009-09-29 2011-04-14 Nec Corp 調停優位性の切り替え方法、調停装置、及びプロセッサ
US20130073773A1 (en) * 2011-09-15 2013-03-21 Yuuji Matsuda Access control apparatus, image forming apparatus, and access control method
CN114185823A (zh) * 2022-02-17 2022-03-15 深圳比特微电子科技有限公司 仲裁器、仲裁方法、控制器和芯片
CN114911727A (zh) * 2022-05-26 2022-08-16 上海美仁半导体有限公司 总线仲裁方法和装置、计算机可读存储介质及主控芯片

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114911727A (zh) * 2022-05-26 2022-08-16 上海美仁半导体有限公司 总线仲裁方法和装置、计算机可读存储介质及主控芯片
CN117807000A (zh) * 2024-02-29 2024-04-02 浪潮电子信息产业股份有限公司 通道总线仲裁电路、加速装置、方法、系统、装置及介质
CN117807000B (zh) * 2024-02-29 2024-05-28 浪潮电子信息产业股份有限公司 通道总线仲裁电路、加速装置、方法、系统、装置及介质

Also Published As

Publication number Publication date
CN114911727A (zh) 2022-08-16

Similar Documents

Publication Publication Date Title
WO2023226497A1 (zh) 总线仲裁方法和装置、计算机可读存储介质及主控芯片
US7350004B2 (en) Resource management device
EP3553646A1 (en) Operation instruction scheduling method and apparatus for nand flash memory device
US6151651A (en) Communication link with isochronous and asynchronous priority modes coupling bridge circuits in a computer system
JP3596799B2 (ja) バスを動的に制御するシステムおよび方法
US20080195806A1 (en) System and method for controlling memory operations
US7213084B2 (en) System and method for allocating memory allocation bandwidth by assigning fixed priority of access to DMA machines and programmable priority to processing unit
US6148357A (en) Integrated CPU and memory controller utilizing a communication link having isochronous and asynchronous priority modes
US10678723B2 (en) Urgent in-band interrupts on an I3C bus
JPH11513158A (ja) 並列パケット化されたモジュール間調停高速制御およびデータバス
US6542940B1 (en) Method and apparatus for controlling task execution in a direct memory access controller
WO2019139684A1 (en) Priority scheme for fast arbitration procedures
CN109002408B (zh) 总线仲裁方法和系统
CN116868167A (zh) 操作系统的运行控制方法和装置，以及嵌入式系统和芯片
JPH06231074A (ja) システムバスの多重アクセス方式
JP2011095967A (ja) バス共有システム
US11662948B2 (en) Norflash sharing
US8943238B2 (en) Operations using direct memory access
US6532507B1 (en) Digital signal processor and method for prioritized access by multiple core processors to shared device
US10318457B2 (en) Method and apparatus for split burst bandwidth arbitration
JP2008513886A (ja) バスの送信チャネル上の帯域幅を割り振る方法および装置
JP3766377B2 (ja) バス制御装置及び情報処理システム
JP4151362B2 (ja) バス調停方式、データ転送装置、及びバス調停方法
US8195846B2 (en) Direct memory access controller for improving data transmission efficiency in MMoIP and method therefor
JP2000276437A (ja) Ｄｍａ制御装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23810573

Country of ref document: EP

Kind code of ref document: A1