WO2023226444A1 - 一种数字预失真电路、数字预失真方法以及装置 - Google Patents

一种数字预失真电路、数字预失真方法以及装置 Download PDF

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WO2023226444A1
WO2023226444A1 PCT/CN2023/070659 CN2023070659W WO2023226444A1 WO 2023226444 A1 WO2023226444 A1 WO 2023226444A1 CN 2023070659 W CN2023070659 W CN 2023070659W WO 2023226444 A1 WO2023226444 A1 WO 2023226444A1
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input signal
coefficient
signal
output signal
sub
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PCT/CN2023/070659
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English (en)
French (fr)
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伏罗比耶夫安德烈
马克西姆内菲多夫
赵一凡
吴燕鸣
高留闯
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华为技术有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion

Definitions

  • Embodiments of the present application relate to the field of electronic equipment, and more specifically to a digital predistortion circuit, digital predistortion method and device.
  • DPD digital pre-distortion
  • PA power amplifier
  • Embodiments of the present application provide a digital predistortion circuit, digital predistortion method and device, which can determine the DPD coefficient and the index coefficient according to the first characteristic and the second characteristic of the input signal, thereby performing digital predistortion processing to avoid passing through the power amplifier. A nonlinear output signal is obtained.
  • a digital predistortion circuit in a first aspect, includes: a digital predistortion module and a power amplifier, wherein the digital predistortion module is used to obtain the first characteristic and the first characteristic of the first input signal.
  • the second characteristic of the first input signal wherein the first characteristic of the first input signal includes at least one of the following: the amplitude of the first input signal, the in-phase component of the first input signal, the third An orthogonal component of an input signal, the second characteristic includes at least one of the following: the bandwidth of the first input signal, the temperature of the digital predistortion circuit when processing the first input signal, the first The frequency point of the input signal, the modulation format of the first input signal, the standing wave generated by the digital predistortion circuit processing of the first input signal, and used to determine the first coefficient according to the first characteristic, according to the The second characteristic determines a second coefficient for generating a second signal according to the first input signal and the first coefficient, and generating a first output signal according to the second signal and the second coefficient, and converting the second signal
  • the first output signal is input to the power amplifier;
  • the power amplifier is used to amplify the first output signal to generate a second output signal.
  • the DPD module can determine the first coefficient and the second coefficient according to the first characteristic and the second characteristic of the first input signal, and use the first coefficient and the second coefficient to modify the first input signal. Perform digital predistortion processing, and then input the first output signal after digital predistortion processing into the power amplifier, so that a linear and non-distorted second output signal can be obtained.
  • the digital predistortion circuit further includes a coefficient module, the coefficient module stores the corresponding relationship between the first feature and the first coefficient and the The corresponding relationship between the second feature and the second coefficient.
  • the digital predistortion module is specifically configured to extract the first coefficient from the coefficient module according to the first feature and extract the first coefficient from the coefficient module according to the second feature.
  • the coefficient module extracts the second coefficient.
  • the digital predistortion module includes N digital predistortion sub-modules and a synthesis module, and the N digital predistortion sub-modules are used according to the first A feature determines N first sub-coefficients, and N second sub-coefficients are determined according to the second feature, N ⁇ 1, and is an integer, and the N first sub-coefficients are different; according to the first input signal and The N first sub-coefficients generate N second sub-signals; generate N first output sub-signals according to the N second sub-signals and the N second sub-coefficients; the synthesis module is used to The first output signal is generated based on the N first output sub-signals.
  • the first feature further includes data carried by the first input signal and/or a signal amplitude of the second input signal and/or a signal amplitude of the second input signal.
  • the data carried, wherein the second input signal is an input signal that differs from the first input signal by a certain time interval.
  • the digital predistortion circuit further includes a digital-to-analog converter, wherein the digital-to-analog converter is used to obtain the first output a signal, perform digital-to-analog conversion processing on the first output signal, and input the first output signal after the digital-to-analog conversion processing to the power amplifier.
  • the digital predistortion circuit further includes a preprocessing module and a solving module, the solving module is preset with an algorithm for solving coefficients, wherein the third An input signal and the second output signal are input to the preprocessing module, when the adjacent channel leakage ratio of the first input signal and the second output signal exceeds a first threshold and/or the error vector amplitude exceeds a second threshold
  • the preprocessing module is configured to preprocess the first input signal and the second output signal to align the first input signal and the second output signal;
  • the input signal and the preprocessed second output signal are input to the solution module; the solution module is used to calculate the preprocessed first input signal and the preprocessed second output according to the algorithm.
  • the signal is processed to generate a third coefficient and a fourth coefficient; the digital predistortion module is also used to generate a third signal according to the first input signal and the third coefficient; according to the third signal and the The fourth coefficient generates a third output signal; the third output signal is input to the power amplifier; and the power amplifier is used to amplify the third output signal.
  • the digital predistortion circuit when the ACLR of the first input signal and the second output signal exceeds the first threshold or the EVM exceeds the second threshold, the digital predistortion circuit can recalculate a new signal based on the first input signal and the second output signal. coefficients, so that the digital predistortion circuit can generate a third output signal based on the third coefficient and the fourth coefficient, and then input the third output signal into the power amplifier, thereby obtaining a distortion-free fourth output signal.
  • a digital predistortion method includes: obtaining a first characteristic of a first input signal and a second characteristic of the first input signal, wherein the first characteristic of the first input signal includes At least one of the following: the amplitude of the first input signal, the in-phase component of the first input signal, the quadrature component of the first input signal, and the second characteristic includes at least one of the following: the first The bandwidth of an input signal, the temperature of the digital predistortion circuit when processing the first input signal, the frequency point of the first input signal, the modulation format of the first input signal, the digital predistortion circuit Processing the standing wave generated by the first input signal; determining a first coefficient according to the first characteristic and determining a second coefficient according to the second characteristic; generating a second coefficient according to the first input signal and the first coefficient. signal; generating a first output signal according to the second signal and the second coefficient; performing power amplification processing on the first output signal to generate a second output signal.
  • determining the first coefficient and the second coefficient according to the first characteristic and the second characteristic of the first input signal include: according to the first characteristic Determine N first sub-coefficients, determine N second sub-coefficients according to the second characteristics, and the N first sub-coefficients are different; generate a second sub-coefficient according to the first input signal and the first coefficient.
  • N first output sub-signals are generated according to the N second sub-signals and the N second sub-coefficients; a first output signal is generated according to the N first output sub-signals.
  • the method further includes: preprocessing the first input signal and the second output signal to align the first input signal and the second output signal; The signal and the preprocessed second output signal are processed to generate a third coefficient and a fourth coefficient; a third signal is generated according to the first input signal and the third coefficient; according to the third signal and The fourth coefficient generates a third output signal; the third output signal is subjected to power amplification processing to generate a fourth output signal.
  • the first feature further includes data carried by the first input signal and/or a signal amplitude of the second input signal and/or the second input signal The data carried, wherein the second input signal is an input signal that differs from the first input signal by a certain time interval.
  • a transmitting device in a third aspect, includes a transceiver unit, a digital predistortion unit, and a power amplification unit, wherein the transceiver unit is used to receive the first input signal; the digital predistortion unit is used To obtain the first characteristic of the first input signal and the second characteristic of the first input signal, wherein the first characteristic of the first input signal includes at least one of the following: the amplitude of the first input signal , the in-phase component of the first input signal, the quadrature component of the first input signal, the second characteristic includes at least one of the following: the bandwidth of the first input signal, the processing speed of the digital predistortion circuit The temperature of the first input signal, the frequency point of the first input signal, the modulation format of the first input signal, and the standing wave generated by the digital predistortion circuit processing the first input signal; according to the Determine a first coefficient based on the first characteristic, determine a second coefficient based on the second characteristic; generate a second signal
  • the transmitting device further includes a coefficient unit, in which the corresponding relationship between the first feature and the first coefficient and the second coefficient are stored.
  • the corresponding relationship between features and the second coefficient; the digital predistortion unit is specifically configured to extract the first coefficient from the coefficient unit according to the first feature and extract the coefficient from the coefficient unit according to the second feature Extract the second coefficient.
  • the digital preprocessing unit is specifically configured to: determine N first sub-coefficients according to the first characteristics and determine N first sub-coefficients according to the second characteristics. second sub-coefficients, the N first sub-coefficients are different; generate N second sub-signals according to the first input signal and the N first coefficients; generate N second sub-signals according to the N second sub-signals and the N second sub-coefficients generate N first output sub-signals; the first output signal is generated according to the N first output sub-signals.
  • the transmitting device further includes a preprocessing unit and a solving unit, the solving unit is preset with an algorithm for solving coefficients, wherein the first input The signal and the second output signal are input to the preprocessing unit.
  • the a preprocessing unit configured to preprocess the first input signal and the second output signal to align the first input signal and the second output signal; the preprocessing unit is also configured to convert the preprocessing unit into The processed first input signal and the preprocessed second output signal are input to the calculation unit; the calculation unit is configured to calculate the preprocessed first input signal and the preprocessed output signal according to the algorithm.
  • the preprocessed second output signal is processed to generate a third coefficient and a fourth coefficient; the digital predistortion unit is also used to generate a third signal according to the first input signal and the third coefficient; according to The third signal and the fourth coefficient generate a third output signal; the third output signal is input to the power amplification unit; the power amplification unit is also used to amplify the third output signal ; The transceiver unit is also used to send the amplified third output signal.
  • the first characteristic further includes data carried by the first input signal and/or a signal amplitude of the second input signal and/or a signal amplitude of the second input signal.
  • the data carried, wherein the second input signal is an input signal that differs from the first input signal by a certain time interval.
  • a fourth aspect provides a transmitting device, which includes the first aspect and any possible digital predistortion circuit of the first aspect, or includes the third aspect and any possible transmitting device of the third aspect.
  • a transmitting device including one or more processors; one or more memories; one or more transceivers; the one or more memories store one or more computer programs, and the One or more computer programs include instructions that, when executed by the one or more processors, cause the above-mentioned second aspect and any possible designed technical solution of the second aspect to be executed.
  • a chip is provided, which is coupled to a memory in an electronic device and used to call a computer program stored in the memory and execute the second aspect of the embodiment of the present application and any possible technical solution of the second aspect.
  • "Coupling" in the embodiment of this application means that two components are directly or indirectly combined with each other.
  • a computer-readable storage medium includes a computer program.
  • the electronic device causes the electronic device to perform the above-mentioned second aspect and any of the second aspect thereof.
  • a computer program product includes a computer program.
  • the computer program product includes a computer program. When the computer program is run, it causes the computer to execute the technical solutions of the above-mentioned second aspect and any possible design of the second aspect.
  • Figure 1 is a schematic flow chart of a linearization scheme for digital predistortion.
  • FIG. 2 is a schematic structural diagram of a digital predistortion circuit provided by an embodiment of the present application.
  • Figure 3 is a schematic diagram of the digital predistortion module determining the first coefficient provided by the embodiment of the present application.
  • Figure 4 is a schematic diagram of another digital predistortion module determining the first coefficient provided by the embodiment of the present application.
  • Figure 5 is a schematic structural diagram of a digital predistortion module provided by an embodiment of the present application.
  • Figure 6 is a schematic structural diagram of a digital predistortion submodule provided by an embodiment of the present application.
  • Figure 7 is a schematic structural diagram of a coefficient module provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a digital predistortion circuit provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a digital predistortion circuit provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a digital predistortion circuit provided by an embodiment of the present application.
  • Figure 11 is a schematic flow chart of the digital predistortion method provided by the embodiment of the present application.
  • Figure 12 is a schematic flow chart of a digital predistortion method provided according to an embodiment of the present application.
  • Figure 13 is a schematic flow chart of a digital predistortion method provided according to an embodiment of the present application.
  • Figure 14 is a transmitting device provided by an embodiment of the present application.
  • Figure 15 is a communication device provided by an embodiment of the present application.
  • GSM Global System of Mobile communication
  • CDMA Code Division Multiple Access
  • WCDMA broadband code division multiple access
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution
  • FDD Frequency Division Duplex
  • TDD Time Division Duplex
  • UMTS Universal Mobile Telecommunication System
  • WiMAX Worldwide Interoperability for Microwave Access
  • 5G fifth generation
  • 5NR New Radio
  • the technical solutions provided by the embodiments of this application can also be applied to other communication systems that need to implement digital predistortion processing.
  • the device to which the technical solution provided by the embodiment of the present application is applied is a transmitting device, and the transmitting device may be a network device or a terminal device. Among them, the transmitting device may also be called a sending device.
  • Terminal equipment is a device with wireless transceiver functions that can be deployed on land, including indoors or outdoors, handheld, wearable or vehicle-mounted; it can also be deployed on water (such as ships, etc.); it can also be deployed in the air (such as aircraft, Balloons and satellites, etc.
  • the terminal device can communicate with the core network via a radio access network (RAN), and exchange voice and/or data with the RAN.
  • RAN radio access network
  • the terminal device can be a mobile phone, Tablet computer (Pad), computer with wireless transceiver function, mobile internet device (MID), wearable device, virtual reality (VR) terminal device, augmented reality (AR) terminal device, Wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical, wireless terminals in smart grid, transportation safety ), wireless terminals in smart homes, drones, drone controllers, etc.
  • the embodiments of this application do not limit the application scenarios.
  • the terminal device may also be called user equipment sometimes. (user equipment, UE), mobile station and remote station, etc.
  • the embodiments of this application do not limit the specific technology, equipment form and name used by the terminal equipment.
  • the network equipment involved in the embodiment of this application includes a base station (BS), a network controller, a mobile switching center, or other access network equipment or core network equipment.
  • base stations include various forms of macro base stations, micro base stations, relay stations, access points, etc.
  • the base station can be a base station in GSM or CDMA: base transceiver station (BTS); it can also be a base station in WCDMA: NodeB; it can also be an evolved base station in LTE: eNB or e-NodeB; or It can be a base station in the 5G system.
  • the base station in the 5G system can be called a transmission reception point (TRP) or a next-generation Node B (generation Node B, gNB); further, the base station can also be This application does not limit the base stations in future networks.
  • TRP transmission reception point
  • gNB next-generation Node B
  • gNB next-generation Node B
  • the technical solution provided by the embodiments of the present application can be applied to the transmitting equipment, and further, can be applied to the transmitting device of the transmitting equipment.
  • FIG. 1 is a schematic flow chart of a linearization scheme using digital predistortion. As shown in Figure 1, it is assumed that the input signal x(n) is not processed by the DPD processing unit 101 and is directly input to the PA102. The input signal x(n) is When using PA102, due to the nonlinear characteristics of PA102, the signal will be distorted, and a nonlinear distortion signal will be output, which will affect the signal quality and communication efficiency.
  • the DPD processing unit 101 is used to perform preprocessing on the input signal x(n) that is opposite to the characteristics of the PA102 before the input signal x(n) is input to the PA102.
  • the P input on the horizontal axis represents the signal input to the DPD processing unit 101
  • the P output on the vertical axis represents the signal output by the DPD processing unit 101
  • the dotted line represents the input to the DPD processing
  • the undistorted input signal x(n) of the unit 101 needs to be processed in the DPD processing unit 101 opposite to the nonlinear characteristics of the PA 102 due to the nonlinear characteristics of the PA. That is, the solid line represents the actual output from the DPD processing unit 101. signal characteristics.
  • the dotted line represents the undistorted signal input to PA102. Due to the nonlinear characteristics of PA102, the solid line represents the signal after the undistorted signal input to PA102 is output due to the nonlinear characteristics of PA102. It can be seen that , due to the nonlinear characteristics of PA102, distortion will occur after outputting PA102. Therefore, it is necessary to perform a process in the DPD processing unit 101 that is opposite to the nonlinear characteristics of the PA 102 . By setting up the feedback circuit unit 103, that is, a part of the signal output from the PA is transmitted to the DPD processing unit 101 through the feedback circuit unit 103.
  • the DPD processing unit 101 can obtain the nonlinear characteristics of the PA102 by processing this part of the signal, so that the In advance, the DPD processing unit 101 performs a process opposite to the nonlinear characteristics of PA102, and then inputs the signal processed by the DPD processing unit 101 to PA102. PA102 can finally output a linear and distortion-free signal, ensuring that the signal output from PA102 The signal is linear and distortion-free.
  • the solid line represents the signal output by PA102. It can be seen that after the pre-distortion processing of the DPD processing unit 101, the signal output by PA102 will not be distorted.
  • PA nonlinear distortion characteristics
  • Common PA models include Volterra model, memory polynomial (MP) model, generalized memory polynomial (GMP) model, Wiener model, Hammerstein model, etc.
  • MP memory polynomial
  • GMP generalized memory polynomial
  • Wiener model Wiener model
  • Hammerstein model etc.
  • the mathematical expression of the memory polynomial model is shown in formula (1):
  • x(n) represents the input signal
  • z(n) represents the output signal of the DPD processing unit
  • K represents the polynomial order
  • Q represents the memory depth
  • a represents the DPD coefficient.
  • the feedback circuit unit needs real-time iteration when calculating the DPD coefficient, which will increase additional power consumption.
  • the second characteristics change (such as bandwidth, temperature, frequency, etc.)
  • embodiments of the present application provide a digital predistortion circuit and device, which can reduce power consumption and improve communication quality.
  • FIG. 2 shows a schematic structural diagram of a digital predistortion circuit provided by an embodiment of the present application.
  • the digital predistortion circuit 200 includes: DPD module 210 and PA220, where,
  • the DPD module 210 is used to obtain the first characteristic of the first input signal and the second characteristic of the first input signal.
  • the DPD module 210 is configured to determine the first coefficient according to the first characteristic of the first input signal, and determine the second coefficient of the second characteristic according to the second characteristic.
  • the DPD module 210 is also used to generate a second signal according to the first input signal and the first coefficient.
  • the DPD module 210 is also used to generate a first output signal according to the second signal and the second coefficient.
  • the DPD module 210 is also used to input the first output signal to the power amplifier.
  • PA220 is used to amplify the first output signal.
  • the first output signal that has undergone power amplification may be called a second output signal.
  • the DPD module can determine the first coefficient and the second coefficient according to the first characteristic and the second characteristic of the first input signal, and use the first coefficient and the second coefficient to modify the first input signal. Perform digital predistortion processing, and then input the first output signal after digital predistortion processing into the PA220, so that a linear and non-distorted second output signal can be obtained.
  • the DPD module 210 can obtain the first characteristic and the second characteristic of the first input signal, then determine the first coefficient according to the first characteristic, and determine the second coefficient according to the second characteristic.
  • the embodiment of the present application does not limit the type of the first input signal.
  • the first input signal may be a modulated signal, such as an LTE signal, a 5G signal, etc., or it may be a continuous wave (CW) signal.
  • CW continuous wave
  • the first characteristic of the first input signal may be signal amplitude.
  • the first characteristic of the first input signal may also include data carried by the first input signal and/or signal amplitude of the second input signal and/or data carried by the second input signal.
  • the first input signal carries The data may be an in-phase component or a quadrature component of the first input signal
  • the second input signal may be an input signal that differs from the first input signal by a certain time interval. For example, if the first input signal is x(n) and the second input signal may be x(n-k), then the characteristic of the first input signal may also be the amplitude of the second input signal, that is,
  • the DPD module 210 may determine the first coefficient in the following ways.
  • the DPD module 210 stores a look-up table (LUT).
  • the look-up table can be understood as a mapping relationship.
  • the mapping relationship is used to indicate multiple first-type features and multiple coefficients. The corresponding relationship between them is to store the coefficients calculated in advance in the table, and then the DPD module 210 can calculate the address in the LUT according to the first feature of the first input signal, so that the first coefficient can be determined, and the first coefficient can be understood is the coefficient corresponding to the first feature in the mapping relationship.
  • the first type of features includes at least one of amplitude, in-phase components, and quadrature components.
  • the DPD module 210 can determine the amplitude of the first input signal x(n) input to the DPD module 210 according to the absolute value unit.
  • the absolute value is
  • of the first input signal indicates the signal amplitude of the first input signal.
  • the DPD module 210 may adjust it through a delay unit to obtain at least one index value.
  • the DPD module 210 can obtain the index value
  • the coefficients determined by LUT are called DPD coefficients.
  • the DPD coefficients of different memory terms in the memory polynomial can be determined by the signal amplitude of the first input signal.
  • the memory depth is related to the memory polynomial.
  • the DPD module 210 obtains three memory depth index values through the delay unit as an example, but the embodiment of the present application is not limited thereto.
  • the digital predistortion circuit 200 further includes a coefficient module 230, which stores a LUT.
  • the lookup table can be understood as a mapping relationship, and the mapping relationship is used to indicate a plurality of first-type features and The corresponding relationship between multiple coefficients is to store the coefficients calculated in advance in the table, and then the DPD module 210 can calculate the address in the LUT according to the first feature of the first input signal, and can determine the first coefficient.
  • the absolute value unit After the first input signal passes through the absolute value unit, its absolute value
  • the absolute value of the first input signal is input into the coefficient module 230.
  • the coefficient module 230 can be adjusted through the delay unit to obtain an index value
  • the memory depth is the index value
  • the LUT corresponding to the index value can be determined according to the index value, that is, 3 LUTs can be determined, and then according to the signal amplitude of the first input signal
  • the value is searched for the corresponding coefficient in the corresponding LUT.
  • the DPD coefficients of different memory items can be determined. Please refer to the following for specific instructions.
  • the second characteristic of the first input signal includes at least one of the following: bandwidth of the first input signal, temperature of the digital predistortion circuit when processing the first input signal, frequency point of the first input signal, first input signal
  • the modulation format of the signal and the digital predistortion circuit process the standing wave generated by the first input signal.
  • the DPD module can determine the second coefficient in the following ways.
  • the DPD module 210 stores an index table.
  • the index table can be understood as a mapping relationship.
  • the mapping relationship is used to indicate the corresponding relationship between multiple second-type features and multiple coefficients.
  • the DPD module 210 can calculate the mapping relationship in the index table according to the second features of the first input signal. Find the corresponding second coefficient in .
  • the second coefficient can be understood as the coefficient corresponding to the second feature in the mapping relationship.
  • the second type of characteristics includes: at least one of bandwidth, temperature, frequency, signal modulation format, and standing wave.
  • the digital predistortion circuit 200 further includes a coefficient module 230, and the coefficient module 230 stores an index table.
  • DPD module 210 may determine the second coefficient in coefficient module 230 based on the second characteristic of the first input signal.
  • the DPD module 210 or the coefficient module 230 also stores multiple index tables.
  • the DPD module can determine M second sub-coefficients based on the M second features of the first input signal, that is, the second coefficients can include the M second sub-coefficients. coefficient.
  • the DPD module 210 or the coefficient module 230 can store a first index table and a second index table, where the first index table corresponds to bandwidth and the second index table corresponds to temperature, so that the bandwidth can be determined according to the bandwidth. and temperature determine corresponding coefficients in the first index table and the second index table respectively.
  • a set of coefficients determined based on different second characteristics of the first input signal may be called second coefficients, that is, the second coefficient may include a plurality of coefficients determined based on different second characteristics of the first input signal.
  • the second coefficient includes a coefficient determined according to the bandwidth and a coefficient determined according to the temperature.
  • the DPD module 210 determines the first coefficient and the second coefficient according to the first characteristic and the second characteristic of the first input signal.
  • the DPD module 210 generates the second signal according to the first coefficient and the first input signal in detail below. and generating a first output signal based on the second signal and the second coefficient.
  • the DPD module 210 may determine the first coefficient according to the first characteristic of the first input signal, the first coefficient may include one DPD coefficient or DPD coefficients of multiple different memory items, the DPD module 210 may combine the first input signal with the first coefficient.
  • Multiplication means multiplying the first input signal by the one DPD coefficient or the DPD coefficients of multiple different memory items to obtain the second signal.
  • the second signal may be multiplied by the second coefficient to obtain the first output signal.
  • the DPD module 210 may include N DPD sub-modules and synthesis modules, where N ⁇ 1 and is an integer.
  • Figure 5 shows a schematic structural diagram of the DPD module 210.
  • the DPD module 210 includes N DPD sub-modules and a synthesis module, where the N DPD sub-modules can be configured according to the first input signal x(n).
  • a feature determines N first sub-coefficients and N second sub-coefficients are determined according to a second feature of the first input signal, where N ⁇ 1 and is an integer.
  • Each of the N first sub-coefficients may include one DPD coefficient or multiple DPD coefficients.
  • the first sub-coefficient including multiple DPD coefficients can be understood as the first sub-coefficient including DPD coefficients of different memory items.
  • the N first sub-coefficients may constitute the first coefficient, that is, the first coefficient may include the N first sub-coefficients.
  • the second coefficient includes the N second sub-coefficients.
  • the N DPD sub-modules can generate N second sub-signals based on the N first sub-coefficients and the first input signal, and then generate N first outputs based on the N second sub-signals and N second sub-coefficients. sub-signal.
  • N is a consideration of factors such as final output performance and computing resources.
  • N 1
  • the second coefficient is a constant
  • N 2.
  • Figure 6 shows a schematic structural diagram of the DPD submodule.
  • the DPD submodule may include a digital predistortion processor and a multiplier.
  • the first input signal x(n) is input to the DPD sub-module
  • the pre-distortion processor can determine the first sub-coefficient and the second sub-coefficient according to the first input signal, and then the pre-distortion processor can combine the first input signal with the first sub-coefficient Multiply, that is, multiply the first input signal with the one DPD coefficient or the DPD coefficients of multiple different memory items to generate a second sub-signal, and then multiply the second sub-signal with the second coefficient through a multiplier to generate the first output sub-signal.
  • N first output sub-signals can be obtained through the N DPD sub-modules, and then the synthesis module can obtain the first output signal through formula (2).
  • the architecture of the digital predistortion processor is not limited in the embodiments of the present application.
  • the architecture of the digital predistortion processor may be an architecture based on memory polynomials.
  • the DPD sub-module can determine the first sub-coefficient and the second coefficient in the following ways.
  • each DPD sub-module stores the LUT and index table corresponding to the DPD sub-module.
  • the LUT table corresponding to each DPD sub-module can include LUTs of different memory items.
  • the DPD sub-module may determine the first sub-coefficient and the second coefficient based on the first characteristic and the second characteristic of the first input signal.
  • the DPD sub-module can determine the first sub-coefficient and the second coefficient corresponding to the first input signal through the coefficient module 230.
  • the coefficient module 230 stores the LUT and index table corresponding to each DPD sub-module.
  • the LUT corresponding to each DPD sub-module can include sub-LUTs of different memory items.
  • Figure 7 shows a schematic structural diagram of the coefficient module storing LUTs and index tables. As shown in Figure 7, each of the N DPD sub-modules has one or more sub-LUTs and one or more sub-LUTs in the coefficient module 230. Multiple environment index tables. The number of sub-LUT tables is related to the memory depth.
  • each DPD sub-module among the N DPD sub-modules includes M environment index tables.
  • each DPD sub-module can determine the first sub-coefficient and the second sub-coefficient from the corresponding LUT and environment index table, so that the first output sub-signal can be generated.
  • first sub-coefficient and the second sub-coefficient determined by each of the N DPD sub-modules according to the first characteristic and the second characteristic of the first input signal may be the same or different.
  • the first output signal can be input into the PA220, and the PA220 can generate a second output signal according to the first output signal.
  • the DPD module 210 can determine the first coefficient and the second coefficient according to the first characteristic and the second characteristic of the first input signal, and use the first coefficient and the second coefficient to modify the first input signal.
  • the signal is subjected to digital predistortion processing, and then the first output signal after digital predistortion processing is input to the PA220, so that a linear and non-distorted second output signal can be obtained.
  • the digital predistortion circuit 200 also includes a coefficient module 230, which stores a LUT and an index table.
  • coefficient module 230 can be referred to the above, and for the sake of brevity, it will not be described again here.
  • the PA may be a digital PA or an analog PA.
  • the digital predistortion circuit 200 also includes a digital to analog converter (digital to analog converter, DAC) 240.
  • the DAC240 is used to convert the first output signal of the DPD module 210 into an analog signal, and input the analog signal into the PA220.
  • the digital predistortion circuit 200 also includes passive components such as filters and mixers between the DAC and the PA 220 .
  • the coefficients in the LUT and the coefficients in the index table stored by the DPD module 210 or the coefficient module 230 above may be calculated in advance.
  • the input signal of the DPD and the output signal of the PA under different bandwidths can be collected, so that the solution can be solved through the solving algorithm Get the DPD coefficient and index coefficient.
  • the second characteristic includes multiple, for example, when the second characteristic includes bandwidth and temperature
  • the input signals of the DPD at different bandwidths and temperatures can be collected and The output signal of the PA is solved, so that two index tables can be obtained, corresponding to the two second characteristics of bandwidth and temperature respectively.
  • the second characteristic of the input signal and the first characteristic are decoupled, so that the DPD coefficient corresponding to the first characteristic and the second characteristic can be obtained.
  • the coefficient corresponding to the feature and then when a second feature is added or the value range of a certain second feature changes, only the index table corresponding to the second feature can be added or adjusted without changing the LUT of the DPD, thereby reducing the number of LUTs and reducing Storage pressure of memory.
  • the first coefficient and the second coefficient can be determined through the solving algorithm according to the preset nonlinear model.
  • the nonlinear model can be a memory polynomial as shown in formula (1)
  • the model may also be other models, which is not limited in this application.
  • the solution method is not limited in the embodiments of this application.
  • the least square (least square, LS) algorithm and its modifications, the least square (Least Mean Square, LMS) algorithm and its modifications, etc. can be adopted.
  • the digital predistortion circuit 200 also includes a preprocessing module 250 and a calculation module 260.
  • the calculation module 260 may be preset with the method for solving the coefficients described above. ,in
  • the first input signal and the second output signal are input to the preprocessing module 250 , and the input signal of the preprocessing module 250 is input to the solution module 260 .
  • the preprocessing module 250 is configured to preprocess the first input signal and the second output signal to align the first input signal and the second output signal.
  • the preprocessing method adopted by the preprocessing module 250 is not limited.
  • the preprocessing module 250 may adopt preprocessing methods such as gain alignment, time delay alignment, and frequency and phase offset correction.
  • the preprocessing module 250 is also used to input the preprocessed first input signal and the second output signal to the solution module 260 .
  • the solving module 260 is configured to process the preprocessed first input signal and the second output signal according to the algorithm to generate the third coefficient and the fourth coefficient.
  • the solution module 260 is also configured to send the third coefficient and the fourth coefficient to the coefficient module 230.
  • the DPD module 210 is also used to generate a third signal according to the first input signal and the third coefficient.
  • the DPD module 210 is also used to generate a third output signal according to the third signal and the fourth coefficient.
  • the DPD module 210 is also used to input the third output signal to the PA220;
  • PA220 is also used to amplify the third output signal.
  • the amplified third output signal may be called a fourth output signal.
  • the first coefficient can be replaced with a third coefficient
  • the second coefficient can be replaced with a fourth coefficient
  • the digital predistortion circuit when the ACLR or EVM of the first input signal and the second output signal exceeds the threshold, the digital predistortion circuit can recalculate new coefficients based on the first input signal and the second output signal, thereby digital predistortion
  • the circuit can generate a third output signal according to the third coefficient and the fourth coefficient, and then input the third output signal into the power amplifier, thereby obtaining a distortion-free fourth output signal.
  • the digital predistortion circuit may also include a buffer, which is used to store the first input signal and the second output signal, and then input the first input signal and the second output signal to the preprocessing module. .
  • the digital predistortion circuit may also include a preprocessing module and a decoding module.
  • the coefficients in the coefficient module cannot guarantee the performance of the DPD module, the coefficients in the coefficient module can be updated in real time to adapt to the input signal, thereby It can ensure that the output signal of the PA is not distorted.
  • Figure 11 shows a schematic flow of the digital predistortion method 1100 provided by the embodiment of the present application.
  • This method is applied to a transmitting device or a transmitting device including a transmitting device.
  • the transmitting device includes a DPD processing module, a PA and a memory.
  • the LUT and index table of the DPD are stored in the memory.
  • the method 1100 includes:
  • the transmitting device can obtain the first input signal, which can be an LTE signal, a 5G signal, a continuous wave signal, etc., so as to obtain the first characteristic of the first input signal and the second characteristic of the first input signal. .
  • S1120 Determine the first coefficient according to the first characteristic of the first input signal, and determine the second coefficient according to the second characteristic.
  • the transmitting device may determine the first coefficient according to the first characteristic of the first input signal and the second coefficient according to the second characteristic.
  • the transmitting device may generate the second signal according to the first input signal and the first coefficient.
  • the transmitting device may generate the first output signal according to the second signal and the second coefficient.
  • the transmitting device may process the first output signal through a power amplifier to generate a second output signal.
  • the transmitting device can determine the first coefficient and the second coefficient according to the first characteristic and the second characteristic of the first input signal, and use the first coefficient and the second coefficient to perform digital predistortion processing on the first input signal. , and then the first output signal processed by digital predistortion is input into the power amplifier, so that a linear and non-distorted second output signal can be obtained.
  • Figure 12 shows a schematic flow chart of a digital predistortion method according to an embodiment of the present application.
  • S1120 determine the first coefficient and the second coefficient according to the first characteristic and the second characteristic of the first input signal.
  • Two coefficients including:
  • S1121 Determine N first sub-coefficients and N second sub-coefficients according to the first characteristics and second characteristics of the first input signal.
  • the transmitting device may determine N first sub-coefficients and N second sub-coefficients based on the first characteristics and the second characteristics of the first input signal.
  • the transmitting device may generate N second sub-signals based on the first input signal and N first sub-coefficients.
  • S1141 generate N first output sub-signals based on N second sub-signals and N second sub-coefficients
  • the transmitting device may generate N first output sub-signals based on N second sub-signals and N second coefficients, and then sum the N first output sub-signals to obtain the first output signal.
  • the method 1100 when the second feature of the first input signal includes M second features, the method 1100 further includes:
  • M second sub-coefficients are determined based on M second features of the first input signal.
  • the second coefficient is determined based on the M second sub-coefficients.
  • the transmitting device After the transmitting device determines M second sub-coefficients, it can determine the second coefficients based on the M sub-coefficients.
  • the M second sub-coefficients may be multiplied to obtain the second coefficient.
  • Figure 13 shows a schematic flow chart of a digital predistortion method according to an embodiment of the present application. As shown in Figure 13, when the adjacent channel leakage ratio of the first input signal and the second output signal exceeds the first threshold and/or Or when the error vector amplitude exceeds the second threshold, the method 1100 further includes:
  • S1160 Preprocess the first input signal and the second output signal to align the first input signal and the second output signal.
  • S1180 Generate a third signal according to the first input signal and the third coefficient.
  • S1190 Generate a third output signal according to the third signal and the fourth coefficient.
  • S11100 Use the power amplifier to process the third output signal to generate a fourth output signal.
  • the digital predistortion circuit can re-solve the problem based on the first input signal and the second output signal.
  • the new coefficients allow the digital predistortion circuit to generate a third output signal based on the third coefficient and the fourth coefficient, and then input the third output signal into the power amplifier, thereby obtaining a distortion-free fourth output signal.
  • Figure 14 shows a transmitting device 1400 provided by an embodiment of the present application.
  • the transmitting device 1400 is applied to a transmitting device.
  • the transmitting device 1400 includes a transceiver unit 1410, a DPD unit 1420, and a power amplification unit 1430.
  • the transceiver unit 1410 is used to receive the first input signal.
  • the DPD unit 1420 is used to obtain the first characteristic of the first input signal and the second characteristic of the first input signal.
  • DPD unit 1420 configured to determine a first coefficient according to the first first characteristic and a second coefficient according to the second characteristic.
  • the DPD unit 1420 is also used to generate a second signal according to the first input signal and the first coefficient.
  • the DPD unit 1420 is also configured to generate a first output signal according to the second signal and the second coefficient.
  • the DPD unit 1420 is also used to input the first output signal to the power amplification unit 1430.
  • the power amplification unit 1430 is used to generate a second output signal according to the first output signal.
  • the transceiver unit 1410 is also used to send the second output signal.
  • the transmitting device further includes a coefficient unit, and the coefficient unit stores a LUT and an index table.
  • the DPD unit 1420 is specifically configured to extract the first coefficient from the coefficient unit according to the first feature and the second coefficient from the coefficient unit according to the second feature.
  • the DPD unit 1420 is specifically used for:
  • N second sub-signals are generated according to the first input signal and N first coefficients.
  • N first output sub-signals are generated according to N second sub-signals and N second sub-coefficients.
  • the first output signal is generated based on the N first output sub-signals.
  • the second feature includes M second sub-features, DPD unit 1420, specifically used for:
  • the second coefficient is determined based on M second sub-coefficients.
  • the transmitting device 1400 also includes a preprocessing unit and a solving unit, where the solving unit may be preset with an algorithm for solving coefficients, where the first input signal and the second output signal
  • the input preprocessing unit is configured to process the first input signal and the second output signal when the adjacent channel leakage ratio of the first input signal and the second output signal exceeds the first threshold or the error vector amplitude exceeds the second threshold. Preprocessing is performed to align the first input signal and the second output signal.
  • the preprocessing unit is also used to input the preprocessed first input signal and the preprocessed second output signal to the solving unit.
  • the solving unit is configured to process the preprocessed first input signal and the preprocessed second output signal according to the algorithm to generate third coefficients and fourth coefficients.
  • the solution unit is also used to input the third coefficient and the fourth coefficient into the coefficient unit.
  • the DPD unit 1420 is also used to generate a third signal according to the first input signal and the third coefficient.
  • the DPD unit 1420 is also configured to generate a third output signal according to the third signal and the fourth coefficient.
  • the DPD unit 1420 is also used to input the third output signal to the power amplification unit 1430.
  • the power amplification unit 1430 is also used to generate a fourth output signal according to the third output signal.
  • the transceiver unit 1410 is also used to send the fourth output signal.
  • this embodiment of the present application also provides a communication device (such as a transmitting device) 1500.
  • the communication device 1500 includes a processor 1510.
  • the processor 1510 is coupled to a memory 1520.
  • the memory 1520 is used to store computer programs or instructions and/or data.
  • the processor 1510 is used to execute the computer programs or instructions and/or data stored in the memory 1520. , so that the method in the above method embodiment is executed.
  • the communication device 1500 includes one or more processors 1510 .
  • the communication device 1500 may include one or more memories 1520 .
  • the memory 1520 can be integrated with the processor 1510 or provided separately.
  • the wireless communication device 1500 may also include a transceiver 1530, which is used for receiving and/or transmitting signals.
  • the processor 1510 is used to control the transceiver 1530 to receive and/or transmit signals.
  • the communication device 1500 is used to implement the operations performed by each unit in the transmitting device in the above method embodiment.
  • Embodiments of the present application also provide a computer-readable storage medium on which are stored computer instructions for implementing the method performed by the transmitting device in the above method embodiment, or the method performed by the transmitting device.
  • An embodiment of the present application also provides a computer program product.
  • the computer program When the computer program is executed by a computer, the computer can implement the method executed by the transmitting device in the above method embodiment.
  • An embodiment of the present application also provides a communication system, which includes the communication device in the above embodiment.
  • the communication device may include a hardware layer, an operating system layer running on the hardware layer, and an application layer running on the operating system layer.
  • the hardware layer can include hardware such as central processing unit (CPU), memory management unit (MMU) and memory (also called main memory).
  • the operating system of the operating system layer can be any one or more computer operating systems that implement business processing through processes, such as Linux operating system, Unix operating system, Android operating system, iOS operating system or windows operating system, etc.
  • the application layer can include applications such as browsers, address books, word processing software, and instant messaging software.
  • the embodiments of this application do not specifically limit the specific structure of the execution body of the method provided by the embodiments of this application, as long as the program recorded in the code of the method provided by the embodiments of this application can be used according to the method provided by the embodiments of this application.
  • the execution subject of the method provided by the embodiment of the present application may be a terminal device or a satellite, or a functional module in the terminal device or satellite that can call a program and execute the program.
  • inventions of the present application may be implemented as methods, apparatus, or articles of manufacture using standard programming and/or engineering techniques.
  • article of manufacture as used herein may encompass a computer program accessible from any computer-readable device, carrier or medium.
  • computer-readable media may include, but are not limited to: magnetic storage devices (such as hard disks, floppy disks or tapes, etc.), optical disks (such as compact discs (CD), digital versatile discs (DVD), etc. ), smart cards, and flash memory devices (e.g., erasable programmable read-only memory (EPROM), cards, sticks, or key drives, etc.).
  • the various storage media described herein may represent one or more devices and/or other machine-readable media for storing information.
  • the term "machine-readable medium” may include, but is not limited to, wireless channels and various other media capable of storing, containing and/or carrying instructions and/or data.
  • processors mentioned in the embodiments of this application may be a central processing unit (CPU), or other general-purpose processor, digital signal processor (DSP), or application-specific integrated circuit (ASIC).
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • a general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.
  • non-volatile memory may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
  • non-volatile memory can be read-only memory (ROM), programmable ROM (PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically removable memory. Erase electrically programmable read-only memory (EPROM, EEPROM) or flash memory.
  • Volatile memory can be random access memory (RAM).
  • RAM can be used as an external cache.
  • RAM may include the following forms: static random access memory (static RAM, SRAM), dynamic random access memory (dynamic RAM, DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM) , double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous link dynamic random access memory (synchlink DRAM, SLDRAM) and Direct memory bus random access memory (direct rambus RAM, DR RAM).
  • static random access memory static random access memory
  • dynamic RAM dynamic random access memory
  • DRAM synchronous dynamic random access memory
  • SDRAM synchronous DRAM
  • double data rate SDRAM double data rate SDRAM
  • DDR SDRAM double data rate SDRAM
  • ESDRAM enhanced synchronous dynamic random access memory
  • SLDRAM synchronous link dynamic random access memory
  • Direct memory bus random access memory direct rambus RAM, DR RAM
  • the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component
  • the memory storage module
  • memories described herein are intended to include, but are not limited to, these and any other suitable types of memories.
  • the disclosed systems, devices and methods can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or can be integrated into another system, or some features can be ignored, or not implemented.
  • the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit.
  • the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solutions of the embodiments of the present application are essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program code. .

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Abstract

本申请实施例提供了一种数字预失真电路、方法以及装置，该数字预失真电路包括：数字预失真模块和功率放大器，数字预失真模块，用于获取第一输入信号的第一特征和第一输入信号的第二特征；根据第一输入信号的第一特征确定第一系数和根据第二特征确定第二系数；根据第一输入信号与第一系数生成第二信号；数字预根据第二信号与第二系数生成第一输出信号；将第一输出信号输入到功率放大器；功率放大器，用于对第一输出信号进行放大以生成第二输出信号。本申请实施例提供的数字预失真电路可以避免输入信号经过功率放大器后产生的信号失真。

Description

一种数字预失真电路、数字预失真方法以及装置
本申请要求于2022年05月27日提交俄罗斯联邦专利局、申请号为2022114387、申请名称为“一种数字预失真电路、数字预失真方法以及装置”的俄罗斯联邦专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及电子设备领域，并且更加具体地涉及一种数字预失真电路、数字预失真方法以及装置。
背景技术
在通信系统中，为了避免功率放大器(power amplifier，PA)工作在非线性区域造成信号的非线性和记忆失真而引入了数字预失真(digital pre-distortion，DPD)。随着功率放大器向着高效率、大带宽、低功耗、高集成度方向发展，目前的数字预失真系统已不能满足功率放大器的需求。
发明内容
本申请实施例提供一种数字预失真电路、数字预失真方法以及装置，能够根据输入信号的第一特征以及第二特征确定DPD系数和索引系数，从而进行数字预失真处理以避免经过功率放大器后得到非线性的输出信号。
第一方面，提供了一种数字预失真电路，该数字预失真电路包括：数字预失真模块和功率放大器，其中，所述数字预失真模块，用于获取第一输入信号的第一特征和所述第一输入信号的第二特征，其中所述第一输入信号的第一特征包括以下至少一项：所述第一输入信号的幅值、所述第一输入信号的同相分量、所述第一输入信号的正交分量，所述第二特征包括以下至少一项：所述第一输入信号的带宽、所述数字预失真电路在处理所述第一输入信号时的温度、所述第一输入信号的频点、所述第一输入信号的调制格式、所述数字预失真电路处理所述第一输入信号产生的驻波，并用于根据所述第一特征确定第一系数，根据所述第二特征确定第二系数，用于根据所述第一输入信号与所述第一系数生成第二信号，并根据所述第二信号与所述第二系数生成第一输出信号，并将所述第一输出信号输入到所述功率放大器；
所述功率放大器，用于对所述第一输出信号进行放大处理以生成第二输出信号。
本申请实施例提供的数字预失真电路，DPD模块可以根据第一输入信号的第一特征以及第二特征确定第一系数和第二系数，并利用第一系数和第二系数对第一输入信号做数字预失真处理，然后将经过数字预失真处理后的第一输出信号输入到功率放大器中，从而可以得到线性非失真的第二输出信号。
结合第一方面，在第一方面的某些实现方式中，所述数字预失真电路还包括系数模块， 所述系数模块存储有所述第一特征与所述第一系数的对应关系和所述第二特征与所述第二系数的对应关系，所述数字预失真模块，具体用于根据所述第一特征从所述系数模块提取所述第一系数和根据所述第二特征从所述系数模块提取所述第二系数。第一特征第二特征
结合第一方面，在第一方面的某些实现方式中，所述数字预失真模块包括N个数字预失真子模块和合成模块，所述N个数字预失真子模块，用于根据所述第一特征确定N个第一子系数，根据所述第二特征确定N个第二子系数，N≥1，且为整数，所述N个第一子系数不同；根据所述第一输入信号与所述N个第一子系数生成N个第二子信号；根据所述N个第二子信号与所述N个第二子系数生成N个第一输出子信号；所述合成模块，用于根据所述N个第一输出子信号生成所述第一输出信号。
结合第一方面，在第一方面的某些实现方式中，该第一特征还包括该第一输入信号承载的数据和/或该第二输入信号的信号幅值和/或该第二输入信号承载的数据，其中该第二输入信号是与该第一输入信号相差一定时间间隔的输入信号。
结合第一方面，在第一方面的某些实现方式中，该数字预失真电路还包括数模转换器，其中所述数模转换器，用于从所述数字预失真电路获取所述第一输出信号，并对所述第一输出信号进行数模转换处理，并将经过所述数模转换处理后的所述第一输出信号输入到所述功率放大器。
结合第一方面，在第一方面的某些实现方式中，该数字预失真电路还包括预处理模块，解算模块，所述解算模块预置有用于求解系数的算法，其中，所述第一输入信号和所述第二输出信号输入所述预处理模块，当所述第一输入信号和所述第二输出信号的邻道泄露比超过第一阈值和/或误差向量幅度超过第二阈值时，所述预处理模块，用于对所述第一输入信号和所述第二输出信号进行预处理以对齐所述第一输入信号和所述第二输出信号；将预处理后的第一输入信号和预处理后的第二输出信号输入到解算模块；所述解算模块，用于根据所述算法对所述预处理后的第一输入信号和所述预处理后的第二输出信号进行处理，以生成第三系数和第四系数；所述数字预失真模块，还用于根据所述第一输入信号与所述第三系数生成第三信号；根据所述第三信号与所述第四系数生成第三输出信号；将所述第三输出信号输入到所述功率放大器；所述功率放大器，用于将所述第三输出信号放大。
本申请实施例中，当第一输入信号和第二输出信号的ACLR超过第一阈值或EVM超过第二阈值时，数字预失真电路可以根据第一输入信号和第二输出信号重新解算新的系数，从而数字预失真电路可以根据第三系数和第四系数生成第三输出信号，然后将第三输出信号输入到功率放大器中，进而可以得到无失真的第四输出信号。
第二方面，提供了一种数字预失真方法，该方法包括：获取第一输入信号的第一特征和所述第一输入信号的第二特征，其中所述第一输入信号的第一特征包括以下至少一项：所述第一输入信号的幅值、所述第一输入信号的同相分量、所述第一输入信号的正交分量，所述第二特征包括以下至少一项：所述第一输入信号的带宽、所述数字预失真电路在处理所述第一输入信号时的温度、所述第一输入信号的频点、所述第一输入信号的调制格式、所述数字预失真电路处理所述第一输入信号产生的驻波；根据所述第一特征确定第一系数，根据所述第二特征确定第二系数；根据所述第一输入信号和所述第一系数生成第二信号；根据所述第二信号和所述第二系数生成第一输出信号；对所述第一输出信号进行功率放大 处理以生成第二输出信号。
结合第二方面，在第二方面的某些实现方式中，所述根据所述第一输入信号的第一特征和第二特征确定第一系数和第二系数，包括：根据所述第一特征确定N个第一子系数，根据所述第二特征确定N个第二子系数，所述N个第一子系数不同；所述根据所述第一输入信号和所述第一系数生成第二信号，包括：根据所述第一输入信号与所述N个第一子系数生成N个第二子信号；所述根据所述第二信号和所述第二系数生成第一输出信号，包括：根据所述N个第二子信号与所述N个第二子系数生成N个第一输出子信号；根据所述N个第一输出子信号生成第一输出信号。
结合第二方面，在第二方面的某些实现方式中，当所述第一输入信号和所述第二输出信号的邻道泄露比超过第一阈值和/或误差向量幅度超过第二阈值时，所述方法还包括：对所述第一输入信号和所述第二输出信号进行预处理以对齐所述第一输入信号和所述第二输出信号；对所述预处理后的第一输入信号和所述预处理后的第二输出信号进行处理，以生成第三系数和第四系数；根据所述第一输入信号和所述第三系数生成第三信号；根据所述第三信号和所述第四系数生成第三输出信号；对所述第三输出信号进行功率放大处理以生成第四输出信号。
结合第二方面，在第二方面的某些实现方式中，该第一特征还包括该第一输入信号承载的数据和/或该第二输入信号的信号幅值和/或该第二输入信号承载的数据，其中该第二输入信号是与该第一输入信号相差一定时间间隔的输入信号。
第三方面，提供了一种发射装置，该发射装置包括收发单元、数字预失真单元、功率放大单元，其中，所述收发单元，用于接收第一输入信号；所述数字预失真单元，用于获取所述第一输入信号的第一特征和所述第一输入信号的第二特征，其中所述第一输入信号的第一特征包括以下至少一项：所述第一输入信号的幅值、所述第一输入信号的同相分量、所述第一输入信号的正交分量，所述第二特征包括以下至少一项：所述第一输入信号的带宽、所述数字预失真电路在处理所述第一输入信号时的温度、所述第一输入信号的频点、所述第一输入信号的调制格式、所述数字预失真电路处理所述第一输入信号产生的驻波；根据所述第一特征确定第一系数，根据所述第二特征确定第二系数；根据所述第一输入信号与所述第一系数生成第二信号；根据所述第二信号与所述第二系数生成第一输出信号；将所述第一输出信号输入到所述功率放大单元；所述功率放大单元，用于将所述第一输出信号放大以生成第二输出信号；所述收发单元，还用于发送所述第二输出信号。
结合第三方面，在第三方面的某些实现方式中，该发射装置还包括系数单元，所述系数单元中存储有所述第一特征与所述第一系数的对应关系和所述第二特征与所述第二系数的对应关系；所述数字预失真单元，具体用于根据所述第一特征从所述系数单元提取所述第一系数和根据所述第二特征从所述系数单元提取所述第二系数。
结合第三方面，在第三方面的某些实现方式中，所述数字预处理单元，具体用于：根据所述第一特征确定N个第一子系数和根据所述第二特征确定N个第二子系数，所述N个第一子系数不同；根据所述第一输入信号与所述N个第一系数生成N个第二子信号；根据所述N个第二子信号与所述N个第二子系数生成N个第一输出子信号；根据所述N个第一输出子信号生成所述第一输出信号。
结合第三方面，在第三方面的某些实现方式中，所述发射装置还包括预处理单元和解 算单元，所述解算单元预置有用于求解系数的算法，其中，所述第一输入信号和所述第二输出信号输入所述预处理单元，当所述第一输入信号和所述第二输出信号的邻道泄露比超过第一阈值或误差向量幅度超过第二阈值时，所述预处理单元，用于对所述第一输入信号和所述第二输出信号进行预处理以对齐所述第一输入信号和所述第二输出信号；所述预处理单元，还用于将预处理后的第一输入信号和预处理后的第二输出信号输入到所述解算单元；所述解算单元，用于根据所述算法对所述预处理后的第一输入信号和所述预处理后的第二输出信号进行处理，以生成第三系数和第四系数；所述数字预失真单元，还用于根据所述第一输入信号与所述第三系数生成第三信号；根据所述第三信号与所述第四系数生成第三输出信号；将所述第三输出信号输入到所述功率放大单元；所述功率放大单元，还用于将所述第三输出信号进行放大；所述收发单元，还用于发送放大的所述第三输出信号。
结合第三方面，在第三方面的某些实现方式中，该第一特征还包括该第一输入信号承载的数据和/或该第二输入信号的信号幅值和/或该第二输入信号承载的数据，其中该第二输入信号是与该第一输入信号相差一定时间间隔的输入信号。
第四方面，提供了一种发射设备，该发射设备包括第一方面以及第一方面任一种可能的数字预失真电路，或包括第三方面以及第三方面任一种可能的发射装置。
第五方面，提供了一种发射设备，包括一个或多个处理器；一个或多个存储器；一个或多个收发器；所述一个或多个存储器存储有一个或多个计算机程序，所述一个或多个计算机程序包括指令，当所述指令被所述一个或多个处理器执行时，使得上述第二方面及其第二方面任一可能设计的技术方案被执行。
第六方面，提供了一种芯片，该芯片与电子设备中的存储器耦合，用于调用存储器中存储的计算机程序并执行本申请实施例第二方面及其第二方面任一可能设计的技术方案；本申请实施例中“耦合”是指两个部件彼此直接或间接地结合。
第七方面，提供了一种计算机可读存储介质，该计算机可读存储介质包括计算机程序，当计算机程序在通信装置上运行时，使得该电子设备执行如上述第二方面及其第二方面任一可能设计的技术方案。
第八方面，提供了一种计算机程序产品，该计算机程序产品包括计算机程序，当该计算机程序被运行时，使得该计算机执行如上述第二方面及其第二方面任一可能设计的技术方案。
其中，第二方面至第八方面的有益效果，请参见第一方面的有益效果，不重复赘述。
附图说明
图1是数字预失真的线性化方案的示意性流程图。
图2是本申请实施例提供的一种数字预失真电路的结构性示意图。
图3是本申请实施例提供的数字预失真模块确定第一系数的示意图。
图4是本申请实施例提供的另一种数字预失真模块确定第一系数的示意图。
图5是本申请实施例提供的数字预失真模块的结构示意图。
图6是本申请实施例提供的数字预失真子模块的结构示意图。
图7是本申请实施例提供的系数模块的结构示意图。
图8是本申请实施例提供的一种数字预失真电路的结构性示意图。
图9是本申请实施例提供的一种数字预失真电路的结构性示意图。
图10是本申请实施例提供的一种数字预失真电路的结构性示意图。
图11是本申请实施例提供的数字预失真方法的示意性流程图。
图12是根据本申请实施例提供的数字预失真方法的一例示意性流程图。
图13是根据本申请实施例提供的数字预失真方法的一例示意性流程图。
图14是本申请实施例提供的一种发射装置。
图15是本申请实施例提供的一种通讯装置。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
本申请实施例的技术方案可以应用于各种通信系统，例如：全球移动通讯(Global System of Mobile communication，GSM)系统、码分多址(Code Division Multiple Access，CDMA)系统、宽带码分多址(Wideband Code Division Multiple Access，WCDMA)系统、通用分组无线业务(General Packet Radio Service，GPRS)、长期演进(Long Term Evolution，LTE)系统、LTE频分双工(Frequency Division Duplex，FDD)系统、LTE时分双工(Time Division Duplex，TDD)、通用移动通信系统(Universal Mobile Telecommunication System，UMTS)、全球互联微波接入(Worldwide Interoperability for Microwave Access，WiMAX)通信系统、第五代(5th Generation，5G)系统或新无线(New Radio，NR)，以及未来演进的通信系统等。进一步的，本申请实施例提供的技术方案还可以应用于其他需要实现数字预失真处理的通信系统。在通信系统中，应用本申请实施例提供的技术方案的设备为发射设备，该发射设备可以是网络设备，也可以是终端设备。其中，发射设备也可以称为发送设备。
终端设备是一种具有无线收发功能的设备，可以部署在陆地上，包括室内或室外、手持、穿戴或车载；也可以部署在水面上(如轮船等)；还可以部署在空中(例如飞机、气球和卫星上等。所述终端设备可以经无线接入网(radio access network，RAN)与核心网进行通信，与RAN交换语音和/或数据。所述终端设备可以是手机(mobile phone)、平板电脑(Pad)、带无线收发功能的电脑、移动互联网设备(mobile internet device，MID)、可穿戴设备、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备、工业控制(industrial control)中的无线终端、无人驾驶(self driving)中的无线终端、远程医疗(remote medical)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧家庭(smart home)中的无线终端、无人机、无人机控制器等等。本申请的实施例对应用场景不做限定。终端设备有时也可以称为用户设备(user equipment，UE)、移动台和远方站等，本申请的实施例对终端设备所采用的具体技术、设备形态以及名称不做限定。
本申请实施例中涉及的网络设备包括基站(base station，BS)、网络控制器、移动交换中心或者其它接入网设备或核心网设备。其中，基站包括各种形式的宏基站，微基站，中继站，接入点等。例如，基站可以是GSM或CDMA中的基站：基站收发台(base transceiver station，BTS)；也可以是WCDMA中的基站：NodeB；还可以是LTE中的演进型基站：eNB或e-NodeB；也可以是5G系统中的基站，5G系统中的基站可以称为发送接收点 (transmission reception point，TRP)，也可以称为下一代节点B(generation Node B，gNB)；进一步的，基站还可以是未来网络中的基站，本申请对此不作限定。
本申请实施例提供的技术方案可以应用于发射设备中，进一步地，可以应用于发射设备的发射装置。
PA是非线性原件，为了让信号放大过程中不产生失真，需要对PA进行线性化处理。目前针对PA的线性化处理可以采用DPD方案。图1是采用数字预失真的线性化方案的示意性流程图，如图1所示，假设输入信号x(n)不经过DPD处理单元101处理，直接输入到PA102，输入信号x(n)经过PA102时，由于PA102的非线性特性，会导致信号失真，输出一个非线性的失真信号，会影响信号质量和通信效率。DPD处理单元101的用于在输入信号x(n)输入到PA102之前，对输入信号x(n)进行与PA102特性相反的预处理。图2中，DPD处理单元101上的坐标图中，横轴的P 输入表示输入到DPD处理单元101的信号，纵轴的P 输出表示DPD处理单元101输出后的信号，虚线表示输入到DPD处理单元101的无失真的输入信号x(n)，由于PA的非线性特性，需要在DPD处理单元101做一个与PA102的非线性特性相反的处理，即实线表示实际从DPD处理单元101输出的信号特性。PA102上的坐标图中，虚线表示输入到PA102无失真的信号，由于PA102的非线性特性，实线表示由于PA102的非线性特性导致的输入到PA102无失真的信号输出后的信号，可以看出，由于PA102的非线性特性，输出PA102后的会产生失真。因此，需要在DPD处理单元101做一个与PA102的非线性特性相反的处理。通过设置反馈电路单元103，即从PA输出后的一部分信号经过反馈电路单元103后传输到DPD处理单元101，DPD处理单元101通过对这部分信号的处理，可以获得PA102的非线性特性，从而可以预先在DPD处理单元101做一个与PA102的非线性特性相反的处理，然后将经过DPD处理单元101处理后的信号输入到PA102，PA102最终可以输出线性无失真的信号，保证了从PA102输出后的信号是线性无失真的。PA102右的坐标图中，实线表示PA102输出后的信号，可以看出，经过DPD处理单元101的预失真处理后，PA102输出的信号不会产生失真。
PA的非线性失真特性可以使用多项式表示，因此，可以使用多项式对PA进行建模。常见的PA模型有Volterra模型，记忆多项式(memory polynomial，MP)模型，广义记忆多项式(Generalized Memory Polynomial，GMP)模型，Wiener模型，Hammerstein模型等。记忆多项式模型的数学表达式如公式(1)所示：
Figure PCTCN2023070659-appb-000001
其中，x(n)表示输入信号，z(n)表示DPD处理单元的输出信号，K表示多项式阶数，Q表示记忆深度，a表示DPD系数。
为了利用公式(1)进行预失真处理需要计算DPD系数a，计算DPD系数a有多种方法，本申请实施例对此不作限定。
目前反馈电路单元在计算DPD系数时需要实时迭代会增加额外的功耗以及随着第二特征的变化(例如带宽、温度、频点等)，反馈电路单元难以快速的计算得到DPD系数，从而导致通信质量的下降。基于此，本申请实施例提供了一种数字预失真电路以及装置，可以降低功耗、提高通信质量。
图2示出了本申请实施例提供的一种数字预失真电路的结构示意图。如图2所示，该数字预失真电路200包括：DPD模块210和PA220，其中，
DPD模块210，用于获取第一输入信号的第一特征和第一输入信号的第二特征。
DPD模块210，用于分别根据第一输入信号的第一特征确定第一系数，根据第二特征确定第二特征第二系数。
DPD模块210，还用于根据第一输入信号与第一系数生成第二信号。
DPD模块210，还用于根据第二信号与第二系数生成第一输出信号。
DPD模块210，还用于将第一输出信号输入到功率放大器。
PA220，用于对第一输出信号进行放大。
本申请实施例中，可以将经过功率放大的第一输出信号称为第二输出信号。
本申请实施例提供的数字预失真电路，DPD模块可以根据第一输入信号的第一特征以及第二特征确定第一系数和第二系数，并利用第一系数和第二系数对第一输入信号做数字预失真处理，然后将经过数字预失真处理后的第一输出信号输入到PA220中，从而可以得到线性非失真的第二输出信号。
下面将详细介绍本申请实施例提供的数字预失真电路。
第一输入信号输入DPD模块210后，DPD模块210可以获取第一输入信号的第一特和第二特征，然后根据第一特征确定第一系数，根据第二特征第二特征确定第二系数。
本申请实施例对第一输入信号的类型不作限定，第一输入信号可以是调制信号，如LTE信号、5G信号等，也可以是连续波(continuous wave，CW)信号。
可选的，第一输入信号的第一特征可以是信号幅值。
可选的，第一输入信号的第一特征还可以包括第一输入信号承载的数据和/或第二输入信号的信号幅值和/或第二输入信号承载的数据，第一输入信号承载的数据可以是第一输入信号的同相分量、正交分量，其中第二输入信号可以是与第一输入信号相差一定时间间隔的输入信号。例如，第一输入信号为x(n)，第二输入信号可以是x(n-k)，则第一输入信号的特征还可以是第二输入信号的幅值，即|x(n-k)|。
DPD模块210可以通过以下几种方式确定第一系数。
一种可能的实现方式，DPD模块210存储有查找表(look-up table，LUT),该查找表可以理解为一种映射关系，该映射关系用于指示多个第一类特征与多个系数之间的对应关系，即将事先计算好的系数存储在表格中，然后DPD模块210可以根据第一输入信号的第一特征计算出在LUT的地址，从而可以确定第一系数，第一系数可以理解为是在该映射关系中与第一特征对应的系数。第一类特征包括幅值、同相分量、正交分量中的至少一种。
示例性的，以第一特征为第一输入信号的幅值为例，如图3所示，DPD模块210可以根据通过绝对值单元确定输入到DPD模块210的第一输入信号x(n)的绝对值为|x(n)|。第一输入信号的绝对值|x(n)|指示了第一输入信号的信号幅值。DPD模块210确定第一输入信号的绝对值|x(n)|后，可以通过延时单元调整后得到至少一个索引值。如图3所示，DPD模块210可以得到记忆深度为m 1的索引值|x(n-m 1)|，记忆深度为m 2的索引值|x(n-m 2)|，记忆深度为m 3的索引值|x(n-m 3)|，然后根据索引值可以确定该索引值对应的LUT，即可以确定3个LUT，然后根据第一输入信号的信号幅值在对应的LUT中查找对应的系数。本 申请实施例中将通过LUT确定的系数称为DPD系数。换句话说，通过第一输入信号的信号幅值可以确定记忆多项式中不同记忆项的DPD系数。
需要说明的是，记忆深度与记忆多项式相关，本申请实施例以DPD模块210通过延时单元得到3个记忆深度的索引值为例，但本申请实施例并不限定于此。
一种可能的实现方式，数字预失真电路200还包括系数模块230，该系数模块230存储有LUT，该查找表可以理解为一种映射关系，该映射关系用于指示多个第一类特征与多个系数之间的对应关系，即将事先计算好的系数存储在表格中，然后DPD模块210可以根据第一输入信号的第一特征计算出在LUT的地址，可以确定第一系数。
示例性的，如图4所示，第一输入信号经过绝对值单元后可以得到其绝对值|x(n)|。将第一输入信号的绝对值输入系数模块230，系数模块230可以通过延时单元调整得到记忆深度为m 1的索引值|x(n-m 1)|，记忆深度为m 2的索引值|x(n-m 2)|，记忆深度为m 3的索引值|x(n-m 3)|，然后根据索引值可以确定该索引值对应的LUT，即可以确定3个LUT，然后根据第一输入信号的信号幅值在对应的LUT中查找对应的系数，其中根据第一输入信号的信号幅值在对应的LUT中查找对应的系数时，可以确定不同记忆项的DPD系数，具体说明请参见后文。
可选的，第一输入信号的第二特征包括以下至少一项：第一输入信号的带宽、数字预失真电路在处理第一输入信号时的温度、第一输入信号的频点、第一输入信号的调制格式、数字预失真电路处理所述第一输入信号产生的驻波。
本申请实施例中，DPD模块可以通过以下几种方式确定第二系数。
一种可能的实现方式，DPD模块210存储有索引表。该索引表可以理解为一种映射关系，该映射关系用于指示多个第二类特征与多个系数之间的对应关系，DPD模块210可以根据第一输入信号的第二特征在该索引表中找出对应的第二系数。第二系数可以理解为是在该映射关系中与第二特征对应的系数。第二类特征包括：带宽、温度、频点、信号调制格式、驻波中的至少一种。
一种可能的实现方式，数字预失真电路200还包括系数模块230，该系数模块230存储有索引表。DPD模块210可以根据第一输入信号的第二特征在系数模块230中确定第二系数。
可以理解的是，当第一输入信号包括多个第二特征时，DPD模块210或系数模块230存储的索引表也是多个。
示例性的，第一输入信号包括M个第二特征时，DPD模块可以根据第一输入信号的M个第二特征确定M个第二子系数，即第二系数可以包括该M个第二子系数。例如，第二特征为带宽和温度，则DPD模块210或系数模块230可以存储有第一索引表和第二索引表，其中第一索引表对应带宽，第二索引表对应温度，从而可以根据带宽和温度分别在第一索引表和第二索引表中确定相应的系数。本申请实施例中，可以将根据第一输入信号的不同第二特征确定的系数集合称为第二系数，即第二系数可以包括多个根据第一输入信号的不同第二特征确定的系数。以上文为例，第二系数包括根据带宽确定的系数和根据温度确定的系数。
上文描述了DPD模块210根据第一输入信号的第一特征和第二特征确定第一系数和第二系数，下面将详细说明DPD模块210根据第一系数和第一输入信号生成第二信号， 以及根据第二信号和第二系数生成第一输出信号。
DPD模块210根据第一输入信号的第一特征确定第一系数后，该第一系数可以包括一个DPD系数或多个不同记忆项的DPD系数，DPD模块210可以将第一输入信号与第一系数相乘，即将第一输入信号与该一个DPD系数或多个不同记忆项的DPD系数相乘得到第二信号。在生成第二信号后，可以将第二信号与第二系数相乘得到第一输出信号。
可选的，在一些实施例中，DPD模块210可以包括N个DPD子模块和合成模块，其中N≥1且为整数。
图5所示为DPD模块210的结构示意图，如图5所示，DPD模块210包括N个DPD子模块和合成模块，其中该N个DPD子模块可以根据第一输入信号x(n)的第一特征确定N个第一子系数和根据第一输入信号的第二特征确定N个第二子系数，其中N≥1且为整数。该N个第一子系数中的每一个子系数可以包括一个DPD系数或多个DPD系数。第一子系数包括多个DPD系数可以理解为第一子系数包括不同记忆项的DPD系数。可以理解的是，该N个第一子系数可以构成第一系数，即第一系数可以包括该N个第一子系数。类似的，该第二系数包括该N个第二子系数。该N个DPD子模块可以根据该N个第一子系数和第一输入信号生成N个第二子信号，然后根据该N个第二子信号和N个第二子系数生成N个第一输出子信号。
需要说明的是，N的选取是权衡了最后输出性能与计算资源等因素考虑
可选的，在一些实施例中，N＝1，第二系数为常数。
可选的，在一些实施例中，N＝2。
图6所示为DPD子模块的结构示意图，如图6所示，DPD子模块可以包括数字预失真处理器和乘法器。第一输入信号x(n)输入到DPD子模块，预失真处理器可以根据第一输入信号确定第一子系数和第二系数，然后预失真处理器可以将第一输入信号与第一子系数相乘，即将第一输入信号与该一个DPD系数或多个不同记忆项的DPD系数相乘生成第二子信号，然后通过乘法器将第二子信号与第二系数相乘生成第一输出子信号。可以理解的是，通过该N个DPD子模块可以得到N个第一输出子信号，然后合成模块可以通过公式(2)得到第一输出信号。
Figure PCTCN2023070659-appb-000002
需要说明的是，本申请实施例中对于数字预失真处理器的架构并不限定，例如数字预失真处理器的架构可以是基于记忆多项式的架构。
DPD子模块可以通过以下几种方式确定第一子系数和第二系数。
一种可能的实现方式，每一个DPD子模块存储有该DPD子模块对应的LUT和索引表。每一个DPD子模块对应的LUT表可以包括不同记忆项的LUT。DPD子模块可以根据第一输入信号的第一特征以及第二特征确定第一子系数和第二系数。
应理解，针对DPD子模块存储有DPD子模块对应的LUT和索引表的描述可以参见上文，为了简洁，在此不再赘述。
一种可能的实现方式，DPD子模块可以通过系数模块230确定第一输入信号对应的第一子系数以及第二系数。
示例性的，系数模块230中存储有每一个DPD子模块对应的LUT和索引表。每一个 DPD子模块对应的LUT可以包括不同记忆项的子LUT。例如，图7所示为系数模块存储LUT和索引表的结构示意图，如图7所示，N个DPD子模块的每一个DPD子模块在系数模块230中对应有一个或多个子LUT和一个或多个环境索引表。子LUT表数量与记忆深度相关，如当MP模型记忆深度为3，子LUT表有3个；当GMP模型两个深度分别为3,5时，子LUT表为15个；不同DPD子模块中的记忆深度和记忆项可以是一样的也可以是不一样的。环境索引表的数量与第二特征相关，例如，当第二特征包括M个环境子特征时，该N个DPD子模块中的每个DPD子模块包括M个环境索引表。当第一输入信号输入DPD子模块时，每一个DPD子模块可以从对应的LUT和环境索引表中确定第一子系数和第二子系数，从而可以生成第一输出子信号。
需要说明的是，该N个DPD子模块中的每一个DPD子模块根据第一输入信号的第一特征和第二特征确定的第一子系数和第二子系数可以相同或不同。
DPD模块210生成第一输出信号后，可以将第一输出信号输入到PA220中，PA220可以根据第一输出信号生成第二输出信号。
本申请实施例提供的数字预失真电路，DPD模块210可以根据第一输入信号的第一特征以及第二特征确定第一系数和第二系数，并利用第一系数和第二系数对第一输入信号进行数字预失真处理，然后将经过数字预失真处理后的第一输出信号输入到PA220中，从而可以得到线性非失真的第二输出信号。
可选的，在一些实施例中，如图8所示，数字预失真电路200还包括系数模块230，该系数模块230存储有LUT和索引表。
应理解，针对系数模块230的描述可以参见上文，为了简洁，在此不再赘述。
可选的，在一些实施例中，PA可以是数字PA，也可以是模拟PA。如图9所示，数字预失真电路200还包括数模转换器(digital to analog converter，DAC)240。该DAC240用于将DPD模块210的第一输出信号进行转换得到模拟信号，并将该模拟信号输入到PA220中。
进一步的，在一些实施例中，数字预失真电路200在DAC和PA220之间还包括滤波器、混频器等无源器件。
需要说明的是，本申请实施例对无源器件的种类不作限定。
上文中的DPD模块210或系数模块230存储的LUT中的系数和索引表的系数可以是预先解算好的。
示例性的，以第二特征是带宽为例，在解算LUT中的系数和索引表的系数时，可以采集不同带宽下的DPD的输入信号以及PA的输出信号，从而可以通过解算算法求解得到DPD系数和索引系数。
示例性的，当第二特征包括多个时，例如第二特征包括带宽和温度时，在解算LUT中的系数和索引表的系数时，可以采集不同带宽以及温度下的DPD的输入信号以及PA的输出信号进行解算，从而可以得到两个索引表，分别对应带宽和温度两个第二特征。
可以理解的是，本申请实施例中，在解算输入信号与输出信号时，实现了输入信号的第二特征以及第一特征的解耦，从而可以得到第一特征对应的DPD系数以及第二特征对应的系数，进而当增加第二特征或某个第二特征的数值范围改变时，可以仅增加或调整第二特征对应的索引表而无需改变DPD的LUT，从而可以减少LUT的数量，减少存储器的 存储压力。
需要说明的是，在进行解算时，可以按照预设的非线性模型，通过解算算法确定第一系数和第二系数，例如，非线性模型可以是如公式(1)所示的记忆多项式模型，也可以是其他模型，本申请对此不作限定。此外，本申请实施例中对于解算的方法并不限定，例如可以采取最小二乘法(least square，LS)算法及其变形、最小均方(Least Mean Square，LMS)算法及其变形等。
可选的，在一些实施例中，如图10所示，数字预失真电路200还包括预处理模块250和解算模块260，解算模块260中可以预置有上文所述的求解系数的方法，其中
第一输入信号和第二输出信号输入到预处理模块250，预处理模块250的输入信号输入到解算模块260。
当第一输入信号和第二输出信号的邻道泄露比(adjacent channel leakage ration，ACLR)超过第一阈值和/或误差向量幅度(error vector magnitude，EVM)超过第二阈值时，
预处理模块250，用于对第一输入信号和第二输出信号进行预处理以对齐第一输入信号和第二输出信号。
本申请实施例中对于预处理模块250采取的预处理方法不作限定，例如，预处理模块250可以采用增益对齐、时延对齐、频相偏纠正等预处理方法。
预处理模块250，还用于将预处理后的第一输入信号和第二输出信号输入到解算模块260。
解算模块260，用于根据算法对预处理后的第一输入信号和第二输出信号进行处理，以生成第三系数和第四系数。
可选的，解算模块260，还用于将第三系数和第四系数发送到系数模块230。
DPD模块210，还用于根据第一输入信号与第三系数生成第三信号。
DPD模块210，还用于根据第三信号与第四系数生成第三输出信号。
DPD模块210，还用于将第三输出信号输入到PA220；
PA220，还用于对第三输出信号进行放大处理。
本申请实施例中，可以将经过放大处理的第三输出信号称为第四输出信号。
可选的，在一些实施例中，可以将第一系数替换为第三系数，将第二系数替换为第四系数。
本申请实施例中，当第一输入信号和第二输出信号的ACLR或EVM超过阈值时，数字预失真电路可以根据第一输入信号和第二输出信号重新解算新的系数，从而数字预失真电路可以根据第三系数和第四系数生成第三输出信号，然后将第三输出信号输入到功率放大器中，进而可以得到无失真的第四输出信号。
进一步的，在一些实施例中，数字预失真电路还可以包括缓存器，该缓存器用于存储第一输入信号和第二输出信号，然后将第一输入信号和第二输出信号输入到预处理模块。
本申请实施例中，数字预失真电路还可以包括预处理模块和解算模块，当系数模块中的系数无法保证DPD模块的性能时，可以实时的更新系数模块中的系数以适配输入信号，从而可以保证PA的输出信号不失真。
上文介绍了本申请实施例提供的数字预失真电路，下面将介绍本申请实施例提供的数字预失真方法，如图11所示为本申请实施例提供的数字预失真方法1100的示意性流程图， 该方法应用于发射装置或包括发射装置的发送装置，该发射装置包括DPD处理模块、PA和存储器，存储器中存储有DPD的LUT和索引表，如图11所示，该方法1100包括：
S1110，获取第一输入信号的第一特征和第一输入信号的第二特征。
具体的，发射装置可以获取第一输入信号，该第一输入信号可以是LTE信号、5G信号、连续波信号等，从而可以获取第一输入信号的第一特征和第一输入信号的第二特征。
S1120，根据第一输入信号的第一特征确定第一系数，根据第二特征确定第二系数。
具体的，发射装置可以根据第一输入信号的第一特征确定第一系数以及根据第二特征确定第二系数。
S1130，根据第一输入信号和第一系数生成第二信号。
具体的，发射装置可以根据第一输入信号和第一系数生成第二信号。
S1140，根据第二信号和第二系数生成第一输出信号。
具体的，发射装置可以根据第二信号和第二系数生成第一输出信号。
S1150，对第一输出信号进行功率放大处理以生成第二输出信号。
具体的，发射装置可以通过功率放大器对第一输出信号进行处理以生成第二输出信号。
应理解，针对S1110-S1150的描述可以参见上文，为了简洁，在此不再赘述。
本申请实施例中，发射装置可以根据第一输入信号的第一特征以及第二特征确定第一系数和第二系数，并利用第一系数和第二系数对第一输入信号做数字预失真处理，然后将经过数字预失真处理后的第一输出信号输入到功率放大器中，从而可以得到线性非失真的第二输出信号。
图12所示为根据本申请实施例提供的数字预失真方法的一例示意性流程图，如图12所示，S1120，根据第一输入信号的第一特征和第二特征确定第一系数和第二系数，包括：
S1121，根据第一输入信号的第一特征和第二特征确定N个第一子系数和N个第二子系数。
具体的，发射装置可以根据第一输入信号的第一特征以及第二特征确定N个第一子系数和N个第二子系数。
S1130，根据第一输入信号和第一系数生成第二信号，包括：
S1131，根据第一输入信号与N个第一子系数生成N个第二子信号。
具体的，发射装置可以根据第一输入信号和N个第一子系数生成N个第二子信号。
S1140，根据第二信号和第二系数生成第一输出信号，包括：
S1141，根据N个第二子信号与N个第二子系数生成N个第一输出子信号；
S1142，根据N个第一输出子信号生成第一输出信号。
具体的，发射装置可以根据N个第二子信号和N个第二系数生成N个第一输出子信号，然后求和该N个第一输出子信号以得到第一输出信号。
应理解，针对S1121、S1131、S1141和S1142的详细描述可以参见上文，为了简洁，在此不再赘述。
可选的，在一些实施例中，当第一输入信号的第二特征包括M个第二特征时，方法1100还包括：
根据第一输入信号的M个第二特征确定M个第二子系数。
S1120，根据第一输入信号的第二特征确定第二系数，包括：
根据M个第二子系数确定第二系数。
具体的，当发射装置确定M个第二子系数后，可以根据该M个子系数确定第二系数。
示例性的，可以将该M个第二子系数相乘以得到第二系数。
图13所示为根据本申请实施例提供的数字预失真方法的一例示意性流程图，如图13所示，当第一输入信号和第二输出信号的邻道泄露比超过第一阈值和/或误差向量幅度超过第二阈值时，方法1100还包括：
S1160，对第一输入信号和第二输出信号进行预处理以对齐第一输入信号和第二输出信号。
S1170，对预处理后的第一输入信号和预处理后的第二输出信号进行处理，以生成第三系数和第四系数；
S1180，根据第一输入信号和更第三系数生成第三信号。
S1190，根据第三信号和第四系数生成第三输出信号。
S11100，利用功率放大器对第三输出信号进行处理以生成第四输出信号。本申请实施例中，当第一输入信号和第二输出信号的ACLR超过第一阈值和/或EVM超过第二阈值时，数字预失真电路可以根据第一输入信号和第二输出信号重新解算新的系数，从而数字预失真电路可以根据第三系数和第四系数生成第三输出信号，然后将第三输出信号输入到功率放大器中，进而可以得到无失真的第四输出信号。
图14示出了本申请实施例提供的一种发射装置1400，该发射装置1400应用于发送设备，如图14所示，该发射装置1400包括收发单元1410、DPD单元1420、功率放大单元1430。
其中，收发单元1410，用于接收第一输入信号。
DPD单元1420，用于获取第一输入信号的第一特征和第一输入信号的第二特征。
DPD单元1420，用于根据第一第一特征确定第一系数和根据第二特征确定第二系数。
DPD单元1420，还用于根据第一输入信号与第一系数生成第二信号。
DPD单元1420，还用于根据第二信号与第二系数生成第一输出信号。
DPD单元1420，还用于将第一输出信号输入到功率放大单元1430。
功率放大单元1430，用于根据第一输出信号生成第二输出信号。
收发单元1410，还用于发送第二输出信号。
可选的，在一些实施例中，该发射装置还包括系数单元，系数单元存储有LUT和索引表。
DPD单元1420，具体用于根据第一特征从系数单元提取第一系数和根据第二特征从系数单元提取第二系数。
可选的，在一些实施例中，DPD单元1420，具体用于：
根据第一输入信号的第一特征确定N个第一子系数和根据第二特征确定N个第二子系数；
根据第一输入信号与N个第一系数生成N个第二子信号。
根据N个第二子信号与N个第二子系数生成N个第一输出子信号。
根据N个第一输出子信号生成第一输出信号。
可选的，在一些实施例中，第二特征包括M个第二子特征，DPD单元1420，具体用 于：
根据第一输入信号的M个第二子特征确定M个第二子系数，M≥1，且为整数；
根据M个第二子系数确定所述第二系数。
可选的，在一些实施例中，发射装置1400还包括预处理单元和解算单元，其中解算单元，解算单元可以预置有求解系数的算法，其中，第一输入信号和第二输出信号输入预处理单元，当第一输入信号和第二输出信号的邻道泄露比超过第一阈值或误差向量幅度超过第二阈值时，预处理单元，用于对第一输入信号和第二输出信号进行预处理以对齐第一输入信号和第二输出信号。
预处理单元，还用于将预处理后的第一输入信号和预处理后的第二输出信号输入到解算单元。
解算单元，用于根据算法对预处理后的第一输入信号和预处理后的第二输出信号进行处理，以生成第三系数和第四系数。
可选的，解算单元，还用于将第三系数和第四系数输入到系数单元。
DPD单元1420，还用于根据第一输入信号与第三系数生成第三信号。
DPD单元1420，还用于根据第三信号与更第四系数生成第三输出信号。
DPD单元1420，还用于将第三输出信号输入到功率放大单元1430。
功率放大单元1430，还用于根据第三输出信号生成第四输出信号。
收发单元1410，还用于发送第四输出信号。
如图15所示，本申请实施例还提供一种通信装置(例如发射设备)1500。该通信装置1500包括处理器1510，处理器1510与存储器1520耦合，存储器1520用于存储计算机程序或指令或者和/或数据，处理器1510用于执行存储器1520存储的计算机程序或指令和/或者数据，使得上文方法实施例中的方法被执行。
可选地，该通信装置1500包括的处理器1510为一个或多个。
可选地，该通信装置1500包括的存储器1520可以为一个或多个。
可选地，该存储器1520可以与该处理器1510集成在一起，或者分离设置。
可选地，如图15所示，该无线通信装置1500还可以包括收发器1530，收发器1530用于信号的接收和/或发送。例如，处理器1510用于控制收发器1530进行信号的接收和/或发送。
作为一种方案，该通信装置1500用于实现上文方法实施例中发射装置中的各单元执行的操作。
本申请实施例还提供一种计算机可读存储介质，其上存储有用于实现上述方法实施例中由发射装置执行的方法，或由发射装置执行的方法的计算机指令。
本申请实施例还提供一种计算机程序产品，该计算机程序被计算机执行时，使得该计算机可以实现上述方法实施例中由发射设备执行的方法。
本申请实施例还提供一种通信系统，该通信系统包括上文实施例中的通信设备。
上述提供的任一种无线通信装置中相关内容的解释及有益效果均可参考上文提供的对应的方法实施例，此处不再赘述。
在本申请实施例中，通信设备可以包括硬件层、运行在硬件层之上的操作系统层，以及运行在操作系统层上的应用层。其中，硬件层可以包括中央处理器(central processing unit， CPU)、内存管理单元(memory management unit，MMU)和内存(也称为主存)等硬件。操作系统层的操作系统可以是任意一种或多种通过进程(process)实现业务处理的计算机操作系统，例如，Linux操作系统、Unix操作系统、Android操作系统、iOS操作系统或windows操作系统等。应用层可以包含浏览器、通讯录、文字处理软件、即时通信软件等应用。
本申请实施例并未对本申请实施例提供的方法的执行主体的具体结构进行特别限定，只要能够通过运行记录有本申请实施例提供的方法的代码的程序，以根据本申请实施例提供的方法进行通信即可。例如，本申请实施例提供的方法的执行主体可以是终端设备或卫星，或者，是终端设备或卫星中能够调用程序并执行程序的功能模块。
本申请实施例的各个方面或特征可以实现成方法、装置或使用标准编程和/或工程技术的制品。本文中使用的术语“制品”可以涵盖可从任何计算机可读器件、载体或介质访问的计算机程序。例如，计算机可读介质可以包括但不限于：磁存储器件(例如，硬盘、软盘或磁带等)，光盘(例如，压缩盘(compact disc，CD)、数字通用盘(digital versatile disc，DVD)等)，智能卡和闪存器件(例如，可擦写可编程只读存储器(erasable programmable read-only memory，EPROM)、卡、棒或钥匙驱动器等)。
本文描述的各种存储介质可代表用于存储信息的一个或多个设备和/或其它机器可读介质。术语“机器可读介质”可以包括但不限于：无线信道和能够存储、包含和/或承载指令和/或数据的各种其它介质。
应理解，本申请实施例中提及的处理器可以是中央处理单元(central processing unit，CPU)，还可以是其他通用处理器、数字信号处理器(digital signal processor，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现成可编程门阵列(field programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
还应理解，本申请实施例中提及的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)。例如，RAM可以用作外部高速缓存。作为示例而非限定，RAM可以包括如下多种形式：静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic RAM，DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。
需要说明的是，当处理器为通用处理器、DSP、ASIC、FPGA或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件时，存储器(存储模块)可以集成在处理器中。
还需要说明的是，本文描述的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请实施例的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请实施例所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请实施例揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种数字预失真电路，其特征在于，所述数字预失真电路包括：数字预失真模块和功率放大器，其中，
    所述数字预失真模块，用于获取第一输入信号的第一特征和所述第一输入信号的第二特征，其中所述第一输入信号的第一特征包括以下至少一项：所述第一输入信号的幅值、所述第一输入信号的同相分量、所述第一输入信号的正交分量，所述第二特征包括以下至少一项：所述第一输入信号的带宽、所述数字预失真电路在处理所述第一输入信号时的温度、所述第一输入信号的频点、所述第一输入信号的调制格式、所述数字预失真电路处理所述第一输入信号产生的驻波，并用于根据所述第一特征确定第一系数，根据所述第二特征确定第二系数，用于根据所述第一输入信号与所述第一系数生成第二信号，并根据所述第二信号与所述第二系数生成第一输出信号，并将所述第一输出信号输入到所述功率放大器；
    所述功率放大器，用于对所述第一输出信号进行放大处理以生成第二输出信号。
  2. 根据权利要求1所述的数字预失真电路，其特征在于，所述数字预失真电路还包括系数模块，所述系数模块存储有所述第一特征与所述第一系数的对应关系和所述第二特征与所述第二系数的对应关系，所述数字预失真模块，具体用于根据所述第一特征从所述系数模块提取所述第一系数和根据所述第二特征从所述系数模块提取所述第二系数。
  3. 根据权利要求1或2所述的数字预失真电路，其特征在于，所述数字预失真模块包括N个数字预失真子模块和合成模块，所述N个数字预失真子模块，用于根据所述第一特征确定N个第一子系数，根据所述第二特征确定N个第二子系数，N≥1，且为整数，所述N个第一子系数不同；
    根据所述第一输入信号与所述N个第一子系数生成N个第二子信号；
    根据所述N个第二子信号与所述N个第二子系数生成N个第一输出子信号；
    所述合成模块，用于根据所述N个第一输出子信号生成所述第一输出信号。
  4. 根据权利要求1至3中任一项所述的数字预失真电路，其特征在于，所述数字预失真电路还包括预处理模块，解算模块，所述解算模块预置有用于求解系数的算法，其中，所述第一输入信号和所述第二输出信号输入所述预处理模块，当所述第一输入信号和所述第二输出信号的邻道泄露比超过第一阈值和/或误差向量幅度超过第二阈值时，所述预处理模块，用于对所述第一输入信号和所述第二输出信号进行预处理以对齐所述第一输入信号和所述第二输出信号；
    将预处理后的第一输入信号和预处理后的第二输出信号输入到解算模块；
    所述解算模块，用于根据所述算法对所述预处理后的第一输入信号和所述预处理后的第二输出信号进行处理，以生成第三系数和第四系数；
    所述数字预失真模块，还用于根据所述第一输入信号与所述第三系数生成第三信号；
    根据所述第三信号与所述第四系数生成第三输出信号；
    将所述第三输出信号输入到所述功率放大器；
    所述功率放大器，用于将所述第三输出信号放大。
  5. 根据权利要求1至4中任一项所述的数字预失真电路，其特征在于，所述数字预失真电路还包括数模转换器，其中
    所述数模转换器，用于从所述数字预失真电路获取所述第一输出信号，并对所述第一输出信号进行数模转换处理，并将经过所述数模转换处理后的所述第一输出信号输入到所述功率放大器。
  6. 一种数字预失真方法，其特征在于，所述方法包括：
    获取第一输入信号的第一特征和所述第一输入信号的第二特征，其中所述第一输入信号的第一特征包括以下至少一项：所述第一输入信号的幅值、所述第一输入信号的同相分量、所述第一输入信号的正交分量，所述第二特征包括以下至少一项：所述第一输入信号的带宽、所述数字预失真电路在处理所述第一输入信号时的温度、所述第一输入信号的频点、所述第一输入信号的调制格式、所述数字预失真电路处理所述第一输入信号产生的驻波；
    根据所述第一特征确定第一系数，根据所述第二特征确定第二系数；
    根据所述第一输入信号和所述第一系数生成第二信号；
    根据所述第二信号和所述第二系数生成第一输出信号；
    对所述第一输出信号进行功率放大处理以生成第二输出信号。
  7. 根据权利要求6所述的方法，其特征在于，所述根据所述第一输入信号的第一特征确定第一系数，根据所述第二特征确定第二系数，包括：
    根据所述第一特征确定N个第一子系数，根据所述第二特征确定N个第二子系数，所述N个第一子系数不同；
    所述根据所述第一输入信号和所述第一系数生成第二信号，包括：
    根据所述第一输入信号与所述N个第一子系数生成N个第二子信号；
    所述根据所述第二信号和所述第二系数生成第一输出信号，包括：
    根据所述N个第二子信号与所述N个第二子系数生成N个第一输出子信号；
    根据所述N个第一输出子信号生成第一输出信号。
  8. 根据权利要求6或7所述的方法，其特征在于，当所述第一输入信号和所述第二输出信号的邻道泄露比超过第一阈值和/或误差向量幅度超过第二阈值时，所述方法还包括：
    对所述第一输入信号和所述第二输出信号进行预处理以对齐所述第一输入信号和所述第二输出信号；
    对所述预处理后的第一输入信号和所述预处理后的第二输出信号进行处理，以生成第三系数和第四系数；
    根据所述第一输入信号和所述第三系数生成第三信号；
    根据所述第三信号和所述第四系数生成第三输出信号；
    对所述第三输出信号进行功率放大处理以生成第四输出信号。
  9. 一种发射装置，其特征在于，所述发射装置包括收发单元、数字预失真单元、功率放大单元，其中，
    所述收发单元，用于接收第一输入信号；
    所述数字预失真单元，用于获取所述第一输入信号的第一特征和所述第一输入信号的 第二特征，其中所述第一输入信号的第一特征包括以下至少一项：所述第一输入信号的幅值、所述第一输入信号的同相分量、所述第一输入信号的正交分量，所述第二特征包括以下至少一项：所述第一输入信号的带宽、所述数字预失真电路在处理所述第一输入信号时的温度、所述第一输入信号的频点、所述第一输入信号的调制格式、所述数字预失真电路处理所述第一输入信号产生的驻波；
    根据所述第一特征确定第一系数，根据所述第二特征确定第二系数；
    根据所述第一输入信号与所述第一系数生成第二信号；
    根据所述第二信号与所述第二系数生成第一输出信号；
    将所述第一输出信号输入到所述功率放大单元；
    所述功率放大单元，用于将所述第一输出信号放大以生成第二输出信号；
    所述收发单元，还用于所述第二输出信号。
  10. 根据权利要求9所述的发射装置，其特征在于，所述发射装置还包括系数单元，所述系数单元中存储有所述第一特征与所述第一系数的对应关系和所述第二特征与所述第二系数的对应关系；
    所述数字预失真单元，具体用于根据所述第一特征从所述系数单元提取所述第一系数和根据所述第二特征从所述系数单元提取所述第二系数。
  11. 根据权利要求9或10所述的发射装置，其特征在于，所述数字预处理单元，具体用于：
    根据所述第一特征确定N个第一子系数和根据所述第二特征确定N个第二子系数，所述N个第一子系数不同；
    根据所述第一输入信号与所述N个第一系数生成N个第二子信号；
    根据所述N个第二子信号与所述N个第二子系数生成N个第一输出子信号；
    根据所述N个第一输出子信号生成所述第一输出信号。
  12. 根据权利要求9至11中任一项所述的发射装置，其特征在于，所述发射装置还包括预处理单元和解算单元，所述解算单元预置有用于求解系数的算法，其中，所述第一输入信号和所述第二输出信号输入所述预处理单元，当所述第一输入信号和所述第二输出信号的邻道泄露比超过第一阈值或误差向量幅度超过第二阈值时，所述预处理单元，用于对所述第一输入信号和所述第二输出信号进行预处理以对齐所述第一输入信号和所述第二输出信号；
    所述预处理单元，还用于将预处理后的第一输入信号和预处理后的第二输出信号输入到所述解算单元；
    所述解算单元，用于根据所述算法对所述预处理后的第一输入信号和所述预处理后的第二输出信号进行处理，以生成第三系数和第四系数；
    所述数字预失真单元，还用于根据所述第一输入信号与所述第三系数生成第三信号；
    根据所述第三信号与所述第四系数生成第三输出信号；
    将所述第三输出信号输入到所述功率放大单元；
    所述功率放大单元，还用于将所述第三输出信号放大；
    所述收发单元，还用于发送放大的所述第三输出信号。
  13. 一种发射设备，其特征在于，所述发射设备包括如权利要求1至5中任一项所述 的数字预失真电路，或所述发射设备包括如权利要求9至12中任一项所述的发射装置。
  14. 一种发射设备，其特征在于，包括一个或多个处理器；一个或多个存储器；一个或多个收发器；所述一个或多个存储器存储有一个或多个计算机程序，所述一个或多个计算机程序包括指令，当所述指令被所述一个或多个处理器执行时，使得如权利要求6至8中任一项所述的方法被执行。
  15. 一种计算机可读存储介质，其特征在于，存储有计算机程序或指令，所述计算机程序或指令用于实现如权利要求6至8中任一项所述的方法。
  16. 一种计算机程序产品，所述计算机程序产品包括计算机程序，当所述计算机程序被运行时，使得计算机执行如权利要求6至8中任一项所述的方法。
  17. 一种芯片，其特征在于，所述芯片包括处理器和通信接口，所述通信接口用于接收信号，并将所述信号传输至所述处理器，所述处理器处理所述信号，使得如权利要求6至8中任一项所述的方法被执行。
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