WO2023224092A1

WO2023224092A1 - Nitride semiconductor device

Info

Publication number: WO2023224092A1
Application number: PCT/JP2023/018581
Authority: WO
Inventors: 浩隆大嶽
Original assignee: ローム株式会社
Priority date: 2022-05-20
Filing date: 2023-05-18
Publication date: 2023-11-23

Abstract

This nitride semiconductor device is provided with: a semiconductor substrate; a transistor which is configured from a nitride semiconductor that is formed on the semiconductor substrate, while comprising a drain electrode, a source electrode, a gate electrode, and a Schottky diode and a first PIN diode that are formed between the gate electrode and the source electrode; and a temperature sensor which is provided on the semiconductor substrate in a different position from the transistor, while comprising a second PIN diode that is configured from a nitride semiconductor.

Description

nitride semiconductor device

The present disclosure relates to a nitride semiconductor device.

Currently, high electron mobility transistors (HEMTs), which are a type of nitride semiconductor devices using nitride semiconductors, are being commercialized (for example, see Patent Document 1).

JP2017-73506A

By the way, a nitride semiconductor device using a nitride semiconductor has a higher temperature dependence of on-resistance than, for example, a transistor using silicon carbide (SiC). Therefore, in a nitride semiconductor device using a nitride semiconductor, improved accuracy of temperature detection and appropriate control based on temperature information may be required.

A nitride semiconductor device according to one aspect of the present disclosure includes a semiconductor substrate, a nitride semiconductor formed on the semiconductor substrate, and includes a drain electrode, a source electrode, a gate electrode, the gate electrode and the source. A transistor including a Schottky diode and a first PIN diode formed between an electrode and a second PIN diode provided at a different position from the transistor on the semiconductor substrate and made of the nitride semiconductor. A temperature sensor.

According to the nitride semiconductor device of the present disclosure, it is possible to improve the accuracy of temperature detection.

FIG. 1 is a schematic cross-sectional view of a transistor in an exemplary nitride semiconductor device according to a first embodiment. FIG. 2 is a schematic cross-sectional view of a temperature sensor in the exemplary nitride semiconductor device according to the first embodiment. FIG. 3 is a schematic plan view showing an exemplary formation pattern of the nitride semiconductor device of FIGS. 1 and 2. FIG. FIG. 4 is a schematic back view of the nitride semiconductor unit of FIG. 3. FIG. 5 is a schematic cross-sectional view showing an exemplary manufacturing process of the nitride semiconductor device of the first embodiment. FIG. 6 is a schematic cross-sectional view showing the manufacturing process following FIG. 5. FIG. 7 is a schematic cross-sectional view showing the manufacturing process following FIG. 6. FIG. 8 is a schematic cross-sectional view showing the manufacturing process following FIG. 7. FIG. 9 is a schematic cross-sectional view showing the manufacturing process following FIG. 8. FIG. 10 is a schematic cross-sectional view showing the manufacturing process following FIG. 9. FIG. 11 is a schematic cross-sectional view showing the manufacturing process following FIG. 10. FIG. 12 is a schematic cross-sectional view showing the manufacturing process following FIG. 11. FIG. 13 is a schematic cross-sectional view of a temperature sensor in an exemplary nitride semiconductor device according to the second embodiment. FIG. 14 is a schematic cross-sectional view showing an exemplary manufacturing process of the nitride semiconductor device of the second embodiment. FIG. 15 is a schematic cross-sectional view showing the manufacturing process following FIG. 14. FIG. 16 is a schematic cross-sectional view showing the manufacturing process following FIG. 15. FIG. 17 is a schematic cross-sectional view showing the manufacturing process following FIG. 16. FIG. 18 is a schematic cross-sectional view showing the manufacturing process following FIG. 17. FIG. 19 is a schematic cross-sectional view showing the manufacturing process following FIG. 18. FIG. 20 is a schematic cross-sectional view showing the manufacturing process following FIG. 19. FIG. 21 is a schematic cross-sectional view showing the manufacturing process following FIG. 20. FIG. 22 is a schematic plan view showing an exemplary formation pattern of a modified nitride semiconductor device. FIG. 23 is a schematic cross-sectional view of the nitride semiconductor device taken along line F23-F23 in FIG.

Hereinafter, some embodiments of a nitride semiconductor device according to the present disclosure will be described with reference to the accompanying drawings.
It should be noted that, for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Further, in order to facilitate understanding, hatching lines may be omitted in the cross-sectional views. The accompanying drawings are merely illustrative of embodiments of the disclosure and should not be considered as limiting the disclosure.

The following detailed description includes devices, systems, and methods that embody example embodiments of the present disclosure. This detailed description is illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

<First embodiment>
[Cross-sectional structure of nitride semiconductor device]
1 and 2 are schematic cross-sectional views of an exemplary nitride semiconductor device 10 according to the first embodiment. Note that the term "planar view" used in the present disclosure refers to viewing the nitride semiconductor device 10 in the Z-axis direction of the mutually orthogonal XYZ axes shown in FIG. Further, in the nitride semiconductor device 10 shown in FIG. 1, for convenience, the +Z direction is defined as top, the -Z direction as bottom, the +X direction as right, and the -X direction as left. Unless explicitly stated otherwise, "planar view" refers to viewing nitride semiconductor device 10 from above along the Z-axis.

The nitride semiconductor device 10 is a high electron mobility transistor (HEMT) using a nitride semiconductor. Nitride semiconductor device 10 includes a semiconductor substrate 12, a nitride semiconductor 13 formed on the semiconductor substrate 12, and a passivation layer 22 covering the nitride semiconductor 13. The nitride semiconductor 13 includes a buffer layer 14, a first nitride semiconductor layer 16 formed on the buffer layer 14, a second nitride semiconductor layer 18 formed on the first nitride semiconductor layer 16, and a second nitride semiconductor layer 18 formed on the first nitride semiconductor layer 16. and a third nitride semiconductor layer 20 formed on the second nitride semiconductor layer 18 .

As the semiconductor substrate 12, for example, a silicon (Si) substrate can be used. Alternatively, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a sapphire substrate can be used instead of the Si substrate. The thickness of the semiconductor substrate 12 can be, for example, 200 μm or more and 1500 μm or less. In the following description, unless explicitly stated otherwise, thickness refers to the dimension along the Z direction in FIGS. 1 and 2.

The buffer layer 14 may be made of any material that can suppress the occurrence of wafer warpage and cracking due to mismatch in thermal expansion coefficients between the semiconductor substrate 12 and the first nitride semiconductor layer 16. Additionally, buffer layer 14 can include one or more nitride semiconductor layers. Buffer layer 14 may include, for example, at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer with a different aluminum (Al) composition. For example, the buffer layer 14 is made of a single film of AlN, a single film of AlGaN, a film having an AlGaN/GaN superlattice structure, a film having an AlN/AlGaN superlattice structure, a film having an AlN/GaN superlattice structure, or the like. may have been done.

In one example, the buffer layer 14 includes a first buffer layer that is an AlN layer formed on the semiconductor substrate 12 and a second buffer layer that is an AlGaN layer formed on the AlN layer (first buffer layer). Can be done. The first buffer layer may be, for example, an AlN layer with a thickness of 200 nm, and the second buffer layer may be a graded AlGaN layer, for example, with a thickness of 300 nm. Note that in order to suppress leakage current in the buffer layer 14, impurities may be introduced into a portion of the buffer layer 14 to make the buffer layer 14 semi-insulating except for the surface layer region. In this case, the impurity is, for example, carbon (C) or iron (Fe). The impurity concentration can be, for example, 4×10 ¹⁶ cm ⁻³ or higher.

Since the first nitride semiconductor layer 16 is formed on the buffer layer 14 formed on the semiconductor substrate 12, it can be said that it is formed on the semiconductor substrate 12 in a broad sense. The first nitride semiconductor layer 16 includes an electron transit layer. The first nitride semiconductor layer 16 may be, for example, a GaN layer. The thickness of the first nitride semiconductor layer 16 can be, for example, 0.5 μm or more and 2 μm or less. Note that in order to suppress leakage current in the first nitride semiconductor layer 16, impurities are introduced into a part of the first nitride semiconductor layer 16 to make the area other than the surface layer of the first nitride semiconductor layer 16 semi-insulating. You may also do so. In this case, the impurity is, for example, C. The concentration of impurities can be, for example, 4×10 ¹⁶ cm ⁻³ or more. That is, the first nitride semiconductor layer 16 can include a plurality of GaN layers having different impurity concentrations, for example, a C-doped GaN layer and a non-doped GaN layer. In this case, a C-doped GaN layer is formed on the buffer layer 14. The C-doped GaN layer can have a thickness of 0.5 μm or more and 2 μm or less. The C concentration in the C-doped GaN layer can be set to 5×10 ¹⁷ cm ⁻³ or more and 9×10 ¹⁹ cm ⁻³ or less. The non-doped GaN layer is formed on the C-doped GaN layer. The undoped GaN layer can have a thickness of 0.05 μm or more and 0.4 μm or less. The non-doped GaN layer is in contact with the second nitride semiconductor layer 18. In one example, the first nitride semiconductor layer 16 includes a C-doped GaN layer with a thickness of 0.4 μm and a non-doped GaN layer with a thickness of 0.4 μm. The C concentration in the C-doped GaN layer is approximately 2×10 ¹⁹ cm ⁻³ .

The second nitride semiconductor layer 18 includes an electron supply layer having a larger band gap than the first nitride semiconductor layer 16. The second nitride semiconductor layer 18 may be, for example, an AlGaN layer. In a nitride semiconductor, the higher the Al composition, the larger the band gap. Therefore, the second nitride semiconductor layer 18, which is an AlGaN layer, has a larger band gap than the first nitride semiconductor layer 16, which is a GaN layer. In one example, the second nitride semiconductor layer 18 is made of Al _x Ga _1-x N. In other words, the second nitride semiconductor layer 18 can be said to be an Al _x Ga _1-x N layer. x is 0<x<0.4, more preferably 0.1<x<0.3. The second nitride semiconductor layer 18 can have a thickness of, for example, 5 nm or more and 20 nm or less.

The first nitride semiconductor layer 16 and the second nitride semiconductor layer 18 have different lattice constants in the bulk region. Therefore, the first nitride semiconductor layer 16 and the second nitride semiconductor layer 18 are a lattice mismatched junction. The first nitride semiconductor layer 16 is caused by the spontaneous polarization of the first nitride semiconductor layer 16 and the second nitride semiconductor layer 18 and the piezo polarization caused by compressive stress applied to the heterojunction of the first nitride semiconductor layer 16. The energy level of the conduction band of the first nitride semiconductor layer 16 near the heterojunction interface between the first nitride semiconductor layer 16 and the second nitride semiconductor layer 18 is lower than the Fermi level. As a result, there is a two-dimensional structure in the first nitride semiconductor layer 16 at a position close to the heterojunction interface between the first nitride semiconductor layer 16 and the second nitride semiconductor layer 18 (for example, at a distance of several nm from the interface). Electron gas (2DEG) 24 is spreading.

The third nitride semiconductor layer 20 is formed on the second nitride semiconductor layer 18. The third nitride semiconductor layer 20 has a smaller band gap than the second nitride semiconductor layer 18 and is made of a nitride semiconductor containing acceptor type impurities. The third nitride semiconductor layer 20 may be made of any material having a smaller bandgap than the second nitride semiconductor layer 18, which is an AlGaN layer, for example. In one example, the third nitride semiconductor layer 20 is a GaN layer (p-type GaN layer) doped with acceptor type impurities. The acceptor type impurity can include at least one of zinc (Zn), magnesium (Mg), and C. The maximum concentration of acceptor type impurities in the third nitride semiconductor layer 20 is, for example, 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²⁰ cm ⁻³ or less.

Passivation layer 22 covers third nitride semiconductor layer 20 . The passivation layer 22 is made of, for example, one of silicon nitride (SiN), silicon dioxide (SiO ₂ ), silicon oxynitride (SiON), alumina (Al ₂ O ₃ ), AlN, and aluminum oxynitride (AlON). The material may be made up of materials including: In one example, passivation layer 22 is formed of a material containing SiN.

As shown in FIG. 1, nitride semiconductor device 10 includes a transistor 11 made of nitride semiconductor 13. As shown in FIG.
Transistor 11 includes a gate layer 26, a source electrode 28, a drain electrode 30, and a gate electrode 32. Gate layer 26 and gate electrode 32 are covered by passivation layer 22 . Passivation layer 22 has a source opening 22A and a drain opening 22B. Both the source opening 22A and the drain opening 22B expose the second nitride semiconductor layer 18. The source electrode 28 is in contact with the second nitride semiconductor layer 18 through the source opening 22A. Drain electrode 30 is in contact with second nitride semiconductor layer 18 via drain opening 22B.

The gate layer 26 is composed of the third nitride semiconductor layer 20. That is, the gate layer 26 is included in the third nitride semiconductor layer 20. Therefore, the gate layer 26 can also be said to be a GaN layer (p-type GaN layer) doped with acceptor type impurities. Gate layer 26 is partially formed on second nitride semiconductor layer 18 .

As described above, by including the acceptor type impurity in the gate layer 26, the energy levels of the first nitride semiconductor layer 16 and the second nitride semiconductor layer 18 are raised. Therefore, in the region immediately below the gate layer 26, the energy level of the conduction band of the first nitride semiconductor layer 16 near the heterojunction interface between the first nitride semiconductor layer 16 and the second nitride semiconductor layer 18 is , approximately equal to or larger than the Fermi level. Therefore, at zero bias when no voltage is applied to the gate electrode 32, the 2DEG 24 is not formed in the first nitride semiconductor layer 16 in the region immediately below the gate layer 26. On the other hand, a 2DEG 24 is formed in the first nitride semiconductor layer 16 in a region other than the region directly under the gate layer 26.

In this way, the presence of the gate layer 26 doped with acceptor type impurities causes the 2DEG 24 to be depleted in the region immediately below the gate layer 26. As a result, normally-off operation of the nitride semiconductor device 10 is realized. When an appropriate on-voltage is applied to the gate electrode 32, a channel is formed by the 2DEG 24 in the first nitride semiconductor layer 16 in the region immediately below the gate electrode 32, so that conduction occurs between the source and the drain.

The gate layer 26 includes a bottom surface 26A in contact with the second nitride semiconductor layer 18 and a top surface 26B on the opposite side from the bottom surface 26A. The gate electrode 32 is formed on the upper surface 26B of the gate layer 26. The gate layer 26 can have a rectangular, trapezoidal, or ridge-shaped cross section in the XZ plane in FIG.

In this embodiment, the gate layer 26 includes a gate ridge portion 26C including an upper surface 26B on which the gate electrode 32 is formed, and two gate extension portions (a first gate extension portion) extending outside the gate ridge portion 26C in plan view. portion 26D and second gate extension portion 26E). Therefore, the upper surface 26B of the gate layer 26 refers to the upper surface formed in the gate ridge portion 26C.

The first gate extension portion 26D extends from the gate ridge portion 26C toward the source opening portion 22A in plan view. The first gate extension 26D is spaced apart from the source opening 22A.

The second gate extension portion 26E extends from the gate ridge portion 26C toward the drain opening 22B in plan view. The second gate extension 26E is spaced apart from the drain opening 22B.

The gate ridge portion 26C is located between the first gate extension portion 26D and the second gate extension portion 26E, and is formed integrally with the first gate extension portion 26D and the second gate extension portion 26E. The first gate extension portion 26D and the second gate extension portion 26E are formed to sandwich the gate ridge portion 26C in the width direction (X-axis direction) of the gate ridge portion 26C.

Due to the presence of the first gate extension part 26D and the second gate extension part 26E, the bottom surface 26A of the gate layer 26 has a larger area than the top surface 26B. In this embodiment, the second gate extension part 26E extends longer toward the outside of the gate ridge part 26C in plan view than the first gate extension part 26D.

The gate ridge portion 26C corresponds to a relatively thick portion of the gate layer 26, and has a thickness of, for example, 80 nm or more and 150 nm or less. The thickness of the gate layer 26, particularly the gate ridge portion 26C, can be determined in consideration of parameters including the gate threshold voltage. In one example, gate layer 26 (gate ridge portion 26C) has a thickness greater than 110 nm.

Each of the first gate extension part 26D and the second gate extension part 26E has a thickness smaller than the thickness of the gate ridge part 26C. In one example, each of the first gate extension part 26D and the second gate extension part 26E has a thickness that is 1/2 or less of the thickness of the gate ridge part 26C.

In this embodiment, each

gate extension portion

26D, 26E is a flat portion having a substantially constant thickness. Note that in this specification, "substantially constant thickness" refers to a thickness within a range of manufacturing variations (for example, 20%). Alternatively, each

gate extension portion

26D, 26E may include a tapered portion having a thickness that gradually decreases as the distance from the gate ridge portion 26C increases in a region adjacent to the gate ridge portion 26C. Each

gate extension portion

26D, 26E may include a flat portion having a substantially constant thickness in a region beyond a predetermined distance from the gate ridge portion 26C. In one example, the flat portion has a thickness of 5 nm or more and 25 nm or less.

The gate electrode 32 includes a bottom surface 32A in contact with the gate layer 26, a top surface 32B opposite to the bottom surface 32A, and a side surface 32C extending between the bottom surface 32A and the top surface 32B. Gate electrode 32 is composed of one or more metal layers. The gate electrode 32 is, for example, a titanium nitride (TiN) layer. Alternatively, the gate electrode 32 may include a first metal layer made of a material containing Ti, and a second metal layer laminated on the first metal layer and made of a material containing TiN. . The thickness of the gate electrode 32 may be, for example, 50 nm or more and 200 nm or less. The gate electrode 32 can form a Schottky junction with the gate layer 26. Thus, transistor 11 includes a Schottky diode 34 configured between gate electrode 32 and gate layer 26.

Furthermore, a first PIN diode 36 is configured between the gate layer 26, the second nitride semiconductor layer 18, and the first nitride semiconductor layer 16. In other words, the first PIN diode 36 is configured between the third nitride semiconductor layer 20, the second nitride semiconductor layer 18, and the first nitride semiconductor layer 16. More specifically, the first PIN diode 36 is configured between the third nitride semiconductor layer 20, the second nitride semiconductor layer 18, and the 2DEG 24. It can also be said that the first PIN diode 36 is configured between the gate layer 26, the second nitride semiconductor layer 18, and the 2DEG 24. That is, the transistor 11 includes the first PIN diode 36. In this way, the nitride semiconductor device 10 includes the drain electrode 30, the source electrode 28, the gate electrode 32, the Schottky diode 34 and the first PIN diode 36 formed between the gate electrode 32 and the source electrode 28, including.

Here, the PIN diode is a diode that includes an undoped intrinsic semiconductor (I-type semiconductor) between a p-type semiconductor and an n-type semiconductor. In the first PIN diode 36, the third nitride semiconductor layer 20 constitutes a p-type semiconductor, the 2DEG 24 constitutes an n-type semiconductor, and the second nitride semiconductor layer 18 constitutes an intrinsic semiconductor.

The source electrode 28 and the drain electrode 30 are composed of one or more metal layers (eg, Ti, Al, AlCu, TiN, etc.). The source electrode 28 and the drain electrode 30 are in ohmic contact with the 2DEG 24 via the source opening 22A and drain opening 22B, respectively. That is, both the source electrode 28 and the drain electrode 30 are electrically connected to the 2DEG 24.

The source electrode 28 includes a source contact portion 28A and a source field plate portion 28B continuous with the source contact portion 28A. The source contact portion 28A corresponds to a portion filled in the source opening 22A. The source field plate portion 28B is formed integrally with the source contact portion 28A. Source field plate portion 28B covers passivation layer 22. Source field plate portion 28B includes an end portion 28C located between drain opening 22B and gate layer 26 in plan view. Therefore, the source field plate portion 28B is spaced apart from the drain electrode 30 formed in the drain opening 22B. The source field plate portion 28B extends along the surface of the passivation layer 22 from the source contact portion 28A to the end portion 28C toward the drain electrode 30. The passivation layer 22 covers the upper surface of the second nitride semiconductor layer 18, the side surfaces and upper surface 26B of the gate layer 26, and the side surfaces 32C and upper surface 32B of the gate electrode 32. Therefore, the source field plate portion 28B extending along the surface of the passivation layer 22 has a non-flat surface. The source field plate portion 28B plays a role of alleviating electric field concentration near the end of the gate electrode 32 during zero bias when no gate voltage is applied to the gate electrode 32.

The drain electrode 30 includes a drain contact portion 30A and a drain plate portion 30B continuous to the drain contact portion 30A. The drain contact portion 30A corresponds to a portion filled in the drain opening 22B. The drain plate portion 30B is formed integrally with the drain contact portion 30A. Drain plate portion 30B covers passivation layer 22. The drain plate portion 30B is formed at the periphery of the drain opening 22B in the passivation layer 22.

Although not shown, the nitride semiconductor device 10 can further include an interlayer insulating layer, a source wiring, a drain wiring, and a gate wiring.
The interlayer insulating layer covers the source electrode 28 and the drain electrode 30. The interlayer insulating layer may be made of a material containing, for example, any one of SiN, SiO ₂ , SiON, Al ₂ O ₃ , AlN, and AlON. In one example, the interlayer insulating layer is formed of a material containing _SiO2 .

The source wiring, drain wiring, and gate wiring are formed so as to be separated from each other on the interlayer insulating layer. The source wiring is electrically connected to the source electrode 28. The drain wiring is electrically connected to the drain electrode 30. The gate wiring is electrically connected to the gate electrode 32. Each of the source wiring, drain wiring, and gate wiring is composed of one or more metal layers. The metal layer may be made of a material containing, for example, any one of copper (Cu), Al, Ti, and TiN. In one example, each of the source wiring, drain wiring, and gate wiring is formed of a laminated structure of Ti, TiN, AlCu, and TiN.

(temperature sensor)
As shown in FIG. 2, the nitride semiconductor device 10 further includes a temperature sensor 40 including a second PIN diode 42 made of the nitride semiconductor 13. Therefore, it can be said that the temperature sensor 40 is composed of the nitride semiconductor 13. In this way, nitride semiconductor device 10 includes both transistor 11 (see FIG. 1) and temperature sensor 40. In other words, the nitride semiconductor device 10 includes a transistor 11 made of a nitride semiconductor 13 formed on a semiconductor substrate 12 and a temperature sensor 40 .

Similarly to the first PIN diode 36, the second PIN diode 42 is configured between the third nitride semiconductor layer 20, the second nitride semiconductor layer 18, and the first nitride semiconductor layer 16. More specifically, the second PIN diode 42 is configured between the third nitride semiconductor layer 20, the second nitride semiconductor layer 18, and the 2DEG 24. The third nitride semiconductor layer 20 includes a sensor layer 44 that constitutes a second PIN diode 42 . The sensor layer 44 is provided separately from the gate layer 26 (see FIG. 1), and is a GaN layer (p-type GaN layer) doped with acceptor type impurities like the gate layer 26. In one example, the impurity concentration of sensor layer 44 is equal to the impurity concentration of gate layer 26. Sensor layer 44 is spaced apart from gate layer 26. The second PIN diode 42 is configured between the sensor layer 44, the second nitride semiconductor layer 18, and the first nitride semiconductor layer 16. More specifically, the second PIN diode 42 is configured between the sensor layer 44, the second nitride semiconductor layer 18, and the 2DEG 24. In the second PIN diode 42, the sensor layer 44 is a p-type semiconductor, the 2DEG 24 is an n-type semiconductor, and the second nitride semiconductor layer 18 is an intrinsic semiconductor (I-type semiconductor).

The sensor layer 44 includes a bottom surface that is in contact with the second nitride semiconductor layer 18 and an upper surface that is opposite to the bottom surface. The sensor layer 44 can have a rectangular, trapezoidal, or ridge-shaped cross section in the XZ plane in FIG. 2 . In this embodiment, the sensor layer 44 has a different cross section than the gate layer 26 in the XZ plane in FIG. Specifically, the sensor layer 44 has a rectangular cross section in the XZ plane in FIG. 2 .

In this embodiment, the thickness TS of the sensor layer 44 is thinner than the thickness TG of the gate layer 26 (see FIG. 1). Here, the thickness TG of the gate layer 26 is the thickness TGC of the gate ridge portion 26C (see FIG. 1). The thickness of the gate ridge portion 26C can be defined by the distance between the bottom surface 26A and the top surface 26B (see FIG. 1) of the gate layer 26 in the Z-axis direction. The thickness TS of the sensor layer 44 can be defined by the distance between the bottom surface of the sensor layer 44 and the top surface of the sensor layer 44 in the Z-axis direction.

The thickness TS of the sensor layer 44 is equal to the thickness TG1 of the first gate extension portion 26D (both see FIG. 1). The thickness TS of the sensor layer 44 is equal to the thickness TG2 of the second gate extension 26E (see FIG. 1). Here, if the difference between the thickness TS of the sensor layer 44 and the thickness TG1 of the first gate extension part 26D is within 20% of the thickness TS of the sensor layer 44, the thickness TS of the sensor layer 44 is It can be said that the thickness is equal to the thickness TG1 of the first gate extension portion 26D. Further, if the difference between the thickness TS of the sensor layer 44 and the thickness TG2 of the second gate extension portion 26E is within 20% of the thickness TS of the sensor layer 44, the thickness TS of the sensor layer 44 is It can be said that the thickness is equal to the thickness TG2 of the two-gate extension portion 26E. The thickness TG1 of the first gate extension portion 26D refers to the thickness of the portion of the first gate extension portion 26D whose upper surface is a flat surface. The thickness TG2 of the second gate extension 26E refers to the thickness of the portion of the second gate extension 26E whose upper surface is a flat surface.

The width WS of the sensor layer 44 is equal to the width WG of the gate layer 26 (see FIG. 1). Here, if the difference between the width WS of the sensor layer 44 and the width WG of the gate layer 26 is within 10% of the width WS of the sensor layer 44, then the width WS of the sensor layer 44 is equal to the width WG of the gate layer 26. It can be said. In the example of FIG. 2, the width WS of the sensor layer 44 can be defined by the distance between both end surfaces of the sensor layer 44 in the X-axis direction in the X-axis direction. The width WG of the gate layer 26 can be defined by the distance in the X-axis direction between the tip surface of the first gate extension section 26D in the X-axis direction and the tip surface of the second gate extension section 26E in the X-axis direction. Thus, in this embodiment, the width WS of the sensor layer 44 is larger than the width of the gate ridge portion 26C of the gate layer 26.

The sensor layer 44 is at least partially covered by the passivation layer 22. Passivation layer 22 has an anode opening 22C and a cathode opening 22D. The anode opening 22C exposes a part of the upper surface of the sensor layer 44. That is, the anode opening 22C is formed at a position overlapping the sensor layer 44 in plan view. The cathode opening 22D is spaced apart from the anode opening 22C in the X-axis direction. The cathode opening 22D is spaced apart from the sensor layer 44 in the X-axis direction in plan view. The cathode opening 22D exposes a portion of the second nitride semiconductor layer 18.

The second PIN diode 42 includes an anode electrode 46 and a cathode electrode 48.
The anode electrode 46 is in contact with the upper surface of the sensor layer 44 through the anode opening 22C. In one example, anode electrode 46 is in ohmic contact with sensor layer 44 . The anode electrode 46 includes an anode contact portion 46A and an anode plate portion 46B continuous with the anode contact portion 46A. The anode contact portion 46A corresponds to a portion filled in the anode opening 22C. The anode plate portion 46B is formed integrally with the anode contact portion 46A. The anode plate portion 46B covers the passivation layer 22. The anode plate portion 46B includes a portion of the passivation layer 22 formed around the periphery of the anode opening 22C.

The cathode electrode 48 is in contact with the second nitride semiconductor layer 18 through the cathode opening 22D. In one example, cathode electrode 48 is in ohmic contact with second nitride semiconductor layer 18 . The cathode electrode 48 includes a cathode contact portion 48A and a cathode plate portion 48B continuous with the cathode contact portion 48A. The cathode contact portion 48A corresponds to a portion filled in the cathode opening 22D. The cathode plate portion 48B covers the passivation layer 22. The cathode plate portion 48B includes a portion of the passivation layer 22 formed around the periphery of the cathode opening 22D. Cathode plate section 48B is spaced apart from anode plate section 46B. That is, the anode electrode 46 and the cathode electrode 48 are spaced apart from each other.

The anode electrode 46 and the cathode electrode 48 are composed of one or more metal layers (eg, Ti, Al, AlCu, TiN, etc.). The anode electrode 46 and the cathode electrode 48 are formed of the same material as the source electrode 28 and the drain electrode 30, for example.

Although not shown, the nitride semiconductor device 10 can further include an anode wiring and a cathode wiring formed on the interlayer insulating layer. The interlayer insulating layer covers the anode electrode 46 and the cathode electrode 48.

The anode wiring and the cathode wiring are formed on the interlayer insulating layer so as to be separated from each other. The anode wiring is electrically connected to the anode electrode 46. The cathode wiring is electrically connected to the cathode electrode 48. Each of the anode wiring and the cathode wiring is composed of one or more metal layers. The metal layer may be made of a material containing, for example, any one of Cu, Al, Ti, and TiN. In one example, each of the anode wiring and the cathode wiring is formed of a laminated structure of Ti, TiN, AlCu, and TiN. The anode wiring and the cathode wiring may be formed of the same material as the source wiring, the drain wiring, and the gate wiring.

[Overall planar structure of nitride semiconductor device]
FIG. 3 shows a schematic planar structure of an exemplary formation pattern 100 of the nitride semiconductor device 10 of FIG. 1. In order to facilitate understanding, in FIG. 3, the same reference numerals are given to the same components as those in FIGS. 1 and 2. Also in FIG. 3, passivation layer 22 is depicted as being transparent so that gate layer 26 is visible. Further, in FIG. 3, a part of the source electrode 28 is drawn with a two-dot chain line. Furthermore, in FIG. 3, the gate electrode 32 and the anode electrode 46 are omitted for convenience.

As shown in FIG. 3, the formation pattern 100 includes an active region 102 that contributes to transistor operation and an outer peripheral region 104 surrounding the active region 102. It can also be said that the outer peripheral region 104 is a region that does not contribute to transistor operation.

The active region 102 is a region where a source electrode 28, a drain electrode 30, and a gate electrode 32 are arranged. Active region 102 includes a region where current flows between the source and drain when a voltage is applied to gate electrode 32. As shown in FIG. 3, within the active region 102, a source opening 22A and a drain opening 22B of the passivation layer 22 are arranged.

A plurality of source openings 22A are provided spaced apart from each other in the Y-axis direction. Although not shown, a plurality of source openings 22A are provided spaced apart from each other in the X-axis direction. A plurality of drain openings 22B of the passivation layer 22 are provided spaced apart from each other in the Y-axis direction. Further, although not shown, a plurality of drain openings 22B are provided spaced apart from each other in the X-axis direction. Each source opening 22A and each drain opening 22B extend along the Y-axis direction.

The gate layer 26 is arranged in the active region 102. Although not shown, a plurality of gate layers 26 are provided spaced apart from each other in the X-axis direction. Further, a plurality of gate layers 26 are provided spaced apart from each other in the Y-axis direction. The gate layer 26 is formed in a ring shape so as to surround the two source openings 22A arranged in the Y-axis direction in a plan view. More specifically, the gate layer 26 includes linear main gate portions 26F arranged on both sides of the source opening 22A in the X-axis direction, and end portions connecting these main gate portions 26F at both ends in the Y-axis direction. It includes a connecting portion 26G and an intermediate connecting portion 26H that connects these main gate portions 26F at an intermediate portion in the Y-axis direction.

The main gate portion 26F is arranged between the source opening 22A and the drain opening 22B that are adjacent to each other in the X-axis direction. More specifically, the main gate portion 26F is arranged closer to the source opening 22A than the drain opening 22B. The main gate portion 26F extends along the Y-axis direction.

The end connecting portion 26G is arranged on the opposite side from one of the two source openings 22A adjacent to each other in the Y-axis direction. The end connecting portion 26G is formed into a curved shape when viewed from above. The intermediate connecting portion 26H is arranged between two adjacent source openings 22A in the Y-axis direction. The intermediate connecting portion 26H extends in the X-axis direction. In this way, one source opening 22A is surrounded by two main gate portions 26F, one end connecting portion 26G, and intermediate connecting portion 26H that are spaced apart from each other in the X-axis direction.

Although not shown, the gate electrode 32 has the same shape as the gate layer 26 in plan view. That is, the gate electrode 32 is formed so as to surround two source openings 22A that are adjacent to each other in the Y-axis direction in plan view. In this way, in the active region 102, a plurality of structures of the transistor 11 shown in FIG. 1 are formed in each of the X-axis direction and the Y-axis direction.

As shown in FIG. 3, the temperature sensor 40 is provided in the outer peripheral region 104. In other words, the temperature sensor 40 is not provided in the active area 102. Temperature sensor 40 is placed apart from transistor 11 in the Y-axis direction.

The sensor layer 44 of the temperature sensor 40 is spaced apart from the gate layer 26 in the Y-axis direction. Although not shown, a plurality of sensor layers 44 are provided in the X-axis direction. Further, a plurality of sensor layers 44 may be provided in the Y-axis direction.

The sensor layer 44 is formed into a ring shape in plan view. More specifically, the sensor layer 44 includes two main sensor sections 44A that are spaced apart from each other in the X-axis direction, and an end connecting section 44B that connects both ends of these main sensor sections 44A in the Y-axis direction. ,including.

In plan view, the position of each main sensor section 44A in the X-axis direction is the same as the position of each main gate section 26F in the X-axis direction. Each main sensor section 44A extends along the Y-axis direction. The size (width dimension) of each main sensor section 44A in the X-axis direction corresponds to the width WS of the sensor layer 44. Further, the size (width dimension) of each main gate portion 26F in the X-axis direction corresponds to the width WG of the gate layer 26. Therefore, the size (width dimension) of each main sensor section 44A in the X-axis direction is equal to the size (width dimension) of each main gate section 26F in the X-axis direction. In the illustrated example, the length of each main sensor section 44A in the Y-axis direction is shorter than the length of the main gate section 26F in the Y-axis direction.

The end connecting portion 44B is formed into a curved shape in plan view. In the illustrated example, the shape of the end connecting portion 44B in plan view is the same as the shape of the end connecting portion 26G of the gate layer 26.

In the outer peripheral region 104, an anode opening 22C and a cathode opening 22D of the passivation layer 22 are arranged.
The anode opening 22C is provided at a position overlapping each main sensor section 44A in plan view. That is, in the illustrated example, two anode openings 22C are provided corresponding to the two main sensor sections 44A. Each anode opening 22C extends along the Y-axis direction.

Note that the shape of the anode opening 22C in plan view is not limited to the shape along the Y-axis direction, and can be arbitrarily changed. In one example, the shape of the anode opening 22C in plan view may be formed in a ring shape similar to the sensor layer 44.

The cathode opening 22D is arranged at a position shifted in the X-axis direction with respect to each main sensor section 44A in plan view. A plurality of cathode openings 22D are provided spaced apart from each other in the X-axis direction. The anode openings 22C and cathode openings 22D are alternately arranged one by one in the X-axis direction. One of the plurality of cathode openings 22D is arranged within a region surrounded by the sensor layer 44 in plan view. The cathode opening 22D located within the region surrounded by the sensor layer 44 is located at the same position as the source opening 22A in the X-axis direction. The cathode opening 22D is arranged at a different position from the drain opening 22B in the X-axis direction.

Although not shown in FIG. 3, the anode electrode 46 (see FIG. 2) has the same shape as the sensor layer 44 in plan view. That is, the anode electrode 46 is formed in a ring shape when viewed from above. In other words, the anode plate portion 46B (see FIG. 2) of the anode electrode 46 is formed into a ring shape in plan view.

The cathode electrode 48 extends along the Y-axis direction. In other words, the cathode plate portion 48B of the cathode electrode 48 extends along the Y-axis direction. In the illustrated example, the cathode electrode 48 is arranged at a different position from the drain electrode 30 in the X-axis direction.

[Planar structure of external electrode of nitride semiconductor unit]
FIG. 4 is a schematic plan view showing the appearance of the nitride semiconductor unit 10U.
As shown in FIG. 4, the nitride semiconductor unit 10U includes a nitride semiconductor device 10, a sealing resin 50 that seals the nitride semiconductor device 10, and a circuit board on which the nitride semiconductor device 10 is mounted. and an external electrode 52 for connection to. In addition, in FIG. 4, in order to facilitate understanding, the nitride semiconductor device 10 is shown by a solid line, and both the sealing resin 50 and the external electrode 52 are shown by a two-dot chain line.

The nitride semiconductor device 10 includes a device front surface 70 and a device back surface (not shown). The back surface of the device can be formed by a semiconductor substrate 12 (see FIG. 1). In other words, the back surface of the device can be formed by the surface of the semiconductor substrate 12 that is opposite to the buffer layer 14 (see FIG. 1). The device surface 70 is a surface facing away from the device back surface.

The nitride semiconductor device 10 includes an electrode pad 72 exposed from the device surface 70. Electrode pad 72 is electrically connected to external electrode 52. Electrode pad 72 includes a drain pad 74 , a source pad 76 , a gate pad 78 , and an anode pad 80 . In FIG. 4, in order to facilitate understanding of the drawing, the drain pad 74 is labeled "D", the source pad 76 is labeled "S(C)", the gate pad 78 is labeled "G", and the anode pad 80 is labeled "D". It is marked as "A".

The drain pad 74 is electrically connected to the drain electrode 30 (see FIG. 1) via a drain wiring. The source pad 76 is electrically connected to the source electrode 28 (see FIG. 1) via a source wiring. The source pad 76 is electrically connected to the cathode electrode 48 (see FIG. 2) via cathode wiring. In other words, the source pad 76 also constitutes a cathode pad. Gate pad 78 is electrically connected to gate electrode 32 (see FIG. 1) via gate wiring. Anode pad 80 is electrically connected to anode electrode 46 (see FIG. 2) via anode wiring.

A plurality of each of drain pads 74, source pads 76, gate pads 78, and anode pads 80 are provided. In the illustrated example, electrode pads 72 include three drain pads 74, two source pads 76, two gate pads 78, and two anode pads 80.

The three drain pads 74 and the two source pads 76 are alternately arranged one by one in the X-axis direction. The three drain pads 74 are distributed at both ends and the center of the device surface 70 in the X-axis direction. The length in the Y-axis direction of the drain pads 74 placed at both ends of the device surface 70 in the X-axis direction is longer than the length in the Y-axis direction of the drain pad 74 placed at the center of the device surface 70 in the X-axis direction. short. The length of each source pad 76 in the Y-axis direction is equal to the length of the drain pad 74 located at the center of the device surface 70 in the X-axis direction.

The two gate pads 78 are distributed and arranged at both ends of the device surface 70 in the X-axis direction. The two anode pads 80 are distributed and arranged at both ends of the device surface 70 in the X-axis direction. The gate pad 78 and the anode pad 80 are distributed and arranged on both sides of the drain pad 74 in the Y-axis direction, which are arranged at both ends of the device surface 70 in the X-axis direction. The gate pad 78, the anode pad 80, and the drain pad 74 are aligned with each other in the X-axis direction and spaced apart from each other in the Y-axis direction. Drain pad 74 is arranged between gate pad 78 and anode pad 80 in the Y-axis direction. Anode pad 80 is arranged at a position overlapping source pad 76 when viewed from the X-axis direction. In other words, the anode pad 80 is placed adjacent to the source pad 76 in the X-axis direction.

Note that the number and arrangement of the electrode pads 72 can be changed arbitrarily. In one example, electrode pad 72 may include a cathode pad separate from source pad 76. In this case, the cathode pad may be arranged, for example, adjacent to the anode pad 80 in the X-axis direction. Further, the shape of the electrode pad 72 can be changed arbitrarily.

The sealing resin 50 is made of an electrically insulating material. As the electrically insulating material, for example, black epoxy resin is used. Sealing resin 50 includes a surface 50A. In plan view, the sealing resin 50 has a rectangular shape with the X-axis direction being the longitudinal direction and the Y-axis direction being the lateral direction.

The external electrode 52 is exposed from the surface 50A of the sealing resin 50. The external electrode 52 constitutes an electrode pad for electrical connection with wiring on the circuit board side. External electrode 52 includes a drain external electrode 54 , a source external electrode 56 , a gate external electrode 58 , an anode external electrode 60 , and a cathode external electrode 62 .

The drain external electrode 54 is electrically connected to each drain pad 74 by a lead frame, a clip, or the like. Therefore, the drain external electrode 54 is electrically connected to the drain electrode 30 via each drain pad 74. The source external electrode 56 is electrically connected to each source pad 76 by a lead frame, a clip, or the like. Therefore, the source external electrode 56 is electrically connected to the source electrode 28 via each source pad 76. The gate external electrode 58 is electrically connected to each gate pad 78 by a lead frame, a clip, or the like. Therefore, the gate external electrode 58 is electrically connected to the gate electrode 32 via each gate pad 78. The anode external electrode 60 is electrically connected to each anode pad 80 by a lead frame, a clip, or the like. Therefore, the anode external electrode 60 is electrically connected to the anode electrode 46 via each anode pad 80. The cathode external electrode 62 is electrically connected to each source pad 76 by a lead frame, a clip, or the like. Therefore, the cathode external electrode 62 is electrically connected to the cathode electrode 48 via each source pad 76.

The drain external electrode 54 and the source external electrode 56 are aligned with each other in the X-axis direction and spaced apart from each other in the Y-axis direction. Each of the drain external electrode 54 and the source external electrode 56 has a rectangular shape with a longitudinal direction in the X-axis direction and a transverse direction in the Y-axis direction. The gate external electrode 58, the anode external electrode 60, and the cathode external electrode 62 are spaced apart from the drain external electrode 54 and the source external electrode 56 in the X-axis direction.

The gate external electrode 58, the anode external electrode 60, and the cathode external electrode 62 are arranged so as to be aligned with each other in the X-axis direction and spaced apart from each other in the Y-axis direction. The cathode external electrode 62 is arranged between the gate external electrode 58 and the anode external electrode 60 in the Y-axis direction. The cathode external electrode 62 is arranged closer to the anode external electrode 60 than the gate external electrode 58 . In the illustrated example, each of gate external electrode 58, anode external electrode 60, and cathode external electrode 62 is square. The area of each of the gate external electrode 58, the anode external electrode 60, and the cathode external electrode 62 is smaller than the area of each of the drain external electrode 54 and the source external electrode 56. In the illustrated example, the anode external electrode 60 and the cathode external electrode 62 are arranged at positions overlapping with the drain external electrode 54 when viewed from the X-axis direction. In the illustrated example, the gate external electrode 58 is placed at a position overlapping the source external electrode 56 when viewed from the X-axis direction. Note that the number and arrangement of the external electrodes 52 can be changed arbitrarily. Further, the shape of the external electrode 52 can be changed arbitrarily.

[Method for manufacturing nitride semiconductor device]
Next, an example of a method for manufacturing the nitride semiconductor device 10 shown in FIG. 1 will be described.
5 to 12 are schematic cross-sectional views showing exemplary manufacturing steps of the nitride semiconductor device 10. In order to facilitate understanding, in FIGS. 5 to 12, the same reference numerals are given to the same components as those in FIGS. 1 and 2. Further, in FIGS. 5 to 12, a part of the active region 102 and a part of the outer peripheral region 104 are shown side by side.

The method for manufacturing the nitride semiconductor device 10 includes forming a nitride semiconductor 13 with a drain electrode 30, a source electrode 28, a gate electrode 32, a Schottky diode 34 formed between the gate electrode 32 and the source electrode 28, and a Schottky diode 34 formed between the gate electrode 32 and the source electrode 28. 1PIN diode 36; The method for manufacturing the nitride semiconductor device 10 also includes forming a temperature sensor 40 including a second PIN diode 42 made of the nitride semiconductor 13 at a position different from the transistor 11 on the semiconductor substrate 12. In this embodiment, the process of forming the transistor 11 and the process of forming the temperature sensor 40 may include a common process.

As shown in FIG. 5, the method for manufacturing the nitride semiconductor device 10 includes forming a buffer layer 14, a first nitride semiconductor layer 16, a second nitride semiconductor layer 18, and a third nitride semiconductor layer on a semiconductor substrate 12, which is a Si substrate, for example. The method includes sequentially forming a nitride semiconductor layer 20 and a metal layer 800.

The buffer layer 14, the first nitride semiconductor layer 16, the second nitride semiconductor layer 18, and the third nitride semiconductor layer 20 are epitaxially grown using a metal organic chemical vapor deposition (MOCVD) method. can be done.

Although detailed illustrations are omitted, in one example, the buffer layer 14 is a multilayer buffer layer, and after an AlN layer (first buffer layer) is formed on the semiconductor substrate 12, a graded AlGaN layer (first buffer layer) is formed on the AlN layer. 2 buffer layer) is formed. The graded AlGaN layer is formed, for example, by stacking three AlGaN layers with Al compositions of 75%, 50%, and 25% in order from the side closest to the AlN layer.

A GaN layer is formed as the first nitride semiconductor layer 16 on the buffer layer 14 . That is, the first nitride semiconductor layer 16 is formed on the semiconductor substrate 12 with the buffer layer 14 interposed therebetween. Subsequently, an AlGaN layer is formed as a second nitride semiconductor layer 18 on the first nitride semiconductor layer 16 . Therefore, the second nitride semiconductor layer 18 has a larger band gap than the first nitride semiconductor layer 16.

Subsequently, a GaN layer containing acceptor type impurities is formed as the third nitride semiconductor layer 20 on the second nitride semiconductor layer 18 .
Since the buffer layer 14, the first nitride semiconductor layer 16, the second nitride semiconductor layer 18, and the third nitride semiconductor layer 20 are made of nitride semiconductors with relatively similar lattice constants, they can be continuously epitaxially grown. can be done.

As described above, the method for manufacturing the nitride semiconductor device 10 includes forming the nitride semiconductor 13 on the semiconductor substrate 12. More specifically, forming the nitride semiconductor 13 on the semiconductor substrate 12 means forming the first nitride semiconductor layer 16 on the semiconductor substrate 12, and forming the nitride semiconductor layer 13 on the semiconductor substrate 12 has a band gap smaller than that of the first nitride semiconductor layer 16. forming a large second nitride semiconductor layer 18 on the first nitride semiconductor layer 16; forming a third nitride semiconductor layer 20 containing acceptor type impurities on the second nitride semiconductor layer 18; including.

Subsequently, a metal layer 800 is formed on the third nitride semiconductor layer 20. In one example, metal layer 800 is a TiN layer formed by sputtering.
Each of the buffer layer 14, the first nitride semiconductor layer 16, the second nitride semiconductor layer 18, the third nitride semiconductor layer 20, and the metal layer 800 is formed over both the active region 102 and the outer peripheral region 104. There is.

FIG. 6 is a schematic cross-sectional view showing the manufacturing process following FIG. 5.
As shown in FIG. 6, the method for manufacturing nitride semiconductor device 10 includes forming a gate electrode 32. As shown in FIG. Gate electrode 32 is formed by selectively removing metal layer 800 by lithography and etching.

In one example, a first mask 802 is formed that covers a region of the metal layer 800 where the gate electrode 32 will be formed. The metal layer 800 is selectively removed using the first mask 802. As a result, the gate electrode 32 is formed.

FIG. 7 is a schematic sectional view showing a manufacturing process following FIG. 6, and FIG. 8 is a schematic sectional view showing a manufacturing process following FIG. 7.
As shown in FIGS. 7 and 8, the method for manufacturing nitride semiconductor device 10 includes forming a gate layer 26 and a sensor layer 44.

As shown in FIG. 7, the third nitride semiconductor layer 20 is patterned by lithography and etching to form a gate ridge portion 26C of the gate layer 26.
In one example, a second mask 804 is formed that covers the top and side surfaces of the gate electrode 32. Then, using this second mask 804, the third nitride semiconductor layer 20 is patterned by dry etching. As a result, the third nitride semiconductor layer 20 located under the second mask 804 remains even after etching, and the gate ridge portion 26C of the gate layer 26 is formed. The third nitride semiconductor layer 20 not covered by the second mask 804 is etched to a predetermined depth. At this time, the third nitride semiconductor layer 20 has a thickness that gradually decreases as the distance from the gate ridge part 26C increases in the region adjacent to the gate ridge part 26C, but in the region adjacent to the gate ridge part 26C, the thickness decreases as the distance from the gate ridge part 26C exceeds a predetermined distance. The region can be etched to have a substantially constant thickness.

The patterning process shown in FIG. 7 may include multiple etching steps to obtain the desired pattern as described above, or may include a slow etch rate in the vicinity of the structures covered by the second mask 804. It may include a single etching step with selected conditions. Further, after forming an SiN film on and on both sides of the gate electrode 32 using a SiN film that can be formed isotropically, the third nitride semiconductor layer 20 is selected using the hard mask. The structure shown in FIG. 7 can also be obtained by removing the structure.

As shown in FIG. 8, the third nitride semiconductor layer 20 is patterned by lithography and etching. As a result, the first gate extension part 26D, the second gate extension part 26E, and the sensor layer 44 are formed.

In one example, the gate electrode 32, the gate ridge portion 26C, a portion of the third nitride semiconductor layer 20 corresponding to the first gate extension portion 26D and the second gate extension portion 26E, and a portion of the third nitride semiconductor layer 20 corresponding to the sensor layer 44 are illustrated. A third mask 806 is formed to cover a portion of the third nitride semiconductor layer 20. The third nitride semiconductor layer 20 is then patterned by dry etching using the third mask 806. Through the above steps, the gate layer 26 and the sensor layer 44 are formed.

Due to the formation of the gate layer 26, there are A first PIN diode 36 is formed. By forming the sensor layer 44, the second PIN diode 42 is connected between the third nitride semiconductor layer 20 (sensor layer 44), the second nitride semiconductor layer 18, and the first nitride semiconductor layer 16 (2DEG24). It is formed. The first PIN diode 36 is formed in the active region 102, and the second PIN diode 42 is formed in the outer peripheral region 104. Further, the gate layer 26 forms a Schottky junction with the gate electrode 32. In other words, the gate electrode 32 and the gate layer 26 form a Schottky diode 34 (see FIG. 1).

The steps shown in FIGS. 7 and 8 are included in the step of forming the transistor 11 and the step of forming the temperature sensor 40. That is, forming the transistor 11 includes forming the gate layer 26 by etching the third nitride semiconductor layer 20. Forming the temperature sensor 40 includes forming the sensor layer 44 by etching a position of the third nitride semiconductor layer 20 that is different from the gate layer 26 . Then, as shown in FIGS. 7 and 8, the gate layer 26 and the sensor layer 44 are formed in a common process.

In addition, the steps shown in FIGS. 7 and 8 include forming the gate layer 26 by forming a gate ridge portion 26C where the gate electrode 32 is located, and forming the gate ridge portion 26C in the width direction (X-axis direction) of the gate ridge portion 26C. The method includes forming a first gate extension part 26D and a second gate extension part 26E extending from the gate ridge part 26C. As shown in FIGS. 7 and 8, the sensor layer 44, the first gate extension part 26D, and the second gate extension part 26E are formed in a common process.

FIG. 9 is a schematic sectional view showing a manufacturing process following FIG. 8, and FIG. 10 is a schematic sectional view showing a manufacturing process following FIG. 9.
As shown in FIGS. 9 and 10, the method for manufacturing nitride semiconductor device 10 includes forming a passivation layer 22. As shown in FIGS.

As shown in FIG. 9, a passivation layer 808 is formed to cover the entire exposed surfaces of the second nitride semiconductor layer 18, gate layer 26, gate electrode 32, and sensor layer 44. In one example, the passivation layer 808 is a SiN layer formed by a low-pressure chemical vapor deposition (LPCVD) method.

As shown in FIG. 10, passivation layer 808 is selectively removed by lithography and etching. More specifically, a fourth mask 810 is formed covering the passivation layer 808. The passivation layer 808 is selectively removed using the fourth mask 810. As a result, a source opening 22A, a drain opening 22B, an anode opening 22C, and a cathode opening 22D are formed in the passivation layer 808. Each of the source opening 22A, drain opening 22B, and cathode opening 22D exposes the second nitride semiconductor layer 18. The anode opening 22C exposes the sensor layer 44. Through the above steps, the passivation layer 22 is formed.

FIG. 11 is a schematic sectional view showing a manufacturing process following FIG. 10, and FIG. 12 is a schematic sectional view showing a manufacturing process following FIG. 11.
As shown in FIGS. 11 and 12, the method for manufacturing nitride semiconductor device 10 includes forming a source electrode 28, a drain electrode 30, an anode electrode 46, and a cathode electrode 48. The steps shown in FIGS. 11 and 12 are included in the step of forming the transistor 11 and the step of forming the temperature sensor 40.

As shown in FIG. 11, a metal layer 812 is formed which fills each of the source opening 22A, drain opening 22B, anode opening 22C, and cathode opening 22D and covers the entire exposed surface of the passivation layer 22. Ru. In one example, metal layer 812 is formed by a combination of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, an AlCu layer, and the like.

As shown in FIG. 12, metal layer 812 is selectively removed by lithography and etching. More specifically, a fifth mask 814 covering the metal layer 812 is formed. The metal layer 812 is selectively removed using the fifth mask 814. As a result, source electrode 28, drain electrode 30, anode electrode 46, and cathode electrode 48 are formed. The source electrode 28, the drain electrode 30, and the cathode electrode 48 are in contact with the second nitride semiconductor layer 18. The drain electrode 30 and the cathode electrode 48 are in ohmic contact with the second nitride semiconductor layer 18 . The source electrode 28, the drain electrode 30, and the cathode electrode 48 are electrically connected to the 2DEG 24. Anode electrode 46 is in contact with sensor layer 44 . Anode electrode 46 is in ohmic contact with sensor layer 44 . In this way, the nitride semiconductor device 10 shown in FIG. 1 can be manufactured.

As shown in FIGS. 11 and 12, forming the temperature sensor 40 includes forming an anode electrode 46 on the sensor layer 44 and forming a second nitride electrode 46 on the sensor layer 44 at a different position from the source electrode 28 and the drain electrode 30. The method includes forming a cathode electrode 48 in contact with the semiconductor layer 18 . Forming the transistor 11 includes forming a source electrode 28 and a drain electrode 30 electrically connected to the 2DEG 24 (see FIG. 1) generated in the first nitride semiconductor layer 16. Further, as shown in FIGS. 11 and 12, the source electrode 28, drain electrode 30, anode electrode 46, and cathode electrode 48 are formed in a common process.

[Effect]
The operation of the nitride semiconductor device 10 of this embodiment will be explained.
One possible method for detecting the temperature of a transistor, which is a GaNHEMT, is to detect the temperature of the transistor using a temperature sensor provided outside a chip on which the transistor is formed. However, with a temperature sensor outside the chip, it is not possible to improve the accuracy of transistor temperature detection.

Therefore, in this embodiment, the transistor 11 and the temperature sensor 40 are formed by the nitride semiconductor 13 formed on the semiconductor substrate 12, and the temperature sensor 40 is provided at a different position from the transistor 11 in the nitride semiconductor 13. There is. Specifically, the transistor 11 is provided in the active region 102 and the temperature sensor 40 is provided in the outer peripheral region 104. That is, both the transistor 11 and the temperature sensor 40 are formed in the same chip, in other words, in the nitride semiconductor 13 on the same semiconductor substrate 12. Thereby, the accuracy of temperature detection of the transistor 11 can be improved.

In addition, it is known that the transistor 11, which is a GaNHEMT, has a characteristic of low on-resistance. In other words, the chip area of the transistor 11 can be reduced. Therefore, when the temperature of the active region 102 increases, the temperature of the outer peripheral region 104 also increases. Thereby, even if the temperature of the outer peripheral region 104 is detected, the temperature of the transistor 11 can be detected with high accuracy. In other words, the temperature sensor 40 must be formed at a different location within the chip than the transistor 11, or in other words, at a location different from where the transistor 11 is formed in the nitride semiconductor 13 on the same semiconductor substrate 12. For example, the accuracy of temperature detection of the transistor 11 by the temperature sensor 40 can be improved.

Here, as a method of measuring the temperature of the transistor 11, for example, there may be a method of measuring the gate leakage current and estimating the temperature from the gate leakage current. However, if an attempt is made to increase the gate leakage current from the viewpoint of improving accuracy in measuring the temperature of the transistor 11, there is a concern that the reliability of the gate will deteriorate. Furthermore, in the transistor 11 of this embodiment, a Schottky junction is formed between the gate electrode 32 and the gate layer 26, so that the structure is such that gate leakage current does not easily flow. Therefore, in the nitride semiconductor device 10, it is difficult to detect the temperature of the transistor 11 based on the gate leakage current.

Therefore, in the nitride semiconductor device 10 of this embodiment, both the first PIN diode 36 of the transistor 11 and the second PIN diode 42 of the temperature sensor 40 are connected to the third nitride semiconductor layer 20, the second nitride semiconductor layer 18, and 1 nitride semiconductor layer 16. More specifically, both the first PIN diode 36 and the second PIN diode 42 are configured between the third nitride semiconductor layer 20, the second nitride semiconductor layer 18, and the 2DEG 24. In other words, the current flowing through the temperature sensor 40 corresponds to the gate leakage current of the transistor 11, and the two can be considered to be equivalent. By measuring the amount of current flowing through the temperature sensor 40, the temperature of the transistor 11 can be detected with high sensitivity.

[effect]
According to the nitride semiconductor device 10 of this embodiment, the following effects can be obtained.
(1-1) The nitride semiconductor device 10 includes a semiconductor substrate 12 and a nitride semiconductor 13 formed on the semiconductor substrate 12, and includes a drain electrode 30, a source electrode 28, a gate electrode 32, and a gate The transistor 11 including the Schottky diode 34 and the first PIN diode 36 formed between the electrode 32 and the source electrode 28 is provided at a different position from the transistor 11 on the semiconductor substrate 12, and is and a temperature sensor 40 including a second PIN diode 42 configured.

According to this configuration, since the transistor 11 and the temperature sensor 40 are formed on the common semiconductor substrate 12 and the nitride semiconductor 13, the temperature The accuracy of temperature detection of the transistor 11 by the sensor 40 can be improved.

(1-2) The nitride semiconductor 13 is formed on the first nitride semiconductor layer 16 formed on the semiconductor substrate 12 and on the first nitride semiconductor layer 16, and has a lower band than the first nitride semiconductor layer 16. The second nitride semiconductor layer 18 includes a second nitride semiconductor layer 18 having a large gap, and a third nitride semiconductor layer 20 that is formed on the second nitride semiconductor layer 18 and includes acceptor type impurities. Both the first PIN diode 36 and the second PIN diode 42 are configured between the third nitride semiconductor layer 20, the second nitride semiconductor layer 18, and the first nitride semiconductor layer 16 (2DEG 24).

According to this configuration, the first PIN diode 36 and the second PIN diode 42 are arranged between the third nitride semiconductor layer 20, the second nitride semiconductor layer 18, and the first nitride semiconductor layer 16 (2DEG 24). Since the current flowing through the temperature sensor 40 corresponds to the gate leakage current of the transistor 11, the two can be considered to be equivalent. Therefore, by using the second PIN diode 42 of the temperature sensor 40, it is possible to improve the accuracy of temperature detection of the transistor 11.

In addition, since both the first PIN diode 36 and the second PIN diode 42 are configured between the third nitride semiconductor layer 20, the second nitride semiconductor layer 18, and the first nitride semiconductor layer 16 (2DEG 24). , the first PIN diode 36 and the second PIN diode 42 can be formed in a common process. That is, the second PIN diode 42 can be formed without adding a dedicated process for forming the second PIN diode 42. Therefore, the manufacturing process of nitride semiconductor device 10 can be simplified.

(1-3) The transistor 11 includes an electron transit layer included in the first nitride semiconductor layer 16, an electron supply layer included in the second nitride semiconductor layer 18, and a gate included in the third nitride semiconductor layer 20. layer 26 and a source electrode 28 and a drain electrode 30 electrically connected to the two-dimensional electron gas (2DEG 24) generated in the electron transport layer. Gate electrode 32 is formed on gate layer 26.

According to this configuration, since the gate layer 26 is interposed between the gate electrode 32 and the second nitride semiconductor layer 18, the 2DEG 24 is depleted directly under the gate layer 26 when no current is supplied to the gate electrode 32. be converted into Therefore, a normally-off transistor 11 can be realized.

(1-4) The gate layer 26 forms a Schottky junction with the gate electrode 32.
According to this configuration, the gate threshold voltage of the transistor 11 can be improved compared to the case where the gate electrode 32 and the gate layer 26 are in ohmic contact. Therefore, since the gate breakdown voltage can be increased, the reliability of the gate can be improved.

(1-5) The gate layer 26 includes a gate ridge portion 26C where the gate electrode 32 is located, and a first gate extension portion as a gate extension portion extending from the gate ridge portion 26C in the width direction of the gate ridge portion 26C. 26D and a second gate extension 26E.

According to this configuration, when holes are injected from the gate electrode 32 into the gate layer 26 by applying a positive bias to the gate electrode 32, the injected holes are transferred to the first gate extension part 26D and the second gate extension part 26D. It is distributed in the gate extension part 26E. Therefore, the hole density at the interface between the gate layer 26 and the second nitride semiconductor layer 18 is reduced compared to the case where the

gate extensions

26D and 26E are not formed. Therefore, band bending of the second nitride semiconductor layer 18 due to hole accumulation is suppressed, so electron movement from the first nitride semiconductor layer 16 to the gate layer 26, that is, gate leakage current, can be reduced.

(1-6) Each of the first gate extension portion 26D and the second gate extension portion 26E has a thickness thinner than the gate ridge portion 26C. The thickness TS of the sensor layer 44 is equal to the thickness TG1 of the first gate extension part 26D and the thickness TG2 of the second gate extension part 26E.

According to this configuration, each

gate extension portion

26D, 26E and the sensor layer 44 can be formed in a common process. Therefore, the sensor layer 44 can be formed without adding a dedicated process for forming the sensor layer 44. Therefore, the manufacturing process of nitride semiconductor device 10 can be simplified.

(1-7) The anode electrode 46 is in ohmic contact with the sensor layer 44.
According to this configuration, current easily flows from the anode electrode 46 to the sensor layer 44. Therefore, the amount of change in current with respect to a change in temperature of nitride semiconductor 13 increases, so that the accuracy of temperature detection of nitride semiconductor 13 by temperature sensor 40 can be improved. Therefore, the accuracy of temperature detection of the transistor 11 by the temperature sensor 40 can be improved.

(1-8) The anode electrode 46 and the cathode electrode 48 are formed of the same material as the source electrode 28 and the drain electrode 30.
According to this configuration, the anode electrode 46, the cathode electrode 48, the source electrode 28, and the drain electrode 30 can be formed by a common process. Therefore, the manufacturing process of nitride semiconductor device 10 can be simplified.

(1-9) The nitride semiconductor 13 includes an active region 102 in which the transistor 11 is formed, and an outer peripheral region 104 surrounding the active region 102. The second PIN diode 42 is formed in the outer peripheral region 104.

According to this configuration, compared to a configuration in which the temperature sensor 40 is provided in the active region 102, reduction in the area in the active region 102 where the transistor 11 is formed can be suppressed.

<Second embodiment>
[Cross-sectional structure of nitride semiconductor device]
FIG. 13 is a schematic cross-sectional view of a portion of an exemplary nitride semiconductor device 10 according to the second embodiment. The nitride semiconductor device 10 of the second embodiment differs from the nitride semiconductor device 10 of the first embodiment mainly in the configuration of the temperature sensor 200. Below, the configuration of the temperature sensor 200 will be described in detail, and the same reference numerals will be given to the same components as in the first embodiment, and the description thereof will be omitted.

As shown in FIG. 13, the nitride semiconductor device 10 of this embodiment includes a temperature sensor 200 instead of the temperature sensor 40 of the first embodiment (see FIG. 2). Temperature sensor 200 includes a second PIN diode 202.

The second PIN diode 202 is located between the third nitride semiconductor layer 20, the second nitride semiconductor layer 18, and the first nitride semiconductor layer 16, similarly to the second PIN diode 42 of the first embodiment (see FIG. 2). It is made up of. More specifically, the second PIN diode 202 is configured between the third nitride semiconductor layer 20, the second nitride semiconductor layer 18, and the 2DEG 24. In this way, the third nitride semiconductor layer 20 includes the sensor layer 204 that constitutes the second PIN diode 202. The sensor layer 204 is provided separately from the gate layer 26, and is a GaN layer (p-type GaN layer) doped with acceptor type impurities like the gate layer 26. In one example, the impurity concentration of sensor layer 204 is equal to the impurity concentration of gate layer 26. Sensor layer 204 is spaced apart from gate layer 26. The second PIN diode 202 is configured between the sensor layer 204, the second nitride semiconductor layer 18, and the first nitride semiconductor layer 16. More specifically, the second PIN diode 202 is configured between the sensor layer 204, the second nitride semiconductor layer 18, and the 2DEG 24. In the second PIN diode 202, the sensor layer 204 is a p-type semiconductor, the 2DEG 24 is an n-type semiconductor, and the second nitride semiconductor layer 18 is an intrinsic semiconductor (I-type semiconductor).

The sensor layer 204 includes a bottom surface 204A in contact with the second nitride semiconductor layer 18 and a top surface 204B on the opposite side of the bottom surface 204A. The sensor layer 204 can have a rectangular, trapezoidal, or ridge-shaped cross section in the XZ plane in FIG. 13 .

In this embodiment, the sensor layer 204 includes a sensor ridge portion 204C having a trapezoidal cross section, and two sensor extension portions (a first sensor extension portion 204D and a second sensor extension part 204E). In addition, in the following description, the cathode opening 22D on the left side with respect to the sensor ridge portion 204C will be referred to as the “cathode opening portion 22DA”, and the cathode opening portion 22D on the right side with respect to the sensor ridge portion 204C will be referred to as the “cathode opening portion 22DB”. do.

The first sensor extension portion 204D extends from the sensor ridge portion 204C toward the cathode opening 22DA in plan view. The first sensor extension 204D is spaced apart from the cathode opening 22DA.

The second sensor extension portion 204E extends from the sensor ridge portion 204C toward the cathode opening 22DB in plan view. The second sensor extension 204E is spaced apart from the cathode opening 22DB.

The sensor ridge portion 204C is located between the first sensor extension portion 204D and the second sensor extension portion 204E, and is formed integrally with the first sensor extension portion 204D and the second sensor extension portion 204E. The first sensor extension portion 204D and the second sensor extension portion 204E are formed to sandwich the sensor ridge portion 204C in the width direction (X-axis direction in FIG. 13) of the sensor ridge portion 204C. The sensor ridge portion 204C includes an upper surface 204B. In other words, the upper surface 204B of the sensor layer 204 refers to the upper surface formed on the sensor ridge portion 204C.

Due to the presence of the first sensor extension part 204D and the second sensor extension part 204E, the bottom surface 204A of the sensor layer 204 has a larger area than the top surface 204B. In this embodiment, the length of the first sensor extension part 204D in the X-axis direction is equal to the length of the second sensor extension part 204E in the X-axis direction. Here, the difference between the length of the first sensor extension part 204D in the X-axis direction and the length of the second sensor extension part 204E in the X-axis direction is, for example, the length of the first sensor extension part 204D in the X-axis direction. If it is within 10%, it can be said that the length of the first sensor extension part 204D in the X-axis direction is equal to the length of the second sensor extension part 204E in the X-axis direction.

The sensor ridge portion 204C corresponds to a relatively thick portion of the sensor layer 204, and has a thickness of, for example, 80 nm or more and 150 nm or less. In one example, sensor layer 204 (sensor ridge portion 204C) has a thickness greater than 110 nm.

In one example, the thickness TSC of the sensor ridge portion 204C is equal to the thickness TGC of the gate ridge portion 26C of the gate layer 26 (see FIG. 1). Here, if the difference between the thickness TSC of the sensor ridge part 204C and the thickness TGC of the gate ridge part 26C is within 20% of the thickness TSC of the sensor ridge part 204C, then the thickness TSC of the sensor ridge part 204C is It can be said that it is equal to the thickness TGC of the gate ridge portion 26C.

Each of the first sensor extension part 204D and the second sensor extension part 204E has a thickness smaller than the thickness TSC of the sensor ridge part 204C. In one example, each of the first sensor extension part 204D and the second sensor extension part 204E has a thickness that is 1/2 or less of the thickness of the sensor ridge part 204C.

In this embodiment, each

sensor extension portion

204D, 204E is a flat portion having a substantially constant thickness. Alternatively, each

sensor extension portion

204D, 204E may include a tapered portion having a thickness that gradually decreases as the distance from the sensor ridge portion 204C increases in a region adjacent to the sensor ridge portion 204C. Each

sensor extension portion

204D, 204E may include a flat portion having a substantially constant thickness in a region beyond a predetermined distance from the sensor ridge portion 204C. In one example, the flat portion has a thickness of 5 nm or more and 25 nm or less.

In one example, the thicknesses TS1 and TS2 of each

sensor extension

204D and 204E are equal to the thickness TG1 and TG2 of each

gate extension

26D and 26E of the gate layer 26 (both shown in FIG. 1). Here, the difference between the thickness TS1, TS2 of each

sensor extension part

204D, 204E and the thickness TG1, TG2 of each

gate extension part

26D, 26E is, for example, the thickness TS1, TS1 of each

sensor extension part

204D, 204E. If it is within 20% of TS2, it can be said that the thicknesses TS1 and TS2 of each

sensor extension part

204D and 204E are equal to the thickness TG1 and TG2 of each

gate extension part

26D and 26E. The thickness TS1 of the first sensor extension portion 204D refers to the thickness of the portion of the first sensor extension portion 204D whose upper surface is a flat surface. The thickness TS2 of the second sensor extension portion 204E refers to the thickness of the portion of the second sensor extension portion 204E whose upper surface is a flat surface.

The width WS of the sensor layer 204 is equal to the width WG of the gate layer 26 (see FIG. 1). Here, the width WS of the sensor layer 204 can be defined by the distance in the X-axis direction between the tip surface of the first sensor extension section 204D and the tip surface of the second sensor extension section 204E in FIG. 13. Furthermore, if the difference between the width WS of the sensor layer 204 and the width WG of the gate layer 26 is within 10% of the width WS of the sensor layer 204, then the width WS of the sensor layer 204 is equal to the width WG of the gate layer 26. I can say that.

In the outer peripheral region 104, both the sensor layer 204 and the second nitride semiconductor layer 18 are covered with a passivation layer 22. In the example shown in FIG. 13, the thickness of the portion of the passivation layer 22 that covers each

sensor extension portion

204D, 204E is thicker than the thickness of the passivation layer 22 in the active region 102 in FIG. The passivation layer 22 has an anode opening 22C and a cathode opening 22D as in the first embodiment. The anode opening 22C exposes a part of the upper surface 204B of the sensor ridge 204C. That is, the anode opening 22C is formed at a position overlapping the sensor ridge 204C in plan view. The cathode opening 22D exposes a portion of the second nitride semiconductor layer 18.

The second PIN diode 202 includes an anode electrode 206 and a cathode electrode 208. The material constituting the anode electrode 206 and the cathode electrode 208 is the same as the material constituting the source electrode 28 and the drain electrode 30 (both shown in FIG. 1).

The anode electrode 206 is in contact with the upper surface 204B of the sensor ridge portion 204C through the anode opening 22C. In one example, the anode electrode 206 is in ohmic contact with the sensor ridge portion 204C. The anode electrode 206 includes an anode contact portion 206A and an anode plate portion 206B continuous with the anode contact portion 206A. The anode contact portion 206A corresponds to a portion filled in the anode opening 22C. The anode plate portion 206B is formed integrally with the anode contact portion 206A. Anode plate portion 206B covers passivation layer 22. The anode plate portion 206B includes a portion of the passivation layer 22 formed around the periphery of the anode opening 22C. The width WA of the anode plate portion 206B is larger than the width WSC of the upper surface 204B of the sensor ridge portion 204C. On the other hand, the width WA of the anode plate portion 206B is smaller than the width WS of the sensor layer 204.

The cathode electrode 208 is in contact with the second nitride semiconductor layer 18 through the cathode opening 22D. In one example, cathode electrode 208 is in ohmic contact with second nitride semiconductor layer 18 . The cathode electrode 208 includes a cathode contact portion 208A and a cathode plate portion 208B continuous with the cathode contact portion 208A. The cathode contact portion 208A corresponds to a portion filled in the cathode opening 22D. Cathode plate portion 208B covers passivation layer 22. The cathode plate portion 208B includes a portion of the passivation layer 22 formed around the periphery of the cathode opening 22D. Cathode plate section 208B is spaced apart from anode plate section 206B. That is, the anode electrode 206 and the cathode electrode 208 are spaced apart from each other.

The second PIN diode 202 includes a metal member 210 formed on the upper surface 204B of the sensor ridge portion 204C. Metal member 210 is formed to surround anode contact portion 206A. Metal member 210 is in contact with anode contact portion 206A. Metal member 210 is covered with passivation layer 22. The metal member 210 is made of a material containing TiN, for example. The metal member 210 may be formed of the same material as the gate electrode 32 (see FIG. 1).

Although not shown, the shape of the second PIN diode 202 in plan view is similar to the shape of the second PIN diode 42 of the first embodiment (see FIG. 2). The arrangement of the anode electrode 206 and the cathode electrode 208 is also the same as in the first embodiment.

[Method for manufacturing nitride semiconductor device]
Next, an example of a method for manufacturing the nitride semiconductor device 10 shown in FIG. 13 will be described.
14 to 21 are schematic cross-sectional views showing exemplary manufacturing steps of the nitride semiconductor device 10. In order to facilitate understanding, in FIGS. 14 to 21, the same reference numerals are given to the same components as those in FIG. 13. Further, in FIGS. 14 to 21, a part of the active region 102 and a part of the outer peripheral region 104 are shown side by side.

As shown in FIG. 14, the method for manufacturing the nitride semiconductor device 10 includes forming a buffer layer 14, a first nitride semiconductor layer 16, a second nitride semiconductor layer 18, a third The method includes sequentially forming a nitride semiconductor layer 20 and a metal layer 800. The methods for forming the buffer layer 14, first nitride semiconductor layer 16, second nitride semiconductor layer 18, third nitride semiconductor layer 20, and metal layer 800 are the same as in the first embodiment.

FIG. 15 is a schematic cross-sectional view showing the manufacturing process following FIG. 14.
As shown in FIG. 15, the method for manufacturing nitride semiconductor device 10 includes forming gate electrode 32 and sensor metal layer 820. Both gate electrode 32 and sensor metal layer 820 are formed by selectively removing metal layer 800 by lithography and etching. More specifically, a first mask 822 is formed that covers both the region where the gate electrode 32 is formed and the region where the sensor ridge portion 204C of the sensor layer 204 (see FIG. 13) is formed. Using this first mask 822, the metal layer 800 is selectively removed.

FIG. 16 is a schematic sectional view showing a manufacturing process following FIG. 15, and FIG. 17 is a schematic sectional view showing a manufacturing process following FIG. 16.
As shown in FIGS. 16 and 17, the method for manufacturing nitride semiconductor device 10 includes forming a gate layer 26 and a sensor layer 204.

As shown in FIG. 16, the third nitride semiconductor layer 20 is patterned by lithography and etching to form each of the gate ridge portion 26C of the gate layer 26 and the sensor ridge portion 204C of the sensor layer 204.

In one example, a second mask 824 is formed that covers the top and side surfaces of the gate electrode 32 and the top and side surfaces of the sensor metal layer 820. Then, using this second mask 824, the third nitride semiconductor layer 20 is patterned by dry etching. As a result, the third nitride semiconductor layer 20 located under the second mask 824 remains after etching, and the gate ridge portion 26C of the gate layer 26 and the sensor ridge portion 204C of the sensor layer 204 are formed, respectively. The third nitride semiconductor layer 20 not covered by the second mask 824 is etched to a predetermined depth. At this time, the third nitride semiconductor layer 20 has a thickness that gradually decreases as the distance from the gate ridge portion 26C increases in the region adjacent to the gate ridge portion 26C in the active region 102, but at a predetermined distance from the gate ridge portion 26C. Regions further apart can be etched to have a substantially constant thickness. Further, the third nitride semiconductor layer 20 has a thickness that gradually decreases as the distance from the sensor ridge portion 204C increases in a region adjacent to the sensor ridge portion 204C in the outer peripheral region 104, but beyond a predetermined distance from the sensor ridge portion 204C. The etching can be performed to have a substantially constant thickness in distant regions.

The patterning process shown in FIG. 16 may include multiple etching steps to obtain the desired pattern as described above, or may include a slow etch rate in the vicinity of the structures covered by the second mask 824. It may include a single etching step with selected conditions. Further, by using a SiN film that can be formed isotropically, a SiN film is formed on the top and both sides of the gate electrode 32 and on top and both sides of the sensor metal layer 820, and then the hard mask is formed. The structure shown in FIG. 16 can also be obtained by selectively removing the third nitride semiconductor layer 20 using .

As shown in FIG. 17, the third nitride semiconductor layer 20 is patterned by lithography and etching. Thereby, the first gate extension part 26D and the second gate extension part 26E, and the first sensor extension part 204D and the second sensor extension part 204E are formed.

In one example, the gate electrode 32, the gate ridge portion 26C, a portion of the third nitride semiconductor layer 20 corresponding to the first gate extension portion 26D and the second gate extension portion 26E, the sensor ridge portion 204C, and the A third mask 826 is formed to cover a portion of the third nitride semiconductor layer 20 corresponding to the first sensor extension portion 204D and the second sensor extension portion 204E. The third nitride semiconductor layer 20 is then patterned by dry etching using the third mask 826. Through the above steps, the gate layer 26 and the sensor layer 204 are formed.

As shown in FIGS. 16 and 17, forming the sensor layer 204 involves forming a sensor ridge portion 204C and extending from the sensor ridge portion 204C in the width direction (X-axis direction) of the sensor ridge portion 204C. forming a first sensor extension 204D and a second sensor extension 204E. As shown in FIG. 16, the sensor ridge portion 204C and the gate ridge portion 26C are formed in a common process. As shown in FIG. 17, the first sensor extension part 204D and the second sensor extension part 204E, and the first gate extension part 26D and the second gate extension part 26E are formed in a common process.

FIG. 18 is a schematic sectional view showing a manufacturing process following FIG. 17, and FIG. 19 is a schematic sectional view showing a manufacturing process following FIG. 18.
As shown in FIGS. 18 and 19, the method for manufacturing nitride semiconductor device 10 includes forming a passivation layer 22. As shown in FIGS. The method for forming the passivation layer 22 is the same as in the first embodiment. In the step of FIG. 18, a passivation layer 808 is formed. In the process of FIG. 19, a source opening 22A, a drain opening 22B, an anode opening 22C, and a cathode opening 22D are formed. As a result, a passivation layer 22 is formed. In this embodiment, in the step of FIG. 19, the passivation layer 808 and the sensor metal layer 820 are removed when the anode opening 22C is formed. As a result, a portion of the sensor metal layer 820 remains. The remaining sensor metal layer 820 constitutes the metal member 210. That is, the metal member 210 is exposed through the anode opening 22C.

FIG. 20 is a schematic sectional view showing a manufacturing process following FIG. 19, and FIG. 21 is a schematic sectional view showing a manufacturing process following FIG. 20.
As shown in FIGS. 20 and 21, the method for manufacturing nitride semiconductor device 10 includes forming a source electrode 28, a drain electrode 30, an anode electrode 206, and a cathode electrode 208. The method of forming the source electrode 28, drain electrode 30, anode electrode 206, and cathode electrode 208 is the same as in the first embodiment. In this way, the nitride semiconductor device 10 shown in FIG. 13 can be manufactured.

(effect)
According to this embodiment, in addition to (1-1) to (1-5) of the first embodiment, the following effects can be obtained.

(2-1) The sensor layer 204 includes a sensor ridge portion 204C where the anode electrode 206 is located, and a first sensor extension portion 204D extending from the sensor ridge portion 204C in the X-axis direction as the width direction of the sensor ridge portion 204C. and a second sensor extension part 204E. The thickness TSC of the sensor ridge portion 204C is equal to the thickness TGC of the gate ridge portion 26C.

According to this configuration, the sensor ridge portion 204C and the gate ridge portion 26C can be formed in a common process. Therefore, the manufacturing process of nitride semiconductor device 10 can be simplified.

(2-2) The thickness TS1 of the first sensor extension part 204D and the thickness TS2 of the second sensor extension part 204E are the same as the thickness TG1 of the first gate extension part 26D and the thickness TS2 of the second gate extension part 26E. It is equal to the thickness TG2.

According to this configuration, the first sensor extension part 204D, the second sensor extension part 204E, and the first gate extension part 26D and the second gate extension part 26E can be formed by a common process. Therefore, the manufacturing process of nitride semiconductor device 10 can be simplified.

(2-3) The anode electrode 206 is in ohmic contact with the sensor layer 204.
According to this configuration, current easily flows from the anode electrode 206 to the sensor layer 204. For this reason, the amount of change in current with respect to a change in temperature of nitride semiconductor 13 increases, so that the accuracy of temperature detection of nitride semiconductor 13 by temperature sensor 200 can be improved. Therefore, the accuracy of temperature detection of the transistor 11 by the temperature sensor 200 can be improved.

(2-4) The anode electrode 206 and the cathode electrode 208 are formed of the same material as the source electrode 28 and the drain electrode 30.
According to this configuration, the anode electrode 206, the cathode electrode 208, the source electrode 28, and the drain electrode 30 can be formed by a common process. Therefore, the manufacturing process of nitride semiconductor device 10 can be simplified.

(2-5) The nitride semiconductor 13 includes an active region 102 in which the transistor 11 is formed, and an outer peripheral region 104 surrounding the active region 102. The second PIN diode 202 is formed in the outer peripheral region 104.

According to this configuration, compared to a configuration in which the temperature sensor 200 is provided in the active region 102, the reduction in the area in the active region 102 where the transistor 11 is formed can be suppressed.

<Example of change>
Each of the above embodiments can be modified and implemented as follows. Moreover, each of the above embodiments and each of the following modified examples can be implemented in combination with each other within a technically consistent range.

- In each of the above embodiments, the temperature sensor 40 (200) is arranged in the outer peripheral region 104 at a position aligned with the active region 102 in the Y-axis direction, but the temperature sensor 40 (200) is not limited to this. The temperature sensor 40 (200) may be arranged in the outer peripheral region 104 at a position aligned with the active region 102 in the X-axis direction.

- In each of the above embodiments, the position of the sensor layer 44 (204) in the X-axis direction can be changed arbitrarily. In one example, the sensor layer 44 (204) may be placed at a position shifted from the gate layer 26 in the X-axis direction.

- In each of the above embodiments, the shape of the second PIN diode 42 (202) in plan view can be arbitrarily changed. In one example, as shown in FIG. 22, the shape of the sensor layer 44 and the anode electrode 46 (see FIG. 2) of the second PIN diode 42 in plan view is the same as the shape of the gate layer 26 and the gate electrode 32 (see FIG. 1). It may be.

The sensor layer 44 includes a pair of main sensor sections 44A separated from each other in the X-axis direction, an end connecting section 44BA that connects both ends of the pair of main sensor sections 44A in the Y-axis direction, and a pair of main sensor sections 44A. an intermediate connecting portion 44BB that connects the central portions of the Y-axis direction. In the illustrated example, the pair of main sensor portions 44A, end connecting portions 44BA, and intermediate connecting portions 44BB are integrally formed. The end connecting portion 44BA has the same configuration as the end connecting portion 44B (see FIG. 3) of the sensor layer 44 of the first embodiment.

The length of the main sensor section 44A of the sensor layer 44 in the Y-axis direction is the same as the length of the main gate section 26F of the gate layer 26 in the Y-axis direction. longer than the length of Here, in plan view, the cathode electrode 48 disposed within the area surrounded by the sensor layer 44 is referred to as a "cathode electrode 48P", and the cathode electrode 48 disposed outside the sensor layer 44 is referred to as a "cathode electrode 48Q". shall be. The cathode opening 22D provided with the cathode electrode 48P is referred to as a "cathode opening 22DA", and the cathode opening 22D provided with the cathode electrode 48Q is referred to as a "cathode opening 22DB".

The main sensor section 44A is arranged closer to the cathode electrode 48P than the cathode electrode 48Q. Therefore, the anode electrode 46 is arranged closer to the cathode electrode 48P than the cathode electrode 48Q.

In the example shown in FIG. 23, the sensor layer 44 includes a sensor ridge portion 44C and two sensor extension portions (a first sensor extension portion 44D and a second sensor extension portion) extending outside the sensor ridge portion 44C in plan view. part 44E).

The first sensor extension portion 44D extends from the sensor ridge portion 44C toward the cathode opening 22DA in plan view. The first sensor extension 44D is spaced apart from the cathode opening 22DA.

The second sensor extension portion 44E extends from the sensor ridge portion 44C toward the cathode opening 22DB in plan view. The second sensor extension 44E is spaced apart from the cathode opening 22DB.

The sensor ridge portion 44C is located between the first sensor extension portion 44D and the second sensor extension portion 44E, and is formed integrally with the first sensor extension portion 44D and the second sensor extension portion 44E. The first sensor extension portion 44D and the second sensor extension portion 44E are formed to sandwich the sensor ridge portion 44C in the width direction (X-axis direction) of the sensor ridge portion 44C.

Due to the presence of the first sensor extension 44D and the second sensor extension 44E, the bottom surface of the sensor layer 44 has a larger area than the top surface of the sensor layer 44.
In the illustrated example, the length of the second sensor extension 44E is longer than the length of the first sensor extension 44D. Here, the length of the second sensor extension part 44E can be defined by the length from the side surface of the sensor ridge part 44C closer to the second sensor extension part 44E to the tip surface of the second sensor extension part 44E. The length of the first sensor extension part 44D can be defined by the length from the side surface of the sensor ridge part 44C closer to the first sensor extension part 44D to the tip surface of the first sensor extension part 44D.

The sensor ridge portion 44C corresponds to a relatively thick portion of the sensor layer 44, and has a thickness of, for example, 80 nm or more and 150 nm or less. In one example, the sensor layer 44 (sensor ridge portion 44C) has a thickness greater than 110 nm. The thickness TSC of the sensor ridge portion 44C of the sensor layer 44 is equal to the thickness TGC of the gate ridge portion 26C of the gate layer 26 (see FIG. 1). Here, the difference between the thickness TSC of the sensor ridge portion 44C of the sensor layer 44 and the thickness TGC of the gate ridge portion 26C of the gate layer 26 is, for example, within 20% of the thickness TSC of the sensor ridge portion 44C of the sensor layer 44. If so, it can be said that the thickness TSC of the sensor ridge portion 44C of the sensor layer 44 is equal to the thickness TGC of the gate ridge portion 26C of the gate layer 26.

Each of the first sensor extension part 44D and the second sensor extension part 44E has a thickness smaller than the thickness of the sensor ridge part 44C. In one example, each of the first sensor extension part 44D and the second sensor extension part 44E has a thickness that is 1/2 or less of the thickness of the sensor ridge part 44C.

In the illustrated example, each

sensor extension

44D, 44E is a flat portion having a substantially constant thickness. Alternatively, each

sensor extension portion

44D, 44E may include a tapered portion having a thickness that gradually decreases as the distance from the sensor ridge portion 44C increases in a region adjacent to the sensor ridge portion 44C. Each

sensor extension portion

44D, 44E may include a flat portion having a substantially constant thickness in a region beyond a predetermined distance from the sensor ridge portion 44C. In one example, the flat portion has a thickness of 5 nm or more and 25 nm or less. In the illustrated example, the thickness TS1 of the first sensor extension 44D is equal to the thickness TG1 (see FIG. 1) of the first gate extension 26D. The thickness TS2 of the second sensor extension 44E is equal to the thickness TG2 (see FIG. 1) of the second gate extension 26E. Here, if the difference between the thickness TS1 of the first sensor extension part 44D and the thickness TG1 of the first gate extension part 26D is, for example, within 20% of the thickness TS1 of the first sensor extension part 44D, It can be said that the thickness TS1 of the first sensor extension part 44D is equal to the thickness TG1 of the first gate extension part 26D. Further, if the difference between the thickness TS2 of the second sensor extension part 44E and the thickness TG2 of the second gate extension part 26E is within 20% of the thickness TS2 of the second sensor extension part 44E, It can be said that the thickness TS2 of the two-sensor extension part 44E is equal to the thickness TG2 of the second gate extension part 26E.

According to the configurations shown in FIGS. 22 and 23, since the configuration of the sensor layer 44 and the configuration of the gate layer 26 are the same, the tendency of the current to change with respect to the temperature of the second PIN diode 42 is the same as that of the current with respect to the temperature of the first PIN diode 36. The change trend is similar to that of . Therefore, the temperature of the transistor 11 can be detected with high accuracy using the second PIN diode 42 of the temperature sensor 40.

In addition, there is no need to form a dedicated sensor layer 44 shape for forming the second PIN diode 42. That is, the gate layer 26 and the sensor layer 44 can be formed with a common shape. Therefore, the second PIN diode 42 and the transistor 11 can be easily formed.

- In FIG. 22, two anode openings 22C are arranged spaced apart from each other in the Y-axis direction, but the invention is not limited to this. For example, the two anode openings 22C in FIG. 22 may be configured as one anode opening 22C by communicating in the Y-axis direction. Furthermore, three or more anode openings 22C may be arranged spaced apart from each other in the Y-axis direction.

- In FIG. 22, two cathode electrodes 48Q are arranged spaced apart from each other in the Y-axis direction, but the invention is not limited to this. For example, the two cathode electrodes 48Q in FIG. 22 may be connected in the Y-axis direction to form one cathode electrode 48Q. Although not shown, the cathode electrode 48P may be similarly changed.

- In another example of the second PIN diode 42 (202), in plan view, the sensor layer 44 may have a linear shape extending in the Y-axis direction instead of a ring shape. That is, the end connecting portion 44B may be omitted from the sensor layer 44. In this case, the sensor layer 44 includes, for example, two main sensor sections 44A.

- In each of the above embodiments, the number of sensor layers 44 (204) can be changed arbitrarily. In one example, a plurality of sensor layers 44 (204) may be arranged apart from each other in the X-axis direction.

- In the first embodiment, the thickness TS of the sensor layer 44 can be changed arbitrarily. In one example, the thickness TS of the sensor layer 44 may be thicker than the thickness TG1 of the first gate extension 26D. The thickness TS of the sensor layer 44 may be thicker than the thickness TG2 of the second gate extension 26E. In this case, the thickness TS of the sensor layer 44 may be thinner than the thickness of the gate ridge portion 26C (thickness TG of the gate layer 26). In another example, the thickness TS of the sensor layer 44 may be equal to the thickness of the gate ridge portion 26C (thickness TG of the gate layer 26).

- In the first embodiment, the width WS of the sensor layer 44 can be changed arbitrarily. In one example, the width WS of the sensor layer 44 may be shorter than the width WG of the gate layer 26 or longer than the width WG of the gate layer 26.

- In the second embodiment, the thickness TSC of the sensor ridge portion 204C of the sensor layer 204 can be changed arbitrarily. In one example, the thickness TSC of the sensor ridge portion 204C may be thinner than the thickness of the gate ridge portion 26C of the gate layer 26 (thickness TG of the gate layer 26).

- In the second embodiment, each of the thickness TS1 of the first sensor extension part 204D and the thickness TS2 of the second sensor extension part 204E of the sensor layer 204 can be changed arbitrarily. In one example, the thickness TS1 of the first sensor extension 204D may be thicker than the thickness TG1 of the first gate extension 26D of the gate layer 26, or the thickness of the first gate extension 26D. It may be thinner than TG1. Further, the thickness TS1 of the first sensor extension part 204D may be thicker than the thickness TG2 of the second gate extension part 26E, or may be thinner than the thickness TG2 of the second gate extension part 26E. Good too.

In one example, the thickness TS2 of the second sensor extension 204E may be thicker than the thickness TG1 of the first gate extension 26D, or may be thicker than the thickness TG1 of the first gate extension 26D. It can be thin. Further, the thickness TS2 of the second sensor extension part 204E may be thicker than the thickness TG2 of the second gate extension part 26E, or may be thinner than the thickness TG2 of the second gate extension part 26E. Good too.

- In the second embodiment, the configuration of the sensor layer 204 can be changed arbitrarily. In one example, one of the first sensor extension part 204D and the second sensor extension part 204E may be omitted.
- In each of the above embodiments, the shape of the anode electrode 46 (206) in plan view can be arbitrarily changed. In one example, the anode electrode 46 may be formed in a region of the sensor layer 44 corresponding to the main sensor section 44A and may have a linear shape extending in the Y-axis direction. That is, the anode electrode 46 does not need to be formed on the end connecting portion 44B of the sensor layer 44.

- In each of the above embodiments, the anode electrode 46 (206) and the cathode electrode 48 (208) may be formed of a different material from the source electrode 28 and the drain electrode 30.

- In each of the above embodiments, the configuration of the gate layer 26 can be changed arbitrarily. In one example, at least one of the first gate extension part 26D and the second gate extension part 26E may be omitted from the gate layer 26.

- In each of the above embodiments, the impurity concentration of the sensor layer 44 (204) may be different from the impurity concentration of the gate layer 26. A map (table) of the correlation between the electrical characteristics of the temperature sensor 40 (200) and the temperature may be set in advance.

- In each of the above embodiments, the buffer layer 14 may be omitted from the nitride semiconductor 13.
As used herein, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B."
As used in this disclosure, the term "on" includes the meanings of "on" and "above" unless the context clearly dictates otherwise. Thus, the phrase "the first layer is formed on the second layer" refers to the fact that in some embodiments the first layer may be directly disposed on the second layer in contact with the second layer, but in other embodiments. It is contemplated that the first layer may be placed above the second layer without contacting the second layer. That is, the term "on" does not exclude structures in which other layers are formed between the first layer and the second layer. For example, in each of the above embodiments in which the second nitride semiconductor layer 18 is formed on the first nitride semiconductor layer 16, in order to stably form the 2DEG 24, the second nitride semiconductor layer 18 and the first nitride semiconductor It also includes a structure in which an intermediate layer is located between layer 16.

The Z-axis direction used in the present disclosure does not necessarily need to be a vertical direction, nor does it need to completely coincide with the vertical direction. Accordingly, various structures according to the present disclosure (e.g., the structure shown in FIG. 1) are different from each other in that "upper" and "lower" in the Z-axis direction described herein are "upper" and "lower" in the vertical direction. Not limited to one thing. For example, the X-axis direction may be a vertical direction, or the Y-axis direction may be a vertical direction.

<Additional notes>
The technical ideas that can be grasped from each of the above embodiments and modifications are described below. It should be noted that, for the purpose of assisting understanding rather than with the intention of limiting, the corresponding reference numerals in the embodiments for the configurations described in the supplementary notes are shown in parentheses. The symbols are shown as examples to aid understanding, and the components described with each symbol should not be limited to the components indicated by the symbols.

[Appendix A1]
a semiconductor substrate (12);
It is composed of a nitride semiconductor (13) formed on the semiconductor substrate (12), and includes a drain electrode (30), a source electrode (28), a gate electrode (32), and the gate electrode (32). a transistor (11) including a Schottky diode (34) and a first PIN diode (36) formed between the source electrode (28);
a temperature sensor (40) provided at a different position from the transistor (11) on the semiconductor substrate (12) and including a second PIN diode (42) made of the nitride semiconductor (13); Nitride semiconductor device (10).

[Appendix A2]
The nitride semiconductor (13) is
a first nitride semiconductor layer (16) formed on the semiconductor substrate (12);
a second nitride semiconductor layer (18) formed on the first nitride semiconductor layer (16) and having a larger band gap than the first nitride semiconductor layer (16);
a third nitride semiconductor layer (20) formed on the second nitride semiconductor layer (18) and containing acceptor type impurities;
Both the first PIN diode (36) and the second PIN diode (42) include the third nitride semiconductor layer (20), the second nitride semiconductor layer (18), and the first nitride semiconductor layer ( 16) The nitride semiconductor device according to appendix A1.

[Appendix A3]
The transistor (11) is
an electron transit layer included in the first nitride semiconductor layer (16);
an electron supply layer included in the second nitride semiconductor layer (18);
a gate layer (26) included in the third nitride semiconductor layer (20),
The source electrode (28) and the drain electrode (30) are electrically connected to the two-dimensional electron gas (24) generated in the electron transit layer (16),
The nitride semiconductor device according to Appendix A2, wherein the gate electrode (32) is formed on the gate layer (26).

[Appendix A4]
The nitride semiconductor device according to Appendix A3, wherein the gate layer (26) forms a Schottky junction with the gate electrode (32).

[Appendix A5]
The gate layer (26) is
a gate ridge portion (26C) where the gate electrode (32) is located;
A gate extension part (26D, 26E) extending from the gate ridge part (26C) in the width direction (X-axis direction) of the gate ridge part (26C), the nitride semiconductor according to appendix A3 or A4. Device.

[Appendix A6]
The nitride according to Appendix A5, wherein the gate extension portions (26D, 26E) are formed to sandwich the gate ridge portion (26C) in the width direction (X-axis direction) of the gate ridge portion (26C). Semiconductor equipment.

[Appendix A7]
The third nitride semiconductor layer (20) includes a sensor layer (44) constituting the second PIN diode (42),
The second PIN diode (42) has an anode electrode (46) and a cathode electrode (48),
The anode electrode (46) is formed on the sensor layer (44),
The cathode electrode (48) is formed so as to be in contact with the second nitride semiconductor layer (18),
The nitride semiconductor device according to appendix A5 or A6, wherein a thickness (TS) of the sensor layer (44) is thinner than a thickness (TGC) of the gate ridge portion (26C).

[Appendix A8]
The gate extension portion (26D, 26E) has a thickness (TG1, TG2) thinner than the gate ridge portion (26C),
The nitride semiconductor device according to appendix A7, wherein the thickness (TS) of the sensor layer (44) is equal to the thickness (TG1, TG2) of the gate extension portion (26D, 26E).

[Appendix A9]
The nitride semiconductor device according to appendix A7 or A8, wherein the anode electrode (46) and the cathode electrode (48) are formed of the same material as the source electrode (28) and the drain electrode (30).

[Appendix A10]
The nitride semiconductor device according to any one of appendices A7 to A9, wherein the anode electrode (46) is in ohmic contact with the sensor layer (44).

[Appendix A11]
The third nitride semiconductor layer (20) includes a sensor layer (44) constituting the second PIN diode (42),
The second PIN diode (42) has an anode electrode (46) and a cathode electrode (48),
The anode electrode (46) is formed on the sensor layer (44),
The nitride semiconductor device according to any one of appendices A2 to A10, wherein the cathode electrode (48) is formed so as to be in contact with the second nitride semiconductor layer (18).

[Appendix A12]
The sensor layer (204) includes:
a sensor ridge portion (204C) where the anode electrode (206) is located;
The nitride semiconductor device according to appendix A11, further comprising: a sensor extension part (204D, 204E) extending from the sensor ridge part (204C) in the width direction (X-axis direction) of the sensor ridge part (204C).

[Appendix A13]
The nitride according to appendix A12, wherein the sensor extension portion (204D, 204E) is formed to sandwich the sensor ridge portion (204C) in the width direction (X-axis direction) of the sensor ridge portion (204C). Semiconductor equipment.

[Appendix A14]
The third nitride semiconductor layer (20) includes a gate layer (26) forming a Schottky junction with the gate electrode (32),
The gate layer (26) is
a gate ridge portion (26C) where the gate electrode (32) is located;
a gate extension part (26D, 26E) extending from the gate ridge part (26C) in the width direction (X-axis direction) of the gate ridge part (26C),
The nitride semiconductor device according to appendix A12, wherein a thickness (TSC) of the sensor ridge portion (204C) is equal to a thickness (TGC) of the gate ridge portion (26C).

[Appendix A15]
The nitride semiconductor (13) is
an active region (102) that contributes to transistor operation;
an outer peripheral area (104) surrounding the active area (102);
The nitride semiconductor device according to any one of appendices A1 to A14, wherein the second PIN diode (42) is formed in the outer peripheral region (104).

[Appendix A16]
The nitride semiconductor device according to any one of Appendices A1 to A15, including a drain pad (74), a source pad (76), and a gate pad (78) formed on a device surface (70).

[Appendix A17]
an anode pad (80) formed on a device surface (70);
The nitride semiconductor device according to appendix A16, wherein the source pad (76) is electrically connected to both the source electrode (28) and the cathode electrode (48) of the temperature sensor (40).

[Appendix A18]
The transistor (11) includes a gate layer (26) included in the third nitride semiconductor layer (20),
The nitride semiconductor device according to any one of appendices A2 to A14, wherein the shape of the sensor layer (44) in plan view is the same as the shape of the gate layer (26) in plan view.

[Appendix A19]
A nitride semiconductor device (10) according to any one of Appendices A1 to A18,
a sealing resin (50) for sealing the nitride semiconductor device (10);
A nitride semiconductor unit (10U) comprising: an external electrode (52) provided on the surface (50A) of the sealing resin (50).

[Appendix B1]
forming a nitride semiconductor (13) on a semiconductor substrate (12);
A shot formed in the nitride semiconductor (13) with a drain electrode (30), a source electrode (28), and a gate electrode (32), and between the gate electrode (32) and the source electrode (28). forming a transistor (11) including a key diode (34) and a first PIN diode (36);
forming a temperature sensor (40) including a second PIN diode (42) made of the nitride semiconductor (13) at a position different from the transistor (11) on the semiconductor substrate (12); A method for manufacturing a nitride semiconductor device (10).

[Appendix B2]
Forming the nitride semiconductor (13) on the semiconductor substrate (12) includes:
forming a first nitride semiconductor layer (16) on the semiconductor substrate (12);
forming a second nitride semiconductor layer (18) having a larger band gap than the first nitride semiconductor layer (16) on the first nitride semiconductor layer (16);
forming a third nitride semiconductor layer (20) containing acceptor type impurities on the second nitride semiconductor layer (18),
Both the first PIN diode (36) and the second PIN diode (42) include the third nitride semiconductor layer (20), the second nitride semiconductor layer (18), and the first nitride semiconductor layer ( 16) The method for manufacturing a nitride semiconductor device according to Appendix B1.

[Appendix B3]
Forming the transistor (11) includes forming a gate layer (26) by etching the third nitride semiconductor layer (20),
Forming the temperature sensor (40) includes forming a sensor layer (44) by etching a position of the third nitride semiconductor layer (20) that is different from the gate layer (26). ,
The method for manufacturing a nitride semiconductor device according to Appendix B2, wherein the gate layer (26) and the sensor layer (44) are formed in a common process.

[Appendix B4]
Forming the transistor (11) includes:
forming a gate electrode (32) on the gate layer (26);
forming a source electrode (28) and a drain electrode (30) electrically connected to the two-dimensional electron gas (24) generated in the first nitride semiconductor layer (16),
The method for manufacturing a nitride semiconductor device according to Appendix B3, wherein the gate layer (26) forms a Schottky junction with the gate electrode (32).

[Appendix B5]
Forming the gate layer (26) includes:
forming a gate ridge portion (26C) on which the gate electrode (32) is located;
forming a gate extension part (26D, 26E) extending from the gate ridge part (26C) in the width direction (X-axis direction) of the gate ridge part (26C),
The method for manufacturing a nitride semiconductor device according to appendix B3 or B4, wherein the sensor layer (44) and the gate extension portion (26D, 26E) are formed in a common process.

[Appendix B6]
Forming the temperature sensor (40) comprises:
forming an anode electrode (46) on the sensor layer (44);
forming a cathode electrode (48) in contact with the second nitride semiconductor layer (18) at a position different from the source electrode (28) and the drain electrode (30),
The method for manufacturing a nitride semiconductor device according to any one of appendices B3 to B5, wherein the anode electrode (46) is in ohmic contact with the sensor layer (44).

[Appendix B7]
The method for manufacturing a nitride semiconductor device according to Appendix B6, wherein the anode electrode (46), the cathode electrode (48), the source electrode (28), and the drain electrode (30) are formed in a common process.

[Appendix B8]
Forming the sensor layer (204) comprises:
forming a sensor ridge portion (204C);
and forming a sensor extension part (204D, 204E) extending from the sensor ridge part (204C) in the width direction (X-axis direction) of the sensor ridge part (204C). A method for manufacturing a nitride semiconductor device.

[Appendix B9]
Forming the gate layer (26) includes:
forming a gate ridge portion (26C) on which the gate electrode (32) is located;
forming a gate extension part (26D, 26E) extending from the gate ridge part (26C) in the width direction (X-axis direction) of the gate ridge part (26C),
The method for manufacturing a nitride semiconductor device according to appendix B8, wherein the sensor ridge portion (204C) and the gate ridge portion (26C) are formed in a common process.

[Appendix B10]
The method for manufacturing a nitride semiconductor device according to appendix B9, wherein the sensor extension portion (204D, 204E) and the gate extension portion (26D, 26E) are formed in a common process.

[Appendix B11]
The nitride semiconductor (13) is
an active region (102) that contributes to transistor operation;
an outer peripheral area (104) surrounding the active area (102);
The method for manufacturing a nitride semiconductor device according to any one of appendices B1 to B10, wherein the second PIN diode (42) is formed in the outer peripheral region (104).

The above description is merely an example. Those skilled in the art will recognize that many more possible combinations and permutations are possible beyond those listed for the purpose of describing the techniques of the present disclosure. This disclosure is intended to cover all alternatives, variations, and modifications falling within the scope of this disclosure, including the claims.

10... Nitride semiconductor device 10U... Nitride semiconductor unit 11... Transistor 12... Semiconductor substrate 13... Nitride semiconductor 14... Buffer layer 16... First nitride semiconductor layer 18... Second nitride semiconductor layer 20... Third nitride Semiconductor layer 22... Passivation layer 22A... Source opening 22B... Drain opening 22C... Anode opening 22D, 22DA, 22DB... Cathode opening 24... 2DEG (two-dimensional electron gas)
26...Gate layer 26A...Bottom surface 26B...Top surface 26C...Gate ridge portion 26D...First gate extension portion 26E...Second gate extension portion 26F...Main gate portion 26G...End connection portion 26H...Intermediate connection portion 28...Source Electrode 28A...Source contact part 28B...Source field plate part 28C...End part 30...Drain electrode 30A...Drain contact part 30B...Drain plate part 32...Gate electrode 32A...Bottom surface 32B...Top surface 32C...Side surface 34...Schottky diode 36... First PIN diode 40...Temperature sensor 42...Second PIN diode 44...Sensor layer 44A...Main sensor section 44B, 44BA...End connecting section 44BB...Intermediate connecting section 44C...Sensor ridge section 44D...First sensor extension section 44E...th 2 sensor extension part 46... Anode electrode 46A... Anode contact part 46B...

Anode plate part

48, 48P, 48Q... Cathode electrode 48A... Cathode contact part 48B... Cathode plate part 50... Sealing resin 50A... Surface 52... External electrode 54 ...Drain external electrode 56...Source external electrode 58...Gate external electrode 60...Anode external electrode 62...Cathode external electrode 70...Device surface 72...Electrode pad 74...Drain pad 76...Source pad 78...Gate pad 80...Anode pad 100... Formation pattern 102...Active region 104...Outer peripheral area 200...Temperature sensor 202...2nd PIN diode 204...Sensor layer 204A...Bottom surface 204B...Top surface 204C...Sensor ridge portion 204D...First sensor extension portion 204E...Second sensor extension portion 206... Anode electrode 206A... Anode contact part 206B... Anode plate part 208... Cathode electrode 208A... Cathode contact part 208B... Cathode plate part 210... Metal member 800... Metal layer 802... First mask 804... Second mask 806... Third Mask 808... Passivation layer 810... Fourth mask 812... Metal layer 814... Fifth mask 820... Sensor metal layer 822... First mask 824... Second mask 826... Third mask TG... Thickness of gate layer TGC... Gate ridge TG1...Thickness of the first gate extension part TG2...Thickness of the second gate extension part TS...Thickness of the sensor layer TSC...Thickness of the sensor ridge part TS1...Thickness of the first sensor extension part Thickness TS2...Thickness of the second sensor extension part WG...Width of the gate layer WS...Width of the sensor layer WA...Width of the anode plate part WSC...Width of the sensor ridge part

Claims

a semiconductor substrate;
A Schottky diode and a first PIN diode formed of a nitride semiconductor formed on the semiconductor substrate, and formed between a drain electrode, a source electrode, and a gate electrode, and between the gate electrode and the source electrode. , a transistor including;
a temperature sensor including a second PIN diode provided at a different position from the transistor on the semiconductor substrate and made of the nitride semiconductor;
A nitride semiconductor device comprising:
The nitride semiconductor is
a first nitride semiconductor layer formed on the semiconductor substrate;
a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer;
a third nitride semiconductor layer formed on the second nitride semiconductor layer and containing acceptor type impurities;
including;
The first PIN diode and the second PIN diode are both configured between the third nitride semiconductor layer, the second nitride semiconductor layer, and the first nitride semiconductor layer. Nitride semiconductor device.
The transistor is
an electron transit layer included in the first nitride semiconductor layer;
an electron supply layer included in the second nitride semiconductor layer;
a gate layer included in the third nitride semiconductor layer;
including;
The source electrode and the drain electrode are electrically connected to a two-dimensional electron gas generated in the electron transit layer,
The nitride semiconductor device according to claim 2, wherein the gate electrode is formed on the gate layer.
The nitride semiconductor device according to claim 3, wherein the gate layer forms a Schottky junction with the gate electrode.
The gate layer is
a gate ridge portion where the gate electrode is located;
a gate extension portion extending from the gate ridge portion in the width direction of the gate ridge portion;
The nitride semiconductor device according to claim 3 or 4.
The nitride semiconductor device according to claim 5, wherein the gate extension portion is formed to sandwich the gate ridge portion in the width direction of the gate ridge portion.
The third nitride semiconductor layer includes a sensor layer constituting the second PIN diode,
The second PIN diode has an anode electrode and a cathode electrode,
the anode electrode is formed on the sensor layer,
The cathode electrode is formed in contact with the second nitride semiconductor layer,
The nitride semiconductor device according to claim 5 or 6, wherein the sensor layer has a thickness thinner than the gate ridge portion.
The gate extension part has a thickness thinner than the gate ridge part,
The nitride semiconductor device according to claim 7, wherein the thickness of the sensor layer is equal to the thickness of the gate extension.
The nitride semiconductor device according to claim 7 , wherein the anode electrode and the cathode electrode are formed of the same material as the source electrode and the drain electrode.
The nitride semiconductor device according to claim 7, wherein the anode electrode is in ohmic contact with the sensor layer.
The third nitride semiconductor layer includes a sensor layer constituting the second PIN diode,
The second PIN diode has an anode electrode and a cathode electrode,
the anode electrode is formed on the sensor layer,
The nitride semiconductor device according to any one of claims 2 to 10, wherein the cathode electrode is formed so as to be in contact with the second nitride semiconductor layer.
The sensor layer includes:
a sensor ridge portion where the anode electrode is located;
a sensor extension part extending from the sensor ridge part in the width direction of the sensor ridge part;
The nitride semiconductor device according to claim 11.
The nitride semiconductor device according to claim 12, wherein the sensor extension portion is formed to sandwich the sensor ridge portion in the width direction of the sensor ridge portion.
The third nitride semiconductor layer includes a gate layer forming a Schottky junction with the gate electrode,
The gate layer is
a gate ridge portion where the gate electrode is located;
a gate extension portion extending from the gate ridge portion in the width direction of the gate ridge portion;
including;
The nitride semiconductor device according to claim 12, wherein the thickness of the sensor ridge portion is equal to the thickness of the gate ridge portion.
The nitride semiconductor is
an active region that contributes to transistor operation;
an outer peripheral area surrounding the active area;
including;
The nitride semiconductor device according to claim 1, wherein the second PIN diode is formed in the outer peripheral region.