WO2023221457A1 - 一种用于pon olt系统的硅基光电子的收发集成芯片 - Google Patents

一种用于pon olt系统的硅基光电子的收发集成芯片 Download PDF

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Publication number
WO2023221457A1
WO2023221457A1 PCT/CN2022/135717 CN2022135717W WO2023221457A1 WO 2023221457 A1 WO2023221457 A1 WO 2023221457A1 CN 2022135717 W CN2022135717 W CN 2022135717W WO 2023221457 A1 WO2023221457 A1 WO 2023221457A1
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optical
silicon
channel
signal
electrical
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PCT/CN2022/135717
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English (en)
French (fr)
Inventor
魏志坚
许国威
郑波
过开甲
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深圳市迅特通信技术股份有限公司
江西迅特通信技术有限公司
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Publication of WO2023221457A1 publication Critical patent/WO2023221457A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12133—Functions
    • G02B2006/12142—Modulator
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12133—Functions
    • G02B2006/12147—Coupler
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12133—Functions
    • G02B2006/1215—Splitter

Definitions

  • the present disclosure relates to the field of optical communication technology, and in particular to a silicon-based optoelectronic transceiver integrated chip used in a PON (Passive Optical Network, Passive Optical Network) OLT (Optical Line Terminal, Optical Line Terminal) system.
  • PON Passive Optical Network, Passive Optical Network
  • OLT Optical Line Terminal, Optical Line Terminal
  • the existing technology discloses a central office equipment used in passive optical networks above 50G, which includes: a golden finger plugged into the system board, a continuous downlink transmission channel above 50G, and a burst uplink reception channel above 25G And single-fiber bidirectional BOSA (Bi-Directional Optical Sub-Assembly, bidirectional optical component).
  • BOSA Bi-Directional Optical Sub-Assembly, bidirectional optical component
  • the transmission channel includes DSP (Digital Signal Processor, digital signal processor/digital signal processing chip), PAM4 (Pulsed Amplitude Modulation Four-Level, fourth-order pulse amplitude modulation) drive unit, core packaging optical component BOX; two parts of the DSP receiving system board A 25G NRZ (Non Return to Zero) TX (Transmitting) signal is synthesized into a 50G PAM4 modulated signal; the PAM4 driver unit receives the PAM4 modulated signal to drive the external modulator in the core package optical component to generate The transmitted optical signal of 50G PAM4; the receiving channel includes: coaxial package TO (Transistor Outline, transistor shape), LA (Linear Amplifier, linear amplifier) and CDR (Clock Data Recovery, clock data recovery), and the coaxial package TO receives light The signal is converted into an electrical signal, which is current-limited and shaped through LA and CDR, and then input to the system board through the golden finger.
  • DSP Digital Signal Processor, digital signal processor/digital signal processing chip
  • the inventor found that the existing optical channel transmission and reception are implemented through coaxial package TO and core package optical components such as BOSA optical components, which occupy space and cost high, and cannot realize the miniaturization and multi-function of central office equipment. speed requirements.
  • this embodiment provides a silicon-based optoelectronic transceiver integrated chip, an optical engine, a central office module and a PON OLT system board for use in a PON OLT system.
  • the multi-rate central office module based on a silicon-based optoelectronic integrated chip provided in this embodiment effectively reduces the occupied volume and can adapt to multi-rate scenarios.
  • an embodiment provides a silicon-based optoelectronic transceiver integrated chip for a PON OLT system.
  • the transceiver integrated chip is located in the optical engine of the OLT and realizes an integrated transceiver chip.
  • the transceiver integrated chip is based on The single-channel, dual-channel or four-channel driving electrical signals generated by the OLT modulation drive component modulate the optical signal.
  • the modulated downlink optical signal undergoes gain processing by the optical engine and is emitted through the optical interface of the optical engine;
  • the transceiver integrated chip performs photoelectric conversion on the uplink optical signal received by the optical interface of the optical engine to send to the burst mode receiving amplification chipset of the OLT located in the external area of the optical engine for processing.
  • the driving electrical signal is a driving electrical signal
  • the modulated downlink optical signal is a downlink optical signal
  • the driving electrical signals are two independent driving electrical signals, then the transceiver integrated chip modulates the optical signal based on each driving electrical signal, and the modulated downlink optical signal is two downlink optical signals;
  • the driving electrical signals are four independent driving electrical signals, then the transceiver integrated chip modulates the optical signal based on each driving electrical signal, and the modulated downstream optical signals are four downstream optical signals;
  • the transceiver integrated chip performs photoelectric conversion on the uplink optical signal and outputs a converted electrical signal
  • the transceiver integrated chip performs photoelectric conversion on the two uplink optical signals respectively and outputs the converted two independent electrical signals
  • the transceiver integrated chip performs photoelectric conversion on the four uplink optical signals respectively and outputs the converted four independent electrical signals.
  • the transceiver integrated chip includes:
  • Silicon optical couplers silicon optical modulators, silicon optical multiplexers and demultiplexers, silicon optical PIN (Positive Intrinsic Negative, positive-insulation-negative) receivers;
  • the silicon optical coupler receives the laser signal as a downstream light source emitted by the laser component in the optical engine.
  • the downstream light source is transmitted through the optical path and enters the silicon optical modulator for modulation.
  • the driving electrical signal of the silicon optical modulator Modulate the downlink light source to obtain a modulated optical signal;
  • the modulated optical signal is transmitted to the silicon optical multiplexer and demultiplexer through the optical path and output to the optical engine, so that the optical engine performs gain processing and performs downlink transmission through the optical interface;
  • the uplink optical signal received through the optical interface is gain-amplified in the optical engine and then enters the silicon optical PIN receiver through the silicon optical multiplexer and demultiplexer for photoelectric conversion and output.
  • the transceiver integrated chip includes:
  • a silicon optical coupler a silicon optical splitter, two silicon optical modulators, two silicon optical multiplexers and demultiplexers, and two silicon optical PIN receivers;
  • Each silicon optical multiplexer and demultiplexer of this transceiver integrated chip needs to support the multiplexing and demultiplexing of two optical signals of different wavelengths for a single downlink and a single uplink;
  • the silicon optical coupler receives the laser signal as a downlink light source emitted by the laser component in the optical engine, and the downlink light source is split through a silicon-based optical splitter to form two downlink light sources;
  • Each downstream light source is transmitted through the optical path and enters its corresponding silicon optical modulator for modulation.
  • Each silicon optical modulator modulates the downstream light source based on a driving electrical signal to obtain a modulated optical signal;
  • the modulated two optical signals are respectively transmitted to respective silicon optical multiplexers and demultiplexers through optical paths to be output to the optical engine respectively, so that the two gain components of the optical engine perform gain processing on the two outputs respectively and pass through the optical
  • the interface performs downlink transmission of two optical signals
  • the two uplink optical signals received through the optical interface are gain amplified in the two gain components of the optical engine, enter the respective silicon optical multiplexer and demultiplexer for processing, and then are transmitted to the respective silicon optical PIN receivers through the optical path.
  • Photoelectric conversion, each silicon optical PIN receiver outputs a converted electrical signal.
  • the transceiver integrated chip includes:
  • Two silicon optical couplers two silicon optical modulators, one silicon optical multiplexer and demultiplexer, and two silicon optical PIN receivers;
  • Each silicon optical coupler receives the laser signal as the downstream light source emitted by the corresponding laser component in the optical engine.
  • the wavelengths of the laser signals corresponding to the two downstream light sources are different, and the distance between the two wavelengths is greater than 10nm.
  • the downstream light source is transmitted through the optical path Enter a corresponding silicon light modulator for modulation.
  • Each silicon light modulator modulates the downstream light source of the road based on a driving electrical signal;
  • the modulated two optical signals of different wavelengths are transmitted through the optical path to a silicon optical multiplexer and demultiplexer and then enter a gain component of the optical engine. After being gain amplified, they are coupled into the optical fiber through the SC optical interface to combine the two optical signals. Downstream transmission;
  • the two uplink optical signals of different wavelengths received through the optical interface are gain amplified in a gain component of the optical engine and then demultiplexed by a silicon optical multiplexer and demultiplexer to become two spatially separated uplink optical signals.
  • the upstream optical signal is transmitted through the optical path to the respective silicon optical PIN receiver for photoelectric conversion, and each silicon optical PIN receiver outputs a converted electrical signal.
  • the two upstream optical signal wavelengths in this implementation are also different from the two downstream optical signal wavelengths.
  • the transceiver integrated chip when the driving electrical signals are four-way driving electrical signals, the transceiver integrated chip includes:
  • Two silicon optical couplers two silicon optical splitters, four silicon optical modulators, two silicon optical multiplexers and demultiplexers, and four silicon optical PIN receivers;
  • the two silicon optical couplers respectively receive laser signals as downstream light sources emitted by the two laser components in the optical engine, and the two laser signals have different wavelengths.
  • the downstream light sources are split through a silicon-based optical splitter to form Four downward light sources, two of which have the same wavelength;
  • Each downstream light source is transmitted through the optical path and enters its corresponding silicon optical modulator for modulation.
  • Each silicon optical modulator modulates the downstream light source based on a driving electrical signal to obtain a modulated optical signal;
  • the four modulated optical signals are respectively transmitted to the silicon optical multiplexer and demultiplexer through optical paths, and the two optical signals of different wavelengths are one group.
  • a total of two groups are output to the optical engine through two silicon optical multiplexers and demultiplexers, so that The two gain components of the optical engine perform gain processing on the two sets of four optical signal outputs respectively and perform downlink transmission of the optical signals through the duplex LC optical interface;
  • the four uplink optical signals received through the optical interface are gain amplified in the two gain components of the optical engine respectively, enter the respective silicon optical multiplexer and demultiplexer for processing, and then are transmitted to the respective silicon optical PIN receivers through the optical path.
  • Photoelectric conversion, each silicon optical PIN receiver outputs a converted electrical signal.
  • the transceiver integrated chip when the driving electrical signals are four-way driving electrical signals, the transceiver integrated chip includes:
  • Each silicon optical coupler receives the laser signal as a downstream light source emitted by the corresponding laser component in the optical engine, and the four laser signals have different wavelengths.
  • the downstream light source enters a corresponding silicon optical modulator through optical path transmission. Modulation, each silicon optical modulator modulates the downstream light source of this path based on a driving electrical signal to obtain a modulated optical signal;
  • the modulated four optical signals are transmitted through the optical path to a silicon optical multiplexer and demultiplexer, and are spatially combined into an on-chip waveguide to output the four downlink optical signals to the optical engine, so that one gain component of the optical engine can output the four channels Perform gain processing and perform downlink transmission of four optical signals through the Simplex SC optical interface;
  • the four uplink optical signals received through the optical interface are gain amplified in a gain component of the optical engine and coupled into an on-chip waveguide on the silicon-based optoelectronic integrated chip, and are processed by a silicon optical multiplexer and demultiplexer. Different wavelengths enter the four on-chip waveguides and become four spatially separated uplink optical signals.
  • Each uplink optical signal is transmitted through the optical path to its respective silicon optical PIN receiver for photoelectric conversion.
  • Each silicon optical PIN receiver outputs one converted optical signal. electric signal.
  • the transceiver integrated chip also includes: a silicon optical waveguide and a silicon optical monitor corresponding to optical path transmission;
  • the silicon optical waveguide and silicon optical monitor are used to transmit and monitor the optical signal transmitted by the optical path.
  • an embodiment also provides an optical engine for a PON OLT system.
  • the optical engine is located in a system that adopts SFP-DD (Small Form-factor Pluggable-Double Density, double-density small pluggable) or SFP-DD112. (Small Form-factor Pluggable-Double Density 112G, single-channel 112G double-density small pluggable) packaged OLT module, and based on the single-channel, dual-channel or four-channel drive electrical signals generated by the modulation drive component in the OLT for the downstream The optical signal is modulated, and after gain processing, is emitted through the optical interface of the optical engine;
  • the uplink optical signal received by the optical interface of the optical engine is photoelectrically converted to be sent to the burst mode receiving amplification chipset of the OLT located in the external area of the optical engine for processing;
  • the optical engine is provided with the silicon-based optoelectronic transceiver integrated chip described in any one of the first aspects.
  • the optical interface of the optical engine is used to receive uplink optical signals or send downlink optical signals.
  • the optical interface includes: single-channel single-fiber bidirectional Simplex SC (Simplex, single Fiber bidirectional; SC, Standard Connector) interface and/or dual-channel single fiber bidirectional dual Simplex LC (Lucent Connector, Lucent Connector) interface; the optical interface is used for SFP-DD/SFP-DD112 packaging optical module.
  • the light engine includes:
  • Silicon-based optoelectronic transceiver integrated chips O-band lasers and driving components, O-band gain chips and driving components, optical interfaces, and golden finger arrays;
  • the O-band laser and driving component are used as laser components to generate laser signals as downlink light sources; the O-band gain chip and driving component are used to gain processing the optical signal output by the silicon-based optoelectronic transceiver integrated chip, or to perform gain processing on the optical signal received by the optical interface.
  • the uplink optical signal undergoes gain processing; the golden finger array is used to transmit electrical signals/driving electrical signals of the optical engine and other components in the OLT;
  • the driving electrical signal is a one-channel driving electrical signal
  • the driving electrical signal is a two-way driving electrical signal, there is one O-band laser and driving component, and two O-band gain chips and driving components;
  • the driving electrical signal is a two-way driving electrical signal
  • the driving electrical signal is a two-way driving electrical signal
  • the driving electrical signal is a four-way driving electrical signal
  • driving electrical signals are four-way driving electrical signals, there are four O-band lasers and driving components, and one O-band gain chip and driving component.
  • an embodiment further provides a multi-rate central office module based on a silicon-based optoelectronic integrated chip.
  • the central office module is a module packaged in SFP-DD/SFP-DD112.
  • the central office module includes: Electrical interface, analog/digital signal processing integrated components with single/dual/quad multi-rate combination, optical engine and burst mode receiving amplification chipset with single/dual/quad multi-rate combination;
  • the electrical interface is used to realize electrical signal transmission between the central office module and the system board;
  • the analog/digital signal processing integrated component is used to perform clock data recovery, rate and/or code type conversion processing on the downlink electrical signal with the first parameter transmitted by the system board through the electrical interface of the optical module, so as to obtain An electrical signal with a second parameter, which is used to apply the optical signal corresponding to the silicon-based optoelectronic integrated chip in the optical engine to achieve modulation of the optical signal, and pass the modulated downlink optical signal through the optical interface of the optical engine transmission network side,
  • the uplink optical signal received by the optical interface of the optical engine is converted into an electrical signal through the reception of the silicon-based optoelectronic integrated chip in the optical engine; the electrical signal is transmitted to the said electrical signal through the burst mode receiving amplification chipset and the electrical interface. system board;
  • the silicon-based optoelectronic integrated chip in the light engine is a transceiver integrated chip that integrates the transmission and reception of optical signals.
  • the silicon-based optoelectronic integrated chip in the light engine is the silicon-based optoelectronic transceiver integrated chip used in the PON OLT system as described in any of the above-mentioned first aspects.
  • the optical engine is the optical engine used in the PON OLT system described in any of the above second aspects.
  • the electrical interface includes: a gold finger array of an SFP-DD/SFP-DD112 packaged printed circuit board;
  • the burst mode receiving amplification chipset includes: a burst mode receiving transimpedance amplifier and a burst mode receiving linear amplifier;
  • the input and output burst mode electrical signals of the burst mode receiving and amplifying chipset are one channel, and the electrical signal rate of this burst mode receiving and amplifying chipset is equal to or is less than the rate of the electrical signal having the second parameter,
  • the burst mode receiving and amplifying chipset input and output burst mode electrical signals are two channels, and the two-channel burst mode receiving and amplifying chipset electrical signals are The rate is no higher than the rate of the electrical signal having the second parameter;
  • the burst mode receiving and amplifying chipset input and output burst mode electrical signals are four channels
  • the four-channel burst mode receiving and amplifying chipset electrical signals are The rate is no higher than the rate of the electrical signal having the second parameter.
  • the electrical interface is used to implement a 25/50/100/200G PON OLT system and/or a 25/50/100/200G EPON OLT (Ethernet Passive Optical Network OLT, Ethernet
  • the connection between the network standard passive optical network OLT) system and the central office module, and the electrical interface includes one or more of the following interfaces: single-channel high-speed electrical interface, dual-channel high-speed electrical interface and four-channel high-speed electrical interface .
  • the analog/digital signal processing integrated component includes: a digital processing chip DSP and a modulation driving component for silicon light optical signal modulation;
  • the DSP is used to perform clock data recovery, rate and/or code pattern mapping conversion on the single-channel or dual-channel electrical signal transmitted by the electrical interface according to the parameters of the optical transmission equipment, so as to obtain a signal that is consistent with the optical transmission equipment.
  • Digital processing chip DSP and modulation drive components for silicon light optical signal modulation Digital processing chip DSP and modulation drive components for silicon light optical signal modulation
  • the DSP is used to perform clock data recovery, rate and/or code pattern mapping conversion, etc. on the dual-channel electrical signals transmitted by the electrical interface according to the parameters of the optical transmission equipment, so as to obtain a signal that meets the transmission parameter requirements of the optical transmission equipment.
  • Dual-channel downlink electrical signals are used to modulate the drive components to obtain the dual-channel drive electrical signals, which are the second parameters;
  • Digital processing chip DSP and modulation drive components for silicon light optical signal modulation Digital processing chip DSP and modulation drive components for silicon light optical signal modulation
  • the DSP is used to perform clock data recovery, rate and/or code pattern mapping conversion and other processing on the four-way electrical signals transmitted by the electrical interface according to the parameters of the optical transmission equipment, so as to obtain a signal that meets the transmission parameter requirements of the optical transmission equipment.
  • a single-channel downlink electrical signal is used to modulate the drive component to obtain a single-channel drive electrical signal, which is the second parameter;
  • Digital processing chip DSP and modulation drive components for silicon light optical signal modulation Digital processing chip DSP and modulation drive components for silicon light optical signal modulation
  • the DSP is used to perform clock data recovery, rate and/or code pattern mapping conversion and other processing on the four-way electrical signals transmitted by the electrical interface according to the parameters of the optical transmission equipment, so as to obtain a signal that meets the transmission parameter requirements of the optical transmission equipment.
  • Dual-channel downlink electrical signals are used to modulate the drive components to obtain the dual-channel drive electrical signals, which are the second parameters;
  • Digital processing chip DSP and modulation drive components for silicon light optical signal modulation Digital processing chip DSP and modulation drive components for silicon light optical signal modulation
  • the DSP is used to perform clock data recovery, rate and/or code pattern mapping conversion and other processing on the four-way electrical signals transmitted by the electrical interface according to the parameters of the optical transmission equipment, so as to obtain a signal that meets the transmission parameter requirements of the optical transmission equipment.
  • Four channels of downlink electrical signals are used to modulate the drive components to obtain four channels of drive electrical signals, which are the second parameters;
  • Analog/digital signal processing integrated components include: dual-channel retimer components and modulation drive components for optical signal modulation;
  • the dual-channel retimer component is used to perform clock data recovery, rate and/or code pattern mapping conversion on the dual-channel electrical signals transmitted by the electrical interface according to the parameters of the optical transmission equipment, so as to obtain transmission parameters that meet the requirements of the optical transmission equipment.
  • the two downlink electrical signals are generated, and by modulating the drive components, the two drive electrical signals, which are the second parameters, are obtained;
  • Analog/digital signal processing integrated components include: four-way retimer components and modulation drive components for optical signal modulation;
  • the four-way retimer component is used to perform clock data recovery, rate and/or code pattern mapping conversion on the four-way electrical signals transmitted by the electrical interface according to the parameters of the optical transmission equipment, so as to obtain transmission parameters that meet the requirements of the optical transmission equipment.
  • the four-way downlink electrical signals are generated, and the four-way driving electrical signals are obtained by modulating the driving components.
  • the four-way rates can be consistent, such as 4x25Gbps, 4x50Gbps, or 4x100Gbps. Or, in other embodiments, they can also be consistent, such as a combination of 2x25Gbps+2x50Gbps. This embodiment is not correct. The limits are selected according to actual needs.
  • the DSP includes: a Retimer component, a Gearbox (gearbox) component, and a code conversion module;
  • the DSP gearbox Gearbox component When a single-channel 1x25Gbps or 1x50Gbps NRZ or 1x100Gbps PAM4 code is input, the DSP gearbox Gearbox component does not work.
  • the single-channel Retimer component will input a single-channel electrical signal for clock data recovery and output a single-channel 1x25Gbps NRZ or 1x50Gbps NRZ or 1x100Gbps PAM4 code. As a downward electrical signal;
  • the dual-channel input electrical signal 2x25Gbps NRZ mapping is converted into a single-channel 50Gbps NRZ code pattern through the Retimer component and the gearbox Gearbox component as an output downlink electrical signal;
  • the dual-channel input signal 2x25Gbps NRZ mapping is converted into a single-channel 50Gbps PAM4 code pattern through the Retimer component, the gearbox Gearbox component and the code pattern conversion module, as an output downlink electrical signal;
  • the dual-channel input signal 2x50Gbps NRZ mapping is converted into a single-channel 100Gbps NRZ code pattern through the Retimer component and the gearbox Gearbox component, which is used as an output downlink electrical signal;
  • the dual-channel input signal 2x50Gbps NRZ mapping is converted into a single-channel 100Gbps PAM4 code pattern through the Retimer component, the gearbox Gearbox component and the code conversion module, which is used as an output downlink electrical signal;
  • the dual-channel input signal 2x 100Gbps PAM4 is mapped and converted into a single-channel 1x200Gbps PAM4 code through the Retimer component and the gearbox Gearbox component, which is used as an output downlink electrical signal.
  • the dual-channel retimer component includes: a retimer chip
  • the retimer chip When the dual-channel 2x25Gbps NRZ code pattern is input, the retimer chip is used to recover the clock data of the dual-channel electrical signals received by the electrical interface, and map and convert them into dual-channel 25Gbps NRZ code pattern as the output dual-channel downlink electrical signal;
  • one channel is 25Gbps NRZ code type
  • the other channel is 50Gbps NRZ code type.
  • the retimer or DSP chip is used to recover the clock data of the two channels of electrical signals received by the electrical interface, and map and convert them into one channel.
  • 25Gbps NRZ, and the other channel is 50Gbps NRZ code type as the output dual-channel downlink electrical signal;
  • the retimer or DSP chip When the dual-channel 2x50Gbps NRZ code pattern is input, the retimer or DSP chip is used to recover the clock data of the dual-channel electrical signals received by the electrical interface, and map and convert them into dual-channel 2x50Gbps NRZ code pattern as the output dual-channel downlink power supply. Signal;
  • the retimer or DSP chip When the dual-channel 2x100Gbps PAM4 code is input, the retimer or DSP chip is used to recover the clock data of the dual-channel electrical signals received by the electrical interface, and map and convert them into the dual-channel 2x100Gbps PAM4 code, which is used as the output dual-channel downstream power. Signal.
  • the four-channel retimer or DSP components include: a retimer chip or DSP chip;
  • the retimer chip When four channels of 4x25Gbps NRZ code are input, the retimer chip is used to perform clock data recovery on each of the four channels of electrical signals received by the electrical interface, and map and convert them into four channels of 25Gbps NRZ code as the output of the four channels of downlink electrical signals;
  • the DSP chip When the four-channel 4x25Gbps NRZ code pattern is input, the DSP chip is used to perform clock data recovery on each of the four-channel electrical signals received by the electrical interface, and map and convert them into a single-channel 100Gbps PAM4 code pattern as the output single-channel downlink electrical signal;
  • the DSP chip When four channels of 4x25Gbps NRZ code are input, the DSP chip is used to perform clock data recovery on each of the four channels of electrical signals received by the electrical interface, and map and convert them into dual channels of 2x50Gbps NRZ or PAM4 code, which are used as output dual channels of downstream power. Signal;
  • the retimer or DSP chip When four channels of 4x50Gbps NRZ code are input, the retimer or DSP chip is used to recover the clock data of the four channels of electrical signals received by the electrical interface, and map and convert them into four channels of 4x50Gbps NRZ code, as the output of the four channels of downlink power. Signal;
  • the DSP chip When the four-channel 4x50Gbps NRZ code pattern is input, the DSP chip is used to perform clock data recovery on each of the four-channel electrical signals received by the electrical interface, and map and convert them into a single-channel 200Gbps PAM4 code pattern as the output single-channel downlink electrical signal;
  • the DSP chip When the four-channel 4x50Gbps NRZ code pattern is input, the DSP chip is used to perform clock data recovery on each of the four-channel electrical signals received by the electrical interface, and map and convert them into a dual-channel 2x100Gbps PAM4 code pattern as the output dual-channel downlink electrical signal;
  • the retimer or DSP chip When using 2x25Gbps and 2x50Gbps four-way combined input, the retimer or DSP chip is used to recover the clock data of the four-way electrical signals received by the electrical interface, and map and convert them into four-way 2x25Gbps and 2x50Gbps NRZ code patterns as the output four-way Electric signal down the road.
  • the modulation driving component is a silicon light modulation driving component, integrated in a DSP, or integrated with a retimer chip on one component.
  • an embodiment also provides a passive optical network PON OLT system, which is characterized in that it includes: a multi-rate central office module based on a silicon-based optoelectronic integrated chip according to any one of the above third aspects; The system interacts with the PON network side through the central office module.
  • the optical interface in the central office module OLT of each embodiment is consistent with the four optical interface types defined by the existing SFP-DD/SFP-DD112MSA protocol (Duplex LC (Duplex Lucent Connector, dual-fiber bidirectional Lucent interface), MPO-12 (Multi Fiber Push On 12, 12-channel multi-core connector), MDC (Mini Duplex Connector, micro dual-fiber two-way connector), SN (SN Connector: SN connector)) are different.
  • Duplex LC Duplex Lucent Connector, dual-fiber bidirectional Lucent interface
  • MPO-12 Multi Fiber Push On 12, 12-channel multi-core connector
  • MDC Mini Duplex Connector, micro dual-fiber two-way connector
  • SN SN Connector: SN connector
  • SFP- The DD/SFP-DD112 encapsulation protocol encapsulates the Simplex SC optical interface in the OLT, so that the Simplex SC optical interface supports single-channel single-fiber bidirectional (BiDi) transmission of optical signals in the PON; independent dual-channel Simplex can also be used in each embodiment
  • the LC optical interface further doubles the port density of the PON OLT system board and achieves higher-density single-fiber bidirectional transmission characteristics.
  • the current high-speed and compact SFP-DD/SFP-DD112 packaging protocol is applied to the electrical interface of system board interaction to support the high port density and system high performance of the next generation PON OLT system. need.
  • the PON OLT system in each embodiment helps operators realize that the central office module increases the access network downlink rate from the current 10Gbps of XG(S)PON to higher bandwidths such as 25Gbps, 50Gbps, 100Gbps, etc.; the uplink rate increases from 10Gbps to 25G or 50Gbps.
  • the application of the central office module of each embodiment in the PON OLT system can achieve higher board throughput.
  • the XG(S)PON OLT system can support 16 10Gbps PON OLT SFP+ optical transceivers (ie, central office module/central office equipment).
  • the number of optical transceivers inserted in the PON OLT system remains unchanged, and the total throughput of the system board in the PON OLT system is ( Throughput) is increased to 2.5 to 20 times that of the XG(S)PON board.
  • one SFP-DD/SFP-DD112 board is equivalent to 32 SFP-DD/SFP-DD11225G/50G/100GPON optical transceivers, and the total throughput of the system board is further doubled. 5 ⁇ 20x the maximum throughput of the XG(S)PON board.
  • one SFP-DD/SFP-DD112 board can plug in 16 SFP-DD/SFP-DD112100G/200G TWDM PON optical transceivers or the equivalent of 32 SFP-DD/SFP-DD112 50G /25G Combo PON optical transceiver.
  • the central office module of each embodiment can flexibly configure the rate of the downlink optical signal, be compatible with more customer needs, and be compatible with different standards.
  • the PON OLT system of each embodiment supports operators based on their own customer business needs, FTTx (Fiber to the Anything, fiber to any location) cost demands, PONMAC ASIC (Application Specific Integrated Circuit, application specific integrated circuit) rate and SERDES (Serializer/Deserializer) : serializer-deserializer) rate, flexible configuration of downlink optical signal rate and related services. For example, more than ten input and output signal rate combinations can be supported; the OLT/optical transceiver/central office module of each embodiment is compatible with the different rate requirements and plans of next-generation PONs of domestic operators and overseas operators, domestic equipment manufacturers The structure is in line with the different speed requirements of foreign equipment manufacturers and the implementation of next-generation PON technology standards promoted by multiple international standards organizations.
  • the central office module of each embodiment is open and scalable for future applications. Specifically, the Ethernet rate-based SFP-DD/SFP-DD112MSA (Multi Source Agreement) adds support for single-channel 100G PAM4 input and output.
  • PON MAC Media Access Control, media access control layer
  • SerDes is upgraded to 100Gbps rate in the future
  • the central office module of each embodiment can be smoothly expanded to support TDM (Time Division Multiplexing, time division multiplexing) or TWDM (Time and WavelengthDivision) Multiplexing, time division and wavelength division multiplexing) 200G(E)PON, 100G/50G or 50G/25G Combo PON (combined passive optical network).
  • TDM Time Division Multiplexing, time division multiplexing
  • TWDM Time and WavelengthDivision
  • the central office module in each embodiment applies an optical engine based on a silicon-based optoelectronic integrated chip to the PON network optical connection for the first time.
  • the optical engine in the central office module of each embodiment uses an integrated silicon-based optoelectronic integrated transceiver chip (SiP: Silicon Photonics) instead of the traditional optoelectronic hybrid integrated BOSA package, which can effectively avoid the problems caused by using dozens of discrete high-speed optoelectronic chips for hybrid integrated packaging.
  • process complexity improve product yield, reduce costs, reduce the total power consumption of optical transceivers, and improve product reliability; it also has the characteristics of high performance, high integration, high reliability, and is suitable for miniaturized packaging, making it suitable for higher-end applications in the future. Higher performance port density PON OLT system.
  • the silicon-based optoelectronic integrated chip used in the central office module in each embodiment is implemented by an integrated transceiver chip.
  • the receiving end uses a low-cost and high-performance GeSi PIN receiver.
  • APD Avalanche Photo Diode (avalanche photodiode) receiver
  • PIN receiver has low cost, high yield, and is fully compatible with the silicon-based MZ modulator process of the silicon photonics process at the transmitting end.
  • the existing mature silicon photonics process production line can be used to achieve transceiver in one taping.
  • Integrated integrated chips; the production and manufacturing of key silicon photonic integrated chips can be completed without upgrading the processing and manufacturing equipment and precision of the existing silicon photonics industry.
  • the O-band gain chip integrated with SiP simultaneously amplifies the high-power optical signal on the transmitting side and the low-power optical signal on the receiving side of the central office module (i.e., optical transceiver); for GeSi PIN itself, the receiving sensitivity is not as good as APD has high receiving sensitivity and the PON uplink signal may have attenuated to a level lower than the sensitivity of the PIN receiver after long-distance transmission.
  • the central office module of each embodiment uses an integrated O-band gain chip (Gain Chip) to amplify the received signal to meet the requirements of silicon germanium PIN.
  • the receiver has its own sensitivity requirements and compensates for the high dispersion cost caused by fiber transmission of optical signals of different wavelengths at different ultra-high speeds. That is, using the PIN+Gain Chip integration method to replace the traditional APD and applying it to the next generation PON optical network is a comprehensive consideration of multiple factors such as meeting technical standards, optimizing the cost of the optical transceiver optical engine, and being compatible with the existing mature silicon photonics process. result.
  • the OLT central office equipment used in the passive optical network PON in each embodiment supports the miniaturized SFP-DD/SFP-DD112 package, effectively supporting the high-density and high-performance port requirements of the next-generation OLT system equipment.
  • the existing configuration of 16 pluggable optical transceiver ports on one PON board can be maintained, the board port density remains unchanged, and the board throughput is increased to 2.5 ⁇ that of today's 10GPON boards. 20x.
  • the double-row gold finger distribution of the SFP-DD/SFP-DD112 electrical interface in each embodiment can be downwardly compatible with the single-row gold fingers of SFP28/SFP56/SFP112, and its gold finger array can also be flexibly redefined to make it compatible with both Group Combo PON to achieve multi-rate channel compatibility.
  • Figures 1 to 3 are respectively schematic diagrams of a silicon-based optoelectronic transceiver integrated chip in an embodiment
  • Figures 4 to 6 are respectively schematic diagrams of a light engine in another embodiment
  • Figure 7 is a schematic diagram of the optical interface type defined by SFP-DD/SFP-DD112MSA in the prior art
  • Figure 8 is a schematic diagram of a single-channel Simplex SC optical interface and a dual-channel SimplexLC interface used in another embodiment
  • FIGS 9 to 11 are schematic diagrams of the functional architecture of the central office module in another embodiment.
  • Figures 12 to 14 are schematic architectural diagrams of the PON OLT system used in the central office module
  • Figures 15 and 16 are respectively schematic diagrams of a silicon-based optoelectronic transceiver integrated chip and the associated optical engine in another embodiment.
  • O-band gain chip 10. SimplexSC optical interface or Simplex LC optical interface
  • burst mode transimpedance amplifier/BM-TIA15 burst mode linear amplifier/BM-LA
  • 21a, 21b, 21c, 21d On-chip waveguide 22, high-power semiconductor laser driver
  • microlens 26 gold finger array.
  • the current global access network is in the transition stage from GPON to 10G(S)PON, which is also a critical time for the development and selection of next-generation PON technology.
  • the next generation PON technology has a rate of 50G and 100G high-speed PON.
  • 25Gbps and 50Gbps used by various standard protocol organizations.
  • 25G(S)PON MSA and ITU-T 50GPON follow the history of ITU-T (International Telecommunication Union Telecommunication Standardization Sector, International Telecommunication Union Telecommunication Standardization Sector) Traditionally, its 25Gbps and 50Gbps are actually 24.8832Gbps and 49.7664Gbps, using NRZ encoding.
  • the IEEE standard 25Gbps and 50Gbps are actually 25.78125Gbps and 2x25.78125Gbps NRZ encoding, following the Ethernet speed tradition.
  • the above-mentioned subtle differences represent different standards organizations' judgments on the future direction of the industrial chain and different positions in leading the industrial chain through standards. They also cause differentiation in the industrial chain.
  • the PMA (Physical Media Attachment, physical media adaptation layer) and PMD (Physical Media Dependent, physical media dependency layer) layers already have a mature and complete optoelectronic chip industry chain supporting the Ethernet standard 25.78125Gbps NRZ.
  • the basic units for realizing the IEEE25G/50G-EPON physical layer are complete, and the technical span is not large.
  • the current difficulties are focused on application requirements and the realization of miniaturization and low cost.
  • the power consumption is packaged to support the two pairs of 25G different wavelength transceiver chipsets required by 50G-EPON. Since the SerDes rate of the Ethernet industry chain in the post-25G era has been 56G PAM4 (28G Baud) and 112G PAM4 (56G Baud) using PAM4 code, the optical port signal rate is 53.125Gbps (also referred to as 50Gbps) and 50Gbps using PAM4 code.
  • SFP Small Form-factor Pluggable
  • SFP+ are typical packaging methods used in optical transceivers. This packaging method allows one OLT board to accommodate 16 optical transceivers. device.
  • the current high-density and high-performance OLT system frame can insert 17 or more such boards.
  • the industry has yet to reach a consensus on which optical transceiver package to use in the next generation of higher-performance, higher-density OLT systems.
  • the fastest growing sector in optical communication network technology and applications has been the Hyper Scale Data Center.
  • SFP-based SFP-DD/SFP-DD112MSA protocol defines four optical fiber interface types (Duplex LC ( Figure 7(a)) shown), MPO-12 (shown in Figure 7(b)), MDC (shown in Figure 7(d)), SN (shown in Figure 7(c)).
  • the SFP-DD/SFP-DD112 optical transceiver can flexibly support single (1x) or dual (2x) electrical port 25G NRZ, 56G PAM4 (28GBaud), 112G PAM4 (56GBaud) and other SerDes rates and optical port 1x25Gbps to 2x100Gbps Ethernet rate.
  • Each embodiment involves an optical communication network that adopts next-generation passive optical network technology.
  • the optical transceiver in each embodiment that is, the central office module, adopts SFP-DD/SFP-DD112 package and silicon-based optoelectronic transceiver integrated chip Silicon Photonics (SiP ) and digital signal processing chip DSP (or retimer), the optical interface adopts a single-channel Simplex SC interface (as shown in (a) in Figure 8) or a dual-channel Simplex LC interface (as shown in (b) in Figure 8) , realizes downlink 25G/50G/100G/200Gbps NRZ or PAM4 signals, uplink burst mode 25G/50G/100Gbps NRZ or PAM4 signals, and supports the next generation of high-performance and high-density 25G(S)PON Multi Source Agreement (MSA: multi-source agreement) , ITU-T 9804.3 50GPON, IEEE 802.3ca (2020) 50G-EPON and other standard protocols,
  • the SFP-DD/SFP-DD112 electrical interface of each embodiment can adopt a single-channel high-speed electrical signal transceiver, can adopt a dual-channel high-speed electrical signal transceiver, and can also learn from the electrical interface golden finger method defined by SFP+Combo PON to redefine SFP -DD/SFP-DD112 double row gold fingers to support a total of four high-speed electrical signal transceivers.
  • the four-channel high-speed signal can use the same rate and each channel of optical signal has a different wavelength to realize the 100G/200G TWDM (Time and Wavelength Division Multiplexing, Time and Wavelength Division Multiplexing) PON of the Simplex SC optical interface.
  • the downlink refers to transmitting TX
  • the uplink refers to receiving RX.
  • the interfaces used to transmit optical signals are all optical interfaces.
  • the central office module in each embodiment is an OLT, an OLT transceiver, etc.
  • single channel refers to one optical signal or electrical signal
  • dual channel refers to two optical signals or electrical signals
  • four channel refers to four optical signals. or electrical signals
  • single channel means that the optical interface of the light engine is an optical fiber interface, which can send and receive at least two optical signals of different wavelengths at the same time
  • dual channel means that the optical interface of the light engine is two optical fiber interfaces, and each interface can send and receive at least two optical signals of different wavelengths at the same time. optical signals of different wavelengths.
  • This embodiment provides a silicon-based optoelectronic transceiver integrated chip for a PON OLT system.
  • the transceiver integrated chip is located in the optical engine of the OLT and implements an integrated transceiver chip.
  • the transceiver integrated chip is based on a single-channel front-end of the OLT. , dual-channel or four-channel driving electrical signals modulate the optical signal, and the modulated downlink optical signal is transmitted through the optical interface of the optical engine after gain processing by the optical engine;
  • the transceiver integrated chip performs photoelectric conversion on the uplink optical signal received by the optical interface of the optical engine to send to the burst mode receiving amplification chipset of the OLT located in the external area of the optical engine for processing.
  • the silicon-based optoelectronic transceiver integrated chip in this embodiment can be a transceiver integrated chip that is made by a one-time tape-out process and includes a silicon optical coupler, a silicon optical modulator, a silicon optical multiplexer and a silicon optical PIN receiver.
  • the chip also corresponds to silicon optical waveguides, silicon optical monitors and other components in actual optical path transmission. For details, please refer to Figures 1 to 3, Figure 15, and Figure 16.
  • the driving electrical signal received by the transceiver integrated chip is a driving electrical signal
  • the modulated downstream optical signal is a downstream optical signal
  • the drive electrical signals received by the transceiver integrated chip are two independent drive electrical signals, and the transceiver integrated chip modulates the optical signal based on each drive electrical signal, and the modulated downstream optical signal is two downstream optical signals;
  • the transceiver integrated chip performs photoelectric conversion on the uplink optical signal and outputs a converted electrical signal
  • the transceiver integrated chip performs photoelectric conversion on the two uplink optical signals respectively and outputs the converted two independent electrical signals.
  • the driving electrical signals are four independent driving electrical signals
  • the transceiver integrated chip modulates the optical signal based on each driving electrical signal, and the modulated downstream optical signals are four downstream optical signals; accordingly, the optical interface If the received uplink optical signals are four uplink optical signals, the transceiver integrated chip performs photoelectric conversion on the four uplink optical signals respectively and outputs the converted four independent electrical signals.
  • the silicon-based optoelectronic transceiver integrated chip A1 of this embodiment may include: a silicon optical coupler 7, a silicon optical modulator 5, a silicon optical multiplexer and demultiplexer 8, and a silicon optical PIN receiver 11;
  • the silicon optical coupler 7 receives the laser signal as the downlink light source emitted by the laser component in the optical engine A2.
  • the downlink light source enters the silicon optical modulator 5 for modulation through optical path transmission.
  • the driving electrical signal of the silicon light modulator 5 modulates the downstream light source to obtain a modulated optical signal;
  • the modulated optical signal is transmitted to the silicon optical multiplexer and demultiplexer 8 through the optical path to be output to the optical engine A2, so that the optical engine performs gain processing and performs downlink transmission through the optical interface;
  • the uplink optical signals received through the optical interface are gain amplified in the optical engine A2 and then enter the silicon optical PIN receiver 11 through the silicon optical multiplexer and demultiplexer 8 for photoelectric conversion and output.
  • the silicon-based optoelectronic transceiver integrated chip shown in Figure 1 can realize the modulation processing of a driving electrical signal, and is also the basic component unit of the core innovation in this embodiment.
  • there are also silicon light monitors that is, silicon light chip on-chip light monitors such as 20a, 20b, and 20c. This monitor has the same function as the existing light transmission monitor.
  • it is integrated Optical transmission is realized on the transceiver integrated chip.
  • the silicon optical waveguides namely on-chip waveguides 21a, 21b, 21c and 21d, also have the same functions as existing optical waveguides. In this embodiment, they are integrated on a transceiver integrated chip to achieve optical transmission.
  • the silicon-based optoelectronic transceiver integrated chip A1 of this embodiment may include: a silicon optical coupler 7, a silicon-based optical splitter 24, and two silicon optical modulators. 5. Two silicon optical multiplexers and demultiplexers 8. Two silicon optical PIN receivers 11;
  • the silicon optical coupler 7 receives the laser signal as the downstream light source emitted by the laser component in the optical engine A2.
  • the downstream light source is split through the silicon-based optical splitter 24 to form two downstream channels. light source;
  • Each downstream light source is transmitted through an optical path and enters its corresponding silicon optical modulator 5 for modulation.
  • Each silicon optical modulator 5 modulates the downstream light source based on a driving electrical signal to obtain a modulated optical signal; this
  • Figure 2 shows a laser component that generates a laser signal as the downlink light source, which is divided into two optical signals through a silicon-based 1:2 optical splitter.
  • the modulated two optical signals are respectively transmitted to respective silicon optical multiplexers and demultiplexers 8 via optical paths to be output to the optical engine A2 respectively, so that the two gain components of the optical engine A2 perform gain processing on the two outputs respectively and process them.
  • the optical interface performs downlink transmission of two optical signals.
  • the two uplink optical signals received through the optical interface are gain amplified in the two gain components of the optical engine respectively, enter the respective silicon optical multiplexers and demultiplexers for processing, and then are transmitted to the respective silicon optical multiplexers and demultiplexers via optical paths.
  • the PIN receiver performs photoelectric conversion, and each silicon photonic PIN receiver outputs a converted electrical signal.
  • the silicon-based optoelectronic transceiver integrated chip in Figure 2 can be used in various devices that adopt time division multiplexing mode ITU-T 50GPON, future 100GPON, and 25G(S)PON MSA protocol using ITU-T PON rate. And through the silicon optical splitter, two independent optical channels based on Figure 1 are realized, helping the optical engine to achieve dual-channel single-fiber bidirectional transmission.
  • the silicon-based optoelectronic transceiver integrated chip includes: two silicon optical couplers 7, two silicon optical modulators 5, one silicon optical multiplexer and demultiplexer 8, two Silicon Photonic PIN Receiver 11;
  • each silicon optical coupler 7 receives the laser signal as the downstream light source emitted by the corresponding laser component in the optical engine A2. At this time, the wavelengths of the laser signals corresponding to each channel are different.
  • the two laser components can emit laser signals of two wavelengths such as ⁇ DS0 and ⁇ DS1 .
  • Each downstream light source enters a corresponding silicon optical modulator 5 for modulation through optical path transmission.
  • Each silicon optical modulator 5 modulates the downstream light source of this path based on a driving electrical signal to obtain a modulated optical signal;
  • the modulated two optical signals are transmitted to a silicon optical multiplexer and demultiplexer 8 through the optical path.
  • the two downlink optical signals are output to the optical engine A2 through a port of the silicon optical multiplexer and demultiplexer 8, so that the optical engine A2 A gain component performs gain processing on two outputs and performs downlink transmission of two optical signals through the optical interface.
  • the two uplink optical signals received through the optical interface (the optical signals may be optical signals with different wavelengths, such as uplink ⁇ US0 and uplink ⁇ US1 ) are gained by a gain component of the optical engine. Amplified, and then processed by the silicon optical multiplexer and demultiplexer 8, it becomes two spatially separated uplink optical signals. Each uplink optical signal is transmitted through the optical path to its respective silicon optical PIN receiver for photoelectric conversion. Each silicon optical PIN receiver Output a converted electrical signal.
  • IEEE 50G-EPON 2x25Gbps signal rate and NRZ encoding uses O-band dual downlink wavelengths and dual uplink wavelengths to achieve 2x25Gbps total 50Gbps transceiver transmission, involving a total of four wavelength signals: 1342 ⁇ 2nm, 1358 ⁇ 2nm, 1270 ⁇ 10nm, 1300 ⁇ 10nm.
  • These four wavelengths can be amplified by an O-band gain chip, making the optical engine design simpler.
  • the wavelength of the uplink optical signal and the wavelength of the downlink optical signal are different, so they are shown by lines with different depths in FIG. 3 .
  • any optical path transmission is also provided with silicon optical waveguides for optical path transmission (such as on-chip waveguides 21a, 21b, 21c, 21d, etc. shown in each figure), silicon Light monitors (light monitoring on silicon photonic chips such as 20a, 20b, 20c, 20d, etc. shown in each figure).
  • the silicon optical waveguide and silicon optical monitor in this embodiment are used to transmit and monitor the optical signal transmitted by the optical path.
  • Optical monitoring on silicon photonic wafer monitors the optical signals of each device node on the chip.
  • Waveguide on silicon photonic wafer used to achieve high-speed optical signal transmission on silicon-based optoelectronic integrated chips.
  • the silicon-based optoelectronic integrated chip used in the central office module in this embodiment is implemented by an integrated transceiver chip.
  • the receiving end uses a low-cost and high-performance silicon germanium PIN receiver. Compared with traditional PON that uses an APD receiver, the PIN receiver It has low machine cost, high yield, and is fully compatible with the silicon-based MZ modulator process of the silicon photonics process at the transmitter.
  • the existing mature silicon photonics process production line can be used to realize the integrated transceiver integrated chip in one taping; there is no need to upgrade the existing silicon photonics. Industrial processing and manufacturing equipment and precision can complete the production and manufacturing of key silicon photonic integrated chips.
  • this embodiment also provides a transceiver integrated chip for four-way driving electrical signals, as shown in the structure in a large rectangular frame in Figure 15.
  • the silicon-based optoelectronics transceiver integrated chip architecture uses For dual-channel 100G/200G EPON OLT optical transceiver or dual-channel 50G/25G Combo PON, it has two downlink wavelengths, two uplink wavelengths, dual-channel Simplex LC interface, two gain chips, and two lasers.
  • the transceiver integrated chip includes:
  • Two silicon optical couplers two silicon optical splitters, four silicon optical modulators, two silicon optical multiplexers and demultiplexers, and four silicon optical PIN receivers;
  • the two silicon optical couplers respectively receive the laser signals as downlink light sources emitted by the two laser components in the optical engine (the wavelengths of the two laser signals are different, that is, the wavelengths of ⁇ DS0 and ⁇ DS1 in Figure 15 are different, and there are two sets of ⁇ DS0 and two groups of ⁇ DS1 ), the downlink light source is split through a silicon optical splitter to form four downlink light sources, two of which have the same wavelength; in particular, the modulation signals are also in four groups, TX1 to TX4.
  • Each silicon optical multiplexer and demultiplexer of this transceiver integrated chip needs to support the multiplexing and demultiplexing of two downlink and two uplink optical signals with a total of four different wavelengths.
  • Each downstream light source is transmitted through the optical path and enters its corresponding silicon optical modulator for modulation.
  • Each silicon optical modulator modulates the downstream light source based on a driving electrical signal to obtain a modulated optical signal;
  • the four modulated optical signals are respectively transmitted to the silicon optical multiplexer and demultiplexer through optical paths, and the two optical signals of different wavelengths are one group.
  • a total of two groups are output to the optical engine through two silicon optical multiplexers and demultiplexers, so that The two gain components of the optical engine perform gain processing on the two sets of four-channel optical signal outputs respectively and perform downlink transmission of the four-channel optical signals through the dual-channel Simplex LC optical interface;
  • the four upstream optical signals received through the dual-channel Simplex LC optical interface are divided into two groups, each group consisting of two upstream optical signals with wavelengths ⁇ US0 and ⁇ US1 .
  • the gain is amplified in the two gain components of the optical engine respectively, and then enters the respective silicon optical multiplexer and demultiplexer for processing, and then is transmitted through the optical path to the respective silicon optical PIN receiver for photoelectric conversion.
  • Each silicon optical PIN receiver outputs one channel after conversion. electrical signals (such as RX1 to RX4 (Receiving)).
  • the transceiver integrated chip modulates the optical signal based on each driving electrical signal, and the modulated downstream optical signals are four downstream optical signals; accordingly, in the optical
  • the uplink optical signals received by the interface are four uplink optical signals, and the transceiver integrated chip performs photoelectric conversion on the four uplink optical signals respectively and outputs the converted four independent electrical signals.
  • this embodiment also provides a transceiver integrated chip for four-way driving electrical signals, with a large rectangular frame structure as shown in Figure 16.
  • the silicon-based optoelectronics transceiver integrated chip architecture is used for 100G/200G TWDM-PON OLT optical transceiver, which can have four downlink wavelengths, four uplink wavelengths, a Simplex SC interface, an O-band gain chip, and four O-band lasers.
  • the transceiver integrated chip includes:
  • Each silicon optical coupler receives the laser signal as a downstream light source emitted by the corresponding laser component in the optical engine.
  • the downstream light source is transmitted through the optical path and enters a corresponding silicon optical modulator for modulation.
  • Each silicon optical modulator Modulate the downstream light source of this path based on a driving electrical signal to obtain a modulated optical signal;
  • the modulated four optical signals are transmitted through the optical path to a silicon optical multiplexer and demultiplexer and merged into an on-chip waveguide to output the four downlink optical signals to the optical engine, so that a gain component of the optical engine performs gain processing on the four outputs. And the downlink transmission of four optical signals is performed through the optical interface.
  • a silicon optical multiplexer and demultiplexer of this transceiver integrated chip needs to support the multiplexing and demultiplexing of four downlink and four uplink optical signals with a total of eight different wavelengths.
  • the four upstream optical signals received through the optical interface are gain amplified in a gain component of the optical engine, processed by a silicon optical multiplexer and demultiplexer, and then enter four different on-chip waveguides according to different wavelengths to become spatially separated four
  • the uplink optical signals on the road ( ⁇ US0 , ⁇ US1 , ⁇ US2 , and ⁇ US3 in Figure 16) are transmitted through the optical path to their respective silicon optical PIN receivers for photoelectric conversion.
  • Each silicon optical PIN receives The converter outputs a converted electrical signal.
  • the silicon optical multiplexer and demultiplexer of the above embodiments can be monolithically integrated with other functions of the silicon optical integrated chip: such as on-chip waveguides, silicon optical modulators, silicon optical receivers, optical splitters, etc.
  • the optical engine in the central office module of this embodiment uses an integrated silicon-based optoelectronic integrated transceiver chip (SiP) instead of the traditional optoelectronic hybrid integrated BOSA package, which can effectively avoid the problems caused by using dozens or even hundreds of discrete high-speed optoelectronic chips for hybrid integrated packaging.
  • SiP integrated silicon-based optoelectronic integrated transceiver chip
  • the board card corresponding to the central office module using the above-mentioned transceiver integrated chip can be used in the four-way electrical signal mode.
  • a board card based on the SFP-DD/SFP-DD112 package can insert 16 SFP-DD/SFP -DD112100G or 200G TWDM PON optical transceiver or equivalent 32 SFP-DD/SFP-DD112 100G/50G or 50G/25G Combo PON optical transceiver to improve throughput and achieve flexible configuration of the rate of downlink optical signals, compatible with more customer needs, and compatibility with different standards.
  • the above embodiments can be oriented to 50G/100G/200G OLT pluggable PON optical modules for future applications, and can adopt a rate combination (Combo) method (for example, the downlink transmission in the same OLT optical module can use two different rate combinations of 25G+50G, 50G+100G two-way combination of different rates, etc. (no need to use the same rate), so the OLT module must be equipped with a chipset to handle 25G/50G/100Gbps multi-channel burst mode reception amplification at multiple rates; with the help of burst mode reception amplification The chipset realizes the processing of various burst data of the home optical modem ONU.
  • a rate combination for example, the downlink transmission in the same OLT optical module can use two different rate combinations of 25G+50G, 50G+100G two-way combination of different rates, etc. (no need to use the same rate)
  • the OLT module must be equipped with a chipset to handle 25G/50G/100Gbps
  • This embodiment provides an optical engine for a PON OLT system.
  • the optical engine in this embodiment is used in PON network optical connections.
  • the optical engine can be pluggably connected to a PON optical transceiver module, that is, an optical module.
  • the optical engine in the subordinate embodiment The module is inserted into the array slot on the PON OLT system panel to realize the PON network optical connection. This can effectively achieve high integration and small packaging, and solve the problems of high cost and difficult packaging caused by the existing mixed packaging stack combination structure.
  • the optical engine is located in the OLT module that adopts the SFP-DD/SFP-DD112 protocol, that is, the optical transceiver, and modulates and gains the optical signal based on the single, dual or four-channel driving electrical signals at the OLT front end to Emitted through the optical interface of the light engine;
  • the uplink optical signal received by the optical interface of the optical engine is photoelectrically converted to be sent to the burst mode receiving amplification chipset of the OLT located in the external area of the optical engine for processing;
  • the optical engine in this embodiment is provided with an implementation Take an arbitrarily described silicon-based optoelectronic transceiver integrated chip (as shown in Figures 1 to 3, Figure 15 and Figure 16).
  • the transceiver integrated chip modulates the optical signal based on the single-channel or dual-channel drive electrical signal at the front end of the OLT, and the modulated downlink optical signal is transmitted through the optical interface of the optical engine after gain processing by the optical engine; and, the transceiver integrated chip
  • the uplink optical signal received by the optical interface of the optical engine is photoelectrically converted to be sent to the burst mode receiving amplification chipset of the OLT located in the external area of the optical engine for processing.
  • the light engine uses an integrated silicon-based optoelectronic integrated transceiver chip (SiP) instead of the traditional optoelectronic hybrid integrated BOSA package, which can effectively avoid the process complexity caused by using multiple discrete high-speed optoelectronic chips for hybrid integrated packaging and improve the product quality. Yield, cost reduction, total power consumption of optical transceivers, and product reliability are improved; it has the characteristics of high performance, high integration, high reliability, and is suitable for miniaturization packaging, and is suitable for higher performance and higher port density PON OLT in the future. system.
  • SiP integrated silicon-based optoelectronic integrated transceiver chip
  • the optical interface in the optical engine A2 of this embodiment can be used to receive uplink optical signals or send downlink optical signals.
  • the optical interface can include: a single-channel single-fiber bidirectional Simplex SC interface and/or a dual-channel single-fiber Dual Simplex LC interface for bidirectional transmission; shown in Figure 8.
  • optical interface is an interface packaged in an SFP-DD/SFP-DD112 module.
  • the current optical interface is different from the four optical interface types defined by the existing SFP-DD/SFP-DD112MSA protocol (Duplex LC, MPO-12, MDC, SN, as shown in Figure 7).
  • the SFP-DD/SFP-DD112 encapsulation protocol is used to encapsulate the Simplex SC optical interface in the OLT, so that the Simplex SC optical interface supports single-channel single-fiber bidirectional (Bi-Direction, BiDi) transmission of optical signals in the PON.
  • the SFP-DD/SFP-DD112 encapsulation protocol can also be used to encapsulate the dual-channel Simplex LC optical interface, so that the dual-channel Simplex LC optical interface supports the single-fiber bidirectional transmission characteristics of multi-port high-density PON OLT systems.
  • the optical interfaces shown in Figures 4 to 6 are single-channel Simplex SC or dual-channel Simplex LC (Bi-Direction) optical interfaces.
  • the dual-channel Simplex LC PON optical transceiver supports higher-density and higher-performance OLT systems: while maintaining the same PON MAC Serdes rate, the total throughput of the PON board can be compared with that of using a single-channel SC optical interface optical module. The total throughput of the PON board is doubled.
  • the original PON board supports up to 16 SC ports (channels) SFP series PON OLT optical transceivers, and now it can support 32 high-speed LC optical interface PON transceiver channels.
  • PON MAC SerDes rate is upgraded to 100Gbps (PAM4) in the future, this solution can smoothly support dual-port 2x100GPON.
  • the light engine A2 mainly includes: O-band laser and driving components (such as O-band high-power semiconductor laser 6, high-power semiconductor laser driver 22), O-band gain chip And driving components (O-band gain chip 9, SOA driver 12), optical interface (such as SimplexSC optical interface 10), golden finger array 26;
  • O-band laser and driving components such as O-band high-power semiconductor laser 6, high-power semiconductor laser driver 22
  • O-band gain chip And driving components O-band gain chip 9, SOA driver 12
  • optical interface such as SimplexSC optical interface 10
  • golden finger array 26 such as O-band laser and driving components (such as O-band high-power semiconductor laser 6, high-power semiconductor laser driver 22), O-band gain chip And driving components (O-band gain chip 9, SOA driver 12), optical interface (such as SimplexSC optical interface 10), golden finger array 26;
  • the O-band laser and driver components are used as laser components to generate laser signals as downlink light sources; the O-band gain chip and driver components are used to transmit and receive the optical signals output by the silicon-based optoelectronic integrated chip. Perform gain processing, or perform gain processing on the uplink optical signals received by the optical interface; the golden finger array is used to transmit electrical signals/driving electrical signals of the optical engine and other components in the OLT.
  • the driving electrical signal at the front end of the OLT is one driving electrical signal
  • the driving electrical signal at the front end of the OLT is a two-way driving electrical signal
  • the method is to divide one light source signal into two independent optical signals in a 1:2 manner on the silicon optical chip, which can be used for 25G(S)PON, ITU-T 50GPON with doubled density, or single-channel 100GPON with higher speed in the future. .
  • the light engine can use a high-power semiconductor laser to split the signal into two paths on the SiP chip through the silicon-based optical splitter 24, that is, the silicon-based 1:2 optical splitter/1:2 optical splitter, and realize high-speed signal modulation on the chip respectively. , combine and split waves, transmit and receive.
  • microlenses 25a and 25b are shown in FIG. 5 , which realize the transmission of gain-processed optical signals to the optical interface.
  • curved arrows are used to illustrate the processes of uplink and downlink optical signal transmission respectively. That is, there are respective on-chip waveguides corresponding to the optical signal transmission, as well as respective optical monitors 20a to 20b, as shown in solid The circles show the structure.
  • the driving electrical signals at the front end of the OLT are two driving electrical signals
  • there are two O-band lasers and driving components a high-power semiconductor laser driver in Figure 6, used to emit ⁇ DS0 laser
  • the O-band gain chip and the driving component are one, and a micro lens 25.
  • the optical interface of the optical engine also receives two wavelength optical signals. After passing through the silicon optical multiplexer and demultiplexer, it is divided into uplink optical signal ⁇ US0 and uplink optical signal ⁇ US1 and enters their respective silicon optical PIN receivers.
  • the light engine shown in Figure 6 also has two modulation control signals, such as TX1 and TX2 shown in Figure 6 .
  • the OLT optical transceiver to which the optical engine belongs can be used in the IEEE50G-EPON system based on 2x25G.
  • the two driving electrical signal rates are different, such as 50Gbps on one side and 25Gbps on the other, 50GPON/25G Combo PON can be realized.
  • these two different rate electrical signals can be realized through a single row of SFP-DD/SFP-DD112 optical transceiver golden finger array: each row is equipped with a pair of 25Gbps and 50Gbps signals; it can also be realized through double rows: One row of gold finger arrays is equipped with two channels of 25Gbps signals, and the second row of gold finger arrays is equipped with two channels of 50Gbps signals.
  • two sets of 50G/25G Combo PON can be implemented in one SFP-DD/SFP-DD112 optical transceiver.
  • the structure shown in Figure 6 puts forward higher requirements for the integration level of optoelectronic chip packaging. Compared with the single-channel light engine shown in Figure 4, it needs to integrate an additional set of high-speed optoelectronic chips, and the integration level is higher in the limited space of SFP. .
  • the integration level of the structures shown in Figures 15 and 16 is at least doubled compared to the integration level shown in Figure 6 .
  • silicon-based optoelectronic integrated SiP technology can be used to integrate a variety of multi-grain (tens to hundreds) silicon (germanium) devices, optical couplers, high-speed modulators, and multiplexers and demultiplexers on a small-area silicon chip.
  • optical interconnection waveguide high-speed PIN receiver, 1:2 optical power splitter, on-chip optical power dynamic monitor, etc., suitable for SFP-DD/SFP-DD112 for next-generation PON applications with high performance, high density, and low power consumption Miniaturized packaging.
  • the optical transceiver when only using the retimer function of the DSP or only using an independent retimer chip, the optical transceiver can support IEEE 802.3ca 50G-EPON based on the Ethernet rate.
  • the standard is based on dual wavelength 25G to enable 50G. In this case, the two channels use different wavelengths.
  • the downlink wavelengths are 1342nm ⁇ 2nm and 1358nm ⁇ 2nm respectively.
  • the optical engine integrates different wavelength lasers, and the dual lasing wavelengths enter the SiP chip through the silicon optical coupler. In this embodiment, a 1:2 optical splitter is not used, and the receiving end wavelengths are 1270nm ⁇ 10nm and 1300 ⁇ 10nm respectively.
  • this embodiment can be used to support Combo PON: For example, when the two-way electrical signal rates are 50Gbps and 25Gbps respectively, this optical transceiver can support future 50G/25G Combo PON.
  • SerDes rate is upgraded to 28GBAUD (56G PAM4) or 56GBAUD (112G PAM4) rate
  • the optical transceiver of this embodiment can smoothly support future single-port dual-wavelength 100G-EPON or 200G-EPON.
  • the driving electrical signals at the front end of the OLT are two driving electrical signals
  • the driving electrical signals are four-way driving electrical signals, there are two O-band lasers and driving components, and two O-band gain chips and driving components, as shown in Figure 15.
  • driving electrical signals are four-way driving electrical signals, there are four O-band lasers and driving components, and one O-band gain chip and driving component. As shown in Figure 16.
  • the silicon optical modulator 5 modulates the CW (Continuous Wave: continuous wave) laser signal from the silicon optical coupler into the silicon optical chip at high speed, and passes the high-speed modulated optical signal through the silicon optical chip.
  • the on-chip waveguide sends it to the silicon optical multiplexer and demultiplexer 8 .
  • O-band high-power semiconductor laser 6 outputs a transmitter laser signal that meets the protocol wavelength requirements
  • Silicon optical coupler 7 used to couple the laser signal generated by the O-band high-power semiconductor laser to the transceiver integrated chip A1;
  • Silicon photonic multiplexer and demultiplexer 8 Silicon photonic integrated on-chip dual-wave filter (multiplexer and demultiplexer): the transmitted signal from the silicon photonic modulator 5 and the electrical interface 2 is coupled into the O-band gain chip 9 through this;
  • O-band gain chip 9 O-band optical signals of different wavelengths are amplified simultaneously through this gain chip when transmitting (downlink ⁇ DS ) and receiving (uplink ⁇ US ).
  • the downlink ⁇ DS is coupled to the SimplexLC optical interface 10 of the SFP-DD optical transceiver through free space and microlenses
  • the uplink ⁇ US is coupled to the O-band gain chip 9 through free space and lenses;
  • Simplex LC optical interface 10 Downstream ⁇ DS is coupled into the transmission fiber through this interface; upstream ⁇ US enters the transceiver through this interface and is coupled to the silicon optical multiplexer and demultiplexer 8 through free space and lenses (such as microlens 25c).
  • Silicon photonic PIN receiver 11 Downstream ⁇ DS enters this PIN receiver through the on-chip waveguide;
  • SOA (Gain Chip) driver 12 Sets the operating point of the O-band gain chip 9;
  • Micro TEC controller (not shown in the figure): used to achieve micro temperature control, control the SiP temperature within a certain range, and prevent the performance of O-band high-power semiconductor lasers from declining at high temperatures and the performance of silicon photonics multiplexers and demultiplexers from drifting with temperature.
  • High-power semiconductor laser driver 22 used to set the optimal operating point of the O-band high-power semiconductor laser.
  • silicon optical couplers silicon optical multiplexers and demultiplexers, silicon optical modulators, silicon optical PIN receivers, on-chip monitors, and on-chip waveguides that support PON applications are silicon devices that realize multiple functional devices on silicon-based materials through one taping.
  • Optoelectronic monolithic integration has greatly improved the integration level of high-speed optoelectronic chips, improving reliability and production yield; while O-band CW high-power semiconductor lasers and O-band gain chips achieve optical coupling with SiP through heterogeneous integration.
  • the downlink electrical signal When the downlink electrical signal is 25Gbps, it forms a symmetrical single-channel 25G(S)PON working mode with the uplink burst mode 25Gbps, which can support the 25G(S)PON multi-source protocol led by overseas equipment vendors (such as Nokia) and is applicable to The next generation high-speed PON network of large overseas operators (AT&T, etc.); through 2:1 gearbox (one of the analog/digital signal processing integrated component functions), overseas equipment manufacturers and operators using 25G PON MAC do not need to upgrade MAC and SerDes In the case of high speed, the PMD layer can be smoothly implemented to support 50G(S)PON.
  • the downlink When the downlink is 50Gbps, it forms a 50G(S)PON working mode with the uplink 25Gbps (or 50Gbps), supporting the ITU-T50GPON standard and the next-generation high-speed PON technology path selected by the three major domestic operators.
  • This embodiment provides a multi-rate central office module based on a silicon-based optoelectronic integrated chip.
  • the central office module is a module packaged in SFP-DD/SFP-DD112.
  • the central office module includes: an electrical interface, a single/ Dual/quad multi-rate analog/digital signal processing integrated components, optical engine and burst mode receiving amplification chipset;
  • the electrical interface is used to realize electrical signal transmission between the central office module and the system board;
  • the analog/digital signal processing integrated component is used to perform clock data recovery, rate and/or code type conversion processing on the downlink electrical signal with the first parameter transmitted by the system board through the electrical interface, to obtain a signal with the first parameter.
  • a two-parameter electrical signal which is used to apply the optical signal corresponding to the silicon-based optoelectronic integrated chip in the optical engine to achieve modulation of the optical signal, and transmit the modulated downlink optical signal through the optical interface transmission network of the optical engine.
  • the uplink optical signal received by the optical interface of the optical engine is converted into an electrical signal through the reception of the silicon-based optoelectronic integrated chip in the optical engine; the electrical signal is transmitted to the said electrical signal through the burst mode receiving amplification chipset and the electrical interface. system board;
  • the silicon-based optoelectronic integrated chip in the light engine is a transceiver integrated chip that integrates the transmission and reception of optical signals.
  • the silicon-based optoelectronic integrated chip in the optical engine of the central office module is the silicon-based optoelectronic transceiver integrated chip used in the PON OLT system as described in any of the above embodiments.
  • the above-mentioned optical engine can also be any of the optical engines used in the PON OLT system described in the second embodiment.
  • the SFP-DD of this embodiment implements dual-channel Simplex LC optical interface (dual-channel BiDi) high-speed PON, which poses higher challenges to optical chip integration.
  • the optoelectronic chip supporting PON applications requires two Sets or even four sets, it is difficult to put all the devices into the SFP-DD optical transceiver using the traditional optical engine packaging method of hybrid integrated discrete devices.
  • the use of silicon-based optoelectronic integrated chips can realize these functional devices and their mutual connections on a small chip. For example, two sets of silicon optical couplers, silicon optical multiplexers, silicon optical modulators, silicon optical PIN receivers, on-chip monitors, and on-chip waveguides are required, and silicon optical splitters are added. These can be passed through a single flow The chip realizes monolithic integrated chip SiP on silicon-based materials.
  • the electrical interface in the central office module in this embodiment may include: a gold finger array of an SFP-DD/SFP-DD112 packaged printed circuit board, that is, an SFP-DD/SFP-DD112 packaged electrical interface 2.
  • the electrical interface in this embodiment is used to realize the connection between the 25/50/100/200G PON OLT system and/or the 50/100/200G EPON OLT system and the central office module, and the electrical interface includes one or more of the following Types: single-channel electrical interface, dual-channel electrical interface, and four-channel electrical interface.
  • the PON MAC ASIC 1 in the system board enters the central office module through the electrical interface 2 of the SFP-DD/SFP-DD112 package, and is processed by the digital processing chip 3 and the silicon light modulation driver 4, and then Output to the optical engine A2 and then output through the optical interface; accordingly, the uplink optical signal received by the optical interface is converted into an uplink electrical signal by the optical engine, and passes through the burst mode transimpedance amplifier BM-TIA 14 and the burst mode linear amplifier BM-LA After 15, it is output to the burst mode CDR SERDES16 in the system board with the help of the electrical interface 2, and then further enters the PON MAC ASIC 1.
  • the analog/digital signal processing integrated components in this embodiment include: a digital processing chip DSP 3 and a modulation drive component for optical signal modulation;
  • the DSP 3 is used to perform clock data recovery, rate and/or code pattern mapping conversion on the single or dual-channel electrical signals (such as TX1 and TX2) transmitted by the electrical interface according to the parameters of the optical transmission equipment, so as to obtain A downlink electrical signal with consistent parameters of the optical transmission equipment is obtained by modulating the drive component to obtain a drive electrical signal;
  • the DSP includes: Retimer component, gearbox Gearbox component, and code conversion module;
  • the DSP gearbox Gearbox component When a single-channel 1x25Gbps or 1x50Gbps NRZ or 1x100Gbps PAM4 code is input, the DSP gearbox Gearbox component does not work.
  • the single-channel Retimer component will input a single-channel electrical signal for clock data recovery and output a single-channel 1x25Gbps NRZ or 1x50Gbps NRZ or 1x100Gbps PAM4 code. As a downward electrical signal;
  • the dual-channel input electrical signal 2x25Gbps NRZ mapping is converted into a single-channel 50Gbps NRZ code pattern through the Retimer component and the gearbox Gearbox component as an output downlink electrical signal;
  • the dual-channel input signal 2x25Gbps NRZ mapping is converted into a single-channel 50Gbps PAM4 code pattern through the Retimer component, the gearbox Gearbox component and the code pattern conversion module, as an output downlink electrical signal;
  • the dual-channel input signal 2x50Gbps NRZ mapping is converted into a single-channel 100Gbps NRZ code pattern through the Retimer component and the gearbox Gearbox component as an output downlink electrical signal;
  • the dual-channel input signal 2x50Gbps NRZ mapping is converted into a single-channel 100Gbps PAM4 code pattern through the Retimer component, the gearbox Gearbox component and the code conversion module, which is used as an output downlink electrical signal;
  • the dual-channel input signal 2x100Gbps PAM4 mapping is converted into a single-channel 1x200Gbps PAM4 code pattern through the Retimer component and the gearbox Gearbox component, which is used as an output downlink electrical signal.
  • the retimer can be used to achieve high-quality transceiver transmission of high-speed electrical signals between the optical module and the system board.
  • the first parameter electrical signal rate is not less than 50Gbps
  • a DSP chip is required to process the high-speed electrical signal, and retime-only is only used in some scenarios with limited transmission performance.
  • the OLT optical module cases shown in Figures 9 to 14 cover three types of functional architecture: DSP processes both sending and receiving signals, both sending and receiving are retimer-only, and DSP only processes the sending end signal and the receiving end does not require a DSP.
  • the analog/digital signal processing integrated component in this embodiment includes: a dual-channel retimer component and a modulation drive component for optical signal modulation;
  • the dual-channel retimer component is used to perform clock data recovery, rate and/or code pattern mapping conversion on the dual-channel electrical signals transmitted by the electrical interface according to the parameters of the optical transmission equipment, so as to obtain a signal consistent with the parameters of the optical transmission equipment.
  • Two channels of downlink electrical signals are generated by modulating the drive components to obtain two channels of drive electrical signals.
  • the above-mentioned dual-channel retimer component may include: retimer chip;
  • the retimer chip When the dual-channel 2x25Gbps NRZ code pattern is input, the retimer chip is used to recover the clock data of the dual-channel electrical signals received by the electrical interface, and map and convert them into dual-channel 25Gbps NRZ code pattern as the output dual-channel downlink electrical signal;
  • the retimer When the dual-channel 2x50Gbps NRZ code pattern is input, the retimer is used to recover the clock data of the dual-channel electrical signals received by the electrical interface, and map and convert them into the dual-channel 2x50Gbps NRZ code pattern as the output dual-channel downlink electrical signal;
  • one channel is 25Gbps NRZ code type, and the other channel is 50Gbps NRZ code type.
  • the retimer is used to recover the clock data of the dual-channel electrical signals received by the electrical interface, and map and convert them into one channel being 25Gbps NRZ, and the other channel being 25Gbps NRZ. It is 50Gbps NRZ code type, used as the output dual downlink electrical signal;
  • the retimer When the dual-channel 2x100Gbps PAM4 code pattern is input, the retimer is used to recover the clock data of the dual-channel electrical signals received by the electrical interface, and map and convert them into the dual-channel 2x 100Gbps PAM4 code pattern as the output dual-channel downlink electrical signal.
  • the retimer function when only using the retimer function, it can support dual-channel single-fiber bidirectional optical interface mode and support dual-channel 25G(S)PON or 50G(S)PON.
  • the advantage of dual-channel PON transceivers is that they support higher-density and higher-performance OLT systems. Without changing the PON MAC serdes rate, the total bandwidth of the PON connection is doubled compared to the single-channel scenario.
  • the original PON board supported 16-port SFP+PON OLT optical transceiver, but now it can support 32 high-speed PON ports.
  • the analog/digital signal processing integrated component includes: four-channel DSP (including retimer) or an independent retimer component and a modulation driving component for optical signal modulation.
  • the four-way retimer component is used to perform clock data recovery, rate and/or code pattern mapping conversion on the four-way electrical signals transmitted by the electrical interface according to the parameters of the optical transmission equipment, so as to obtain a result consistent with the parameters of the optical transmission equipment.
  • Four-way downlink electrical signals are generated, and four-way drive electrical signals are obtained by modulating the drive components.
  • the four-way speed can be consistent, such as 4x25Gbps, 4x50Gbps, or two-to-one, such as a combination of 2x25Gbps+2x50Gbps.
  • the four-way retimer component includes: retimer chip;
  • the retimer chip When four channels of 4x25Gbps NRZ code are input, the retimer chip is used to perform clock data recovery on each of the four channels of electrical signals received by the electrical interface, and map and convert them into four channels of 25Gbps NRZ code as the output of the four channels of downlink electrical signals;
  • the retimer When four channels of 4x50Gbps NRZ code are input, the retimer is used to recover the clock data of each of the four channels of electrical signals received by the electrical interface, and map and convert them into four channels of 4x50Gbps NRZ code as the output of the four channels of downlink electrical signals;
  • the retimer When using 2x25Gbps and 2x50Gbps four-way combined input, the retimer is used to recover the clock data of the four-way electrical signals received by the electrical interface, and map and convert them into four-way 2x25Gbps and 2x50Gbps NRZ code patterns as the output of the four-way downlink power supply. Signal.
  • the modulation driver component is a silicon light modulation driver component, which is integrated in the DSP, or integrated with the retimer chip on one component.
  • the burst mode receiving amplification chipset in the central office module of this embodiment may include: a burst mode receiving transimpedance amplifier 14 and a burst mode receiving linear amplifier 15, as shown in Figures 9 to 11.
  • the DSP is used to perform clock data recovery, rate and/or code pattern mapping conversion on the single-channel or dual-channel electrical signal transmitted by the electrical interface according to the parameters of the optical transmission equipment, so as to obtain a signal that is consistent with the optical transmission equipment.
  • the transmission parameters require a downlink electrical signal, and by modulating the drive component, a drive electrical signal, which is the second parameter, is obtained.
  • the input and output burst mode electrical signals of the burst mode receiving amplification chipset are one channel, as shown in Figure 9, and this burst mode receiving the electrical signal rate of the amplifying chipset is equal to or lower than the rate of the electrical signal having the second parameter,
  • the input and output burst mode electrical signals of the burst mode receiving amplification chipset are two-way, as shown in Figure 10 and Figure 11, and the two-way The rate at which the burst mode receives the amplified chipset electrical signal is no higher than the rate at which the electrical signal has the second parameter.
  • the burst mode receiving and amplifying chipset input and output burst mode electrical signals are four channels
  • the four-channel burst mode receiving and amplifying chipset electrical signals are The rate is no higher than the rate of the electrical signal having the second parameter.
  • the above second parameter can also be:
  • Digital processing chip DSP and modulation drive components for silicon light optical signal modulation Digital processing chip DSP and modulation drive components for silicon light optical signal modulation
  • the DSP is used to perform clock data recovery, rate and/or code pattern mapping conversion and other processing on the four-way electrical signals transmitted by the electrical interface according to the parameters of the optical transmission equipment, so as to obtain a signal that meets the transmission parameter requirements of the optical transmission equipment.
  • a single-channel downlink electrical signal is used to modulate the drive component to obtain a single-channel drive electrical signal, which is the second parameter;
  • a digital processing chip DSP and a modulation drive component for silicon optical signal modulation the DSP is used to perform clock data recovery, rate and/or on the four-way electrical signals transmitted by the electrical interface according to the parameters of the optical transmission equipment. Mapping and conversion of code patterns and other processing to obtain a dual-channel downlink electrical signal that meets the transmission parameter requirements of the optical transmission equipment, and through the modulation drive component, the dual-channel drive electrical signal, which is the second parameter, is obtained, or the digital processing chip DSP and the user Modulation driver components for silicon photonic optical signal modulation;
  • the DSP is used to perform clock data recovery, rate and/or code pattern mapping conversion and other processing on the four-way electrical signals transmitted by the electrical interface according to the parameters of the optical transmission equipment, so as to obtain a signal that meets the transmission parameter requirements of the optical transmission equipment.
  • the four-way downlink electrical signals are used to modulate the driving components to obtain the four-way driving electrical signals, which are the second parameters.
  • the uplink electrical signal received by the burst mode amplification chipset is a single channel 1x25Gbps NRZ;
  • the uplink electrical signal passed through the burst mode receiving amplification chipset is a single channel 1x25Gbps NRZ or 1x50Gbps NRZ;
  • the uplink electrical signal passing through the burst mode receiving amplification chipset is a single channel 1x50Gbps NRZ or 1x100Gbps NRZ or a single channel 1x100Gbps PAM4;
  • the uplink electrical signal passed through the burst mode receiving amplification chipset is a single channel 1x50Gbps PAM4 or a single channel 1x25Gbps NRZ;
  • the uplink electrical signal passed through the burst mode receiving amplification chipset is a single channel 1x100Gbps PAM4 or a single channel 1x50Gbps NRZ;
  • the uplink electrical signal passed through the burst mode receiving amplification chipset is a single channel 1x200Gbps PAM4 or a single channel 1x100Gbps PAM4.
  • the upstream electrical signal received by the burst mode reception amplification chipset is dual-channel 2x25Gbps NRZ;
  • the upstream electrical signal through the burst mode receiving and amplifying chipset is dual-channel 2x50Gbps NRZ or dual-channel 2x25Gbps NRZ or a combination of single-channel 1x50Gbps NRZ and single-channel 1x25Gbps NRZ. ;
  • the upstream electrical signal received through the burst mode receiving amplification chipset is dual-channel 2x100Gbps PAM4 or dual-channel 2x50Gbps NRZ.
  • the upstream electrical signal through the burst mode receiving amplification chipset is a combination of a single channel 1x25Gbps NRZ and a single channel 1x50Gbps NRZ, or dual channels 2x25Gbps NRZ;
  • the uplink electrical signal of the burst mode receiving amplification chipset is four channels of 4x25Gbps NRZ;
  • the upstream electrical signal of the burst mode receiving and amplifying chipset is four channels of 4x50Gbps NRZ;
  • the upstream electrical signal of the burst mode receiving amplification chipset is a combination of four 2x25Gbps NRZ and 2x50Gbps NRZ or four 4x25Gbps NRZ;
  • the central office module also needs to include: a microprocessor 17, an EEPROM 18, a power management component 23, etc.
  • the processing methods of these components can be consistent with the processing methods of each component in the existing central office module. The examples will not be described in detail.
  • Figure 12 also shows the optical transceiver power supply 19 that provides power for the central office module, which can be configured as needed in actual applications.
  • the central office equipment of this embodiment adopts the miniaturized SFP-DD/SFP-DD112 module to effectively meet the high port density and high performance requirements of the next generation OLT system equipment.
  • Figures 12 to 14 it can be seen that the SerDes rates applicable to Figures 12 and 13 are currently 24.8832Gbps NRZ and 49.7664Gbps NRZ. In the future, the SerDes rate can reach 99.5328Gbps PAM4.
  • the left side of Figures 12 to 14 belongs to the OLT PON MAC in the system board. It is located on the system board and is programmable in the form of ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array). Gate array) method to implement Physical Coding Sublayer (PCS) functions, including forward error correction (FEC), signal encoding and decoding, etc.
  • ASIC Application Specific Integrated Circuit
  • FPGA Field Programmable Gate Array
  • PCS Physical Coding Sublayer
  • the MAC single-channel high-speed signal uses the ITU-T PON standard rate of 24.8832Gbps (referred to as 25Gbps) or 49.7664Gbps (50Gbps), and the encoding method uses NRZ. This structure has the same function as the existing structure and will not be repeated here.
  • the MAC single-channel high-speed signal can also be upgraded to 99.5328Gbps in the future, and the encoding method is PAM4.
  • the MAC single-channel high-speed signal can also use the Ethernet rate 25.78125Gbps (also referred to as 25Gbps).
  • PMA currently outputs 2*24.8832Gbps NRZ and 2*49.7664Gbps NRZ, and can output 2*99.5328Gbps PAM4 in the future.
  • the SerDes single-channel rate is currently 28G NRZ, and the optical port single-channel rate is currently 25.78125Gbps NRZ.
  • the single-channel rate of Ethernet PON SerDes can reach 56Gbps PAM4 and 112Gbps PAM4.
  • the high-speed signals, control signals, power supply, etc. of the system board enter and exit the optical transceiver through this; the electrical interface can provide dual high-speed electrical signal input (TX1&2) and output (RX1&2) at the same time, or according to the system board requirements , only provides one input and output (Tx1+Rx1).
  • Silicon light modulator driver/silicon light modulation driver component The high-speed signal after mapping conversion is superimposed on this driver, and the driver modulates the silicon light modulator at high speed.
  • the current output of the silicon light modulation driver shown in Figure 12 is 1*24.8832Gbps NRZ, 1*49.7664Gbps NRZ, 1*49.7664Gbps PAM4; the output of the future silicon light modulation driver can be 1*99.5328Gbps NRZ, 1*99.5328 Gbps PAM4, 1*199.0656Gbps PAM4.
  • Burst mode transimpedance amplifier 14 amplifies the 25G or 50G burst mode signal received by the PIN receiver 11;
  • Burst mode linear amplifier 15 amplifies the 25G/50G differential electrical signal output by the burst TIA and reduces the loss of the preamble;
  • BM CDR SERDES (Burst Mode Clock Data Recovery SerDes): Located on the system board.
  • the received signal Rx1 enters this BM CDR SERDES 16 after passing through the burst mode linear amplifier 15 and the electrical interface 2; under the reference of the local precise clock signal 24.8832Gbps or 49.7664Gbps, frequency and phase identification are performed on the signal of the burst limiting amplifier.
  • Process eliminate the jitter and inter-symbol interference of the uplink signal, and then transmit it back to the PON MAC ASIC 1 in the system.
  • Microprocessor 17 used to process the control signals and sensing signals of each component of the optical transceiver, and coordinate the work of each component;
  • EEPROM Electrical Erasable Programmable Read-only Memory 18: used to store the performance and control information of each optical device inside the optical transceiver. When the optical transceiver is working normally, it is passed by the micro TEC controller I 2 C calls the corresponding technical parameters in EEPROM 18;
  • Optical transceiver power supply 19 Provides the power required for normal operation of each component of the optical transceiver through the electrical interface 2; for example, a 3.3V power input can be provided.
  • Power management component 23 used to step down or boost the 3.3V total power supply of the optical transceiver to the level required by each unit circuit, and supply power to the corresponding unit circuit according to the specified timing.
  • the electrical interface defined by the SFF-DD MSA protocol is combined with the ITU-T PON rate definition, and the same package is also provided.
  • the optical port rate is upgraded to a direct path to a single 100GPON, and the encoding method can be flexibly adopted NRZ or Use PAM4.
  • SFP-DD112MSA has added support for a single 100G PAM4 input signal, so the above-mentioned optical transceiver can be expanded to a single 200GPON (output signal after 2x1gearbox) in the future on the SFP-DD112 package.
  • This embodiment also provides a passive optical network PON OLT system, which includes: a multi-rate channel central office module based on a silicon-based optoelectronic integrated chip as described in any of the above-mentioned embodiment four; the system passes through the central office The module interacts with the PON network side.
  • the basic hardware unit of the system includes power supply, chassis and boards.
  • the number of SFP-DD/SFP-DD112 optical transceivers that can be inserted into the central office board of the PON OLT system is 16.
  • the encoded high-speed signal sent by the PON MAC ASIC 1 enters the digital processing chip (DSP) 3 in the optical transceiver through the electrical interface 2 of the SFP-DD/SFP-DD112 package.
  • the signal rate complies with the ITU-T PON standard rate requirements: 24.8832Gbps (referred to as 25Gbps) or 49.7664Gbps (50Gbps), and the encoding method is NRZ.
  • SFP-DD/SFP-DD112 can support dual high-speed electrical signal inputs (TX1&TX2) and outputs (RX1&RX2), or only one input and output (Tx1+Rx1).
  • the single/dual/quad high-speed signals output by the digital processing chip (DSP) 3 are applied to the silicon light modulation driver 4, the silicon light modulation driver 4 modulates at high speed, and the high-power semiconductor laser driver 22 sets the O-band high-power semiconductor laser 6
  • the optimal operating point is the O-band high-power semiconductor laser 6 with the optimal operating point set to output a high-power laser signal as the PON downlink light source.
  • the lasing wavelength is maintained at 1342nm ⁇ 2nm and 1358nm ⁇ 2nm within the full operating temperature range.
  • the transceiver integrated chip A1 through the silicon optical coupler 7
  • enter the silicon optical modulator 4 through the on-chip waveguide, and are modulated at high speed, then pass through the on-chip waveguide, pass through the silicon optical multiplexer and demultiplexer 8, and then leave the transceiver integrated chip A1.
  • the O-band gain chip 9 is set by the SOA driver 12 to the optimal chip operating point, and transmits (downlink ⁇ DS ) and receives (uplink ⁇ US ) O-band optical signals of different wavelengths through this gain chip at the same time magnified.
  • the ⁇ DS emitted high-power signal amplified by the O-band gain chip 9 is coupled to the SimplexSC optical interface 10 of the SFP-DD/SFP-DD112 optical transceiver through the microlens (25c, 25a or 25b), and enters the far end of the transmission fiber transmission network ;
  • the signal description in the receiving direction is as follows:
  • the upstream lambda US enters the optical engine of the optical transceiver from the transmission fiber through the SimplexSC optical interface 10.
  • the upstream ⁇ US enters the O-band gain chip 9 through the microlens (25c, 25a or 25b) and is amplified and passes through the silicon optical multiplexer and demultiplexer 8.
  • the upstream ⁇ US passes through the silicon optical multiplexer and demultiplexer 8 and enters the silicon optical PIN receiver 11;
  • the optical PIN receiver 11 converts the single-channel high-speed uplink burst mode ⁇ US optical signal into a single-channel burst mode high-speed electrical signal; the burst mode high-speed electrical signal output by the silicon optical PIN receiver 11 is sequentially passed through the burst mode transimpedance amplifier 14. Burst mode linear amplifier 15.
  • the electrical interface 2 of the SFP-DD/SFP-DD112 package leaves the optical transceiver and enters the system board, and the signal passes through the BM CDR SERDES 16 of the high-speed system board and then enters the PON MAC ASIC 1 , complete the signal sending and receiving closed loop on the OLT side.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • the word “comprising” does not exclude the presence of elements or steps other than those listed in a claim.
  • the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements.
  • the embodiments described above may be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In the claim enumerating several means, several of these means may be embodied by the same hardware.
  • the use of the words first, second, third, etc. is only for convenience of expression and does not indicate any order. These words can be understood as part of the component name.

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Abstract

一种用于PON OLT系统的硅基光电子的收发集成芯片（A1）、光引擎（A2）、局端模块及PON OLT系统板卡，收发集成芯片（A1）位于OLT的光引擎（A2）中，并基于OLT前端单路、双路或四路的驱动电信号对光信号进行调制，调制后的下行光信号经过光引擎（A2）的增益处理后经由光引擎（A2）的光接口发射；以及，收发集成芯片（A1）对光引擎（A2）的光接口接收的上行光信号进行光电转换以发送OLT的位于光引擎（A2）外部区域的突发模式接收放大芯片组进行处理。局端模块为采用SFP-DD/SFP-DD112封装的模块。局端模块可以灵活配置速率，并兼容不同标准和应用场景，且能够有效降低成本。

Description

一种用于PON OLT系统的硅基光电子的收发集成芯片 技术领域
本公开涉及光通信技术领域，尤其涉及一种用于PON(Passive Optical Network，无源光网络)OLT(Optical Line Terminal，光线路终端)系统的硅基光电子的收发集成芯片。
背景技术
现有技术中公开一种用于50G以上无源光网络中的局端设备，其包括：插接在系统板上的金手指、50G以上的连续下行发射通道、25G以上的突发上行接收通道和单纤双向BOSA(Bi-Directional Optical Sub-Assembly，双向光组件)。发射通道包括DSP(Digital Signal Processor，数字信号处理器/数字信号处理芯片)、PAM4(Pulsed Amplitude Modulation Four-Level，四阶脉冲幅度调制)驱动单元、核心封装光组件BOX；DSP接收系统板的两路25G的NRZ(Non Return to Zero，非归零)TX(Transmitting，发射)信号，并合成一路50G的PAM4调制信号；PAM4驱动单元接收PAM4调制信号以驱动核心封装光组件中的外调制器生成发射的50G PAM4的光信号；接收通道包括：同轴封装TO(Transistor Outline，晶体管外形)、LA(Linear Amplifier，线性放大器)和CDR(Clock Data Recovery，时钟数据恢复)，同轴封装TO接收光信号，并转换为电信号经由LA和CDR进行限流整形后通过金手指输入给系统板，由此，上述局端设备能够实现将接入网的下行速率从10G提升到50G，上行速度提升到25G。
本发明人在研究过程中发现现有的光通道发送和接收是通过同轴封装TO和核心封装光组件如BOSA光组件实现，其占用空间、成本高，无法实现局端设备的小型化及多速率的需求。
发明内容
鉴于现有技术的上述缺点、不足，本实施例提供一种用于PON OLT系统的硅基光电子的收发集成芯片、光引擎、局端模块及于PON OLT系统板卡。
本实施例提供的基于硅基光电子集成芯片的多速率的局端模块，有效降低占用体积，且能够适应多速率的场景。
第一方面，一实施例提供一种用于PON OLT系统的硅基光电子的收发集成芯片，所述收发集成芯片位于OLT的光引擎中，且实现收发一体的集成芯片，所述收发集成芯片基于OLT调制驱动组件产生的单路、双路或四路的驱动电信号对光信号进行调制，调制后的下行光信号经过光引擎的增益处理后经由光引擎的光接口发射；
以及，所述收发集成芯片对光引擎的光接口接收的上行光信号进行光电转换以发送所述OLT的位于光引擎外部区域的突发模式接收放大芯片组进行处理。
在一种可能的实现方式中，所述驱动电信号为一路驱动电信号，则调制后的下行光信号为一路下行光信号；
所述驱动电信号为两路独立的驱动电信号，则收发集成芯片基于每一路驱动电信号对光信号进行调制，调制后的下行光信号为两路下行光信号；
所述驱动电信号为四路独立的驱动电信号，则收发集成芯片基于每一路驱动电信号对光信号进行调制，调制后的下行光信号为四路下行光信号；
所述光接口接收的上行光信号为一路上行光信号，则所述收发集成芯片对一路上行光信号进行光电转换并输出一路转换后的电信号；
所述光接口接收的上行光信号为两路上行光信号，则所述收发集成芯片对两路上行光信号分别进行光电转换并输出转换后的两路独立的电 信号；
所述光接口接收的上行光信号为四路上行光信号，则所述收发集成芯片对四路上行光信号分别进行光电转换并输出转换后的四路独立的电信号。
在一种可能的实现方式中，驱动电信号为一路驱动电信号即第二参数时，所述收发集成芯片包括：
硅光耦合器、硅光调制器、硅光合分波器、硅光PIN(Positive Intrinsic Negative，正极-绝缘-负极)接收器；
所述硅光耦合器接收所述光引擎中激光组件发出的作为下行光源的激光信号，所述下行光源经由光路传输进入到硅光调制器进行调制，所述硅光调制器所述驱动电信号对下行光源进行调制，得到调制后的光信号；
调制后的光信号经光路传输至硅光合分波器以输出至所述光引擎，以使光引擎进行增益处理并经所述光接口进行下行传输；
以及，经所述光接口接收的上行光信号在光引擎中增益放大后经硅光合分波器进入所述硅光PIN接收器进行光电转换以输出。
在一种可能的实现方式中，驱动电信号为两路驱动电信号时，所述收发集成芯片包括：
一个硅光耦合器、一个硅基分光器、两个硅光调制器、两个硅光合分波器、两个硅光PIN接收器；
此收发集成芯片的每个硅光合分波器需支持单下行单上行共两个不同波长光信号的合分波；
所述硅光耦合器接收所述光引擎中激光组件发出的作为下行光源的激光信号，所述下行光源经由硅基分光器进行分光处理，形成两路下行光源；
每一路下行光源经光路传输进入到各自对应的硅光调制器进行调制，每一个硅光调制器基于一路驱动电信号对该路的下行光源进行调制，得到调制后的一路光信号；
调制后的两路光信号分别经光路传输至各自的硅光合分波器以分别输出至所述光引擎，以使光引擎的两个增益组件对两路输出分别进行增益处理并经所述光接口进行两路光信号的下行传输；
以及，经所述光接口接收的两路上行光信号在光引擎的两个增益组件中分别进行增益放大后进入各自的硅光合分波器处理后经光路传输至各自的硅光PIN接收器进行光电转换，每一个硅光PIN接收器输出一路转换后的电信号。
在一种可能的实现方式中，驱动电信号为两路驱动电信号时，所述收发集成芯片包括：
两个硅光耦合器、两个硅光调制器、一个硅光合分波器、两个硅光PIN接收器；
每一个硅光耦合器接收所述光引擎中对应激光组件发出的作为下行光源的激光信号，两路下行光源分别对应的激光信号波长不同，且两波长间距大于10nm，所述下行光源经由光路传输进入到各自对应的一个硅光调制器进行调制，每一个硅光调制器基于一路驱动电信号对该路的下行光源进行调制；
调制后的两路不同波长光信号经光路传输至一个硅光合分波器合波后进入光引擎的一个增益组件，被增益放大处理后经所述SC光接口耦合入光纤进行两路光信号的下行传输；
以及，经所述光接口接收的两路不同波长上行光信号在光引擎的一个增益组件中进行增益放大后经一个硅光合分波器分波处理后成为两路空间分离的上行光信号，每一路上行光信号经光路传输至各自的硅光PIN 接收器进行光电转换，每一个硅光PIN接收器输出一路转换后的电信号。此实现方式中的两个上行光信号波长也不同于两个下行的光信号波长。
在一种可能的实现方式中，驱动电信号为四路驱动电信号时，所述收发集成芯片包括：
两个硅光耦合器、两个硅基分光器、四个硅光调制器、两个硅光合分波器、四个硅光PIN接收器；
所述两个硅光耦合器分别接收所述光引擎中两个激光组件发出的作为下行光源的激光信号，且两个激光信号波长不同，所述下行光源经由硅基分光器进行分光处理，形成四路下行光源，其中两两波长一致；
每一路下行光源经光路传输进入到各自对应的硅光调制器进行调制，每一个硅光调制器基于一路驱动电信号对该路的下行光源进行调制，得到调制后的一路光信号；
调制后的四路光信号分别经光路传输至硅光合分波器，且两路不同波长光信号为一组，一共两组分别通过两个硅光合分波器输出至所述光引擎，以使光引擎的两个增益组件对两组四路光信号输出分别进行增益处理并经所述duplex LC光接口进行光信号的下行传输；
以及，经所述光接口接收的四路上行光信号在光引擎的两个增益组件中分别进行增益放大后进入各自的硅光合分波器处理后经光路传输至各自的硅光PIN接收器进行光电转换，每一个硅光PIN接收器输出一路转换后的电信号。
在一种可能的实现方式中，驱动电信号为四路驱动电信号时，所述收发集成芯片包括：
四个硅光耦合器、四个硅光调制器、一个硅光合分波器、四个硅光PIN接收器；
每一个硅光耦合器接收所述光引擎中对应激光组件发出的作为下行 光源的激光信号，且四路激光信号波长不同，所述下行光源经由光路传输进入到各自对应的一个硅光调制器进行调制，每一个硅光调制器基于一路驱动电信号对该路的下行光源进行调制，得到调制后的一路光信号；
调制后的四路光信号经光路传输至一个硅光合分波器在空间上合并进入一个片上波导以输出四路下行光信号至所述光引擎，以使光引擎的一个增益组件对四路输出进行增益处理并经所述Simplex SC光接口进行四路光信号的下行传输；
以及，经所述光接口接收的四路上行光信号在光引擎的一个增益组件中进行增益放大后耦合进入硅基光电子集成芯片上一个片上波导，并经一路硅光合分波器处理后，依不同波长进入四个片上波导成为四路空间分离的上行光信号，每一路上行光信号经光路传输至各自的硅光PIN接收器进行光电转换，每一个硅光PIN接收器输出一路转换后的电信号。
在一种可能的实现方式中，所述收发集成芯片还包括：对应光路传输的硅光波导、硅光监测器；
所述硅光波导、硅光监测器用于对光路传输的光信号进行传输和监测。
第二方面，一实施例还提供一种用于PON OLT系统的光引擎，所述光引擎位于采用SFP-DD(Small Form-factor Pluggable-Double Density，双密度小型可插拔)或SFP-DD112(Small Form-factor Pluggable-Double Density 112G，单路112G的双密度小型可插拔)封装的OLT模块中，并基于OLT内调制驱动组件产生的单路、双路或四路驱动电信号对下行光信号进行调制，经增益处理后，通过光引擎的光接口发射；
以及，所述光引擎的光接口接收的上行光信号进行光电转换以发送所述OLT的位于光引擎外部区域的突发模式接收放大芯片组进行处理；
所述光引擎中设置有第一方面任一所述的硅基光电子的收发集成芯片。
在第二方面的一种可能的实现方式中，所述光引擎的光接口用于接收上行光信号或发送下行光信号，所述光接口包括：单通道单纤双向的Simplex SC(Simplex，单纤双向；SC，Standard Connector标准连接器)接口和/或双通道单纤双向的双Simplex LC(Lucent Connector，朗讯连接器)接口；所述光接口用于SFP-DD/SFP-DD112封装方式的光模块。
在第二方面的一种可能的实现方式中，所述光引擎包括：
硅基光电子收发集成芯片、O波段激光器及驱动组件、O波段增益芯片及驱动组件、光接口、金手指阵列；
所述O波段激光器及驱动组件作为激光组件产生作为下行光源的激光信号；O波段增益芯片及驱动组件用于对硅基光电子的收发集成芯片输出的光信号进行增益处理，或者对光接口接收的上行光信号进行增益处理；金手指阵列用于传输光引擎与OLT中其他组件的电信号/驱动电信号；
其中，所述驱动电信号为一路驱动电信号时，所述O波段激光器及驱动组件为一个、O波段增益芯片及驱动组件为一个；
所述驱动电信号为两路驱动电信号时，所述O波段激光器及驱动组件为一个、O波段增益芯片及驱动组件为两个；
所述驱动电信号为两路驱动电信号时，所述O波段激光器及驱动组件为两个、O波段增益芯片及驱动组件为两个；
所述驱动电信号为两路驱动电信号时，所述O波段激光器及驱动组件为两个、O波段增益芯片及驱动组件为一个；
所述驱动电信号为四路驱动电信号时，所述O波段激光器及驱动组件为两个、O波段增益芯片及驱动组件为两个；
所述驱动电信号为四路驱动电信号时，所述O波段激光器及驱动组件为四个、O波段增益芯片及驱动组件为一个。
第三方面，一实施例还提供一种基于硅基光电子集成芯片的多速率的局端模块，所述局端模块为采用SFP-DD/SFP-DD112封装的模块，所述局端模块包括：电气接口、具有单/双/四路多速率组合的模拟/数字信号处理集成组件、光引擎和具有单/双/四路多速率组合的突发模式接收放大芯片组；
所述电气接口用于实现局端模块与系统板卡之间的电信号传输；
所述模拟/数字信号处理集成组件用于将系统板卡通过所述光模块电气接口传输的具有第一参数的下行电信号进行时钟数据恢复、速率和/或码型的变换处理，得到用于具有第二参数的电信号，该电信号用以施加在光引擎中硅基光电子集成芯片对应的光信号上实现光信号的调制，并将调制后的下行光信号通过所述光引擎的光接口传输网络端，
以及，借助于光引擎的光接口接收的上行光信号经由光引擎中硅基光电子集成芯片的接收转换成电信号；该电信号经突发模式接收放大芯片组和所述电气接口传输至所述系统板卡；
所述光引擎中硅基光电子集成芯片为对光信号实现收发一体的收发集成芯片。
在第三方面的一种可能的实现方式中，所述光引擎中硅基光电子集成芯片为上述第一方面任一所述的用于PON OLT系统的硅基光电子的收发集成芯片。
在第三方面的一种可能的实现方式中，所述光引擎为上述第二方面任一所述的用于PON OLT系统的光引擎。
在第三方面的一种可能的实现方式中，所述电气接口包括：SFP-DD/SFP-DD112封装的印刷电路板的金手指阵列；
所述突发模式接收放大芯片组包括：突发模式接收跨阻放大器和突发模式接收线性放大器；
所述具有第二参数的电信号为一路电信号时，所述突发模式接收放大芯片组输入输出突发模式电信号为一路，且该路突发模式接收放大芯片组的电信号速率等于或低于具有第二参数的电信号的速率，
所述用于具有第二参数的电信号为两路电信号时，所述突发模式接收放大芯片组输入输出突发模式电信号为两路，且两路突发模式接收放大芯片组电信号的速率不高于具有第二参数的电信号的速率；
所述用于具有第二参数的电信号为四路电信号时，所述突发模式接收放大芯片组输入输出突发模式电信号为四路，且四路突发模式接收放大芯片组电信号的速率不高于具有第二参数的电信号的速率。
在第三方面的一种可能的实现方式中，所述电气接口用以实现25/50/100/200G PON OLT系统和/或25/50/100/200G EPON OLT(Ethernet Passive Optical Network OLT，以太网标准无源光网络OLT)系统与局端模块之间的连接，且电气接口包括下述的接口的一种或多种：单路高速电接口、双路高速电接口和四路高速电接口。
在第三方面的一种可能的实现方式中，模拟/数字信号处理集成组件包括：数字处理芯片DSP和用于硅光光信号调制的调制驱动组件；
所述DSP用于按照光传输设备的参数对所述电气接口传输的单路或双路电信号即第一参数进行时钟数据恢复、速率和/或码型的映射转换，以得到符合光传输设备的传输参数要求的一路下行电信号，并通过调制驱动组件，得到一路驱动电信号即第二参数；
和/或，
数字处理芯片DSP和用于硅光光信号调制的调制驱动组件；
所述DSP用于按照光传输设备的参数对所述电气接口传输的双路电信号进行时钟数据恢复、速率和/或码型的映射转换等处理，以得到符合光传输设备的传输参数要求的双路下行电信号，并通过调制驱动组件， 得到双路驱动电信号即第二参数；
和/或，
数字处理芯片DSP和用于硅光光信号调制的调制驱动组件；
所述DSP用于按照光传输设备的参数对所述电气接口传输的四路电信号进行时钟数据恢复、速率和/或码型的映射转换等处理，以得到符合光传输设备的传输参数要求的单路下行电信号，并通过调制驱动组件，得到单路驱动电信号即第二参数；
和/或，
数字处理芯片DSP和用于硅光光信号调制的调制驱动组件；
所述DSP用于按照光传输设备的参数对所述电气接口传输的四路电信号进行时钟数据恢复、速率和/或码型的映射转换等处理，以得到符合光传输设备的传输参数要求的双路下行电信号，并通过调制驱动组件，得到双路驱动电信号即第二参数；
和/或，
数字处理芯片DSP和用于硅光光信号调制的调制驱动组件；
所述DSP用于按照光传输设备的参数对所述电气接口传输的四路电信号进行时钟数据恢复、速率和/或码型的映射转换等处理，以得到符合光传输设备的传输参数要求的四路下行电信号，并通过调制驱动组件，得到四路驱动电信号即第二参数；
和/或，
模拟/数字信号处理集成组件包括：双路retimer(重定时器)组件和用于光信号调制的调制驱动组件；
所述双路retimer组件用于按照光传输设备的参数对所述电气接口传输的双路电信号进行时钟数据恢复、速率和/或码型的映射转换，以得到符合光传输设备的传输参数要求的两路下行电信号，并通过调制驱动组 件，得到两路驱动电信号即第二参数；
和/或，
模拟/数字信号处理集成组件包括：四路retimer组件和用于光信号调制的调制驱动组件；
所述四路retimer组件用于按照光传输设备的参数对所述电气接口传输的四路电信号进行时钟数据恢复、速率和/或码型的映射转换，以得到符合光传输设备的传输参数要求的四路下行电信号，并通过调制驱动组件，得到四路驱动电信号。在实际应用中，四路速率可一致，如均可采用4x25Gbps、4x50Gbps、4x100Gbps的速率；或者，在其他实施例中，也可采用两两一致，如2x25Gbps+2x50Gbps的组合等，本实施例不对其限定，根据实际需要选择。
在第三方面的一种可能的实现方式中，DSP包括：Retimer组件、Gearbox(变速箱)组件、码型转换模块；
单路1x25Gbps或1x50Gbps NRZ或1x100Gbps PAM4码型输入时，DSP变速箱Gearbox组件不工作，单路Retimer组件将输入单路电信号进行时钟数据恢复，输出单路1x25Gbps NRZ或1x50Gbps NRZ或1x100Gbps PAM4码型作为下行电信号；
双路2x25Gbps NRZ码型输入时，经过Retimer组件、变速箱Gearbox组件将双路输入电信号2x25Gbps NRZ映射转换为单路50Gbps NRZ码型，以作为输出的一路下行电信号；
双路2x25Gbps NRZ码型输入时，经过Retimer组件、变速箱Gearbox组件和码型转换模块将双路输入信号2x25Gbps NRZ映射转换为单路50Gbps PAM4码型，以作为输出的一路下行电信号；
双路2x50Gbps NRZ码型输入时，经过Retimer组件、变速箱Gearbox组件将双路输入信号2x50Gbps NRZ映射转换为单路100Gbps NRZ码型， 以作为输出的一路下行电信号；
双路2x50Gbps NRZ码型输入时，经过Retimer组件、变速箱Gearbox组件和码型转换模块将双路输入信号2x50Gbps NRZ映射转换为单路100Gbps PAM4码型，以作为输出的一路下行电信号；
双路2x 100Gbps PAM4码型输入时，经过Retimer组件、变速箱Gearbox组件将双路输入信号2x 100Gbps PAM4映射转换为单路1x200Gbps PAM4码型，以作为输出的一路下行电信号。
在第三方面的一种可能的实现方式中，双路retimer组件包括：retimer芯片；
双路2x25Gbps NRZ码型输入时，retimer芯片用于将电气接口接收的双路的电信号各自进行时钟数据恢复，映射转换为双路的25Gbps NRZ码型，以作为输出的双路下行电信号；
双路采用不同速率方式输入时，一路为25Gbps NRZ码型，另一路为50Gbps NRZ码型，retimer或DSP芯片用于将电气接口接收的双路电信号各自进行时钟数据恢复，映射转换为一路为25Gbps NRZ、另一路为50Gbps NRZ码型，以作为输出的双路下行电信号；
双路2x50Gbps NRZ码型输入时，retimer或DSP芯片用于将电气接口接收的双路的电信号各自进行时钟数据恢复，映射转换为双路的2x50Gbps NRZ码型，以作为输出的双路下行电信号；
双路2x100Gbps PAM4码型输入时，retimer或DSP芯片用于将电气接口接收的双路的电信号各自进行时钟数据恢复，映射转换为双路的2x100Gbps PAM4码型，以作为输出的双路下行电信号。
在第三方面的一种可能的实现方式中，四路retimer或DSP组件包括：retimer芯片或DSP芯片；
四路4x25Gbps NRZ码型输入时，retimer芯片用于将电气接口接收 的四路的电信号各自进行时钟数据恢复，映射转换为四路的25Gbps NRZ码型，以作为输出的四路下行电信号；
四路4x25Gbps NRZ码型输入时，DSP芯片用于将电气接口接收的四路的电信号各自进行时钟数据恢复，映射转换为单路的100Gbps PAM4码型，以作为输出的单路下行电信号；
四路4x25Gbps NRZ码型输入时，DSP芯片用于将电气接口接收的四路的电信号各自进行时钟数据恢复，映射转换为双路的2x50Gbps NRZ或PAM4码型，以作为输出的双路下行电信号；
四路4x50Gbps NRZ码型输入时，retimer或DSP芯片用于将电气接口接收的四路的电信号各自进行时钟数据恢复，映射转换为四路的4x50Gbps NRZ码型，以作为输出的四路下行电信号；
四路4x50Gbps NRZ码型输入时，DSP芯片用于将电气接口接收的四路的电信号各自进行时钟数据恢复，映射转换为单路的200Gbps PAM4码型，以作为输出的单路下行电信号；
四路4x50Gbps NRZ码型输入时，DSP芯片用于将电气接口接收的四路的电信号各自进行时钟数据恢复，映射转换为双路的2x100GbpsPAM4码型，以作为输出的双路下行电信号；
采用2x25Gbps与2x50Gbps四路组合输入时，retimer或DSP芯片用于将电气接口接收的四路的电信号各自进行时钟数据恢复，映射转换为四路的2x25Gbps与2x50Gbps NRZ码型，以作为输出的四路下行电信号。
在第三方面的一种可能的实现方式中，调制驱动组件为硅光调制驱动组件，集成在DSP中，或，与retimer芯片集成在一个组件上。
第四方面，一实施例还提供一种无源光网络PON OLT系统，其特征在于，包括：上述第三方面任一所述的基于硅基光电子集成芯片的多速率的局端模块；所述系统通过所述局端模块与PON网络侧交互。
上述各实施例的技术方案的优势和效果：
1)各实施例的局端模块OLT中的光接口与现有SFP-DD/SFP-DD112MSA协议定义的四种光接口类型(Duplex LC(Duplex Lucent Connector，双纤双向朗讯接口)、MPO-12(Multi Fiber Push On 12，12通道多纤芯连接器)、MDC(Mini Duplex Connector，微型双纤双向连接器)、SN(SN Connector：SN连接器))不同，各实施例中是采用SFP-DD/SFP-DD112封装协议对OLT中Simplex SC光接口封装，使得Simplex SC光接口支持PON中光信号的单通道单纤双向(BiDi)传输；各实施例中还可采用相互独立的双通道Simplex LC光接口，使得PON OLT系统板卡的端口密度进一步加倍，实现更高密度的单纤双向传输特性。
2)各实施例的技术方案中，将当前高速小型化SFP-DD/SFP-DD112封装协议应用在于系统板卡交互的电气接口上，以支持下一代PON OLT系统的端口高密度、系统高性能需求。各实施例中的PON OLT系统助力运营商实现局端模块将接入网下行速率从目前XG(S)PON的10Gbps提升到25Gbps、50Gbps、100Gbps等的更高带宽；上行速率从10Gbps提升到25G或50Gbps。
3)各实施例的局端模块应用在PON OLT系统中可实现更高的板卡吞吐量。具体地，XG(S)PON OLT系统可支持16个10Gbps PON OLT SFP+光收发器(即局端模块/局端设备)。采用各实施例的单路电信号SFP-DD/SFP-DD112封装的电气接口的局端模块，PON OLT系统中插入的光收发器数量不变，而PON OLT系统中系统板卡总吞吐量(Throughput)提升至XG(S)PON板卡的2.5～20倍。
尤其是在双路电信号模式下，一张SFP-DD/SFP-DD112板卡等效32个SFP-DD/SFP-DD11225G/50G/100GPON的光收发器，系统板卡总吞吐 量进一步加倍达到XG(S)PON板卡最大吞吐量的5～20x。
在四路电信号模式下，一张SFP-DD/SFP-DD112板卡可插入16个SFP-DD/SFP-DD112100G/200G TWDM PON光收发器或等效32个SFP-DD/SFP-DD112 50G/25G Combo PON光收发器。
4)各实施例的局端模块可以实现灵活配置下行光信号的速率，兼容多更客户需求，以及兼容不同标准。
各实施例的PON OLT系统支持运营商根据自身客户业务需要、FTTx(Fiber to the Anything，光纤到任意地点)成本诉求、PONMAC ASIC(Application Specific Integrated Circuit，专用集成电路)速率和SERDES(Serializer/Deserializer：串行器解串器)速率，灵活配置下行光信号速率及相关服务。例如，可以支持十多种输入输出信号速率组合；各实施例的OLT/光收发器/局端模块采用的是兼容国内运营商与海外运营商的下一代PON不同速率需求及规划、国内设备商与国外设备商的不同速率需求、多个国际标准组织推进的下一代PON技术标准实现的结构。
5)各实施例的局端模块具备面向未来应用的开放和可扩展性。具体地，基于以太网速率的SFP-DD/SFP-DD112MSA(Multi Source Agreement多源协议)增加了对单路100G PAM4输入输出的支持。在未来PON MAC(Media Access Control，媒体接入控制层)SerDes升级至100Gbps速率时，各实施例的局端模块可平滑扩展至支持TDM(Time Division Multiplexing，时分复用)或TWDM(Time and WavelengthDivision Multiplexing，时分与波分复用)200G(E)PON、100G/50G或50G/25G Combo PON(组合无源光网络)。各实施例支持的多达13种以上高速率PON类型。
6)各实施例中的局端模块首次将基于硅基光电子集成芯片的光引擎应用于PON网络光连接。各实施例的局端模块中光引擎以集成硅基光电 子集成收发芯片(SiP:Silicon Photonics)替代传统的光电子混合集成BOSA封装，可有效规避采用数十颗分立高速光电芯片进行混合集成封装导致的工艺复杂度、提高产品良率、降低成本、降低光收发器总功耗、提升产品可靠性；并具有高性能、高集成度、高可靠性、适合小型化封装等特点，适用于未来更高性能更高端口密度PON OLT系统。
7)各实施例中局端模块所应用的硅基光电子集成芯片，其采用收发一体集成芯片方式实现，其中接收端采用低成本高性能GeSi PIN接收器，相比于传统PON采用APD(Avalanche Photo Diode，雪崩光电二极管)接收器，PIN接收机成本低、良率高、与发射端硅光工艺硅基MZ调制器工艺全兼容，可利用现有成熟的硅光工艺生产线一次流片即实现收发一体化集成芯片；无需升级现有硅光产业的加工制造设备和精度即能完成关键硅光集成芯片的生产制造。
8)局端模块中，与SiP集成的O波段增益芯片对局端模块(即光收发器)的发射侧大功率光信号和接收侧小功率光信号同时进行放大；针对GeSi PIN自身接收灵敏度不如APD接收灵敏度高且PON上行信号经长距传输可能已衰减至低于PIN接收器灵敏度的缺陷，各实施例的局端模块采用集成O波段增益芯片(Gain Chip)放大接收信号以满足锗硅PIN接收器自身灵敏度要求，且补偿不同波长光信号在不同超高速率下传纤所带来的高色散代价。即，采用PIN+Gain Chip集成方式替代传统的APD，并应用于下一代PON光网络，是兼顾满足技术标准、优化光收发器光引擎成本、兼容现有成熟硅光工艺等多因素综合考虑的结果。
综上，各实施例中的无源光网络PON采用的OLT局端设备支持小型化的SFP-DD/SFP-DD112封装，有效支持下一代OLT系统设备的端口高密度、高性能需求。相应地，在PONOLT系统中可允许保持现有一张PON板卡16个可插拔光收发器端口的构型，板卡端口密度不变，而板卡吞吐 量提升至当今10GPON板卡的2.5～20x。进一步地，各实施例中SFP-DD/SFP-DD112电气接口的双排金手指分布可向下兼容SFP28/SFP56/SFP112的单排金手指，还可灵活重定义其金手指阵列使之兼容两组Combo PON，从而实现了多速率通道的兼容。
附图说明
图1至图3分别为一实施例中硅基光电子收发集成芯片的示意图；
图4至图6分别为另一实施例中的光引擎的示意图；
图7为现有技术中SFP-DD/SFP-DD112MSA定义的光接口类型的示意图；
图8为另一实施例中使用的单通道Simplex SC光接口和双通道SimplexLC接口的示意图；
图9至图11为另一实施例中局端模块的功能架构示意图；
图12至图14为局端模块所应用的PON OLT系统的架构示意图；
图15和图16分别为另一实施例中硅基光电子收发集成芯片和所属光引擎的示意图。
附图标记说明
A1、硅基光电子的收发集成芯片A2、光引擎
1、PON MAC ASIC2、电气接口/应用SFP-DD/SFP-DD112协议的电气接口
3、DSP/数字处理芯片4、硅光调制驱动器
5、硅光调制器6、O波段大功率半导体激光器
7、硅光耦合器8、硅光合分波器
9、O波段增益芯片10、SimplexSC光接口或Simplex LC光接口
11、硅光PIN接收器12、SOA驱动器
14、突发模式跨阻放大器/BM-TIA15、突发模式线性放大器/BM-LA
16、突发模式时钟数据恢复SerDes/BM CDR SERDES
17、微处理器18、EEPROM
19、光收发器电源20a、20b、20c和20d、硅光芯片片上光监测器
21a、21b、21c、21d：片上波导22、大功率半导体激光器驱动器
23、电源管理组件24、硅基分光器/硅基1:2分光器
25a、25b和25c、微透镜26、金手指阵列。
具体实施方式
为了更好的解释技术方案，以便于理解，下面结合附图，通过具体实施方式，对技术方案作详细描述。下述描述的技术方案均不对技术方案进行限定，仅为举例说明，便于理解，其提供相对应的附图进行说明。
当前全球接入网络，处于从GPON向10G(S)PON过渡阶段，也正值下一代PON技术开发和选择的关键时机。下一代PON技术的速率为50G、100G的高速PON。各标准协议组织使用的25Gbps、50Gbps的概念中存在稍许差别，如25G(S)PON MSA和ITU-T 50GPON沿袭ITU-T(International Telecommunication UnionTelecommunication Standardization Sector，国际电信联盟电信标准化分部)速率的历史传统，其25Gbps、50Gbps实为24.8832Gbps、49.7664Gbps，采用NRZ编码。而IEEE标准的25Gbps、50Gbps实为25.78125Gbps、2x25.78125Gbps NRZ编码，沿袭以太网速率传统。上述细微的差别代表不同标准组织对产业链未来方向的判断以及通过标准引领产业链的不同立场，同时也造成产业链分化。比如PMA(Physical Media Attachment，物理媒介适配层)和PMD(Physical Media Dependent，物理媒介依赖层)层已有成熟完整的光电芯片产业链支持以太网标准的25.78125Gbps NRZ。对于基于以太网速率的EPON应用，除个别关键电芯片尚需补齐，实现IEEE25G/50G-EPON物理层的基本单元已完备，技术跨度不大，目前难点集中 在应用需求以及实现小型化、低功耗封装以支持50G-EPON所需的两对25G不同波长收发芯片组。由于以太网产业链在后25G时代SerDes速率已为采用PAM4码型的56G PAM4(28G Baud)和112G PAM4(56G Baud)，光口信号速率为采用PAM4码型的53.125Gbps(亦简称50Gbps)和106.25Gbps(亦简称100Gbps)，可以预期后50G-EPON时代的IEEE PON标准会采用PAM4码型信号，与ITU-T50GPON采用NRZ码型的方式进一步分化。
在GPON和XG(S)PON时代，SFP(Small Form-factor Pluggable，小型化可插拔)及SFP+是光收发器采用的典型封装方式，该封装方式允许一张OLT板卡容纳16个光收发器。此外，当前高密度高性能OLT系统机框可插入17张甚至更多这样的板卡。行业尚未针对下一代更高性能、更高密度OLT系统采用何种封装的光收发器达成共识。而过去10年光通信网络技术及应用发展最快的板块是超大规模数据中心(Hyper Scale Data Center)。源于支持数据中心内高密度高性能低功耗低成本光互连，新一代基于SFP的SFP-DD/SFP-DD112MSA协议定义了四种光纤接口类型(Duplex LC(如图7中(a)所示)、MPO-12(如图7中(b)所示)、MDC(如图7中(d)所示)、SN(如图7中(c)所示)。遵循该多源协议的SFP-DD/SFP-DD112光收发器可灵活支持电口单(1x)或双(2x)路25G NRZ、56G PAM4(28GBaud)、112G PAM4(56GBaud)等SerDes速率和光口1x25Gbps至2x100Gbps以太网速率。
各实施例涉及光通信网络采用的是下一代无源光网络技术，各实施例的光收发器即局端模块中采用SFP-DD/SFP-DD112封装、硅基光电子收发集成芯片Silicon Photonics(SiP)和数字信号处理芯片DSP(或retimer)、光接口采用单通道Simplex SC接口(如图8中的(a)所示)或双通道Simplex LC接口(如图8中的(b)所示)，实现下行 25G/50G/100G/200GbpsNRZ或PAM4信号，上行突发模式25G/50G/100Gbps NRZ或PAM4信号、支持下一代高性能高密度25G(S)PON Multi Source Agreement(MSA：多源协议)、ITU-T 9804.3 50GPON、IEEE 802.3ca(2020)50G-EPON等标准协议，并面向未来100G/200GPON应用进行扩展。
各实施例的SFP-DD/SFP-DD112电气接口可采用单路高速电信号收发，可采用双路高速电信号收发，还可借鉴SFP+Combo PON定义的电气接口金手指的方式，重新定义SFP-DD/SFP-DD112双排金手指以实现支持总共四路高速电信号收发。以四路电信号方式为例，该四路高速信号可采用同一速率每一路光信号波长不同，实现Simplex SC光接口的100G/200G TWDM(Time and Wavelength Division Multiplexing，时分与波分复用)PON；也可实现四路高速电信号采用同一速率而四路光信号两两一组、每组的两路光信号波长不一样、组间波长方案一致，以此实现双通道Duplex LC光接口的双密度50G/100G PON；当四路高速电信号也分为两路一组，组内两路速率不一时，可支持双密度Combo PON。如一路50G与一路25G为一组，可在SFP-DD/SFP-DD112光收发器上实现双通道的50G/25G Combo PON，且每个50G/25G Combo PON光路端口采用Simplex LC接口。
下述各实施例中的下行是指发射TX，上行是指接收RX，用于传输光信号的接口均为光接口。各实施例的局端模块即为OLT、OLT收发器等，各实施例的描述中单路指一路光信号或电信号，双路指两路光信号或电信号，四路指四路光信号或电信号；单通道指光引擎光接口为一个光纤接口，此接口可以同时收发最少两路不同波长的光信号；双通道指光引擎光接口为两个光纤接口，每接口可以同时收发最少两路不同波长的光信号。
实施例一
本实施例提供一种用于PON OLT系统的硅基光电子的收发集成芯片，所述收发集成芯片位于OLT的光引擎中，且实现收发一体的集成芯片，所述收发集成芯片基于OLT前端单路、双路或四路的驱动电信号对光信号进行调制，调制后的下行光信号经过光引擎的增益处理后经由光引擎的光接口发射；
以及，所述收发集成芯片对光引擎的光接口接收的上行光信号进行光电转换以发送所述OLT的位于光引擎外部区域的突发模式接收放大芯片组进行处理。
本实施例中的硅基光电子的收发集成芯片可为采用一次流片工艺制成的包括有硅光耦合器、硅光调制器、硅光合分波器、硅光PIN接收器的收发集成一体的芯片，其在实际的光路传输中还对应有硅光波导、硅光监测器等组件，具体可参照图1至图3、图15、图16所示。
在具体应用中，收发集成芯片接收的驱动电信号为一路驱动电信号，则调制后的下行光信号为一路下行光信号；
收发集成芯片接收的驱动电信号为两路独立的驱动电信号，则收发集成芯片基于每一路驱动电信号对光信号进行调制，调制后的下行光信号为两路下行光信号；
所述光接口接收的上行光信号为一路上行光信号，则所述收发集成芯片对一路上行光信号进行光电转换并输出一路转换后的电信号；
所述光接口接收的上行光信号为两路上行光信号，则所述收发集成芯片对两路上行光信号分别进行光电转换并输出转换后的两路独立的电信号。
所述驱动电信号为四路独立的驱动电信号，则收发集成芯片基于每一路驱动电信号对光信号进行调制，调制后的下行光信号为四路下行光 信号；相应地，所述光接口接收的上行光信号为四路上行光信号，则所述收发集成芯片对四路上行光信号分别进行光电转换并输出转换后的四路独立的电信号。
如图1所示，本实施例的硅基光电子的收发集成芯片A1可包括：硅光耦合器7、硅光调制器5、硅光合分波器8、硅光PIN接收器11；
针对下行信号的传输，所述硅光耦合器7接收所述光引擎A2中激光组件发出的作为下行光源的激光信号，所述下行光源经由光路传输进入到硅光调制器5进行调制，所述硅光调制器5所述驱动电信号对下行光源进行调制，得到调制后的光信号；
调制后的光信号经光路传输至硅光合分波器8以输出至所述光引擎A2，以使光引擎进行增益处理并经所述光接口进行下行传输；
针对上行信号的传输，经所述光接口接收的上行光信号在光引擎A2中增益放大后经硅光合分波器8进入所述硅光PIN接收器11进行光电转换以输出。
在图1所示的硅基光电子的收发集成芯片可实现一路驱动电信号的调制处理，也是本实施例中核心创新的基本组成单元。另外，图1中光传输过程中也设置有硅光监测器即硅光芯片片上光监测器如20a、20b、20c，该监测器和现有光传输的监测器功能一致，本申请中是集成在收发集成芯片上实现光传输。另外，硅光波导即片上波导21a、21b、21c和21d也是和现有光波导功能一致，本实施例中集成在收发集成芯片上实现光传输。
在另一种可能的实现方式，如图2所示，本实施例的硅基光电子的收发集成芯片A1可包括：一个硅光耦合器7、一个硅基分光器24、两个硅光调制器5、两个硅光合分波器8、两个硅光PIN接收器11；
针对下行的两路驱动电信号，硅光耦合器7接收所述光引擎A2中激 光组件发出的作为下行光源的激光信号，所述下行光源经由硅基分光器24进行分光处理，形成两路下行光源；
每一路下行光源经光路传输进入到各自对应的硅光调制器5进行调制，每一个硅光调制器5基于一路驱动电信号对该路的下行光源进行调制，得到调制后的一路光信号；此时两路下行光源的波长是一致的，图2中示出的是一个激光组件产生作为下行光源的激光信号，经由硅基1:2分光器分为两路光信号。
调制后的两路光信号分别经光路传输至各自的硅光合分波器8以分别输出至所述光引擎A2，以使光引擎A2的两个增益组件对两路输出分别进行增益处理并经所述光接口进行两路光信号的下行传输。
针对上行的光信号，经所述光接口接收的两路上行光信号在光引擎的两个增益组件中分别进行增益放大后进入各自的硅光合分波器处理后经光路传输至各自的硅光PIN接收器进行光电转换，每一个硅光PIN接收器输出一路转换后的电信号。
图2中的硅基光电子的收发集成芯片可应用速率方面采用时分复用方式的ITU-T 50GPON、未来的100GPON，以及采用ITU-T PON速率的25G(S)PON MSA协议的各设备中，并通过硅光分光器实现在图1基础上的两个独立光学通道，助力光引擎实现双通道的单纤双向传输。
在第三种可能的实现方式，如图3所示，硅基光电子的收发集成芯片包括：两个硅光耦合器7、两个硅光调制器5、一个硅光合分波器8、两个硅光PIN接收器11；
针对下行的两路驱动电信号，每一个硅光耦合器7接收所述光引擎A2中对应激光组件发出的作为下行光源的激光信号，此时，各路对应的激光信号波长不一样。图3中存在两个激光组件，每一激光组件发出一个波长的激光信号，两路激光组件可发出两个波长的激光信号如λ DS0和 λ DS1。
每一路下行光源经由光路传输进入到各自对应的一个硅光调制器5进行调制，每一个硅光调制器5基于一路驱动电信号对该路的下行光源进行调制，得到调制后的一路光信号；
调制后的两路光信号经光路传输至一个硅光合分波器8，合波后通过硅光合分波器8的一个端口输出两路下行光信号至所述光引擎A2，以使光引擎的一个增益组件对两路输出进行增益处理并经所述光接口进行两路光信号的下行传输。
针对上行的两路驱动电信号，经所述光接口接收的两路上行光信号(该光信号可以是波长不同的光信号，如上行λ US0和上行λ US1)通过光引擎的一个增益组件增益放大，再经硅光合分波器8处理后成为两路空间分离的上行光信号，每一路上行光信号经光路传输至各自的硅光PIN接收器进行光电转换，每一个硅光PIN接收器输出一路转换后的电信号。
具体地，基于图3所示的结构，IEEE 50G-EPON 2x25Gbps信号速率和NRZ编码，并采用O波段双下行波长和双上行波长方式实现2x25Gbps总共50Gbps的收发传输，涉及共四个波长的信号：1342±2nm、1358±2nm、1270±10nm、1300±10nm。这四个波长可通过一个O波段增益芯片放大，光引擎设计更简洁。特别地，上行光信号的波长和下行光信号的波长不同，故在图3中采用不同深度的线条示出。
基于上述的图1至图3的收发集成芯片的结构，任意光路传输中还设置有用于光路传输的硅光波导(如各图中示出的21a、21b、21c、21d等片上波导)、硅光监测器(如各图中示出的20a、20b、20c、20d等硅光芯片上的光监测)。本实施例的硅光波导、硅光监测器用于对光路传输的光信号进行传输和监测。硅光片上光监测：监测片上各器件节点光信号，硅光片上波导：用于在硅基光电子集成芯片上实现高速光信号传 输。
本实施例局端模块所应用的硅基光电子集成芯片，其采用收发一体集成芯片方式实现，其中接收端采用低成本高性能锗硅PIN接收器，相比于传统PON采用APD接收器，PIN接收机成本低、良率高、与发射端硅光工艺硅基MZ调制器工艺全兼容，可利用现有成熟的硅光工艺生产线一次流片即实现收发一体化集成芯片；无需升级现有硅光产业的加工制造设备和精度即能完成关键硅光集成芯片的生产制造。
在第四种可能的实现方式中，本实施例还提供一种针对四路驱动电信号的收发集成芯片，如图15所示的大矩形框内的结构，硅基光电子的收发集成芯片架构用于双通道100G/200G EPON OLT光收发器或双通道50G/25G Combo PON，其具有两个下行波长、两个上行波长、双通道Simplex LC接口、两个增益芯片、两个激光器。具体地，该收发集成芯片包括：
两个硅光耦合器、两个硅基分光器、四个硅光调制器、两个硅光合分波器、四个硅光PIN接收器；
两个硅光耦合器分别接收所述光引擎中两个激光组件发出的作为下行光源的激光信号(两激光信号波长不一样，即图15中λ DS0和λ DS1波长不同，存在两组λ DS0和两组λ DS1)，所述下行光源经由硅光分光器进行分光处理，形成四路下行光源，其中两两波长一致；特别说明的是，调制信号也是四组，TX1至TX4。此收发集成芯片的每个硅光合分波器需支持两下行两上行共四个不同波长光信号的合分波。每一路下行光源经光路传输进入到各自对应的硅光调制器进行调制，每一个硅光调制器基于一路驱动电信号对该路的下行光源进行调制，得到调制后的一路光信号；
调制后的四路光信号分别经光路传输至硅光合分波器，且两路不同波长光信号为一组，一共两组分别通过两个硅光合分波器输出至所述光 引擎，以使光引擎的两个增益组件对两组四路光信号输出分别进行增益处理并经所述双通道Simplex LC光接口进行四路光信号的下行传输；
以及，经所述双通道Simplex LC光接口接收的四路上行光信号分为两组，每组由两路上行波长为λ US0和λ US1的光信号组成。在光引擎的两个增益组件中分别进行增益放大后进入各自的硅光合分波器处理后经光路传输至各自的硅光PIN接收器进行光电转换，每一个硅光PIN接收器输出一路转换后的电信号(如RX1至RX4(Receiving接收))。
也就是说，驱动电信号为四路独立的驱动电信号，则收发集成芯片基于每一路驱动电信号对光信号进行调制，调制后的下行光信号为四路下行光信号；相应地，在光接口接收的上行光信号为四路上行光信号，则收发集成芯片对四路上行光信号分别进行光电转换并输出转换后的四路独立的电信号。
在第五种可能的实现方式中，本实施例还提供一种针对四路驱动电信号的收发集成芯片，如图16所示的大矩形框的结构，硅基光电子的收发集成芯片架构用于100G/200G TWDM-PON OLT光收发器，其可具有四个下行波长、四个上行波长、一个Simplex SC接口、一个O波段增益芯片、四个O波段激光器。具体地，该收发集成芯片包括：
四个硅光耦合器、四个硅光调制器、一个硅光合分波器、四个硅光PIN接收器；
每一个硅光耦合器接收所述光引擎中对应激光组件发出的作为下行光源的激光信号，所述下行光源经由光路传输进入到各自对应的一个硅光调制器进行调制，每一个硅光调制器基于一路驱动电信号对该路的下行光源进行调制，得到调制后的一路光信号；
调制后的四路光信号经光路传输至一个硅光合分波器合并进入一个片上波导以输出四路下行光信号至所述光引擎，以使光引擎的一个增益 组件对四路输出进行增益处理并经所述光接口进行四路光信号的下行传输。需要说明的是，因为光引擎中使用四个激光器，其产生四个下行光波长，λ DS0、λ DS1、λ DS2、λ DS3。此收发集成芯片的硅光合分波器需支持四下行四上行共八个不同波长光信号的合分波。
当然，经所述光接口接收的四路上行光信号在光引擎的一个增益组件中进行增益放大后经一路硅光合分波器处理后依不同波长进入四个不同片上波导成为空间上分离的四路上行光信号(如图16中的λ US0、λ US1、λ US2、λ US3)，每一路上行光信号经光路传输至各自的硅光PIN接收器进行光电转换，每一个硅光PIN接收器输出一路转换后的电信号。
举例来说，上述各实施例的硅光合分波器可与硅光集成芯片的其它功能：如片上波导、硅光调制器、硅光接收器、分光器等实现单片集成。
本实施例的局端模块中光引擎以集成硅基光电子集成收发芯片(SiP)替代传统的光电子混合集成BOSA封装，可有效规避采用数十乃至上百颗分立高速光电芯片进行混合集成封装导致的工艺复杂度、提高产品良率、降低成本、降低光收发器总功耗、提升产品可靠性；并具有高性能、高集成度、高可靠性、适合小型化封装等特点，适用于未来更高性能更高端口密度PON OLT系统。
由此，使得使用上述收发集成芯片的局端模块对应的板卡，可在四路电信号模式下，基于SFP-DD/SFP-DD112封装的一张板卡可插入16个SFP-DD/SFP-DD112100G或200G TWDM PON光收发器或等效32个SFP-DD/SFP-DD112 100G/50G或50G/25G Combo PON光收发器，提高吞吐量，实现灵活配置下行光信号的速率，兼容多更客户需求，以及兼容不同标准。
上述实施例可面向未来应用的50G/100G/200G OLT可插拔PON光模块，且可采用速率组合(Combo)方式(如同一OLT光模块中下行发射 可采用25G+50G两路不同速率组合、50G+100G两路不同速率组合等方式，无需采用同一速率)，故OLT模块中必须设有处理25G/50G/100Gbps多路多种速率突发模式接收放大芯片组；借助于突发模式接收放大芯片组实现对家庭光猫ONU的各种突发数据的处理。
实施例二
本实施例提供一种用于PON OLT系统的光引擎，本实施例的光引擎均应用于PON网络光连接，该光引擎可插拔式连接PON光收发模块即光模块，下属实施例的光模块插于PON OLT系统面板上的阵列插槽中，进而实现PON网络光连接。这样可以有效实现集成度高，封装小，解决了现有混合封装叠装组合结构带来的成本高，封装难的问题。
所述的光引擎位于采用SFP-DD/SFP-DD112协议的OLT模块即光收发器中，并基于OLT前端单路、双路或四路的驱动电信号对光信号进行调制和增益处理，以通过光引擎的光接口发射；
以及，所述光引擎的光接口接收的上行光信号进行光电转换以发送所述OLT的位于光引擎外部区域的突发模式接收放大芯片组进行处理；本实施例中的光引擎中设置有实施例一种任意描述的硅基光电子的收发集成芯片(如图1至图3、图15和图16所示)。
该收发集成芯片基于OLT前端单路或双路的驱动电信号对光信号进行调制，调制后的下行光信号经过光引擎的增益处理后经由光引擎的光接口发射；以及，所述收发集成芯片对光引擎的光接口接收的上行光信号进行光电转换以发送所述OLT的位于光引擎外部区域的突发模式接收放大芯片组进行处理。
在本实施例中，光引擎以集成硅基光电子集成收发芯片(SiP)替代传统的光电子混合集成BOSA封装，可有效规避采用多颗分立高速光电芯片进行混合集成封装导致的工艺复杂度、提高产品良率、降低成本、 降低光收发器总功耗、提升产品可靠性；具有高性能、高集成度、高可靠性、适合小型化封装等特点，适用于未来更高性能更高端口密度PON OLT系统。
在实际应用中，本实施例光引擎A2中的光接口可用于接收上行光信号或发送下行光信号，例如，光接口可包括：单通道单纤双向的Simplex SC接口和/或双通道单纤双向传输的双Simplex LC接口；如图8所示。
且所述光接口为采用SFP-DD/SFP-DD112模块封装的接口。
可理解的是，当前光接口与现有SFP-DD/SFP-DD112MSA协议定义的四种光接口类型(Duplex LC、MPO-12、MDC、SN，如图7所示)不同，本实施例中是采用SFP-DD/SFP-DD112封装协议对OLT中Simplex SC光接口封装，使得Simplex SC光接口支持PON中光信号的单通道单纤双向(Bi-Direction，简称BiDi)传输，同时本实施例中还可采用SFP-DD/SFP-DD112封装协议对双通道Simplex LC光接口封装，使得双通道Simplex LC光接口支持多端口高密度PON OLT系统单纤双向传输特性。
图4至图6中所示的光接口为单通道Simplex SC或双通道Simplex LC(Bi-Direction)光接口。双通道Simplex LC PON光收发器支持更高密度更高性能的OLT系统：在保持PON MAC Serdes速率不变前提下，可使PON板卡总吞吐量相比于使用单通道SC光接口光模块的PON板卡总吞吐量加倍，比如原一张PON板卡最高支持16个SC端口(通道)SFP系列PON OLT光收发器，现可支持可容纳32个高速LC光接口PON收发通道。当PON MAC SerDes速率未来升级到100Gbps(PAM4)时，此方案可平滑支持双端口2x100GPON。
具体地，参见图4至图6所示，本实施例中光引擎A2主要包括：O波段激光器及驱动组件(如O波段大功率半导体激光器6、大功率半导 体激光器驱动器22)、O波段增益芯片及驱动组件(O波段增益芯片9、SOA驱动器12)、光接口(如SimplexSC光接口10)、金手指阵列26；
在光引擎A2的信号发送和接收过程中，O波段激光器及驱动组件作为激光组件产生作为下行光源的激光信号；O波段增益芯片及驱动组件用于对硅基光电子的收发集成芯片输出的光信号进行增益处理，或者对光接口接收的上行光信号进行增益处理；金手指阵列用于传输光引擎与OLT中其他组件的电信号/驱动电信号。
如图4所示，OLT前端的驱动电信号为一路驱动电信号时，所述O波段激光器及驱动组件为一个、O波段增益芯片及驱动组件为一个；此单路激光器入射单路输出的方式，可用于25G(S)PON、ITU-T 50GPON，或未来更高速率的单路100GPON。
如图5所示，OLT前端的驱动电信号为两路驱动电信号时，所述O波段激光器及驱动组件为一个、O波段增益芯片及驱动组件为两个；此单路激光器入射双路输出的方式是将一路光源信号在硅光芯片上以1:2方式分为两路独立光信号，用于密度加倍的25G(S)PON、ITU-T 50GPON，或未来更高速率的单路100GPON。
图5中光引擎可用一个大功率半导体激光器在SiP芯片上通过硅基分光器24，即硅基1:2分光器/1:2分光器将信号分成两路，并在片上分别实现信号高速调制、合分波、发射、接收。为更好的示出光传输过程，在图5中示出微透镜25a和25b，其实现增益处理的光信号传输至光接口。图5和图6中对上行和下行光信号传输的过程分别采用弯曲箭头示出各自的片上光导即在光信号传输中均对应有各自的片上波导,以及各自光监测器20a至20b，如实心的圆圈示出的结构。
如图6所示，OLT前端的驱动电信号为两路驱动电信号时，所述O波段激光器及驱动组件为两个(如图6中的一个大功率半导体激光器驱 动器、用于发出λ DS0激光波长的第一个O波段大功率激光器和用于发出λ DS1激光波长的第二个O波段大功率激光器)、O波段增益芯片及驱动组件为一个，及一个微透镜25。图6中光引擎的光接口也是接收两个波长光信号，经过硅光合分波器之后分为上行光信号λ US0和上行光信号λ US1进入各自的硅光PIN接收器。
特别说明的是，图6所示的光引擎的调驱动制信号也是两个，如图6中所示的TX1和TX2。
此时，光引擎所属的OLT光收发器可用于基于2x25G的IEEE50G-EPON系统。当两路驱动电信号速率不一样时，如一路50Gbps，另一路25Gbps，可实现50GPON/25G Combo PON。进一步地，这两个不同速率电信号可通过SFP-DD/SFP-DD112光收发器金手指阵列的单排实现：每排各设置一对25Gbps和50Gbps信号；也可通过双排分别实现：第一排金手指阵列安排两路25Gbps信号、第二排金手指阵列安排两路50Gbps。更进一步，基于这样的2x25Gbps与2x50Gbps电信号组合，结合图15和图16的硅光集成芯片，可以在一个SFP-DD/SFP-DD112光收发器实现两组50G/25G的Combo PON。
图6所示的结构对光电芯片封装的集成度提出了更高的要求，相比图4所示的单通道光引擎需多集成一套高速光电芯片，在SFP有限空间下的集成度更高。而图15和图16所示结构的集成度比图6所示集成度更提高了至少一倍。本实施例中，利用硅基光电子集成SiP技术可在一块小面积硅芯片上集成多种多粒(数十至上百颗)硅(锗)器件、光耦合器、高速调制器、合分波器、光互连波导、高速PIN接收器、1:2光功率分光器、片上光功率动态监测器等，适合面向高性能、高密度、低功耗下一代PON应用的SFP-DD/SFP-DD112小型化封装。
本实施例在仅使用DSP的retimer功能或仅使用独立retimer芯片时， 光收发器可支持基于以太网速率的IEEE 802.3ca 50G-EPON。该标准基于双波长25G以实现50G。此情况两路分别采用不同波长，下行波长分别为1342nm±2nm和1358nm±2nm，光引擎集成不同波长激光器，双激射波长通过硅光耦合器进入SiP芯片。此实施例中不使用1:2分光器，且接收端波长分别为为1270nm±10nm和1300±10nm。具体实现过程中不同波长的收发带来设计、工艺、封装复杂性，可以有效地通过硅基光电子集成芯片方式解决。当双路电信号速率不一致时，本实施例可用于支持Combo PON：如当两路电信号速率分别为50Gbps和25Gbps时，此光收发器可支持未来50G/25G Combo PON。当SerDes速率升级到28GBAUD(56G PAM4)或56GBAUD(112G PAM4)速率时，本实施例的光收发器可平滑支持未来单端口双波长100G-EPON或200G-EPON。
在其他的拓展实施例中，OLT前端的驱动电信号为两路驱动电信号时，所述O波段激光器及驱动组件为两个、O波段增益芯片及驱动组件为两个；即双入射双输出的结构。
当然，在驱动电信号为四路驱动电信号时，所述O波段激光器及驱动组件为两个、O波段增益芯片及驱动组件为两个，如图15所示。
所述驱动电信号为四路驱动电信号时，所述O波段激光器及驱动组件为四个、O波段增益芯片及驱动组件为一个。如图16所示。
上述各结构可根据实际的需要进行调整。
结合图4至图6所示出的结构可知，硅光调制器5，高速调制来自硅光耦合器进入硅光芯片的CW(Continuous Wave:连续波)激光信号，并将高速调制光信号经硅光片上波导发送至硅光合分波器8。
O波段大功率半导体激光器6：输出满足协议波长要求的发射端激光信号；
硅光耦合器7：用于将O波段大功率半导体激光器发生的激光信号 耦合至收发集成芯片A1；
硅光合分波器8：硅光集成片上双波滤波器(合分波器)：来自硅光调制器5和电气接口2的发射信号经此耦合进入O波段增益芯片9；
O波段增益芯片9：发射(下行λ DS)和接收(上行λ US)不同波长的o-波段光信号经此增益芯片同时被放大。其中下行λ DS通过自由空间及微透镜耦合至SFP-DD光收发器的SimplexLC光接口10，上行λ US通过自由空间及透镜耦合至O波段增益芯片9；
Simplex LC光接口10：下行λ DS经此接口耦合进入传输光纤；上行λ US经此接口进入收发器并通过自由空间及透镜(如微透镜25c)耦合至硅光合分波器8。
硅光PIN接收器11：下行λ DS经片上波导进入此PIN接收器；
SOA(Gain Chip)驱动器12：设置O波段增益芯片9的工作点；
微型TEC控制器(图中未标出)：用于实现微型温度控制，将SiP温度控制在一定范围，防止高温下O波段大功率半导体激光器性能下降、硅光合分波器性能随温度漂移。
大功率半导体激光器驱动器22：用于设置O波段大功率半导体激光器的最优工作点。
上述支持PON应用的硅光耦合器、硅光合分波器、硅光调制器、硅光PIN接收器、片上监测器、片上波导是通过一次流片在硅基材料上实现多种功能器件的硅基光电子单片集成，大大提升了高速光电子芯片的集成度，提高了可靠性和生产良率；而O波段CW大功率半导体激光器、O波段增益芯片是通过异质集成方式与SiP实现光耦合。
当下行电信号为25Gbps时，与上行突发模式25Gbps构组成对称单通道25G(S)PON工作模式，可支持海外设备商(如Nokia)牵头的25G(S)PON多源协议，并适用于大型海外运营商(AT&T等)的下一代 高速PON网络；通过2:1gearbox(模拟/数字信号处理集成组件功能之一)使能采用25G PON MAC的海外设备商和运营商在无需升级MAC及SerDes速率的情况下，平滑实现PMD层支持50G(S)PON。当下行50Gbps时，与上行25Gbps(或50Gbps)构成50G(S)PON工作模式，支持ITU-T50GPON标准和国内三大运营商选取的下一代高速PON技术路径。
实施例三
本实施例提供一种基于硅基光电子集成芯片的多速率的局端模块，该局端模块为采用SFP-DD/SFP-DD112封装的模块，所述局端模块包括：电气接口、具有单/双/四路多速率的模拟/数字信号处理集成组件、光引擎和突发模式接收放大芯片组；
所述电气接口用于实现局端模块与系统板卡之间的电信号传输；
所述模拟/数字信号处理集成组件用于将系统板卡通过所述电气接口传输的具有第一参数的下行电信号进行时钟数据恢复、速率和/或码型的变换处理，得到用于具有第二参数的电信号，该电信号用以施加在光引擎中硅基光电子集成芯片对应的光信号上实现光信号的调制，并将调制后的下行光信号通过所述光引擎的光接口传输网络端，
以及，借助于光引擎的光接口接收的上行光信号经由光引擎中硅基光电子集成芯片的接收转换成电信号；该电信号经突发模式接收放大芯片组和所述电气接口传输至所述系统板卡；
所述光引擎中硅基光电子集成芯片为对光信号实现收发一体的收发集成芯片。
在具体应用中，局端模块的光引擎中硅基光电子集成芯片为上述实施例一种任意所述的用于PON OLT系统的硅基光电子的收发集成芯片。当然，上述的光引擎还可为上述实施例二中任意所述的用于PON OLT系统的光引擎。其对应描述参见上述实施例一和实施例二的描述，该处不 再重复。
此外，本实施例的SFP-DD实现双通道Simplex LC光接口(双通道BiDi)高速PON对光芯片集成度提出的更高的挑战，相比于单通道情景，支持PON应用的光电芯片需要两套甚至四套，采用混合集成分立器件的传统光引擎封装方式难以将所有器件都放入SFP-DD光收发器内。而利用硅基光电子集成芯片可在一块小芯片上即实现这些功能器件及其互相的连接。如用的硅光耦合器、硅光合分波器、硅光调制器、硅光PIN接收器、片上监测器、片上波导均需两套，并增加了硅光分路器，这些可通过一次流片在硅基材料上实现单片集成芯片SiP。
另外，本实施例局端模块中电气接口可包括：SFP-DD/SFP-DD112封装的印刷电路板的金手指阵列，即SFP-DD/SFP-DD112封装的电气接口2。本实施例的电气接口用以实现25/50/100/200G PON OLT系统和/或50/100/200G EPON OLT系统与局端模块之间的连接，且电气接口包括下述的一种或多种：单路电接口、双路电接口和四路电接口。如图12中所示的系统板卡中的PON MAC ASIC 1经由SFP-DD/SFP-DD112封装的电气接口2进入到局端模块，并经由数字处理芯片3和硅光调制驱动器4处理，再输出至光引擎A2进而通过光接口输出；相应地，光接口接收的上行光信号经过光引擎转换为上行电信号，经由突发模式跨阻放大器BM-TIA 14和突发模式线性放大器BM-LA 15之后，借助于电气接口2输出至系统板卡中的突发模式CDR SERDES16，再进一步进入到PON MAC ASIC 1。
参见图9和图10所示，本实施例中模拟/数字信号处理集成组件包括：数字处理芯片DSP 3和用于光信号调制的调制驱动组件；
所述DSP 3用于按照光传输设备的参数对所述电气接口传输的单路或双路电信号(如TX1和TX2)进行时钟数据恢复、速率和/或码型的映 射转换，以得到与光传输设备的参数一致的一路下行电信号，并通过调制驱动组件，得到一路驱动电信号；
具体地，DSP包括：Retimer组件、变速箱Gearbox组件、码型转换模块；
单路1x25Gbps或1x50Gbps NRZ或1x100Gbps PAM4码型输入时，DSP变速箱Gearbox组件不工作，单路Retimer组件将输入单路电信号进行时钟数据恢复，输出单路1x25Gbps NRZ或1x50Gbps NRZ或1x100Gbps PAM4码型作为下行电信号；
双路2x25Gbps NRZ码型输入时，经过Retimer组件、变速箱Gearbox组件将双路输入电信号2x25Gbps NRZ映射转换为单路50Gbps NRZ码型，以作为输出的一路下行电信号；
双路2x25Gbps NRZ码型输入时，经过Retimer组件、变速箱Gearbox组件和码型转换模块将双路输入信号2x25Gbps NRZ映射转换为单路50Gbps PAM4码型，以作为输出的一路下行电信号；
双路2x50Gbps NRZ码型输入时，经过Retimer组件、变速箱Gearbox组件将双路输入信号2x50Gbps NRZ映射转换为单路100Gbps NRZ码型，以作为输出的一路下行电信号；
双路2x50Gbps NRZ码型输入时，经过Retimer组件、变速箱Gearbox组件和码型转换模块将双路输入信号2x50Gbps NRZ映射转换为单路100Gbps PAM4码型，以作为输出的一路下行电信号；
双路2x100Gbps PAM4码型输入时，经过Retimer组件、变速箱Gearbox组件将双路输入信号2x100Gbps PAM4映射转换为单路1x200Gbps PAM4码型，以作为输出的一路下行电信号。
当第一参数电信号速率不高于25Gbps时，使用retimer可实现光模块与系统板卡间高速电信号的高质量收发传输。当第一参数电信号速率 不低于50Gbps时，需用DSP芯片对高速电信号进行处理，retime-only仅用于部分传输性能有限场景。图9至图14展示的OLT光模块案例覆盖了三类功能架构：DSP对收发信号均进行处理、收发均retimer-only、DSP仅处理发端信号收端无需DSP。
参见图10所示，本实施例中模拟/数字信号处理集成组件包括：双路retimer组件和用于光信号调制的调制驱动组件；
所述双路retimer组件用于按照光传输设备的参数对所述电气接口传输的双路电信号进行时钟数据恢复、速率和/或码型的映射转换，以得到与光传输设备的参数一致的两路下行电信号，并通过调制驱动组件，得到两路驱动电信号。
上述双路retimer组件可包括：retimer芯片；
双路2x25Gbps NRZ码型输入时，retimer芯片用于将电气接口接收的双路的电信号各自进行时钟数据恢复，映射转换为双路的25Gbps NRZ码型，以作为输出的双路下行电信号；
双路2x50Gbps NRZ码型输入时，retimer用于将电气接口接收的双路的电信号各自进行时钟数据恢复，映射转换为双路的2x50Gbps NRZ码型，以作为输出的双路下行电信号；
双路组合速率输入时，其中一路为25GbpsNRZ码型，另一路为50Gbps NRZ码型，retimer用于将电气接口接收的双路的电信号各自进行时钟数据恢复，映射转换为一路为25GbpsNRZ、另一路为50Gbps NRZ码型，以作为输出的双路下行电信号；
双路2x100Gbps PAM4码型输入时，retimer用于将电气接口接收的双路的电信号各自进行时钟数据恢复，映射转换为双路的2x 100Gbps PAM4码型，以作为输出的双路下行电信号。
需要说明的是，仅使用retimer功能时，其可支持双通道路单纤双向 光接口方式，支持双通道25G(S)PON或50G(S)PON。双通道PON收发器的优点是支持更高密度更高性能的OLT系统，在不改变PON MAC serdes速率前提下，相比于单通道场景实现了PON连接总带宽的加倍。原一张PON板卡支持16端口SFP+PON OLT光收发器，现可支持32个高速PON端口。
在其他实施例中，模拟/数字信号处理集成组件包括：四路DSP(含retimer)或独立retimer组件和用于光信号调制的调制驱动组件。此时，四路retimer组件用于按照光传输设备的参数对所述电气接口传输的四路电信号进行时钟数据恢复、速率和/或码型的映射转换，以得到与光传输设备的参数一致的四路下行电信号，并通过调制驱动组件，得到四路驱动电信号。四路速率可一致，如采用4x25Gbps、4x50Gbps，也可采用两两一致，如2x25Gbps+2x50Gbps的组合。
具体地，四路retimer组件包括：retimer芯片；
四路4x25Gbps NRZ码型输入时，retimer芯片用于将电气接口接收的四路的电信号各自进行时钟数据恢复，映射转换为四路的25Gbps NRZ码型，以作为输出的四路下行电信号；
四路4x50Gbps NRZ码型输入时，retimer用于将电气接口接收的四路的电信号各自进行时钟数据恢复，映射转换为四路的4x50Gbps NRZ码型，以作为输出的四路下行电信号；
采用2x25Gbps与2x50Gbps四路组合输入时，retimer用于将电气接口接收的四路的电信号各自进行时钟数据恢复，映射转换为四路的2x25Gbps与2x50Gbps NRZ码型，以作为输出的四路下行电信号。
在实际应用中，调制驱动组件为硅光调制驱动组件，集成在DSP中，或，与retimer芯片集成在一个组件上。
另外，本实施例的局端模块中突发模式接收放大芯片组可包括：突 发模式接收跨阻放大器14和突发模式接收线性放大器15，参见图9至图11所示。
所述DSP用于按照光传输设备的参数对所述电气接口传输的单路或双路电信号即第一参数进行时钟数据恢复、速率和/或码型的映射转换，以得到符合光传输设备的传输参数要求的一路下行电信号，并通过调制驱动组件，得到一路驱动电信号即第二参数。
可理解的是，具有第二参数的电信号为一路电信号时，所述突发模式接收放大芯片组输入输出突发模式电信号为一路，如图9所示，且该路突发模式接收放大芯片组的电信号速率等于或低于具有第二参数的电信号的速率，
所述用于具有第二参数的电信号为两路电信号时，所述突发模式接收放大芯片组输入输出突发模式电信号为两路，如图10和图11所示，且两路突发模式接收放大芯片组电信号的速率不高于具有第二参数的电信号的速率。
当用于具有第二参数的电信号为四路电信号时，所述突发模式接收放大芯片组输入输出突发模式电信号为四路，且四路突发模式接收放大芯片组电信号的速率不高于具有第二参数的电信号的速率。
上述的第二参数还可以是：
数字处理芯片DSP和用于硅光光信号调制的调制驱动组件；
所述DSP用于按照光传输设备的参数对所述电气接口传输的四路电信号进行时钟数据恢复、速率和/或码型的映射转换等处理，以得到符合光传输设备的传输参数要求的单路下行电信号，并通过调制驱动组件，得到单路驱动电信号即第二参数；
或者，数字处理芯片DSP和用于硅光光信号调制的调制驱动组件；所述DSP用于按照光传输设备的参数对所述电气接口传输的四路电信号 进行时钟数据恢复、速率和/或码型的映射转换等处理，以得到符合光传输设备的传输参数要求的双路下行电信号，并通过调制驱动组件，得到双路驱动电信号即第二参数，或者，数字处理芯片DSP和用于硅光光信号调制的调制驱动组件；
所述DSP用于按照光传输设备的参数对所述电气接口传输的四路电信号进行时钟数据恢复、速率和/或码型的映射转换等处理，以得到符合光传输设备的传输参数要求的四路下行电信号，并通过调制驱动组件，得到四路驱动电信号即第二参数。
具体地，当DSP或retimer输出下行电信号为单路1x25Gbps NRZ时，经过所述突发模式接收放大芯片组的上行电信号为单路1x25Gbps NRZ；
当DSP输出下行电信号为单路1x50Gbps NRZ时，经过所述突发模式接收放大芯片组的上行电信号为单路1x25Gbps NRZ或1x50Gbps NRZ；
当DSP输出下行电信号为单路1x100Gbps NRZ时，经过所述突发模式接收放大芯片组的上行电信号为单路1x50Gbps NRZ或1x100Gbps NRZ或单路1x100Gbps PAM4；
当DSP输出下行电信号为单路1x50Gbps PAM4时，经过所述突发模式接收放大芯片组的上行电信号为单路1x50Gbps PAM4或单路1x25Gbps NRZ；
当DSP输出下行电信号为单路1x100Gbps PAM4时，经过所述突发模式接收放大芯片组的上行电信号为单路1x100Gbps PAM4或单路1x50Gbps NRZ；
当DSP输出下行电信号为单路1x200Gbps PAM4时，经过所述突发模式接收放大芯片组的上行电信号为单路1x200Gbps PAM4或单路1x100Gbps PAM4。
当retimer芯片输出下行电信号为双路2x25Gbps NRZ时，经过所述 突发模式接收放大芯片组的上行电信号为双路2x25Gbps NRZ；
当retimer或DSP芯片输出下行电信号为双路2x50Gbps NRZ时，经过所述突发模式接收放大芯片组上行电信号为双路2x50Gbps NRZ或双路2x25Gbps NRZ或单路1x50Gbps NRZ与单路1x25Gbps NRZ组合；
当retimer或DSP芯片输出下行电信号为双路2x100Gbps PAM4时，经过所述突发模式接收放大芯片组的上行电信号为双路2x100Gbps PAM4或双路2x50Gbps NRZ。
当retimer或DSP芯片输出下行电信号为单路1x25Gbps NRZ与单路1x50Gbps NRZ组合时，经过所述突发模式接收放大芯片组上行电信号为单路1x25Gbps NRZ与单路1x50Gbps NRZ组合，或者双路2x25Gbps NRZ；
当retimer或DSP芯片输出下行电信号为四路4x25Gbps NRZ时，经过所述突发模式接收放大芯片组的上行电信号为四路4x25Gbps NRZ；
当retimer或DSP芯片输出下行电信号为四路4x50Gbps NRZ时，经过所述突发模式接收放大芯片组上行电信号为四路4x50Gbps NRZ；
当retimer或DSP芯片输出下行电信号为四路2x25Gbps NRZ与2x50Gbps NRZ组合时，经过所述突发模式接收放大芯片组上行电信号为四路2x25Gbps NRZ与2x50Gbps NRZ组合或者四路4x25Gbps NRZ；
在其他实施例中，局端模块还需要包括：微处理器17、EEPROM 18、电源管理组件23等，该些组件的处理方式可与现有的局端模块中各组件的处理方式一致，本实施例不进行详细说明。另外，图12中还示出了为局端模块提供电源的光收发器电源19，在实际应用中可根据需要配置。
本实施例的局端设备采用小型化的SFP-DD/SFP-DD112模块，有效实现下一代OLT系统设备的端口高密度、高性能需求。
结合图12至图14可知，图12和图13适用的SerDes速率目前是24.8832Gbps NRZ和49.7664Gbps NRZ，未来SerDes速率可达 99.5328Gbps PAM4。具体地，图12至图14的左侧属于系统板卡中的OLT PON MAC，其位于系统板卡，以ASIC(Application Specific Integrated Circuit，专用集成电路)或FPGA(Field Programmable Gate Array，现场可编程门阵列)方式实现Physical Coding Sublayer(PCS)功能，包括前向纠错(FEC)、信号编解码等。MAC单路高速信号采用ITU-T PON标准速率24.8832Gbps(简称25Gbps)或49.7664Gbps(50Gbps)，编码方式采用NRZ，该结构和现有的结构功能一致，该处不再赘述。MAC单路高速信号也可在未来提升至99.5328Gbps，编码方式为PAM4。MAC单路高速信号亦可采用以太网速率25.78125Gbps(亦简称25Gbps)。
需要说明的是，在图13中，PMA现在输出是2*24.8832Gbps NRZ和2*49.7664Gbps NRZ，未来可输出2*99.5328Gbps PAM4。
在图14中，SerDes单路速率目前是28G NRZ，光端口单路速率目前是25.78125Gbps NRZ。未来以太网PON SerDes单路速率可达56Gbps PAM4和112Gbps PAM4。
电气接口：系统板卡的高速信号、控制信号、电源供应等经此进出光收发器；电气接口可同时提供双路高速电信号输入(TX1&2)及输出(RX1&2)，也可根据系统板卡要求，只提供一路输入输出(Tx1+Rx1)。
硅光调制器驱动器/硅光调制驱动组件：经由映射转换后的高速信号叠加至此驱动器上，由该驱动器高速调制硅光调制器。图12中示出的硅光调制驱动器目前的输出是1*24.8832Gbps NRZ、1*49.7664Gbps NRZ、1*49.7664Gbps PAM4；未来硅光调制驱动器的输出可以是1*99.5328Gbps NRZ、1*99.5328Gbps PAM4、1*199.0656Gbps PAM4。
突发模式跨阻放大器14：将PIN接收器11接收到的25G或50G突发模式信号放大；
突发模式线性放大器15：对突发TIA输出的25G/50G差分电信号进 行放大，并减少前导码的丢失；
BM CDR SERDES(突发模式时钟数据恢复SerDes)：位于系统板卡上。接收信号Rx1经突发模式线性放大器15和电气接口2后进入此BM CDR SERDES 16；在本地精确时钟信号24.8832Gbps或49.7664Gbps的参考之下，对突发限幅放大器的信号进行鉴频鉴相处理，消除上行信号的抖动和码间干扰后再传回给系统中的PON MAC ASIC 1。
微处理器17：用于处理光收发器各元器件的控制信号、感知信号、协调各元器件的工作；
EEPROM(Electrically Erasable Programmable Read-only Memory带电可擦除可编程只读存储器)18：用于存储光收发器内部各光器件的性能和控制信息，光收发器正常工作时，由微型TEC控制器通过I 2C调用EEPROM 18中相应技术参数；
光收发器电源19：通过电气接口2提供光收发器各组件正常运行所需电源；例如可以提供一种3.3V的电源输入。
电源管理组件23：用于把光收发器的3.3V总电源降压或升压到各个单元电路需要的电平，并按照规定的时序给对应的单元电路供电。
本实施例中，采用SFF-DD MSA协议定义的电气接口结合ITU-T PON速率定义，也提供了同一封装，光口速率升级至单路100GPON的直接路径，且编码方式可灵活采用NRZ也可采用PAM4。
此外，SFP-DD112MSA增加了支持单路100G PAM4输入信号，因此上述的光收发器还可于SFP-DD112封装上未来实现扩展至单路200GPON(经2x1gearbox后的输出信号)。
实施例四
本实施例还提供一种无源光网络PON OLT系统，其包括：上述实施例四中任意所述的基于硅基光电子集成芯片的多速率通道的局端模块； 所述系统通过所述局端模块与PON网络侧交互。系统的基本硬件单元包含电源、机框和板卡。本实施例中，所述PON OLT系统局端板卡可插入SFP-DD/SFP-DD112光收发器的数量为16个。
结合图1至图16可知，PON MAC ASIC 1发出编码后的高速信号经SFP-DD/SFP-DD112封装的电气接口2进入光收发器内的数字处理芯片(DSP)3。信号速率遵守ITU-T PON标准速率要求：为24.8832Gbps(简称25Gbps)或49.7664Gbps(50Gbps)，编码方式均为NRZ。SFP-DD/SFP-DD112可支持双路高速电信号输入(TX1&TX2)及输出(RX1&RX2)，也可只采用一路输入输出(Tx1+Rx1)。
数字处理芯片(DSP)3输出的单路/双路/四路高速信号施加在硅光调制驱动器4上，硅光调制驱动器4高速调制，大功率半导体激光器驱动器22设置O波段大功率半导体激光器6最优工作点，经设置最优工作点的O波段大功率半导体激光器6输出大功率激光信号作为PON下行光源。根据ITU-T 50GPON、IEEE 25G/50G-EPON及25G(S)PON要求全工作温度范围内激射波长维持在1342nm±2nm和1358nm±2nm。
1342nm±2nm和1358nm±2nm通过硅光耦合器7进入收发集成芯片A1，经片上波导进入硅光调制器4被高速调制，再经片上波导，通过硅光合分波器8后离开收发集成芯片A1，耦合进入O波段增益芯片9；O波段增益芯片9由SOA驱动器12设置最优芯片工作点，发射(下行λ DS)和接收(上行λ US)不同波长的O波段光信号经此增益芯片同时被放大。
被O波段增益芯片9放大的λ DS发射大功率信号经微透镜(25c、25a或25b)耦合至SFP-DD/SFP-DD112光收发器的SimplexSC光接口10，并进入传输光纤发网远端；
接收方向的信号说明如下：
上行λ US从传输光纤经SimplexSC光接口10进入光收发器的光引擎。
上行λ US经微透镜(25c、25a或25b)进入O波段增益芯片9被放 大后通过硅光合分波器8，上行λ US经硅光合分波器8和进入硅光PIN接收器11；硅光PIN接收器11将单路高速上行突发模式λ US光信号转化成单路突发模式高速电信号；硅光PIN接收器11输出的突发模式高速电信号顺序经突发模式跨阻放大器14、突发模式线性放大器15、SFP-DD/SFP-DD112封装的电气接口2后离开光收发器进入系统板卡，以及信号经过高速的系统板卡的BM CDR SERDES 16后进入PON MAC ASIC 1，完成OLT侧的信号收发闭环。
应当注意的是，在权利要求中，不应将位于括号之间的任何附图标记理解成对权利要求的限制。词语“包含”不排除存在未列在权利要求中的部件或步骤。位于部件之前的词语“一”或“一个”不排除存在多个这样的部件。上述各实施例可以借助于包括有若干不同部件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的权利要求中，这些装置中的若干个可以是通过同一个硬件来具体体现。词语第一、第二、第三等的使用，仅是为了表述方便，而不表示任何顺序。可将这些词语理解为部件名称的一部分。
此外，需要说明的是，在本说明书的描述中，术语“一个实施例”、“一些实施例”、“实施例”、“示例”、“具体示例”或“一些示例”等的描述，是指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管已描述了各实施例的技术方案，但本领域的技术人员在得知了基本创造性概念后，则可对这些实施例作出另外的变更和修改。所以，权利要求应该解释为包括可选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明进行各种修改和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也应该包含这些修改和变型在内。

Claims (22)

  1. 一种用于PON OLT系统的硅基光电子的收发集成芯片，其特征在于，所述收发集成芯片位于OLT的光引擎中，且实现收发一体的集成芯片，所述收发集成芯片基于OLT前端单路、双路或四路的驱动电信号对光信号进行调制，调制后的下行光信号经过光引擎的增益处理后经由光引擎的光接口发射；
    以及，所述收发集成芯片对光引擎的光接口接收的上行光信号进行光电转换以发送所述OLT的位于光引擎外部区域的突发模式接收放大芯片组进行处理。
  2. 根据权利要求1所述的硅基光电子的收发集成芯片，其特征在于，
    所述驱动电信号为一路驱动电信号，则调制后的下行光信号为一路下行光信号；
    所述驱动电信号为两路独立的驱动电信号，则收发集成芯片基于每一路驱动电信号对光信号进行调制，调制后的下行光信号为两路下行光信号；
    所述驱动电信号为四路独立的驱动电信号，则收发集成芯片基于每一路驱动电信号对光信号进行调制，调制后的下行光信号为四路下行光信号；
    所述光接口接收的上行光信号为一路上行光信号，则所述收发集成芯片对一路上行光信号进行光电转换并输出一路转换后的电信号；
    所述光接口接收的上行光信号为两路上行光信号，则所述收发集成芯片对两路上行光信号分别进行光电转换并输出转换后的两路独立的电信号；
    所述光接口接收的上行光信号为四路上行光信号，则所述收发集成芯片对四路上行光信号分别进行光电转换并输出转换后的四路独立的电信号。
  3. 根据权利要求1所述的硅基光电子的收发集成芯片，其特征在于，驱动电信号为一路驱动电信号时，所述收发集成芯片包括：
    硅光耦合器、硅光调制器、硅光合分波器、硅光PIN接收器；
    所述硅光耦合器接收所述光引擎中激光组件发出的作为下行光源的激光信号，所述下行光源经由光路传输进入到硅光调制器进行调制，所述硅光调制器所述驱动电信号对下行光源进行调制，得到调制后的光信号；
    调制后的光信号经光路传输至硅光合分波器以输出至所述光引擎，以使光引擎进行增益处理并经所述光接口进行下行传输；
    以及，经所述光接口接收的上行光信号在光引擎中增益放大后经硅光合分波器进入所述硅光PIN接收器进行光电转换以输出。
  4. 根据权利要求1所述的硅基光电子的收发集成芯片，其特征在于，驱动电信号为两路驱动电信号时，所述收发集成芯片包括：
    一个硅光耦合器、一个硅基分光器、两个硅光调制器、两个硅光合分波器、两个硅光PIN接收器；
    所述硅光耦合器接收所述光引擎中激光组件发出的作为下行光源的激光信号，所述下行光源经由硅基分光器进行分光处理，形成两路下行光源；
    每一路下行光源经光路传输进入到各自对应的硅光调制器进行调制，每一个硅光调制器基于一路驱动电信号对该路的下行光源进行调制，得到调制后的一路光信号；
    调制后的两路光信号分别经光路传输至各自的硅光合分波器以分别输出至所述光引擎，以使光引擎的两个增益组件对两路输出分别进行增益处理并经所述光接口进行两路光信号的下行传输；
    以及，经所述光接口接收的两路上行光信号在光引擎的两个增益组 件中分别进行增益放大后进入各自的硅光合分波器处理后经光路传输至各自的硅光PIN接收器进行光电转换，每一个硅光PIN接收器输出一路转换后的电信号。
  5. 根据权利要求1所述的硅基光电子的收发集成芯片，其特征在于，驱动电信号为两路驱动电信号时，所述收发集成芯片包括：
    两个硅光耦合器、两个硅光调制器、一个硅光合分波器、两个硅光PIN接收器；
    每一个硅光耦合器接收所述光引擎中对应激光组件发出的作为下行光源的激光信号，两路下行光源分别对应的激光信号波长不同，所述下行光源经由光路传输进入到各自对应的一个硅光调制器进行调制，每一个硅光调制器基于一路驱动电信号对该路的下行光源进行调制，得到调制后的一路光信号；
    调制后的两路光信号经光路传输至一个硅光合分波器以输出两路下行光信号至所述光引擎，以使光引擎的一个增益组件对两路输出进行增益处理并经所述光接口进行两路光信号的下行传输；
    以及，经所述光接口接收的两路上行光信号在光引擎的一个增益组件中进行增益放大后经一路硅光合分波器处理后成为两路上行光信号，每一路上行光信号经光路传输至各自的硅光PIN接收器进行光电转换，每一个硅光PIN接收器输出一路转换后的电信号。
  6. 根据权利要求1所述的硅基光电子的收发集成芯片，其特征在于，驱动电信号为四路驱动电信号时，所述收发集成芯片包括：
    两个硅光耦合器、两个硅基分光器、四个硅光调制器、两个硅光合分波器、四个硅光PIN接收器；
    所述两个硅光耦合器分别接收所述光引擎中两个激光组件发出的作为下行光源的激光信号，且两个激光信号波长不同，所述下行光源经由 硅基分光器进行分光处理，形成四路下行光源，其中两两波长一致；
    每一路下行光源经光路传输进入到各自对应的硅光调制器进行调制，每一个硅光调制器基于一路驱动电信号对该路的下行光源进行调制，得到调制后的一路光信号；
    调制后的四路光信号分别经光路传输至硅光合分波器，且两路不同波长光信号为一组，一共两组分别通过两个硅光合分波器输出至所述光引擎，以使光引擎的两个增益组件对两组四路光信号输出分别进行增益处理并经所述光接口进行四路光信号的下行传输；
    以及，经所述光接口接收的四路上行光信号在光引擎的两个增益组件中分别进行增益放大后进入各自的硅光合分波器处理后经光路传输至各自的硅光PIN接收器进行光电转换，每一个硅光PIN接收器输出一路转换后的电信号。
  7. 根据权利要求1所述的硅基光电子的收发集成芯片，其特征在于，驱动电信号为四路驱动电信号时，所述收发集成芯片包括：
    四个硅光耦合器、四个硅光调制器、一个硅光合分波器、四个硅光PIN接收器；
    每一个硅光耦合器接收所述光引擎中对应激光组件发出的作为下行光源的激光信号，且四路激光信号波长不同，所述下行光源经由光路传输进入到各自对应的一个硅光调制器进行调制，每一个硅光调制器基于一路驱动电信号对该路的下行光源进行调制，得到调制后的一路光信号；
    调制后的四路光信号经光路传输至一个硅光合分波器以输出四路下行光信号至所述光引擎，以使光引擎的一个增益组件对四路输出进行增益处理并经所述光接口进行四路光信号的下行传输；
    以及，经所述光接口接收的四路上行光信号在光引擎的一个增益组件中进行增益放大后经一路硅光合分波器处理后成为四路上行光信号， 每一路上行光信号经光路传输至各自的硅光PIN接收器进行光电转换，每一个硅光PIN接收器输出一路转换后的电信号。
  8. 根据权利要求3至7任一所述的硅基光电子的收发集成芯片，其特征在于，所述收发集成芯片还包括：对应光路传输的硅光波导、硅光监测器；
    所述硅光波导、硅光监测器用于对光路传输的光信号进行传输和监测。
  9. 一种用于PON OLT系统的光引擎，其特征在于，所述光引擎位于采用SFP-DD/SFP-DD112封装的OLT模块中，并基于OLT模块调制驱动组件产生的单路、双路或四路驱动电信号对下行光信号进行调制，经增益处理后通过光引擎的光接口发射；
    以及，所述光引擎的光接口接收的上行光信号进行光电转换以发送所述OLT模块的位于光引擎外部区域的突发模式接收放大芯片组进行处理；
    所述光引擎中设置有权利要求1至8任一所述的硅基光电子的收发集成芯片。
  10. 根据权利要求9所述的光引擎，其特征在于，所述光引擎的光接口用于接收上行光信号或发送下行光信号，所述光接口包括：单通道单纤双向的Simplex SC接口和/或双通道单纤双向传输的双Simplex LC接口；
    且所述光接口用于SFP-DD/SFP-DD112封装方式的光模块。
  11. 根据权利要求9所述的光引擎，其特征在于，所述光引擎包括：
    O波段激光器及驱动组件、O波段增益芯片及驱动组件、光接口、金手指阵列；
    所述O波段激光器及驱动组件作为激光组件产生作为下行光源的激 光信号；O波段增益芯片及驱动组件用于对硅基光电子的收发集成芯片输出的光信号进行增益处理，或者对光接口接收的上行光信号进行增益处理；金手指阵列用于传输光引擎与OLT中其他组件的电信号/驱动电信号；
    其中，所述驱动电信号为一路驱动电信号时，所述O波段激光器及驱动组件为一个、O波段增益芯片及驱动组件为一个；
    所述驱动电信号为两路驱动电信号时，所述O波段激光器及驱动组件为一个、O波段增益芯片及驱动组件为两个；
    所述驱动电信号为两路驱动电信号时，所述O波段激光器及驱动组件为两个、O波段增益芯片及驱动组件为两个；
    所述驱动电信号为两路驱动电信号时，所述O波段激光器及驱动组件为两个、O波段增益芯片及驱动组件为一个；
    所述驱动电信号为四路驱动电信号时，所述O波段激光器及驱动组件为两个、O波段增益芯片及驱动组件为两个；
    所述驱动电信号为四路驱动电信号时，所述O波段激光器及驱动组件为四个、O波段增益芯片及驱动组件为一个。
  12. 一种基于硅基光电子集成芯片的多速率的局端模块，其特征在于，所述局端模块为采用SFP-DD/SFP-DD112封装的模块，所述局端模块包括：电气接口、具有单/双/四路多速率组合的模拟/数字信号处理集成组件、光引擎和具有单/双/四路多速率组合的突发模式接收放大芯片组；
    所述电气接口用于实现局端模块与系统板卡之间的电信号传输；
    所述模拟/数字信号处理集成组件用于将系统板卡通过所述光模块电气接口传输的具有第一参数的下行电信号进行时钟数据恢复、速率和/或码型的变换处理，得到用于具有第二参数的电信号，该电信号用以施加在光引擎中硅基光电子集成芯片对应的光信号上实现光信号的调制，并 将调制后的下行光信号通过所述光引擎的光接口传输网络端，
    以及，借助于光引擎的光接口接收的上行光信号经由光引擎中硅基光电子集成芯片的接收转换成电信号；该电信号经突发模式接收放大芯片组和所述电气接口传输至所述系统板卡；
    所述光引擎中硅基光电子集成芯片为对光信号实现收发一体的收发集成芯片。
  13. 根据权利要求12所述的局端模块，其特征在于，所述光引擎中硅基光电子集成芯片为上述权利要求1至8任一所述的用于PON OLT系统的硅基光电子的收发集成芯片。
  14. 根据权利要求12所述的局端模块，其特征在于，所述光引擎为上述权利要求9至11任一所述的用于PON OLT系统的光引擎。
  15. 根据权利要求12所述的局端模块，其特征在于，所述电气接口包括：SFP-DD/SFP-DD112封装的印刷电路板的金手指阵列；
    所述突发模式接收放大芯片组包括：突发模式接收跨阻放大器和突发模式接收线性放大器；
    所述具有第二参数的电信号为一路电信号时，所述突发模式接收放大芯片组输入输出突发模式电信号为一路，且该路突发模式接收放大芯片组的电信号速率等于或低于具有第二参数的电信号的速率，
    所述用于具有第二参数的电信号为两路电信号时，所述突发模式接收放大芯片组输入输出突发模式电信号为两路，且两路突发模式接收放大芯片组电信号的速率不高于具有第二参数的电信号的速率；
    所述用于具有第二参数的电信号为四路电信号时，所述突发模式接收放大芯片组输入输出突发模式电信号为四路，且四路突发模式接收放大芯片组电信号的速率不高于具有第二参数的电信号的速率。
  16. 根据权利要求12至15任一所述的局端模块，其特征在于，
    所述电气接口用以实现25/50/100/200G PON OLT系统和/或25/50/100/200G EPON OLT系统与局端模块之间的连接，且电气接口包括下述的接口的一种或多种：单路电接口、双路电接口和四路电接口。
  17. 根据权利要求12至15任一所述的局端模块，其特征在于，
    模拟/数字信号处理集成组件包括：
    数字处理芯片DSP和用于硅光光信号调制的调制驱动组件；
    所述DSP用于按照光传输设备的参数对所述电气接口传输的单路或双路电信号即第一参数进行时钟数据恢复、速率和/或码型的映射转换，以得到符合光传输设备的传输参数要求的一路下行电信号，并通过调制驱动组件，得到一路驱动电信号即第二参数；
    和/或，
    数字处理芯片DSP和用于硅光光信号调制的调制驱动组件；
    所述DSP用于按照光传输设备的参数对所述电气接口传输的双路电信号进行时钟数据恢复、速率和/或码型的映射转换等处理，以得到符合光传输设备的传输参数要求的双路下行电信号，并通过调制驱动组件，得到双路驱动电信号即第二参数；
    和/或，
    数字处理芯片DSP和用于硅光光信号调制的调制驱动组件；
    所述DSP用于按照光传输设备的参数对所述电气接口传输的四路电信号进行时钟数据恢复、速率和/或码型的映射转换等处理，以得到符合光传输设备的传输参数要求的单路下行电信号，并通过调制驱动组件，得到单路驱动电信号即第二参数；
    和/或，
    数字处理芯片DSP和用于硅光光信号调制的调制驱动组件；
    所述DSP用于按照光传输设备的参数对所述电气接口传输的四路电 信号进行时钟数据恢复、速率和/或码型的映射转换等处理，以得到符合光传输设备的传输参数要求的双路下行电信号，并通过调制驱动组件，得到双路驱动电信号即第二参数；
    和/或，
    数字处理芯片DSP和用于硅光光信号调制的调制驱动组件；
    所述DSP用于按照光传输设备的参数对所述电气接口传输的四路电信号进行时钟数据恢复、速率和/或码型的映射转换等处理，以得到符合光传输设备的传输参数要求的四路下行电信号，并通过调制驱动组件，得到四路驱动电信号即第二参数；
    和/或，
    模拟/数字信号处理集成组件包括：双路retimer组件和用于光信号调制的调制驱动组件；
    所述双路retimer组件用于按照光传输设备的参数对所述电气接口传输的双路电信号进行时钟数据恢复、速率和/或码型的映射转换，以得到符合光传输设备的传输参数要求的两路下行电信号，并通过调制驱动组件，得到两路驱动电信号；
    和/或，
    模拟/数字信号处理集成组件包括：四路retimer组件和用于光信号调制的调制驱动组件；
    所述四路retimer组件用于按照光传输设备的参数对所述电气接口传输的四路电信号进行时钟数据恢复、速率和/或码型的映射转换，以得到符合光传输设备的传输参数要求的四路下行电信号，并通过调制驱动组件，得到四路驱动电信号。
  18. 根据权利要求17所述的局端模块，其特征在于：
    DSP包括：Retimer组件、变速箱Gearbox组件、码型转换模块；
    单路1x25Gbps或1x50Gbps NRZ或1x100Gbps PAM4码型输入时，变速箱Gearbox组件不工作，单路Retimer组件将输入单路电信号进行时钟数据恢复，输出单路1x25Gbps NRZ或1x50Gbps NRZ或1x100Gbps PAM4码型作为下行电信号；
    双路2x25Gbps NRZ码型输入时，经过Retimer组件、变速箱Gearbox组件将双路输入电信号2x25Gbps NRZ映射转换为单路50Gbps NRZ码型，以作为输出的一路下行电信号；
    双路2x25Gbps NRZ码型输入时，经过Retimer组件、变速箱Gearbox组件和码型转换模块将双路输入信号2x25Gbps NRZ映射转换为单路50Gbps PAM4码型，以作为输出的一路下行电信号；
    双路2x50Gbps NRZ码型输入时，经过Retimer组件、变速箱Gearbox组件将双路输入信号2x50Gbps NRZ映射转换为单路100Gbps NRZ码型，以作为输出的一路下行电信号；
    双路2x50Gbps NRZ码型输入时，经过Retimer组件、变速箱Gearbox组件和码型转换模块将双路输入信号2x50Gbps NRZ映射转换为单路100Gbps PAM4码型，以作为输出的一路下行电信号；
    双路2x 100Gbps PAM4码型输入时，经过Retimer组件、变速箱Gearbox组件将双路输入信号2x 100Gbps PAM4映射转换为单路1x200Gbps PAM4码型，以作为输出的一路下行电信号。
  19. 根据权利要求17所述的局端模块，其特征在于，使用集成于DSP芯片中的retimer，或非集成于DSP中的独立双路retimer组件，包括：retimer芯片；
    双路2x25Gbps NRZ码型输入时，retimer芯片用于将电气接口接收的双路的电信号各自进行时钟数据恢复，映射转换为双路的25Gbps NRZ码型，以作为输出的双路下行电信号；
    双路2x50Gbps NRZ码型输入时，retimer或DSP芯片用于将电气接口接收的双路的电信号各自进行时钟数据恢复，映射转换为双路的2x50Gbps NRZ码型，以作为输出的双路下行电信号；
    双路采用不同速率方式输入时，一路为25Gbps NRZ码型，另一路为50Gbps NRZ码型，retimer或DSP芯片用于将电气接口接收的双路电信号各自进行时钟数据恢复，映射转换为一路为25Gbps NRZ、另一路为50Gbps NRZ码型，以作为输出的双路下行电信号；
    双路2x100Gbps PAM4码型输入时，retimer或DSP芯片用于将电气接口接收的双路的电信号各自进行时钟数据恢复，映射转换为双路的2x 100Gbps PAM4码型，以作为输出的双路下行电信号。
  20. 根据权利要求17所述的局端模块，其特征在于，四路retimer或DSP组件包括：retimer或DSP芯片；
    四路4x25Gbps NRZ码型输入时，retimer或DSP芯片用于将电气接口接收的四路的电信号各自进行时钟数据恢复，映射转换为四路的25Gbps NRZ码型，以作为输出的四路下行电信号；
    四路4x25Gbps NRZ码型输入时，DSP芯片用于将电气接口接收的四路的电信号各自进行时钟数据恢复，经Gearbox后映射转换为单路的100Gbps PAM4码型，以作为输出的单路下行电信号；
    四路4x25Gbps NRZ码型输入时，DSP芯片用于将电气接口接收的四路的电信号各自进行时钟数据恢复，经Gearbox后映射转换为双路的2x50GbpsPAM4或NRZ码型，以作为输出的双路下行电信号；
    四路4x50Gbps NRZ码型输入时，retimer或DSP芯片用于将电气接口接收的四路的电信号各自进行时钟数据恢复，映射转换为四路的4x50Gbps NRZ码型，以作为输出的四路下行电信号；
    四路4x50Gbps NRZ码型输入时，DSP芯片用于将电气接口接收的四 路的电信号各自进行时钟数据恢复，经Gearbox后映射转换为单路的200Gbps PAM4码型，以作为输出的单路下行电信号；
    四路4x50Gbps NRZ码型输入时，DSP芯片用于将电气接口接收的四路的电信号各自进行时钟数据恢复，经Gearbox后映射转换为双路的2x100GbpsPAM4码型，以作为输出的双路下行电信号；
    采用2x25Gbps与2x50Gbps四路组合输入时，retimer或DSP芯片用于将电气接口接收的四路的电信号各自进行时钟数据恢复，映射转换为四路的2x25Gbps与2x50Gbps NRZ码型，以作为输出的四路下行电信号。
  21. 根据权利要求17所述的局端模块，其特征在于，调制驱动组件为硅光调制驱动组件，集成在DSP中，或，与retimer芯片集成在一个组件上。
  22. 一种无源光网络PON OLT系统，其特征在于，包括：上述权利要求12至21任一所述的基于硅基光电子集成芯片的多速率的局端模块；所述PON OLT系统通过所述局端模块与PON网络侧交互。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114647030B (zh) * 2022-05-19 2022-09-09 深圳市迅特通信技术股份有限公司 一种用于pon olt系统的硅基光电子的收发集成芯片
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CN117270123B (zh) * 2023-11-23 2024-03-19 之江实验室 一种多通道光电收发集成系统
CN117650848A (zh) * 2024-01-29 2024-03-05 深圳市迅特通信技术股份有限公司 一种800g lr8光模块

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013172037A (ja) * 2012-02-21 2013-09-02 Sumitomo Electric Ind Ltd 光トランシーバ
CN109412696A (zh) * 2018-08-28 2019-03-01 武汉光迅科技股份有限公司 基于pam4调制技术的双向光收发模块
CN110176960A (zh) * 2019-06-27 2019-08-27 成都光创联科技有限公司 一种新型单纤双向多通道输入光模块
CN113346954A (zh) * 2021-08-05 2021-09-03 深圳市迅特通信技术股份有限公司 一种用于50g以上无源光网络中的局端设备
CN113759477A (zh) * 2020-06-05 2021-12-07 颖飞公司 多信道光引擎的封装型小芯片及共同封装型光电模块
CN114647030A (zh) * 2022-05-19 2022-06-21 深圳市迅特通信技术股份有限公司 一种用于pon olt系统的硅基光电子的收发集成芯片

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0756185B1 (en) * 1995-07-26 2002-04-10 Sumitomo Electric Industries, Ltd. PD/LD module and PD module
DE59802489D1 (de) * 1997-03-07 2002-01-31 Contraves Space Ag Zuerich Verfahren und Anordnung zum Betreiben eines Laser-Sendesystems für optische Freiraum-Kommunikation
BR9811127A (pt) * 1997-08-04 2000-07-18 Pirelli Cavi E Sistemi Spa Transmissor de pulso óptico, sistema de transmissão, e, processo de transmissão óptica de alta velocidade
JP3808413B2 (ja) * 2001-08-15 2006-08-09 日本電信電話株式会社 光通信システム
US7778320B2 (en) * 2005-10-03 2010-08-17 Clariphy Communications, Inc. Multi-channel equalization to compensate for impairments introduced by interleaved devices
CN101350670B (zh) * 2007-07-20 2012-07-04 华为技术有限公司 一种用于无源光网络中光信号的放大装置和方法以及光线路终端
CN101335571B (zh) * 2008-07-22 2012-02-15 华为技术有限公司 光接收装置、光网络系统及光接收方法
CN101354515B (zh) * 2008-09-05 2012-04-04 中兴通讯股份有限公司 激光调制器偏置控制方法和装置
JP5399932B2 (ja) * 2010-01-28 2014-01-29 日本電信電話株式会社 光受信装置および光送受信装置
CN102820931A (zh) * 2012-08-09 2012-12-12 青岛海信宽带多媒体技术有限公司 双模光网络单元光模块
CN203133335U (zh) * 2013-03-13 2013-08-14 深圳新飞通光电子技术有限公司 四端口olt光收发一体模块
CN105553561A (zh) * 2015-12-24 2016-05-04 武汉光迅科技股份有限公司 一种2×100g光收发模块
CN107294611A (zh) * 2017-06-29 2017-10-24 武汉光迅科技股份有限公司 基于pam4调制的400gdml光收发模块
CN207200703U (zh) * 2017-07-26 2018-04-06 深圳市傲科华芯技术有限公司 一种单模光纤双向光收发器
CN107579781B (zh) * 2017-10-18 2024-04-12 成都优博创通信技术股份有限公司 光信号接收模块及光信号收发装置
CN109100989A (zh) * 2018-08-31 2018-12-28 深圳前海达闼云端智能科技有限公司 一种机器人控制方法、装置、介质及电子设备
US10826613B1 (en) * 2019-12-06 2020-11-03 Inphi Corporation Integrated compact in-package light engine
US11218242B2 (en) * 2020-06-05 2022-01-04 Marvell Asia Pte, Ltd. In-packaged multi-channel light engine on single substrate
CN112187368A (zh) * 2020-11-27 2021-01-05 武汉联特科技股份有限公司 一种基于qsfp28封装的10通道mlg光模块
CN113315726B (zh) * 2021-07-29 2021-12-17 深圳市迅特通信技术股份有限公司 一种nrz突发接收的鉴相电路及光模块
CN113346955B (zh) * 2021-08-05 2021-12-17 深圳市迅特通信技术股份有限公司 一种用于50g以上无源光网络中的onu模块

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013172037A (ja) * 2012-02-21 2013-09-02 Sumitomo Electric Ind Ltd 光トランシーバ
CN109412696A (zh) * 2018-08-28 2019-03-01 武汉光迅科技股份有限公司 基于pam4调制技术的双向光收发模块
CN110176960A (zh) * 2019-06-27 2019-08-27 成都光创联科技有限公司 一种新型单纤双向多通道输入光模块
CN113759477A (zh) * 2020-06-05 2021-12-07 颖飞公司 多信道光引擎的封装型小芯片及共同封装型光电模块
CN113346954A (zh) * 2021-08-05 2021-09-03 深圳市迅特通信技术股份有限公司 一种用于50g以上无源光网络中的局端设备
CN114647030A (zh) * 2022-05-19 2022-06-21 深圳市迅特通信技术股份有限公司 一种用于pon olt系统的硅基光电子的收发集成芯片

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