WO2023221221A1 - 输入共模补偿电路、流水线型模数转换器及输入共模补偿方法 - Google Patents

输入共模补偿电路、流水线型模数转换器及输入共模补偿方法 Download PDF

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WO2023221221A1
WO2023221221A1 PCT/CN2022/099444 CN2022099444W WO2023221221A1 WO 2023221221 A1 WO2023221221 A1 WO 2023221221A1 CN 2022099444 W CN2022099444 W CN 2022099444W WO 2023221221 A1 WO2023221221 A1 WO 2023221221A1
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switch
input
amplifier
common mode
residual amplifier
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PCT/CN2022/099444
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English (en)
French (fr)
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王翊舟
刘璐
徐代果
朱璨
付东兵
蒋和全
李儒章
王健安
俞宙
张正平
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重庆吉芯科技有限公司
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Publication of WO2023221221A1 publication Critical patent/WO2023221221A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type

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  • the invention relates to the technical field of integrated circuits, and in particular to an input common mode compensation circuit, a pipeline analog-to-digital converter and an input common mode compensation method.
  • the residual amplifier in a high-speed pipelined analog-to-digital converter usually adopts a fully differential switched capacitor amplifier structure.
  • the level at both ends of the capacitor is controlled by switching, and the corresponding input signal and output signal of the amplifier are generated by charge redistribution. .
  • This method will inevitably lead to a certain deviation in signal generation due to the influence of parasitic capacitance.
  • the parasitic capacitance on the reset switch will cause the common-mode signal at the input end of the residual amplifier to attenuate during operation.
  • the attenuation of the common-mode value will lead to the static operating point of the residual amplifier. Deviation from the reset value causes performance deterioration such as output swing and linearity, ultimately worsening the performance of the pipeline analog-to-digital converter.
  • the purpose of the present invention is to provide an input common mode compensation scheme for the residual amplifier in a pipeline analog-to-digital converter to compensate for the common mode attenuation due to parasitic capacitance, so that the residual amplifier
  • the input common-mode value in the operating state is as close as possible to the reset value without excessive attenuation, thereby preventing the residual amplifier performance from deteriorating due to common-mode attenuation.
  • An input common mode compensation circuit used to compensate the common mode value of the input signal of the residual amplifier in a pipeline analog-to-digital converter including:
  • An energy storage module one end of which is connected to the input end of the residual amplifier
  • the switching selection module has its input end connected to the other end of the energy storage module and its first output end connected to ground;
  • the feedback compensation module has a first input terminal connected to one end of the energy storage module and the residual amplifier, a second input terminal connected to the reset voltage of the residual amplifier, and an output terminal connected to the switching selection module. second output terminal;
  • the input terminal of the switching selection module is connected to the first output terminal of the switching selection module, and the energy storage module is charged under the action of the reset voltage; in the working phase of the residual amplifier, the input end of the switching selection module is connected to the second output end of the switching selection module, and the feedback compensation module performs feedback compensation on the energy storage module, thereby providing feedback to the energy storage module.
  • the common mode value of the input signal of the residual amplifier is compensated and adjusted.
  • the energy storage module includes a first capacitor and a second capacitor, one end of the first capacitor is connected to the non-inverting input end of the residual amplifier, and one end of the second capacitor is connected to the non-inverting input end of the residual amplifier. Inverting input.
  • the switching selection module includes a first switch unit and a second switch unit;
  • the first switch unit includes a first switch and a second switch, and the input terminal of the first switch is connected to the first capacitor.
  • the output end of the first switch is connected to ground
  • the input end of the second switch is connected to the other end of the second capacitor
  • the output end of the second switch is connected to ground;
  • the second switch unit includes a third switch and a fourth switch, the input terminal of the third switch is connected to the other terminal of the first capacitor, and the input terminal of the fourth switch is connected to the other terminal of the second capacitor.
  • the feedback compensation module includes a high slew rate amplifier, a first resistor and a second resistor.
  • the inverting input end of the high slew rate amplifier is connected to the residual amplifier through the first resistor connected in series.
  • the non-inverting input terminal of the high slew rate amplifier is also connected to the inverting input terminal of the residual amplifier through the second resistor connected in series, and the non-inverting input terminal of the high slew rate amplifier is connected to The reset voltage and the output terminal of the high slew rate amplifier are respectively connected to the output terminal of the third switch and the output terminal of the fourth switch.
  • the first switch and the second switch are both closed, the third switch and the fourth switch are both open, and the first switch unit is connected On, the second switch unit is off, and the first capacitor and the second capacitor are respectively charged under the action of the reset voltage;
  • the first switch and the The second switches are all open, the third switch and the fourth switch are both closed, the first switch unit is off, the second switch unit is on, and the high slew rate amplifier is used to The common mode value of the input signal to the residual amplifier is compensated and adjusted.
  • the capacitance of the first capacitor is equal to the capacitance of the second capacitor, and the resistance of the first resistor is equal to the resistance of the second resistor.
  • a pipeline type analog-to-digital converter including the input common mode compensation circuit described in any one of the above, the input common mode compensation circuit is connected to the input end of the residual amplifier in the pipeline type analog to digital converter, the The input common mode compensation circuit compensates and adjusts the common mode value of the input signal of the residual amplifier.
  • An input common mode compensation method used to compensate and adjust the common mode value of the input signal of the residual amplifier in a pipeline analog-to-digital converter including:
  • the energy storage module is charged using the reset voltage of the input terminal of the residual amplifier
  • the feedback compensation module is used to perform feedback compensation on the energy storage module, and then compensate and adjust the common mode value of the input signal of the residual amplifier.
  • the input common mode compensation circuit, pipeline analog-to-digital converter and input common mode compensation method provided by the present invention have at least the following beneficial effects:
  • the entire input common mode compensation circuit is based on the structural design of "energy storage module + switching selection module + feedback compensation module".
  • the energy storage module is charged under the action of the reset voltage.
  • the energy storage module is fed back and compensated through the feedback compensation module, and then the common mode value of the input signal of the residual amplifier is compensated and adjusted; it can effectively suppress the problem caused by the parasitic capacitance of the reset switch without affecting the normal operation of the residual amplifier.
  • the input common mode attenuation phenomenon of the residual amplifier under working conditions ensures the stability of the common mode value of the residual amplifier, thereby ensuring the stable performance of the pipeline analog-to-digital converter.
  • Figure 1 shows the circuit structure diagram of the residual amplifier in a high-speed pipelined analog-to-digital converter.
  • Figure 2 shows a circuit diagram of the input common mode compensation circuit in the present invention.
  • Figure 3 shows the simulation results of the input signal common mode value of the residual amplifier in a high-speed pipeline analog-to-digital converter without input common mode compensation.
  • Figure 4 shows the simulation results of the input signal common mode value of the residual amplifier in a high-speed pipeline analog-to-digital converter with input common mode compensation.
  • the overall structure of the residual amplifier in the traditional high-speed pipeline analog-to-digital converter is shown in Figure 1. It mainly consists of switches SWi1 ⁇ SWi6, SW7 ⁇ SW10, capacitors Cf1 ⁇ Cf2, Ci1 ⁇ Ci2, and residual amplifier AMP1. In order to To achieve subtractive amplification, it uses N sampling units set in parallel. The value of N is an even number greater than or equal to 2, such as 4, 6, 8, etc., and the specific number of N is related to the multiple of the residual amplifier.
  • the i-th The sampling unit includes switches SWi1 ⁇ SWi6 and capacitors Ci1 ⁇ Ci2, and the value of i is 1 ⁇ N.
  • the high reference voltage VREFH is connected to one end of Ci1 through the series-connected switch SWi1
  • the low reference voltage VREFL is connected to one end of Ci1 through the series-connected switch SWi2.
  • the reference voltage VREFL is connected to one end of Ci2 through the series-connected switch SWi3.
  • the high reference voltage VREFH is connected to one end of Ci2 through the series-connected switch SWi4.
  • the positive input signal VIP0 is connected to one end of the capacitor Ci1 through the series-connected switch SWi5.
  • the negative input signal VIP0 is connected to one end of the capacitor Ci1 through the series-connected switch SWi5.
  • the input signal VIN0 is connected to one end of the capacitor Ci2 through the series-connected switch SWi6, and the other end of the capacitor Ci1 is connected to the non-inverting input end of the residual amplifier AMP1. That is, the signal at the other end of the capacitor Ci1 is the non-inverting input signal VIP of the residual amplifier AMP1.
  • the capacitor Ci1 is also connected to the reset voltage VRST through the switches SW7 and SW9 connected in series.
  • the other end of the capacitor Ci2 is connected to the inverting input end of the residual amplifier AMP1. That is, the signal at the other end of the capacitor Ci2 is the inverting input of the residual amplifier AMP1.
  • terminal signal VIN, the capacitor Ci2 is also connected to the common terminal of the switch SW7 and the switch SW9 through the series-connected switch SW8.
  • one end of the capacitor Cf1 is connected to the non-inverting input end of the residual amplifier AMP1
  • the other end of the capacitor Cf1 is connected to the inverting output end of the residual amplifier AMP1
  • the inverting output end of the residual amplifier AMP1 outputs a signal.
  • VON one end of the capacitor Cf2 is connected to the inverting input end of the residual amplifier AMP1
  • the other end of the capacitor Cf2 is connected to the non-inverting output end of the residual amplifier AMP1.
  • the non-inverting output end of the residual amplifier AMP1 outputs the signal VOP.
  • the residual amplifier AMP1 A switch SW10 is connected in series between the non-inverting output end of the amplifier and the inverting output end of the residual amplifier AMP1.
  • the switches SWi5 and SWi6 are turned off, and each group of switches SWi1, SWi2, SWi3, and SWi4 will be turned on and off reasonably based on the results of the comparator.
  • the switches SWi1, SWi2, SWi3, and SWi4 in N/2 sampling units are turned off, and N/ The switches SWi1, SWi2, SWi3, and SWi4 in the two sampling units are turned on, the switches SW7, SW8, SW9, and SW10 are turned off, and the residual amplifier AMP1 is in the working state.
  • the non-inverting input signal of the residual amplifier AMP1 is Vx, so
  • the charge conservation expression on the non-inverting input terminal of the residual amplifier AMP1 is as follows
  • Vx [(CN1+Cf1)*VRST+CN1*(VREFH+VREFL)/2-CN1*VIP0]/(CN1+Cf1);
  • the common mode value of the two reference voltages during sampling i.e., the high reference voltage VREFH and the low reference voltage VREFL
  • VREFH the high reference voltage
  • VREFL the low reference voltage
  • Vx VRST
  • the common mode value of the input signal of the residual amplifier AMP1 should be equal to the reset voltage VRST.
  • one end of the parasitic capacitance Cp1 is connected to the non-inverting input terminal of the residual amplifier AMP1, and the parasitic capacitance Cp1
  • the other end of the parasitic capacitor Cp2 is connected to the reset voltage VRST
  • one end of the parasitic capacitor Cp2 is connected to the inverting input end of the residual amplifier AMP1
  • the other end of the parasitic capacitor Cp2 is connected to the reset voltage VRST.
  • the common-mode signal at the input terminal of the residual amplifier AMP1 will be attenuated due to the charge distribution on the parasitic capacitance Cp1 ⁇ Cp2.
  • the expression is as follows, for the non-inverting input terminal of the residual amplifier AMP1 containing the parasitic capacitance Cp1 (for The inverting input terminal of the residual amplifier AMP1, analyzed in the same way)
  • Vx [(CN1+Cf1)*VRST+CN1*(VREFH+VREFL)/2-CN1*VIP0]/(CN1+Cf1+Cp1);
  • the present invention proposes an input common mode compensation technical solution: during the reset phase of the residual amplifier, the energy storage module is charged for the first time through the reset voltage, and during the working phase of the residual amplifier, the energy storage module is charged through the feedback compensation module.
  • the module can perform feedback compensation to realize the second charge, so as to stabilize the common mode value of the input signal of the residual amplifier near the reset voltage during the working stage and suppress the input common mode attenuation of the residual amplifier during the working state caused by the parasitic capacitance of the reset switch. Phenomenon.
  • the present invention provides an input common mode compensation circuit for compensating the common mode value of the input signal of the residual amplifier in the pipeline analog-to-digital converter, which includes:
  • the energy storage module has one end connected to the input end of the residual amplifier AMP1;
  • the switching selection module has its input end connected to the other end of the energy storage module and its first output end connected to ground AGND;
  • the feedback compensation module has its first input terminal connected to one end of the energy storage module and the residual amplifier AMP1, its second input terminal connected to the reset voltage VRST of the residual amplifier AMP1, and its output terminal connected to the second output terminal of the switching selection module;
  • the input terminal of the switching selection module is connected to the first output terminal of the switching selection module, and the energy storage module is charged under the action of the reset voltage VRST;
  • the switching selection module The input end of the module is connected to the second output end of the switching selection module, and the feedback compensation module performs feedback compensation on the energy storage module, thereby compensating and adjusting the common mode value of the input signal of the residual amplifier.
  • the energy storage module includes a first capacitor Cc1 and a second capacitor Cc2.
  • One end of the first capacitor Cc1 is connected to the non-inverting input end of the residual amplifier AMP1, and one end of the second capacitor Cc2 is connected to the residual amplifier AMP1. the inverting input terminal.
  • the switching selection module includes a first switch unit and a second switch unit;
  • the first switch unit includes a first switch SW11 and a second switch SW12, and the input terminal of the first switch SW11 is connected to the first capacitor Cc1.
  • the other end of the first switch SW11 is connected to ground AGND, the input end of the second switch SW12 is connected to the other end of the second capacitor Cc2, and the output end of the second switch SW12 is connected to ground AGND;
  • the second switch unit includes a third switch SW13 and The input terminal of the fourth switch SW14 and the third switch SW13 is connected to the other terminal of the first capacitor Cc1, and the input terminal of the fourth switch SW14 is connected to the other terminal of the second capacitor Cc2.
  • the feedback compensation module includes a high slew rate amplifier AMP2, a first resistor R1 and a second resistor RR2.
  • the inverting input end of the high slew rate amplifier AMP2 is connected through the first resistor R1 in series and then the residual
  • the non-inverting input terminal of the difference amplifier AMP1 and the inverting input terminal of the high-slew rate amplifier AMP2 are also connected to the inverting input terminal of the residual amplifier AMP1 through the second resistor R2 connected in series.
  • the non-inverting input terminal of the high-slew rate amplifier AMP2 is connected to reset.
  • Voltage VRST, the output terminal of the high slew rate amplifier AMP2 is connected to the output terminal of the third switch SW13 and the output terminal of the fourth switch SW14 respectively.
  • the input terminal of the first switch unit and the input terminal of the second switch unit are connected together, which are the input terminals of the entire switching selection module, and the output terminal of the first switching unit is the switching selection module.
  • the first output end of the second switch unit is the second output end of the switching selection module;
  • the inverting input end of the high slew rate amplifier AMP2 is the first input end of the feedback compensation module, and the high slew rate amplifier AMP2
  • the non-inverting input terminal of is the second input terminal of the feedback compensation module, and the output terminal of the high slew rate amplifier AMP2 is the output terminal of the feedback compensation module.
  • the capacitance of the first capacitor Cc1 is equal to the capacitance of the second capacitor Cc2
  • the resistance of the first resistor R1 is equal to the resistance of the second resistor R2.
  • the third switch SW13 and the fourth switch SW14 are both closed, the first switch unit is turned off, the second switch unit is turned on, and the common mode value of the input signal of the residual amplifier AMP1 is compensated and adjusted through the high slew rate amplifier AMP2.
  • the input common mode compensation circuit works as follows:
  • the first switch SW11 and the second switch SW12 are both closed, the third switch SW13 and the fourth switch SW14 are both open, the first switch unit is turned on, and the second switch unit is turned off.
  • the first capacitor Cc1 and the second capacitor Cc2 are respectively charged under the action of the reset voltage VRST at the input terminal of the residual amplifier AMP1.
  • the charge conservation expression on the non-inverting input terminal of the residual amplifier AMP1 can be listed as follows (residual amplifier AMP1 The same applies to the inverting input terminal)
  • the first switch SW11 and the second switch SW12 are both turned off, the third switch SW13 and the fourth switch SW14 are both closed, the first switch unit is turned off, and the second switch unit is turned on.
  • the high slew rate amplifier AMP2 starts to work. Due to the existence of parasitic capacitances Cp1 ⁇ Cp2, the non-inverting input signal and the inverting input signal of the residual amplifier AMP1 are both pulled low, and both are loaded to the inverting input of the high slew rate amplifier AMP2.
  • the common mode value on the terminal is also pulled down, lower than the reset voltage VRST.
  • the output voltage VAMP of the high slew rate amplifier AMP2 changes from zero to a positive value. Since the high slew rate amplifier AMP2 is a high slew rate amplifier, it can The value of the output voltage VAMP is adjusted in a very short time. At the same time, the originally grounded end of the first capacitor Cc1 (and the second capacitor Cc2) is connected to the positive voltage VAMP, and the first capacitor Cc1 (and the second capacitor Cc2) The voltage at one end connected to the residual amplifier AMP1 rises, causing the common mode value of the input signal loaded on the inverting input of the high-slew rate amplifier AMP2 to also rise to a certain extent.
  • the common mode value of the input signal on the inverting input terminal of the high slew rate amplifier AMP2 approaches infinitely close to the reset voltage VRST, achieving the effect of suppressing attenuation. That is to say, the common mode value of the input signal of the residual amplifier AMP1 through the high slew rate amplifier AMP2 value for compensation adjustment.
  • the charge conservation expression on the non-inverting input terminal of the residual amplifier AMP1 can be listed as follows (the same is true for the inverting input terminal of the residual amplifier AMP1)
  • Vx [(CN1+Cf1+Cc1)*VRST+VAMP*Cc1]/(CN1+Cf1+Cc1+Cp1);
  • Vx after adding the first capacitor Cc1, the value of Vx can be compensated to a certain extent, so that it will not attenuate very drastically.
  • the energy storage module is charged for the first time through the reset voltage VRST, and a part of the charge is stored to ensure that partial compensation can be carried out at the beginning of the working phase. This prevents the parasitic capacitance Cp1 from pulling down the common mode value of the input signal too much; during the working phase, the energy storage module is compensated for the second time through the high slew rate amplifier AMP2 and the external reset voltage VRST to achieve the second charging. Gradually pull the common mode value of the input signal toward the reset voltage VRST.
  • the above-mentioned input common-mode compensation circuit is used for an MDAC of a high-speed pipeline analog-to-digital converter in a 28nm CMOS process.
  • the working speed of this MDAC is 1GHz (that is, the total time of sampling and working state is 1 nanosecond).
  • the closed-loop gain of the residual amplifier AMP1 is 4 times.
  • the number of sampling units is 8.
  • the type of switch is related to the signal connected to it. .
  • the switch connected to the high reference voltage VREFH is a PMOS tube switch
  • the switch connected to the low reference voltage VREFL is an NMOS tube switch
  • the switch connected to the ground level is an NMOS tube switch
  • the switch connected to the output voltage of the residual amplifier AMP1 is a transmission switch. Door switch.
  • the structure of the high slew rate amplifier AMP2 adopts an ordinary OTA op amp structure, which requires a relatively large current to meet the slew rate requirement so that the output voltage VAMP reaches an appropriate value within one clock cycle. Construct the above input common mode compensation circuit and perform simulation.
  • the external input signals (VIP0 and VIN0) are common mode signals
  • the reset voltage VRST is 800mV.
  • the case where the input common mode compensation circuit of the present invention is not added is added.
  • the simulation results without adding the input common mode compensation circuit of the present invention are shown in Figure 3.
  • the input common mode value of the residual amplifier AMP1 is 800mV (799.97mV).
  • the input The common mode value is attenuated to 760mV, an attenuation of 40mV.
  • the simulation results of adding the input common mode compensation circuit of the present invention are shown in Figure 4.
  • the attenuation value is only 8mV, which fully illustrates the input common mode compensation circuit of the present invention's ability to reduce the input common mode attenuation caused by parasitic capacitance. Inhibitory effect.
  • the input common mode compensation circuit will not affect the normal amplification function of the residual amplifier AMP1 for differential mode signals.
  • the present invention also provides a pipeline type analog-to-digital converter, which includes the above-mentioned input common mode compensation circuit.
  • the input common mode compensation circuit is connected to the input end of the residual amplifier in the pipeline type analog to digital converter.
  • the input common mode compensation circuit The common mode value of the input signal of the residual amplifier is compensated and adjusted to suppress the input common mode attenuation of the residual amplifier in the working state due to the parasitic capacitance of the reset switch, ensuring the stability of the common mode value of the residual amplifier, thereby ensuring the pipeline type
  • the performance of the analog-to-digital converter is stable.
  • the present invention also provides an input common mode compensation method for compensating and adjusting the common mode value of the input signal of the residual amplifier in the pipeline analog-to-digital converter, which includes the steps:
  • the common input signal of the difference amplifier can be The mode value is pulled closer to the reset voltage, effectively suppressing the common mode attenuation of the input signal of the difference amplifier.
  • the energy storage module is charged under the action of the reset voltage.
  • the feedback compensation module performs feedback compensation on the energy storage module.

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Abstract

一种输入共模补偿电路、流水线型模数转换器及输入共模补偿方法，所述输入共模补偿电路包括储能模块、切换选择模块及反馈补偿模块，在残差放大器的复位阶段，储能模块在复位电压的作用下充电，在残差放大器的工作阶段，通过反馈补偿模块对储能模块进行反馈补偿，通过复位阶段的一次充电和工作阶段的二次补偿充电，能对工作阶段残差放大器输入信号的共模值进行补偿调节，能够在不影响残差放大器正常工作的前提下，有效抑制了由于复位开关寄生电容导致的工作状态下残差放大器的输入共模衰减现象，保证了残差放大器共模值的稳定，进而保证了流水线型模数转换器的性能稳定。

Description

输入共模补偿电路、流水线型模数转换器及输入共模补偿方法 技术领域
本发明涉及集成电路技术领域，特别是涉及一种输入共模补偿电路、流水线型模数转换器及输入共模补偿方法。
背景技术
高速流水线型模数转换器(Pipelined ADC)中的残差放大器通常采用全差分开关电容放大器结构，通过开关控制电容两端的电平，以电荷重分布的方式来产生放大器对应的输入信号和输出信号。这种方式不可避免的会由于寄生电容的影响而导致信号生成产生一定的偏差。特别是对于残差放大器的输入端而言，复位开关上的寄生电容会造成残差放大器的输入端共模信号在工作状态下衰减，共模值的衰减则会导致残差放大器的静态工作点偏离复位值，引起输出摆幅、线性度等性能的恶化，最终使得流水线型模数转换器的性能变差。
因此，目前亟需一种流水线型模数转换器中残差放大器的输入共模补偿技术方案。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种流水线型模数转换器中残差放大器的输入共模补偿方案，以补偿由于寄生电容产生的共模衰减，使残差放大器在工作状态下的输入共模值尽可能地靠近复位值而不会衰减过多，从而防止因为共模衰减引起的残差放大器性能恶化。
为实现上述目的及其他相关目的，本发明提供的技术方案如下。
一种输入共模补偿电路，用于对流水线型模数转换器中残差放大器输入信号的共模值进行补偿，包括：
储能模块，其一端接所述残差放大器的输入端；
切换选择模块，其输入端接所述储能模块的另一端，其第一输出端接地；
反馈补偿模块，其第一输入端接所述储能模块与所述残差放大器连接的一端，其第二输入端接所述残差放大器的复位电压，其输出端接所述切换选择模块的第二输出端；
其中，在所述残差放大器的复位阶段，所述切换选择模块的输入端与所述切换选择模块的第一输出端接通，所述储能模块在所述复位电压的作用下充电；在所述残差放大器的工作阶段，所述切换选择模块的输入端与所述切换选择模块的第二输出端接通，通过所述反馈补偿模块对所述储能模块进行反馈补偿，进而对所述残差放大器输入信号的共模值进行补偿调 节。
可选地，所述储能模块包括第一电容和第二电容，所述第一电容的一端接所述残差放大器的同相输入端，所述第二电容的一端接所述残差放大器的反相输入端。
可选地，所述切换选择模块包括第一开关单元和第二开关单元；所述第一开关单元包括第一开关和第二开关，所述第一开关的输入端接所述第一电容的另一端，所述第一开关的输出端接地，所述第二开关的输入端接所述第二电容的另一端，所述第二开关的输出端接地；所述第二开关单元包括第三开关和第四开关，所述第三开关的输入端接所述第一电容的另一端，所述第四开关的输入端接所述第二电容的另一端。
可选地，所述反馈补偿模块包括高摆率放大器、第一电阻和第二电阻，所述高摆率放大器的反相输入端经串接的所述第一电阻后接所述残差放大器的同相输入端，所述高摆率放大器的反相输入端还经串接的所述第二电阻后接所述残差放大器的反相输入端，所述高摆率放大器的同相输入端接所述复位电压，所述高摆率放大器的输出端分别接所述第三开关的输出端和所述第四开关的输出端。
可选地，在所述残差放大器的复位阶段，所述第一开关和所述第二开关均闭合，所述第三开关和所述第四开关均断开，所述第一开关单元接通，所述第二开关单元关断，所述第一电容和所述第二电容分别在所述复位电压的作用下充电；在所述残差放大器的工作阶段，所述第一开关和所述第二开关均断开，所述第三开关和所述第四开关均闭合，所述第一开关单元关断，所述第二开关单元接通，通过所述高摆率放大器对所述残差放大器输入信号的共模值进行补偿调节。
可选地，所述第一电容的容值等于所述第二电容的容值，所述第一电阻的阻值等于所述第二电阻的阻值。
一种流水线型模数转换器，包括上述任意一项所述的输入共模补偿电路，所述输入共模补偿电路与所述流水线型模数转换器中残差放大器的输入端连接，所述输入共模补偿电路对所述残差放大器输入信号的共模值进行补偿调节。
一种输入共模补偿方法，用于对流水线型模数转换器中残差放大器输入信号的共模值进行补偿调节，包括：
提供上述任意一项所述的输入共模补偿电路；
在所述残差放大器的复位阶段，利用所述残差放大器的输入端复位电压对所述储能模块充电；
在所述残差放大器的工作阶段，利用所述反馈补偿模块对所述储能模块进行反馈补偿， 进而对所述残差放大器输入信号的共模值进行补偿调节。
如上所述，本发明提供的输入共模补偿电路、流水线型模数转换器及输入共模补偿方法，至少具有以下有益效果：
整个输入共模补偿电路基于“储能模块+切换选择模块+反馈补偿模块”的结构设计，在残差放大器的复位阶段，储能模块在复位电压的作用下充电，在残差放大器的工作阶段，通过反馈补偿模块对储能模块进行反馈补偿，进而对残差放大器输入信号的共模值进行补偿调节；能够在不影响残差放大器正常工作的前提下，有效抑制由于复位开关寄生电容导致的工作状态下残差放大器的输入共模衰减现象，保证残差放大器共模值的稳定，进而保证流水线型模数转换器的性能稳定。
附图说明
图1显示为高速流水线型模数转换器中残差放大器的电路结构图。
图2显示为本发明中输入共模补偿电路的电路图。
图3显示为没有进行输入共模补偿的高速流水线型模数转换器中残差放大器的输入信号共模值的仿真结果图。
图4显示为进行了输入共模补偿的高速流水线型模数转换器中残差放大器的输入信号共模值的仿真结果图。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图4。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技术的人士了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。
传统高速流水线型模数转换器中残差放大器的整体结构如图1所示，它主要由开关SWi1～SWi6、SW7～SW10，电容Cf1～Cf2、Ci1～Ci2，以及残差放大器AMP1构成，为了实现减法放大，它采用了N个并行设置的采样单元，N的取值为大于等于2的偶数，如4、6、8等，而N的具体数目和残差放大器的倍数相关，第i个采样单元包括开关SWi1～SWi6和电容Ci1～Ci2，i的取值为1～N。
详细地，如图1所示，在第i个采样单元中，高参考电压VREFH经串接的开关SWi1后接Ci1的一端，低参考电压VREFL经串接的开关SWi2后接Ci1的一端，低参考电压VREFL经串接的开关SWi3后接Ci2的一端，高参考电压VREFH经串接的开关SWi4后接Ci2的一端，正端输入信号VIP0经串接的开关SWi5后接电容Ci1的一端，负输入信号VIN0经串接的开关SWi6后接电容Ci2的一端，电容Ci1的另一端接残差放大器AMP1的同相输入端，即电容Ci1另一端的信号就是残差放大器AMP1的同相输入端信号VIP，电容Ci1还经依次串接的开关SW7、SW9后接复位电压VRST，电容Ci2的另一端接残差放大器AMP1的反相输入端，即电容Ci2另一端的信号就是残差放大器AMP1的反相输入端信号VIN，电容Ci2还经串接的开关SW8后接开关SW7与开关SW9的公共端。
详细地，如图1所示，电容Cf1的一端接残差放大器AMP1的同相输入端，电容Cf1的另一端接残差放大器AMP1的反相输出端，残差放大器AMP1的反相输出端输出信号VON，电容Cf2的一端接残差放大器AMP1的反相输入端，电容Cf2的另一端接残差放大器AMP1的同相输出端，残差放大器AMP1的同相输出端输出信号VOP，同时，残差放大器AMP1的同相输出端与残差放大器AMP1的反相输出端之间串接有开关SW10。
更详细地，如图1所示，传统高速流水线型模数转换器中残差放大器的工作原理如下：
1)、在复位(采样)阶段，N个并行设置的采样单元中，开关SWi5、SWi6导通，开关SWi1、SWi2、SWi3、SWi4断开，且开关SW7、SW8、SW9、SW10导通，残差放大器AMP1处于复位状态(即不工作)。此时，信号VOP和信号VON的共模值由残差放大器AMP1决定，设其为VCMOUT。为了便于理解，假设输入信号的值为双端输入信号的共模值(即VIP0＝VIN0)，则残差放大器AMP1的同相输入端上的电荷守恒表达式如下(残差放大器AMP1的反相输入端同理分析)
(VIP0-VRST)CN1+(VCMOUT-VRST)Cf1＝Q；
其中，假设N个采样单元中电容的容值相等，均为C0，即C11＝C12＝…＝Ci1＝Ci2＝…＝CN1＝CN2＝C0，则CN1＝N*C0；
2)、在工作阶段，N个并行设置的采样单元中，开关SWi5、SWi6断开，开关SWi1、SWi2、 SWi3、SWi4中的每一组都会根据比较器的结果来合理地进行导通和断开，在输入信号的值为双端输入信号的共模值的情况下，N个并行设置的采样单元中，N/2个采样单元中的开关SWi1、SWi2、SWi3、SWi4断开，N/2个采样单元中的开关SWi1、SWi2、SWi3、SWi4导通，开关SW7、SW8、SW9、SW10断开，残差放大器AMP1处于工作状态，设残差放大器AMP1的同相输入端信号为Vx，此时，残差放大器AMP1的同相输入端上的电荷守恒表达式如下
(VREFH-Vx)CN1/2+(VREFL-Vx)CN1/2+(VCMOUT-Vx)Cf1＝Q；
3)、根据电荷守恒定律，残差放大器AMP1的同相输入端电荷Q在采样阶段和工作阶段相等，这样可以求解出工作状态残差放大器AMP1的同相输入端电压
Vx＝[(CN1+Cf1)*VRST+CN1*(VREFH+VREFL)/2-CN1*VIP0]/(CN1+Cf1)；
通常情况下，采样时的两个参考电压(即高参考电压VREFH与低参考电压VREFL)的共模值，也就是(VREFH+VREFL)/2，与输入信号的共模值相同，因此等于此处的VIP0，所以最后有
Vx＝VRST；
因此，在正常情况下，残差放大器AMP1的输入信号的共模值应该等于复位电压VRST。
然而，由于开关SW7、SW8、SW9的寄生电容以及版图的寄生电容，如图1所示的寄生电容Cp1和寄生电容Cp2，寄生电容Cp1的一端接残差放大器AMP1的同相输入端，寄生电容Cp1的另一端接复位电压VRST，寄生电容Cp2的一端接残差放大器AMP1的反相输入端，寄生电容Cp2的另一端接复位电压VRST。在工作阶段，残差放大器AMP1的输入端共模信号会由于寄生电容Cp1～Cp2上的电荷分配而有衰减，其表达式如下，对于含有寄生电容Cp1的残差放大器AMP1的同相输入端(对于残差放大器AMP1的反相输入端，同理分析)
Vx＝[(CN1+Cf1)*VRST+CN1*(VREFH+VREFL)/2-CN1*VIP0]/(CN1+Cf1+Cp1)；
因此，由上述公式可知，当开关MOS管寄生、版图寄生导致的寄生电容Cp1不能忽略时，在工作阶段，残差放大器AMP1的同相输入端信号Vx就会产生衰减，进而使得残差放大器AMP1输入信号的共模值产生衰减，如前述在背景技术中所提及的，输入信号共模值的衰减则会导致残差放大器的静态工作点偏离复位值，引起输出摆幅、线性度等性能的恶化，最终使得该流水线型模数转换器的性能变差。
基于此，本发明提出一种输入共模补偿技术方案：在残差放大器的复位阶段，通过复位电压对储能模块进行第一次充电，在残差放大器的工作阶段，通过反馈补偿模块对储能模块 进行反馈补偿，实现第二次充电，以将工作阶段残差放大器输入信号的共模值稳定在复位电压附近，抑制由于复位开关寄生电容导致的工作状态下残差放大器的输入共模衰减现象。
首先，如图2所示，本发明提供一种输入共模补偿电路，用于对流水线型模数转换器中残差放大器输入信号的共模值进行补偿，其包括：
储能模块，其一端接残差放大器AMP1的输入端；
切换选择模块，其输入端接储能模块的另一端，其第一输出端接地AGND；
反馈补偿模块，其第一输入端接储能模块与残差放大器AMP1连接的一端，其第二输入端接残差放大器AMP1的复位电压VRST，其输出端接切换选择模块的第二输出端；
其中，在残差放大器的复位阶段，切换选择模块的输入端与切换选择模块的第一输出端接通，储能模块在复位电压VRST的作用下充电；在残差放大器的工作阶段，切换选择模块的输入端与切换选择模块的第二输出端接通，通过反馈补偿模块对储能模块进行反馈补偿，进而对残差放大器输入信号的共模值进行补偿调节。
详细地，如图2所示，储能模块包括第一电容Cc1和第二电容Cc2，第一电容Cc1的一端接残差放大器AMP1的同相输入端，第二电容Cc2的一端接残差放大器AMP1的反相输入端。
详细地，如图2所示，切换选择模块包括第一开关单元和第二开关单元；第一开关单元包括第一开关SW11和第二开关SW12，第一开关SW11的输入端接第一电容Cc1的另一端，第一开关SW11的输出端接地AGND，第二开关SW12的输入端接第二电容Cc2的另一端，第二开关SW12的输出端接地AGND；第二开关单元包括第三开关SW13和第四开关SW14，第三开关SW13的输入端接第一电容Cc1的另一端，第四开关SW14的输入端接第二电容Cc2的另一端。
详细地，如图2所示，反馈补偿模块包括高摆率放大器AMP2、第一电阻R1和第二电阻RR2，高摆率放大器AMP2的反相输入端经串接的第一电阻R1后接残差放大器AMP1的同相输入端，高摆率放大器AMP2的反相输入端还经串接的第二电阻R2后接残差放大器AMP1的反相输入端，高摆率放大器AMP2的同相输入端接复位电压VRST，高摆率放大器AMP2的输出端分别接第三开关SW13的输出端和第四开关SW14的输出端。
更详细地，如图2所示，第一开关单元的输入端和第二开关单元的输入端接在一起，为整个切换选择模块的输入端，第一开关单元的输出端即为切换选择模块的第一输出端，第二开关单元的输出端即为切换选择模块的第二输出端；高摆率放大器AMP2的反相输入端即为反馈补偿模块的第一输入端，高摆率放大器AMP2的同相输入端即为反馈补偿模块的第二输 入端，高摆率放大器AMP2的输出端即为反馈补偿模块的输出端。
在本发明的一可选实施例中，为了使残差放大器AMP1同相输入端的阻抗与残差放大器AMP1反相输入端的阻抗相均衡匹配，第一电容Cc1的容值等于第二电容Cc2的容值，第一电阻R1的阻值等于第二电阻R2的阻值。
更详细地，如图2所示，在残差放大器AMP1的复位阶段，第一开关SW11和第二开关SW12均闭合，第三开关SW13和第四开关SW14均断开，第一开关单元接通，第二开关单元关断，第一电容Cc1和第二电容Cc2分别在复位电压VRST的作用下充电；在残差放大器AMP1的工作阶段，第一开关SW11和第二开关SW12均断开，第三开关SW13和第四开关SW14均闭合，第一开关单元关断，第二开关单元接通，通过高摆率放大器AMP2对残差放大器AMP1输入信号的共模值进行补偿调节。
更详细地，如图2所示，输入共模补偿电路的工作原理如下：
1)、在残差放大器AMP1的复位阶段，第一开关SW11和第二开关SW12均闭合，第三开关SW13和第四开关SW14均断开，第一开关单元接通，第二开关单元关断，第一电容Cc1和第二电容Cc2分别在残差放大器AMP1输入端的复位电压VRST的作用下充电，此时可以列出残差放大器AMP1同相输入端上的电荷守恒表达式如下(残差放大器AMP1反相输入端同理)
(VIP0-VRST)CN1+(VCMOUT-VRST)Cf1-VRST*Cc1＝Q；
2)、在残差放大器AMP1的工作阶段，第一开关SW11和第二开关SW12均断开，第三开关SW13和第四开关SW14均闭合，第一开关单元关断，第二开关单元接通，高摆率放大器AMP2开始工作，由于寄生电容Cp1～Cp2的存在，残差放大器AMP1的同相输入端信号及反相输入端信号均被拉低，二者加载到高摆率放大器AMP2反相输入端上的共模值同样被拉低，低于复位电压VRST，因此，高摆率放大器AMP2输出电压VAMP由零变为正值，由于高摆率放大器AMP2是高摆率放大器，因此它能够在极短的时间之内调整输出电压VAMP的值，同时，第一电容Cc1(和第二电容Cc2)原来接地的一端接入为正值的电压VAMP，第一电容Cc1(和第二电容Cc2)接残差放大器AMP1的一端的电压跟着抬升，使得加载到高摆率放大器AMP2反相输入端上的输入信号共模值同样被抬升一定幅度，但由于寄生电容Cp1的拉低，仍小于复位电压VRST，高摆率放大器AMP2输出电压VAMP的正值变小，第一电容Cc1(和第二电容Cc2)接残差放大器AMP1的一端的电压跟着被小幅度抬升，如此循环往复，在一定时间内，在高摆率放大器AMP2的作用下，第一电容Cc1(和第二电容Cc2)接残差放大器AMP1一端的电压被连续多次小幅度(抬升幅度越来越小)抬升，最终使得加 载到高摆率放大器AMP2反相输入端上的输入信号共模值无限趋近于复位电压VRST，达到抑制衰减的效果，也就是说，通过高摆率放大器AMP2对残差放大器AMP1输入信号的共模值进行补偿调节。考虑寄生电容Cp1，此时可以列出残差放大器AMP1同相输入端上的电荷守恒表达式如下(残差放大器AMP1反相输入端同理)
(VREFH-Vx)CN1/2+(VREFL-Vx)CN1/2+(VCMOUT-Vx)Cf1+(VAMP-Vx)Cc1-VxCp1＝Q；
由于电荷守恒，因此可以解得Vx
Vx＝[(CN1+Cf1+Cc1)*VRST+VAMP*Cc1]/(CN1+Cf1+Cc1+Cp1)；
可以看到，加入第一电容Cc1后，能够一定程度补偿Vx的值，使它不会衰减得非常剧烈。
需要强调的是，在上述输入共模补偿电路中，在复位阶段，通过复位电压VRST对储能模块进行第一次充电，存储一部分电荷，以保证在工作阶段的开始时候就能进行部分补偿，使得寄生电容Cp1不会将输入信号的共模值下拉得太厉害；在工作阶段，通过高摆率放大器AMP2及外接的复位电压VRST对储能模块进行第二次补偿，实现第二次充电，将输入信号的共模值逐步向复位电压VRST拉升。
在本发明的一可选实施例中，为了进一步验证上述输入共模补偿电路的优点，在28nm CMOS工艺下，对一个高速流水线型模数转换器的MDAC采用上述输入共模补偿电路。该MDAC的工作速度为1GHz(即采样和工作状态总时间为1纳秒)，残差放大器AMP1的闭环增益为4倍，采样单元的个数为8，开关的种类和与其相接的信号有关。接入高参考电压VREFH的开关为PMOS管开关、接入低参考电压VREFL的开关为NMOS管开关、接到地电平的开关为NMOS管开关，接入残差放大器AMP1输出电压的开关为传输门开关。高摆率放大器AMP2的结构采用普通OTA运放结构，它需要比较大的电流来满足摆率要求，使得输出电压VAMP在一个时钟周期内达到合适的值。构建上述输入共模补偿电路并进行仿真，外部输入信号(VIP0和VIN0)为共模信号，复位电压VRST为800mV。
为了和本发明的输入共模补偿电路进行对比，增加了没有添加本发明输入共模补偿电路的情况。没有增加本发明输入共模补偿电路的仿真结果如图3所示，在复位阶段残差放大器AMP1的输入共模值为800mV(799.97mV)，到了工作阶段，由于复位开关寄生电容的影响，输入共模值衰减为760mV，衰减了40mV。添加了本发明输入共模补偿电路的仿真结果如图4所示，可以看到，衰减值仅仅只有8mV，这充分说明了本发明输入共模补偿电路对由于寄生电容引起的输入共模衰减的抑制效果。同时，该输入共模补偿电路并不会影响残差放大器AMP1对差模信号的正常放大功能。
其次，本发明还提供一种流水线型模数转换器，其包括上述输入共模补偿电路，输入共模补偿电路与流水线型模数转换器中残差放大器的输入端连接，输入共模补偿电路对残差放大器输入信号的共模值进行补偿调节，以抑制由于复位开关寄生电容导致的工作状态下残差放大器的输入共模衰减现象，保证残差放大器共模值的稳定，进而保证流水线型模数转换器的性能稳定。
最后，本发明还提供一种输入共模补偿方法，用于对流水线型模数转换器中残差放大器输入信号的共模值进行补偿调节，其包括步骤：
S1、提供上述输入共模补偿电路；
S2、在残差放大器的复位阶段，利用残差放大器的输入端复位电压对储能模块充电；
S3、在残差放大器的工作阶段，利用反馈补偿模块对储能模块进行反馈补偿，进而对残差放大器输入信号的共模值进行补偿调节。
详细地，在步骤S2～S3中，通过储能模块的第一次充电和反馈补偿模块对储能模块的第二次补偿充电，在残差放大器的工作阶段，能将差放大器输入信号的共模值向复位电压拉升靠近，有效抑制了差放大器输入信号的共模衰减。
综上所述，在本发明提供的输入共模补偿电路、流水线型模数转换器及输入共模补偿方法中，在残差放大器的复位阶段，储能模块在复位电压的作用下充电，在残差放大器的工作阶段，通过反馈补偿模块对储能模块进行反馈补偿，通过复位阶段的一次充电和工作阶段的二次补偿充电，能对工作阶段残差放大器输入信号的共模值进行补偿调节，能够在不影响残差放大器正常工作的前提下，有效抑制了由于复位开关寄生电容导致的工作状态下残差放大器的输入共模衰减现象，保证了残差放大器共模值的稳定，进而保证了流水线型模数转换器的性能稳定。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (8)

  1. 一种输入共模补偿电路，用于对流水线型模数转换器中残差放大器输入信号的共模值进行补偿，其特征在于，包括：
    储能模块，其一端接所述残差放大器的输入端；
    切换选择模块，其输入端接所述储能模块的另一端，其第一输出端接地；
    反馈补偿模块，其第一输入端接所述储能模块与所述残差放大器连接的一端，其第二输入端接所述残差放大器的复位电压，其输出端接所述切换选择模块的第二输出端；
    其中，在所述残差放大器的复位阶段，所述切换选择模块的输入端与所述切换选择模块的第一输出端接通，所述储能模块在所述复位电压的作用下充电；在所述残差放大器的工作阶段，所述切换选择模块的输入端与所述切换选择模块的第二输出端接通，通过所述反馈补偿模块对所述储能模块进行反馈补偿，进而对所述残差放大器输入信号的共模值进行补偿调节。
  2. 根据权利要求1所述的输入共模补偿电路，其特征在于，所述储能模块包括第一电容和第二电容，所述第一电容的一端接所述残差放大器的同相输入端，所述第二电容的一端接所述残差放大器的反相输入端。
  3. 根据权利要求2所述的输入共模补偿电路，其特征在于，所述切换选择模块包括第一开关单元和第二开关单元；所述第一开关单元包括第一开关和第二开关，所述第一开关的输入端接所述第一电容的另一端，所述第一开关的输出端接地，所述第二开关的输入端接所述第二电容的另一端，所述第二开关的输出端接地；所述第二开关单元包括第三开关和第四开关，所述第三开关的输入端接所述第一电容的另一端，所述第四开关的输入端接所述第二电容的另一端。
  4. 根据权利要求3所述的输入共模补偿电路，其特征在于，所述反馈补偿模块包括高摆率放大器、第一电阻和第二电阻，所述高摆率放大器的反相输入端经串接的所述第一电阻后接所述残差放大器的同相输入端，所述高摆率放大器的反相输入端还经串接的所述第二电阻后接所述残差放大器的反相输入端，所述高摆率放大器的同相输入端接所述复位电压，所述高摆率放大器的输出端分别接所述第三开关的输出端和所述第四开关的输出端。
  5. 根据权利要求4所述的输入共模补偿电路，其特征在于，在所述残差放大器的复位阶段，所述第一开关和所述第二开关均闭合，所述第三开关和所述第四开关均断开，所述第一 开关单元接通，所述第二开关单元关断，所述第一电容和所述第二电容分别在所述复位电压的作用下充电；在所述残差放大器的工作阶段，所述第一开关和所述第二开关均断开，所述第三开关和所述第四开关均闭合，所述第一开关单元关断，所述第二开关单元接通，通过所述高摆率放大器对所述残差放大器输入信号的共模值进行补偿调节。
  6. 根据权利要求4所述的输入共模补偿电路，其特征在于，所述第一电容的容值等于所述第二电容的容值，所述第一电阻的阻值等于所述第二电阻的阻值。
  7. 一种流水线型模数转换器，其特征在于，包括权利要求1-6中任意一项所述的输入共模补偿电路，所述输入共模补偿电路与所述流水线型模数转换器中残差放大器的输入端连接，所述输入共模补偿电路对所述残差放大器输入信号的共模值进行补偿调节。
  8. 一种输入共模补偿方法，用于对流水线型模数转换器中残差放大器输入信号的共模值进行补偿调节，其特征在于，包括：
    提供权利要求1-6中任意一项所述的输入共模补偿电路；
    在所述残差放大器的复位阶段，利用所述残差放大器的输入端复位电压对所述储能模块充电；
    在所述残差放大器的工作阶段，利用所述反馈补偿模块对所述储能模块进行反馈补偿，进而对所述残差放大器输入信号的共模值进行补偿调节。
PCT/CN2022/099444 2022-05-18 2022-06-17 输入共模补偿电路、流水线型模数转换器及输入共模补偿方法 WO2023221221A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103944573A (zh) * 2013-01-23 2014-07-23 马克西姆综合产品公司 具有差分电流抵消的mdac
US9716513B1 (en) * 2016-08-03 2017-07-25 Analog Devices, Inc. Systems and methods for generating a common mode compensation voltage in a SAR ADC
CN107528594A (zh) * 2017-08-25 2017-12-29 中国电子科技集团公司第二十四研究所 电荷式流水线逐次逼近型模数转换器及其控制方法
CN107800435A (zh) * 2017-11-27 2018-03-13 安凯(广州)微电子技术有限公司 一种电容阵列寄生效应的补偿电路和抵消方法
CN109004911A (zh) * 2017-06-07 2018-12-14 亚德诺半导体集团 具有调节的共模抑制的差分放大器和具有改进的共模抑制比率的电路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103944573A (zh) * 2013-01-23 2014-07-23 马克西姆综合产品公司 具有差分电流抵消的mdac
US9716513B1 (en) * 2016-08-03 2017-07-25 Analog Devices, Inc. Systems and methods for generating a common mode compensation voltage in a SAR ADC
CN109004911A (zh) * 2017-06-07 2018-12-14 亚德诺半导体集团 具有调节的共模抑制的差分放大器和具有改进的共模抑制比率的电路
CN107528594A (zh) * 2017-08-25 2017-12-29 中国电子科技集团公司第二十四研究所 电荷式流水线逐次逼近型模数转换器及其控制方法
CN107800435A (zh) * 2017-11-27 2018-03-13 安凯(广州)微电子技术有限公司 一种电容阵列寄生效应的补偿电路和抵消方法

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