WO2023221126A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2023221126A1
WO2023221126A1 PCT/CN2022/094235 CN2022094235W WO2023221126A1 WO 2023221126 A1 WO2023221126 A1 WO 2023221126A1 CN 2022094235 W CN2022094235 W CN 2022094235W WO 2023221126 A1 WO2023221126 A1 WO 2023221126A1
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Prior art keywords
display area
light
substrate
display
layer
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PCT/CN2022/094235
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English (en)
French (fr)
Inventor
谢涛峰
胡明
石博
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/094235 priority Critical patent/WO2023221126A1/zh
Priority to CN202280001362.5A priority patent/CN117546628A/zh
Publication of WO2023221126A1 publication Critical patent/WO2023221126A1/zh

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  • the present disclosure relates to but is not limited to the field of display technology, and specifically relates to a display substrate, a preparation method thereof, and a display device.
  • the present disclosure provides a display substrate, including a first display area and a second display area.
  • the second display area is located on at least one side of the first display area.
  • the first display area is under the screen.
  • Sensing area; the display substrate at least includes:
  • a substrate located at least in the first display area and the second display area
  • a pixel circuit layer at least part of the pixel circuit layer is located in the second display area and on one side of the substrate;
  • a first reflective interface is located at least in the first display area and the second display area, and is located on a side of the substrate away from the pixel circuit layer; the first reflective interface directs at least part of the light toward the pixel circuit layer reflection;
  • a first polarizing structure at least part of the first polarizing structure is located in the second display area, and at least part of the first polarizing structure is located between the substrate and the first reflective interface, the first polarizing structure It is configured to block the light reflected by the first reflective interface from entering the pixel circuit layer.
  • a third display area is further included, the third display area is located on at least one side of the first display area and the second display area, and at least part of the pixel circuit layer is located on the third display area.
  • it also includes:
  • a plurality of first light-emitting elements are located in the first display area and on the side of the substrate away from the first reflective interface;
  • the second reflective interface is located at least in the first display area and the second display area, and at least on the side of the plurality of first light-emitting elements away from the substrate.
  • the second reflective interface converts at least one first The light emitted by the light-emitting element forms reflected light;
  • a second polarizing structure is located at least in the first display area and the second display area, and at least between the plurality of first light-emitting elements and the second reflective interface, the second polarizing structure is configured In order to transmit the reflected light, the transmitted reflected light forms a first circularly polarized light, and the first circularly polarized light is emitted toward the first reflective interface;
  • the first reflective interface is configured to form the incident first circularly polarized light into a second circularly polarized light, and to reflect at least part of the second circularly polarized light to the first polarizing structure; the The first polarizing structure is configured to block the second circularly polarized light from entering the pixel circuit layer.
  • the second polarizing structure includes a stacked second linearly polarizing film layer and a second retardation film layer, and the second retardation film layer is located on the second linearly polarizing film layer close to the substrate.
  • the second linearly polarizing film layer is configured to transmit the reflected light and form the transmitted reflected light into a first linearly polarized light
  • the second retardation film layer is configured to transmit the first linearly polarized light. Linearly polarized light, and the transmitted first linearly polarized light forms the first circularly polarized light.
  • the first polarizing structure includes a stacked first linear polarizing film layer and a first phase difference film layer, and the first phase difference film layer is located close to the first linear polarizing film layer.
  • the first phase difference film layer is configured to transmit the second circularly polarized light, and form the transmitted second circularly polarized light into a second linearly polarized light, and the first linearly polarized film layer configured to block the transmission of the incident second linearly polarized light.
  • the polarization direction of the second linearly polarized light is perpendicular to the polarization direction of the first linearly polarized film layer.
  • the orthographic projection of the first linearly polarizing film layer on the substrate does not overlap with the first display area, and at least part of the orthographic projection of the first linear polarizing film layer on the substrate overlap with the first display area.
  • an orthographic projection of the first polarizing structure on the substrate does not overlap the first display area.
  • the method further includes: a backplane, the backplane is located at least in the first display area and the second display area, and the backplane is at least located in the first polarizing structure away from the substrate. On one side, the interface between the side surface of the back plate away from the substrate and the outside of the display substrate forms the first reflective interface.
  • it also includes: a composite film, the composite film is located at least in the second display area, the composite film is at least located on the side of the back plate away from the substrate, the composite film is on the The orthographic projection of the substrate does not overlap with the first display area.
  • it further includes: a cover plate, the cover plate is located at least in the first display area and the second display area, and the cover plate is located on the side of the second polarizing structure away from the substrate. , the interface between the side surface of the cover plate away from the base and the outside of the display substrate forms the second reflective interface.
  • an encapsulation layer is further included, the encapsulation layer is located at least in the first display area and the second display area, and the encapsulation layer is located on a side of the pixel circuit layer away from the substrate.
  • it further includes: a plurality of second light-emitting elements, the pixel circuit layer includes a plurality of first pixel circuits and a plurality of second pixel circuits, the plurality of second light-emitting elements, the plurality of The first pixel circuit and the plurality of second pixel circuits are located in the second display area, the plurality of second light-emitting elements are located on the side of the pixel circuit layer away from the substrate, the first pixel circuit and The first light-emitting element is electrically connected, and the second pixel circuit is electrically connected with the second light-emitting element.
  • the spacing between the first light-emitting elements is greater than the spacing between the second light-emitting elements; and/or the area of the first light-emitting elements is smaller than that of the second light-emitting elements. area.
  • the second display area has 3 or 4 second light-emitting elements arranged in a direction away from the first display area.
  • the orthographic projection of the first polarizing structure on the substrate overlaps with the orthographic projection of the three or four second light-emitting elements on the substrate.
  • a light-absorbing layer is further included, the light-absorbing layer is located at least in the first display area and the second display area, and the light-absorbing layer is stacked between the first polarizing structure and the third display area. between a reflective interface.
  • a light-shielding layer is further included.
  • the light-shielding layer is located in the second display area.
  • the orthographic projection of the light-shielding layer on the substrate does not overlap with the first display area.
  • the light-shielding layers are stacked. On the side of the pixel circuit layer close to the substrate.
  • the present disclosure also provides a display device, including any of the above-mentioned display substrates and a photosensitive sensor.
  • the photosensitive sensor is located on a side away from the light emitting side of the display substrate.
  • the photosensitive sensor is located on the side of the display substrate. There is an overlapping area between the orthographic projection on the display substrate and the first display area in the display substrate.
  • the present disclosure also provides a method for preparing a display substrate, the display substrate including a first display area and a second display area, the second display area being located on at least one side of the first display area,
  • the first display area is the under-screen sensing area;
  • the preparation method of the display substrate includes:
  • a first reflective interface is formed at least on the side of the substrate away from the pixel circuit layer, and the first reflective interface is located at least in the first display area and the second display area; the first reflective interface will At least part of the light is reflected toward the pixel circuit layer;
  • At least a first polarizing structure is formed between the substrate and the first reflective interface, and at least part of the first polarizing structure is located in the second display area, and the first polarizing structure is configured to block the first polarizing structure.
  • the light reflected by a reflective interface is incident on the pixel circuit layer.
  • Figure 1A is a schematic diagram of a display substrate according to an embodiment of the present disclosure
  • FIG. 1B is another schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • Figure 2A is a cross-sectional view of a display substrate according to an embodiment of the present disclosure
  • Figure 2B is another cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • Figure 2C is another cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • Figure 2D is another cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • Figure 2E is another cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • Figure 3 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • Figure 4 is a schematic diagram of a display substrate in related technology
  • 5A is a top view of the light-emitting element in the first display area of the display substrate of the present disclosure
  • Figure 5B is a top view of the light-emitting element in the second display area of the display substrate of the present disclosure
  • Figure 5C is a top view of the light-emitting element in the third display area of the display substrate of the present disclosure.
  • Figure 5D is a second top view of the light-emitting element in the first display area of the display substrate of the present disclosure
  • FIG. 6 is a schematic diagram showing an optical path in a substrate according to an embodiment of the present disclosure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode .
  • the channel region refers to the region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • component having some electrical function There is no particular limitation on the “component having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • elements having some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • film and “layer” may be interchanged.
  • conductive layer may sometimes be replaced by “conductive film.”
  • insulating film may sometimes be replaced by “insulating layer”.
  • FIG. 4 is a schematic diagram of a display substrate in the related art.
  • the display substrate of the related technology includes an under-screen sensing area B1 and a display area B2 located around the under-screen sensing area B1.
  • the under-screen sensing is an under-screen sensing camera (FDC, Full Display).
  • the under-screen sensing area B1 includes a substrate and a plurality of first light-emitting elements b1 provided on the substrate
  • the display area B2 includes a substrate, a plurality of second light-emitting elements b2 provided on the base, and a pixel circuit layer b3, a plurality of second light-emitting elements b2 are located on the side of the pixel circuit layer b3 away from the substrate.
  • the light emitted by the first light-emitting element b1 in the under-screen sensing area B1 will be reflected on the internal film layer of the display substrate and illuminate the pixel circuit layer b3 in the display area B2, causing the pixel circuit to be damaged.
  • the characteristics of layer b3 are forward biased, causing the second light-emitting element b2 to emit light, and the radiation area is about 3 to 4 second light-emitting elements b2, causing dark rings and other undesirable phenomena, affecting the display effect.
  • the dark ring gradually lightens away from the under-screen sensing area B1.
  • the inventor of the present application painted the backlight side of the under-screen sensing area B1 black, so that the light intensity received by the second display unit b2 of the display area B2 is reduced, and the dark ring response is reduced by about 38%.
  • An embodiment of the present disclosure provides a display substrate, including a first display area and a second display area.
  • the second display area is located on at least one side of the first display area.
  • the first display area is an under-screen transmission area.
  • Sensing area; the display substrate at least includes:
  • a substrate located at least in the first display area and the second display area
  • a pixel circuit layer at least part of the pixel circuit layer is located in the second display area and on one side of the substrate;
  • a first reflective interface is located at least in the first display area and the second display area, and is located on a side of the substrate away from the pixel circuit layer; the first reflective interface directs at least part of the light toward the pixel circuit layer reflection;
  • a first polarizing structure at least part of the first polarizing structure is located in the second display area, and at least part of the first polarizing structure is located between the substrate and the first reflective interface, the first polarizing structure It is configured to block the light reflected by the first reflective interface from entering the pixel circuit layer.
  • FIG. 1A is a schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 1B is another schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • the display substrate includes: a display area AA and a frame area BB located around the display area AA.
  • the display area AA may include: a first display area A1, a second display area A2, and a third display area A3.
  • the second display area A2 may be located at at least one side of the first display area A1.
  • the third display area A3 is located at at least one side of the first display area A1 and the second display area A2.
  • the area within the display area AA other than the first display area A1 and the second display area A2 is a third display area A3.
  • the first display area A1 can also be called an under-screen sensing area, such as an under-screen camera (FDC, Full Display with Camera) area
  • the second display area A2 can also be called a buffer area
  • the third display area A3 can also be called a buffer area. It can be called the normal display area.
  • this embodiment is not limited to this.
  • the first display area A1 and the second display area A2 may be located at the top middle position of the display substrate.
  • this embodiment is not limited to this.
  • the first display area A1 and the second display area A2 may be located at other positions such as the upper left corner or the upper right corner of the display substrate.
  • the second display area A2 may be located on opposite sides of the first display area A1 in the first direction X.
  • this embodiment is not limited to this.
  • the second display area may be located on one side of the first display area in the first direction, or may be located on at least one side of the first display area in the second direction.
  • the display area AA may be a rectangle, for example, a rounded rectangle.
  • the first display area A1 may be circular or elliptical.
  • the first display area A1 may be rectangular.
  • this embodiment is not limited to this.
  • the first display area may be in another shape such as a quadrilateral or a pentagon.
  • the first display area A1 may also be called an under-screen sensing area, and the under-screen sensing area may be a light-transmitting display area.
  • the orthographic projection of hardware such as a photosensitive sensor (eg, camera) on the display substrate may be located in the first display area A1 of the display substrate.
  • the display substrate in this example does not require drilling holes, making a true full screen possible while ensuring the practicality of the display substrate.
  • the first display area A1 may be circular, and the size of the orthographic projection of the photosensitive sensor on the display substrate may be smaller than or equal to the size of the first display area A1 . In other examples, as shown in FIG.
  • the first display area A1 may be rectangular, and the size of the orthographic projection of the photosensitive sensor on the display substrate may be less than or equal to the size of the inscribed circle of the first display area A1 .
  • this embodiment is not limited to this.
  • the display substrate may include a plurality of sub-pixels disposed on the substrate, and at least one sub-pixel may include a pixel circuit and a light-emitting element.
  • the pixel circuit is configured to drive the light emitting element.
  • the pixel circuit is configured to provide a driving current to drive the light emitting element to emit light.
  • the light-emitting element may be an organic light-emitting diode (OLED).
  • OLED organic light-emitting diode
  • the light-emitting element emits red light, green light, blue light, or white light, etc., driven by its corresponding pixel circuit.
  • the color of the light-emitting element can be determined according to needs.
  • the light transmittance of the first display area A1 in order to improve the light transmittance of the first display area A1, only light-emitting elements may be provided in the first display area A1, and a pixel circuit that drives the light-emitting elements of the first display area A1 may be provided in the second display area A1. Display area A2. That is, the light transmittance of the first display area A1 is increased by separately disposing the light-emitting element and the pixel circuit. In this example, in the first display area A1, no pixel circuit is provided.
  • a pixel circuit can also be provided in the first display area A1.
  • island-shaped pixel circuits are provided in the first display area A1, and the number of pixel circuits in the unit area (for example: 1000 square microns) of the first display area A1 is smaller than the number of pixel circuits in the third display area A3.
  • the area of the first light-emitting element 21 in the first display area A1 is smaller than the area of the second light-emitting element 22 and/or the third light-emitting element 23 .
  • the area of at least one color of the first light-emitting element 21 (for example: red R) in the first display area A1 is smaller than the area of the corresponding color of the second light-emitting element 22 (for example: red R) and/or the third light-emitting element 23 ( For example: the area of red R).
  • the distance between the first light-emitting elements 21 of the first display area A1 is greater than the distance between the second light-emitting elements 22 of the second display area A2; and/or the first light-emitting element of the first display area A1
  • the spacing between the elements 21 is greater than the spacing between the third light-emitting elements 23 in the third display area A3.
  • the shape of the first light-emitting element 21 in the first display area A1 is different from the shape of the second light-emitting element 22 and/or the third light-emitting element 23 .
  • the first light-emitting element 21 in the first display area A1 is circular in shape
  • the second light-emitting element 22 and/or the third light-emitting element 23 is rectangular.
  • FIG. 2C is another cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • the display substrate of the embodiment of the present disclosure includes a substrate 2 and a plurality of first light-emitting elements 21 , a plurality of second light-emitting elements 22 and a plurality of third light-emitting elements disposed on the substrate 2 .
  • the light-emitting elements 23 include a plurality of first light-emitting elements 21 located in the first display area A1, a plurality of second light-emitting elements 22 located in the second display area A2, and a plurality of third light-emitting elements 23 located in the third display area A3.
  • Quantum dot structures 20 of corresponding colors may be provided above or below corresponding positions of the first light-emitting element 21 , the second light-emitting element 22 , and the third light-emitting element 23 .
  • a red quantum dot element is arranged above the red light-emitting element (R) among the first light-emitting element 21, the second light-emitting element 22, and the third light-emitting element 23.
  • the quantum dot structure 20 includes a plurality of first quantum dot elements 211 , a plurality of second quantum dot elements 221 , and a plurality of third quantum dot elements 231 .
  • the plurality of first quantum dot elements 211 are arranged in one-to-one correspondence with the plurality of first light-emitting elements 21 .
  • the first quantum dot elements 211 are located on the side of the first light-emitting element 21 away from the substrate, and at least part of the first quantum dot elements 211 is on the substrate 2
  • the orthographic projection of the first light-emitting element 21 overlaps with the orthographic projection of the first light-emitting element 21 on the substrate 2 .
  • the plurality of second quantum dot elements 221 are arranged in one-to-one correspondence with the plurality of second light-emitting elements 22 .
  • the second quantum dot elements 221 are located on the side of the second light-emitting element 22 away from the substrate, and at least part of the second quantum dot elements 221 is on the substrate 2
  • the orthographic projection of the second light-emitting element 22 overlaps with the orthographic projection of the second light-emitting element 22 on the substrate 2 .
  • the plurality of third quantum dot elements 231 are arranged in one-to-one correspondence with the plurality of third light-emitting elements 23 .
  • the third quantum dot elements 231 are located on the side of the third light-emitting element 23 away from the substrate, and at least part of the third quantum dot elements 231 is on the substrate 2
  • the orthographic projection of the third light-emitting element 23 overlaps with the orthographic projection of the third light-emitting element 23 on the substrate 2 .
  • the number of quantum dot elements with a unit area (for example: 1000 square micrometers) in the first display area A1 is smaller than the number of quantum dot elements with a unit area (for example: 1000 square micrometers) in the second display area A2; And/or, the number of quantum dot elements with a unit area (eg, 1000 square micrometers) in the first display area A1 is smaller than the number of quantum dot elements with a unit area (eg, 1000 square micrometers) in the third display area A3.
  • the area of the first quantum dot element 211 in the first display area A1 is smaller than the area of the second quantum dot element 221 in the second display area A2 and/or the third quantum dot element 231 in the third display area A3.
  • the distance between the first quantum dot elements 211 in the first display area A1 is greater than the distance between the second quantum dot elements 221 in the second display area A2; and/or the distance between the first quantum dot elements 211 in the first display area A1
  • the distance between a quantum dot element is greater than the distance between the third quantum dot elements 231 in the third display area.
  • the shape of the first quantum dot element 211 in the first display area A1 is different from the shape of the second quantum dot element 221 and/or the third quantum dot element 231.
  • the shape of the first quantum dot element 211 in the first display area A1 is circular, and the second quantum dot element 221 and/or the third quantum dot element 231 is rectangular.
  • the materials of the first quantum dot element 211 , the second quantum dot element 221 and the third quantum dot element 231 may include II-VI compounds, III-V compounds, IV-VI compounds, IV compounds or combinations thereof.
  • the display substrate of the embodiment of the present disclosure further includes an insulating layer 24 located on the quantum dot structure 20 and connected with a plurality of first light-emitting elements 21 and a plurality of second light-emitting elements. 22 and the plurality of third light-emitting elements 23 for isolating the quantum dot structure 20 from the plurality of first light-emitting elements 21 , the plurality of second light-emitting elements 22 and the plurality of third light-emitting elements 23 respectively.
  • the quantum dot structure 20 in the display substrate of the embodiment of the present disclosure also includes a black matrix 25.
  • the black matrix 25 is located between the first quantum dot elements 211 in the first display area A1, between the second quantum dot elements 221 in the second display area A2 and between the third quantum dot elements 231 in the third display area A3.
  • FIG. 2A is a cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • the display substrate may include: a plurality of first light-emitting elements 21 , a plurality of second light-emitting elements 22 , and a plurality of third light-emitting elements 23 , a plurality of first pixel circuits 13 , a plurality of second pixel circuits 11 and a plurality of third pixel circuits 12 .
  • a plurality of first light-emitting elements 21 are located in the first display area A1, a plurality of second light-emitting elements 22, a plurality of first pixel circuits 13 and a plurality of second pixel circuits 11 are located in the second display area A2, and a plurality of third light-emitting elements are located in the second display area A2.
  • 23 and a plurality of third pixel circuits 12 are located in the third display area A3.
  • the first display area A1 may also be called an under-screen sensing area, and the under-screen sensing area may be a light-transmitting display area.
  • the second display area A2 may also be called a buffer area.
  • the third display area A3 may also be called a normal display area.
  • the structures of the first pixel circuit 13, the second pixel circuit 11, and the third pixel circuit 12 may be the same.
  • the size of the first pixel circuit 13, the size of the second pixel circuit 11, and the size of the third pixel circuit 12 may be the same.
  • At least one first pixel circuit 13 is electrically connected to at least one first light-emitting element 21 .
  • one first pixel circuit 13 is electrically connected to two first light-emitting elements 21 through conductive lines.
  • the orthographic projections of the first pixel circuit 13 and the electrically connected first light-emitting element 21 on the substrate may not overlap.
  • At least one second pixel circuit 11 is electrically connected to at least one second light-emitting element 22 .
  • the orthographic projection of the at least one second pixel circuit 11 on the substrate at least partially overlaps the orthographic projection of the at least one second light-emitting element 22 on the substrate.
  • one second pixel circuit 11 is electrically connected to two second light-emitting elements 22 .
  • the orthographic projections of the second pixel circuit 11 and the electrically connected second light-emitting element 22 on the substrate may overlap.
  • At least one third pixel circuit 12 is electrically connected to at least one third light emitting element 23 .
  • the orthographic projection of the at least one third pixel circuit 12 on the substrate at least partially overlaps the orthographic projection of the at least one third light-emitting element 23 on the substrate.
  • the plurality of third pixel circuits 12 and the plurality of third light-emitting elements 23 are electrically connected in a one-to-one correspondence.
  • the orthographic projections of the third pixel circuit 12 and the electrically connected third light-emitting element 23 on the substrate overlap.
  • At least one first pixel circuit may be electrically connected to at least one first light emitting element 21 and at least one second light emitting element 22 .
  • a first pixel circuit 13 is electrically connected to a first light-emitting element 21 and a second light-emitting element 22 respectively through conductive lines.
  • At least one second pixel circuit may be electrically connected to at least one first light emitting element 21 and at least one second light emitting element 22.
  • a second pixel circuit 13 is electrically connected to a first light-emitting element 21 and a second light-emitting element 22 respectively through conductive lines.
  • the first pixel circuit of the second display area A2 may be electrically connected to the first light emitting element 21 through a conductive line.
  • the conductive line may extend from the second display area A2 to the first display area A1.
  • One end of the conductive line can be electrically connected to the first pixel circuit in the second display area A2, and the other end can be electrically connected to the first light-emitting element 21 in the first display area A1, thereby realizing the connection between the first pixel circuit and the first light-emitting element 21. electrical connection between.
  • the conductive threads may be made of transparent conductive materials.
  • conductive lines can be made from conductive oxide materials.
  • the conductive oxide material may include indium tin oxide (ITO).
  • ITO indium tin oxide
  • the first display area A1 is not provided with a pixel circuit
  • the second display area A2 is provided with a plurality of first pixel circuits and a plurality of second pixel circuits 11 .
  • the first pixel circuit may provide a driving signal to the first light-emitting element 21 in the first display area A1 to drive the first light-emitting element 21 to emit light.
  • the second pixel circuit 11 can provide a driving signal to the second light-emitting element 22 in the second display area A2 to drive the second light-emitting element 22 to emit light.
  • the third pixel circuit 12 provided in the third display area A3 can provide a driving signal to the third light-emitting element 23 of the third display area A3 to drive the third light-emitting element 23 to emit light.
  • the first display area A1 is a light-transmitting display area
  • the second display area A2 and the third display area A3 are non-light-transmitting display areas. That is, the first display area A1 can be light-transmissive, and the light transmittance of the second display area A2 and the third display area A3 is less than the light transmittance of the first display area A1; of course, the light transmittance of the third display area A3 can also be It is less than the light transmittance of the second display area A2 and less than the light transmittance of the first display area A1.
  • the first display area A1 since the first display area A1 only includes light-emitting elements and does not include pixel circuits, it can also ensure that the light transmittance of the first display area A1 is good.
  • FIG. 5A is a top view of the light-emitting element in the first display area of the display substrate of the present disclosure
  • FIG. 5B is a top view of the light-emitting element of the second display area of the display substrate of the present disclosure
  • FIG. 5C is a third display area of the display substrate of the present disclosure.
  • the display area AA is arranged with a plurality of pixel units. At least one pixel unit may include: a green (G) light-emitting element, a red (R) light-emitting element, and a blue (B) light-emitting element.
  • a green light-emitting element, a red light-emitting element and a blue light-emitting element are arranged in sequence in the first direction X.
  • the light-emitting elements in this example adopt an RGB arrangement.
  • the first display area A1 is arranged with a plurality of first pixel units, and the first pixel unit may include: a green (G) first light-emitting element 21a, a red (R) first light-emitting element 21b and a blue ( B) First light emitting element 21c.
  • G green
  • R red
  • B blue
  • a green first light-emitting element 21a, a red first light-emitting element 21b and a blue first light-emitting element 21c are sequentially arranged in the first direction X, as shown in FIG. 5A.
  • the second display area A2 is arranged with a plurality of second pixel units.
  • the second pixel unit may include: a green (G) second light-emitting element 22a, a red (R) second light-emitting element 22b and a blue (B) The second light emitting element 22c.
  • a green second light-emitting element 22a, a red second light-emitting element 22b and a blue second light-emitting element 22c are sequentially arranged in the first direction X, as shown in FIG. 5B.
  • the third display area A3 is arranged with a plurality of third pixel units.
  • the third pixel unit may include: a green (G) third light-emitting element 23a, a red (R) third light-emitting element 23b and a blue (B) The third light emitting element 23c.
  • G green
  • R red
  • B blue
  • the third light emitting element 23c A green third light-emitting element 23a, a red third light-emitting element 23b and a blue third light-emitting element 23c are sequentially arranged in the first direction X, as shown in FIG. 5C.
  • FIG. 5D is a second top view of the light-emitting element in the first display area of the display substrate of the present disclosure.
  • this embodiment is not limited to this.
  • a pixel unit may include other colors and other numbers of light-emitting elements.
  • the first display area A1 is arranged with a plurality of first pixel units, and the first pixel unit may include: a green (G) first light-emitting element 21a, a red (R) first light-emitting element 21b, a blue ( B) The first light-emitting element 21c and a white first light-emitting element 21d, a green (G) first light-emitting element 21a, a red (R) first light-emitting element 21b, a blue (B) first light-emitting element 21c and A white first light-emitting element 21d can be arranged horizontally, vertically or vertically.
  • a green (G) first light-emitting element 21a, a red (R) first light-emitting element 21b, a blue (B) first light-emitting element 21c and a white first light-emitting element 21d are arranged horizontally, as shown in Figure Shown in 5D.
  • this embodiment is not limited to this.
  • the display substrate in a plane perpendicular to the display substrate, the display substrate may include:
  • the substrate 2 is located in the first display area A1, the second display area A2 and the third display area A3;
  • the pixel circuit layer includes a plurality of first pixel circuits 13, a plurality of second pixel circuits 11 and a plurality of third pixel circuits 12.
  • the plurality of first pixel circuits 13 and the plurality of second pixel circuits 11 are located in the second display area A2 , and located on one side of the substrate 2;
  • a plurality of third pixel circuits 12 are located in the third display area A3, and located on one side of the substrate 2;
  • a plurality of first light-emitting elements 21, a plurality of second light-emitting elements 22 and a plurality of third light-emitting elements 23 are located in the first display area and on one side of the substrate 2;
  • Two light-emitting elements 22 are located in the second display area A2, and are located on the side of the pixel circuit layer away from the substrate 2;
  • a plurality of third light-emitting elements 23 are located in the third display area A3, and are located on the side of the pixel circuit layer away from the substrate 2;
  • Encapsulation layer 3 the encapsulation layer 3 is located in the first display area A1, the second display area A2 and the third display area A3, and is located in the plurality of first light-emitting elements 21, the plurality of second light-emitting elements 22 and the plurality of third light-emitting elements.
  • 23 is away from the side of the substrate 2 and covers the plurality of first light-emitting elements 21, the plurality of second light-emitting elements 22 and the plurality of third light-emitting elements 23;
  • the second polarizing structure 4 is located in the first display area A1, the second display area A2 and the third display area A3, and is located on the side of the packaging layer 3 away from the substrate 2;
  • Cover plate 5 the cover plate 5 is located in the first display area A1, the second display area A2 and the third display area A3, and is located on the side of the second polarizing structure 4 away from the substrate 2;
  • the first polarizing structure 6 is located in the second display area A2 and the third display area A3, and is located on the side of the substrate 2 away from the pixel circuit layer;
  • the back plate 1 is located in the first display area A1, the second display area A2 and the third display area A3, and is located on the side of the first polarizing structure 6 away from the substrate 2;
  • the first reflective interface 32 is located in the first display area A1, the second display area A2 and the third display area A3, and is at least located on the side of the substrate 2 away from the pixel circuit layer.
  • the first reflective interface 32 diverts at least part of the light. Reflected toward the pixel circuit layer; the first polarizing structure 6 is configured to block the light reflected by the first reflective interface from entering the pixel circuit layer. For example: the first polarizing structure 6 is configured to block the light reflected from the first display area A1 entering the first reflective interface from entering the pixel circuit layer.
  • a first reflective interface 32 is formed at the interface between the surface of the back plate 1 of the display substrate away from the substrate 2 and the outside of the display substrate.
  • the interface between other film layers located on the side of the second polarizing structure away from the substrate in the display substrate of the embodiment of the present disclosure can also form a second reflective interface.
  • the interface of other film layers on the side of the first polarizing structure away from the substrate The interface between other film layers on the side can also form a first reflective interface.
  • this embodiment is not limited to this.
  • the first display area A1 may include: a backplane 1 , a substrate 2 disposed on one side of the backplane 1 , and a substrate 2 disposed far away from the backplane 1 .
  • the first display area A1 is not provided with a pixel circuit layer and a first polarizing structure, and the orthographic projection of the first polarizing structure on the substrate 2 does not overlap with the first display area A1.
  • the second display area A2 may include: a backplane 1, a first polarizing structure 6 disposed on the backplane 1, and a first polarizing structure 6 disposed away from the backplane.
  • the pixel circuit layer includes a plurality of first pixel circuits and a plurality of second pixel circuits 11 .
  • the second display area A2 is provided with a pixel circuit layer and a first polarizing structure 6 .
  • the third display area A3 may include: a backplane 1 , a first polarizing structure 6 disposed on the backplane 1 , and a first polarizing structure 6 disposed away from the backplane.
  • the polarizing structure 4 is away from the cover plate 5 on one side of the back plate 1 .
  • the pixel circuit layer includes a plurality of third pixel circuits 12 .
  • the wiring layer includes multiple signal traces 7 .
  • the third display area A3 is provided with a pixel circuit layer, a wiring layer and a first polarizing structure 6 .
  • the signal trace 7 may include at least one of a scanning line, a data signal line, a ground line, a first driving line and a second driving line.
  • the first display area A1 in the plane perpendicular to the display substrate, does not have a pixel circuit layer, a first polarizing structure and a wiring layer, which can ensure that the first display area A1 The light transmittance is better.
  • the second display area A2 is provided with a pixel circuit layer and a first polarizing structure, and is not provided with a wiring layer.
  • the third display area A3 is provided with a pixel circuit layer, a wiring layer and a first polarizing structure.
  • the second display area A2 in a plane parallel to the display substrate, has 3 or 4 second light-emitting elements arranged in a direction away from the first display area A1 twenty two.
  • the second display area A2 may include a first area a and a second area b in the first direction X, and the first area a and the second area b are located on both sides of the first display area A1 in the first direction X:
  • the first area a and the second area b respectively include a green (G) second light-emitting element, a red (R) second light-emitting element, a blue (B) second light-emitting element, and a green (G) second light-emitting element.
  • the elements, a red (R) second light-emitting element and a blue (B) second light-emitting element are arranged along the first direction X.
  • the radiation area of the dark ring is about 3 to 4 light-emitting elements, and the dark ring gradually decreases along the direction away from the first display area A1.
  • the display substrate of the embodiment of the present disclosure arranges 3 or 4 light-emitting elements in the second display area A2 in a direction away from the first display area A1, so that the dark ring does not extend to the third display area A3 and avoid affecting the third display area A3.
  • the first polarizing structure 6 in a plane parallel to the display substrate, may be located only in the second display area A2 , and the first polarizing structure 6 is in the orthographic projection of the substrate 2 Overlapping with the second display area A2, the orthographic projection of the first polarizing structure 6 on the substrate 2 does not overlap with either the first display area A1 or the third display area A3.
  • the first polarizing structure 6 covers at least three or four light-emitting elements arranged in the direction away from the first display area A1 in the second display area A2.
  • the first polarizing structure 6 is located in the first area a and the second area b of the second display area A2.
  • FIG. 2D is another cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • the display substrate of the embodiment of the present disclosure also includes a light-absorbing layer 40 , which is located in the first display area A1 , the second display area A2 and the third display area A3 , and the light-absorbing layer 40
  • the light absorbing layer 40 is stacked between the first polarizing structure 6 and the first reflective interface 32 .
  • the light absorbing layer 40 is stacked between the first polarizing structure 6 and the back plate 1 .
  • the light absorbing layer 40 is configured to absorb light emitted toward the first reflective interface 32 .
  • the light-absorbing layer 40 has the function of absorbing light and can reduce the light emitted toward the first reflective interface 32, thereby reducing the light reflected by the first reflective interface 32 to the pixel circuit layer, thereby avoiding the occurrence of dark rings and other undesirable phenomena.
  • FIG. 2E is another cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • the display substrate of the embodiment of the present disclosure also includes a light-shielding layer 50 .
  • the light-shielding layer 50 is located in the second display area A2 and the third display area A3 , and the light-shielding layer 50 is stacked on the pixel circuit. The layer is close to the base 2 side.
  • the light-shielding layer 50 blocks light in the second display area A2 and the third display area A3.
  • the light-shielding layer 50 is not located in the first display area A1, and the orthographic projection of the light-shielding layer 50 on the substrate 2 does not overlap with the first display area A1, so as to avoid blocking the light of the first display area A1 and affecting the light transmittance of the first display area A1. .
  • the light-shielding layer 50 forms a mesh structure, and the light-shielding layer 50 includes a pattern area and a hollow area.
  • the orthographic projection of the pattern area of the light-shielding layer 50 on the substrate 2 overlaps with the orthographic projection of the pixel circuit on the substrate 2 .
  • the light-shielding layer forms a network structure, and the light-shielding layer may be located in the first display area A1, the second display area A2, and the third display area A3.
  • the area of the hollow area of the light-shielding layer in the first display area A1 is larger than the area of the hollow area of the light-shielding layer in the second display area A2; and/or, the area of the hollow area of the light-shielding layer in the first display area A1 is larger than the area of the hollow area of the light-shielding layer in the third display area.
  • the substrate 2 may be made of materials such as polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer soft film.
  • PI polyimide
  • PET polyethylene terephthalate
  • surface-treated polymer soft film PI
  • the pixel circuit in the display substrate of the embodiment of the present disclosure may include a transistor and a capacitor, and the transistor may include an active layer, a gate electrode, and a source and drain electrode.
  • the light-emitting element in the display substrate of the embodiment of the present disclosure may be OLED, QLED, Micro-LED or Mini-LED.
  • the light emitting element may include an anode layer, a pixel defining layer, an organic light emitting layer, and a cathode layer.
  • the organic light-emitting layer may include a stacked hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer.
  • the cathode layer of the first display area A1, the cathode layer of the second display area A2, and the cathode layer of the third display area A3 may be an integrated structure.
  • the cathode layer of the display area may be a full-surface cathode.
  • the cathode layer may be a transparent cathode, which may be made of transparent conductive materials such as ITO or IZO.
  • the light-emitting element can emit light from the side away from the substrate through a transparent cathode to achieve a top-emission structure.
  • the cathode layer of the first display area A1 may be a patterned cathode having a hollow area.
  • the embodiment of the present disclosure shows that the encapsulation layer 3 in the substrate may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer.
  • the first encapsulation layer uses inorganic materials
  • the second encapsulation layer uses organic materials
  • the third encapsulation layer uses inorganic materials to cover the first encapsulation layer and the second encapsulation layer.
  • this embodiment is not limited to this.
  • the encapsulation layer may adopt a five-layer structure of inorganic/organic/inorganic/organic/inorganic.
  • the substrate further includes a first dielectric layer, a second dielectric layer, and a third dielectric layer.
  • the first dielectric layer, the second dielectric layer, and the third dielectric layer are along a direction away from the substrate 2 Layer the settings one by one.
  • the first dielectric layer is located in the first display area A1, the second display area A2 and the third display area A3.
  • the first dielectric layer is stacked between the pixel circuit layer and the substrate 2.
  • the second dielectric layer is located in the first display area A1, the second display area A2 and the third display area A3.
  • the second dielectric layer is stacked between the pixel circuit layer and the wiring layer.
  • the third dielectric layer is located in the first display area A1, the second display area A2 and the third display area A3, and the third dielectric layer is stacked between the wiring layer and the light-emitting element.
  • the first dielectric layer, the second dielectric layer and the third dielectric layer may be made of organic materials, such as resin.
  • the display substrate of the embodiment of the present disclosure further includes a first glue layer 8 located in the first display area A1, the second display area A2, and the third display area A3.
  • the first adhesive layer 8 is laminated between the back plate 1 and the first polarizing structure 6; in the first display area A1, the first adhesive layer 8 is laminated between between back plate 1 and base 2.
  • the first adhesive layer 8 is used to bond the first polarizing structure 6 to the back plate 1 and to bond the substrate 2 to the back plate 1 .
  • the first adhesive layer 8 can be pressure-sensitive adhesive (PSA).
  • the display substrate of the embodiment of the present disclosure also includes a second glue layer 9.
  • the second glue layer 9 is located in the first display area A1, the second display area A2, and the third display area A3.
  • the second glue layer 9 9 is stacked between the cover plate 5 and the second polarizing structure 4 .
  • the second adhesive layer 9 is used to bond the cover plate 5 and the second polarizing structure 4 .
  • the second adhesive layer 9 can be optical adhesive (OCA).
  • the embodiment of the present disclosure shows that the substrate further includes a second reflective interface 31 .
  • the second reflective interface 31 is located in the first display area A1, the second display area A2 and the third display area A3, and is at least located on the side of the second polarizing structure 4 away from the substrate 2.
  • the interface between the cover plate 5 of the display substrate away from the substrate 2 and the outside of the display substrate forms a second reflective interface 31 .
  • the second reflective interface 31 forms the light emitted by the at least one first light-emitting element 21 into a reflected light.
  • the light emitted by the at least one first light-emitting element 21 passes through the second reflective interface 31 .
  • Total reflection occurs at 31, forming the above-mentioned reflected light emitted toward the second polarizing structure 4.
  • the second polarizing structure 4 is configured to transmit the above-mentioned reflected light, form the transmitted reflected light into a first circularly polarized light, and emit at least part of the first circularly polarized light toward the first reflective interface 32 .
  • the first reflective interface 32 converts the incident first circularly polarized light into a second circularly polarized light, and reflects at least part of the second circularly polarized light, so that at least part of the second circularly polarized light emits toward the first polarizing structure 6 .
  • the first polarizing structure 6 is configured to block the transmission of the incident second circularly polarized light, thereby blocking the second circularly polarized light from emitting to the first pixel circuit, the second pixel circuit 11 and the third display in the second display area A2
  • the third pixel circuit 12 in the area A3 prevents the light emitted by the first light-emitting element 21 from being reflected by the internal film layer of the display substrate and incident on the pixel circuit in the display substrate, thereby preventing the characteristic deviation of the pixel circuit in the display substrate.
  • Improve the display substrate's negative phenomena such as dark rings and improve the display effect.
  • the optical path of light in the display substrate of the embodiment of the present disclosure is: the first light-emitting element 21 emits light, a part of the light emitted from the display substrate for displaying an image, and a part of the light passes through the second reflective interface.
  • Total reflection occurs at 31, forming reflected light that is emitted toward the second polarizing structure 4; the reflected light is emitted to the second polarizing structure 4, and the second polarizing structure 4 transmits at least part of the reflected light, and forms the transmitted reflected light into the first circular polarization light, and emit at least part of the first circularly polarized light toward the first reflective interface 32; at least part of the first circularly polarized light emits to the first reflective interface 32, and total reflection occurs at the first reflective interface 32, forming a first polarized light toward the first reflective interface 32.
  • the second circularly polarized light emitted from the structure 6 is blocked at the first polarizing structure 6 and cannot transmit the first polarizing structure 6 , thereby preventing the second circularly polarized light from emitting to the second display area A2
  • the first pixel circuit, the second pixel circuit 11 and the third pixel circuit 12 in the third display area A3 can avoid the characteristic deviation of the pixel circuit in the display substrate, improve the dark ring and other undesirable phenomena in the display substrate, and improve the display effect.
  • the orthographic projection of the second polarizing structure 4 on the substrate 2 is the same as the orthographic projection of the plurality of first light-emitting elements 21 on the substrate 2 and the plurality of second light-emitting elements 22 on the substrate 2 .
  • the orthographic projection and the orthographic projection of the plurality of third light-emitting elements 23 overlap on the substrate 2, and at least part of the second polarizing structure 4 covers the plurality of first light-emitting elements 21, the plurality of second light-emitting elements 22 and the plurality of third light-emitting elements. twenty three.
  • the second polarizing structure may be located only in the first display area A1 and not in the second display area A2 and the third display area A3.
  • the orthographic projection of the second polarizing structure on the substrate 2 overlaps with the orthographic projection of the plurality of first light-emitting elements 21 on the substrate 2 , and overlaps with the orthographic projection of the plurality of second light-emitting elements 22 on the substrate 2 and the plurality of third light-emitting elements 23 .
  • Orthographic projections of base 2 do not overlap.
  • the second polarizing structure 4 includes a stacked second retardation film layer 401 and a second linear polarization film layer 402 .
  • the second retardation film layer 401 is located on the second linear polarization film layer. 402 is close to the side of the substrate 2, the second linearly polarizing film layer 402 is configured to transmit the reflected light, and form the transmitted reflected light into the first linearly polarized light, and the second retardation film layer 401 is configured to transmit the first linearly polarized light, And the transmitted first linearly polarized light is formed into a first circularly polarized light.
  • the second retardation film layer is configured to transmit the first linearly polarized light and form the transmitted first linearly polarized light into the first elliptically polarized light.
  • this embodiment is not limited to this.
  • the orthographic projection of the first polarizing structure 6 on the substrate 2 and the orthographic projection of the plurality of second light-emitting elements 22 on the substrate 2 and the plurality of third light-emitting elements 23 on the substrate 2 The orthographic projection overlaps and does not overlap with the orthographic projection of the plurality of first light-emitting elements 21 on the substrate 2 .
  • the first polarizing structure 6 includes a first-order phase difference film layer 601 and a first linear polarization film layer 602 arranged in a stack.
  • the first linear polarization film layer 602 is located at the first-order phase difference layer.
  • the film layer 601 is close to the side of the substrate 2.
  • the first phase difference film layer 601 is configured to transmit the second circularly polarized light and form the transmitted second circularly polarized light into a second linearly polarized light.
  • the first linearly polarized film layer 602 is configured To block the transmission of incident second linearly polarized light.
  • the light vector rotation directions of the first circularly polarized light ray and the second circularly polarized light ray are opposite.
  • the first circularly polarized light can be a left-handed circularly polarized light
  • the second circularly polarized light can be a right-handed circularly polarized light
  • the first circularly polarized light can be a right-handed circularly polarized light
  • the second circularly polarized light can be a left-handed circularly polarized light.
  • Circularly polarized light is not limited to this.
  • the polarization direction of the second linearly polarized light is perpendicular to the polarization direction of the first linearly polarized film layer 602 , so that the second linearly polarized light cannot pass through the first linearly polarized film layer 602 , thereby making the first polarizing structure 6 Preventing the second circularly polarized light from emitting to the first pixel circuit, the second pixel circuit 11 in the second display area A2 and the third pixel circuit 12 in the third display area A3, thereby avoiding characteristic deviation of the pixel circuit in the display substrate. shift.
  • the angle between the transmission axis of the second retardation film layer 401 in the second polarizing structure 4 and the plane of the display substrate may be -5 degrees to 5 degrees.
  • the angle between the transmission axis of the second retardation film layer 401 and the plane of the display substrate may be 0 degrees.
  • the angle between the transmission axis of the first phase difference film layer 601 in the first polarizing structure 6 and the plane of the display substrate may be -5 degrees to 5 degrees.
  • the angle between the transmission axis of the first phase difference film layer 601 and the plane of the display substrate may be 0 degrees.
  • the angle between the transmission axis of the second phase difference film layer 401 and the plane of the display substrate may be the same as the angle between the transmission axis of the first phase difference film layer 601 and the plane of the display substrate.
  • the angles are the same.
  • the angle between the transmission axis of the second phase difference film layer 401 and the plane of the display substrate and the angle between the transmission axis of the first phase difference film layer 601 and the plane of the display substrate can both be 0 degrees. .
  • this embodiment is not limited to this.
  • the angle between the transmission axis of the second phase difference film layer and the plane of the display substrate may also be different from the angle between the transmission axis of the first phase difference film layer and the plane of the display substrate. .
  • the phase difference of the second retardation film layer 401 in the second polarizing structure 4 may be 60 nanometers to 450 nanometers.
  • the phase difference of the second retardation film layer 401 in the second polarizing structure 4 can be 68.75 nanometers, 137.5 nanometers, 206.25 nanometers or 412.5 nanometers.
  • this embodiment is not limited to this.
  • the phase difference of the first phase difference film layer 601 in the first polarizing structure 6 may be 60 nanometers to 450 nanometers.
  • the phase difference of the first phase difference film layer 601 in the first polarizing structure 6 may be 68.75 nanometers, 137.5 nanometers, 206.25 nanometers or 412.5 nanometers.
  • this embodiment is not limited to this.
  • the second retardation film layer 401 may use a quarter wave plate.
  • the angle between the transmission axis direction of the second linearly polarizing film layer 402 and the fast axis of the second retardation film layer 401 in the second polarizing structure 4 may be 40 to 50 degrees; or 130 to 140 degrees.
  • the angle between the transmission axis direction of the second linear polarizing film layer 402 and the fast axis of the second retardation film layer 401 may be 45 degrees or 135 degrees.
  • the second retardation film layer may use a half-wave plate.
  • the fast axis refers to the direction of the light vector that propagates fast.
  • the first phase difference film layer 601 may use a quarter wave plate.
  • the angle between the transmission axis direction of the first linearly polarizing film layer 602 and the fast axis of the first phase difference film layer 601 in the first polarizing structure 6 may be 40 to 50 degrees; or 130 to 140 degrees.
  • the angle between the transmission axis direction of the first linear polarizing film layer 602 and the fast axis of the first phase difference film layer 601 may be 45 degrees or 135 degrees.
  • the first phase difference film layer may use a half-wave plate. However, this embodiment is not limited to this.
  • FIG. 6 is a schematic diagram showing an optical path in a substrate according to an embodiment of the present disclosure.
  • the transmission axis of the second retardation film layer 401 and the transmission axis of the first retardation film layer 601 are both 0 degrees, and the phase difference of the second retardation film layer 401 is 137.5 nanometers
  • the angle between the transmission axis direction of the second linearly polarizing film layer 402 and the fast axis of the second retardation film layer 401 is 45°.
  • the phase difference of the first retardation film layer 601 is 137.5 nanometers.
  • the first linearly polarizing film layer The angle between the transmission axis direction of 602 and the fast axis of the first phase difference film layer 601 is 45° as an example to illustrate the optical path of light in the display substrate according to the embodiment of the present disclosure.
  • the first light-emitting element 21 in the first display area A1 emits light
  • part of the light is emitted from the display substrate for displaying an image
  • part of the light is formed at the interface between the side of the cover 5 away from the light-emitting element and the outside of the display substrate.
  • Total reflection occurs at the second reflective interface 31, forming a reflected light b that is emitted toward the second polarizing structure 4; after the reflected light b passes through the second linear polarizing film layer 402, it forms a fast axis with the second retardation film layer 401.
  • the first linearly polarized light c with an included angle of 45° passes through the second retardation film layer 401 to form a left-handed first circularly polarized light d, and at least part of the first circularly polarized light d Emits toward the first reflective interface 32; at least part of the first circularly polarized light d emits to the first reflective interface 32, and is totally reflected at the first reflective interface 32, forming a right-handed second circularly polarized light e, and the second circularly polarized light e.
  • the light e passes through the first phase difference film layer 601, it forms a second linearly polarized light f with an angle of 135° from the fast axis of the first phase difference film layer 601.
  • the polarization direction of the second linearly polarized light f is consistent with the first phase difference film layer 601.
  • the transmission axis direction of the linearly polarized film layer 602 is vertical, so that the second linearly polarized light f cannot pass through the first linearly polarized film layer 602 , thereby causing the second circularly polarized light e to be blocked at the first polarizing structure 6 .
  • the transmission axis of the second retardation film layer 401 and the transmission axis of the first retardation film layer 601 are both 0 degrees, and the phase difference of the second retardation film layer 401 is 137.5 nanometers
  • the angle between the transmission axis direction of the second linearly polarizing film layer 402 and the fast axis of the second retardation film layer 401 is 45°.
  • the phase difference of the first retardation film layer 601 is 412.5 nanometers.
  • the first linearly polarizing film layer The angle between the transmission axis direction of 602 and the fast axis of the first phase difference film layer 601 is 135° as an example to illustrate the optical path of light in the display substrate according to the embodiment of the present disclosure.
  • the first light-emitting element 21 in the first display area A1 emits light
  • part of the light emits out of the display substrate for displaying an image
  • part of the light is at the second reflective interface 31 formed by the interface between the side of the cover 5 away from the light-emitting element and the outside of the display substrate.
  • Total reflection occurs, forming reflected light that is emitted toward the second polarizing structure 4; after passing through the second linearly polarizing film layer 402, the reflected light forms an angle of 45° with the fast axis of the second retardation film layer 401.
  • the first linearly polarized light passes through the second retardation film layer 401 to form a left-handed first circularly polarized light, and at least part of the first circularly polarized light emits toward the first reflective interface 32; at least part of the first circularly polarized light emits toward the first reflective interface 32; The circularly polarized light emits to the first reflective interface 32 and undergoes total reflection at the first reflective interface 32 to form a right-handed second circularly polarized light.
  • the second circularly polarized light passes through the first phase difference film layer 601, it forms The angle between the fast axes of the first phase difference film layer 601 is 45° for the second linearly polarized light, and the polarization direction of the second linearly polarized light is perpendicular to the transmission axis direction of the first linearly polarized film layer 602, so that the second linearly polarized light It cannot pass through the first linearly polarizing film layer 602 , so that the second circularly polarized light is blocked at the first polarizing structure 6 .
  • the display substrate of the embodiment of the present disclosure also includes a composite film 10.
  • the composite film 10 is located in the second display area A2 and the third display area A3. That is, the orthographic projection of the composite film 10 on the substrate 2 is in line with the first display area.
  • the area A1 does not overlap, but overlaps with the second display area A2 and the third display area A3.
  • the composite film 10 is stacked on the side of the back plate 1 away from the substrate 2 .
  • the orthographic projection of the composite film 10 on the substrate 2 does not overlap with the first display area A1, which can prevent the composite film 10 from reducing the light transmittance of the first display area A1.
  • the composite film 10 may be a super clean foam (SCF) composite film.
  • the composite film 10 generally includes an adhesive layer, a buffer layer and a heat dissipation layer sequentially laminated in a direction away from the back plate 1 .
  • the composite film 10 can buffer the stress acting on the display substrate, dissipate the heat generated when the display substrate is working, and provide a certain protection effect on the display substrate.
  • FIG. 2B is another cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • the first display area A1 may include: a backplane 1 , a first polarizing structure 6 disposed on the backplane 1 , A polarizing structure 6 on the side of the substrate 2 away from the back plate 1 , a plurality of first light-emitting elements 21 arranged on the side of the substrate 2 far away from the back plate 1 , and a package arranged on the side of the plurality of first light-emitting elements 21 away from the back plate 1 Layer 3, a second polarizing structure 4 disposed on the side of the encapsulation layer 3 away from the back plate 1, and a cover plate 5 disposed on the side of the second polarizing structure 4 away from the back plate 1.
  • the first display area A1 is not provided with a pixel circuit layer
  • the first phase difference film layer 601 in the first polarizing structure 6 overlaps with the first display area A1 in the orthographic projection of the substrate
  • the first phase difference film layer 601 in the first polarizing structure 6 overlaps with the first display area A1.
  • the orthographic projection of the linear polarizing film layer 602 on the substrate does not overlap with the first display area A1 to prevent the first linear polarizing film layer 602 from reducing the light transmittance of the first display area A1.
  • the second display area A2 may include: a backplane 1 , a first polarizing structure 6 disposed on the backplane 1 , and a first polarizing structure 6 disposed away from the backplane.
  • the pixel circuit layer includes a plurality of first pixel circuits and a plurality of second pixel circuits 11 .
  • the second display area A2 is provided with a pixel circuit layer and a first polarizing structure.
  • the third display area A3 may include: a backplane 1 , a first polarizing structure 6 disposed on the backplane 1 , and a first polarizing structure 6 disposed away from the backplane.
  • the polarizing structure 4 is away from the cover plate 5 on one side of the back plate 1 .
  • the pixel circuit layer includes a plurality of third pixel circuits 12 .
  • the wiring layer includes multiple signal traces 7 .
  • the third display area A3 is provided with a pixel circuit layer, a wiring layer and a first polarizing structure 6
  • the first display area A1 in the plane perpendicular to the display substrate, the first display area A1 does not have a pixel circuit layer and a wiring layer, and the first phase difference film layer in the first polarizing structure 6 601 is located in the first display area A1, and the first linear polarizing film layer 602 in the first polarizing structure 6 is not located in the first display area A1.
  • the second display area A2 is provided with a pixel circuit layer and a first polarizing structure, and is not provided with a wiring layer.
  • the third display area A3 is provided with a pixel circuit layer, a wiring layer and a first polarizing structure.
  • the transmission axis of the second retardation film layer 401 and the transmission axis of the first retardation film layer 601 are both 0 degrees, and the phase difference of the second retardation film layer 401 is 137.5 nanometers
  • the angle between the transmission axis direction of the second linearly polarizing film layer 402 and the fast axis of the second retardation film layer 401 is 45°.
  • the phase difference of the first retardation film layer 601 is 68.75 nanometers.
  • the first linearly polarizing film layer The angle between the transmission axis direction of 602 and the fast axis of the first phase difference film layer 601 is 45° as an example to illustrate the optical path of light in the display substrate according to the embodiment of the present disclosure.
  • the first light-emitting element 21 in the first display area A1 emits light
  • part of the light emits out of the display substrate for displaying an image
  • part of the light is at the second reflective interface 31 formed by the interface between the side of the cover 5 away from the light-emitting element and the outside of the display substrate.
  • Total reflection occurs, forming reflected light that is emitted toward the second polarizing structure 4; after passing through the second linearly polarizing film layer 402, the reflected light forms an angle of 45° with the fast axis of the second retardation film layer 401.
  • the first linearly polarized light passes through the second retardation film layer 401 to form a left-handed first circularly polarized light, and at least part of the first circularly polarized light emits toward the first reflective interface 32; at least part of the first circularly polarized light emits toward the first reflective interface 32; The circularly polarized light emits to the first reflective interface 32 and undergoes total reflection at the first reflective interface 32 to form a right-handed second circularly polarized light.
  • the second circularly polarized light passes through the first phase difference film layer 601, it forms a
  • the angle between the fast axes of the first phase difference film layer 601 is 135° for the second linearly polarized light, and the polarization direction of the second linearly polarized light is perpendicular to the transmission axis direction of the first linearly polarized film layer 602, so that the second linearly polarized light It cannot pass through the first linearly polarizing film layer 602 , so that the second circularly polarized light is blocked at the first polarizing structure 6 .
  • the transmission axis of the second retardation film layer 401 and the transmission axis of the first retardation film layer 601 are both 0 degrees, and the phase difference of the second retardation film layer 401 is 137.5 nanometers
  • the angle between the transmission axis direction of the second linear polarizing film layer 402 and the fast axis of the second phase difference film layer 401 is 45°.
  • the phase difference of the first phase difference film layer 601 is 206.25 nanometers.
  • the first linear polarizing film layer The angle between the transmission axis direction of 602 and the fast axis of the first phase difference film layer 601 is 135° as an example to illustrate the optical path of light in the display substrate according to the embodiment of the present disclosure.
  • the first light-emitting element 21 in the first display area A1 emits light
  • part of the light emits out of the display substrate for displaying an image
  • part of the light is at the second reflective interface 31 formed by the interface between the side of the cover 5 away from the light-emitting element and the outside of the display substrate.
  • Total reflection occurs, forming reflected light that is emitted toward the second polarizing structure 4; after passing through the second linearly polarizing film layer 402, the reflected light forms an angle of 45° with the fast axis of the second retardation film layer 401.
  • the first linearly polarized light passes through the second retardation film layer 401 to form a left-handed first circularly polarized light, and at least part of the first circularly polarized light emits toward the first reflective interface 32; at least part of the first circularly polarized light emits toward the first reflective interface 32; The circularly polarized light emits to the first reflective interface 32 and undergoes total reflection at the first reflective interface 32 to form a right-handed second circularly polarized light.
  • the second circularly polarized light passes through the first phase difference film layer 601, it forms a
  • the angle between the fast axes of the first phase difference film layer 601 is 45° for the second linearly polarized light, and the polarization direction of the second linearly polarized light is perpendicular to the transmission axis direction of the first linearly polarized film layer 602, so that the second linearly polarized light It cannot pass through the first linearly polarizing film layer 602 , so that the second circularly polarized light is blocked at the first polarizing structure 6 .
  • FIG. 3 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • the present disclosure provides a display device, including: a display substrate 100 and a photosensitive sensor 200 located on a light-emitting side away from the display substrate 100 . There is an overlapping area between the orthographic projection of the photosensitive sensor 200 on the display substrate 100 and the first display area A1 in the display substrate.
  • the display substrate 100 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate.
  • the display device may be: an OLED display, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • the embodiments of the present disclosure are not limited thereto.
  • the present disclosure provides a method for preparing a display substrate.
  • the display substrate can be any of the above-mentioned display substrates.
  • the display substrate includes a first display area and a second display area, and the second display area is located in the first display area. At least one side of a display area, the first display area is the under-screen sensing area; the preparation method of the display substrate includes:
  • a first reflective interface is formed at least on the side of the substrate away from the pixel circuit layer, and the first reflective interface is located at least in the first display area and the second display area; the first reflective interface will At least part of the light is reflected toward the pixel circuit layer;
  • At least a first polarizing structure is formed between the substrate and the first reflective interface, and at least part of the first polarizing structure is located in the second display area, and the first polarizing structure is configured to block the first polarizing structure.
  • the light reflected by a reflective interface is incident on the pixel circuit layer.

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Abstract

一种显示基板及其制备方法、显示装置，该显示基板包括第一显示区（A1）和第二显示区（A2），该第二显示区位于该第一显示区的至少一侧，该第一显示区为屏下传感区域；该显示基板至少包括：基底（2），至少位于该第一显示区和该第二显示区；像素电路层，至少部分该像素电路层位于该第二显示区，且位于该基底一侧；第一反射界面（32），至少位于该第一显示区和该第二显示区，且位于该基底远离该像素电路层的一侧；该第一反射界面将至少部分光线朝向该像素电路层反射；第一偏光结构（6），至少部分该第一偏光结构位于该第二显示区，且至少部分该第一偏光结构位于该基底与该第一反射界面之间，该第一偏光结构被配置为阻挡该第一反射界面反射的光线入射该像素电路层。

Description

显示基板及其制备方法、显示装置 技术领域
本公开涉及但不限于显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
随着显示技术的不断发展，为了实现屏占比最大化，先后出现了刘海屏、水滴屏、屏内挖孔等技术。这些技术是通过在显示区的局部设置屏下传感区域，例如：在屏下传感区域的下方放置摄像头来减小摄像头占据周边区的面积，进而提高屏占比；然而，上述显示设备在屏下传感区域附近会出现暗环等不良现象，影响显示效果。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括第一显示区和第二显示区，所述第二显示区位于所述第一显示区的至少一侧，所述第一显示区为屏下传感区域；所述显示基板至少包括：
基底，至少位于所述第一显示区和所述第二显示区；
像素电路层，至少部分所述像素电路层位于所述第二显示区，且位于所述基底一侧；
第一反射界面，至少位于所述第一显示区和所述第二显示区，且位于所述基底远离所述像素电路层的一侧；所述第一反射界面将至少部分光线朝向所述像素电路层反射；
第一偏光结构，至少部分所述第一偏光结构位于所述第二显示区，且至 少部分所述第一偏光结构位于所述基底与所述第一反射界面之间，所述第一偏光结构被配置为阻挡所述第一反射界面反射的光线入射所述像素电路层。
在示例性实施方式中，还包括第三显示区，所述第三显示区位于所述第一显示区和所述第二显示区的至少一侧，至少部分所述像素电路层位于所述第三显示区，至少部分所述第一偏光结构位于所述第三显示区。
在示例性实施方式中，还包括：
多个第一发光元件，位于所述第一显示区，且位于所述基底远离所述第一反射界面一侧；
第二反射界面，至少位于所述第一显示区和所述第二显示区，且至少位于所述多个第一发光元件远离所述基底一侧，所述第二反射界面将至少一个第一发光元件发出的光线形成反射光线；
第二偏光结构，至少位于所述第一显示区和所述第二显示区，且至少位于所述多个第一发光元件与所述第二反射界面之间，所述第二偏光结构被配置为透射所述反射光线，使透射的所述反射光线形成第一圆偏振光线，并将所述第一圆偏振光线朝向所述第一反射界面出射；
所述第一反射界面被配置为将入射的所述第一圆偏振光线形成第二圆偏振光线，并将至少部分所述第二圆偏振光线反射至所述第一偏光结构；所述所述第一偏光结构被配置为阻挡所述第二圆偏振光线入射所述像素电路层。
在示例性实施方式中，所述第二偏光结构包括层叠设置的第二线偏光膜层和第二位相差膜层，所述第二位相差膜层位于所述第二线偏光膜层靠近所述基底一侧，所述第二线偏光膜层被配置为透射所述反射光线，并将透射的所述反射光线形成第一线偏振光线，所述第二位相差膜层被配置为透射所述第一线偏振光线，并将透射的所述第一线偏振光线形成所述第一圆偏振光线。
在示例性实施方式中，所述第一偏光结构包括层叠设置的第一线偏光膜层和第一位相差膜层，所述第一位相差膜层位于所述第一线偏光膜层靠近所述基底一侧，所述第一位相差膜层被配置为透射所述第二圆偏振光线，并将透射的所述第二圆偏振光线形成第二线偏振光线，所述第一线偏光膜层被配置为阻挡入射的所述第二线偏振光线透射。
在示例性实施方式中，所述第二线偏振光线的偏振方向与所述第一线偏光膜层的偏振方向垂直。
在示例性实施方式中，所述第一线偏光膜层在所述基底的正投影与所述第一显示区不交叠，至少部分所述第一位相差膜层在所述基底的正投影与所述第一显示区交叠。
在示例性实施方式中，所述第一偏光结构在所述基底的正投影与所述第一显示区不交叠。
在示例性实施方式中，还包括：背板，所述背板至少位于所述第一显示区和所述第二显示区，且所述背板至少位于所述第一偏光结构远离所述基底一侧，所述背板远离所述基底一侧表面与所述显示基板外侧的交界形成所述第一反射界面。
在示例性实施方式中，还包括：复合膜，所述复合膜至少位于所述第二显示区，所述复合膜至少位于所述背板远离所述基底一侧，所述复合膜在所述基底的正投影与所述第一显示区不交叠。
在示例性实施方式中，还包括：盖板，所述盖板至少位于所述第一显示区和所述第二显示区，所述盖板位于所述第二偏光结构远离所述基底一侧，所述盖板远离所述基底一侧表面与所述显示基板外侧的交界形成所述第二反射界面。
在示例性实施方式中，还包括：封装层，所述封装层至少位于所述第一显示区和所述第二显示区，所述封装层位于所述像素电路层远离所述基底一侧。
在示例性实施方式中，还包括：多个第二发光元件，所述像素电路层包括多个第一像素电路和多个第二像素电路，所述多个第二发光元件、所述多个第一像素电路和所述多个第二像素电路均位于所述第二显示区，所述多个第二发光元件位于所述像素电路层远离所述基底一侧，所述第一像素电路与所述第一发光元件电连接，所述第二像素电路与所述第二发光元件电连接。
在示例性实施方式中，所述第一发光元件之间的间距，大于所述第二发光元件之间的间距；和/或，所述第一发光元件的面积小于所述第二发光元的 面积。
在示例性实施方式中，所述第二显示区在远离所述第一显示区的方向上排布有3或4个第二发光元件。
在示例性实施方式中，所述第一偏光结构在所述基底的正投影与所述3或4个第二发光元件在所述基底的正投影交叠。
在示例性实施方式中，还包括吸光层，所述吸光层至少位于所述第一显示区和所述第二显示区，且所述吸光层层叠设置在所述第一偏光结构与所述第一反射界面之间。
在示例性实施方式中，还包括遮光层，所述遮光层位于所述第二显示区，所述遮光层在基底的正投影与所述第一显示区不交叠，所述遮光层层叠设置在所述像素电路层靠近所述基底一侧。
另一方面，本公开还提供了一种显示装置，包括前面任一所述的显示基板以及感光传感器，所述感光传感器位于远离所述显示基板的出光侧的一侧，所述感光传感器在所述显示基板上的正投影与所述显示基板中第一显示区存在交叠区域。
另一方面，本公开还提供了一种显示基板的制备方法，所述显示基板包括第一显示区和第二显示区，所述第二显示区位于所述第一显示区的至少一侧，所述第一显示区为屏下传感区域；所述显示基板的制备方法包括：
至少在所述第一显示区和所述第二显示区中形成基底；
至少在所述第二显示区的基底上形成像素电路层；
至少在所述基底远离所述像素电路层的一侧形成第一反射界面，且所述第一反射界面至少位于所述第一显示区和所述第二显示区；所述第一反射界面将至少部分光线朝向所述像素电路层反射；
至少在所述基底与所述第一反射界面之间形成第一偏光结构，且至少部分所述第一偏光结构位于所述第二显示区，所述第一偏光结构被配置为阻挡所述第一反射界面反射的光线入射所述像素电路层。
在阅读并理解了附图和详细描述后，可以明白其它方面。
附图说明
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1A为本公开实施例的显示基板的一种示意图；
图1B为本公开实施例的显示基板的另一示意图；
图2A为本公开实施例的显示基板的一种剖视图；
图2B为本公开实施例的显示基板的另一种剖视图；
图2C为本公开实施例的显示基板的另一种剖视图；
图2D为本公开实施例的显示基板的另一种剖视图；
图2E为本公开实施例的显示基板的另一种剖视图；
图3为本公开实施例的显示装置的示意图；
图4为相关技术的显示基板的一种示意图；
图5A为本公开显示基板中第一显示区的发光元件的俯视图一；
图5B为本公开显示基板中第二显示区的发光元件的俯视图；
图5C为本公开显示基板中第三显示区的发光元件的俯视图；
图5D为本公开显示基板中第一显示区的发光元件的俯视图二；
图6为本公开实施例显示基板中光路的示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。 因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互 相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图4为相关技术的显示基板的一种示意图。如图4所示，相关技术的显示基板包括屏下传感区域B1以及位于屏下传感区域B1周侧的显示区域B2，例如：屏下传感为屏下传感摄像头(FDC，Full Display with Camera)区域B1；屏下传感区域B1包括基底以及设置在基底上的多个第一发光元件b1，显示区域B2包括基底以及设置在基底上的多个第二发光元件b2以及像素电路层b3，多个第二发光元件b2位于像素电路层b3远离基底一侧。
经过本申请发明人的研究发现，屏下传感区域B1的第一发光元件b1发出的光线，会在显示基板的内部膜层发生反射，照射到显示区域B2的像素电路层b3，引起像素电路层b3的特性正偏，使第二发光元件b2发光，辐射面积约3～4个第二发光元件b2，产生暗环等不良现象，影响显示效果。其中，暗环沿着远离屏下传感区域B1逐渐减轻。
本申请发明人将屏下传感区域B1的背光侧涂黑，使显示区域B2的第二显示单元b2接收到的光强减小，暗环响应的减小，减小比例约38％。
本公开实施例提供了一种显示基板，包括第一显示区和第二显示区，所 述第二显示区位于所述第一显示区的至少一侧，所述第一显示区为屏下传感区域；所述显示基板至少包括：
基底，至少位于所述第一显示区和所述第二显示区；
像素电路层，至少部分所述像素电路层位于所述第二显示区，且位于所述基底一侧；
第一反射界面，至少位于所述第一显示区和所述第二显示区，且位于所述基底远离所述像素电路层的一侧；所述第一反射界面将至少部分光线朝向所述像素电路层反射；
第一偏光结构，至少部分所述第一偏光结构位于所述第二显示区，且至少部分所述第一偏光结构位于所述基底与所述第一反射界面之间，所述第一偏光结构被配置为阻挡所述第一反射界面反射的光线入射所述像素电路层。
下面通过一些示例对本实施例的方案进行举例说明。
图1A为本公开实施例的显示基板的一种示意图。图1B为本公开实施例的显示基板的另一示意图。在示例性实施方式中，如图1A和图1B所示，显示基板包括：显示区域AA和位于显示区域AA周边的边框区域BB。显示区域AA可以包括：第一显示区A1、第二显示区A2和第三显示区A3。第二显示区A2可以位于第一显示区A1的至少一侧。第三显示区A3位于第一显示区A1和第二显示区A2的至少一侧。显示区域AA内除第一显示区A1和第二显示区A2以外的区域为第三显示区A3。其中，第一显示区A1还可以称为屏下传感区域，例如：屏下摄像头(FDC，Full Display with Camera)区域，第二显示区A2还可以称为缓冲区，第三显示区A3还可以称为正常显示区。然而，本实施例对此并不限定。
在示例性实施方式中，如图1A和图1B所示，第一显示区A1和第二显示区A2可以位于显示基板的顶部正中间位置。然而，本实施例对此并不限定。例如，第一显示区A1和第二显示区A2可以位于显示基板的左上角或右上角位置等其他位置。
在示例性实施方式中，如图1A和图1B所示，第二显示区A2可以在第一方向X上位于第一显示区A1的相对两侧。然而，本实施例对此并不限定。 例如，第二显示区可以在第一方向上位于第一显示区一侧，或者，可以在第二方向上位于第一显示区的至少一侧。
在示例性实施方式中，如图1A和图1B所示，显示区域AA可以为矩形，例如，圆角矩形。如图1A所示，第一显示区A1可以为圆形或椭圆形。如图1B所示，第一显示区A1可以为矩形。然而，本实施例对此并不限定。例如，第一显示区可以为其他四边形或五边形等形状。
在示例性实施方式中，第一显示区A1还可以称为屏下传感区域，屏下传感区域可以为透光显示区域。感光传感器(如，摄像头)等硬件在显示基板上的正投影可以位于显示基板的第一显示区A1内。本示例的显示基板无需打孔，在确保显示基板实用性的前提下，可以使真全面屏成为可能。在一些示例中，如图1A所示，第一显示区A1可以为圆形，感光传感器在显示基板上的正投影的尺寸可以小于或等于第一显示区A1的尺寸。在另一些示例中，如图1B所示，第一显示区A1可以为矩形，感光传感器在显示基板上的正投影的尺寸可以小于或等于第一显示区A1的内切圆的尺寸。然而，本实施例对此并不限定。
在示例性实施方式中，显示基板可以包括：设置在基底上的多个子像素，至少一个子像素可以包括像素电路和发光元件。像素电路配置为驱动发光元件。例如，像素电路配置为提供驱动电流以驱动发光元件发光。例如，发光元件可以为有机发光二极管(OLED)，发光元件在其对应的像素电路的驱动下发出红光、绿光、蓝光、或者白光等。发光元件发光的颜色可根据需要而定。
在示例性实施方式中，为了提高第一显示区A1的光透过率，可以在第一显示区A1仅设置发光元件，而将驱动第一显示区A1的发光元件的像素电路设置在第二显示区A2。即，通过发光元件和像素电路分离设置的方式来提高第一显示区A1的光透过率。在本示例中，在第一显示区A1，不设置像素电路。
当然，也可以在第一显示区A1，设置像素电路。例如：在第一显示区A1设置岛状像素电路，在第一显示区A1单元面积(例如：1000平方微米)的像素电路数量小于在第三显示区A3的像素电路数量。
可选的，第一显示区A1的第一发光元件21的面积小于第二发光元件22和/或第三发光元件23的面积。例如：第一显示区A1的至少一种颜色的第一发光元件21(例如：红色R)的面积小于对应颜色的第二发光元件22(例如：红色R)和/或第三发光元件23(例如：红色R)的面积。可选的，第一显示区A1的第一发光元件21之间的间距，大于第二显示区A2的第二发光元件22之间的间距；和/或，第一显示区A1的第一发光元件21之间的间距大于第三显示区A3的第三发光元件23之间的间距。
可选的，第一显示区A1的第一发光元件21的形状与第二发光元件22和/或第三发光元件23的形状不同。例如：第一显示区A1的第一发光元件21的形状为圆形，第二发光元件22和/或第三发光元件23为矩形。
图2C为本公开实施例的显示基板的另一种剖视图。在示例性实施方式中，如图2C所示，本公开实施例的显示基板包括基底2以及设置在基底2上的多个第一发光元件21、多个第二发光元件22以及多个第三发光元件23，多个第一发光元件21位于第一显示区A1，多个第二发光元件22位于第二显示区A2，多个第三发光元件23位于第三显示区A3。在第一发光元件21，第二发光元件22，第三发光元件23对应位置的上方或下方可以设置相应颜色的量子点结构20。示例性的，第一发光元件21，第二发光元件22，第三发光元件23中的红色发光元件(R)上方设置红色量子点元件。例如：量子点结构20包括多个第一量子点元件211，多个第二量子点元件221，多个第三量子点元件231。多个第一量子点元件211与多个第一发光元件21一一对应设置，第一量子点元件211位于第一发光元件21远离基底一侧，且至少部分第一量子点元件211在基底2的正投影与第一发光元件21在基底2的正投影交叠。多个第二量子点元件221与多个第二发光元件22一一对应设置，第二量子点元件221位于第二发光元件22远离基底一侧，且至少部分第二量子点元件221在基底2的正投影与第二发光元件22在基底2的正投影交叠。多个第三量子点元件231与多个第三发光元件23一一对应设置，第三量子点元件231位于第三发光元件23远离基底一侧，且至少部分第三量子点元件231在基底2的正投影与第三发光元件23在基底2的正投影交叠。
可选的，第一显示区A1中的单元面积(例如：1000平方微米)的量子 点元件的数量小于第二显示区A2中的单元面积(例如：1000平方微米)的量子点元件的数量；和/或，第一显示区A1中的单元面积(例如：1000平方微米)的量子点元件的数量小于第三显示区A3中的单元面积(例如：1000平方微米)的量子点元件的数量。
可选的，第一显示区A1的第一量子点元件211的面积小于第二显示区A2第二量子点元件221和/或第三显示区A3第三量子点元件231的面积。可选的，第一显示区A1的第一量子点元件211之间的间距，大于第二显示区A2的第二量子点元件221之间的间距；和/或，第一显示区A1的第一量子点元件之间的间距大于第三显示区的第三量子点元件231之间的间距。
可选的，第一显示区A1的第一量子点元件211的形状与第二量子点元件221和/或第三量子点元件231的形状不同。例如：第一显示区A1的第一量子点元件211的形状为圆形，第二量子点元件221和/或第三量子点元件231为矩形。
在示例性实施方式中，第一量子点元件211、第二量子点元件221和第三量子点元件231的材料可以包括II-VI族化合物、III-V族化合物、IV-VI族化合物、IV族化合物或其组合。
在示例性实施方式中，如图2C所示，本公开实施例的显示基板还包括绝缘层24，绝缘层24位于量子点结构20，与多个第一发光元件21、多个第二发光元件22以及多个第三发光元件23之间，用于将量子点结构20分别与多个第一发光元件21、多个第二发光元件22以及多个第三发光元件23隔离。
在示例性实施方式中，如图2C所示，本公开实施例的显示基板中量子点结构20还包括黑矩阵25，黑矩阵25位于第一显示区A1中第一量子点元件211之间、第二显示区A2中第二量子点元件221之间以及第三显示区A3中第三量子点元件231之间。
图2A为本公开实施例的显示基板的一种剖视图。在示例性实施方式中，如图2A所示，在垂直于显示基板的平面内，显示基板可以包括：多个第一发光元件21、多个第二发光元件22、多个第三发光元件23、多个第一像素电路13、多个第二像素电路11以及多个第三像素电路12。多个第一发光元件21位于第一显示区A1，多个第二发光元件22、多个第一像素电路13和 多个第二像素电路11位于第二显示区A2，多个第三发光元件23和多个第三像素电路12位于第三显示区A3。第一显示区A1还可以称为屏下传感区域，屏下传感区域可以为透光显示区域。第二显示区A2还可以称为缓冲区。第三显示区A3还可以称为正常显示区。第一像素电路13的结构、第二像素电路11的结构和第三像素电路12的结构可以相同。第一像素电路13的尺寸、第二像素电路11的尺寸和第三像素电路12的尺寸可以相同。
在示例性实施方式中，如图2A所示，至少一个第一像素电路13与至少一个第一发光元件21电连接。例如，一个第一像素电路13通过导电线与两个第一发光元件21电连接。第一像素电路13与电连接的第一发光元件21在基底上的正投影可以没有交叠。至少一个第二像素电路11与至少一个第二发光元件22电连接。至少一个第二像素电路11在基底的正投影与至少一个第二发光元件22在基底的正投影至少部分交叠。例如，一个第二像素电路11与两个第二发光元件22电连接。第二像素电路11与电连接的第二发光元件22在基底上的正投影可以存在交叠。至少一个第三像素电路12与至少一个第三发光元件23电连接。至少一个第三像素电路12在基底的正投影与至少一个第三发光元件23在基底的正投影至少部分交叠。例如，多个第三像素电路12与多个第三发光元件23一一对应电连接。第三像素电路12与电连接的第三发光元件23在基底上的正投影存在交叠。
在一些实施例中，至少一个第一像素电路可以与至少一个第一发光元件21和至少一个第二发光元件22电连接。例如，一个第一像素电路13通过导电线分别与一个第一发光元件21和一个第二发光元件22电连接。至少一个第二像素电路可以与至少一个第一发光元件21和至少一个第二发光元件22电连接。例如，一个第二像素电路13通过导电线分别与一个第一发光元件21和一个第二发光元件22电连接。
在示例性实施方式中，第二显示区A2的第一像素电路可以通过导电线与第一发光元件21电连接。导电线可以从第二显示区A2延伸到第一显示区A1。导电线的一端可以在第二显示区A2与第一像素电路电连接，另一端可以在第一显示区A1与第一发光元件21电连接，从而实现第一像素电路与第一发光元件21之间的电连接。在一些示例中，导电线可以采用透明导电材料 制作。例如，导电线可以采用导电氧化物材料制作。例如，导电氧化物材料可以包括氧化铟锡(ITO)。然而，本实施例对此并不限定。
在示例性实施方式中，如图2A所示，第一显示区A1没有设置像素电路，第二显示区A2设置有多个第一像素电路和多个第二像素电路11。第一像素电路可以给第一显示区A1的第一发光元件21提供驱动信号，以驱动第一发光元件21发光。第二像素电路11可以给第二显示区A2的第二发光元件22提供驱动信号，以驱动第二发光元件22发光。第三显示区A3设置的第三像素电路12可以给第三显示区A3的第三发光元件23提供驱动信号，以驱动第三发光元件23发光。
在示例性实施方式中，第一显示区A1为透光显示区域，第二显示区A2和第三显示区A3为非透光显示区。即，第一显示区A1可以透光，第二显示区A2和第三显示区A3透光率小于第一显示区A1的透光率；当然，还可以是第三显示区A3的透光率小于第二显示区A2透光率，且小于第一显示区A1的透光率。如此一来，无需在显示基板上进行挖孔处理，可以将感光传感器等所需硬件结构直接设置于第一显示区的下方，为真全面屏的实现奠定坚实的基础。并且，由于第一显示区A1内仅包括发光元件，而不包括像素电路，还可以确保第一显示区A1的光透过率较好。
图5A为本公开显示基板中第一显示区的发光元件的俯视图一；图5B为本公开显示基板中第二显示区的发光元件的俯视图；图5C为本公开显示基板中第三显示区的发光元件的俯视图。在示例性实施方式中，显示区域AA排布有多个像素单元。至少一个像素单元可以包括：一个绿色(G)发光元件、一个红色(R)发光元件和一个蓝色(B)发光元件。一个绿色发光元件、一个红色发光元件和一个蓝色发光元件在第一方向X上依次排布。本示例的发光元件采用RGB的排布方式。例如，第一显示区A1排布有多个第一像素单元，第一像素单元可以包括：一个绿色(G)第一发光元件21a、一个红色(R)第一发光元件21b和一个蓝色(B)第一发光元件21c。一个绿色第一发光元件21a、一个红色第一发光元件21b和一个蓝色第一发光元件21c在第一方向X上依次排布，如图5A所示。第二显示区A2排布有多个第二像素单元，第二像素单元可以包括：一个绿色(G)第二发光元件22a、一个红 色(R)第二发光元件22b和一个蓝色(B)第二发光元件22c。一个绿色第二发光元件22a、一个红色第二发光元件22b和一个蓝色第二发光元件22c在第一方向X上依次排布，如图5B所示。第三显示区A3排布有多个第三像素单元，第三像素单元可以包括：一个绿色(G)第三发光元件23a、一个红色(R)第三发光元件23b和一个蓝色(B)第三发光元件23c。一个绿色第三发光元件23a、一个红色第三发光元件23b和一个蓝色第三发光元件23c在第一方向X上依次排布，如图5C所示。
图5D为本公开显示基板中第一显示区的发光元件的俯视图二。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括其他颜色以及其他数量的发光元件。例如，第一显示区A1排布有多个第一像素单元，第一像素单元可以包括：一个绿色(G)第一发光元件21a、一个红色(R)第一发光元件21b、一个蓝色(B)第一发光元件21c以及一个白色第一发光元件21d，一个绿色(G)第一发光元件21a、一个红色(R)第一发光元件21b、一个蓝色(B)第一发光元件21c以及一个白色第一发光元件21d可以采用水平并列、竖直并列或品字方式排列。示例的，一个绿色(G)第一发光元件21a、一个红色(R)第一发光元件21b、一个蓝色(B)第一发光元件21c以及一个白色第一发光元件21d采用水平并列，如图5D所示。然而，本实施例对此并限定。
在示例性实施方式中，如图2A所示，在垂直于显示基板的平面内，显示基板可以包括：
基底2，位于第一显示区A1、第二显示区A2和第三显示区A3；
像素电路层，包括多个第一像素电路13、多个第二像素电路11和多个第三像素电路12，多个第一像素电路13、多个第二像素电路11位于第二显示区A2，且位于基底2的一侧；多个第三像素电路12位于第三显示区A3，且位于基底2的一侧；
多个第一发光元件21、多个第二发光元件22和多个第三发光元件23，多个第一发光元件21位于所述第一显示区，且位于基底2的一侧；多个第二发光元件22位于第二显示区A2，且位于像素电路层远离基底2一侧；多个 第三发光元件23位于第三显示区A3，且位于像素电路层远离基底2一侧；
封装层3，封装层3位于第一显示区A1、第二显示区A2和第三显示区A3，且位于多个第一发光元件21、多个第二发光元件22和多个第三发光元件23远离基底2一侧，并将多个第一发光元件21、多个第二发光元件22和多个第三发光元件23覆盖；
第二偏光结构4，第二偏光结构4位于第一显示区A1、第二显示区A2和第三显示区A3，且位于封装层3远离基底2一侧；
盖板5，盖板5位于第一显示区A1、第二显示区A2和第三显示区A3，且位于第二偏光结构4远离基底2一侧；
第一偏光结构6，第一偏光结构6位于第二显示区A2和第三显示区A3，且位于基底2远离像素电路层一侧；
背板1，背板1位于第一显示区A1、第二显示区A2和第三显示区A3，且位于第一偏光结构6远离基底2一侧；
第一反射界面32，第一反射界面32位于第一显示区A1、第二显示区A2和第三显示区A3，且至少位于基底2远离像素电路层一侧，第一反射界面将至少部分光线朝向所述像素电路层反射；第一偏光结构6被配置为阻挡第一反射界面反射的光线入射像素电路层。例如：第一偏光结构6被配置为阻挡第一显示区A1进入第一反射界面反射的光线入射像素电路层。
在示例性实施方式中，如图2A所示，本公开实施例显示基板的背板1远离基底2一侧表面与显示基板外侧的交界形成第一反射界面32。在一些实施例中，本公开实施例显示基板中位于第二偏光结构远离基底一侧其他膜层的交界也可以形成第二反射界面，本公开实施例显示基板中位于第一偏光结构远离基底一侧其他膜层的交界也可以形成第一反射界面。然而，本实施例对此并不限定。
在示例性实施方式中，如图2A所示，在垂直于显示基板的平面内，第一显示区A1可以包括：背板1、设置在背板1一侧的基底2、设置在基底2远离背板1一侧的多个第一发光元件21、设置在多个第一发光元件21远离背板1一侧的封装层3、设置在封装层3远离背板1一侧的第二偏光结构4 以及设置在第二偏光结构4远离背板1一侧的盖板5。其中，第一显示区A1不设置像素电路层以及第一偏光结构，第一偏光结构在基底2的正投影与第一显示区A1不交叠。
如图2A所示，在垂直于显示基板的平面内，第二显示区A2可以包括：背板1、设置在背板1上的第一偏光结构6、设置在第一偏光结构6远离背板1一侧的基底2、设置在基底2远离背板1一侧的像素电路层、设置在像素电路层远离背板1一侧的多个第二发光元件22、设置在多个第二发光元件22远离背板1一侧的封装层3、设置在封装层3远离背板1一侧的第二偏光结构4以及设置在第二偏光结构4远离背板1一侧的盖板5。其中，像素电路层包括多个第一像素电路以及多个第二像素电路11。第二显示区A2设置有像素电路层以及第一偏光结构6。
如图2A所示，在垂直于显示基板的平面内，第三显示区A3可以包括：背板1、设置在背板1上的第一偏光结构6、设置在第一偏光结构6远离背板1一侧的基底2、设置在基底2远离背板1一侧的像素电路层、设置在像素电路层远离背板1一侧的走线层、设置在走线层远离背板1一侧的多个第三发光元件23、设置在多个第三发光元件23远离背板1一侧的封装层3、设置在封装层3远离背板1一侧的第二偏光结构4以及设置在第二偏光结构4远离背板1一侧的盖板5。其中，像素电路层包括多个第三像素电路12。走线层包括多个信号走线7。第三显示区A3设置有像素电路层、走线层以及第一偏光结构6。其中，信号走线7可以包括扫描线、数据信号线、接地线、第一驱动线和第二驱动线中的至少一种。
在示例性实施方式中，如图2A所示，在垂直于显示基板的平面内，第一显示区A1不设置像素电路层、第一偏光结构以及走线层，可以确保第一显示区A1的光透过率较好。第二显示区A2设置有像素电路层以及第一偏光结构，不设置有走线层。第三显示区A3设置有像素电路层、走线层以及第一偏光结构。
在示例性实施方式中，如图1A和1B所示，在平行于显示基板的平面内，第二显示区A2在远离第一显示区A1的方向上排布有3或4个第二发光元件22。例如，第二显示区A2在第一方向X上可以包括第一区域a和第二区域 b，第一区域a和第二区域b位于第一显示区A1在第一方向X上的两侧：第一区域a和第二区域b分别包括一个绿色(G)第二发光元件、一个红色(R)第二发光元件和一个蓝色(B)第二发光元件，一个绿色(G)第二发光元件、一个红色(R)第二发光元件和一个蓝色(B)第二发光元件沿着第一方向X排布。
经过发明人的研究发现，暗环的辐射面积约为3～4个发光元件，暗环沿着远离第一显示区A1方向逐渐减轻。本公开实施例显示基板通过在第二显示区A2中沿着远离第一显示区A1的方向排布有3或4个发光元件，使暗环不会延伸至第三显示区A3，避免影响第三显示区A3的显示效果。
在示例性实施方式中，如图1A和1B所示，在平行于显示基板的平面内，第一偏光结构6可以仅位于第二显示区A2中，第一偏光结构6在基底2的正投影与第二显示区A2交叠，第一偏光结构6在基底2的正投影与第一显示区A1和第三显示区A3均不交叠。第一偏光结构6至少覆盖第二显示区A2中沿着远离第一显示区A1方向排布的3或4个发光元件。例如，第一偏光结构6位于第二显示区A2的第一区域a和第二区域b。
图2D为本公开实施例的显示基板的另一种剖视图。在示例性实施方式中，如图2D所示，本公开实施例显示基板还包括吸光层40，吸光层40位于第一显示区A1、第二显示区A2以及第三显示区A3，且吸光层40层叠设置在第一偏光结构6与第一反射界面32之间，例如，吸光层40层叠设置在第一偏光结构6与背板1之间。吸光层40被配置为吸收朝向第一反射界面32出射的光线。吸光层40具有吸收光线的作用，能够减少朝向第一反射界面32出射的光线，从而减少第一反射界面32反射至像素电路层的光线，进而避免发生暗环等不良现象。
图2E为本公开实施例的显示基板的另一种剖视图。在示例性实施方式中，如图2E所示，本公开实施例显示基板还包括遮光层50，遮光层50位于第二显示区A2以及第三显示区A3，且遮光层50层叠设置在像素电路层靠近基底2一侧。遮光层50对第二显示区A2以及第三显示区A3进行挡光。遮光层50不位于第一显示区A1，遮光层50在基底2的正投影与第一显示区A1不交叠，避免遮挡第一显示区A1的光线，影响第一显示区A1的透光性。
在示例性实施方式中，遮光层50形成网状结构，遮光层50包括图案区和镂空区，遮光层50的图案区在基底2的正投影与像素电路在基底2的正投影交叠。
在一些实施例中，遮光层形成网状结构，遮光层可以位于第一显示区A1、第二显示区A2以及第三显示区A3。遮光层在第一显示区A1的镂空区面积大于遮光层在第二显示区A2的镂空区面积；和/或，遮光层在第一显示区A1的镂空区面积大于遮光层在第三显示区A3的镂空区面积。
在示例性实施方式中，基底2可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料。
在示例性实施方式中，本公开实施例显示基板中像素电路可以包括晶体管以及电容，晶体管可以包括有源层、栅极以及源漏极。
在示例性实施方式中，本公开实施例显示基板中发光元件可以为OLED、QLED、Micro-LED或者Mini-LED。发光元件可以包括阳极层、像素定义层、有机发光层和阴极层。有机发光层可以包括叠设的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层。在一些示例中，第一显示区A1的阴极层、第二显示区A2的阴极层和第三显示区A3的阴极层可以为一体结构。在本示例中，显示区域的阴极层可以为整面阴极。例如，阴极层可以为透明阴极，例如可以采用ITO或IZO等透明导电材料制备。在本示例中，发光元件可以通过透明阴极从远离基底一侧出光，实现顶发射结构。然而，本实施例对此并不限定。例如，第一显示区A1的阴极层可以为具有镂空区域的图案化阴极。
在示例性实施方式中，本公开实施例显示基板中封装层3可以包括叠设的第一封装层、第二封装层和第三封装层。第一封装层采用无机材料，第二封装层采用有机材料，第三封装层采用无机材料，覆盖第一封装层和第二封装层。然而，本实施例对此并不限定。在一些示例中，封装层可以采用无机/有机/无机/有机/无机的五层结构。
在示例性实施方式中，本公开实施例显示基板还包括第一介质层、第二介质层以及第三介质层，第一介质层、第二介质层以及第三介质层沿着远离基底2方向依次层叠设置。第一介质层位于第一显示区A1、第二显示区A2 以及第三显示区A3中，第一介质层层叠设置于像素电路层与基底2之间。第二介质层位于第一显示区A1、第二显示区A2以及第三显示区A3中，第二介质层层叠设置于像素电路层与走线层之间。第三介质层位于第一显示区A1、第二显示区A2以及第三显示区A3中，第三介质层层叠设置于走线层与发光元件之间。第一介质层、第二介质层以及第三介质层可以采用有机材料，例如，树脂。
在示例性实施方式中，本公开实施例显示基板还包括第一胶层8，第一胶层8位于第一显示区A1、第二显示区A2以及第三显示区A3中。在第二显示区A2以及第三显示区A3中，第一胶层8层叠设置于背板1与第一偏光结构6之间；在第一显示区A1中，第一胶层8层叠设置于背板1与基底2之间。第一胶层8用于将第一偏光结构6与背板1粘接以及将基底2与背板1粘接。其中，第一胶层8可以采用压敏胶(PSA)。
在示例性实施方式中，本公开实施例显示基板还包括第二胶层9，第二胶层9位于第一显示区A1、第二显示区A2以及第三显示区A3中，第二胶层9层叠设置于盖板5与第二偏光结构4之间。第二胶层9用于将盖板5与第二偏光结构4粘接。其中，第二胶层9可以采用光学胶(OCA)。
在示例性实施方式中，如图2A所示，本公开实施例显示基板还包括第二反射界面31。第二反射界面31位于第一显示区A1、第二显示区A2和第三显示区A3，且至少位于第二偏光结构4远离基底2一侧。例如，本公开实施例显示基板的盖板5远离基底2一侧与显示基板外侧的交界形成第二反射界面31。
在示例性实施方式中，如图2A所示，第二反射界面31将至少一个第一发光元件21发出的光线形成反射光线，例如，至少一个第一发光元件21发出的光线在第二反射界面31处发生全反射，形成朝向第二偏光结构4出射的上述反射光线。第二偏光结构4被配置为透射上述反射光线，将透射的反射光线形成第一圆偏振光线，并将至少部分第一圆偏振光线朝向第一反射界面32出射。第一反射界面32将入射的上述第一圆偏振光线形成第二圆偏振光线，并将至少部分第二圆偏振光线反射，使至少部分第二圆偏振光线朝向第一偏光结构6出射。第一偏光结构6被配置为阻挡入射的上述第二圆偏振光 线透射，从而阻挡上述第二圆偏振光线出射至第二显示区A2中的第一像素电路、第二像素电路11以及第三显示区A3中的第三像素电路12，避免第一发光元件21发出的光线经过显示基板内部膜层的反射，入射至显示基板中的像素电路，从而避免显示基板中的像素电路发生特性偏移，改善显示基板产生暗环等不良现象，提升显示效果。
在示例性实施方式中，如图2A所示，本公开实施例显示基板中光线的光路为：第一发光元件21发出光线，一部分光线射出显示基板用于显示图像，一部分光线在第二反射界面31处发生全反射，形成朝向第二偏光结构4出射的反射光线；该反射光线出射至第二偏光结构4，第二偏光结构4透射至少部分反射光线，将透射的反射光线形成第一圆偏振光线，并将至少部分第一圆偏振光线朝向第一反射界面32出射；至少部分第一圆偏振光线出射至第一反射界面32，在第一反射界面32处发生全反射，形成朝向第一偏光结构6出射的第二圆偏振光线，第二圆偏振光线在第一偏光结构6处被阻挡，无法透射第一偏光结构6，从而避免第二圆偏振光线出射至第二显示区A2中的第一像素电路、第二像素电路11以及第三显示区A3中的第三像素电路12，从而避免显示基板中的像素电路发生特性偏移，改善显示基板产生暗环等不良现象，提升显示效果。
在示例性实施方式中，如图2A所示，第二偏光结构4在基底2的正投影均与多个第一发光元件21在基底2的正投影、多个第二发光元件22在基底2的正投影以及多个第三发光元件23在基底2的正投影交叠，至少部分第二偏光结构4覆盖多个第一发光元件21、多个第二发光元件22以及多个第三发光元件23。
在一些实施方式中，第二偏光结构可以只位于第一显示区A1，不位于第二显示区A2和第三显示区A3。第二偏光结构在基底2的正投影与多个第一发光元件21在基底2的正投影交叠，与多个第二发光元件22在基底2的正投影以及多个第三发光元件23在基底2的正投影不交叠。
在示例性实施方式中，如图2A所示，第二偏光结构4包括层叠设置的第二位相差膜层401和第二线偏光膜层402，第二位相差膜层401位于第二线偏光膜层402靠近基底2一侧，第二线偏光膜层402被配置为透射反射光 线，并将透射的反射光线形成第一线偏振光线，第二位相差膜层401被配置为透射第一线偏振光线，并将透射的第一线偏振光线形成第一圆偏振光线。在一些实施例中，第二位相差膜层被配置为透射第一线偏振光线，并将透射的第一线偏振光线形成第一椭圆偏振光线。然而，本实施例对此并限定。
在示例性实施方式中，如图2A所示，第一偏光结构6在基底2的正投影与多个第二发光元件22在基底2的正投影以及多个第三发光元件23在基底2的正投影交叠，与多个第一发光元件21在基底2的正投影不交叠。
在示例性实施方式中，如图2A所示，第一偏光结构6包括层叠设置的第一位相差膜层601和第一线偏光膜层602，第一线偏光膜层602位于第一位相差膜层601靠近基底2一侧，第一位相差膜层601被配置为透射第二圆偏振光线，并将透射的第二圆偏振光线形成第二线偏振光线，第一线偏光膜层602被配置为阻挡入射的第二线偏振光线透射。
在示例性实施方式中，第一圆偏振光线与第二圆偏振光线的光矢量旋转方向相反。例如，第一圆偏振光线可以为左旋圆偏振光线，第二圆偏振光线可以为右旋圆偏振光线；或者，第一圆偏振光线可以为右旋圆偏振光线，第二圆偏振光线可以为左旋圆偏振光线。然而，本实施例对此并限定。
在示例性实施方式中，第二线偏振光线的偏振方向与第一线偏光膜层602的偏振方向垂直，使第二线偏振光线无法透过第一线偏光膜层602，进而使第一偏光结构6阻止第二圆偏振光线出射至第二显示区A2中的第一像素电路、第二像素电路11以及第三显示区A3中的第三像素电路12，从而避免显示基板中的像素电路发生特性偏移。
在示例性实施方式中，第二偏光结构4中第二位相差膜层401的透过轴与显示基板所在平面之间的夹角可以为-5度至5度。例如，第二位相差膜层401的透过轴与显示基板所在平面之间的夹角可以为0度。
在示例性实施方式中，第一偏光结构6中第一位相差膜层601的透过轴与显示基板所在平面之间的夹角可以为-5度至5度。例如，第一位相差膜层601的透过轴与显示基板所在平面之间的夹角可以为0度。
在示例性实施方式中，第二位相差膜层401的透过轴与显示基板所在平 面之间的夹角可以与第一位相差膜层601的透过轴与显示基板所在平面之间的夹角相同。例如，第二位相差膜层401的透过轴与显示基板所在平面之间的夹角和第一位相差膜层601的透过轴与显示基板所在平面之间的夹角均可以为0度。然而，本实施例对此并限定。在一些实施例中，第二位相差膜层的透过轴与显示基板所在平面之间的夹角与第一位相差膜层的透过轴与显示基板所在平面之间的夹角也可以不同。
在示例性实施方式中，第二偏光结构4中第二位相差膜层401的相位差可以为60纳米至450纳米。例如，第二偏光结构4中第二位相差膜层401的相位差可以为68.75纳米、137.5纳米、206.25纳米或412.5纳米。然而，本实施例对此并限定。
在示例性实施方式中，第一偏光结构6中第一位相差膜层601的相位差可以为60纳米至450纳米。例如，第一偏光结构6中第一位相差膜层601的相位差可以为68.75纳米、137.5纳米、206.25纳米或412.5纳米。然而，本实施例对此并限定。
在示例性实施方式中，第二位相差膜层401可以采用四分之一波片。第二偏光结构4中第二线偏光膜层402的透射轴方向与第二位相差膜层401的快轴之间的夹角可以为40度至50度；或者130度至140度。例如，第二线偏光膜层402的透射轴方向与第二位相差膜层401的快轴之间的夹角可以为45度或135度。在一些实施例中，第二位相差膜层可以采用二分之一波片。然而，本实施例对此并限定。其中，快轴是指传播速度快的光矢量方向。
在示例性实施方式中，第一位相差膜层601可以采用四分之一波片。第一偏光结构6中第一线偏光膜层602的透射轴方向与第一位相差膜层601的快轴之间的夹角可以为40度至50度；或者130度至140度。例如，第一线偏光膜层602的透射轴方向与第一位相差膜层601的快轴之间的夹角可以为45度或135度。在一些实施例中，第一位相差膜层可以采用二分之一波片。然而，本实施例对此并限定。
图6为本公开实施例显示基板中光路的示意图。在示例性实施方式中，以第二位相差膜层401的透过轴和第一位相差膜层601的透过轴均为0度，第二位相差膜层401的相位差为137.5纳米，第二线偏光膜层402的透射轴 方向与第二位相差膜层401的快轴之间的夹角为45°，第一位相差膜层601的相位差为137.5纳米，第一线偏光膜层602的透射轴方向与第一位相差膜层601的快轴之间的夹角为45°为例，来说明本公开实施例显示基板中光线的光路。如图6所示，当第一显示区A1中第一发光元件21发出光线，一部分光线射出显示基板用于显示图像，一部分光线在盖板5远离发光元件一侧与显示基板外侧的交界形成的第二反射界面31处发生全反射，形成朝向第二偏光结构4出射的反射光线b；该反射光线b穿过第二线偏光膜层402后，形成与第二位相差膜层401的快轴之间的夹角为45°的第一线偏振光线c，第一线偏振光线c穿过第二位相差膜层401，形成左旋的第一圆偏振光线d，且至少部分第一圆偏振光线d朝向第一反射界面32出射；至少部分第一圆偏振光线d出射至第一反射界面32，在第一反射界面32处发生全反射，形成右旋的第二圆偏振光线e，第二圆偏振光线e穿过第一位相差膜层601后，形成与第一位相差膜层601的快轴之间的夹角为135°的第二线偏振光线f，第二线偏振光线f的偏振方向与第一线偏光膜层602的透射轴方向垂直，使第二线偏振光线f无法穿过第一线偏光膜层602，进而使第二圆偏振光线e在第一偏光结构6处被阻挡。
在示例性实施方式中，以第二位相差膜层401的透过轴和第一位相差膜层601的透过轴均为0度，第二位相差膜层401的相位差为137.5纳米，第二线偏光膜层402的透射轴方向与第二位相差膜层401的快轴之间的夹角为45°，第一位相差膜层601的相位差为412.5纳米，第一线偏光膜层602的透射轴方向与第一位相差膜层601的快轴之间的夹角为135°为例，来说明本公开实施例显示基板中光线的光路。当第一显示区A1中第一发光元件21发出光线，一部分光线射出显示基板用于显示图像，一部分光线在盖板5远离发光元件一侧与显示基板外侧的交界形成的第二反射界面31处发生全反射，形成朝向第二偏光结构4出射的反射光线；该反射光线穿过第二线偏光膜层402后，形成与第二位相差膜层401的快轴之间的夹角为45°的第一线偏振光线，第一线偏振光线穿过第二位相差膜层401，形成左旋的第一圆偏振光线，且至少部分第一圆偏振光线朝向第一反射界面32出射；至少部分第一圆偏振光线出射至第一反射界面32，在第一反射界面32处发生全反射， 形成右旋的第二圆偏振光线，第二圆偏振光线穿过第一位相差膜层601后，形成与第一位相差膜层601的快轴之间的夹角为45°的第二线偏振光线，第二线偏振光线的偏振方向与第一线偏光膜层602的透射轴方向垂直，使第二线偏振光线无法穿过第一线偏光膜层602，进而使第二圆偏振光线在第一偏光结构6处被阻挡。
在示例性实施方式中，本公开实施例显示基板还包括复合膜10，复合膜10位于第二显示区A2以及第三显示区A3中，即复合膜10在基底2的正投影与第一显示区A1不交叠，与第二显示区A2以及第三显示区A3交叠。复合膜10层叠设置在背板1远离基底2一侧。复合膜10在基底2的正投影与第一显示区A1不交叠，能够避免复合膜10降低第一显示区A1的透光性。
在示例性实施方式中，复合膜10可以采用超净泡沫(super clean foam，SCF)复合膜。复合膜10一般包括沿远离背板1的方向依次层叠的粘结层、缓冲层和散热层。复合膜10能够对作用于显示基板的应力起到缓冲作用，且能够散发显示基板工作时产生的热量，对显示基板起到一定的保护效果。
图2B为本公开实施例的显示基板的另一种剖视图。在示例性实施方式中，如图2B所示，在垂直于显示基板的平面内，第一显示区A1可以包括：背板1、设置在背板1上的第一偏光结构6、设置在第一偏光结构6远离背板1一侧的基底2、设置在基底2远离背板1一侧的多个第一发光元件21、设置在多个第一发光元件21远离背板1一侧的封装层3、设置在封装层3远离背板1一侧的第二偏光结构4以及设置在第二偏光结构4远离背板1一侧的盖板5。其中，第一显示区A1不设置像素电路层，第一偏光结构6中的第一位相差膜层601在基底的正投影与第一显示区A1交叠，第一偏光结构6中的第一线偏光膜层602在基底的正投影与第一显示区A1不交叠，避免第一线偏光膜层602降低第一显示区A1的透光性。
如图2B所示，在垂直于显示基板的平面内，第二显示区A2可以包括：背板1、设置在背板1上的第一偏光结构6、设置在第一偏光结构6远离背板1一侧的基底2、设置在基底2远离背板1一侧的像素电路层、设置在像素电路层远离背板1一侧的多个第二发光元件22、设置在多个第二发光元件22远离背板1一侧的封装层3、设置在封装层3远离背板1一侧的第二偏光结 构4以及设置在第二偏光结构4远离背板1一侧的盖板5。其中，像素电路层包括多个第一像素电路以及多个第二像素电路11。第二显示区A2设置有像素电路层以及第一偏光结构。
如图2B所示，在垂直于显示基板的平面内，第三显示区A3可以包括：背板1、设置在背板1上的第一偏光结构6、设置在第一偏光结构6远离背板1一侧的基底2、设置在基底2远离背板1一侧的像素电路层、设置在像素电路层远离背板1一侧的走线层、设置在走线层远离背板1一侧的多个第三发光元件23、设置在多个第三发光元件23远离背板1一侧的封装层3、设置在封装层3远离背板1一侧的第二偏光结构4以及设置在第二偏光结构4远离背板1一侧的盖板5。其中，像素电路层包括多个第三像素电路12。走线层包括多个信号走线7。第三显示区A3设置有像素电路层、走线层以及第一偏光结构6。
在示例性实施方式中，如图2B所示，在垂直于显示基板的平面内，第一显示区A1不设置像素电路层以及走线层，第一偏光结构6中的第一位相差膜层601位于第一显示区A1中，第一偏光结构6中的第一线偏光膜层602不位于第一显示区A1中。第二显示区A2设置有像素电路层以及第一偏光结构，不设置有走线层。第三显示区A3设置有像素电路层、走线层以及第一偏光结构。
在示例性实施方式中，以第二位相差膜层401的透过轴和第一位相差膜层601的透过轴均为0度，第二位相差膜层401的相位差为137.5纳米，第二线偏光膜层402的透射轴方向与第二位相差膜层401的快轴之间的夹角为45°，第一位相差膜层601的相位差为68.75纳米，第一线偏光膜层602的透射轴方向与第一位相差膜层601的快轴之间的夹角为45°为例，来说明本公开实施例显示基板中光线的光路。当第一显示区A1中第一发光元件21发出光线，一部分光线射出显示基板用于显示图像，一部分光线在盖板5远离发光元件一侧与显示基板外侧的交界形成的第二反射界面31处发生全反射，形成朝向第二偏光结构4出射的反射光线；该反射光线穿过第二线偏光膜层402后，形成与第二位相差膜层401的快轴之间的夹角为45°的第一线偏振光线，第一线偏振光线穿过第二位相差膜层401，形成左旋的第一圆偏振光 线，且至少部分第一圆偏振光线朝向第一反射界面32出射；至少部分第一圆偏振光线出射至第一反射界面32，在第一反射界面32处发生全反射，形成右旋的第二圆偏振光线，第二圆偏振光线穿过第一位相差膜层601后，形成与第一位相差膜层601的快轴之间的夹角为135°的第二线偏振光线，第二线偏振光线的偏振方向与第一线偏光膜层602的透射轴方向垂直，使第二线偏振光线无法穿过第一线偏光膜层602，进而使第二圆偏振光线在第一偏光结构6处被阻挡。
在示例性实施方式中，以第二位相差膜层401的透过轴和第一位相差膜层601的透过轴均为0度，第二位相差膜层401的相位差为137.5纳米，第二线偏光膜层402的透射轴方向与第二位相差膜层401的快轴之间的夹角为45°，第一位相差膜层601的相位差为206.25纳米，第一线偏光膜层602的透射轴方向与第一位相差膜层601的快轴之间的夹角为135°为例，来说明本公开实施例显示基板中光线的光路。当第一显示区A1中第一发光元件21发出光线，一部分光线射出显示基板用于显示图像，一部分光线在盖板5远离发光元件一侧与显示基板外侧的交界形成的第二反射界面31处发生全反射，形成朝向第二偏光结构4出射的反射光线；该反射光线穿过第二线偏光膜层402后，形成与第二位相差膜层401的快轴之间的夹角为45°的第一线偏振光线，第一线偏振光线穿过第二位相差膜层401，形成左旋的第一圆偏振光线，且至少部分第一圆偏振光线朝向第一反射界面32出射；至少部分第一圆偏振光线出射至第一反射界面32，在第一反射界面32处发生全反射，形成右旋的第二圆偏振光线，第二圆偏振光线穿过第一位相差膜层601后，形成与第一位相差膜层601的快轴之间的夹角为45°的第二线偏振光线，第二线偏振光线的偏振方向与第一线偏光膜层602的透射轴方向垂直，使第二线偏振光线无法穿过第一线偏光膜层602，进而使第二圆偏振光线在第一偏光结构6处被阻挡。
图3为本公开实施例的显示装置的示意图。如图3所示，本公开提供了一种显示装置，包括：显示基板100以及位于远离显示基板100的出光侧的感光传感器200。感光传感器200在显示基板100上的正投影与显示基板中第一显示区A1存在交叠区域。
在一些示例中，显示基板100可以为柔性OLED显示基板、QLED显示基板、Micro-LED显示基板、或者Mini-LED显示基板。显示装置可以为：OLED显示器、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开实施例并不以此为限。
本公开提供了一种显示基板的制备方法，该显示基板可以为前面任一所述的显示基板，该显示基板包括第一显示区和第二显示区，所述第二显示区位于所述第一显示区的至少一侧，所述第一显示区为屏下传感区域；所述显示基板的制备方法包括：
至少在所述第一显示区和所述第二显示区中形成基底；
至少在所述第二显示区的基底上形成像素电路层；
至少在所述基底远离所述像素电路层的一侧形成第一反射界面，且所述第一反射界面至少位于所述第一显示区和所述第二显示区；所述第一反射界面将至少部分光线朝向所述像素电路层反射；
至少在所述基底与所述第一反射界面之间形成第一偏光结构，且至少部分所述第一偏光结构位于所述第二显示区，所述第一偏光结构被配置为阻挡所述第一反射界面反射的光线入射所述像素电路层。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种显示基板，包括第一显示区和第二显示区，所述第二显示区位于所述第一显示区的至少一侧，所述第一显示区为屏下传感区域；所述显示基板至少包括：
    基底，至少位于所述第一显示区和所述第二显示区；
    像素电路层，至少部分所述像素电路层位于所述第二显示区，且位于所述基底一侧；
    第一反射界面，至少位于所述第一显示区和所述第二显示区，且位于所述基底远离所述像素电路层的一侧；所述第一反射界面将至少部分光线朝向所述像素电路层反射；
    第一偏光结构，至少部分所述第一偏光结构位于所述第二显示区，且至少部分所述第一偏光结构位于所述基底与所述第一反射界面之间，所述第一偏光结构被配置为阻挡所述第一反射界面反射的光线入射所述像素电路层。
  2. 根据权利要求1所述的显示基板，还包括第三显示区，所述第三显示区位于所述第一显示区和所述第二显示区的至少一侧，至少部分所述像素电路层位于所述第三显示区，至少部分所述第一偏光结构位于所述第三显示区。
  3. 根据权利要求1所述的显示基板，还包括：
    多个第一发光元件，位于所述第一显示区，且位于所述基底远离所述第一反射界面一侧；
    第二反射界面，至少位于所述第一显示区和所述第二显示区，且至少位于所述多个第一发光元件远离所述基底一侧，所述第二反射界面将至少一个第一发光元件发出的光线形成反射光线；
    第二偏光结构，至少位于所述第一显示区和所述第二显示区，且至少位于所述多个第一发光元件与所述第二反射界面之间，所述第二偏光结构被配置为透射所述反射光线，使透射的所述反射光线形成第一圆偏振光线，并将所述第一圆偏振光线朝向所述第一反射界面出射；
    所述第一反射界面被配置为将入射的所述第一圆偏振光线形成第二圆偏 振光线，并将至少部分所述第二圆偏振光线反射至所述第一偏光结构；所述所述第一偏光结构被配置为阻挡所述第二圆偏振光线入射所述像素电路层。
  4. 根据权利要求3所述的显示基板，其中，所述第二偏光结构包括层叠设置的第二线偏光膜层和第二位相差膜层，所述第二位相差膜层位于所述第二线偏光膜层靠近所述基底一侧，所述第二线偏光膜层被配置为透射所述反射光线，并将透射的所述反射光线形成第一线偏振光线，所述第二位相差膜层被配置为透射所述第一线偏振光线，并将透射的所述第一线偏振光线形成所述第一圆偏振光线。
  5. 根据权利要求3所述的显示基板，其中，所述第一偏光结构包括层叠设置的第一线偏光膜层和第一位相差膜层，所述第一位相差膜层位于所述第一线偏光膜层靠近所述基底一侧，所述第一位相差膜层被配置为透射所述第二圆偏振光线，并将透射的所述第二圆偏振光线形成第二线偏振光线，所述第一线偏光膜层被配置为阻挡入射的所述第二线偏振光线透射。
  6. 根据权利要求5所述的显示基板，其中，所述第二线偏振光线的偏振方向与所述第一线偏光膜层的偏振方向垂直。
  7. 根据权利要求5所述的显示基板，其中，所述第一线偏光膜层在所述基底的正投影与所述第一显示区不交叠，至少部分所述第一位相差膜层在所述基底的正投影与所述第一显示区交叠。
  8. 根据权利要求1至6任一所述的显示基板，其中，所述第一偏光结构在所述基底的正投影与所述第一显示区不交叠。
  9. 根据权利要求1至8任一所述的显示基板，还包括：背板，所述背板至少位于所述第一显示区和所述第二显示区，且所述背板至少位于所述第一偏光结构远离所述基底一侧，所述背板远离所述基底一侧表面与所述显示基板外侧的交界形成所述第一反射界面。
  10. 根据权利要求9所述的显示基板，还包括：复合膜，所述复合膜至少位于所述第二显示区，所述复合膜至少位于所述背板远离所述基底一侧，所述复合膜在所述基底的正投影与所述第一显示区不交叠。
  11. 根据权利要求3所述的显示基板，还包括：盖板，所述盖板至少位 于所述第一显示区和所述第二显示区，所述盖板位于所述第二偏光结构远离所述基底一侧，所述盖板远离所述基底一侧表面与所述显示基板外侧的交界形成所述第二反射界面。
  12. 根据权利要求1至11任一所述的显示基板，还包括：封装层，所述封装层至少位于所述第一显示区和所述第二显示区，所述封装层位于所述像素电路层远离所述基底一侧。
  13. 根据权利要求3所述的显示基板，还包括：多个第二发光元件，所述像素电路层包括多个第一像素电路和多个第二像素电路，所述多个第二发光元件、所述多个第一像素电路和所述多个第二像素电路均位于所述第二显示区，所述多个第二发光元件位于所述像素电路层远离所述基底一侧，所述第一像素电路与所述第一发光元件电连接，所述第二像素电路与所述第二发光元件电连接。
  14. 根据权利要求13所述的显示基板，其中，所述第一发光元件之间的间距，大于所述第二发光元件之间的间距；和/或，所述第一发光元件的面积小于所述第二发光元的面积。
  15. 根据权利要求13任所述的显示基板，其中，所述第二显示区在远离所述第一显示区的方向上排布有3或4个第二发光元件。
  16. 根据权利要求15所述的显示基板，其中，所述第一偏光结构在所述基底的正投影与所述3或4个第二发光元件在所述基底的正投影交叠。
  17. 根据权利要求1至16任一所述的显示基板，还包括吸光层，所述吸光层至少位于所述第一显示区和所述第二显示区，且所述吸光层层叠设置在所述第一偏光结构与所述第一反射界面之间。
  18. 根据权利要求1至16任一所述的显示基板，还包括遮光层，所述遮光层位于所述第二显示区，所述遮光层在基底的正投影与所述第一显示区不交叠，所述遮光层层叠设置在所述像素电路层靠近所述基底一侧。
  19. 一种显示装置，包括权利要求1至18任一所述的显示基板以及感光传感器，所述感光传感器位于远离所述显示基板的出光侧的一侧，所述感光传感器在所述显示基板上的正投影与所述显示基板中第一显示区存在交叠区 域。
  20. 一种显示基板的制备方法，所述显示基板包括第一显示区和第二显示区，所述第二显示区位于所述第一显示区的至少一侧，所述第一显示区为屏下传感区域；所述显示基板的制备方法包括：
    至少在所述第一显示区和所述第二显示区中形成基底；
    至少在所述第二显示区的基底上形成像素电路层；
    至少在所述基底远离所述像素电路层的一侧形成第一反射界面，且所述第一反射界面至少位于所述第一显示区和所述第二显示区；所述第一反射界面将至少部分光线朝向所述像素电路层反射；
    至少在所述基底与所述第一反射界面之间形成第一偏光结构，且至少部分所述第一偏光结构位于所述第二显示区，所述第一偏光结构被配置为阻挡所述第一反射界面反射的光线入射所述像素电路层。
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CN108269943A (zh) * 2016-12-30 2018-07-10 乐金显示有限公司 有机发光显示装置
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