WO2023216289A1

WO2023216289A1 - Switched-capacitor circuit, voltage-controlled oscillator, and method for forming switched-capacitor circuit

Info

Publication number: WO2023216289A1
Application number: PCT/CN2022/093604
Authority: WO
Inventors: 李闻界; 管逸; 汝斐
Original assignee: 上海韬润半导体有限公司
Priority date: 2022-05-10
Filing date: 2022-05-18
Publication date: 2023-11-16
Also published as: CN114978042A; CN114978042B

Abstract

The present invention relates to a switched-capacitor circuit, a voltage-controlled oscillator comprising same, and a method for forming a switched-capacitor circuit. The switched-capacitor circuit, according to an aspect of the present invention, comprises: a first capacitor; a second capacitor; and a transistor, which is arranged between the first capacitor and the second capacitor, wherein a gate electrode of the transistor is provided with a high-resistance resistor.

Description

Switched capacitor circuit, voltage controlled oscillator and method of forming switched capacitor circuit

Technical field

The present invention relates to the field of circuit technology, and more specifically to a switched capacitor circuit, a voltage controlled oscillator including the switched capacitor circuit, and a method of forming a switched capacitor circuit.

Background technique

In a circuit system, the total energy stored in the system divided by the energy lost in a single cycle is defined as the quality factor (Q). In a circuit system, the less energy expected to be lost, the better, that is, the larger the Q value, the better.

At present, a voltage-controlled oscillator is generally equipped with a switched capacitor array, and one or more switches in the switched capacitor array are controlled to close according to the target oscillation frequency, so that the voltage-controlled oscillator with a certain capacitance value can output an oscillation closest to the target. Frequency frequency.

However, as the signal frequency becomes higher and higher, the performance requirements for the voltage controlled oscillator are also getting higher and higher. Although the switched capacitor array can effectively expand the tuning range of the voltage-controlled oscillator, a certain power loss will occur when high-frequency signals pass through the switched capacitor array. This power loss is mainly caused by the equivalent series resistance of the switched capacitor array itself. Switched capacitor arrays with low Q values have poor response capabilities to high-frequency signals, and may even cause severe attenuation of high-frequency signals. In addition, in the traditional switched capacitor array structure, the control voltage from the outside is directly connected to the gate of the transistor, resulting in large noise interference and additional capacitance to ground in the AC path.

Contents of the invention

In order to solve or at least alleviate one or more of the above problems, the following technical solutions are provided.

According to a first aspect of the present invention, a switched capacitor circuit is provided. The switched capacitor circuit includes: a first capacitor; a second capacitor; and a transistor, which is disposed between the first capacitor and the second capacitor, The gate of the transistor is provided with a high resistance resistor.

According to the switched capacitor circuit according to an embodiment of the present invention, the resistance of the high-resistance resistor is greater than 20k ohms.

According to the switched capacitor circuit according to an embodiment of the present invention or any of the above embodiments, the source of the transistor is connected to the first capacitor, and the drain of the transistor is connected to the second capacitor.

According to the switched capacitor circuit according to an embodiment of the present invention or any of the above embodiments, the first capacitor and the second capacitor are configured in a first preset manner, and the first preset manner enables the The resistance of the first parasitic resistance of the first capacitor and the resistance of the second parasitic resistance of the second capacitor are reduced.

According to the switched capacitor circuit according to an embodiment of the present invention or any of the above embodiments, the first capacitor and the second capacitor are MOM capacitors, and the MOM capacitors include a plurality of stacked metal layers, so Each metal layer in the plurality of stacked metal layers includes a plurality of interdigital metals and a common fulcrum connecting the plurality of interdigital metals.

According to the switched capacitor circuit according to an embodiment of the present invention or any of the above embodiments, when the first capacitor and the second capacitor are MOM capacitors, the first preset mode includes the following: One or more ways: increasing the width of the interdigital metal to reduce the resistance of the resistance of the interdigital metal; increasing the width of the common fulcrum to reduce the resistance of the common fulcrum; and A plurality of through holes are provided between the plurality of stacked metal layers.

According to the switched capacitor circuit according to an embodiment of the present invention or any of the above embodiments, the transistor is configured in a second preset manner, and the second preset manner makes the equivalent resistance of the transistor value decreases.

According to the switched capacitor circuit according to an embodiment of the present invention or any of the above embodiments, the second preset method includes increasing the value of W/L of the transistor to a predetermined threshold, where W represents the transistor The active area width and L represent the channel length of the transistor, and the predetermined threshold is determined based on the parasitic capacitance between the switched capacitor circuit and the substrate and the quality factor of the switched capacitor circuit.

According to the switched capacitor circuit according to an embodiment of the present invention or any of the above embodiments, the transistor is a MOS transistor.

According to a second aspect of the present invention, a voltage controlled oscillator is provided, the voltage controlled oscillator including the switched capacitor circuit according to the first aspect of the present invention.

According to a third aspect of the present invention, a method of forming a switched capacitor circuit is provided, which includes: setting a first capacitor; setting a second capacitor; setting a transistor between the first capacitor and the second capacitor; and The gate of the transistor is provided with a high resistance resistor.

According to the method of forming a switched capacitor circuit according to an embodiment of the present invention, the resistance of the high-resistance resistor is greater than 20k ohms.

The method of forming a switched capacitor circuit according to an embodiment of the present invention or any of the above embodiments, wherein the method further includes: connecting the source of the transistor to the first capacitor, and connecting the transistor to the first capacitor. The drain is connected to the second capacitor.

According to the method of forming a switched capacitor circuit according to an embodiment of the present invention or any of the above embodiments, the method further includes: configuring the first capacitor and the second capacitor in a first preset manner, so The first preset mode reduces the resistance of the first parasitic resistance of the first capacitor and the resistance of the second parasitic resistance of the second capacitor.

According to the method of forming a switched capacitor circuit according to an embodiment of the present invention or any of the above embodiments, the method further includes: implementing the first capacitor and the second capacitor as MOM capacitors, and the MOM The capacitor includes a plurality of stacked metal layers, each of the plurality of stacked metal layers including a plurality of interdigital metals and a common fulcrum connecting the plurality of interdigital metals.

According to the method of forming a switched capacitor circuit according to an embodiment of the present invention or any of the above embodiments, when the first capacitor and the second capacitor are implemented as MOM capacitors, the first preset mode Including one or more of the following methods: increasing the width of the interdigital metal to reduce the resistance of the resistance of the interdigital metal; increasing the width of the common fulcrum to reduce the resistance of the common fulcrum. value; and arranging a plurality of through holes between the plurality of stacked metal layers.

According to the method of forming a switched capacitor circuit according to an embodiment of the present invention or any of the above embodiments, the method further includes: configuring the transistor in a second preset manner, and the second preset manner enables the The equivalent resistance of the transistor decreases.

According to the method of forming a switched capacitor circuit according to an embodiment of the present invention or any of the above embodiments, the second preset method includes increasing the value of W/L of the transistor to a predetermined threshold, where W represents The active area width of the transistor and L represent the channel length of the transistor, and the predetermined threshold is determined based on the parasitic capacitance between the switched capacitor circuit and the substrate and the quality factor of the switched capacitor circuit.

According to the method of forming a switched capacitor circuit according to an embodiment of the present invention or any of the above embodiments, the transistor is a MOS transistor.

The switched capacitor circuit according to one or more embodiments of the present invention sets a high-value resistor at the gate of the transistor, which on the one hand can reduce noise interference from the outside, and on the other hand makes the direction visible from the source and drain of the transistor The gates of the transistors are all in a high-resistance state, which can improve the ground capacitance to the differential mode capacitance, thereby reducing ground-coupled noise interference. In addition, the switched capacitor circuit according to one or more embodiments of the present invention can significantly increase the Q value of the switched capacitor circuit, reduce the power loss generated when high-frequency signals pass through the switched capacitor circuit, and improve the response of the switched capacitor circuit to high-frequency signals. responsiveness.

Description of the drawings

The above and/or other aspects and advantages of the present invention will become clearer and easier to understand through the following description of various aspects in conjunction with the accompanying drawings, in which the same or similar units are designated by the same reference numerals. In said drawing:

Figure 1 illustrates a switched capacitor circuit in accordance with one or more embodiments of the present invention.

Figure 2 illustrates a parasitic equivalent model of the switched capacitor circuit shown in Figure 1 in accordance with one or more embodiments of the present invention.

Figure 3 shows the layout structure of a single capacitor layer of a MOM capacitor.

Figure 4 illustrates a flowchart of a method of forming a switched capacitor circuit in accordance with one or more embodiments of the present invention.

Detailed ways

The following description of the detailed embodiments is merely exemplary in nature and is not intended to limit the disclosed technology or the application and uses of the disclosed technology. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background or the following detailed description.

In the following detailed description of the embodiments, numerous specific details are set forth in order to provide a thorough understanding of the disclosed technology. However, it will be apparent to one of ordinary skill in the art that the disclosed technology may be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating the description.

Words such as "comprising" and "including" mean that in addition to having units and steps that are directly and explicitly stated in the specification, the technical solution of the present invention does not exclude having other units and steps that are not directly or explicitly stated. situation. Terms such as "first" and "second" do not indicate the order of units in terms of time, space, size, etc. but are merely used to distinguish between units.

Hereinafter, exemplary embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 1, the switched capacitor circuit 10 includes a first capacitor C0 and a second capacitor C1, and a transistor disposed between the first capacitor C0 and the second capacitor C1. Optionally, the transistor may be a MOS transistor, or further may be an NMOS transistor, and its gate terminal may be connected to a control voltage.

In FIG. 1, S represents the source of the transistor, G represents the gate of the transistor, and D represents the drain of the transistor. The source S of the transistor is connected to the first capacitor C0, and the drain D of the transistor is connected to the second capacitor C1. In the transistor, the resistors Rhs and Rhd are high-resistance resistors connected to the source S and drain D of the transistor respectively, and a high-resistance resistor Rhg is provided at the gate G of the transistor. Optionally, the resistance of the high-resistance resistor Rhg may be greater than 20k ohms.

As shown in Figure 1, by setting a high-resistance resistor Rhg at the gate G of the transistor, on the one hand, it is possible to reduce noise interference from the outside (for example, caused by the control voltage from the outside being directly connected to the gate G of the transistor). (noise interference), on the other hand, it makes the source S of the transistor and the drain D of the transistor appear in a high resistance state towards the gate G of the transistor, which can improve the ground capacitance to the differential mode capacitance, thereby reducing Ground coupled noise interference.

As shown in FIG. 2 , the parasitic equivalent model 20 of the switched capacitor circuit 10 shown in FIG. 1 includes a first capacitor C0 and a second capacitor C1 , and a transistor disposed between the first capacitor C0 and the second capacitor C1 . Among them, the resistor Rc0 is a first parasitic resistance as the first capacitor C0, and the resistor Rc1 is a second parasitic resistance as the second capacitor C1. In a transistor, the resistor Rmsw is the equivalent resistance of the transistor, and the resistors Rhs and Rhd are high-resistance resistors connected to the source S and drain D of the transistor respectively. The capacitor Cmgnd is a parasitic capacitance between the switched capacitor circuit and the substrate.

Optionally, the transistor may be a MOS transistor, or further may be an NMOS transistor, and its gate terminal may be connected to a control voltage.

Based on the parasitic equivalent model 20 of the switched capacitor circuit 10 shown in FIG. 1 shown in FIG. 2 in accordance with one or more embodiments of the present invention, the quality factor Q of the switched capacitor circuit 10 shown in FIG. 1 can be Expressed by the following formula:

Among them, f represents the oscillation frequency of the signal from the voltage-controlled oscillator, C0 and C1 represent the capacitance values of the first capacitor C0 and the second capacitor C1 respectively, Rc0 and Rc1 respectively represent the first parasitic resistance Rc0 of the first capacitor C0 The resistance value and the resistance value of the second parasitic resistance Rc1 of the second capacitor C1, and Rnsw represent the resistance value of the equivalent resistance Rmsw of the transistor.

Based on the above formula, it can be seen that the quality factor Q of the switched capacitor circuit 10 can be improved by reducing the parallel capacitance (C0//C1) or reducing the resistance (Rc0+Rmsw+Rc1).

Optionally, the first capacitor C0 and the second capacitor C1 may be configured in a first preset manner, which enables the resistance of the first parasitic resistance Rc0 of the first capacitor C0 to be reduced and the second resistance of the first capacitor C0 to be reduced. The resistance of the second parasitic resistance Rc1 of the capacitor C1.

Optionally, the transistor may be configured in a second preset manner, which reduces the resistance value of the equivalent resistance Rmsw of the transistor. Optionally, the second preset method includes increasing the value of W/L of the transistor to a predetermined threshold, where W represents the active area width of the transistor and L represents the channel length of the transistor, and the predetermined threshold It is determined based on the parasitic capacitance Cmgnd between the switched capacitor circuit and the substrate and the quality factor Q of the switched capacitor circuit. It should be noted that an excessive value of W/L will cause the parasitic capacitance Cmgnd between the switched capacitor circuit and the substrate to be too large, and the excessive parasitic capacitance Cmgnd will significantly affect the total capacitance of the first capacitor C0 and the second capacitor C1 value, thereby affecting the desired frequency of the voltage controlled oscillator. Therefore, the upper limit threshold of the value of W/L needs to be selected so that the parasitic capacitance Cmgnd between the switched capacitor circuit and the substrate does not significantly affect the total capacitance value of the first capacitor C0 and the second capacitor C1 and the quality factor Q of the switched capacitor circuit Meet expectations. In a preferred embodiment, the upper limit threshold of the value of W/L is selected such that the parasitic capacitance Cmgnd between the switched capacitor circuit and the substrate is less than one-twentieth of the total capacitance value of the first capacitor C0 and the second capacitor C1 . In another preferred embodiment, the upper limit threshold of the W/L value is selected so that the quality factor Q of the switched capacitor circuit is greater than 30, that is, it is ensured that the quality factor Q of the switched capacitor circuit is much greater than the quality factor Q of the inductor in the oscillator. In general process design, the quality factor Q of the inductor in the oscillator is about 3-8, so the upper limit threshold of the W/L value needs to be selected so that the quality factor Q of the switched capacitor circuit is greater than 30. By configuring the transistors in the above second preset manner, the resistance value of the equivalent resistance Rmsw of the transistors can be significantly reduced, thereby improving the quality factor Q of the switched capacitor circuit 10.

In one embodiment, the first capacitor C0 and the second capacitor C1 may be implemented by metal-oxide-metal (MOM) capacitors. MOM capacitors use a combination of finger structure and lamination. Based on the layout of the original decoupling capacitor, capacitors composed of the same layer of metal are used, and a multi-layer metal stack structure is connected in parallel to the decoupling capacitor, so that it can be used in smaller devices. A larger capacitance value is obtained under the area.

Figure 3 shows the layout structure of a single capacitor layer of a MOM capacitor. The capacitance value of a MOM capacitor is mainly formed by the sidewall capacitance of two adjacent interdigital metals. For example, a MOM capacitor placed vertically as shown in FIG. 3 includes 12 interdigital metals 310 . Assume that the unit capacitance formed by two adjacent interdigital metals 310 in the MOM capacitor is Cunit. Under the condition that the width and length of the interdigital metal remain unchanged, when the MOM capacitor includes 12 interdigital metals 310, the MOM The capacitance value of the capacitor is 11*Cunit. It should be noted that the number of interdigital metals 310 shown in FIG. 3 is only exemplary. The number of interdigital metals 310 may be more than 12 or less than 12 without departing from the spirit and scope of the present invention. 12.

According to a preferred embodiment of the present invention, the MOM capacitor may include a plurality of stacked metal layers as shown in FIG. The two interdigitated fingers refer to the common fulcrum 320 of the metal 310 .

For example, when the number of interdigital metals 310 shown in Figure 3 is three, based on the parasitic equivalent model of the MOM capacitor shown in Figure 3, the equivalent resistance R _pn of the MOM capacitor can be obtained =2* (((((R ₃₂₀ +R ₃₁₀ )//R ₃₁₀ )+R ₃₂₀ )//R ₃₁₀ )+R ₃₂₀ ), where R ₃₁₀ represents the resistance value of a single interdigital metal 310 , and R ₃₂₀ represents the resistance value corresponding to a single The cross refers to the resistance of the common fulcrum 320 of the metal 310 .

In one embodiment, when the first capacitor C0 and the second capacitor C1 are MOM capacitors, the first preset method may include one or more of the following methods: increasing the width w1 of the interdigital metal 310 to reduce the The resistance R ₃₁₀ of the interdigitated metal 310 is increased; the width w2 of the common fulcrum 320 is increased to reduce the resistance R ₃₂₀ of the common fulcrum; and a plurality of via holes are provided between multiple stacked metal layers. In a preferred embodiment, the width w1 of the interdigital metal 310 can be increased to the minimum width that can provide a through hole between two adjacent metal layers in a plurality of stacked metal layers using the process. In another preferred embodiment, the width w2 of the common fulcrum 320 can be increased to about 8 times the width w1 of the interdigital metal 310, thereby improving the Q value of the switched capacitor circuit without introducing unnecessary parasitics. The capacitor Cmgnd does not introduce excess capacitance area.

By configuring the first capacitor C0 and the second capacitor C1 in the first preset manner, the resistance value of the first parasitic resistance Rc0 of the first capacitor C0 and the resistance value of the second parasitic resistance Rc1 of the second capacitor C1 can be significantly reduced. , thereby improving the quality factor Q of the switched capacitor circuit 10 . Experiments have shown that configuring the first capacitor C0 and the second capacitor C1 in the above-mentioned first preset manner can increase the quality factor Q of the first capacitor C0 and the second capacitor C1 from approximately 15 to approximately 190 when the signal frequency is 28 GHz. .

It can be seen through experimental simulation that compared with the Q value of the switched capacitor circuit of 9 when the signal frequency is 28 GHz under the traditional process, the switched capacitor circuit according to one or more embodiments of the present invention can achieve a Q value of 34 when the signal frequency is 28 GHz. Q value. Therefore, the performance of a switched capacitor circuit according to one or more embodiments of the present invention is improved several times.

As shown in Figure 4, a method of forming a switched capacitor circuit according to one or more embodiments of the present invention includes the following steps:

Step 410: Set the first capacitor C0;

Step 420: Set the second capacitor C1;

Step 430: Set a transistor between the first capacitor C0 and the second capacitor C1; and

Step 440: Set a high-resistance resistor Rhg on the gate of the transistor.

Optionally, the method of forming a switched capacitor circuit according to one or more embodiments of the present invention further includes connecting the source S of the transistor to the first capacitor C0, and connecting the drain D of the transistor to the first capacitor C0. Two capacitors C1.

Optionally, the resistance of the high-resistance resistor Rhg may be greater than 20k ohms.

By setting a high-resistance resistor Rhg at the gate G of the transistor, on the one hand, it can reduce noise interference from the outside (for example, noise interference caused by the control voltage from the outside being directly connected to the gate G of the transistor), on the other hand This makes the source S of the transistor and the drain D of the transistor appear in a high resistance state toward the gate G of the transistor, thereby improving the ground capacitance to the differential mode capacitance, thereby reducing noise interference from ground coupling.

Optionally, the method of forming a switched capacitor circuit according to one or more embodiments of the present invention may further include configuring the first capacitor C0 and the second capacitor C1 in a first preset manner that enables Reduce the resistance of the first parasitic resistance Rc0 of the first capacitor C0 and the resistance of the second parasitic resistance Rc1 of the second capacitor C1.

Optionally, the method of forming a switched capacitor circuit according to one or more embodiments of the present invention may further include configuring the transistor in a second preset manner, the second preset manner causing the equivalent resistance Rmsw of the transistor to The resistance decreases. Optionally, the second preset method includes increasing the value of W/L of the transistor to a predetermined threshold, where W represents the active area width of the transistor and L represents the channel length of the transistor, and the predetermined threshold It is determined based on the parasitic capacitance Cmgnd between the switched capacitor circuit and the substrate and the quality factor Q of the switched capacitor circuit. By configuring the transistors in the second preset manner, the resistance value of the equivalent resistance Rmsw of the transistors can be significantly reduced, thereby improving the quality factor Q of the switched capacitor circuit 10 .

In one embodiment, the first capacitor C0 and the second capacitor C1 may be implemented by MOM capacitors. When the first capacitor C0 and the second capacitor C1 are MOM capacitors, the first preset method may include one or more of the following methods: increasing the width of the interdigital metal to reduce the resistance of the interdigital metal. ; Increase the width of the common fulcrum to reduce the resistance of the resistance of the common fulcrum; and provide multiple through holes between multiple stacked metal layers. By configuring the first capacitor C0 and the second capacitor C1 in the first preset manner, the resistance value of the first parasitic resistance Rc0 of the first capacitor C0 and the resistance value of the second parasitic resistance Rc1 of the second capacitor C1 can be significantly reduced. , thereby improving the quality factor Q of the switched capacitor circuit 10 . Experiments have shown that configuring the first capacitor C0 and the second capacitor C1 in the above-mentioned first preset manner can increase the quality factor Q of the first capacitor C0 and the second capacitor C1 from approximately 15 to approximately 190 when the signal frequency is 28 GHz. .

The method of forming a switched capacitor circuit according to one or more embodiments of the present invention sets a high-resistance resistor on the gate of the transistor, which on the one hand can reduce noise interference from the outside, and on the other hand allows the source and drain of the transistor to pass through. The gates of the transistors are all in a high-resistance state, which can improve the ground capacitance to the differential mode capacitance, thereby reducing ground-coupled noise interference. In addition, the method of forming a switched capacitor circuit according to one or more embodiments of the present invention can significantly increase the Q value of the switched capacitor circuit, reduce the power loss generated when high frequency signals pass through the switched capacitor circuit, and improve the efficiency of the switched capacitor circuit. High frequency signal response capability.

Additionally, as mentioned above, the present invention may also be implemented as a voltage controlled oscillator including a switched capacitor circuit according to an aspect of the present invention.

The embodiments and examples set forth herein are provided in order to best explain the embodiments according to the invention and its specific applications, and to thereby enable any person skilled in the art to make and use the invention. However, those skilled in the art will appreciate that the above description and examples are provided for convenience of illustration and example only. The description presented is not intended to cover all aspects of the invention or to limit the invention to the precise forms disclosed.

Claims

A switched capacitor circuit, characterized in that the switched capacitor circuit includes:

first capacitor;

the second capacitor; and

A transistor is provided between the first capacitor and the second capacitor, and a high-resistance resistor is provided on the gate of the transistor.
The circuit of claim 1, wherein the high resistance resistor has a resistance greater than 20k ohms.
The circuit of claim 1 , wherein the source of the transistor is connected to the first capacitor, and the drain of the transistor is connected to the second capacitor.
The circuit of claim 1 , wherein the first capacitor and the second capacitor are configured in a first preset manner, the first preset manner makes the resistance of the first parasitic resistance of the first capacitor The value and the resistance value of the second parasitic resistance of the second capacitor are reduced.
The circuit of claim 4, wherein the first capacitor and the second capacitor are MOM capacitors, the MOM capacitors include a plurality of stacked metal layers, each of the plurality of stacked metal layers Each metal layer includes a plurality of interdigital metals and a common fulcrum connecting the plurality of interdigital metals.
The circuit of claim 5, wherein when the first capacitor and the second capacitor are MOM capacitors, the first preset mode includes one or more of the following:

Increasing the width of the interdigital metal to reduce the resistance of the resistance of the interdigital metal;

increasing the width of the common fulcrum to reduce the resistance of the resistance of the common fulcrum; and

A plurality of through holes are provided between the plurality of stacked metal layers.
The circuit of claim 1, wherein the transistor is configured in a second preset manner, the second preset manner causes the equivalent resistance of the transistor to decrease.
The circuit of claim 7 , wherein the second preset manner includes increasing the value of W/L of the transistor to a predetermined threshold, where W represents the active area width of the transistor and L represents the transistor The predetermined threshold is determined based on the parasitic capacitance between the switched capacitor circuit and the substrate and the quality factor of the switched capacitor circuit.
The circuit of claim 1, wherein the transistor is a MOS transistor.
A voltage-controlled oscillator, characterized in that the voltage-controlled oscillator includes the switched capacitor circuit according to any one of claims 1-9.
A method of forming a switched capacitor circuit, characterized in that the method includes:

Set the first capacitor;

Set the second capacitor;

A transistor is provided between the first capacitor and the second capacitor; and

A high-value resistor is provided at the gate of the transistor.
The method according to claim 11, wherein the resistance of the high resistance resistor is greater than 20k ohms.
The method of claim 11, wherein said method further comprises:

The source of the transistor is connected to the first capacitor, and the drain of the transistor is connected to the second capacitor.
The method of claim 11, wherein said method further comprises:

Configuring the first capacitor and the second capacitor in a first preset manner, the first preset manner makes the resistance of the first parasitic resistance of the first capacitor and the second parasitic resistance of the second capacitor The resistance of the resistor decreases.
The method of claim 14, wherein the method further includes:

The first capacitor and the second capacitor are implemented as MOM capacitors, the MOM capacitor includes a plurality of stacked metal layers, and each metal layer of the plurality of stacked metal layers includes a plurality of interdigitated fingers. metal and a common fulcrum connecting the plurality of interdigitated metals.
The method of claim 15, wherein when the first capacitor and the second capacitor are implemented as MOM capacitors, the first preset mode includes one or more of the following:

Increasing the width of the interdigital metal to reduce the resistance of the resistance of the interdigital metal;

increasing the width of the common fulcrum to reduce the resistance of the resistance of the common fulcrum; and

A plurality of through holes are provided between the plurality of stacked metal layers.
The method of claim 11, wherein said method further comprises:

The transistor is configured in a second preset manner, and the second preset manner causes the resistance value of the equivalent resistance of the transistor to decrease.
The method of claim 17, wherein the second preset manner includes increasing the value of W/L of the transistor to a predetermined threshold, where W represents the active area width of the transistor and L represents the transistor The predetermined threshold is determined based on the parasitic capacitance between the switched capacitor circuit and the substrate and the quality factor of the switched capacitor circuit.
The method according to claim 11, wherein the transistor is a MOS transistor.