CN117542843A - Capacitor structure, manufacturing method and application thereof - Google Patents
Capacitor structure, manufacturing method and application thereof Download PDFInfo
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- CN117542843A CN117542843A CN202311325785.5A CN202311325785A CN117542843A CN 117542843 A CN117542843 A CN 117542843A CN 202311325785 A CN202311325785 A CN 202311325785A CN 117542843 A CN117542843 A CN 117542843A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 424
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 317
- 239000004065 semiconductor Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000010410 layer Substances 0.000 claims description 513
- 238000000034 method Methods 0.000 claims description 66
- 230000008569 process Effects 0.000 claims description 52
- 239000011229 interlayer Substances 0.000 claims description 35
- 238000001259 photo etching Methods 0.000 claims description 25
- 238000001465 metallisation Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 17
- 238000002161 passivation Methods 0.000 claims description 14
- 239000011248 coating agent Substances 0.000 claims description 11
- 238000000576 coating method Methods 0.000 claims description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 6
- 239000003989 dielectric material Substances 0.000 claims 6
- 238000000151 deposition Methods 0.000 description 12
- 238000001883 metal evaporation Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 238000000605 extraction Methods 0.000 description 7
- 238000003475 lamination Methods 0.000 description 6
- 239000004642 Polyimide Substances 0.000 description 4
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000002346 layers by function Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005019 vapor deposition process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
Abstract
The invention discloses a capacitor structure, a manufacturing method of the capacitor structure and application thereof, wherein the capacitor structure comprises at least two of a first capacitor, a second capacitor and a third capacitor which are arranged in different areas on a semiconductor substrate, and the first capacitor comprises a first metal layer, a first dielectric layer and a second metal layer of a first capacitor area from bottom to top; the second capacitor comprises a first metal layer, a first dielectric layer, a second dielectric layer and a third metal layer of a second capacitor region from bottom to top; the third capacitor comprises a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer and a third metal layer in a third capacitor region from bottom to top, and the first metal layer and the third metal layer in the third capacitor region are electrically connected. At least two different capacitor structures are formed by different stacking arrangement of a plurality of metal layers and dielectric layers in different areas so as to meet the requirements of selecting various capacitance values and control the variability of the capacitance values.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a capacitor structure, a manufacturing method of the capacitor structure and application of the capacitor structure.
Background
In a semiconductor integrated circuit, a capacitor is widely used as a device for storing charge, coupling, filtering, or the like. With the improvement of the performance of active devices in integrated circuits, the requirement for the controllability of the capacitance is also higher and higher. For example, as the frequency of rf amplifier operation increases, the capacitance of the matched capacitor used at its output also decreases, and the variability of the capacitance during the process is also increasingly required.
MIM capacitors are commonly used in semiconductor devices, particularly in high frequency devices. Conventional MIM capacitors include upper and lower electrode plates and a dielectric layer sandwiched therebetween. Variation in metal dimensions and variation in dielectric during processing are major causes of capacitance variation, reducing controllability. In addition, the design of the selective requirement of the chip to the capacitor is also a technical problem to be solved.
Disclosure of Invention
Aiming at the defects existing in the prior art, the invention provides a capacitor structure, a manufacturing method of the capacitor structure and application thereof.
In order to achieve the above object, the technical scheme of the present invention is as follows:
a capacitor structure comprises at least two of a first capacitor, a second capacitor and a third capacitor which are arranged on a semiconductor substrate, wherein the first capacitor is arranged in a first capacitor area, the second capacitor is arranged in a second capacitor area, the third capacitor is arranged in a third capacitor area, and the first capacitor comprises a first metal layer, a first dielectric layer and a second metal layer in the first capacitor area from bottom to top; the second capacitor comprises a first metal layer, a first dielectric layer, a second dielectric layer and a third metal layer of a second capacitor region from bottom to top; the third capacitor comprises a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer and a third metal layer in a third capacitor region from bottom to top, and the first metal layer and the third metal layer in the third capacitor region are electrically connected.
The first metal layer, the second metal layer and the third metal layer are respectively metal layers formed by the same metal deposition process and are separated into different parts located in different capacitance areas through etching, namely, the same metal layer is separated and independent from each other in different capacitance areas, so that the first capacitance, the second capacitance and the third capacitance are mutually independent and can independently perform the functions of the first capacitance, the second capacitance and the third capacitance or perform series/parallel connection and application through other connecting structures according to actual requirements.
Optionally, the semiconductor device further comprises an insulating layer and a fourth metal layer, wherein the insulating layer covers the first capacitor region, the second capacitor region and the third capacitor region, the insulating layer is respectively opened to at least two of the first capacitor, the second capacitor and the third capacitor, and the fourth metal layer is respectively filled in the openings.
Optionally, in the third capacitor region, the fourth metal layer includes a first portion for electrically connecting the first metal layer and the third metal layer, and a second portion for leading out the second metal layer, where the first portion and the second portion are independent from each other.
Optionally, the second dielectric layer covers the first capacitor surface and has an opening on the second metal layer.
Optionally, the thickness of the first dielectric layer ranges from 40 nm to 300nm.
Optionally, the thickness of the second dielectric layer ranges from 40 nm to 300nm.
Optionally, the semiconductor substrate includes a GaAs-based epitaxial layer, a passivation layer covers a surface of the epitaxial layer or the epitaxial layer is provided with an isolation region, and at least two of the first capacitor, the second capacitor and the third capacitor are disposed on the passivation layer or the isolation region.
Optionally, the first metal layer is a Ti/Pt/Au/Ti stack, and the thicknesses are respectively Ti: 10-100 nm, pt: 20-100 nm, au: 1-4 mu m, ti: 3-20 nm; the second metal layer is a Ti/Pt/Au/Ti lamination, and the thicknesses are respectively as follows: 10-100 nm, pt: 20-100 nm, au: 200-1000 nm, ti: 3-20 nm; the third metal layer is a Ti/Pt/Au/Ti lamination, and the thicknesses are respectively as follows: 10-100 nm, pt: 20-100 nm, au: 200-1000 nm, ti: 3-20 nm; the fourth metal layer is a Ti/Pt/Au/Ti lamination, and the thicknesses are respectively Ti: 10-100 nm, pt: 20-100 nm, au: 1-4 mu m, ti: 3-20 nm.
A manufacturing method of a capacitor structure comprises the following steps:
1) Forming a first metal layer on the first capacitor region and the second capacitor region of the semiconductor substrate through photoetching and metal deposition processes;
2) Forming a first dielectric layer;
3) Forming a second metal layer on the first dielectric layer of the first capacitor region through photoetching and metal deposition processes;
4) Forming a second dielectric layer;
5) And forming a third metal layer on the second dielectric layer of the second capacitor region through photoetching and metal deposition processes.
Optionally, the method further comprises the following steps:
6) Coating an insulating layer, and forming openings exposing the second metal layer and the third metal layer respectively through an etching process;
7) And forming a fourth metal layer through photoetching and a metal deposition process, wherein the fourth metal layer is respectively connected with the second metal layer and the third metal layer through the opening.
A manufacturing method of a capacitor structure comprises the following steps:
1) Forming a first metal layer on the first capacitor region and the third capacitor region of the semiconductor substrate through photoetching and metal deposition processes;
2) Forming a first dielectric layer;
3) Forming second metal layers on the first dielectric layers of the first capacitor region and the third capacitor region respectively through photoetching and metal deposition processes;
4) Forming a second dielectric layer;
5) And forming a third metal layer on the second dielectric layer of the third capacitor region through photoetching and metal deposition processes.
Optionally, the method further comprises the following steps:
6) Coating an insulating layer, and forming openings of the first metal layer, the second metal layer and the third metal layer of the third capacitor by etching;
7) And forming a fourth metal layer through photoetching and a metal deposition process, wherein the fourth metal layer is respectively connected with the first metal layer, the second metal layer and the third metal layer through openings, and the first metal layer and the third metal layer of the third capacitor are connected through the fourth metal layer.
A manufacturing method of a capacitor structure comprises the following steps:
1) Forming a first metal layer on the second capacitor region and the third capacitor region of the semiconductor substrate through photoetching and metal deposition processes;
2) Forming a first dielectric layer;
3) Forming a second metal layer on the first dielectric layer of the third capacitor region through photoetching and metal deposition processes;
4) Forming a second dielectric layer;
5) And forming a third metal layer on the second dielectric layers of the second capacitor region and the third capacitor region respectively through photoetching and metal deposition processes.
Optionally, the method further comprises the following steps:
6) Coating an insulating layer, and forming third metal layers respectively exposing the second capacitor through an etching process, wherein openings of the first metal layer, the second metal layer and the third metal layer of the third capacitor are formed;
7) And forming a fourth metal layer through photoetching and a metal deposition process, wherein the fourth metal layer is respectively connected with the first metal layer, the second metal layer and the third metal layer through openings, and the first metal layer and the third metal layer of the third capacitor are connected through the fourth metal layer.
A manufacturing method of a capacitor structure comprises the following steps:
1) Forming a first metal layer on the first capacitance region, the second capacitance region and the third capacitance region of the semiconductor substrate through photoetching and metal deposition processes;
2) Forming a first dielectric layer;
3) Forming a second metal layer on the first dielectric layers of the first capacitor region and the third capacitor region through photoetching and metal deposition processes;
4) Forming a second dielectric layer;
5) And forming a third metal layer on the second dielectric layers of the second capacitor region and the third capacitor region respectively through photoetching and metal deposition processes.
Optionally, the method further comprises the following steps:
6) Coating an insulating layer, and forming a second metal layer of the first capacitor and a third metal layer of the second capacitor respectively through an etching process, wherein openings of the first metal layer, the second metal layer and the third metal layer of the third capacitor are formed;
7) And forming a fourth metal layer through photoetching and a metal deposition process, wherein the fourth metal layer is respectively connected with the first metal layer, the second metal layer and the third metal layer through openings, and the first metal layer and the third metal layer of the third capacitor are connected through the fourth metal layer.
The manufacturing method of the capacitor structures comprises the steps that the first metal layer is used as the lower polar plates of the first capacitor, the second capacitor and the third capacitor respectively; the second metal layer is used as an upper polar plate of the first capacitor and a middle polar plate of the third capacitor; the third metal layer is respectively used as upper polar plates of the second capacitor and the third capacitor.
A semiconductor chip comprises the capacitor structure.
Optionally, the semiconductor chip includes HBT transistors and/or HEMT devices.
The beneficial effects of the invention are as follows:
1. at least two different capacitor structures are formed by different stacking arrangement of a plurality of metal layers and dielectric layers in different areas so as to meet the requirements of selecting various capacitance values and control the variability of the capacitance values.
2. At least two different capacitor structures realize the sharing of a plurality of processes, simplify the process steps, and are suitable for practical production and application.
Drawings
Fig. 1 is a schematic diagram of a capacitor structure in embodiment 1;
FIG. 2 is a schematic process diagram of a method for fabricating a capacitor structure according to embodiment 1, wherein the structure obtained by each step is shown;
FIG. 3 is a schematic diagram of a capacitor structure in embodiment 2;
FIG. 4 is a schematic process diagram of a method for fabricating a capacitor structure according to embodiment 2, wherein the structure obtained by each step is shown;
FIG. 5 is a schematic diagram of a capacitor structure in embodiment 3;
FIG. 6 is a schematic process diagram of a method for fabricating a capacitor structure according to embodiment 3, wherein the structure obtained by each step is shown;
FIG. 7 is a schematic diagram of a capacitor structure in embodiment 4;
fig. 8 is a process diagram of a method for fabricating a capacitor structure in embodiment 4, which shows the structure obtained by each step.
Detailed Description
The invention is further explained below with reference to the drawings and specific embodiments. The drawings of the present invention are merely schematic to facilitate understanding of the present invention, and specific proportions thereof may be adjusted according to design requirements. The definition of the context of the relative elements and the front/back of the figures described herein should be understood by those skilled in the art to refer to the relative positions of the elements and thus all the elements may be reversed to represent the same elements, which are all within the scope of the present disclosure.
The invention provides a capacitor structure and a manufacturing method thereof, so as to form at least two of a first capacitor, a second capacitor and a third capacitor in different areas through different stacks, wherein the manufacturing method comprises the following steps:
forming a first metal layer on a semiconductor substrate;
forming a first dielectric layer;
forming a second metal layer;
forming a second dielectric layer;
forming a third metal layer;
forming a capacitor structure through the steps, wherein the capacitor structure comprises at least two of a first capacitor, a second capacitor and a third capacitor, the first capacitor is arranged in a first capacitor area, the second capacitor is arranged in a second capacitor area, the third capacitor is arranged in a third capacitor area, and the first capacitor comprises a first metal layer, a first dielectric layer and a second metal layer in the first capacitor area from bottom to top; the second capacitor comprises a first metal layer, a first dielectric layer, a second dielectric layer and a third metal layer of a second capacitor region from bottom to top; the third capacitor comprises a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer and a third metal layer of a third capacitor region from bottom to top.
Further, the first metal layer and the third metal layer in the third capacitor region are electrically connected.
The first metal layer is respectively used as a lower polar plate of the first capacitor, the second capacitor and the third capacitor; the second metal layer is used as an upper polar plate of the first capacitor and a middle polar plate of the third capacitor; the third metal layer is respectively used as upper polar plates of the second capacitor and the third capacitor.
Example 1
Referring to fig. 1, the capacitor structure of embodiment 1 includes a first capacitor C disposed on a semiconductor substrate 1 1 And a second capacitor C 2 . In this embodiment, the semiconductor substrate 1 is a GaAs-based semiconductor layer, such as an epitaxial layer of a GaAs-based Heterojunction Bipolar Transistor (HBT) or the like, for forming a corresponding functional device. The surface of the epitaxial layer is provided with a passivation layer V 0 Passivation layer V 0 SiN or other material is used. The output end of the device is provided with a capacitor structure, in this embodiment, the capacitor region on the surface of the epitaxial layer forms a first capacitor C by different stacks of a plurality of metal layers and dielectric layers in different regions 1 And a second capacitor C 2 . Wherein, the first capacitor C 1 Is positioned in the first capacitance area A and comprises a first metal layer M from bottom to top 1 First dielectric layer V 1 And a second metal layer M 2 Second capacitor C 2 The second capacitor region B comprises a first metal layer M from bottom to top 1 First dielectric layer V 1 Second dielectric layer V 2 And a third metal layer M 3 . First capacitor C 1 And a second capacitor C 2 Covered with an insulating layer P and passing through a fourth metal layer M located in the first and second capacitive areas a and B, respectively 4 And respectively realizing the extraction. Thus, the first metal layer M 1 Respectively as first capacitors C 1 And a second capacitor C 2 Lower plate of (a); second metal layer M 2 As the first capacitor C 1 Upper plate of (a); third metal layer M 3 As the second capacitor C 2 Upper plate of (a); first dielectric layer V 1 As the first capacitor C 1 Is an interlayer dielectric of a first dielectric layer V 1 Second dielectric layer V 2 As the second capacitor C 2 Is an interlayer dielectric of the first capacitor C 1 And a second capacitorC 2 With different dielectric layer thicknesses to achieve different capacitance values.
The obtained semiconductor chip comprises an HBT device and the capacitor structure matched with the output end of the HBT device, and can be applied to a radio frequency amplifier.
Referring to fig. 2, in the fabrication of the capacitor structure, a first metal layer M is first formed by photolithography and metal evaporation 1 As shown in FIG. 2 (a), which is used for forming the first capacitors C respectively 1 And a second capacitor C 2 Is arranged on the lower polar plate. Then adopting CVD and other processes to deposit SiN with thickness of 100nm as first dielectric layer V 1 As can be appreciated from fig. 2 (b), the first dielectric layer V 1 Covering the first metal layer M 1 Surface and exposed passivation layer V 0 A surface. First dielectric layer V in first capacitor region by photoetching and metal evaporation process 1 On-fabricating a second metal layer M 2 As shown in fig. 2 (c), a MIM capacitor structure is formed. Depositing 100nm SiN as the second dielectric layer V 2 It can be appreciated that the second dielectric layer V 2 Covering the second metal layer M 2 Surface and exposed first dielectric layer V 1 Etching the second dielectric layer V 2 In the second metal layer M 2 The opening a is formed as shown in fig. 2 (d), or the opening a may be etched in a subsequent process. A second dielectric layer V in the second capacitor region by photoetching and metal evaporation process 2 On the third metal layer M 3 Another MIM capacitor structure is formed as shown in fig. 2 (e). Coating an insulating layer P such as polyimide, opening the first and second capacitor regions, depositing metal to form a second metal layer M 2 And a third metal layer M 3 Connected fourth metal layer M 4 As in fig. 2 (f).
The deposition and etching of each metal layer and dielectric layer can be integrated in the manufacturing process of the functional device and synchronously manufactured with each functional layer of the device, so that the process steps are simplified. For example, a second metal layer M 2 Formed in the same process as the collector metal of the HBT device, or a first metal layer M 1 Fourth metal layer M 4 Is co-located with the metal interconnect of the HBT deviceOne process species. Optionally, the first metal layer is a Ti/Pt/Au/Ti stack, and the thicknesses are respectively Ti: 10-100 nm, pt: 20-100 nm, au: 1-4 mu m, ti: 3-20 nm; the second metal layer is a Ti/Pt/Au/Ti lamination, and the thicknesses are respectively as follows: 10-100 nm, pt: 20-100 nm, au: 200-1000 nm, ti: 3-20 nm; the third metal layer is a Ti/Pt/Au/Ti lamination, and the thicknesses are respectively as follows: 10-100 nm, pt: 20-100 nm, au: 200-1000 nm, ti: 3-20 nm; the fourth metal layer is a Ti/Pt/Au/Ti lamination, and the thicknesses are respectively Ti: 10-100 nm, pt: 20-100 nm, au: 1-4 mu m, ti: 3-20 nm.
Prior to capacitor fabrication, capacitors and layout dimensions are typically designed according to requirements. Capacitance formula: c=εs/d=ε (l×w)/d; (epsilon is the dielectric constant of the medium between the polar plates, S is the polar plate area, d is the distance between the polar plates, L is the length of the polar plates, and W is the width of the polar plates.) in the actual process, dimensional deviation can occur, and the dimensional deviation can lead to the fact that the actual capacitance value is not consistent with the preset capacitance value, namely the capacitance value variation is generated. Therefore, the larger the variation of C, i.e., the variation of L, W, d, the smaller the variation percentage of C, as can be seen from the formula, with the change value unchanged, the larger L, W, d.
Designing a first capacitor C 1 And a second capacitor C 2 The following are provided:
after the dimensional deviation, the actual capacitance and the difference value of the two are as follows:
due to the second capacitance C 2 The dielectric layer thickness of (a) is the superposition of the first dielectric layer and the second dielectric layer, relative to the first capacitor C 1 The capacitance variation is small, i.e. a low-density capacitor is selected, which can be used for reducing capacitance variation caused by size fluctuation in the process of capacitor manufacture and providing radio frequencyYield of the amplifier.
In another application, moreover, the first capacitance C 1 And a second capacitor C 2 Different capacitance values can be realized through superposition of different dielectric layer thicknesses when the same length and width dimensions or different length and width dimensions are designed, so that more feasible choices are provided.
Correspondingly, the capacitor structure in the embodiment of the invention is applied to a semiconductor chip, and the semiconductor chip comprises a plurality of HBT devices, a plurality of inductors, a plurality of resistors, a plurality of diodes and a plurality of first capacitors C 1 And a plurality of second capacitors C 2 Constituting a radio frequency amplifier chip.
Example 2
Referring to fig. 3, the capacitor structure of embodiment 2 includes a passivation layer V disposed on a semiconductor substrate 1 0 First capacitor C 1 And a third capacitor C 3 . Wherein, the first capacitor C 1 Is positioned in the first capacitance area A and comprises a first metal layer M from bottom to top 1 First dielectric layer V 1 And a second metal layer M 2 Third capacitor C 3 The third capacitor region C comprises a first metal layer M from bottom to top 1 First dielectric layer V 1 Second metal layer M 2 Second dielectric layer V 2 And a third metal layer M 3 . First capacitor C 1 And a third capacitor C 3 Covered with an insulating layer P and passing through a fourth metal layer M located in the first and third capacitive areas a and C, respectively 4 And respectively realizing the extraction. Wherein in the third capacitance region C, the fourth metal layer M 4 Comprising a first part 41 and a second part 42 which are independent of each other, a first metal layer M 1 And a third metal layer M 3 The electrical connection and the extraction are realized through the first part 41, and the second metal layer M 2 And is led out through the second portion 42 to form a parallel stacked capacitor structure. First metal layer M 1 Respectively as first capacitors C 1 And a third capacitor C 3 Lower plate of (a); second metal layer M 2 As the first capacitor C 1 Upper plate of (C) and third capacitor C 3 Is a middle polar plate; third metal layer M 3 As the third capacitor C 3 Upper plate of (a); first oneDielectric layer V 1 As the first capacitor C 1 Is an interlayer dielectric of a first dielectric layer V 1 As the third capacitor C 3 Interlayer medium between lower polar plate and middle polar plate, second medium layer V 2 As the third capacitor C 3 Interlayer dielectric between the middle plate and the upper plate, thereby a first capacitance C 1 And a third capacitor C 3 Different capacitance values are realized. Wherein the third capacitor C 3 The stacked capacitor with the parallel structure increases the capacity on the premise of saving the area, and realizes the selection of large capacitance density.
Referring to fig. 4, in the fabrication of the capacitor structure, a first metal layer M is first formed by photolithography and metal evaporation 1 As shown in FIG. 4 (a), it is used to form the first capacitors C 1 And a third capacitor C 3 Is arranged on the lower polar plate. Then adopting CVD and other processes to deposit SiN with thickness of 100nm as first dielectric layer V 1 As can be appreciated from fig. 4 (b), the first dielectric layer V 1 Covering the first metal layer M 1 Surface and exposed passivation layer V 0 A surface. First dielectric layer V in first capacitor region and third capacitor region by photoetching and metal vapor deposition process 1 Respectively manufacturing a second metal layer M 2 As shown in fig. 4 (c), MIM capacitor structures are formed. Depositing SiN with thickness of 100nm as a second dielectric layer V by adopting CVD and other processes 2 As can be appreciated from fig. 4 (d), the second dielectric layer V 2 Covering the second metal layer M 2 Surface and exposed first dielectric layer V 1 A surface; etching the second dielectric layer V 2 Forming a bare second metal layer M in the first capacitor region 2 Form a bare first metal layer M in the third capacitor region 1 Is exposed through the opening b and the second metal layer M 2 Or the openings a/b/c may be etched in a subsequent process. Second dielectric layer V in third capacitor region by photoetching and metal evaporation process 2 On the third metal layer M 3 As shown in fig. 4 (e), a stacked capacitor structure is formed. Coating an insulating layer P such as polyimide corresponding to the openings a/b/c and a third metal layer M 3 Respectively opening and depositing a fourth metal layer M 4 Opening in insulating layer PAnd a fourth metal layer M 4 Make the third capacitor C 3 Is a first metal layer M of 1 And a third metal layer M 3 Connection as in fig. 4 (f).
Likewise, the deposition and etching of the various metal and dielectric layers may be integrated into the fabrication process of the functional device, in synchronization with the fabrication of the various functional layers of the device, to simplify the process steps.
Correspondingly, the capacitor structure in the embodiment of the invention is applied to a semiconductor chip, and the semiconductor chip comprises a plurality of HEMT devices, a plurality of inductors, a plurality of resistors, a plurality of diodes and a plurality of first capacitors C 1 And a plurality of third capacitors C 2 Constituting a radio frequency amplifier chip. The HEMT device is a GaAs-based pHEMT device.
Example 3
Referring to fig. 5, the capacitor structure of embodiment 3 includes a passivation layer V disposed on a semiconductor substrate 1 0 Second capacitor C 2 And a third capacitor C 3 . Wherein the second capacitor C 2 The second capacitor region C comprises a first metal layer M from bottom to top 1 First dielectric layer V 1 Second dielectric layer V 2 And a third metal layer M 3 Third capacitor C 3 The third capacitor region C comprises a first metal layer M from bottom to top 1 First dielectric layer V 1 Second metal layer M 2 Second dielectric layer V 2 And a third metal layer M 3 . Second capacitor C 2 And a third capacitor C 3 Covered with an insulating layer P and passing through a fourth metal layer M located in the second and third capacitive areas B and C, respectively 4 And respectively realizing the extraction. Wherein in the third capacitance region C, the fourth metal layer M 4 Comprising a first part 41 and a second part 42 which are independent of each other, a first metal layer M 1 And a third metal layer M 3 The electrical connection and the extraction are realized through the first part 41, and the second metal layer M 2 And is led out through the second portion 42 to form a parallel stacked capacitor structure. First metal layer M 1 Respectively as second capacitors C 2 And a third capacitor C 3 Lower plate of (a); second metal layer M 2 As the third capacitor C 3 Is a middle polar plate; first, theThree metal layers M 3 Respectively as second capacitors C 2 And a third capacitor C 3 Upper plate of (a); first dielectric layer V 1 Second dielectric layer V 2 As the second capacitor C 2 Is a dielectric between layers; first dielectric layer V 1 As the third capacitor C 3 Interlayer medium between lower polar plate and middle polar plate, second medium layer V 2 As the third capacitor C 3 Interlayer dielectric between the middle plate and the upper plate, thereby a second capacitance C 2 And a third capacitor C 3 Different capacitance values are realized. Wherein the first dielectric layer and the second dielectric layer are used as the second capacitor C 2 And at the third capacitor C 3 Through the second metal layer M 2 Spaced apart, forming different capacitive structures.
Referring to fig. 6, in the fabrication of the capacitor structure, a first metal layer M is formed by photolithography and metal evaporation 1 As shown in FIG. 6 (a), it is used to form the second capacitors C 2 And a third capacitor C 3 Is arranged on the lower polar plate. Then adopting CVD and other processes to deposit SiN with thickness of 100nm as first dielectric layer V 1 As can be appreciated from fig. 6 (b), the first dielectric layer V 1 Covering the first metal layer M 1 Surface and exposed passivation layer V 0 A surface. First dielectric layer V in third capacitor region by photoetching and metal evaporation process 1 On-fabricating a second metal layer M 2 As shown in fig. 6 (c). Depositing SiN with thickness of 100nm as a second dielectric layer V by adopting CVD and other processes 2 As can be appreciated from fig. 6 (d), the second dielectric layer V 2 Covering the second metal layer M 2 Surface and exposed first dielectric layer V 1 A surface; etching the second dielectric layer V 2 Forming a bare first metal layer M in the third capacitor region 1 Is exposed through the opening b and the second metal layer M 2 Or the openings b/c may be etched in a subsequent process. A second dielectric layer V in the second capacitance region and the third capacitance region by photoetching and metal evaporation process 2 Respectively preparing a third metal layer M 3 As shown in fig. 6 (e), MIM structures and stacked capacitor structures are formed, respectively. Coating an insulating layer P of polyimide, for example, and opening correspondinglyPort b/c, third metal layer M of second and third capacitance regions 3 Respectively opening and depositing a fourth metal layer M 4 In the opening of the insulating layer P, and a fourth metal layer M 4 Make the third capacitor C 3 Is a first metal layer M of 1 And a third metal layer M 3 Connection as in fig. 6 (f).
Likewise, the deposition and etching of the various metal and dielectric layers may be integrated into the fabrication process of the functional device, in synchronization with the fabrication of the various functional layers of the device, to simplify the process steps.
Correspondingly, the capacitor structure in the embodiment of the invention is applied to a semiconductor chip, and the semiconductor chip comprises a plurality of HBT devices, a plurality of inductors, a plurality of resistors, a plurality of diodes and a plurality of second capacitors C 2 And a plurality of third capacitors C 3 Constituting a radio frequency amplifier chip.
Example 4
Referring to fig. 7, the capacitor structure of embodiment 4 includes a passivation layer V disposed on a semiconductor substrate 1 0 First capacitor C 1 A second capacitor C 2 And a third capacitor C 3 . Wherein, the first capacitor C 1 Is positioned in the first capacitance area A and comprises a first metal layer M from bottom to top 1 First dielectric layer V 1 And a second metal layer M 2 Second capacitor C 2 The second capacitor region B comprises a first metal layer M from bottom to top 1 First dielectric layer V 1 Second dielectric layer V 2 And a third metal layer M 3 Third capacitor C 3 The third capacitor region C comprises a first metal layer M from bottom to top 1 First dielectric layer V 1 Second metal layer M 2 Second dielectric layer V 2 And a third metal layer M 3 . First capacitor C 1 A second capacitor C 2 And a third capacitor C 3 Covered with an insulating layer P and passing through a fourth metal layer M located in the first, second and third capacitance areas a, B and C, respectively 4 And respectively realizing the extraction. Wherein in the third capacitance region C, the fourth metal layer M 4 Comprising a first part 41 and a second part 42 which are independent of each other, a first metal layer M 1 And (d)Three metal layers M 3 The electrical connection and the extraction are realized through the first part 41, and the second metal layer M 2 And is led out through the second portion 42 to form a parallel stacked capacitor structure. First metal layer M 1 Respectively as first capacitors C 1 A second capacitor C 2 And a third capacitor C 3 Lower plate of (a); second metal layer M 2 As the first capacitor C 1 Upper plate of (C) and third capacitor C 3 Is a middle polar plate; third metal layer M 3 As the second capacitor C 2 Upper plate of (C) and third capacitor C 3 Upper plate of (a); first dielectric layer V 1 As the first capacitor C 1 Is an interlayer dielectric of a first dielectric layer V 1 Second dielectric layer V 2 As the second capacitor C 2 Is an interlayer dielectric of a first dielectric layer V 1 As the third capacitor C 3 Interlayer medium between lower polar plate and middle polar plate, second medium layer V 2 As the third capacitor C 3 Interlayer dielectric between the middle plate and the upper plate, thereby a first capacitance C 1 A second capacitor C 2 And a third capacitor C 3 Three different capacitance values are realized.
Referring to fig. 8, in the fabrication of the capacitor structure, a first metal layer M is first formed by photolithography and metal evaporation 1 As shown in FIG. 8 (a), it is used for forming the first capacitors C respectively 1 A second capacitor C 2 And a third capacitor C 3 Is arranged on the lower polar plate. Then adopting CVD and other processes to deposit SiN with thickness of 100nm as first dielectric layer V 1 As can be appreciated from fig. 8 (b), the first dielectric layer V 1 Covering the first metal layer M 1 Surface and exposed passivation layer V 0 A surface. First dielectric layer V in first capacitor region and third capacitor region by photoetching and metal vapor deposition process 1 Respectively manufacturing a second metal layer M 2 As shown in fig. 8 (c), MIM capacitor structures are formed. Depositing SiN with thickness of 100nm as a second dielectric layer V by adopting CVD and other processes 2 As can be appreciated from fig. 8 (d), the second dielectric layer V 2 Covering the second metal layer M 2 Surface and exposed first dielectric layer V 1 A surface; etching the second dielectric layer V 2 In the first capacitance regionForming a bare second metal layer M 2 Form a bare first metal layer M in the third capacitor region 1 Is exposed through the opening b and the second metal layer M 2 Or the openings a/b/c may be etched in a subsequent process. A second dielectric layer V respectively arranged in the second capacitance region and the third capacitance region by photoetching and metal evaporation process 2 On the third metal layer M 3 As shown in fig. 8 (e), MIM capacitor and stacked capacitor structures are formed, respectively. A third metal layer M coated with an insulating layer P such as polyimide and corresponding to the openings a/b/c and the second and third capacitance regions 3 Respectively opening and depositing a fourth metal layer M 4 In the opening of the insulating layer P, and a fourth metal layer M 4 Make the third capacitor C 3 Is a first metal layer M of 1 And a third metal layer M 3 Connection as in fig. 8 (f).
Likewise, the deposition and etching of each metal layer and dielectric layer can be integrated in the fabrication process of the functional device, in synchronization with the fabrication of each functional layer of the device, to simplify the process steps, and to achieve the simultaneous setting of the capacitance structures of three capacitances, to provide more options.
Correspondingly, the capacitor structure in the embodiment of the invention is applied to a semiconductor chip, and the semiconductor chip comprises a plurality of HEMT devices, a plurality of inductors, a plurality of resistors, a plurality of diodes and a plurality of first capacitors C 1 A second capacitor C 2 And a plurality of third capacitors C 3 Constituting a radio frequency amplifier chip. The HEMT device is a GaAs-based pHEMT device.
It should be noted that in several embodiments of the present invention, the surface of the epitaxial layer of the first to third capacitor regions is provided with a passivation layer V 0 The capacitor structure is isolated from the epitaxial layer. In other applications, the epitaxial layers of the first to third capacitor regions may be ion implanted to form isolation regions, and the capacitor structure may be disposed on the isolation regions.
The foregoing embodiments are only used for further illustrating the capacitor structure, the method for manufacturing the capacitor structure and the application thereof, but the invention is not limited to the embodiments, and any simple modification, equivalent variation and modification of the foregoing embodiments according to the technical substance of the invention falls within the scope of the technical solution of the invention.
Claims (20)
1. A capacitor structure, characterized by: the semiconductor device comprises at least two of a first capacitor, a second capacitor and a third capacitor which are arranged on a semiconductor substrate, wherein the first capacitor is arranged in a first capacitor area, the second capacitor is arranged in a second capacitor area, the third capacitor is arranged in a third capacitor area, and the first capacitor comprises a first metal layer, a first dielectric layer and a second metal layer in the first capacitor area from bottom to top; the second capacitor comprises a first metal layer, a first dielectric layer, a second dielectric layer and a third metal layer of a second capacitor region from bottom to top; the third capacitor comprises a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer and a third metal layer in a third capacitor region from bottom to top, and the first metal layer and the third metal layer in the third capacitor region are electrically connected.
2. The capacitive structure of claim 1, wherein: further comprises an insulating layer and a fourth metal layer, wherein the insulating layer coversThe saidThe insulating layer is respectively opened to at least two of the first capacitor, the second capacitor and the third capacitor, and the fourth metal layer is respectively filled in the openings.
3. The capacitive structure of claim 1, wherein: in the third capacitor region, the fourth metal layer includes a first portion for electrically connecting the first metal layer and the third metal layer and a second portion for leading out the second metal layer, where the first portion and the second portion are independent of each other.
4. The capacitive structure of claim 1, wherein: the second dielectric layer covers the first capacitor surface and is provided with an opening on the second metal layer.
5. The capacitive structure of claim 1, wherein: the thickness of the first dielectric layer ranges from 40 nm to 300nm; the thickness of the second dielectric layer ranges from 40 nm to 300nm.
6. The capacitive structure of claim 1, wherein: the semiconductor substrate comprises a GaAs-based epitaxial layer, a passivation layer is covered on the surface of the epitaxial layer or an isolation region is arranged on the epitaxial layer, and at least two of the first capacitor, the second capacitor and the third capacitor are arranged on the passivation layer or the isolation region.
7. The capacitive structure of claim 1, wherein: the capacitor structure comprises a first capacitor and a second capacitor which are arranged on the semiconductor substrate; the first metal layer is respectively used as a lower polar plate of the first capacitor and a lower polar plate of the second capacitor; the second metal layer is used as an upper polar plate of the first capacitor; the third metal layer is used as an upper polar plate of the second capacitor; the first dielectric layer is used as an interlayer dielectric of the first capacitor, and the first dielectric layer and the second dielectric layer are used as interlayer dielectrics of the second capacitor.
8. The capacitive structure of claim 1, wherein: the capacitor structure comprises a first capacitor and a third capacitor which are arranged on a semiconductor substrate, wherein the first metal layer is respectively used as a lower polar plate of the first capacitor and a lower polar plate of the third capacitor; the second metal layer is used as an upper polar plate of the first capacitor and a middle polar plate of the third capacitor; the third metal layer is used as an upper polar plate of the third capacitor; the first dielectric layer is used as an interlayer dielectric of the first capacitor, the first dielectric layer is used as an interlayer dielectric between a lower pole plate and an intermediate pole plate of the third capacitor, and the second dielectric layer is used as an interlayer dielectric between the intermediate pole plate and an upper pole plate of the third capacitor.
9. The capacitive structure of claim 1, wherein: the capacitor structure comprises a second capacitor and a third capacitor which are arranged on the semiconductor substrate; the first metal layer is respectively used as a lower polar plate of the second capacitor and a lower polar plate of the third capacitor; the second metal layer is used as an intermediate polar plate of the third capacitor; the third metal layer is respectively used as upper polar plates of the second capacitor and the third capacitor; the first dielectric layer and the second dielectric layer are used as interlayer dielectrics of the second capacitor; the first dielectric layer is used as an interlayer dielectric between the lower electrode plate and the middle electrode plate of the third capacitor, and the second dielectric layer is used as an interlayer dielectric between the middle electrode plate and the upper electrode plate of the third capacitor.
10. The capacitive structure of claim 1, wherein: the capacitor structure comprises a first capacitor, a second capacitor and a third capacitor which are arranged on the semiconductor substrate; the first metal layer is respectively used as a lower polar plate of the first capacitor, the second capacitor and the third capacitor; the second metal layer is used as an upper polar plate of the first capacitor and a middle polar plate of the third capacitor; the third metal layer is respectively used as upper polar plates of the second capacitor and the third capacitor; the first dielectric layer is used as an interlayer dielectric of the first capacitor, and the first dielectric layer and the second dielectric layer are used as interlayer dielectrics of the second capacitor; the first dielectric layer is used as an interlayer dielectric between the lower electrode plate and the middle electrode plate of the third capacitor, and the second dielectric layer is used as an interlayer dielectric between the middle electrode plate and the upper electrode plate of the third capacitor.
11. The manufacturing method of the capacitor structure is characterized by comprising the following steps of:
1) Forming a first metal layer on the first capacitor region and the second capacitor region of the semiconductor substrate;
2) Forming a first dielectric layer;
3) Forming a second metal layer on the first dielectric layer of the first capacitor region;
4) Forming a second dielectric layer;
5) And forming a third metal layer on the second dielectric layer of the second capacitor region.
12. The method of fabricating a capacitor structure of claim 11, further comprising the steps of:
6) Coating an insulating layer, and forming openings exposing the second metal layer and the third metal layer respectively through an etching process;
7) Forming a fourth metal layer, wherein the fourth metal layer is connected with the second metal layer and the third metal layer through the openings respectively;
the first metal layer is respectively used as a lower polar plate of the first capacitor and a lower polar plate of the second capacitor; the second metal layer is used as an upper polar plate of the first capacitor; the third metal layer is used as an upper polar plate of the second capacitor; the first dielectric layer is used as an interlayer dielectric of the first capacitor, and the first dielectric layer and the second dielectric layer are used as interlayer dielectrics of the second capacitor.
13. The manufacturing method of the capacitor structure is characterized by comprising the following steps of:
1) Forming a first metal layer on the first capacitor region and the third capacitor region of the semiconductor substrate;
2) Forming a first dielectric layer;
3) Forming second metal layers on the first dielectric layers of the first capacitor region and the third capacitor region respectively;
4) Forming a second dielectric layer;
5) And forming a third metal layer on the second dielectric layer of the third capacitor region.
14. The method of fabricating a capacitor structure of claim 13, further comprising the steps of:
6) Coating an insulating layer, and forming openings of the first metal layer, the second metal layer and the third metal layer of the third capacitor by etching;
7) Forming a fourth metal layer, wherein the fourth metal layer is respectively connected with the first metal layer, the second metal layer and the third metal layer through openings, and the first metal layer and the third metal layer of the third capacitor are connected through the fourth metal layer;
the first metal layer is respectively used as a lower polar plate of the first capacitor and a lower polar plate of the third capacitor; the second metal layer is used as an upper polar plate of the first capacitor and a middle polar plate of the third capacitor; the third metal layer is used as an upper polar plate of the third capacitor; the first dielectric layer is used as an interlayer dielectric of the first capacitor, the first dielectric layer is used as an interlayer dielectric between a lower pole plate and an intermediate pole plate of the third capacitor, and the second dielectric layer is used as an interlayer dielectric between the intermediate pole plate and an upper pole plate of the third capacitor.
15. The manufacturing method of the capacitor structure is characterized by comprising the following steps of:
1) Forming a first metal layer on the second capacitor region and the third capacitor region of the semiconductor substrate;
2) Forming a first dielectric layer;
3) Forming a second metal layer on the first dielectric layer of the third capacitor region;
4) Forming a second dielectric layer;
5) And forming a third metal layer on the second dielectric layer of the second capacitor region and the third capacitor region.
16. The method of fabricating a capacitor structure of claim 15, further comprising the steps of:
6) Coating an insulating layer, and forming third metal layers respectively exposing the second capacitor through an etching process, wherein openings of the first metal layer, the second metal layer and the third metal layer of the third capacitor are formed;
7) Forming a fourth metal layer, wherein the fourth metal layer is respectively connected with the first metal layer, the second metal layer and the third metal layer through openings, and the first metal layer and the third metal layer of the third capacitor are connected through the fourth metal layer;
the first metal layer is respectively used as a lower polar plate of the second capacitor and a lower polar plate of the third capacitor; the second metal layer is used as an intermediate polar plate of the third capacitor; the third metal layer is respectively used as upper polar plates of the second capacitor and the third capacitor; the first dielectric layer and the second dielectric layer are used as interlayer dielectrics of the second capacitor; the first dielectric layer is used as an interlayer dielectric between the lower electrode plate and the middle electrode plate of the third capacitor, and the second dielectric layer is used as an interlayer dielectric between the middle electrode plate and the upper electrode plate of the third capacitor.
17. The manufacturing method of the capacitor structure is characterized by comprising the following steps of:
1) Forming a first metal layer on the first capacitance region, the second capacitance region and the third capacitance region of the semiconductor substrate;
2) Forming a first dielectric layer;
3) Forming a second metal layer on the first dielectric layer of the first capacitor region and the third capacitor region;
4) Forming a second dielectric layer;
5) And forming a third metal layer on the second dielectric layer of the second capacitor region and the third capacitor region.
18. The method of fabricating a capacitor structure of claim 17, further comprising the steps of:
6) Coating an insulating layer, and forming a second metal layer of the first capacitor and a third metal layer of the second capacitor respectively through an etching process, wherein openings of the first metal layer, the second metal layer and the third metal layer of the third capacitor are formed;
7) Forming a fourth metal layer through photoetching and a metal deposition process, wherein the fourth metal layer is respectively connected with the first metal layer, the second metal layer and the third metal layer through openings, and the first metal layer and the third metal layer of the third capacitor are connected through the fourth metal layer;
the first metal layer is respectively used as a lower polar plate of the first capacitor, the second capacitor and the third capacitor; the second metal layer is used as an upper polar plate of the first capacitor and a middle polar plate of the third capacitor; the third metal layer is respectively used as upper polar plates of the second capacitor and the third capacitor; the first dielectric layer is used as an interlayer dielectric of the first capacitor, and the first dielectric layer and the second dielectric layer are used as interlayer dielectrics of the second capacitor; the first dielectric layer is used as an interlayer dielectric between the lower electrode plate and the middle electrode plate of the third capacitor, and the second dielectric layer is used as an interlayer dielectric between the middle electrode plate and the upper electrode plate of the third capacitor.
19. A semiconductor chip, characterized in that: a capacitor structure comprising any one of claims 1 to 10.
20. The semiconductor chip of claim 19, wherein: the semiconductor chip comprises an HBT transistor and/or an HEMT device.
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