WO2023212898A1 - 微发光二极管和显示面板 - Google Patents

微发光二极管和显示面板 Download PDF

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WO2023212898A1
WO2023212898A1 PCT/CN2022/091112 CN2022091112W WO2023212898A1 WO 2023212898 A1 WO2023212898 A1 WO 2023212898A1 CN 2022091112 W CN2022091112 W CN 2022091112W WO 2023212898 A1 WO2023212898 A1 WO 2023212898A1
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layer
sub
micro
emitting diode
diode according
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PCT/CN2022/091112
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English (en)
French (fr)
Inventor
王彦钦
陈劲华
郭桓邵
彭钰仁
黄少华
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泉州三安半导体科技有限公司
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Priority to PCT/CN2022/091112 priority Critical patent/WO2023212898A1/zh
Publication of WO2023212898A1 publication Critical patent/WO2023212898A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table

Definitions

  • the invention relates to the field of semiconductor manufacturing, and in particular to micro-luminescent diodes, preparation methods and display panels.
  • Micro-LEDs have the advantages of self-illumination, high efficiency, low power consumption, high brightness, high stability, ultra-high resolution and color saturation, fast response speed, long life, etc., and have been used in displays and optical communications.
  • indoor positioning, biological and medical fields have obtained relevant applications, and are expected to be further expanded to wearable/implantable devices, enhanced display/virtual reality, vehicle-mounted display, ultra-large display and optical communication/optical interconnection, medical detection, intelligence Automotive lights, space imaging and other fields have clear and promising market prospects.
  • micro LEDs are less than 100 ⁇ m. There are defects on the side walls of micro LEDs, which will lead to the generation of non-radiative recombination, thereby affecting the luminous efficiency of micro LEDs. As the size of micro-LEDs becomes smaller and smaller, the phenomenon of non-radiative recombination caused by defects in the side walls of the mesa structure will become more and more serious.
  • the present invention proposes a micro-light-emitting diode, which includes: a semiconductor epitaxial stack having an opposite first surface and a second surface, including a sequentially stacked third surface from the first surface to the second surface.
  • a covering layer, an active layer and a second covering layer characterized in that: the first covering layer includes a superlattice layer formed by alternately stacking first sub-layers and second sub-layers; the first sub-layer is composed of It is composed of combined Al x1 Ga 1-x1 InP material; the second sub-layer is composed of Al x2 Ga 1-x2 InP material, where 0 ⁇ x1 ⁇ x2 ⁇ 1.
  • the range of the Al component x1 of the first sub-layer is 0.4 ⁇ x1 ⁇ 1; the range of the content x2 of the Al component of the second sub-layer is 0.6 ⁇ x1 ⁇ 1.
  • the thickness of the first sub-layer ranges from 1.5 to 15 nm; the thickness of the second sub-layer ranges from 4 to 15 nm.
  • the number of periods of the superlattice structure is more than 10 pairs.
  • the distance from the upper surface of the first covering layer to the upper surface of the active layer is D1, and D1 is less than or equal to 150 nm.
  • the micro-light emitting diode further includes a first current spreading layer and a second current spreading layer, the first covering layer is located on the first current spreading layer, and the second current spreading layer located on the second covering layer.
  • the first covering layer includes a first part and a second part, the first part being a superlattice layer formed by alternately stacking the first sub-layer and the second sub-layer; the second part Partly composed of AlInP material.
  • the first portion of the first covering layer is closer to the active layer than the second portion.
  • the thickness of the first part of the first covering layer ranges from 35 to 150 nm, and the thickness of the second part ranges from 150 to 350 nm.
  • the second covering layer includes a superlattice layer formed by alternately stacking third sub-layers and fourth sub-layers, and the first sub-layer is composed of a combined Al z1 Ga 1-z1 It is composed of InP material; the second sub-layer is composed of Al z2 Ga 1-z2 InP material, where 0 ⁇ x1 ⁇ x2 ⁇ 1.
  • the second covering layer includes a first part and a second part, the first part is a superlattice layer formed by alternately stacking third sub-layers and fourth sub-layers; the second part is composed of AlInP material composition.
  • the first part of the second covering layer is closer to the active layer than the second part.
  • the micro-light emitting diode further includes a first spacer layer and a second spacer layer, the first spacer layer is located between the first covering layer and the active layer, and the second spacer layer A spacer layer is located between the active layer and the second cover layer.
  • the thickness of the first spacer layer is less than 150 nm, and the doping concentration is less than 1E17/cm 3 .
  • the thickness of the second spacer layer is less than 150 nm, and the doping concentration is lower than 1E17/cm 3 .
  • the present invention also proposes a micro-light emitting diode, which includes: a semiconductor epitaxial stack having opposite first surfaces and second surfaces, including sequentially stacked first covering layers, active layers, and a second surface from the first surface to the second surface.
  • the second covering layer characterized in that: the second covering layer includes a superlattice layer formed by alternately stacking third sub-layers and fourth sub-layers; the third sub-layer is composed of combined Al z1 Ga 1-z1 It is composed of InP material; the fourth sub-layer is composed of Al z2 Ga 1-z2 InP material, where 0 ⁇ z1 ⁇ z2 ⁇ 1.
  • the range of the Al component z1 of the third sub-layer is 0.4 ⁇ z1 ⁇ 1; the range of the content z2 of the Al component of the fourth sub-layer is 0.6 ⁇ z2. ⁇ 1.
  • the active layer radiates light with a wavelength of 550 to 950 nm.
  • the light emitting diode has a width or length or height from 2 ⁇ m to 5 ⁇ m, 5 ⁇ m to 10 ⁇ m, 10 ⁇ m to 20 ⁇ m, 20 ⁇ m to 50 ⁇ m, or from 50 ⁇ m to 100 ⁇ m.
  • the present invention also provides a display panel, which includes the light-emitting diode described in any one of the preceding items.
  • the present invention proposes a micro-luminescent diode, which has the following beneficial effects:
  • the first cladding layer adopts a superlattice structure, which can better match the lattice of the first spacer layer, the barrier layer and the well layer in the active layer, effectively releasing stress, thereby improving the performance of the near active area.
  • the quality of epitaxial crystals reduces the crystal defects of semiconductor epitaxial stacks and improves the effective recombination of carriers;
  • Designing the N-type cladding layer as an Al z1 Ga 1-z1 InP/Al z2 Ga 1-z2 InP superlattice structure can increase the current expansion, especially under small current conditions, to increase electron mobility. , thereby improving the external quantum efficiency of micro-light-emitting diodes under low current conditions.
  • Figure 1 is a schematic cross-sectional view of the micro-light emitting diode mentioned in Embodiment 1 of the present invention.
  • Figure 2 is a comparison of test data of photoelectric conversion efficiency-current density of the micro-light emitting diode in Embodiment 1 of the present invention and the traditional structure.
  • Figure 3 is a schematic cross-sectional view of the micro-luminescent element mentioned in Embodiment 1 of the present invention.
  • FIG. 4 is a schematic cross-sectional view of the micro-light emitting diode mentioned in Embodiment 2 of the present invention.
  • FIG. 5 is a schematic cross-sectional view of the micro-light emitting diode mentioned in Embodiment 3 of the present invention.
  • FIG. 6 is a schematic cross-sectional view of the micro-light emitting diode mentioned in Embodiment 4 of the present invention.
  • FIG. 7 to 13 are schematic diagrams of the process of manufacturing micro-light emitting diodes according to Embodiment 5 of the present invention.
  • Figure 14 is a schematic cross-sectional view of a micro-light emitting diode according to Embodiment 6 of the present invention.
  • Figure 15 is a schematic cross-sectional view of a micro-light emitting diode according to Embodiment 7 of the present invention.
  • Figure 16 is a schematic cross-sectional view of a micro-light emitting diode according to Embodiment 8 of the present invention.
  • FIG. 17 is a schematic cross-sectional view of a display panel according to Embodiment 9 of the present invention.
  • growth substrate 100; buffer layer: 101; etching stop layer: 102; first current spreading layer: 103; first covering layer: 104; first spacer layer: 105; active layer: 106; Second spacer layer: 107; second covering layer: 108; second current spreading layer: 109; ohmic contact layer: 110; substrate: 200; bonding layer: 201; first electrode: 203; ohmic contact portion of the first electrode : 203a; the ohmic contact part of the second electrode: 204a; the second electrode: 204; the pad electrode of the first electrode: 203b; the pad electrode of the second electrode: 204b; the first mesa: S1; the second mesa: S2 ;Insulating protective layer: 207; Horizontal part of the insulating protective layer: 2071; Sacrificial layer: 208; Base frame: 250; Bridge arm: 240; First mesa: S1; Second mesa: S2; First of the semiconductor epitaxial stack Surface: A1; second
  • illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner, so the illustrations only show the components related to the present invention and are not based on the number, shape and number of components during actual implementation. Dimension drawing, in actual implementation, the type, quantity and proportion of each component can be arbitrarily changed, and the component layout type may also be more complex.
  • This embodiment provides a micro-light-emitting diode, which can solve the technical problem of low luminous efficiency of micro-light-emitting diodes under small current density in the prior art.
  • the micro-luminescent diode refers to a micron-level light-emitting diode. Since the size of the micro-luminescent diode is small, its manufacturing process is very different from that of traditional light-emitting diodes.
  • the micro-luminescent diode in the present invention mainly refers to the size, including The length, width or height ranges from 2 ⁇ m or more to less than 5 ⁇ m, from 5 ⁇ m or more to less than 10 ⁇ m, from 10 ⁇ m or more to less than 20 ⁇ m, from 20 ⁇ m or more to less than 50 ⁇ m or from 50 ⁇ m or more to 100 ⁇ m or less.
  • the micro light-emitting diode can be widely used in display and other fields.
  • the micro-light emitting diode includes: a semiconductor epitaxial stack having opposite first surfaces A1 and second surfaces A2, including a first type semiconductor layer, a second type semiconductor layer and a second type semiconductor layer located on the first type semiconductor layer.
  • Semiconductor epitaxial stacks can be formed by physical vapor deposition (PVD), chemical vapor deposition (Chemical Vapor Deposition, CVD), epitaxial growth (Epitaxy Growth Technology) and Atomic Layer Deposition, ALD) or other methods are formed on the growth substrate 100.
  • Semiconductor epitaxial stacks are semiconductor materials that can provide conventional radiation such as ultraviolet, blue, green, yellow, red, infrared light, etc. Specifically, they can be 200 ⁇ 950nm materials, such as common nitrides, specifically gallium nitride.
  • gallium nitride-based epitaxial stacks are commonly doped with aluminum, indium and other elements, mainly providing radiation in the 200 ⁇ 550nm band; or common aluminum gallium indium phosphorus-based or aluminum gallium arsenic-based semiconductor epitaxial stacks, Mainly provides radiation in the 550 ⁇ 950nm band.
  • the first type semiconductor layer and the second type semiconductor layer may be n-type doped or p-type doped respectively to provide at least electrons or holes respectively.
  • the n-type semiconductor layer may be doped with an n-type dopant such as Si, Ge, or Sn
  • the p-type semiconductor layer may be doped with a p-type dopant such as Mg, Zn, Ca, Sr, or Ba.
  • the first type semiconductor layer is an n-type semiconductor
  • the second type semiconductor layer is a p-type semiconductor layer
  • the first type semiconductor layer is a p-type semiconductor layer
  • the second type semiconductor layer is an n-type semiconductor layer.
  • the first type semiconductor layer, the active layer, and the second conductivity type semiconductor layer may specifically be materials such as aluminum gallium indium nitride, gallium nitride, aluminum gallium nitride, aluminum indium phosphorus, aluminum gallium indium phosphorus, gallium arsenide, or aluminum gallium arsenide. Make and form.
  • the first type semiconductor layer is an n-type semiconductor layer
  • the second type semiconductor layer is a p-type semiconductor layer; in some optional embodiments, the first type semiconductor layer is a p-type semiconductor layer.
  • the second type semiconductor layer is an n-type semiconductor layer.
  • the first type semiconductor layer and the second type semiconductor layer respectively include a first covering layer 104 and a second covering layer 108 that provide electrons or holes for the active layer 106 .
  • the first type semiconductor layer and the second type semiconductor layer further include a first current spreading layer 103 and a second current spreading layer 109 .
  • the first type semiconductor layer includes a P-type current spreading layer 103 and a P-type covering layer 104; the P-type current spreading layer 103 plays the role of current spreading, and its spreading ability is related to the thickness.
  • the preferred material is Al y1 Ga 1-y1 InP, the thickness is 2500 ⁇ 5000nm, and the P-type doping concentration is 2E18 ⁇ 5E18/cm 3 .
  • Al y1 Ga 1-y1 InP, y1 ranges from 0.3 to 0.7, which can ensure the light transmittance of the P-type current expansion layer.
  • the P-type current spreading layer 103 is in ohmic contact with the first electrode 203 to form an electrical connection; the side of the P-type current spreading layer 103 away from the active layer 106 provides a light-emitting surface.
  • the first spacer layer 105 is located between the P-type cladding layer 104 and the active layer 106.
  • the preferred material is Al a1 Ga 1-a1 InP.
  • the thickness of the first spacer layer 105 is preferably less than 150 nm, and the Al component content a1 The range is 0.3 ⁇ 1; the doping concentration is lower than 1E17/cm 3 .
  • the first covering layer 104 is composed of a superlattice structure formed by alternate stacking of first sub-layers 104a and second sub-layers 104b, and the first sub-layer 104a is composed of a combined Al x1 Ga 1-x1 InP material;
  • the second sub-layer 104b is composed of Al x2 Ga 1-x2 InP material, where 0 ⁇ x1 ⁇ x2 ⁇ 1. In some optional embodiments, x2-x1 ⁇ 0.2 is preferred, and x2-x1 ⁇ 0.4 is more preferred.
  • the thickness of the first sub-layer 104a is 1.5 ⁇ 15nm, preferably 1.5 ⁇ 3.5nm, and the thickness of the second sub-layer 104b is 4 ⁇ 15nm, preferably 4 ⁇ 6nm.
  • the number of periods of the superlattice layer is 10 pairs or more, and more preferably 15 pairs or more.
  • the content x1 of the Al component of the first sub-layer 104a of the first covering layer 104 is in the range of 0.4 ⁇ x1 ⁇ 1; the range of the content x1 of the Al component of the second sub-layer 104b is The range of content x2 is 0.6 ⁇ x2 ⁇ 1.
  • the first sub-layer 104a is preferably Al x1 Ga 1-x1 InP, where 0.4 ⁇ x1 ⁇ 1; the second sub-layer is AlInP.
  • the first cladding layer 104 is designed to have an Al It has better lattice matching, improves the crystal quality of the active area, reduces crystal defects, and improves the effective recombination of carriers, thereby improving the luminous efficiency of the light-emitting diode.
  • the P-type cladding layer 104 is designed to have an Al x1 Ga 1-x1 InP/Al x2 Ga 1-x2 InP superlattice structure, where the Al x Ga 1-x InP can optimize the valence band edge of the P-type cladding layer. Thereby increasing the hole concentration of the P-type covering layer and improving the external quantum efficiency.
  • the distance from the upper surface of the first covering layer 104 to the first surface of the active layer 106 is D1, preferably D1 is less than or equal to 150 nm, which can ensure that the carriers provided by the first covering layer enter the active layer 106 quickly. Radiation recombination occurs in the active layer 106 with the carriers provided by the second covering layer, thereby improving the luminous efficiency of the micro-light emitting diode.
  • the active layer 106 provides a light radiation area for the recombination of electrons and holes. Different materials can be selected according to different emission wavelengths.
  • the active layer 106 can be a periodic structure of a single quantum well or a multi-quantum well. In this embodiment, the active layer 106 is a quantum well structure with n periods. Each quantum well structure includes a well layer and a barrier layer deposited in sequence, where the barrier layer has a larger band gap than the well layer. By adjusting the composition ratio of the semiconductor material in the active layer 106, it is desired to radiate light of a target wavelength.
  • the active layer 106 is a material layer that provides electroluminescent radiation, such as aluminum gallium indium phosphorus or aluminum gallium arsenic, more preferably aluminum gallium indium phosphorus, which is a single quantum well or a multi-quantum well.
  • the semiconductor epitaxial stack is composed of AlGaInP-based or GaAs-based materials, and the active layer radiates light with a wavelength of 550 to 950 nm.
  • the period number n of the quantum well structure in this embodiment is 2 to 100.
  • the well layer is composed of Al x3 Ga 1-x3 InP material;
  • the barrier layer is composed of A y Ga 1-y InP material, where 0 ⁇ x3 ⁇ y ⁇ 1.
  • the thickness of the well layer is 3 to 7 nm; the thickness of the barrier layer is 4 to 8 nm; the Al component content y of the barrier layer ranges from 0.3 to 0.85.
  • the second spacer layer 107 is located on the active layer 106.
  • the material of the second spacer layer 107 is preferably Al b1 Ga 1-b1 InP.
  • the thickness of the second spacer layer 107 is preferably less than 150 nm.
  • the Al component content b1 of the second spacer layer 107 ranges from 0.3 to 1; the doping concentration is lower than 1E17/cm 3 .
  • the second type semiconductor layer includes a second covering layer 108, a second current spreading layer 109 and a second ohmic contact layer 110; the second covering layer 108 functions to provide electrons to the active layer 106, which is preferred in this embodiment.
  • the second covering layer 108 is composed of a superlattice structure formed by alternate stacking of the third sub-layer 108a and the fourth sub-layer 108b.
  • the third sub-layer 108a is composed of a combined Al z1 Ga 1-z1 InP material;
  • Sublayer 108b is composed of Al z2 Ga 1-z2 InP material, where 0 ⁇ z1 ⁇ z2 ⁇ 1. In some optional embodiments, it is preferred that z2-z1 ⁇ 0.2, and more preferably z2-z1 ⁇ 0.4.
  • the thickness of the third sub-layer 108a is 1.5 ⁇ 15nm, preferably 1.5 ⁇ 3.5nm, and the thickness of the fourth sub-layer 108b is 4 ⁇ 15nm, preferably 4 ⁇ 6nm.
  • the number of periods of the superlattice layer is 10 pairs or more, and more preferably 15 pairs or more.
  • the range of the Al component z1 of the third sub-layer 108a is 0.4 ⁇ z1 ⁇ 1; the range of the content z2 of the Al component of the fourth sub-layer 108b is 0.6. ⁇ z1 ⁇ 1.
  • the third sub-layer 108a is preferably Al z1 Ga 1-z1 InP, where 0.4 ⁇ z1 ⁇ 1; the fourth sub-layer is AlInP.
  • the most common n-type doping is Si doping, and it is not ruled out that other elements can be equivalently substituted.
  • the second covering layer 108 is designed to have an Al z1 Ga 1-z1 InP/Al z2 Ga 1-z2 InP superlattice structure, which can improve the uniformity of current expansion, especially the mobility of electrons under small current conditions, thereby improving External quantum efficiency of microluminescent diodes under low current conditions.
  • the second current spreading layer 109 plays the role of current spreading, and its spreading ability is related to thickness. Therefore, in this embodiment, its thickness can be selected according to the specific device size, and the preferred thickness is controlled to be above 300 nm and below 1200 nm. In this embodiment, the thickness of the second current spreading layer 109 is preferably 300 to 800 nm. In this embodiment, the preferred material is GaP, and the n-type doping concentration is 6E17 ⁇ 2E18/cm 3 . The common n-type doping is silicon doping, and equivalent replacement doping by other elements is not excluded.
  • the second ohmic contact layer 110 forms ohmic contact with the second electrode 204.
  • the preferred material is GaP, and the doping concentration is 1E19/cm 3 , more preferably 5E19/cm 3 or more, to achieve better ohmic contact.
  • the thickness of the second ohmic contact layer 109 is preferably between 40 nm and 150 nm. In this embodiment, the thickness of the second ohmic contact layer 110 is preferably 60 nm.
  • the conductive metal in contact between the first electrode 203 and the first type semiconductor layer can be selected from gold, platinum, silver, etc., or a transparent conductive oxide, specifically ITO, ZnO, etc.; more preferably, the first electrode 203 can be It is a multi-layer material, such as an alloy material including at least one of gold germanium nickel, gold beryllium, gold germanium, gold zinc, etc. More preferably, the first electrode 203 can also include a reflective metal, such as gold or silver. Part of the light radiated from the active layer and penetrating the current spreading layer 104 of the first type semiconductor layer is reflected by the semiconductor epitaxial stack and emits light from the light exit side.
  • the second electrode 204 preferably uses a conductive metal such as gold. , platinum or silver, etc.; more preferably, the second electrode 206 may include a multi-layer material, including at least one alloy material including gold germanium nickel, gold beryllium, gold germanium, gold zinc, etc. More preferably, in order to improve the ohmic contact effect between the second electrode 206 and the n-type ohmic contact layer 225 side, at least one metal that can be diffused to the n-type ohmic contact layer 109 side can be included to improve the ohmic contact resistance. In order to promote diffusion Fusion temperatures above at least 300°C can be selected.
  • the diffusion metal is a metal that can directly contact one side of the n-type ohmic contact layer 109, such as gold, platinum or silver.
  • the micro-luminescent diode is provided with an insulating protective layer 207 (not shown in Figure 1) on the first mesa S1, the second mesa S2 and the side walls.
  • the insulating protective layer 207 is The single-layer or multi-layer structure is formed of at least one material of SiO 2 , SiN x , Al 2 O 3 , and Ti 3 O 5 .
  • the insulating protective layer 207 has a Bragg reflective layer structure.
  • the insulating protective layer 207 is formed by alternately stacking two materials: Ti 3 O 5 and SiO 2 .
  • the material of the insulating protective layer 207 can be SiNx or SiO 2 , and the thickness is more than 1 ⁇ m.
  • the first electrode 203 and the second electrode 204 are located on the opposite side of the light emitting side.
  • the first electrode 203 and the second electrode 204 can contact the external electrical connector through the opposite side of the light emitting side to form a flip chip.
  • the first electrode 203 and the second electrode 204 include ohmic contact portions 203a and 203a and pad electrodes 203b and 203b.
  • the pad electrodes 203b and 203b may be at least one layer of gold, aluminum, silver, nickel or tin. Or a combination thereof to realize the solidification of the first electrode 203 and the second electrode 204 .
  • the first electrode 203 and the second electrode 204 may have the same height or different heights, and the pad metal layers of the first electrode and the second electrode do not overlap in the thickness direction.
  • the first covering layer 104 is designed to have an Al
  • the barrier layer has better lattice matching, which can effectively release stress, improve the crystal quality of the active area, reduce crystal defects, and improve the effective recombination of carriers, thereby improving the luminous efficiency of the light-emitting diode.
  • the P-type cladding layer 104 is designed as an Al x1 Ga 1-x1 InP/Al x2 Ga 1-x2 InP superlattice structure, where the AlxGa1-xInP can optimize the valence band edge of the P-type cladding layer, thereby increasing the P-type coverage.
  • the hole concentration of the layer increases the external quantum efficiency.
  • the second covering layer 108 is designed to have an Al z1 Ga 1-z1 InP/Al z2 Ga 1-z2 InP superlattice structure, which can improve the uniformity of current expansion, especially the mobility of electrons under small current conditions, thereby improving Improve the external quantum efficiency of light-emitting diodes under low current conditions.
  • the chip horizontal size is 15x25 ⁇ m.
  • FIG. 3 is a schematic diagram of a micro-luminescent element formed using micro-luminescent diodes in this embodiment.
  • the micro-luminescent element also includes a base frame 250 that supports the micro-light-emitting diode.
  • the base frame 250 is located on the lower side of the micro-light-emitting diode for connection.
  • the micro-luminescent diode and the bridge arm 240 of the base frame 250; the base frame 250 includes a substrate 200 and a bonding layer 201.
  • the material of the bonding layer 201 is BCB glue, silica gel, UV glue or resin.
  • the material of the bridge arm 240 includes dielectric, metal or semiconductor material.
  • the horizontal part 2071 of the insulating protective layer 207 can be used as the bridge arm 240, spanning the bonding layer 201, connecting the micro-light emitting diode and the base. Rack 250.
  • the micro-luminescent diode is separated from the base frame 250 through printing stamp transfer, and the printing stamp material is PDMS, silica gel, pyrolytic glue or UV glue.
  • the printing stamp material is PDMS, silica gel, pyrolytic glue or UV glue.
  • the specific cases include chemical decomposition or physical decomposition, such as ultraviolet light decomposition, Etching removal or impact removal, etc.
  • the first covering layer 104 in this embodiment includes a first part 104-1 and a second part 104-2.
  • the first part 104-1 is a superlattice structure formed by alternately stacking first sub-layers 104a and second sub-layers 104b, and the second part is composed of AlInP material; the first part 104-1 is closer to the active layer than the second part 104-2 ;
  • the thickness of the first part of the first covering layer is 35 ⁇ 150nm, and the thickness of the second part is 150 ⁇ 350nm.
  • the second covering layer 108 includes a first part 108-1 and a second part 108-2.
  • the first part 108-1 of the second covering layer is a superlattice formed by alternately stacking the first sub-layers 108a and the second sub-layers 108b. structure, the second part is composed of AlInP material; the first part 108-1 is closer to the active layer than the second part 108-2; the thickness of the first part 108-1 of the second covering layer is 35 ⁇ 150nm, and the second part The thickness of 108-2 is 150 ⁇ 350nm.
  • the first cladding layer and the second cladding layer in this embodiment include a first part and a second part.
  • the first part is composed of a superlattice structure
  • the second part is composed of AlInP material, which can be connected with the spacer layer and the well in the active layer.
  • the lattice matching between the layer and the barrier layer is better, which can effectively release stress, improve the crystal quality of the active area, reduce crystal defects, and improve the effective recombination of carriers, thereby improving the luminous efficiency of the light-emitting diode.
  • the P-type cladding layer 104 is designed as an Al x1 Ga 1-x1 InP/Al x2 Ga 1-x2 InP superlattice structure, where the Al x Ga 1-x InP can optimize the valence band edge of the P-type cladding layer, thereby Increase the hole concentration of the P-type covering layer and improve the external quantum efficiency.
  • the second covering layer 108 is designed to have an Al z1 Ga 1-z1 InP/Al z2 Ga 1-z2 InP superlattice structure, which can improve the uniformity of current expansion, especially the mobility of electrons under small current conditions, thereby improving External quantum efficiency of microluminescent diodes under low current conditions.
  • the first covering layer and the second covering layer adopt a partial superlattice structure.
  • the invention is not limited to this embodiment.
  • the first covering layer adopts a partial superlattice structure
  • the second covering layer adopts a full superlattice structure; in some optional embodiments, the first covering layer adopts a full superlattice structure.
  • the second covering layer is a partial superlattice structure.
  • the first covering layer 104 in this embodiment is a supercrystal formed by alternate stacking of first sub-layers 104a and second sub-layers 104b.
  • the second covering layer is made of AlInP material.
  • the first covering layer adopts a superlattice structure, which can match the lattice of the well layer and barrier layer in the first spacer layer 105 and the active layer 106 Better, it can effectively release stress, improve the crystal quality of the active area, reduce crystal defects, and improve the effective recombination of carriers, thereby improving the luminous efficiency of the light-emitting diode.
  • the P-type cladding layer 104 is designed as an Al x1 Ga 1-x1 InP/Al x2 Ga 1-x2 InP superlattice structure, where the Al x Ga 1-x InP can optimize the valence band edge of the P-type cladding layer, thereby Increase the hole concentration of the P-type covering layer and improve the external quantum efficiency.
  • the second covering layer 108 in this embodiment is a supercrystal formed by alternate stacking of first sub-layers 108a and second sub-layers 108b.
  • the first covering layer is made of AlInP material
  • the second covering layer 108 in this embodiment adopts a superlattice structure, which can improve the uniformity of current expansion, especially the mobility of electrons under small current conditions, thereby improving the small External quantum efficiency of light-emitting diodes under current conditions.
  • FIG. 7 to 13 show schematic diagrams of the manufacturing process of the micro-light emitting diode according to Embodiment 1.
  • the manufacturing method of the micro-light emitting diode of this embodiment will be described in detail below with reference to the schematic diagrams.
  • an epitaxial structure which specifically includes the following steps: providing a growth substrate 100, growing a semiconductor epitaxial stack through an epitaxial process such as MOCVD epitaxy, and the semiconductor epitaxial stack includes sequentially stacking on the surface of the growth substrate 100
  • the buffer layer 101 and the etching stop layer 102 are used to remove the epitaxial growth substrate 100, and then grow a first type semiconductor layer including a p-type current spreading layer 103, a p-type cladding layer 104, a first spacer layer 105, an active Layer 106 , second spacer layer 107 , is a second type semiconductor layer including an n-type cladding layer 107 , an n-type current spreading layer 108 and an n-type ohmic contact layer 109 .
  • the growth substrate 100 uses a commonly used GaAs substrate, and the material of the buffer layer 101 is set according to the growth substrate 100.
  • the growth substrate 100 is not limited to GaAs, and other materials, such as GaP, can also be used. , InP, etc., the corresponding settings and materials of the buffer layer 101 thereon can be selected according to the specific growth substrate 100 .
  • An etching stop layer 102 is provided on the buffer layer 101, such as GaInP. In order to facilitate the subsequent removal of the subsequent growth substrate 100, it is better to set a thin etching stop layer 102, and its thickness is controlled within 500 nm, more preferably 200 nm. Within.
  • a portion of the semiconductor epitaxial stack is removed by dry etching to form a first mesa S1 and a second mesa S2.
  • the first mesa S1 is composed of the first type semiconductor layer exposed by the depression of the semiconductor epitaxial stack.
  • the second mesa S2 is composed of a second type semiconductor layer and forms a side wall located at the outer edge of the semiconductor epitaxial stack and between the first mesa S1 and the second mesa S2.
  • a first electrode 203 and a second electrode 204 are respectively formed on the first mesa S1 and the second mesa S2; wherein the first electrode 203 and the second electrode 204 include ohmic contact portions 203a and 204a.
  • the contact portion is covered with an insulating protective layer 207, and pad electrodes 203b and 204b are opened above the insulating protective layer 207 to contact the ohmic contact portions 203a and 204a respectively.
  • the material of the ohmic contact portions 203a and 204a can be, for example, Au/AuZn/Au.
  • the insulating protective layer 207 is preferably made of SiNx or SiO 2 and has a thickness of 1 ⁇ m or more. In other optional embodiments, the insulating protective layer 207 may adopt a Bragg reflective layer structure, formed by alternately stacking two materials with different refractive indexes.
  • a sacrificial layer 208 is covered on the surface of the micro-light emitting diode; preferably, the thickness of the sacrificial layer 208 covering the sidewall is more than 1 ⁇ m, and the material of the sacrificial layer 208 can be oxide, nitrogen compounds or materials that can be selectively removed relative to other layers.
  • bond glue such as BCB glue
  • sacrificial layer 208 of the micro-light emitting diode to form a bonding layer 201;
  • the wafer distributing micro-light emitting diodes is bonded to the substrate 200 .
  • the growth substrate 100 is peeled off, and the buffer layer 101 and the etching stop layer 102 are removed.
  • the first type semiconductor layer on the edge of the micro-light emitting diode is removed, and the etching stops on the insulating protective layer 207 to form independent core particles to facilitate the subsequent separation of the core particles, and obtain the micro-chip as shown in Figure 3 led.
  • the formed micro-light emitting diodes are separated from the substrate 210 by using transfer printing and transferred to the packaging substrate. (not shown in the picture)
  • the p-type current expansion layer 103 Compared with the micro-luminescent diode shown in Figure 1 in Embodiment 1, in order to further improve the efficiency of the light emitted from the active layer 106 emerging from the light exit surface, as shown in Figure 14, the p-type current expansion layer 103 The surface has a roughened structure composed of regular or irregular protrusions.
  • the first electrode 203 and the second electrode 204 are on different sides, and the micro-light emitting diode in this embodiment has a vertical structure.
  • the side of the p-type current spreading layer 103 away from the active layer 106 is the light-emitting surface.
  • the n-type ohmic contact layer 109 and the second electrode 204 can be covered with a reflective metal or reflective insulating dielectric layer (not shown in the figure). (shown), part of the light radiated from the active layer and penetrating the current spreading layer 103 of the first type semiconductor layer is reflected back to the semiconductor epitaxial stack, and the light is emitted from the light exit side.
  • the micro-luminescent diode is bonded to the substrate 200 through a bonding layer 201.
  • the bonding layer 201 can be BCB glue or PI.
  • the substrate 200 may be a sapphire substrate.
  • the micro-luminescent element in this embodiment can be transferred to the packaging substrate through laser lift-off or other methods. (not shown in the picture)
  • This embodiment provides a display panel 300. Please refer to FIG. 17.
  • the display panel 300 includes a plurality of micro light-emitting diodes arranged in an array as in any of the previous embodiments. In FIG. 17, a part of the micro light-emitting diodes is shown in an enlarged schematic manner. Diode 1.
  • the display panel 300 is a display panel corresponding to the display screen of a smartphone.
  • the display panel may also be a display panel of other types of electronic products, such as a display panel of a computer display screen, or a display panel of a smart wearable electronic product display screen.
  • the display panel 300 Since the display panel 300 has the micro light-emitting diodes (micro light-emitting diodes 1 ) of the foregoing embodiments, the display panel 300 has the advantages brought by the micro light-emitting diodes of the foregoing embodiments.

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Abstract

本发明公开微发光二极管和显示面板，所述微发光二极管包括半导体外延叠层，具有相对的第一表面和第二表面，自第一表面至第二表面方向包含依次堆叠的第一覆盖层、有源层和第二覆盖层；其特征在于：所述第一覆盖层包含由第一子层和第二子层交替堆叠形成的超晶格结构；所述第一子层由组合式Al x1Ga 1-x1InP材料组成；第二子层由Al x2Ga 1-x2InP材料组成，其中0＜x1＜x2≤1。本发明第一覆盖层和或第二覆盖层包含超晶格结构，可提升半导体外延叠层的晶体质量和微发光二极管的电流扩展的均匀性，从而提升微发光二极管在小电流密度下的发光效率。

Description

微发光二极管和显示面板 技术领域
本发明涉及半导体制造领域，具体涉及微发光二极管及制备方法和显示面板。
 背景技术
微型发光二极管（Micro-LED）具有自发光、高效率、低功耗、高亮度、高稳定性、超高分辨率与色彩饱和度、响应速度快、寿命长等优点，已经在显示、光通信、室内定位、生物和医疗领域获得了相关的应用，并有望进一步扩展到可穿戴/可植入器件、增强显示/虚拟现实、车载显示、超大型显示以及光通信/光互联、医疗探测、智能车灯、空间成像等多个领域，具有明确可观的市场前景。
微型LED的尺寸小于100μm，在微型LED的侧壁存在缺陷，会导致非辐射复合的产生，从而影响微型LED的发光效率。当微型LED的尺寸越来越小，其台面结构(Mesa)侧壁的缺陷造成非辐射复合的现象会越来越严重。
现有微型LED由于侧壁效应引起的非辐射复合，在小电流密度条件下发光效率低下，急需开发出一种提高小电流密度条件下的发光效率的微发光二极管。
 技术解决方案
为了提升微发光二极管的发光效率，本发明提出一种微发光二极管，包括：半导体外延叠层，具有相对的第一表面和第二表面，自第一表面至第二表面方向包含依次堆叠的第一覆盖层、有源层和第二覆盖层；其特征在于：所述第一覆盖层包含由第一子层和第二子层交替堆叠形成的超晶格层；所述第一子层由组合式Al x1Ga 1-x1InP材料组成；第二子层由Al x2Ga 1-x2InP材料组成，其中0＜x1＜x2≤1。
在一些可选的实施例中，x2-x1≥0.2。
在一些可选的实施例中，所述第一子层的Al组分的含量x1的范围为0.4≤x1＜1；所述第二子层的Al组分的含量x2的范围为0.6≤x1≤1。
在一些可选的实施例中，所述第一子层的厚度范围为1.5~15nm；第二子层的厚度范围为4~15nm。
在一些可选的实施例中，所述超晶格结构的周期数为10对以上。
在一些可选的实施例中，所述第一覆盖层的上表面至有源层的上表面的距离为D1，D1小于等于150nm。
在一些可选的实施例中，所述微发光二极管还包含第一电流扩展层和第二电流扩展层，所述第一覆盖层位于第一电流扩展层之上，所述第二电流扩展层位于所述第二覆盖层之上。
在一些可选的实施例中，所述第一覆盖层包括第一部分和第二部分，第一部分为所述第一子层和第二子层交替堆叠形成的超晶格层；所述第二部分由AlInP材料组成，。
在一些可选的实施例中，所述第一覆盖层的第一部分较第二部分靠近有源层。
在一些可选的实施例中，所述第一覆盖层的第一部分的厚度范围为35~150nm，第二部分的厚度范围为150~350nm。
在一些可选的实施例中，所述第二覆盖层包含由第三子层和第四子层交替堆叠形成的超晶格层，所述第一子层由组合式Al z1Ga 1-z1InP材料组成；第二子层由Al z2Ga 1-z2InP材料组成，其中0＜x1＜x2≤1。
在一些可选的实施例中，所述第二覆盖层包含第一部分和第二部分，所述第一部分为第三子层和第四子层交替堆叠形成的超晶格层；第二部分由AlInP材料组成。
在一些可选的实施例中，所述第二覆盖层的第一部分较第二部分靠近有源层。
在一些可选的实施例中，所述微发光二极管还包含第一间隔层和第二间隔层，所述第一间隔层位于所述第一覆盖层和有源层之间，所述第二间隔层位于所述有源层和第二覆盖层之间。
在一些可选的实施例中，所述第一间隔层的厚度小于150nm，所述掺杂浓度低于1E17/cm 3。
在一些可选的实施例中，所述第二间隔层的厚度小于150nm，所述掺杂浓度低于1E17/cm 3。
本发明还提出一种微发光二极管，包括：半导体外延叠层，具有相对的第一表面和第二表面，自第一表面至第二表面方向包含依次堆叠的第一覆盖层、有源层和第二覆盖层；其特征在于：所述第二覆盖层包含由第三子层和第四子层交替堆叠形成的超晶格层；所述第三子层由组合式Al z1Ga 1-z1InP材料组成；第四子层由Al z2Ga 1-z2InP材料组成，其中0＜z1＜z2≤1。
在一些可选的实施例中，z2-z1≥0.2。
在一些可选的实施例中，所述第三子层的Al组分的含量z1的范围为0.4≤z1＜1；所述第四子层的Al组分的含量z2的范围为0.6≤z2≤1。
在一些可选的实施例中，所述有源层辐射波长为550~950nm的光。
在一些可选的实施例中，所述发光二极管具有从2μm到5μm、5μm到10μm、10μm到20μm、20μm到50μm或从50μm到100μm的宽度或长度或高度。
本发明还提出一种显示面板，所述显示面板包含前述任一项所述的发光二极管。
 有益效果
本发明提出一种微发光二极管，具有以下的有益效果：
（1）第一覆盖层采用超晶格结构，可与第一间隔层、有源层中的势垒层和阱层的晶格匹配性更佳，有效释放应力，从而提高近有源区的外延长晶质量，减少半导体外延叠层的晶体缺陷，提高载流子的有效复合；
（2）将P型覆盖层设计为Al x1Ga 1-x1InP/Al x2Ga 1-x2InP超晶格的结构，其中的Al xGa 1-xInP可以优化P型覆盖层的价带边缘，从而增加P型覆盖层的空穴浓度，提高外量子效率；
（3）将N型覆盖层处设计为Al z1Ga 1-z1InP/Al z2Ga 1-z2InP超晶格的结构，可以通过提高电流扩展，尤其是小电流条件下可提高电子的迁移率，从而提高小电流条件下微发光二极管的外量子效率。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。 
虽然在下文中将结合一些示例性实施及使用方法来描述本发明，但本领域技术人员应当理解，并不旨在将本发明限制于这些实施例。反之，旨在覆盖包含在所附的权利要求书所定义的本发明的精神与范围内的所有替代品、修正及等效物。
 附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例一起用于解释本发明，并不构成对本发明的限制。此外，附图数据是描述概要，不是按比例绘制。
图1为本发明实施例1中所提到的微发光二极管的剖面示意图。
图2为本发明实施例1的微发光二极管的光电转换效率-电流密度的测试数据与传统结构的对比。
图3为本发明实施例1中所提到的微发光元件的剖面示意图。
图4为本发明实施例2中所提到的微发光二极管的剖面示意图。
图5为本发明实施例3中所提到的微发光二极管的剖面示意图。
图6为本发明实施例4中所提到的微发光二极管的剖面示意图。
图7~图13为本发明实施例5的制造微发光二极管的过程示意图。
图14为本发明实施例6的微发光二极管的剖面示意图。
图15为本发明实施例7的微发光二极管的剖面示意图。
图16为本发明实施例8的微发光二极管的剖面示意图。
图17为本发明实施例9的显示面板的剖面示意图。
附图标记：生长衬底：100；缓冲层：101；蚀刻截止层：102；第一电流扩展层：103；第一覆盖层：104；第一间隔层：105；有源层：106；第二间隔层：107；第二覆盖层：108；第二电流扩展层：109；欧姆接触层：110；基板：200；键合层：201；第一电极：203；第一电极的欧姆接触部分：203a；第二电极的欧姆接触部分：204a；第二电极：204；第一电极的焊盘电极：203b；第二电极的焊盘电极：204b；第一台面：S1；第二台面：S2；绝缘保护层：207；绝缘保护层的水平部分：2071；牺牲层：208；基架：250；桥臂：240；第一台面：S1；第二台面：S2；半导体外延叠层的第一表面：A1；半导体外延叠层的第二表面：A2。
 本发明的实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。
实施例 1
本实施例提供一种微发光二极管，可解决现有技术中小电流密度下微发光二极管的发光效率低的技术问题。所述微发光二极管指的是微米级的发光二极管，由于微发光二极管的尺寸较小，因此其制作工艺跟传统发光二极管具有很大的区别，在本发明中的微发光二极管主要指尺寸，包含长度、宽度或者高度的范围为从大于等于2μm到小于5μm，从大于等于5μm到小于10μm，从大于等于10μm到小于20μm，从大于等于20μm到小于50μm或从大于等于50μm到小于等于100μm。该微型发光二极管可以广泛运用于显示等领域。
如图1所示，所述微发光二极管包括：半导体外延叠层，具有相对的第一表面A1和第二表面A2，包含第一类型半导体层、第二类型半导体层和位于所述第一类型半导体层和第二类型半导体层之间的有源层106，其中第一类型半导体层提供第一表面；第一台面S1，由所述半导体外延叠层凹陷露出的第一类型半导体层构成，第二台面S2，由所述第二类型半导体层构成；第一电极203，形成于第一台面S1之上，与所述第一类型半导体层形成电连接；第二电极204，形成于第二台面S2之上，与所述第二类型半导体层形成电连接。
半导体外延叠层可以通过物理气相沉积(Physical Vapor Deposition，PVD)、化学气相沉积(Chemical Vapor Deposition，CVD)、外延生长(Epitaxy Growth Technology)和原子束沉积 (Atomic Layer Deposition，ALD)等方式形成在生长衬底100上。半导体外延叠层为能够提供常规的如紫外、蓝、绿、黄、红、红外光等辐射的半导体材料，具体的可以是200~950nm的材料，如常见的氮化物，具体的如氮化镓基半导体外延叠层，氮化镓基外延叠层常见有掺杂铝、铟等元素，主要提供200~550nm波段的辐射；或者常见的铝镓铟磷基或铝镓砷基半导体外延叠层，主要提供550~950nm波段的辐射。
所述第一类型半导体层和第二类型半导体层可分别通过n型掺杂或p型掺杂以实现至少分别提供电子或空穴。n型半导体层可以掺杂有诸如Si、Ge或者Sn的n型掺杂物，p型半导体层可以掺杂有诸如Mg、Zn、Ca、Sr或者Ba的p型掺杂物。当第一类型半导体层为n型半导体时，第二类型半导体层为p型半导体层；当第一类型半导体层为p型半导体层时，第二类型半导体层为n型半导体层。第一类型半导体层、有源层、第二导电型半导体层具体可以是铝镓铟氮、氮化镓、铝镓氮、铝铟磷、铝镓铟磷或砷化镓或铝镓砷等材料制作形成。在一些可选的实施例中，第一类型半导体层为n型半导体层，第二类型半导体层为p型半导体层；在一些可选的实施例中，第一类型半导体层为p型半导体层，第二类型半导体层为n型半导体层。
所述第一类型半导体层和第二类型半导体层分别包括为有源层106提供电子或空穴的第一覆盖层104和第二覆盖层108。为了提升电流扩展的均匀性，所述第一类型半导体层和第二类型半导层还包含第一电流扩展层103和第二电流扩展层109。为了防止第一覆盖层104和第二覆盖层108的掺杂物扩散进入有源层106，影响有源层106的晶体质量，优选在第一覆盖层104和有源层106之间存在第一间隔层105；在第二覆盖层108和有源层106之间存在第二间隔层107。
在本实施例中，第一类型半导体层包含P型电流扩展层103和P型覆盖层104；其中P型电流扩展层103起到电流扩展的作用，其扩展能力与厚度有关，本实施例中优选材料为Al y1Ga 1-y1InP，厚度为2500~5000nm，所述P型掺杂浓度为2E18 ~5E18/cm 3。Al y1Ga 1-y1InP中y1介于0.3~0.7，可保证P型电流扩展层的透光性。所述P型电流扩展103与第一电极203欧姆接触，形成电连接；所述P型电流扩展层103远离有源层106的一侧提供出光面。
所述第一间隔层105位于P型覆盖层104和有源层106之间，优选材料为Al a1Ga 1-a1InP，所述第一间隔层105的厚度优选小于150nm，Al组分含量a1的范围为0.3 ~ 1；掺杂浓度低于1E17/cm 3。
所述第一覆盖层104由第一子层104a和第二子层104b交替堆叠形成的超晶格结构组成，所述第一子层104a由组合式Al x1Ga 1-x1InP材料组成；第二子层104b由Al x2Ga 1-x2InP材料组成，其中0＜x1＜x2≤1。在一些可选的实施例中，优选x2-x1≥ 0.2，更优选x2-x1≥0.4。所述第一子层104a的厚度为1.5~15nm，优选厚度为1.5~3.5nm，第二子层104b的厚度为4~15nm，优选厚度为4~6nm。所述超晶格层的周期数为10对以上，更优选为15对以上。
在一些可选的实施例中，所述第一覆盖层104的第一子层104a的Al组分的含量x1的范围为0.4≤x1＜1；所述第二子层104b的Al组分的含量x2的范围为0.6≤x2≤1。在本实施例中，优选所述第一子层104a为Al x1Ga 1-x1InP，其中所述0.4≤x1＜1；所述第二子层为AlInP。
所述第一覆盖层104设计为Al x1Ga 1-x1InP/Al x2Ga1-x2InP超晶格的结构，可与第一间隔层105、有源层106中的阱层和势垒层的晶格匹配性更佳，提升有源区的晶体质量，减小晶体缺陷，提升载流子的有效复合，从而提升发光二极管的发光效率。同时将P型覆盖层104设计为Al x1Ga 1-x1InP/Al x2Ga 1-x2InP超晶格的结构，其中的Al xGa 1-xInP可以优化P型覆盖层的价带边缘，从而增加P型覆盖层的空穴浓度，提高外量子效率。
所述第一覆盖层104的上表面至有源层106的第一表面的距离为D1，优选D1小于等于150nm，可保证第一覆盖层提供的载流子较快进入有源层106中，在有源层106中与第二覆盖层提供的载流子发生辐射复合，从而提升微发光二极管的发光效率。
有源层106为电子和空穴复合提供光辐射区域，根据发光波长的不同可选择不同的材料，有源层106可以是单量子阱或多量子阱的周期性结构。本实施例中有源层106为n个周期的量子阱结构，每个量子阱结构包含依次沉积的阱层和势垒层，其中势垒层具有比阱层更大的带隙。通过调整有源层106中半导体材料的组成比，以期望辐射出目标波长的光。有源层106为提供电致发光辐射的材料层，如铝镓铟磷或铝镓砷，更优选的为铝镓铟磷，铝镓铟磷为单量子阱或者多量子阱。在本实施例中，优选半导体外延叠层为AlGaInP基或者GaAs基材料组成，所述有源层辐射波长为550~950nm的光线。
本实施例中所述量子阱结构的周期数n为2~100。所述阱层由Al x3Ga 1-x3InP材料组成；所述势垒层由Al yGa 1-yInP材料组成，其中0≤x3≤y≤1。所述阱层的厚度为 3~7nm；所述势垒层的厚度为4~8nm；所述垒层的Al组分含量y的范围为0.3~0.85。
所述第二间隔层107位于有源层106之上，所述第二间隔层107的材料优选为Al b1Ga 1-b1InP，所述第二间隔层107的厚度优选小于150nm，所述第二间隔层107的 Al组分含量b1的范围为0.3 ~ 1；掺杂浓度低于1E17/cm 3。
第二类型半导体层包含第二覆盖层108、第二电流扩展层109和第二欧姆接触层110；其中所述第二覆盖层108的作用为有源层106提供电子，本实施例中优选所述第二覆盖层108为第三子层108a和第四子层108b交替堆叠形成的超晶格结构组成，所述第三子层108a由组合式Al z1Ga 1-z1InP材料组成；第四子层108b由Al z2Ga 1-z2InP材料组成，其中0＜z1＜z2≤1。在一些可选的实施例中，优选z2-z1≥0.2，更优选z2-z1≥0.4。所述第三子层108a的厚度为1.5~15nm，优选厚度为1.5~3.5nm，第四子层108b的厚度为4~15nm，优选厚度为4~6nm。所述超晶格层的周期数为10对以上，更优选为15对以上。
在一些可选的实施例中，所述第三子层108a的Al组分的含量z1的范围为0.4≤z1＜1；所述第四子层108b的Al组分的含量z2的范围为0.6≤z1≤1。在本实施例中，优选所述第三子层108a为Al z1Ga 1-z1InP，其中所述0.4≤z1＜1；所述第四子层为 AlInP。n型掺杂常见的是Si掺杂，也不排除其他的元素等效替代的掺杂。
第二覆盖层108设计为Al z1Ga 1-z1InP/Al z2Ga 1-z2InP超晶格的结构，可以提高电流扩展的均匀性，尤其是小电流条件下提高电子的迁移率，从而提高小电流条件下的微发光二极管的外量子效率。
第二电流扩展层109起到电流扩展的作用，其扩展能力与厚度有关，因此在本实施例中可根据具体的器件尺寸选择其厚度，较佳厚度控制在300nm以上，1200nm以下。本实施例中，优选所述第二电流扩展层109的厚度为300~800nm。本实施例中优选材料为GaP，n型掺杂浓度为6E17~2E18/cm 3，n型掺杂常见的是硅掺杂，也不排除其他的元素等效替代的掺杂。
第二欧姆接触层110为与第二电极204形成欧姆接触，优选材料为GaP，掺杂浓度为1E19/cm 3，更优选为5E19/cm 3以上，以实现更好的欧姆接触。所示第二欧姆接触层109的厚度优选为40nm以上，150nm以下。本实施例中，优选所述第二欧姆接触层110的厚度为60nm。
第一电极203与第一类型半导体层接触的导电型金属可以选择自金、铂或银等，或者为透明导电氧化物，具体的可以为ITO，ZnO等；更优选的，第一电极203可为多层材料，如至少包括金锗镍、金铍、金锗、金锌等至少之一的合金材料，更优选的，第一电极203还可以包括一反射性金属，如金或者银，对自有源层辐射并穿透第一类型半导体层的电流扩展层104的部分光线反射会半导体外延叠层，并从出光侧出光。
所述第二电极204为了与第二类型半导体层的n型欧姆接触层109形成良好的欧姆接触，优选所述第二电极204与n型欧姆接触层109接触的材料可以为导电型金属如金、铂或银等；更优选的，第二电极206可以包括多层材料，其中至少包括金锗镍、金铍、金锗、金锌等至少之一的合金材料。更优选的，为了改善第二电极206与n型欧姆接触层225一侧的欧姆接触效果，可以至少包括一能够扩散至n型欧姆接触层109一侧的金属以改善欧姆接触电阻，为了促进扩散可以选择至少300℃以上的熔合。该扩散金属为可以直接接触n型欧姆接触层109一侧的金属，如金，铂或银等。
为了提高微发光二极管的可靠性，在所述微发光二极管的第一台面S1、第二台面S2和侧壁上具有绝缘保护层207（图1中未示出），所述绝缘保护层207为单层或者多层结构，由SiO 2，SiN x，Al 2O 3，Ti 3O 5的至少一种材料形成。在一些可选的实施例中，所述绝缘保护层207为布拉格反射层结构，例如绝缘保护层207由Ti 3O 5和SiO 2两种材料交替堆叠形成。在本实施例中，所述绝缘保护层207的材料可以采用SiNx或者SiO 2，厚度为1μm以上。
本实施例中，所述第一电极203和第二电极204位于出光侧的相反侧，第一电极203和第二电极204可以通过出光侧的相反侧与外部电连接件进行接触，形成倒装的结构。因此所述的第一电极203和第二电极204包括欧姆接触部分203a和203a以及焊盘电极203b和203b，焊盘电极203b和203b可以是如金、铝、银、镍或锡等至少一层或其搭配，以实现第一电极203和第二电极204的固晶。第一电极203和第二电极204可以等高或不等高，在厚度方向上第一电极和第二电极的焊盘金属层不重叠。
本实施例中，所述第一覆盖层104设计为Al x1Ga 1-x1InP/Al x2Ga1-x2InP超晶格的结构，可与第一间隔层105、有源层106中的阱层和势垒层的晶格匹配性更佳，可有效释放应力，提升有源区的晶体质量，减小晶体缺陷，提升载流子的有效复合，从而提升发光二极管的发光效率。将P型覆盖层104设计为Al x1Ga 1-x1InP/Al x2Ga 1-x2InP超晶格的结构，其中的AlxGa1-xInP可以优化P型覆盖层的价带边缘，从而增加P型覆盖层的空穴浓度，提高外量子效率。同时第二覆盖层108设计为Al z1Ga 1-z1InP/Al z2Ga 1-z2InP超晶格的结构，可以提高电流扩展的均匀性，尤其是小电流条件下提高电子的迁移率，从而提高小电流条件下的发光二极管的外量子效率。如图2所示，利用本实施例中微发光二极管芯片，芯片水平尺寸为15x25μm，单颗芯片封装之后，进行光电转换效率（WPE）随电流（uA/ea）变化测试，在1uA/ea电流条件下，WPE从6.27%→6.86%，提升了9.4%。
图3为使用本实施例微发光二极管形成的微发光元件的示意图，所述微发光元件还包含支撑微发光二极管的基架250，所述基架250位于微发光二极管的下侧，用于连接微发光二极管和基架250的桥臂240；所述基架250包含基板200和键合层201，本实施例中所述键合层201的材料为BCB胶、硅胶、UV紫外胶或者树脂，桥臂240的材料包含介电质、金属或者半导体料，在一些实施例中，绝缘保护层207的水平部分2071可作为桥臂240，跨接在键合层201上，连接微发光二极管和基架250。
微发光二极管通过印刷印模转印与基架250分离，印刷印模材料为PDMS、硅胶、热解胶或UV紫外胶。在一些情况下，微发光二极管与基架之间具有牺牲层208，至少在特定情况下牺牲层208的移除效率高于微发光二极管，特定情况包括化学分解或物理分解，例如紫外光分解、蚀刻移除或者冲击移除等。
实施例 2
与实施例1中图1所示的微发光二极管相比，如图4所示，本实施例中的第一覆盖层104包括第一部分104-1和第二部分104-2，所述第一部分104-1由第一子层104a和第二子层104b交替堆叠形成的超晶格结构，第二部分由AlInP材料组成；所述第一部分104-1较第二部分104-2靠近有源层；所述第一覆盖层第一部分的厚度为35~150nm，第二部分的厚度为150~350nm。
第二覆盖层108包括第一部分108-1和第二部分108-2，所述第二覆盖层的第一部分108-1由第一子层108a和第二子层108b交替堆叠形成的超晶格结构，第二部分由AlInP材料组成；所述第一部分108-1较第二部分108-2靠近有源层；所述第二覆盖层第一部分108-1的厚度为35~150nm，第二部分108-2的厚度为150~350nm。
本实施例中的第一覆盖层和第二覆盖层包括第一部分和第二部分，第一部分由超晶格结构组成，第二部分由AlInP材料组成，可与间隔层、有源层中的阱层和势垒层的晶格匹配性更佳，可有效释放应力，提升有源区的晶体质量，减小晶体缺陷，提升载流子的有效复合，从而提升发光二极管的发光效率。将P型覆盖层104设计为Al x1Ga 1-x1InP/Al x2Ga 1-x2InP超晶格的结构，其中的Al xGa 1-xInP可以优化P型覆盖层的价带边缘，从而增加P型覆盖层的空穴浓度，提高外量子效率。第二覆盖层108设计为Al z1Ga 1-z1InP/Al z2Ga 1-z2InP超晶格的结构，可以提高电流扩展的均匀性，尤其是小电流条件下提高电子的迁移率，从而提高小电流条件下的微发光二极管的外量子效率。
本实施例中第一覆盖层和第二覆盖层采用部分超晶格结构，本发明并不限于此实施例。在一些可选的实施例中，第一覆盖层为部分超晶格结构，第二覆盖层采用全部超晶格结构；在一些可选的实施例中，第一覆盖层采用全部超晶格结构，第二覆盖层为部分超晶格结构。通过第一覆盖层和或第二覆盖层采用超晶格结构，可提升微发光二极管在小电流密度下的发光效率。
实施例 3
与实施例1中图1所示的微发光二极管相比，如图5所示，本实施例中的第一覆盖层104为第一子层104a和第二子层104b交替堆叠形成的超晶格结构，第二覆盖层为AlInP材料，本实施例中第一覆盖层采用超晶格结构，可与第一间隔层105、有源层106中的阱层和势垒层的晶格匹配性更佳，可有效释放应力，提升有源区的晶体质量，减小晶体缺陷，提升载流子的有效复合，从而提升发光二极管的发光效率。将P型覆盖层104设计为Al x1Ga 1-x1InP/Al x2Ga 1-x2InP超晶格的结构，其中的Al xGa 1-xInP可以优化P型覆盖层的价带边缘，从而增加P型覆盖层的空穴浓度，提高外量子效率。
实施例 4
与实施例1中图1所示的微发光二极管相比，如图6所示，本实施例中的第二覆盖层108为第一子层108a和第二子层108b交替堆叠形成的超晶格结构，第一覆盖层为AlInP材料，本实施例中的第二覆盖层108采用超晶格结构，可以提高电流扩展的均匀性，尤其是小电流条件下提高电子的迁移率，从而提高小电流条件下的发光二极管的外量子效率。
实施例 5
图7~图13显示了根据本实施例1中的微发光二极管的制造过程示意图，下面结合示意图对本实施例的微发光二极管的制造方法进行详细的描述。
首先，参见图7，提供一个外延结构，其具体包括以下步骤：提供一个生长衬底100，通过磊晶工艺如MOCVD外延生长半导体外延叠层，半导体外延叠层包括依次层叠在生长衬底100表面的缓冲层101以及蚀刻截止层102，用于移除外延生长衬底100，然后生长包括p型电流扩展层103，p型覆盖层104的第一类型半导体层，第一间隔层105，有源层106，第二间隔层107，包括n型覆盖层107、n型电流扩展层108和n型欧姆接触层109的第二类型半导体层。
本实施例生长衬底100采用常用的GaAs衬底，并根据生长衬底100设置缓冲层101的材料，应当注意的是，生长衬底100并不局限于GaAs，也可采用其他材料，例如GaP、InP等，对应的其上的缓冲层101的设置及材料可根据具体的生长衬底100进行选取。在缓冲层101上设置蚀刻截止层102，例如GaInP，为了便于后续生长衬底100的后续移除，较佳的设置较薄的蚀刻截止层102，其厚度控制在500nm以内，更优选的为200nm以内。
然后，参见图8，通过干法蚀刻方式移除部分的半导体外延叠层形成第一台面S1和第二台面S2，第一台面S1，由半导体外延叠层凹陷露出的第一类型半导体层构成，第二台面S2，由第二类型半导体层构成；形成侧壁，位于半导体外延叠层外边缘，位于第一台面S1和第二台面S2之间。
接着，参见图9，分别在第一台面S1和第二台面S2上分别制作第一电极203和第二电极204；其中第一电极203和第二电极204包括欧姆接触部分203a和204a，在欧姆接触部分上覆盖绝缘保护层207，并在绝缘保护层207上方开口形成焊盘电极203b和204b分别与欧姆接触部分203a和204a接触。所述欧姆接触部分203a和204a的材料可以例如Au/AuZn/Au，在本步骤中可对欧姆接触部分203a和204a进行熔合，使其与半导体外延叠层构形成良好的欧姆接触。所述绝缘保护层207优选采用SiNx或者SiO 2，厚度为1μm以上。在其它可选的实施例中， 所述绝缘保护层207可采用布拉格反射层结构，由两种不同折射率的材料交替堆叠形成。
接着，参见图10，在所述微发光二极管的表面上覆盖牺牲层208；较佳地，覆盖在侧壁上的牺牲层208的厚度为1μm以上，牺牲层208的材料可为氧化物、氮化物或者可选择性地相对于其他层被移除的材料。
接着，参见图11，在所述微发光二极管的牺牲层208上键合胶，如BCB胶，形成键合层201；
接着，参见图12，将分布微发光二极管的晶圆键合到基板200上。
接着，参见图13，剥离生长衬底100，移除缓冲层101和蚀刻截止层102。
接着，通过掩膜和蚀刻，移除微发光二极管边缘的第一类型半导体层，蚀刻停在绝缘保护层207上，形成独立芯粒，便于后续芯粒的分离，得到如图3所示的微型发光二极管。
最后，所述形成的微发光二极管通利用转印压印从基板210分离并转印至封装基板上。（图中未示出）
实施例 6
与实施例1中图1所示的微发光二极管相比，为了进一步提升从有源层106辐射出的光线从出光面中出射的效率，如图14所示，所述p型电流扩展层103的表面具有粗化结构，所述粗化结构由规则或者不规则的凸起组成。
实施例 7
与实施例1中图1所示的微发光二极管相比，如图15所示，所述第一电极203和第二电极204不同侧，本实施例中所述微发光二极管为垂直结构。所述p型电流扩展层103远离有源层106的一侧为出光面，所述n型欧姆接触层109和第二电极204之间可覆盖反射性金属或反射性绝缘介质层（图中未示出），对自有源层辐射并穿透第一类型半导体层的电流扩展层103的部分光线反射回半导体外延叠层，并从出光侧出光。
实施例 8
与实施例1中图4所述的微发光元件相比，如图16所示，所述微发光二极管通过键合层201键合在基板上200上，键合层201可为BCB胶或者PI，基板200可为蓝宝石衬底。本实施例中的微发光元件可通过激光剥离等方式转移到封装基板上。（图中未示出）
实施例 9
本实施例提供一种显示面板300，请参考图17，显示面板300包括如前述任意实施例的多个阵列排布的微型发光二极管，在图17中用放大显示的示意方式显示了一部分微型发光二极管1。
本实施例中，显示面板300为智能手机的显示屏对应的显示面板。其它实施例中，显示面板也可以是其它各类电子产品的显示面板，如电脑显示屏的显示面板，或者智能穿戴电子产品显示屏的显示面板等。
由于具有前述各实施例的微型发光二极管（微型发光二极管1），显示面板300具有前述各实施例微型发光二极管带来的优点。
需要说明的是，以上实施方式仅用于说明本发明，而并非用于限定本发明，本领域的技术人员，在不脱离本发明的精神和范围的情况下，可以对本发明做出各种修饰和变动，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应视权利要求书范围限定。

Claims (22)

  1. 微发光二极管，包括：
    半导体外延叠层，具有相对的第一表面和第二表面，自第一表面至第二表面方向包含依次堆叠的第一覆盖层、有源层和第二覆盖层；
    其特征在于：所述第一覆盖层包含由第一子层和第二子层交替堆叠形成的超晶格层；所述第一子层由组合式Al x1Ga 1-x1InP材料组成；第二子层由Al x2Ga 1-x2InP材料组成，其中0＜x1＜x2≤1。
  2. 根据权利要求1所述的微发光二极管，其特征在于：x2-x1≥0.2。
  3. 根据权利要求2所述的发光二极管，其特征在于：所述第一子层的Al组分的含量x1的范围为0.4≤x1＜1；所述第二子层的Al组分的含量x2的范围为0.6≤x2≤1。
  4. 根据权利要求1所述的微发光二极管，其特征在于：所述第一子层的厚度范围为1.5~15nm；第二子层的厚度范围为4~15nm。
  5. 根据权利要求1所述的微发光二极管，其特征在于：所述超晶格结构的周期数为10对以上。
  6. 根据权利要求1所述的微发光二极管，其特征在于：所述第一覆盖层的上表面至有源层的上表面的距离为D1，D1小于等于150nm。
  7. 根据权利要求1所述的微发光二极管，其特征在于：所述微发光二极管还包含第一电流扩展层和第二电流扩展层，所述第一覆盖层位于第一电流扩展层之上，所述第二电流扩展层位于所述第二覆盖层之上。
  8. 根据权利要求1所述的微发光二极管，其特征在于：所述第一覆盖层包括第一部分和第二部分，第一部分为所述第一子层和第二子层交替堆叠形成的超晶格层；所述第二部分由AlInP材料组成。
  9. 根据权利要求8所述的微发光二极管，其特征在于：所述第一覆盖层的第一部分较第二部分靠近有源层。
  10. 根据权利要求8所述的微发光二极管，其特征在于：所述第一覆盖层的第一部分的厚度范围为35~150nm，第二部分的厚度范围为150~350nm。
  11. 根据权利要求1所述的微发光二极管，其特征在于：所述第二覆盖层包含由第三子层和第四子层交替堆叠形成的超晶格层，所述第三子层由组合式Al z1Ga 1-z1InP材料组成；第四子层由Al z2Ga 1-z2InP材料组成，其中0＜x1＜x2≤1。
  12. 根据权利要求11所述的微发光二极管，其特征在于：所述第二覆盖层包含第一部分和第二部分，第一部分为所述第三子层和第四子层交替堆叠形成的超晶格层；所述第二部分由AlInP材料组成。
  13. 根据权利要求12所述的微发光二极管，其特征在于：所述第二覆盖层的第一部分较第二部分靠近有源层。
  14. 根据权利要求1所述的微发光二极管，其特征在于：还包含第一间隔层和第二间隔层，所述第一间隔层位于所述第一覆盖层和有源层之间，所述第二间隔层位于所述有源层和第二覆盖层之间。
  15. 根据权利要求14所述的微发光二极管，其特征在于：所述第一间隔层的厚度小于150nm，所述掺杂浓度低于1E17/cm 3。
  16. 根据权利要求14所述的微发光二极管，其特征在于：所述第二间隔层的厚度小于150nm，所述掺杂浓度低于1E17/cm 3。
  17. 微发光二极管，包括：
    半导体外延叠层，具有相对的第一表面和第二表面，自第一表面至第二表面方向包含依次堆叠的第一覆盖层、有源层和第二覆盖层；
    其特征在于：第二覆盖层包含由第三子层和第四子层交替堆叠形成的超晶格层；所述第三子层由组合式Al z1Ga 1-z1InP材料组成；第四子层由Al z2Ga 1-z2InP材料组成，其中0＜z1＜z2≤1。
  18. 根据权利要求17所述的微发光二极管，其特征在于：z2-z1≥0.2。
  19. 根据权利要求17所述的微发光二极管，其特征在于：所述第三子层的Al组分的含量z1的范围为0.4≤z1＜1；所述第四子层的Al组分的含量z2的范围为0.6≤z2≤1。
  20. 根据权利要求1或17所述的微发光二极管，其特征在于：所述有源层辐射波长为550~950nm的光。
  21. 根据权利要求1或17所述的微发光二极管，其特征在于：所述发光二极管具有从2μm到5μm、5μm到10μm、10μm到20μm、20μm到50μm或从50μm到100μm的宽度或长度或高度。
  22. 一种显示面板，其特征在于：包含权利要求1~21中任一项所述的发光二极管。
PCT/CN2022/091112 2022-05-06 2022-05-06 微发光二极管和显示面板 WO2023212898A1 (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101887934A (zh) * 2009-05-13 2010-11-17 索尼公司 发光二极管及其制造方法
CN102468387A (zh) * 2010-11-18 2012-05-23 昭和电工株式会社 发光二极管
CN113871520A (zh) * 2021-09-15 2021-12-31 天津三安光电有限公司 一种半导体发光元件及制作方法
CN114342094A (zh) * 2021-11-22 2022-04-12 厦门市三安光电科技有限公司 发光二极管及制备方法和显示面板
CN114388670A (zh) * 2021-12-27 2022-04-22 泉州三安半导体科技有限公司 一种不可见光发光二极管

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101887934A (zh) * 2009-05-13 2010-11-17 索尼公司 发光二极管及其制造方法
CN102468387A (zh) * 2010-11-18 2012-05-23 昭和电工株式会社 发光二极管
CN113871520A (zh) * 2021-09-15 2021-12-31 天津三安光电有限公司 一种半导体发光元件及制作方法
CN114342094A (zh) * 2021-11-22 2022-04-12 厦门市三安光电科技有限公司 发光二极管及制备方法和显示面板
CN114388670A (zh) * 2021-12-27 2022-04-22 泉州三安半导体科技有限公司 一种不可见光发光二极管

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