WO2023207632A1 - 基于gpu并行计算的卫星导航系统码片形状相关器和方法 - Google Patents

基于gpu并行计算的卫星导航系统码片形状相关器和方法 Download PDF

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WO2023207632A1
WO2023207632A1 PCT/CN2023/088342 CN2023088342W WO2023207632A1 WO 2023207632 A1 WO2023207632 A1 WO 2023207632A1 CN 2023088342 W CN2023088342 W CN 2023088342W WO 2023207632 A1 WO2023207632 A1 WO 2023207632A1
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signal
chip
random noise
noise code
pseudo
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PCT/CN2023/088342
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French (fr)
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崔晓伟
王传瑞
刘刚
陆明泉
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清华大学
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
    • G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
    • G01S19/13—Receivers
    • G01S19/35—Constructional details or hardware or software details of the signal processing chain
    • G01S19/37—Hardware or software details of the signal processing chain

Definitions

  • the present application relates to the field of radio navigation software receivers, and in particular to a real-time chip shape correlator and method for a satellite navigation system based on GPU parallel computing.
  • the main signal processing processes of the Global Navigation Satellite System (GNSS, Global Navigation Satellite System) radio software (SDR, software defined radio) receiver are all implemented through the software processing module. Compared with the hardware receiver, it is easier to debug, upgrade and modify, and has Better configurability, therefore playing a very important role in various application fields of GNSS.
  • the related operations include a large number of multiplication and accumulation operations, and the heavy computational burden makes it difficult to guarantee the real-time performance of the processor (CPU)-based SDR receiver.
  • Parallel computing based on graphics processing unit (GPU) can greatly accelerate the relevant calculations in the SDR receiver to meet real-time requirements.
  • Standard correlators usually only output 3-5 correlation values for signal tracking, but some multipath suppression and signal quality monitoring algorithms require more correlation values to output correlation peaks.
  • the standard correlator requires a complete correlation operation for each additional correlation value calculated. It is difficult for the standard correlator of the SDR receiver to calculate multiple correlation values in real time.
  • the chip shape correlator can utilize repeated calculations between multi-path correlation values to reduce the calculation amount of multi-path correlation values.
  • the chip shape The correlator can also measure chip shape for use in multipath suppression algorithms and signal quality monitoring algorithms based on chip-domain observations.
  • the SDR receiver chip shape correlator places higher requirements on memory allocation and access.
  • this application provides a real-time chip shape correlator system and method for a GNSS SDR receiver based on GPU parallel computing.
  • a real-time chip shape correlator based on GPU parallel computing including: a mask generation unit configured to generate a corresponding mask signal according to the chip edge of the real-time local pseudo-random noise code ; and a signal compression unit configured to: compress the product of the mask signal and the input signal using an instant local pseudo-random noise code to generate a compressed signal, and perform calculations on the compressed signal to generate a code for measuring the input signal patch-shaped data; and/or compress the input signal according to the immediate local pseudo-random noise code, the leading pseudo-random noise code, and the lagging pseudo-random noise code to generate a compressed signal, and calculate the compressed signal to generate Measure the data of the correlation peak of the co-correlation between the input signal and the local pseudo-random noise code; wherein the leading pseudo-random noise code and the lagging pseudo-random noise code lead and lag behind the immediate local pseudo-random noise code by a predetermined number of chips respectively.
  • the predetermined number of chips may include 1 chip.
  • the compressed signal is one chip in size and is divided into a grid of chips.
  • the signal compression unit is further configured to: determine an interval between adjacent sampling points of the compressed signal belonging to the same chip grid, and search for all samples belonging to the same chip grid based on the determined interval. points, and map all sample points of the compressed signal belonging to the same chip grid to a thread of the unified computing device architecture CUDA to perform parallel calculations.
  • the edges between two adjacent chips of the real-time local pseudo-random noise code respectively meet (1), it is a rising edge, (2), it is a falling edge, (3) remains +1, (4) When maintained at -1, the values of two adjacent half-chips of the mask signal generated based on the chip edges of the instant local pseudo-random noise code are consistent with the instant local pseudo-random noise code and the values of the remaining chips are 0. .
  • the real-time chip shape correlator may further include: a chip shape measurement unit configured to determine, based on data generated by the signal compression unit for measuring the chip shape of the input signal, the real-time chip shapes including chip rising and falling edges; and an accumulation unit configured to slide data generated by the signal compression unit for measuring correlation peaks of the input signal and the local pseudo-random noise code Accumulate to obtain correlation peaks.
  • a chip shape measurement unit configured to determine, based on data generated by the signal compression unit for measuring the chip shape of the input signal, the real-time chip shapes including chip rising and falling edges
  • an accumulation unit configured to slide data generated by the signal compression unit for measuring correlation peaks of the input signal and the local pseudo-random noise code Accumulate to obtain correlation peaks.
  • a method based on GPU parallel computing including: generating a corresponding mask signal according to the chip edge of the instant local pseudo-random noise code; using the instant local pseudo-random noise code to mask the signal
  • the product with the input signal is compressed to generate a compressed signal, and the compressed signal is calculated to generate data for measuring the chip shape of the input signal; and/or based on the instant local pseudo-random noise code, the leading pseudo-random noise code
  • the input signal is compressed with the lagged pseudo-random noise code to generate a compressed signal, and the compressed signal is calculated to generate data for measuring the correlation peak of the co-correlation between the input signal and the local pseudo-random noise code; where, the lead The pseudo-random noise code and the lagged pseudo-random noise code lead and lag respectively by a predetermined number of chips relative to the immediate local pseudo-random noise code.
  • the step of generating the compressed signal includes: determining the interval between adjacent sampling points belonging to the same chip grid of the compressed signal, searching for all sampling points belonging to the same chip grid according to the determined interval, and All sampling points of the compressed signal belonging to the same chip grid are mapped to a thread of the unified computing device architecture CUDA to perform parallel calculations.
  • the above method further includes: determining the real-time chip shape of the input signal including the rising edge and falling edge of the chip according to the data generated by the signal compression unit for measuring the chip shape of the input signal, and compressing the signal
  • the data generated by the unit are used to measure the co-correlation of the input signal with the local pseudo-random noise code. Sliding accumulation to obtain correlation peaks.
  • a device based on GPU parallel computing including: a memory storing computer-executable instructions; and a processor executing the instructions to implement the method as described above.
  • a storage medium which includes computer-executable instructions that, when executed, implement the method as described above.
  • all sampling points of a tracking channel in the signal compression unit are calculated in parallel, and a parallel computing method is used to map the sampling points to a corresponding thread according to the chip grid to which they belong, and the thread determines The interval between adjacent sampling points belonging to the same chip grid is used to efficiently find all sampling points belonging to the same chip grid to complete accumulation.
  • This parallel computing method significantly reduces the number of registers required for each thread, improving computational efficiency and the upper limit of resolution for chip shape and correlation peak measurements.
  • Figure 1 shows a schematic diagram of a real-time chip shape correlator of a satellite navigation system based on GPU parallel computing according to an embodiment of the present application.
  • Figure 2 shows a schematic diagram of a process for achieving correlation peak measurement according to one embodiment of the present application.
  • Figure 3 shows four types of mask signals generated by local pseudo-random noise codes according to an embodiment of the present application, and a schematic diagram of the process of measuring chip shapes through signal compression.
  • Figure 4 shows the result of measuring the 1s smooth correlation peak of satellite No. 1 of the GPS L1C/A signal using a chip shape correlator according to an embodiment of the present application.
  • Figure 5 shows the result of measuring the 1s smooth correlation peak of satellite No. 1 by adding a co-directional multipath GPS L1C/A signal with an amplitude of 0.5 and a delay of 0.2 chips using a chip shape correlator according to an embodiment of the present application.
  • Figure 6 shows the chip shape correlator according to the embodiment of the present application, measuring the correlation peak of satellite No. 1 adding the reverse multipath GPS L1C/A signal with an amplitude of 0.5 and a delay of 0.2 chips. the result of.
  • Figure 7 shows the result of measuring the 1s smooth chip rising edge of satellite No. 1 of the GPS L1C/A signal using a chip shape correlator according to an embodiment of the present application.
  • Figure 8 shows the chip shape correlator according to the embodiment of the present application measuring the 1s smooth chip rising edge of satellite No. 1 of the GPS L1C/A signal with an amplitude of 0.5 and a delay of 0.2 chips added to the co-directional multipath. the result of.
  • Figure 9 shows the chip shape correlator according to an embodiment of the present application measuring the 1s smooth chip rising edge of the GPS L1C/A signal of satellite No. 1 with an amplitude of 0.5 and a delay of 0.2 chips added to the reverse multipath. the result of.
  • FIG. 1 shows a schematic block diagram of a real-time chip shape correlator 10 of a satellite navigation system based on GPU parallel computing according to an embodiment of the present application.
  • the real-time chip shape correlator 10 may include a mask generation unit 101 and a signal compression unit 102.
  • the mask generation unit 101 generates a corresponding mask signal according to the chip edge of the instant local pseudo-random noise code.
  • Signal compression unit 102 may compress a product of the mask signal and the input carrier-stripped signal using an instantaneous local pseudo-random noise code to generate a compressed signal, and perform calculations on the compressed signal to generate a carrier-stripped signal for the measurement input.
  • the chip shape data of the resulting signal may be used to compress a product of the mask signal and the input carrier-stripped signal using an instantaneous local pseudo-random noise code to generate a compressed signal, and perform calculations on the compressed signal to generate a carrier-stripped signal for the measurement input.
  • the signal compression unit 102 may also use advanced, immediate, and delayed pseudo-random codes to perform signal compression on the input carrier-stripped signal to generate a compressed signal, and perform calculations on the compressed signal to generate Measure the correlation peak data of the co-correlation between the input carrier-stripped signal and the local pseudo-random noise code.
  • the leading pseudo-random noise code and the lagging pseudo-random noise code may lead and lag behind the immediate local pseudo-random noise code by 1 chip respectively.
  • the local pseudo-random noise code of the navigation signal can be expressed in the following form:
  • the input signal is weighted and accumulated using ⁇ k of the local pseudo-random noise code, that is,
  • the compressed signal is only one chip in length and retains all the information of the signal.
  • signal compression coherently accumulates all the chips in the signal within a period of time, the carrier-to-noise ratio gain is obtained, so the chips originally submerged in the noise can be visually observed from the compressed signal.
  • signal compression under discrete conditions is to divide the chips evenly into M grids, and during the signal compression process, the sampling points belonging to the same grid are accumulated.
  • FIG. 2 shows a schematic diagram 20 of a process in which the accumulation unit 104 performs sliding accumulation on the compressed signal obtained from the signal compression unit 102 to calculate multi-channel correlation values and implement correlation peak detection according to an embodiment of the present application.
  • Discrete correlation values can also be calculated from compressed signals. details as follows:
  • T b T c /M, is the chip grid period.
  • the received signal is compressed using an immediate pseudo-random code and a leading pseudo-random code and a lagging pseudo-random code that are one chip ahead and one chip respectively relative to the immediate pseudo-random code.
  • the compressed signal including three chips (a total of 3M chip grids) of leading, immediate and lagging. Assume its label is -M to 2M-1, then the label is n to n+M-1 (-Mn ⁇ M) M grids The sum of is R rm (nT b ), which is the correlation value with code phase n/M. Therefore, only M times of addition operations are needed to obtain a correlation value, thereby obtaining multi-channel correlation values with a small amount of operations.
  • the multi-channel correlator method requires O(L ⁇ N s ) multiplication operations and O(L ⁇ N s ) addition operations, while the chip shape correlator 10 only requires O(N s ) multiplication operations and O(N s +M ⁇ L) addition operations. Since M ⁇ N s , Therefore, the chip shape correlator 10 requires less multiplication and addition operations than a conventional multi-path correlator.
  • Figure 3 shows the four mask signals generated based on the local pseudo-random noise code to obtain the chip shape for the four cases of rising edge, falling edge, keeping +1, and keeping -1, as well as the passing signal Schematic diagram of the process of compression to measure chip shape 30.
  • this application generates the four mask signals y(t) shown in Figure 3 based on the four chip edge conditions of the local pseudo-random noise code. Only when the edges between two adjacent chips of the local pseudo-random noise code meet the requirements, the values of the mask signals of the two adjacent half-chips are consistent with the local pseudo-random noise code, and the rest are all 0. In this way, the product y(t) ⁇ r(t) of the input signal and the mask signal is compressed by the signal compression unit 102 according to the following rules:
  • the compressed signal with a size of one chip passes through the chip shape measurement unit 103 to exchange the first half of the chip and the second half of the chip, and the chips of the four situations of rising edge, falling edge, keeping +1, and keeping -1 can be obtained respectively. Accurate measurements of shape.
  • the signal compression unit 102 is further configured to: determine adjacent sampling points of the compressed signal that belong to the same chip grid. interval between them, search for all sampling points belonging to the same chip grid according to the determined interval, and map all sampling points of the compressed signal belonging to the same chip grid to a unified computing device architecture CUDA Threads to perform parallel computations.
  • the real-time chip shape correlator 10 may further include a chip shape measurement unit 103 configured to determine, based on the data generated by the signal compression unit 102 for measuring the chip shape of the input signal, the information including the code of the input signal. Real-time chip shape for chip rising and falling edges.
  • the real-time chip shape correlator 10 may further include an accumulation unit 104 configured to perform sliding accumulation on data generated by the signal compression unit 102 for measuring the correlation peaks of the input signal and the local pseudo-random noise code, to Obtain relevant peaks.
  • an accumulation unit 104 configured to perform sliding accumulation on data generated by the signal compression unit 102 for measuring the correlation peaks of the input signal and the local pseudo-random noise code, to Obtain relevant peaks.
  • the GPU-based parallel algorithm in the signal compression unit 102 can be implemented using CUDA, and can also be extended to other heterogeneous platform programming frameworks. Each tracking channel is mapped to a CUDA thread block for parallel calculation, and the sampling points are mapped to threads in the CUDA thread block for parallel accumulation calculation.
  • the calculation result of signal compression is a compressed signal of length M, and in order to calculate the correlation value, the signal compression unit 102 needs to complete the signal compression of the in-directional and orthogonal components of the E, P, and L compressed signals, so each thread stores all signals
  • the compression result requires 6M registers. Registers on the GPU are scarce resources, and the maximum number of registers for a thread in CUDA is 255.
  • each thread is only responsible for the multiplication and accumulation calculation of all sampling points falling into a certain chip grid, and only 6 registers are needed to store a certain The 6-way accumulation result of the chip grid avoids register overflow and improves calculation efficiency.
  • the upper limit of the value of M is also extended to the maximum number of threads in the thread block in CUDA, 1024, and the upper limit of the resolution of the chip shape correlator 10 is also increased accordingly.
  • the thread determines the distance from the next sampling point belonging to the same chip grid through an efficient algorithm, thereby finding all the chips that fall into the chip grid that it is responsible for calculating. Sampling point.
  • the interval between adjacent sampling points has only a few fixed possible values Pi (P 1 ⁇ P 2 ⁇ ... ⁇ P n ), and the current specific value can be determined through a simple judgment criterion: after shifting Pi sample points from the current sampling point, in addition to the chip phase that may be moved by an integer, a fractional
  • the chip phase offset is as shown in the following formula:
  • the fractional phase offset of the corresponding chip grid can be defined as:
  • a i can meet the above conditions in ascending order.
  • the P i corresponding to the first A i that meets the conditions is the distance between the current sampling point and the next sampling point. Since the maximum interval between adjacent sampling points belonging to the same chip grid is max(P i ), therefore, at least one sampling point in all chip grids must be found in the continuous max(P i ) sampling points, As the first sampling point in the chip grid, the next sampling point belonging to this chip grid is continuously found through the above judgment criteria, thereby recursively finding all the sampling points belonging to this chip grid.
  • the specific value calculation process of Pi is as follows: First, calculate the possible values of the spacing between all sampling points belonging to the same chip grid Qi . Since P i is the distance between adjacent sampling points belonging to the same chip grid, and Q i is the possible value of the distance between adjacent sampling points belonging to the same chip grid, Q i must contain All Pi . Assume n 1 and n 2 are the indices of two sampling points belonging to the same chip grid, so they need to satisfy:
  • Pi is selected from Qi .
  • Qi the index spacing Pi between adjacent sampling points of the same chip grid, so it is also necessary to filter out Pi from Qi .
  • the fractional chip grid changes to the following offset:
  • the changed fractional frequency must still be in the range of 0 to 1, that is: 0 ⁇ F i +A i ⁇ 1
  • F i corresponding to Q i is calculated in ascending order. If the union of the first k F i is [0,1), then for the initial fractional chip grid situation of 0 ⁇ F ⁇ 1, it can be calculated in Q Find Q i in i ...Q k such that 0 ⁇ F+A i ⁇ 1, that is, Q i ...Q k contains all possible spacings between adjacent sampling points belonging to the same chip grid property, which is the required Pi .
  • the following is an evaluation example of a real-time chip shape correlator and method for a satellite navigation system based on GPU parallel computing according to the present application.
  • the number of grids of one chip in the signal compression unit 102 is 40.
  • the value of Pi is first determined. Substituting the parameters into the inequality 13) mentioned above determines:
  • the signal compression of the L1CA signal can be performed in parallel to achieve real-time measurement of the correlation peak and chip shape.
  • a method based on GPU parallel computing includes: generating a corresponding mask signal according to the chip edge of the instant local pseudo-random noise code; using the instant local pseudo-random noise code to compress the product of the mask signal and the input signal to generate a compressed signal, and performing calculations on the signal to generate data for measuring the chip shape of the input signal; and/or compressing the input signal based on the immediate local pseudo-random noise code, the leading pseudo-random noise code, and the lagging pseudo-random noise code to generate a compressed signal, and performs calculations on the compressed signal to generate the measured input signal versus the local Data on cocorrelated correlation peaks of pseudorandom noise codes.
  • the leading pseudo-random noise code and the lagging pseudo-random noise code lead and lag respectively by a predetermined number of chips relative to the immediate local pseudo-random noise code.
  • the predetermined number of chips may be 1 chip.
  • the compressed signal may be one chip in size and may be divided into a grid of chips.
  • the step of generating the compressed signal may include: determining an interval between adjacent sampling points of the compressed signal that belong to the same chip grid, and searching for all samples belonging to the same chip grid based on the determined interval. points, and map all sample points of the compressed signal belonging to the same chip grid to a thread of the unified computing device architecture CUDA to perform parallel calculations.
  • the step of generating a corresponding mask signal according to the chip edge of the instant local pseudo-random noise code may include: responding to the edges between two adjacent chips of the instant local pseudo-random noise code respectively complying with (1) is the rising edge, (2) is the falling edge, (3) remains +1, (4) remains -1, a mask signal is generated based on the chip edge of the real-time local pseudo-random noise code, where two adjacent mask signals The value of half of the chips is consistent with the instantaneous local pseudo-random noise code and the value of the remaining chips is 0.
  • the above method may further include: determining the real-time chip shape of the input signal, including chip rising edges and falling edges, based on the data generated by the signal compression unit 102 for measuring the chip shape of the input signal, and performing sliding accumulation on the data generated by the signal compression unit 102 for measuring the correlation peak of the co-correlation between the input signal and the local pseudo-random noise code to obtain the correlation peak.
  • This application performs parallel calculations on all sampling points of a tracking channel in the signal compression unit, using a parallel computing method that maps the sampling points to a corresponding thread according to the chip grid to which they belong, and the threads determine that they belong to the same chip grid The interval between adjacent sampling points is used to efficiently search for all sampling points belonging to the same chip grid to complete accumulation.
  • This parallel computing method significantly reduces the number of registers required for each thread, improving computational efficiency and the upper limit of resolution for chip shape and correlation peak measurements.
  • a device based on GPU parallel computing including: a memory that stores computer-executable instructions; and a processor that executes the instructions. to implement the method described above.
  • a storage medium which includes computer-executable instructions that, when executed, implement the method described above.
  • Figure 4 shows the result 40 of the chip shape correlator monitoring the 1s smooth correlation peak of satellite No. 1 of the GPS L1CA signal according to an embodiment of the present application.
  • the signal here is generated by the Spirent GSS9000 analog source.
  • the accumulation unit 104 After being compressed by the signal compression unit 102, the accumulation unit 104 performs sliding addition to obtain multi-channel correlation values to achieve real-time measurement of correlation peaks.
  • the number of chip grids is 40, a maximum of 81 correlation values can be generated, and in this embodiment, 39 correlation values are generated at a chip interval of 0.05.
  • the measured correlation peak is very close to the standard correlation peak, indicating that the current received signal is normal.
  • Figures 5 and 6 respectively show the 1s smoothing of the No. 1 satellite monitored by the chip shape correlator according to the embodiment of the present application, adding the in-directional and reverse multi-path GPS L1CA signals with an amplitude of 0.5 and a delay of 0.2 chips. Correlation peaks result in 50 and 60. It can be seen from the figure that the slope of the correlation function changes significantly at the fourth sampling point of the correlation peak. Therefore, it can be known that the delay of the multipath is 0.2 chips. The phase and amplitude of the multipath can also be determined according to the specific slope. Calculated. This illustrates that the chip shape correlator according to the embodiment of the present application can realize the monitoring of multipath and other distortions of the received signal through real-time measurement of correlation peaks.
  • Figure 7 shows the result 70 of the chip shape correlator monitoring the 1s smooth chip rising edge of satellite No. 1 of the GPS L1C/A signal according to an embodiment of the present application.
  • the code phase interval is 0.025 chips, which can clearly represent the rising edge shape of the chip.
  • Figures 8 and 9 respectively show the chip shape correlator monitoring the GPS L1C/A signal No. 1 under the same direction and reverse multipath with an amplitude of 0.5 and a delay of 0.2 chips according to the embodiment of the present application.
  • the results of the satellite's 1s smooth chip rising edge are 80 and 90. It can be seen from the figure that multipath causes great changes in chip shape.
  • the obtained chip rising edge information can be used for subsequent processing of multipath suppression and other technologies.
  • Table 1 below shows the average time required to process 1ms data in the tracking link according to the chip shape correlator method and the traditional multi-channel correlator method according to the embodiment of the present application.
  • the GPU used in the test is NVIDIA GeForce RTX 3080. During the test, it simultaneously processes the L1C/A and L5 signals of the GPS system, the B1C, B2a, and B1I signals of the BDS system, and the GAL system.
  • the traditional E1OS and E5a signals have a total of 7 signals, each signal has 12 channels, so there are a total of 84 channels.
  • the traditional multi-channel correlator method used as a comparison is also calculated in parallel by the GPU and outputs 5 channels of correlation signals.
  • the chip shape correlator according to the embodiment of the present application is divided into two situations: outputting only 39 channels of correlation values, and outputting 39 channels of correlation values while outputting the chip rising edge shape. It can be seen that since the signal compression method reduces the amount of calculation, the time it takes for the chip shape correlator to calculate 39-channel correlation values is less than the time it takes to calculate 5-channel correlation values using the traditional multi-channel correlator, and the chip shape correlation The extra calculation of the rising edge of the chip will increase the time consumption, but processing 1ms of data on average 0.58ms can still ensure the real-time operation of the receiver.

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Abstract

本申请公开了一种基于GPU并行计算的实时码片形状相关器以及方法。码片形状相关器包括：遮罩生成单元，其配置成根据即时本地伪随机噪声码的码片边缘生成相应的遮罩信号；以及信号压缩单元，其配置成：使用所述即时本地伪随机噪声码对所述遮罩信号与输入信号的乘积进行压缩，生成经压缩信号，并且对所述经压缩信号进行计算以生成用于测量所述输入信号的码片形状的数据；和/或根据即时本地伪随机噪声码、超前伪随机噪声码和滞后伪随机噪声码对输入信号进行压缩，生成经压缩信号，并且对所述经压缩信号进行计算，以生成用于测量所述输入信号与本地伪随机噪声码的协相关的相关峰的数据。

Description

基于GPU并行计算的卫星导航系统码片形状相关器和方法
交叉引用
本申请要求于2022年04月29日向中国专利局提交的、发明名称为“基于GPU并行计算的卫星导航系统码片形状相关器和方法”的第202210473223.4号发明专利申请的优先权，上述专利申请的全部内容通过引用并入本文。
技术领域
本申请涉及无线电导航软件接收机领域，特别涉及一种基于GPU并行计算的卫星导航系统实时码片形状相关器和方法。
背景技术
全球导航卫星系统(GNSS，Global Navigation Satellite System)无线电软件(SDR，software defined radio)接收机的主要信号处理过程均通过软件处理模块实现，相较于硬件接收机更容易调试和升级修改，且有更好的可配置性，因此在GNSS的各种应用领域中发挥着着很重要的作用。而相关运算中包含大量的乘累加运算，沉重的计算负担使得基于处理器(CPU)的SDR接收机的实时性很难保证。而基于图形处理器(GPU)并行计算可以使SDR接收机中的相关计算大幅加速，从而满足实时性要求。
随着对GNSS精度和完好性要求的不断提高，SDR接收机中越来越复杂的信号处理算法对于相关器的输出也提出了更高的要求。标准相关器通常只输出3-5路相关值用于信号跟踪，但一些多径抑制和信号质量监测算法需要更多的相关值输出组成的相关峰。而标准相关器每多计算一路相关值都需要一次完整的相关运算，SDR接收机的标准相关器很难实时计算多路相关值。码片形状相关器可以利用多路相关值之间的重复计算，减小计算多路相关值的计算量。同时，码片形状 相关器也可以测量码片形状，以用于多径抑制算法以及基于码片域观测量的信号质量监测算法。但SDR接收机码片形状相关器对于内存的分配和访问提出了更高的要求。
因此，为了能够满足实时测量相关峰以及码片形状的需求，需要设计更加合理的基于GPU并行计算的卫星导航系统实时码片形状相关器和方法。
发明内容
为了解决上述问题或本领域中存在的其它问题，本申请提供了一种基于GPU并行计算的GNSS SDR接收机实时码片形状相关器系统和方法。
根据本申请的一个方面，提供了一种基于GPU并行计算的实时码片形状相关器，包括：遮罩生成单元，其配置成根据即时本地伪随机噪声码的码片边缘生成相应的遮罩信号；以及信号压缩单元，其配置成：使用即时本地伪随机噪声码对遮罩信号与输入信号的乘积进行压缩，生成经压缩信号，并且对经压缩信号进行计算以生成用于测量输入信号的码片形状的数据；和/或根据即时本地伪随机噪声码、超前伪随机噪声码和滞后伪随机噪声码对输入信号进行压缩，生成经压缩信号，并且对经压缩信号进行计算，以生成用于测量输入信号与本地伪随机噪声码的协相关的相关峰的数据；其中，超前伪随机噪声码和滞后伪随机噪声码相对于即时本地伪随机噪声码分别超前和滞后预定数目的码片。
在一个实施例中，预定数目码片可以包括1个码片。
在一个实施例中，经压缩信号的大小为一个码片，且被划分为多个码片格子。
在一个实施例中，信号压缩单元进一步配置成：确定经压缩信号的属于同一个码片格子的相邻采样点之间的间隔，根据所确定的间隔来寻找属于同一个码片格子的全部采样点，以及将经压缩信号的属于同一个码片格子的全部采样点映射到统一计算设备架构CUDA的一个线程以执行并行计算。
在一个实施例中，当即时本地伪随机噪声码的相邻两个码片之间的边缘分别符合(1)为上升沿，(2)为下降沿，(3)保持+1，(4)保持-1时，根据即时本地伪随机噪声码的码片边缘所生成的遮罩信号的两个相邻的半码片的值与即时本地伪随机噪声码相一致且其余码片的值为0。
在一个实施例中，实时码片形状相关器可以进一步包括：码片形状测量单元，其配置成根据信号压缩单元所生成的、用于测量输入信号的码片形状的数据，确定输入信号的、包括码片上升沿和下降沿的实时码片形状；以及累加单元，其配置成对信号压缩单元所生成的、用于测量输入信号与本地伪随机噪声码的协相关的相关峰的数据进行滑动累加，以获得相关峰。
根据本申请的另一方面，提供了一种基于GPU并行计算的方法，包括：根据即时本地伪随机噪声码的码片边缘生成相应的遮罩信号；使用即时本地伪随机噪声码对遮罩信号与输入信号的乘积进行压缩，生成经压缩信号，并且对经压缩信号进行计算以生成用于测量输入信号的码片形状的数据；和/或根据即时本地伪随机噪声码、超前伪随机噪声码和滞后伪随机噪声码对输入信号进行压缩，生成经压缩信号，并且对经压缩信号进行计算，以生成用于测量输入信号与本地伪随机噪声码的协相关的相关峰的数据；其中，超前伪随机噪声码和所述滞后伪随机噪声码相对于即时本地伪随机噪声码分别超前和滞后预定数目的码片。
其中，生成经压缩信号的步骤包括：确定经压缩信号的属于同一个码片格子的相邻采样点之间的间隔，根据所确定的间隔来寻找属于同一个码片格子的全部采样点，以及将经压缩信号的属于同一个码片格子的全部采样点映射到统一计算设备架构CUDA的一个线程以执行并行计算。
其中，上述方法进一步包括：根据信号压缩单元所生成的、用于测量输入信号的码片形状的数据，确定输入信号的、包括码片上升沿和下降沿的实时码片形状，以及对信号压缩单元所生成的、用于测量输入信号与本地伪随机噪声码的协相关的相关峰的数据进行 滑动累加，以获得相关峰。
根据本申请的另一方面，提供了一种基于GPU并行计算的装置，包括：存储器，存储有计算机可执行的指令；以及处理器，执行指令以实现如上所述的方法。
根据本申请的另一方面，提供了一种存储介质，其包括计算机可执行的指令，该指令被执行时实现如上所述的方法。
根据本申请的一个实施例，对信号压缩单元中一个跟踪通道的全部采样点进行并行计算，采用将采样点根据其所属的码片格子映射到对应的一个线程的并行运算方法，并且线程通过确定属于同一个码片格子的相邻采样点之间的间隔，来高效寻找属于同一个码片格子的全部采样点以完成累加。该并行计算方式使得每个线程所需使用的寄存器数量大幅降低，提高了计算效率以及码片形状和相关峰测量的分辨率上限。
附图说明
图1示出了根据本申请实施例的基于GPU并行计算的卫星导航系统实时码片形状相关器的示意图。
图2示出了根据本申请一个实施例的用于实现相关峰测量的过程的示意图。
图3示出了根据本申请一个实施例的本地伪随机噪声码产生的四种遮罩信号，以及通过信号压缩来测量码片形状的过程的示意图。
图4示出了根据本申请实施例的码片形状相关器测量GPS L1C/A信号的1号卫星的1s平滑相关峰的结果。
图5示出了根据本申请实施例的码片形状相关器测量添加了幅度为0.5、延迟为0.2码片的同向多径GPS L1C/A信号的1号卫星的1s平滑相关峰的结果。
图6示出了根据本申请实施例的码片形状相关器测量添加了幅度为0.5、延迟为0.2码片的反向多径GPS L1C/A信号的1号卫星的相关峰 的结果。
图7示出了根据本申请实施例的码片形状相关器测量GPS L1C/A信号的1号卫星的1s平滑码片上升沿的结果。
图8示出了根据本申请实施例的码片形状相关器测量添加了幅度为0.5、延迟为0.2码片的同向多径的GPS L1C/A信号的1号卫星的1s平滑码片上升沿的结果。
图9示出了根据本申请实施例的码片形状相关器测量添加了幅度为0.5、延迟为0.2码片的反向多径的GPS L1C/A信号的1号卫星的1s平滑码片上升沿的结果。
具体实施方式
以下描述参考附图更全面地说明本公开的实施例及其各种特征和细节。省略对公知部件和处理技术的描述，以免不必要地模糊本公开的实施例。另外，本公开描述的各种实施例无需相互排斥，因为一些实施例可以与一个或多个其他实施例组合以形成新的实施例。除非另外指明，否则如本公开使用的术语“或”指的是非排他的或。本公开使用的示例仅仅意图帮助理解可以实践本公开的实施例的方式，并且进一步使得本领域的技术人员能够实践本公开的实施例。因此，示例不应被解释为限制本公开的实施例的范围。
还应理解的是，诸如“包括”、“包括有”、“具有”、“包含”和/或“包含有”等表述在本说明书中是开放性而非封闭性的表述，其表示存在所陈述的特征、元件和/或部件，但不排除一个或多个其它特征、元件、部件和/或它们的组合的存在。此外，当诸如“……中的至少一个”的表述出现在所列特征的列表之后时，其修饰整列特征，而非仅仅修饰列表中的单独元件。此外，当描述本申请的实施方式时，使用“可”表示“本申请的一个或多个实施方式”。并且，用语“示例性的”旨在指代示例或举例说明。
除非另外限定，否则本文中使用的全部措辞(包括工程术语和科技术语)均具有与本申请所属领域普通技术人员的通常理解相同的含义。还应理解的是，除非本申请中有明确的说明，否则在常用词典中 定义的词语应被解释为具有与它们在相关技术的上下文中的含义一致的含义，而不应以理想化或过于形式化的意义解释。
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。另外，除非明确限定或与上下文相矛盾，否则本申请所记载的方法中包含的具体步骤不必限于所记载的顺序，而可以任意顺序执行或并行地执行。下面将参考附图并结合实施例来详细说明本申请。
图1示出了根据本申请实施例的基于GPU并行计算的卫星导航系统实时码片形状相关器10的示意框图。实时码片形状相关器10可包括遮罩生成单元101和信号压缩单元102。遮罩生成单元101根据即时本地伪随机噪声码的码片边缘生成相应的遮罩信号。信号压缩单元102可使用即时本地伪随机噪声码对遮罩信号与输入的载波剥离后的信号的乘积进行压缩，生成经压缩信号，并且对经压缩信号进行计算以生成用于测量输入的载波剥离后的信号的码片形状的数据。
在一个示例中，信号压缩单元102还可以使用超前、即时、滞后伪随机码，对输入的载波剥离后的信号进行信号压缩，生成经压缩信号，并且对经压缩信号进行计算，以生成用于测量输入的载波剥离后的信号与本地伪随机噪声码的协相关的相关峰的数据。
优选地，超前伪随机噪声码和滞后伪随机噪声码可以相对于即时本地伪随机噪声码分别超前和滞后1个的码片。
当即时本地伪随机噪声码的相邻两个码片之间的边缘分别符合(1)为上升沿，(2)为下降沿，(3)保持+1，(4)保持-1时，根据即时本地伪随机噪声码的码片边缘所生成的遮罩信号的两个相邻的半码片的值与即时本地伪随机噪声码相一致且其余码片的值为0。
导航信号的本地伪随机噪声码可以表示为以下形式：
即本地伪随机噪声码m(t)可以表示为码片函数c(t)通过εk＝±1加权，移位若干个码片周期Tc相加得到。在信号压缩单元102中， 用本地伪随机噪声码的εk对输入信号进行加权累加，即
经压缩后的信号只有一个码片的长度，且保留了信号的全部信息。另外，由于信号压缩将一段时间内信号中全部的码片进行了相干累加，获得了载噪比的增益，因此原本淹没在噪声中的码片可以从压缩信号中得到可视化的观测。对于实际使用的离散的情况，通常在不同的码片中不会有严格对应的采样点。因此，离散情况下的信号压缩是将码片均匀划分为M个格子，在信号压缩的过程中对属于同一个格子的采样点进行累加。
图2示出了根据本申请一个实施例的、累加单元104对从信号压缩单元102得到的经压缩信号进行滑动累加以计算多路相关值，实现相关峰检测的过程的示意图20。离散相关值也可以由压缩信号计算。具体如下：
其中Tb＝Tc/M，是码片格子周期。
在基于码片形状的相关峰检测中，使用即时伪随机码以及相对于即时伪随机码分别超前和滞后1个码片的超前伪随机码和滞后伪随机码对所接收的信号进行信号压缩，得到包括超前、即时、滞后三个码片(共3M个码片格子)的压缩信号，设其标号为-M到2M-1，则标号为n至n+M-1(-M-n≤M)的M个格子的和为Rrm(nTb)，即为码相位为n/M的相关值。因此只需要进行M次加法运算，即可得到一个相关值，从而以很小的运算量得到多路相关值。设跟踪数据的总采样点数为Ns，相关器输出L路相关值，且L>3，则采用多路相关器方法需要O(L·Ns)的乘法运算和O(L·Ns)的加法运算，而码片形状相关器10只需要O(Ns)的乘法运算以及O(Ns+M·L)的加法运算。由于M＜＜Ns， 因此码片形状相关器10所需的乘法运算和加法运算都要少于传统的多路相关器。
图3示出了用来获得码片边缘为上升沿、下降沿、保持+1、保持-1四种情况的码片形状而根据本地伪随机噪声码产生的四种遮罩信号，以及通过信号压缩来测量码片形状的过程的示意图30。
在信号压缩单元102中，如果直接使用本地伪随机噪声码进行信号压缩，则码片边缘情况不同的码片会被叠加在一起，因此得到的码片边缘是没有意义的。因此，本申请根据本地伪随机噪声码的4种码片边缘情况生成图3中所示的四种遮罩信号y(t)。只有在本地伪随机噪声码相邻的两个码片之间的边缘符合要求时两个相邻的半码片的遮罩信号的值与本地伪随机噪声码一致，其余部分皆为0。这样，输入信号与遮罩信号的乘积y(t)·r(t)经信号压缩单元102通过以下规则压缩：
在信号压缩的过程中只对边缘满足要求的码片单独进行累加，因此可以确保对于码片边缘的测量是准确的。而大小为一个码片的压缩信号经过码片形状测量单元103交换前一半码片和后一半码片，可以分别得到上升沿、下降沿、保持+1、保持-1这四种情况的码片形状的准确测量结果。
在经压缩信号的大小为一个码片，且被划分为多个码片格子的情况下，信号压缩单元102进一步配置成：确定所述经压缩信号的属于同一个码片格子的相邻采样点之间的间隔，根据所确定的间隔来寻找属于同一个码片格子的全部采样点，以及将所述经压缩信号的属于同一个码片格子的全部采样点映射到统一计算设备架构CUDA的一个线程以执行并行计算。
实时码片形状相关器10可以进一步包括码片形状测量单元103，其配置成根据信号压缩单元102所生成的、用于测量输入信号的码片形状的数据，确定所述输入信号的、包括码片上升沿和下降沿的实时码片形状。
实时码片形状相关器10可以进一步包括累加单元104，其配置成对信号压缩单元102所生成的、用于测量输入信号与本地伪随机噪声码的协相关的相关峰的数据进行滑动累加，以获得相关峰。
信号压缩单元102中的基于GPU的并行算法可以采用CUDA实现，也可以推广至其他异构平台程序编写的框架。每个跟踪通道映射到一个CUDA的线程块进行并行计算，采样点映射到CUDA线程块中的线程并行进行累加计算。信号压缩的计算结果是长度为M的压缩信号，而信号压缩单元102为了计算相关值需要完成E、P、L压缩信号的同向和正交分量的信号压缩，因此每个线程存储全部的信号压缩结果需要6M个寄存器。而GPU上的寄存器是稀缺资源，CUDA中一个线程的寄存器数量最大值为255。为了避免出现寄存器溢出导致的计算效率降低，M的取值不能超过42。这意味着对于相关峰和码片形状的测量无法达到很高的分辨率。因此，为了避免这一问题，在本申请的信号压缩单元102的实现中，每个线程只负责落入某一个码片格子的全部采样点的乘累加计算，只需要6个寄存器来存储某一个码片格子的6路累加结果，从而避免了寄存器溢出，提高了计算效率。而且M的取值上限也扩展到CUDA中线程块中的最大线程数1024，码片形状相关器10的分辨率上限也随着提升。
基于信号压缩单元102的采样点到线程的映射机制，线程通过一种高效算法判断与属于同一个码片格子的下一个采样点的间距，从而寻找落入自身所负责计算的码片格子的全部采样点。在给定的采样率fs、码速率fc以及码片格子的数量M下，相邻的采样点的间隔只有几个固定的可能取值Pi(P1<P2<…<Pn)，且可以通过一种简单的判断准则来确定当前的具体取值：在从当前采样点偏移Pi个采样点之后，除了可能移动了整数的码片相位以外，还会产生一个分数的码片相位偏移，如下式所示：
由于码片被划分为M个码片格子，因此可以定义对应的码片格子的分数相位偏移为：
假设在当前采样点位置时还存在一个之前移动产生的分数相位偏移F(0≤F<1)，那么在移动Pi个采样点后，如果采样点仍然在同一个码片格子中，则新的分数相位偏移需要满足：
0≤F+Ai<1                 8)
因此，按照升序的方式检查Ai是否能够满足上述条件，第一个满足条件的Ai所对应的Pi即为当前采样点到下一个采样点之间的间距。由于属于同一个码片格子的相邻采样点之间的最大间隔为max(Pi)，因此，连续的max(Pi)采样点中一定能找到全部码片格子中的至少一个采样点，作为码片格子中的第一个采样点，再通过上述的判断准则不断找到属于这个码片格子的下一个采样点，从而递推的找到属于这个码片格子的全部采样点。
在给定的采样率fs，码速率fc和码片格子数量M下，Pi的特定取值计算过程如下：首先，计算属于同一个码片格子的全部采样点的间距的可能取值Qi。由于Pi是属于同一个码片格子的相邻采样点之间的间距，而Qi是属于同一个码片格子的相邻采样点之间的间距的可能取值，因此Qi中一定包含全部Pi。设n1和n2是属于同一个码片格子的两个采样点的索引，因此需要满足：
令



将k＝1、2、……代入上式中，即可计算出属于同一个码片格子的两个采样点之间的索引之差的全部可能，即为Qi。
随后，从Qi中选出Pi。在上述的Qi中，只有其中的一些可能属于同一个码片格子的相邻采样点之间的索引间距Pi，因此还需要从Qi中筛选出Pi。当移动了Qi个采样点后，分数码片格子的改变为如下偏移：
如果在移动Qi后的采样点仍然属于同一个码片格子，则必有改变后的分数频率仍处于0到1的范围内，即：
0≤Fi+Ai<1
因此，按照升序的顺序计算Qi所对应的Fi，如果前k个Fi的并集是[0,1)，则对于0≤F<1的初始分数码片格子情况，都可以在Qi...Qk中找到Qi，使得0≤F+Ai<1，即Qi...Qk中包含了属于同一个码片格子的相邻采样点之间的间距的全部可能性，即为所要求的Pi。
以下给出根据本申请的一种基于GPU并行计算的卫星导航系统实时码片形状相关器和方法的评估实施例。
对于GPS L1CA信号，码速率fc＝1.023MHz，并采用fs＝24MHz进行采样，信号压缩单元102中一个码片的格子数为40。则按照上述基于GPU并行计算的信号压缩方法，首先确定Pi的取值。代入参数到上面提及的不等式13)确定出：
因此当k＝1时得到的不等式如下：

n2-n1＝23,24
当k＝2时得到的不等式如下：

n2-n1＝47
所以Q1＝23、Q2＝24、Q3＝47是属于相同码片格子的采样点之间的间隔的3个最小可能值。
由Q1＝23、Q2＝24、Q3＝47计算得到对应的分数格子偏移为A1＝-0.785、A2＝0.92、A3＝0.135，因此，要满足偏移后仍在同一个码片格子，对应的初始分数格子偏移区间应为：
F1∈[0.785,1),F2∈[0,0.08),F3∈[0,0.865)
由于：
[0.785,1)∪[0,0.08)∪[0,0.865)＝[0,1)
因此，已经包含了全部的初始分数格子情况，属于同一码片格子的相邻采样点之间的间隔只有P1＝23、P2＝24、P3＝47三种情况。
根据参数P1、P2、P3，按照基于GPU并行计算的信号压缩算法，可以并行进行L1CA信号的信号压缩，实现相关峰和码片形状的实时测量。
根据本申请的另一个方面，提供了一种基于GPU并行计算的方法。该方法包括：根据即时本地伪随机噪声码的码片边缘生成相应的遮罩信号；使用即时本地伪随机噪声码对遮罩信号与输入信号的乘积进行压缩，生成经压缩信号，并且对经压缩信号进行计算以生成用于测量输入信号的码片形状的数据；和/或根据即时本地伪随机噪声码、超前伪随机噪声码和滞后伪随机噪声码对输入信号进行压缩，生成经压缩信号，并且对经压缩信号进行计算，以生成用于测量输入信号与本地 伪随机噪声码的协相关的相关峰的数据。其中，超前伪随机噪声码和滞后伪随机噪声码相对于即时本地伪随机噪声码分别超前和滞后预定数目的码片。
示例性地，预定数目码片可以是1个码片。
示例性地，经压缩信号的大小可以为一个码片，且可以被划分为多个码片格子。
示例性地，生成经压缩信号的步骤可以包括：确定经压缩信号的属于同一个码片格子的相邻采样点之间的间隔，根据所确定的间隔来寻找属于同一个码片格子的全部采样点，以及将经压缩信号的属于同一个码片格子的全部采样点映射到统一计算设备架构CUDA的一个线程以执行并行计算。
示例性地，根据即时本地伪随机噪声码的码片边缘生成相应的遮罩信号的步骤可以包括：响应于即时本地伪随机噪声码的相邻两个码片之间的边缘分别符合(1)为上升沿，(2)为下降沿，(3)保持+1，(4)保持-1，根据即时本地伪随机噪声码的码片边缘生成遮罩信号，其中遮罩信号的两个相邻的半码片的值与即时本地伪随机噪声码相一致且其余码片的值为0。
示例性地，上述方法可以进一步包括：根据信号压缩单元102所生成的、用于测量输入信号的码片形状的数据，确定输入信号的、包括码片上升沿和下降沿的实时码片形状，以及对信号压缩单元102所生成的、用于测量输入信号与本地伪随机噪声码的协相关的相关峰的数据进行滑动累加，以获得相关峰。
本申请对信号压缩单元中一个跟踪通道的全部采样点进行并行计算，采用将采样点根据其所属的码片格子映射到对应的一个线程的并行运算方法，并且线程通过确定属于同一个码片格子的相邻采样点之间的间隔来高效寻找属于同一个码片格子的全部采样点以完成累加。该并行计算方式使得每个线程所需使用的寄存器数量大幅降低，提高了计算效率以及码片形状和相关峰测量的分辨率上限。
根据本申请的另一方面，提供了一种基于GPU并行计算的装置，包括：存储器，存储有计算机可执行的指令；以及处理器，执行指令 以实现上文所述的方法。
根据本申请的另一方面，提供了一种存储介质，其包括计算机可执行的指令，该指令被执行时实现上文所述的方法。
图4示出了根据本申请实施例的码片形状相关器监测GPS L1CA信号的1号卫星的1s平滑相关峰的结果40。此处的信号由Spirent GSS9000模拟源生成，经过信号压缩单元102的压缩后，由累加单元104进行滑动相加，得到多路的相关值，实现相关峰的实时测量。在码片的格子数为40的情况下，最多可以生成81路相关值，而本实施例中按照0.05码片间隔生成了39路相关值。从图中可以看出，测量得到的相关峰和标准的相关峰十分接近，说明当前接收信号正常。
图5和图6分别示出了根据本申请实施例的码片形状相关器监测添加了幅度为0.5、延迟为0.2码片的同向和反向多径GPS L1CA信号的1号卫星的1s平滑相关峰的结果50和60。从图中可以看出，在相关峰第四个采样点处相关函数的斜率发生了明显的变化，因此可以得知多径的延迟为0.2码片，多径的相位和幅度也可以根据具体的斜率计算得出。这说明了根据本申请实施例的码片形状相关器可以通过相关峰实时测量来实现对接收信号多径等失真的监测。
图7示出了根据本申请实施例的码片形状相关器监测GPS L1C/A信号的1号卫星的1s平滑码片上升沿的结果70。在码片相位为-0.5到0.5的一个码片内，共有40个格子，因此，码相位间隔为0.025码片，能够较为清晰的表示码片的上升沿形状。
图8和图9分别示出了根据本申请实施例的码片形状相关器监测添加了幅度为0.5、延迟为0.2码片的同向和反向多径下的GPS L1C/A信号的1号卫星的1s平滑码片上升沿的结果80和90。从图中可以看出，多径导致了码片形状的很大改变。所得到的码片上升沿信息，可以用于多径抑制等技术的后续处理。
下面的表1示出了根据本申请实施例的码片形状相关器方法和传统多路相关器方法在跟踪环节处理1ms数据所需要的平均时间。测试所使用的GPU为NVIDIA GeForce RTX 3080，测试中同时处理GPS系统的L1C/A和L5信号，BDS系统的B1C、B2a、B1I信号，以及GAL系 统的E1OS和E5a信号，共7种信号，每种信号12个通道，因此，总共84个通道，其中作为对照的传统多路相关器方法同样通过GPU并行计算，输出5路相关信号。根据本申请实施例的码片形状相关器分为只输出39路相关值、以及输出39路相关值的同时输出码片上升沿形状这两种情况。可以看出，由于采用信号压缩方法减少了计算量，码片形状相关器计算39路相关值所花费的时间小于使用传统多路相关器计算5路相关值所花费的时间，而码片形状相关器额外计算码片上升沿会使得时间消耗增加，但平均0.58ms处理1ms的数据仍然可以保证接收机运行的实时性。
码片形状相关器方法和传统多路相关器方法处理1ms数据所需平均时间如下表1所示。
表1
以上实施方式仅用于说明本申请，而并非对本申请的限制。有关技术领域的普通技术人员，在不脱离本申请的精神和范围的情况下，可以对本申请所公开的实施方式和实施例做出各种变化和变型，因此所有等同的技术方案也属于本申请的范畴，本申请的专利保护范围由权利要求限定。

Claims (12)

  1. 一种基于GPU并行计算的实时码片形状相关器，包括：
    遮罩生成单元，其配置成根据即时本地伪随机噪声码的码片边缘生成相应的遮罩信号；以及
    信号压缩单元，其配置成：
    使用所述即时本地伪随机噪声码对所述遮罩信号与输入信号的乘积进行压缩，生成经压缩信号，并且对所述经压缩信号进行计算以生成用于测量所述输入信号的码片形状的数据；和/或
    根据即时本地伪随机噪声码、超前伪随机噪声码和滞后伪随机噪声码对输入信号进行压缩，生成经压缩信号，并且对所述经压缩信号进行计算，以生成用于测量所述输入信号与本地伪随机噪声码的协相关的相关峰的数据；其中，所述超前伪随机噪声码和所述滞后伪随机噪声码相对于所述即时本地伪随机噪声码分别超前和滞后预定数目的码片。
  2. 根据权利要求1所述的实时码片形状相关器，其中，所述预定数目码片包括1个码片。
  3. 根据权利要求1-2中任一项所述的实时码片形状相关器，其中，所述经压缩信号的大小为一个码片，且被划分为多个码片格子；
    其中，所述信号压缩单元进一步配置成：
    确定所述经压缩信号的属于同一个码片格子的相邻采样点之间的间隔，
    根据所确定的间隔来寻找属于同一个码片格子的全部采样点，以及
    将所述经压缩信号的属于同一个码片格子的全部采样点映射 到统一计算设备架构CUDA的一个线程以执行并行计算。
  4. 根据权利要求1所述的实时码片形状相关器，其中，当所述即时本地伪随机噪声码的相邻两个码片之间的边缘分别符合(1)为上升沿，(2)为下降沿，(3)保持+1，(4)保持-1时，根据所述即时本地伪随机噪声码的码片边缘所生成的所述遮罩信号的两个相邻的半码片的值与所述即时本地伪随机噪声码相一致且其余码片的值为0。
  5. 根据权利要求1所述的实时码片形状相关器，进一步包括：
    码片形状测量单元，其配置成根据所述信号压缩单元所生成的、用于测量所述输入信号的码片形状的数据，确定所述输入信号的、包括码片上升沿和下降沿的实时码片形状；以及
    累加单元，其配置成对所述信号压缩单元所生成的、用于测量所述输入信号与本地伪随机噪声码的协相关的相关峰的数据进行滑动累加，以获得所述相关峰。
  6. 一种基于GPU并行计算的方法，包括：
    根据即时本地伪随机噪声码的码片边缘生成相应的遮罩信号；
    使用所述即时本地伪随机噪声码对所述遮罩信号与输入信号的乘积进行压缩，生成经压缩信号，并且对所述经压缩信号进行计算以生成用于测量所述输入信号的码片形状的数据；和/或
    根据即时本地伪随机噪声码、超前伪随机噪声码和滞后伪随机噪声码对输入信号进行压缩，生成经压缩信号，并且对所述经压缩信号进行计算，以生成用于测量所述输入信号与本地伪随机噪声码的协相关的相关峰的数据；其中，所述超前伪随机噪声码和所述滞后伪随机噪声码相对于所述即时本地伪随机噪声码分别超前和滞后预定数目的码片。
  7. 根据权利要求6所述的方法，其中，所述预定数目码片包 括1个码片。
  8. 根据权利要求6-7中任一项所述的方法，其中，所述经压缩信号的大小为一个码片，且被划分为多个码片格子；
    其中，生成所述经压缩信号的步骤包括：
    确定所述经压缩信号的属于同一个码片格子的相邻采样点之间的间隔，
    根据所确定的间隔来寻找属于同一个码片格子的全部采样点，以及
    将所述经压缩信号的属于同一个码片格子的全部采样点映射到统一计算设备架构CUDA的一个线程以执行并行计算。
  9. 根据权利要求6所述的方法，其中，根据即时本地伪随机噪声码的码片边缘生成相应的遮罩信号的步骤包括：
    响应于所述即时本地伪随机噪声码的相邻两个码片之间的边缘分别符合(1)为上升沿，(2)为下降沿，(3)保持+1，(4)保持-1，根据所述即时本地伪随机噪声码的码片边缘生成所述遮罩信号，其中所述遮罩信号的两个相邻的半码片的值与所述即时本地伪随机噪声码相一致且其余码片的值为0。
  10. 根据权利要求6所述的方法，进一步包括：
    根据所述信号压缩单元所生成的、用于测量所述输入信号的码片形状的数据，确定所述输入信号的、包括码片上升沿和下降沿的实时码片形状，以及
    对所述信号压缩单元所生成的、用于测量所述输入信号与本地伪随机噪声码的协相关的相关峰的数据进行滑动累加，以获得所述相关峰。
  11. 一种基于GPU并行计算的装置，包括：
    存储器，存储有计算机可执行的指令；以及
    处理器，执行所述指令以实现如权利要求6-10中任一项所述的方法。
  12. 一种存储介质，包括计算机可执行的指令，所述指令被执行时实现权利要求6-10中任一项所述的方法。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060215739A1 (en) * 2005-03-24 2006-09-28 Ian Williamson System and method for making correlation measurements utilizing pulse shape measurements
CN102857251A (zh) * 2012-09-10 2013-01-02 上海交通大学 一种直接序列扩频的并行解扩的码片同步方法
CN106291610A (zh) * 2015-06-12 2017-01-04 北京信息科技大学 一种用于gnss信号压缩捕获处理装置的压缩并行相关模块及其实现方法
CN113466898A (zh) * 2021-07-16 2021-10-01 展讯半导体(成都)有限公司 用于gnss的相关器电路、gnss接收机及其接收信号的方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060215739A1 (en) * 2005-03-24 2006-09-28 Ian Williamson System and method for making correlation measurements utilizing pulse shape measurements
CN102857251A (zh) * 2012-09-10 2013-01-02 上海交通大学 一种直接序列扩频的并行解扩的码片同步方法
CN106291610A (zh) * 2015-06-12 2017-01-04 北京信息科技大学 一种用于gnss信号压缩捕获处理装置的压缩并行相关模块及其实现方法
CN113466898A (zh) * 2021-07-16 2021-10-01 展讯半导体(成都)有限公司 用于gnss的相关器电路、gnss接收机及其接收信号的方法

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