WO2023207376A1 - 时序调整方法和装置、存储介质及电子设备 - Google Patents

时序调整方法和装置、存储介质及电子设备 Download PDF

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Publication number
WO2023207376A1
WO2023207376A1 PCT/CN2023/081226 CN2023081226W WO2023207376A1 WO 2023207376 A1 WO2023207376 A1 WO 2023207376A1 CN 2023081226 W CN2023081226 W CN 2023081226W WO 2023207376 A1 WO2023207376 A1 WO 2023207376A1
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data
sampling
transmission
transmission circuit
edge
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PCT/CN2023/081226
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English (en)
French (fr)
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强鹏
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腾讯科技（深圳）有限公司
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Publication of WO2023207376A1 publication Critical patent/WO2023207376A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals

Definitions

  • the present application relates to the field of computers, and specifically to timing adjustment technology.
  • HBM High-Bandwidth Memory, high-bandwidth memory
  • the data reading and writing speed of HBM devices can reach a maximum bit rate of 3.6GHz.
  • a high operating frequency if data transmission is interfered by noise on the data communication link or crosstalk occurs between data lines, it can easily lead to errors in data reading and writing.
  • High-frequency data reading and data transmission are susceptible to environmental changes in PVT (Process Verification Test, small batch process verification test), as well as the influence of crosstalk between signals, causing the reading data and sampling RDQS signal to deviate, resulting in reading data sampling errors. Case.
  • HBM Host host
  • HBM DRAM Dynamic Random Access Memory
  • HBM DRAM Dynamic Random Access Memory
  • RDQS Read DQ Strobe, read data selection pulse
  • Embodiments of the present application provide a timing adjustment method and device, storage media, and electronic equipment to at least solve the technical problem in related technologies that data signals and sampling signals cannot be aligned, resulting in reading data sampling errors.
  • a timing adjustment method is provided.
  • the method is executed by an electronic device, including: generating a sampling signal in response to an acquired first read instruction, wherein the first read instruction is For reading training data, where the training data is known data represented by N bits, and N is a positive integer greater than or equal to 2; on the sampling edge of the sampling signal, on N transmission circuits
  • the transmitted data signal is sampled to obtain the first sampled data, wherein the data signal transmitted on the N transmission circuits includes the N bits in the training data, and the first sampled data adopts N bits
  • There is a transmission circuit with timing offset in the circuit adjust the transmission delay on the first transmission circuit until the center of the data signal transmitted on the first transmission circuit is aligned with the sampling edge of the sampling signal.
  • a timing adjustment device is also provided.
  • the device is deployed on an electronic device and includes: a generation module configured to generate a sampling signal in response to the acquired first read instruction, wherein , the first read instruction is used to read training data, where the training data is known data represented by N bits, N is a positive integer greater than or equal to 2; the sampling module is used to On the sampling edge of the sampling signal, N transmission circuits The data signals transmitted on the N transmission circuits are sampled to obtain first sampled data, wherein the data signals transmitted on the N transmission circuits include the N bits in the training data, and the first sampled data is obtained by using N bits Data represented by bits; a determination module configured to determine the first transmission circuit among the N transmission circuits based on the value of the same bit in the training data and the first sampling data, the first transmission circuit A transmission circuit with a timing offset among the N transmission circuits; an adjustment module for adjusting the transmission delay on the first transmission circuit until the center of the data signal transmitted on the first transmission circuit is consistent with the
  • a computer-readable storage medium stores a computer program, wherein the computer program is configured to execute the above timing adjustment method when running. .
  • a computer program product includes a computer program, and the computer program is stored in a computer-readable storage medium.
  • the processor of the computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device performs the above timing adjustment method.
  • an electronic device including a memory and a processor.
  • a computer program is stored in the memory, and the processor is configured to execute the above timing adjustment method through the computer program.
  • a sampling signal is generated in response to the obtained first read instruction, where the first read instruction is used to read training data, where the training data is known,
  • the data signals transmitted on N transmission circuits are sampled on the sampling edge of the sampling signal to obtain the first sampled data, where N transmission circuits
  • the data signal transmitted on the Internet includes the N bits in the training data.
  • the first sampled data is data represented by N bits. According to the values of the same bits in the training data and the first sampled data, N transmission circuits are determined.
  • the transmission delay on the first transmission circuit until the center of the data signal transmitted on the first transmission circuit is aligned with the sampling edge of the sampling signal.
  • the offset between the data signal read by the electronic device and the sampling signal can be adjusted to ensure that the sampling signal is aligned to the center of the data signal for reading data, thereby improving the read performance.
  • the technical effect of obtaining data accuracy thereby solves the technical problem in related technologies that the data signal and the sampling signal cannot be aligned, resulting in reading data sampling errors.
  • Figure 1 is a schematic diagram of the application environment of an optional timing adjustment method according to an embodiment of the present application
  • FIG. 2 is a schematic flowchart of an optional timing adjustment method according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of an optional timing adjustment method according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of yet another optional timing adjustment method according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of yet another optional timing adjustment method according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of yet another optional timing adjustment method according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of yet another optional timing adjustment method according to an embodiment of the present application.
  • Figure 8 is a schematic diagram of yet another optional timing adjustment method according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of yet another optional timing adjustment method according to an embodiment of the present application.
  • FIG. 10 is a schematic diagram of yet another optional timing adjustment method according to an embodiment of the present application.
  • FIG 11 is a schematic diagram of yet another optional timing adjustment method according to an embodiment of the present application.
  • Figure 12 is a schematic diagram of yet another optional timing adjustment method according to an embodiment of the present application.
  • Figure 13 is a schematic diagram of yet another optional timing adjustment method according to an embodiment of the present application.
  • Figure 14 is a schematic diagram of yet another optional timing adjustment method according to an embodiment of the present application.
  • Figure 15 is a schematic diagram of yet another optional timing adjustment method according to an embodiment of the present application.
  • Figure 16 is a schematic diagram of yet another optional timing adjustment method according to an embodiment of the present application.
  • Figure 17 is a schematic diagram of yet another optional timing adjustment method according to an embodiment of the present application.
  • Figure 18 is a schematic structural diagram of an optional timing adjustment device according to an embodiment of the present application.
  • Figure 19 is a schematic structural diagram of an optional timing adjustment product according to an embodiment of the present application.
  • Figure 20 is a schematic structural diagram of an optional electronic device according to an embodiment of the present application.
  • HBM High-Bandwidth Memory, high-bandwidth memory.
  • MISR Multiple-input Shift Register, multi-input shift register.
  • Loopback Test Self-loop test.
  • DWORD Data Word, data word.
  • Read Register Mode Read register mode.
  • Training training.
  • RDQS Read DQ Strobe, read data selection pulse.
  • a timing adjustment method is provided.
  • the above timing adjustment method can be applied to the hardware composed of the server 101 and the terminal device 103 as shown in Figure 1 Environment.
  • the server 101 is connected to the terminal device 103 through the network and can be used to provide services for the terminal device or the application program installed on the terminal device.
  • the application program can be a video application, an instant messaging application, Browser applications, educational applications, gaming applications, etc.
  • the database 105 can be set up on the server or independently of the server to provide data storage services for the server 101, for example, a game data storage server.
  • the above-mentioned network can include but is not limited to: a wired network, a wireless network, where the wired network includes: Local area network, metropolitan area network and wide area network.
  • the wireless network includes: Bluetooth, WIFI and other networks that implement wireless communication.
  • the terminal device 103 can be a terminal configured with an application program, which can include but is not limited to at least one of the following: a mobile phone (such as Android Mobile phones, iOS phones, etc.), laptops, tablets, handheld computers, MID (Mobile Internet Devices, mobile Internet devices), PAD, desktop computers, smart TVs, smart voice interaction devices, smart home appliances, vehicle-mounted terminals, aircraft and other computer equipment , the above-mentioned server can be a single server, a server cluster composed of multiple servers, or a cloud server.
  • the application 107 using the above-mentioned timing adjustment method is displayed through the terminal device 103 or other connected display devices.
  • the above timing adjustment method can be implemented on the terminal device 103 (that is, the electronic device that performs the timing adjustment method can be a terminal device) through the following steps:
  • N is a positive integer greater than or equal to 2;
  • the first sampled data is obtained by sampling the data signals transmitted on the N transmission circuits on the sampling edge of the sampling signal, where the data signals transmitted on the N transmission circuits include the training data.
  • N bits the first sampled data is data represented by N bits;
  • the terminal device 103 determine the first transmission circuit among the N transmission circuits based on the values of the same bits in the training data and the first sampling data.
  • the first transmission circuit is the one with timing offset among the N transmission circuits.
  • the above timing adjustment method can also be implemented by a server (that is, the electronic device that performs the timing adjustment method can be a server), for example, implemented in the server 101 shown in Figure 1; Or it is jointly implemented by a terminal device and a server (that is, the electronic device that performs the timing adjustment method may include a terminal device and a server).
  • the above timing adjustment method includes:
  • S204 sample the data signals transmitted on the N transmission circuits on the sampling edge of the sampling signal to obtain the first sampled data, where the data signals transmitted on the N transmission circuits include N bits in the training data, and the first Sampling data is data represented by N bits;
  • the first transmission circuit is the transmission circuit with timing offset among the N transmission circuits;
  • S208 Adjust the transmission delay on the first transmission circuit until the center of the data signal transmitted on the first transmission circuit is aligned with the sampling edge of the sampling signal.
  • the above timing adjustment method may include but is not limited to being applied in any scenario that requires reading data through electronic devices, such as game applications, live broadcast applications, video production applications, instant messaging applications, transportation applications, artificial intelligence applications, etc. In the process of reading data in application scenarios such as intelligence.
  • the above-mentioned first read instruction may include but is not limited to an instruction sent by the host for reading data.
  • the electronic device as an HBM device as an example
  • the data of the HBM 2E device Read and write speeds can reach bit rates up to 3.6GHz. Since HBM's read and write data will transmit data on both the rising and falling edges of the clock, the actual communication clock frequency of HBM 2E is up to 1.8GHz. At such a high operating frequency, if data transmission is interfered by noise on the data communication link, or crosstalk occurs between data lines, it can easily lead to errors in data reading and writing in high-speed operating mode.
  • the read operation of the HBM device is generally organized in the form of burst.
  • the initiation of the read burst operation is marked by the sending of the READ instruction.
  • Figure 3 is a schematic diagram of an optional timing adjustment method according to an embodiment of the present application, as shown in Figure 3 , among which, after a READ instruction is sent, 8-bit data will be read on both the rising edge and the falling edge.
  • the burst length of HBM's READ instruction is 2 or 4 respectively.
  • HBM DRAM When HBM DRAM receives the READ instruction, HBM DRAM will return read data (DQ), data mask (Data Mask, DM), and data bus inversion (Data Bus Inversion, DBI) to HBM Host.
  • DQ read data
  • Data Mask Data Mask
  • DBI data bus inversion
  • 1.tDQSCK(min/max) the minimum and maximum time range between the rising edge of RDQS_c (or falling edge of RDQS_t) and the rising edge of CK_c (or falling edge of CK_t);
  • 2.tDQSCK describes the time delay between the rising edge of RDQS and the rising edge of CK
  • 3.tQSH describes the time delay for the RDQS signal to remain high
  • 4.tQSL describes the time delay for the RDQS signal to remain low
  • 6.tHZ(min/max) describes the minimum and maximum time range for reading data from a low-impedance state to a high-impedance state
  • 7.tDQSQ describes the time delay between the rising edge of RDQS_t (or the falling edge of RDQS_c) and the reading of DQ, DM and DBI data;
  • 8.tQH Describes the time delay from the rising edge of RDQS_t (or the falling edge of RDQS_c) to reading DQ, DM and DBI data to remain stable.
  • Figure 5 is a schematic diagram of another optional timing adjustment method according to an embodiment of the present application. If HBM DRAM adopts a length of BL (Burst Length) of 2, the read data output timing is shown in Figure 5. From Figure 5 It can be seen that data reading lasts for two consecutive cycles.
  • BL Band Length
  • Figure 6 is a schematic diagram of another optional timing adjustment method according to an embodiment of the present application. If HBM DRAM adopts a BL (Burst Length) length of 4, the read data output timing is shown in Figure 6. As can be seen from Figure 6, data reading lasts for four consecutive cycles.
  • BL Band Length
  • sampling signals may include, but is not limited to, assembling corresponding sampling clocks with differential clock signals corresponding to CK_c or CK_t according to different services. That is, different sampling signals may include, but is not limited to, according to the above-mentioned differential clock signals. Clock signal generation.
  • Figure 7 is a schematic diagram of another optional timing adjustment method according to an embodiment of the present application. As shown in Figure 7, taking a read operation by HBM as an example, it may include but is not limited to the following steps:
  • HBM DRAM When HBM Host initiates a read operation to HBM DRAM, HBM DRAM will return the read data to HBM Host. At the same time, HBM DRAM will also return the RDQS (Read Data Selection Pulse) signal that matches the read data to HBM Host.
  • ACT is a one-time activation command
  • PRE is a one-time precharge command. HBM HOST will use this signal as the sampling signal to sample the read data. Therefore, if it can be ensured that the sampling signal RDQS can be aligned to the center of the read data, the sampling accuracy will be the highest.
  • the above-mentioned training data is known and may include but is not limited to pre-configured data for training read data pins.
  • the training data may include but is not limited to data represented by N bits, for example, Including training data generated by 128-bit DQ, 16-bit DM and 16-bit DBI paths.
  • the sampling edge of the above-mentioned sampling signal may include but is not limited to the rising edge or falling edge of the sampling signal
  • the data signal transmitted on the N transmission circuits may include, but is not limited to, data represented by N bits.
  • each transmission circuit transmits data represented by one bit.
  • the above-mentioned sampling of data signals transmitted on N transmission circuits may include but is not limited to when the read data is returned, selecting the pulse signal by returning the read data that matches the read data, To implement sampling of the data signal to obtain the above-mentioned first sampling data.
  • the data signals transmitted on the above-mentioned N transmission circuits include N bits in the training data. It can be understood that each bit of training data is transmitted as a data signal on the corresponding transmission circuit to be read through the N transmission circuits. Take the training data represented by N bits.
  • the above-mentioned first sampling data is data represented by N bits, which means that the above-mentioned first sampling data is regarded as the data to be read by the above-mentioned first read command.
  • the values of the same bits in the training data and the first sampled data can be understood as the transmission of corresponding bits on each transmission channel during the transmission of N-bit data signals on N transmission circuits.
  • the training data is known, and it is judged whether the data signal transmitted by the first sampled data on the N transmission circuits is the same as the value of the training data.
  • the training data can be configured to transmit "1" as the value of the data signal on all N transmission circuits, and determine whether the value of the data signal transmitted by the first sampled data on the N transmission circuits is equal to 1, and then , the transmission circuit whose value of the data signal transmitted on the N transmission circuits is not equal to 1 is determined as the first transmission circuit.
  • Figure 8 is a schematic diagram of another optional timing adjustment method according to an embodiment of the present application. As shown in Figure 8, taking a read operation by HBM as an example, it may include but is not limited to the following steps:
  • FIG 8 shows the use of CLK to sample Data.
  • CLK is the RDQS signal returned by the HBM DRAM.
  • Data contains the DQ, DM and DBI data returned by the HBM DRAM.
  • the sampling edge of CLK is located at the data center of Data. At this time, the sampling accuracy is the highest.
  • the read data and sampling RDQS signals are not aligned and are offset from the data center.
  • the transmission circuit corresponding to the above-mentioned II and III can be determined as the above-mentioned first transmission circuit.
  • the above-mentioned adjustment of the transmission delay on the first transmission circuit may include, but is not limited to, adding a delay circuit to the first transmission circuit.
  • the delay circuit may be, for example, an inverter circuit.
  • the above until the center of the data signal transmitted on the first transmission circuit is aligned with the sampling edge of the sampling signal can be understood to mean that the center of the data signal transmitted on the first transmission circuit and the sampling edge of the sampling signal are both as shown in FIG. As shown in I of 8, the sampling edge of CLK is located at the center of the data signal of Data.
  • a sampling signal is generated in response to the obtained first read instruction, where the first read instruction is used to read training data, where the training data is known,
  • the data signals transmitted on N transmission circuits are sampled on the sampling edge of the sampling signal to obtain the first sampled data, where N transmission circuits
  • the data signal transmitted on the Internet includes the N bits in the training data.
  • the first sampled data is data represented by N bits. According to the values of the same bits in the training data and the first sampled data, N transmission circuits are determined.
  • the transmission delay on the first transmission circuit until the center of the data signal transmitted on the first transmission circuit is aligned with the sampling edge of the sampling signal.
  • the offset between the data signal read by the electronic device and the sampling signal can be adjusted to ensure that the sampling signal is aligned to the center of the data signal for reading data, thereby improving the read performance.
  • the technical effect of obtaining data accuracy thereby solves the technical problem in related technologies that the data signal and the sampling signal cannot be aligned, resulting in reading data sampling errors.
  • the first transmission circuit among the N transmission circuits is determined based on the value of the same bit in the training data and the first sampled data, including:
  • M is greater than or equal to 1, and less than or equal to N.
  • the above determination of whether the values of the same bits in the training data and the first sampled data are the same may include but is not limited to determining whether the value of bit1 of the training data is the same as the value of bit1 of the first sampled data. , if they are the same, it is considered that there is no timing offset in the transmission circuit where bit1 is located. If they are different, it is considered that there is a timing offset in the transmission circuit where bit1 is located, and the transmission circuit where it is located can be determined as the first transmission circuit, and so on, bit2, Bit3,...,bitN all perform the above determination.
  • the presence of M bits with different values among the N bits can be understood as the presence of M transmission circuits among the N transmission circuits, which are the first transmission circuits with timing offsets.
  • the first transmission circuit with timing offset can be determined relatively accurately, so that the timing offset can be adjusted in time to improve the accuracy of reading data.
  • adjusting the transmission delay on the first transmission circuit until the center of the data signal transmitted on the first transmission circuit is aligned with the sampling edge of the sampling signal includes:
  • the above-mentioned first round of adjustment may include but is not limited to aligning the center of the data signal transmitted on each of the N transmission circuits with one sampling edge of the sampling signal, that is, N The center of the data signal transmitted on each transmission circuit in the transmission circuit is aligned with the same or different sampling edge respectively.
  • FIG 9 is a schematic diagram of another optional timing adjustment method according to an embodiment of the present application.
  • clock is a sampling signal, including multiple sampling edges (sampling edge 902, sampling edge 904, sampling edge edge 906), where the centers of the data signals of bit0 and biti are not aligned with the sampling edge 904, and the centers of the data signals of bit1 and bitj are aligned with the sampling edge 904.
  • sampling edge 902, sampling edge 904, sampling edge edge 906 multiple sampling edges
  • the centers of the data signals of bit0 and biti are not aligned with the sampling edge 904, and the centers of the data signals of bit1 and bitj are aligned with the sampling edge 904.
  • the above-mentioned step of bit0 and biti needs to be performed.
  • One round of adjustment is performed so that the centers of the data signals of bit0 and biti are aligned with at least one of the sampling edges 902, 904, and 906.
  • the above-mentioned second round of adjustment may include but is not limited to first determining the target sampling edge, and then moving the center of the data signal transmitted on the second transmission circuit that is not aligned with the target sampling edge to be aligned with the target sampling edge.
  • the method of moving the center of the data signal transmitted on the second transmission circuit to be aligned with the target sampling edge may be to increase the delay unit corresponding to the duration of one sampling period, and divide the target sampling edge from the target sampling edge. The center of the data signal aligned with sampling edges other than the sampling edge is moved to align with the target sampling edge.
  • the centers of the data signals of bit1 and bitj are aligned with the sampling edge 904.
  • the centers of the data signals of bit0 and biti are aligned with the sampling edge 902 and the sampling edge 906 respectively.
  • bit0 and biti are also aligned with the sampling edge 904, until the center of the data signal transmitted on each of the N transmission circuits is aligned with Samples are aligned along 904.
  • the result will be The obtained N transmission circuits are determined as N target transmission circuits.
  • the read data pins can be trained before the initial operation of the HBM chip, which can ensure that the back-end timing does not converge and the sampling of the chip read data path caused by the production failure of the HBM chip can be avoided during the initial operation of the chip. Error to ensure the stability of the read data path when the chip initially works; when the HBM chip detects significant drift in the PVT, the software can configure the chip to train the read data pins to ensure that the chip will not read data due to PVT drift.
  • the automatic training method implemented by hardware circuit is adopted.
  • the entire training process can be completed using software configuration registers. That is, the value of the Step counter can be manually configured using the software configuration register, and the Host can be configured to send read data instructions and the configuration of the MR7 register.
  • the software can independently initiate each step of a single-step training on read data.
  • perform a first round of adjustment on the transmission delay on the first transmission circuit until the center of the data signal transmitted on each of the N transmission circuits is aligned with one sampling edge of the sampling signal include:
  • each first transmission circuit among the N transmission circuits, where each first transmission circuit is the current transmission circuit when performing the following operations:
  • the first edge of the target time window is determined as the first position
  • the second edge of the target time window is determined as the second position
  • the target time window is The time window in which the data signal transmitted on the current transmission circuit is located
  • the target time window is adjusted according to the first delay amount and the second delay amount, so that the center of the data signal currently transmitted on the transmission circuit is aligned with the sampling edge of the sampling signal.
  • the data signal transmitted on the current transmission circuit corresponding to the high level of the sampling signal may include, but is not limited to, any part of the time window in which the data signal is located coincides with the high level interval of the sampling signal.
  • Figure 10 is a schematic diagram of another optional timing adjustment method according to an embodiment of the present application.
  • the partial area corresponding to the left edge of the time window of the data signal in (1) to point A corresponds to the sampling The high level interval of the signal coincides.
  • the data signal is considered to correspond to the high level of the sampling signal.
  • All areas corresponding to the left edge to the right edge of the time window of the data signal in (2) are consistent with the high level of the sampling signal.
  • the flat intervals do not overlap.
  • the data signal is considered to correspond to the low level of the sampling signal.
  • the above time window can be used as the target time window, the rising edge of the target time window can be determined as the first edge, and the right rising edge of the target time window can be determined as the second edge.
  • the above first position is The initial position of the above-mentioned left edge, the above-mentioned second position is the initial position of the above-mentioned right edge;
  • the above-mentioned increase in the transmission delay on the current transmission circuit may include, but is not limited to, increasing the delay circuit on the current transmission circuit to increase the transmission delay.
  • the above-mentioned reduction in the transmission delay on the current transmission circuit may include, but is not limited to Reduce the delay circuit on the current transmission circuit to achieve lower transmission delay.
  • moving the first edge from the first position to the target position may include but is not limited to adding a delay circuit to move the time window in which the data signal transmitted on the current transmission circuit is located backward until the time window The left edge of is aligned with the sampling edge of the sampling signal.
  • the above-mentioned second edge can be moved from the second position to the target position. This includes but is not limited to reducing the delay circuit, so that the time window in which the data signal transmitted on the current transmission circuit is moved forward until the right edge of the time window is aligned with the sampling edge of the sampling signal.
  • the delay circuit amount increased by the first edge moving from the first position to the target position is the first delay amount
  • the delay circuit amount decreased by the second edge moving from the second position to the target position is the second delay amount. Amount of delay.
  • the above-mentioned adjustment of the target time window according to the first delay amount and the second delay amount so that the center of the data signal transmitted on the current transmission circuit is aligned with the sampling edge of the sampling signal may include but is not limited to adjusting the first delay amount.
  • Half of the sum of the amount and the second delay amount is used as the transmission delay that needs to be adjusted to align the center of the data signal transmitted on the current transmission circuit with the sampling edge of the sampling signal.
  • the center of the data signal currently transmitted on the transmission circuit is aligned with the sampling edge of the sampling signal.
  • Figure 11 is a schematic diagram of another optional timing adjustment method according to an embodiment of the present application.
  • the bit of the read data (corresponding to the aforementioned current transmission circuit ) is phase 0.
  • the value of the bit read back should be 1 (corresponding to the high level of the aforementioned data signal transmitted on the current transmission circuit corresponding to the sampling signal).
  • the Step Counter By adjusting the Step Counter, the circuit delay of this bit is continuously increased.
  • the value of the bit read back should be 0 (corresponding to the aforementioned target position).
  • the value of the Step Counter is recorded as R_CNT (corresponding to the aforementioned target position). first delay amount).
  • Step Counter L_CNT (corresponding to the aforementioned second delay amount).
  • this bit can achieve the purpose of edge alignment between the edge of the sampling clock and the time window of the data signal.
  • the transmission delay on the second transmission circuit is until the center of the data signal transmitted on each of the N transmission circuits is aligned with the target sampling edge, including:
  • the second group of sampling edges in the sampling signal except the current sampling edge is closed through clock gating, and the current sampling edge is retained, where the second group of sampling edges includes the target sampling edge, and the current sampling edge is The sampling edge is different from the target sampling edge;
  • the transmission delay on the transmission circuit that transmits the target data signal is adjusted, wherein the center of the target data signal is aligned with the current sampling edge before adjustment, and is aligned with the current sampling edge after adjustment.
  • the current sampling edge is updated to the sampling edge in the sampling signal that has not been retained by the clock gating.
  • the above-mentioned clock gating can be an important means to reduce the power consumption of the microprocessor.
  • one or more sampling periods of the sampling signal can be turned off. , to close the sampling edges that need to be closed and retain the sampling edges that need to be retained.
  • each data signal in the above-mentioned first group of data signals is a data signal whose center is aligned with a sampling edge, but is not aligned with the target sampling edge.
  • the second set of sampling edges in the sampling signal except the current sampling edge can be closed through clock gating, retaining the current sampling edge, and also closing the target sampling edge to find the third Whether a set of data signals are all aligned with the current sampling edge, the data signal aligned with the current sampling edge is used as the target data signal to adjust the transmission delay, so that the adjusted data signal is not aligned with the current sampling edge, but aligned with the target sampling edge .
  • each data signal in the above-mentioned second group of data signals is a data signal whose center is not aligned with the current sampling edge, nor with the target sampling edge.
  • the sampling edge that has not been retained by the clock gating continues to determine whether the first group of data signals exists in the second group of data signals, and the data signal aligned with the current sampling edge is used as the target data signal to adjust the transmission delay.
  • Figure 12 is a schematic diagram of another optional timing adjustment method according to an embodiment of the present application.
  • a in Figure 12 represents the center and target sampling edge of the data signal in the N transmission circuits. Multiple aligned transmission circuits.
  • B in Figure 12 indicates that the first group of sampling edges except the target sampling edge is closed through clock gating, and the target sampling edge is retained. According to whether the center of the data signal transmitted on the N transmission circuits is consistent with The target sampling edge is aligned to determine whether there is a first group of data signals that are not aligned with the target sampling edge among the data signals transmitted on the N transmission circuits.
  • C in Figure 12 indicates that in the case of the first group of data signals, by Clock gating closes the second group of sampling edges in the sampling signal except the current sampling edge, retaining the current sampling edge. According to whether the center of the first group of data signals is aligned with the current sampling edge, there is target data in the first group of data signals. In the case of a signal, the transmission delay on the transmission circuit that transmits the target data signal is adjusted.
  • updating the current sampling edge to the sampling edge in the sampling signal that has not been retained by clock gating can be understood as updating the current sampling edge to the latest one first.
  • adjust the transmission delay on the first transmission circuit until the center of the data signal transmitted on the first transmission circuit is aligned with the sampling edge of the sampling signal including:
  • a delay control unit is provided on each transmission path in the transmission circuit.
  • the delay control unit includes a preset number of delay units connected in series. Each delay unit is used to adjust the transmission delay on the transmission circuit by unit time.
  • the delay control unit may include but is not limited to a delay control circuit implementation.
  • the delay control circuit may support dynamic adjustment of the delay circuit on the read data transmission path, and support the increase or decrease of the delay circuit on the read data path. Delay. A delay circuit for adjusting the bit path delay is added to each read data bit on the read data transmission path.
  • Figure 13 is a schematic diagram of another optional timing adjustment method according to an embodiment of the present application.
  • the read data path includes a 128-bit DQ, a 16-bit DM and a 16-bit DBI path.
  • the DE is The delay unit (Delay Element) unit can include 128 DEs, and each DE contains 4 inverter circuits. Each DE of the delay control unit includes a tap interface (corresponding to the aforementioned output position).
  • Figure 14 is a schematic diagram of another optional timing adjustment method according to an embodiment of the present application, as shown in Figure 14. Step Counter can be used to control the value of the read data bit to be taken out of a certain tap outlet. Therefore, the purpose of adjusting the path delay of the read data can be achieved, that is, the relative position of the read data and the RDQS sampling edge can be moved and adjusted.
  • FIG 15 is a schematic diagram of another optional timing adjustment method according to an embodiment of the present application.
  • the HBM Host includes HBM mode configuration, a read command sending unit, and a read data
  • the path delay control circuit and the four-part circuit of the read data training unit is responsible for controlling the remaining three modules, comparing the read data, and completing the entire data reading training process.
  • N target transmission circuits can be obtained, in which the center of the data signal transmitted on each of the N target transmission circuits is Aligned with the sampling edge of the sampled signal.
  • the data signals transmitted on the N target transmission circuits can be sampled on the sampling edge of the sampling signal to obtain the second sampled data, where the second read instruction Used to read target data, where the target data is unknown data represented by N bits, the data signals transmitted on the N target transmission circuits include the N bits in the target data, and the second sampled data is Data represented by N bits.
  • the above-mentioned N target transmission circuits are Can be used to transfer unknown target data.
  • a second read instruction can also be sent, in which the memory is divided into multiple double-byte registers, and the second read instruction is used to pass N targets
  • the transfer circuit reads the target data in the target double-byte register among the plurality of double-byte registers.
  • the above-mentioned memory may include but is not limited to HBM memory
  • the above-mentioned second read instruction is used to read the target data
  • the HBM mode configuration unit is used to configure the DWORD MISR circuit to the DWORD read register mode (corresponding to the aforementioned read Register mode)
  • this configuration is completed by configuring the mode register MR7 of HBM.
  • Figure 16 is a schematic diagram of another optional timing adjustment method according to an embodiment of the present application.
  • the specific mode of MR7 is shown in Figure 16.
  • the steps for configuring HBM DWORD to read register mode are as follows:
  • OP0 bit is 1, indicating that the DWORD Loopback mode is enabled
  • OP[2:1] is 2'b01, indicating that the value in the MISR register is read, because the value is changed in step 1 reset, so the The value is 0xAAAAh
  • OP[5:3] is 3'b010, which configures the DWORD register to read or write register mode.
  • the remaining bits are default values;
  • HBM DRAM has been configured in DWORD read register mode, and the value in the DWORD register (corresponding to the aforementioned target data) can be read by sending a read command.
  • the above N can have different values.
  • the data signals transmitted on the N target transmission circuits may be different.
  • the value of N can be 160.
  • the data signals transmitted on the 160 target transmission circuits can include a 128-bit memory read data bus signal, a 16-bit read data mask signal and a 16-bit read data mask signal. Bit data bus toggle signal.
  • the 128-bit memory read data bus signal transmitted on the above-mentioned 160 target transmission circuits may include, but is not limited to, a 128-bit DQ signal
  • the 16-bit read data mask signal may include, but is not limited to, a 16-bit DQ signal
  • the DBI signal and the 16-bit data bus flip signal may include but are not limited to the 16-bit DM signal.
  • the 128-bit DWORD of the HBM data path is designed by dividing it into DWORD0, DWORD1, DWORD2 and DWORD3. In each DWORD, according to the width of the MISR algorithm, it is divided into Byte0, Byte1, Byte2 and Byte3. 4 data units for comparison.
  • Figure 17 is a schematic diagram of another optional timing adjustment method according to an embodiment of the present application.
  • each Byte from the 19th bit to the 0th bit are the falling edge data of DBI and the Rising edge data, the falling edge data and rising edge data of each bit of 8bit DQ and the falling edge data and DM rising edge data of DM.
  • the Byte in each DWORD (such as DWORD0, DWORD1, DWORD2, DWORD3) contains A 20-bit value. When the DWORD register is reset, the value will become 0xAAAAh.
  • the read command sending unit is responsible for sending read commands to HBM DRAM.
  • adjust the transmission delay on the first transmission circuit until the center of the data signal transmitted on the first transmission circuit is aligned with the sampling edge of the sampling signal including:
  • the transmission delay on the first transmission circuit is adjusted until the center of the data signal transmitted on the first transmission circuit is aligned with the falling edge of the sampling signal.
  • the above-mentioned sampling edges may include but are not limited to rising edges and falling edges.
  • Data sampling and reading may be implemented through either rising edge or falling edge, or both rising edges may be used at the same time. and the falling edge to implement data sampling and reading.
  • adjust the transmission delay on the first transmission circuit until the center of the data signal transmitted on the first transmission circuit is aligned with the sampling edge of the sampling signal including:
  • a timing adjustment device for implementing the above timing adjustment method is also provided. As shown in Figure 18, the device includes:
  • Generating module 1802 configured to generate a sampling signal in response to the obtained first read instruction, where the first read instruction is used to read training data, where the training data is known and uses N bits
  • N is a positive integer greater than or equal to 2;
  • the sampling module 1804 is used to sample the data signals transmitted on the N transmission circuits on the sampling edge of the sampling signal to obtain the first sampled data, wherein the data signals transmitted on the N transmission circuits include the The N bits in the training data, the first sampled data are data represented by N bits;
  • Determining module 1806, configured to determine the first transmission circuit among the N transmission circuits according to the value of the same bit in the training data and the first sampling data, and the first transmission circuit is the N A transmission circuit with timing offset in a transmission circuit;
  • the adjustment module 1808 is used to adjust the transmission delay on the first transmission circuit until the center of the data signal transmitted on the first transmission circuit is aligned with the sampling edge of the sampling signal.
  • the device is configured to determine the first transmission circuit among the N transmission circuits based on the values of the same bits in the training data and the first sampled data in the following manner: Determine whether the values of the same bits in the training data and the first sampled data are the same; if there are M bits with different values among the N bits, transmit M of the N transmission circuits The circuit is determined as the first transmission circuit, wherein the M transmission circuits are used to transmit data signals corresponding to the M bits, M is greater than or equal to 1, and is less than or equal to N.
  • the device is configured to adjust the transmission delay on the first transmission circuit in the following manner until the center of the data signal transmitted on the first transmission circuit is consistent with the sampling edge of the sampling signal Alignment:
  • the device is configured to perform a first round of adjustment on the transmission delay on the first transmission circuit in the following manner until the data signal transmitted on each of the N transmission circuits is The centers of are aligned with one sampling edge of the sampling signal:
  • each first transmission circuit is the current transmission circuit when performing the following operations:
  • the first edge of the target time window is determined as the first position, and the second edge of the target time window is determined as the second position. position, the target time window is the time window in which the data signal transmitted on the current transmission circuit is located;
  • the target time window is adjusted according to the first delay amount and the second delay amount, so that the center of the data signal transmitted on the current transmission circuit is aligned with the sampling edge of the sampling signal.
  • the device is used in the following manner if among the N transmission circuits obtained after performing the first round of adjustment, there is a second transmission circuit whose transmitted data signal is not aligned with the target sampling edge, A second round of adjustment is performed on the transmission delay on the second transmission circuit until the center of the data signal transmitted on each of the N transmission circuits is aligned with the target sampling edge:
  • the second group of sampling edges in the sampling signal except the current sampling edge is turned off through the clock gating, and the current sampling edge is retained, wherein the The two sets of sampling edges include the target sampling edge, and the current sampling edge is different from the target sampling edge;
  • the transmission delay on the transmission circuit that transmits the target data signal is adjusted, wherein the center of the target data signal is before adjustment and the current
  • the sampling edge is aligned and aligned with the target sampling edge after adjustment;
  • the current sampling edge is updated to a sampling edge in the sampling signal that has not been retained by the clock gating.
  • the device is configured to adjust the transmission delay on the first transmission circuit in the following manner until the center of the data signal transmitted on the first transmission circuit is consistent with the sampling edge of the sampling signal Alignment:
  • the delay control unit includes a preset number of delay units connected in series, and each delay unit is The transmission delay on the transmission circuit is adjusted by unit time.
  • the device is also used for:
  • N target transmission circuits are obtained, wherein the center of the data signal transmitted on each of the N target transmission circuits is consistent with the sampling signal.
  • the sampling edges are aligned;
  • the data signals transmitted on the N target transmission circuits are sampled on the sampling edge of the sampling signal to obtain second sampled data, wherein the second read instruction is For reading target data, wherein the target data is unknown data represented by N bits, and the data signals transmitted on the N target transmission circuits include the N bits in the target data, so The second sampling data is data represented by N bits.
  • the device is also used for:
  • the second read instruction is sent, wherein the memory is divided into multiple double-byte registers, and the second read instruction is used to read through the N target transmission circuits. Get the target data in a target double-byte register among the plurality of double-byte registers.
  • the value of N is 160.
  • the data signals transmitted on the N target transmission circuits include a 128-bit memory read data bus signal, a 16-bit read data mask signal and 16-bit data. Bus toggle signal.
  • the device is configured to adjust the transmission delay on the first transmission circuit in the following manner until the center of the data signal transmitted on the first transmission circuit is consistent with the sampling edge of the sampling signal Alignment:
  • the transmission delay on the first transmission circuit is adjusted until the center of the data signal transmitted on the first transmission circuit is aligned with the falling edge of the sampling signal.
  • the device is configured to adjust the transmission delay on the first transmission circuit in the following manner until the center of the data signal transmitted on the first transmission circuit is consistent with the sampling edge of the sampling signal Alignment:
  • the transmission delay on the first transmission circuit is adjusted until the sampling edge of the sampling signal is located in a time sub-window corresponding to the data signal transmitted on the first transmission circuit, wherein the time sub-window is the
  • the time window includes a sub-window of the center point.
  • a computer program product includes a computer program containing program code for executing the method shown in the flowchart.
  • the computer program may be downloaded and installed from the network via communications portion 1909, and/or installed from removable media 1911.
  • the central processor 1901 When the computer program is executed by the central processor 1901, various functions provided by the embodiments of the present application are executed.
  • Figure 19 schematically shows a block diagram of a computer system used to implement an electronic device according to an embodiment of the present application.
  • the computer system 1900 includes a central processing unit 1901 (Central Processing Unit, CPU), which can be loaded into a random computer according to a program stored in a read-only memory 1902 (Read-Only Memory, ROM) or from a storage part 1908. Access the program in the memory 1903 (Random Access Memory, RAM) to perform various appropriate actions and processes. In the random access memory 1903, various programs and data required for system operation are also stored.
  • the central processing unit 1901, the read-only memory 1902 and the random access memory 1903 are connected to each other through a bus 1904.
  • the input/output interface 1905 Input/Output interface, ie, I/O interface
  • I/O interface input/output interface
  • the following components are connected to the input/output interface 1905: an input part 1906 including a keyboard, a mouse, etc.; an output part 1907 including a cathode ray tube (Cathode Ray Tube, CRT), a liquid crystal display (Liquid Crystal Display, LCD), etc., and a speaker, etc. ; a storage part 1908 including a hard disk, etc.; and a communication part 1909 including a network interface card such as a LAN card, a modem, etc.
  • the communication section 1909 performs communication processing via a network such as the Internet.
  • Driver 1190 is also connected to input/output interface 1905 as needed.
  • Removable media 1911 such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 1190 as needed, so that a computer program read therefrom is installed into the storage portion 1908 as needed.
  • the processes described in the respective method flow charts may be implemented as computer software programs.
  • embodiments of the present application include a computer program product including a computer program carried on a computer-readable medium, the computer program containing program code for performing the method illustrated in the flowchart.
  • the computer program may be downloaded and installed from the network via communications portion 1909, and/or installed from removable media 1911.
  • the central processor 1901 When the computer program is executed by the central processor 1901, various functions defined in the system of the present application are executed.
  • an electronic device for implementing the above timing adjustment method is also provided.
  • the electronic device may be the terminal device or server shown in Figure 1 .
  • This embodiment is explained by taking the electronic device as a terminal device as an example.
  • the electronic device includes a memory 2002 and a processor 2004.
  • the memory 2002 stores a computer program.
  • the processor 2004 is configured to execute the steps in any of the above method embodiments through the computer program.
  • the above-mentioned electronic device may be located in at least one network device among multiple network devices of the computer network.
  • the above-mentioned processor can be configured to perform the following steps through a computer program:
  • S1 in response to the obtained first read instruction, generate a sampling signal, where the first read instruction is used to read training data, where the training data is known data represented by N bits, and N is greater than or A positive integer equal to 2;
  • the first transmission circuit is the transmission circuit with timing offset among the N transmission circuits;
  • the structure shown in Figure 20 is only illustrative, and the electronic device can also be a smart phone (such as an Android phone, an iOS phone, etc.), a tablet computer, a handheld computer, and a Mobile Internet Devices (MID), PAD and other terminal equipment.
  • FIG. 20 does not limit the structure of the above-mentioned electronic device.
  • the electronic device may also include more or fewer components (such as network interfaces, etc.) than shown in FIG. 20 , or have a different configuration than shown in FIG. 20 .
  • the memory 2002 can be used to store software programs and modules, such as the program instructions/modules corresponding to the timing adjustment method and device in the embodiment of the present application.
  • the processor 2004 executes various software programs and modules by running the software programs and modules stored in the memory 2002. Function application and data processing, that is, to implement the above timing adjustment method.
  • Memory 2002 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory.
  • the memory 2002 may further include memory located remotely relative to the processor 2004, and these remote memories may be connected to the terminal through a network. Examples of the above-mentioned networks include but are not limited to the Internet, intranets, local area networks, mobile communication networks and combinations thereof.
  • the memory 2002 may be specifically, but not limited to, used to store training data, target data and other information.
  • the memory 2002 may include, but is not limited to, the generation module 1802, the sampling module 1804, the determination module 1806 and the adjustment module 1808 in the timing adjustment device.
  • the memory 2002 may also include but is not limited to other module units in the above timing adjustment device, which will not be described again in this example.
  • the above-mentioned transmission device 2006 is used to receive or send data via a network.
  • Specific examples of the above-mentioned network may include wired networks and wireless networks.
  • the transmission device 2006 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices and routers through network cables to communicate with the Internet or a local area network.
  • the transmission device 2006 is a radio frequency (Radio Frequency, RF) module, which is used to communicate with the Internet wirelessly.
  • RF Radio Frequency
  • the above-mentioned electronic device also includes: a display 2008, used to display the above-mentioned data signal; and a connection bus 2010, used to connect various module components in the above-mentioned electronic device.
  • the above-mentioned terminal device or server may be a node in a distributed system, wherein the distributed system may be a blockchain system, and the blockchain system may be composed of multiple nodes communicating through a network.
  • a distributed system formed by formal connections.
  • nodes can form a peer-to-peer (P2P, Peer To Peer) network, and any form of computing equipment, such as servers, terminals and other electronic devices, can become a node in the blockchain system by joining the peer-to-peer network.
  • P2P peer-to-peer
  • computing equipment such as servers, terminals and other electronic devices
  • a computer-readable storage medium is provided.
  • a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, causing the computer device to perform the above timing adjustment aspect. Timing adjustment methods provided in various optional implementations.
  • the program can be stored in a computer-readable storage.
  • storage media can include: flash disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk, etc.
  • the integrated units in the above embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in the above computer-readable storage medium.
  • the technical solution of the present application is essentially or contributes to the existing technology, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, It includes several instructions to cause one or more computer devices (which can be personal computers, servers or network devices, etc.) to execute all or part of the steps of the methods described in various embodiments of this application.
  • the disclosed client can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • multiple units or components may be combined or may be Integrated into another system, or some features can be ignored, or not implemented.
  • the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the units or modules may be in electrical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit.
  • the above integrated units can be implemented in the form of hardware or software functional units.

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Abstract

一种时序调整方法和装置、存储介质及电子设备。其中，该方法包括：响应于获取到的第一读指令，生成采样信号，在采样信号的采样沿上对N个传输电路上传输的数据信号进行采样，得到第一采样数据，根据训练数据和第一采样数据中的相同比特的取值，确定N个传输电路中的第一传输电路，调整第一传输电路上的传输延迟，直到第一传输电路上传输的数据信号的中心与采样信号的采样沿对齐。该方法解决了数据信号与采样信号无法对齐，导致读取数据采样错误的技术问题。

Description

时序调整方法和装置、存储介质及电子设备
本申请要求于2022年4月25日提交中国专利局、申请号202210439634.1、申请名称为“时序调整方法和装置、存储介质及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机领域，具体而言，涉及时序调整技术。
背景技术
根据HBM(High-Bandwidth Memory，高带宽内存)的相关协议，HBM设备的数据读写速度可达到最高3.6GHz的比特率。在这样较高的工作频率下，数据的传输如果受到数据通信链路上的噪声干扰，或者数据线之间出现了串扰，很容易导致数据读写的错误。高频率的数据读取和数据传输容易受PVT(Process Verification Test，小批量过程验证测试)的环境变化，以及信号间串扰的影响导致读数据和采样RDQS信号出现偏移，从而出现读数据采样错误的情况。
例如，当HBM Host(主机)向HBM DRAM(Dynamic Random Access Memory，动态随机存取存储器)发起一次读操作时，HBM DRAM将会返回读数据至HBM Host。同时，HBM DRAM还会向HBM Host返回与读数据相匹配的RDQS(Read DQ Strobe，读数据选取脉冲)信号。HBM host将采用该信号作为采样读数据的采样信号，因此，当读数据和采样RDQS信号不对齐时，会导致读数据的采样错误。
当读取HBM DRAM的数据出现错误时，会影响整个HBM子系统的正确执行，严重时甚至会影响整个芯片的正常工作。
发明内容
本申请实施例提供了一种时序调整方法和装置、存储介质及电子设备，以至少解决相关技术中数据信号与采样信号无法对齐，导致读取数据采样错误的技术问题。
根据本申请实施例的一个方面，提供了一种时序调整方法，所述方法由电子设备执行，包括：响应于获取到的第一读指令，生成采样信号，其中，所述第一读指令用于读取训练数据，其中，所述训练数据是已知的、采用N个比特表示的数据，N为大于或等于2的正整数；在所述采样信号的采样沿上对N个传输电路上传输的数据信号进行采样，得到第一采样数据，其中，所述N个传输电路上传输的数据信号包括所述训练数据中的所述N个比特，所述第一采样数据是采用N个比特表示的数据；根据所述训练数据和所述第一采样数据中的相同比特的取值，确定所述N个传输电路中的第一传输电路，所述第一传输电路为所述N个传输电路中存在时序偏移的传输电路；调整所述第一传输电路上的传输延迟，直到所述第一传输电路上传输的数据信号的中心与所述采样信号的采样沿对齐。
根据本申请实施例的另一方面，还提供了一种时序调整装置，所述装置部署在电子设备上，包括：生成模块，用于响应于获取到的第一读指令，生成采样信号，其中，所述第一读指令用于读取训练数据，其中，所述训练数据是已知的、采用N个比特表示的数据，N为大于或等于2的正整数；采样模块，用于在所述采样信号的采样沿上对N个传输电路 上传输的数据信号进行采样，得到第一采样数据，其中，所述N个传输电路上传输的数据信号包括所述训练数据中的所述N个比特，所述第一采样数据是采用N个比特表示的数据；确定模块，用于根据所述训练数据和所述第一采样数据中的相同比特的取值，确定所述N个传输电路中的第一传输电路，所述第一传输电路为所述N个传输电路中存在时序偏移的传输电路；调整模块，用于调整所述第一传输电路上的传输延迟，直到所述第一传输电路上传输的数据信号的中心与所述采样信号的采样沿对齐。
根据本申请实施例的又一方面，还提供了一种计算机可读的存储介质，该计算机可读的存储介质中存储有计算机程序，其中，该计算机程序被设置为运行时执行上述时序调整方法。
根据本申请实施例的又一方面，提供一种计算机程序产品，该计算机程序产品包括计算机程序，该计算机程序存储在计算机可读存储介质中。计算机设备的处理器从计算机可读存储介质读取该计算机程序，处理器执行该计算机程序，使得该计算机设备执行如以上时序调整方法。
根据本申请实施例的又一方面，还提供了一种电子设备，包括存储器和处理器，上述存储器中存储有计算机程序，上述处理器被设置为通过所述计算机程序执行上述的时序调整方法。
在本申请实施例中，在需要读取数据时，响应于获取到的第一读指令，生成采样信号，其中，第一读指令用于读取训练数据，其中，训练数据是已知的、采用N个比特表示的数据，N为大于或等于2的正整数，在采样信号的采样沿上对N个传输电路上传输的数据信号进行采样，得到第一采样数据，其中，N个传输电路上传输的数据信号包括训练数据中的所述N个比特，第一采样数据是采用N个比特表示的数据，根据训练数据和第一采样数据中的相同比特的取值，确定N个传输电路中存在时序偏移的第一传输电路，调整第一传输电路上的传输延迟，直到第一传输电路上传输的数据信号的中心与采样信号的采样沿对齐。通过进行读数据的管脚训练，可以将电子设备读取的数据信号和采样信号之间的偏移进行调整，达到了保证采样信号对齐至读数据的数据信号中心的目的，从而实现了提高读取数据的准确性的技术效果，进而解决了相关技术中数据信号与采样信号无法对齐，导致读取数据采样错误的技术问题。
附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1是根据本申请实施例的一种可选的时序调整方法的应用环境的示意图；
图2是根据本申请实施例的一种可选的时序调整方法的流程示意图；
图3是根据本申请实施例的一种可选的时序调整方法的示意图；
图4是根据本申请实施例的又一种可选的时序调整方法的示意图；
图5是根据本申请实施例的又一种可选的时序调整方法的示意图；
图6是根据本申请实施例的又一种可选的时序调整方法的示意图；
图7是根据本申请实施例的又一种可选的时序调整方法的示意图；
图8是根据本申请实施例的又一种可选的时序调整方法的示意图；
图9是根据本申请实施例的又一种可选的时序调整方法的示意图；
图10是根据本申请实施例的又一种可选的时序调整方法的示意图；
图11是根据本申请实施例的又一种可选的时序调整方法的示意图；
图12是根据本申请实施例的又一种可选的时序调整方法的示意图；
图13是根据本申请实施例的又一种可选的时序调整方法的示意图；
图14是根据本申请实施例的又一种可选的时序调整方法的示意图；
图15是根据本申请实施例的又一种可选的时序调整方法的示意图；
图16是根据本申请实施例的又一种可选的时序调整方法的示意图；
图17是根据本申请实施例的又一种可选的时序调整方法的示意图；
图18是根据本申请实施例的一种可选的时序调整装置的结构示意图；
图19是根据本申请实施例的一种可选的时序调整产品的结构示意图；
图20是根据本申请实施例的一种可选的电子设备的结构示意图。
具体实施方式
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本申请保护的范围。
需要说明的是，本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
首先，在对本申请实施例进行描述的过程中出现的部分名词或者术语适用于如下解释：
HBM：High-Bandwidth Memory，高带宽内存。
MISR：Multiple-input Shift Register，多输入移位寄存器。
Loopback Test：自环测试。
At Speed：在速工作模式。
DWORD：Data Word，数据字。
Read Register Mode：读寄存器模式。
Training：训练。
RDQS：Read DQ Strobe，读数据选取脉冲。
下面结合实施例对本申请进行说明：
根据本申请实施例的一个方面，提供了一种时序调整方法，在一种可能的实现方式中，上述时序调整方法可以应用于如图1所示的由服务器101和终端设备103所构成的硬件环境中。如图1所示，服务器101通过网络与终端设备103进行连接，可用于为终端设备或终端设备上安装的应用程序提供服务，应用程序可以是视频应用程序、即时通信应用程序、 浏览器应用程序、教育应用程序、游戏应用程序等。可在服务器上或独立于服务器设置数据库105，用于为服务器101提供数据存储服务，例如，游戏数据存储服务器，上述网络可以包括但不限于：有线网络，无线网络，其中，该有线网络包括：局域网、城域网和广域网，该无线网络包括：蓝牙、WIFI及其他实现无线通信的网络，终端设备103可以是配置有应用程序的终端，可以包括但不限于以下至少之一：手机(如Android手机、iOS手机等)、笔记本电脑、平板电脑、掌上电脑、MID(Mobile Internet Devices，移动互联网设备)、PAD、台式电脑、智能电视、智能语音交互设备、智能家电、车载终端、飞行器等计算机设备，上述服务器可以是单一服务器，也可以是由多个服务器组成的服务器集群，或者是云服务器，使用上述时序调整方法的应用程序107通过终端设备103或其他连接的显示设备进行显示。
结合图1所示，上述时序调整方法可以在终端设备103(即执行时序调整方法的电子设备可以是终端设备)通过如下步骤实现：
S1，在终端设备103上响应于获取到的第一读指令，生成采样信号，其中，第一读指令用于读取训练数据，其中，训练数据是已知的、采用N个比特表示的数据，N为大于或等于2的正整数；
S2，在终端设备103上通过在采样信号的采样沿上对N个传输电路上传输的数据信号进行采样，得到第一采样数据，其中，N个传输电路上传输的数据信号包括训练数据中的N个比特，第一采样数据是采用N个比特表示的数据；
S3，在终端设备103上根据训练数据和第一采样数据中的相同比特的取值，确定N个传输电路中的第一传输电路，第一传输电路为N个传输电路中存在时序偏移的传输电路；
S4，在终端设备103上调整第一传输电路上的传输延迟，直到第一传输电路上传输的数据信号的中心与采样信号的采样沿对齐。
在一种可能的实现方式中，在本实施例中，上述时序调整方法还可以通过服务器实现(即执行时序调整方法的电子设备可以是服务器)，例如，图1所示的服务器101中实现；或由终端设备和服务器共同实现(即执行时序调整方法的电子设备可以包括终端设备和服务器)。
上述仅是一种示例，本实施例不做具体的限定。
在一种可能的实现方式中，作为一种可选的实施方式，如图2所示，上述时序调整方法包括：
S202，响应于获取到的第一读指令，生成采样信号，其中，第一读指令用于读取训练数据，其中，训练数据是已知的、采用N个比特表示的数据，N为大于或等于2的正整数；
S204，在采样信号的采样沿上对N个传输电路上传输的数据信号进行采样，得到第一采样数据，其中，N个传输电路上传输的数据信号包括训练数据中的N个比特，第一采样数据是采用N个比特表示的数据；
S206，根据训练数据和第一采样数据中的相同比特的取值，确定N个传输电路中的第一传输电路，第一传输电路为N个传输电路中存在时序偏移的传输电路；
S208，调整第一传输电路上的传输延迟，直到第一传输电路上传输的数据信号的中心与采样信号的采样沿对齐。
在本申请实施例中，上述时序调整方法可以包括但不限于应用于任何需要通过电子设备读取数据的场景中，例如，游戏应用，直播应用，视频制作应用，即时通信应用、交通应用、人工智能等的应用场景的读数据过程中。
在本申请实施例中，上述第一读指令可以包括但不限于由主机发送的用于读取数据的指令，以电子设备是HBM设备为例，根据HBM的相关协议，HBM 2E的设备的数据读写速度可达到最高3.6GHz的比特率。由于HBM的读写数据在时钟的上升沿和下降沿均会传输数据，因此实际的HBM 2E的通信时钟频率最高为1.8GHz。在这样较高的工作频率下，数据的传输如果受到数据通信链路上的噪声干扰，或者数据线之间出现了串扰，很容易导致在速工作模式下的数据读写的错误。
HBM设备的读操作一般以burst的形式组织，读burst操作的发起以READ指令的发送为标志，图3是根据本申请实施例的一种可选的时序调整方法的示意图，如图3所示，其中，一次READ指令的发送后，上升沿和下降沿均会读取8比特数据。HBM的READ指令的突发(burst)长度分别为2或4。
当HBM DRAM接收到READ指令后，HBM DRAM会向HBM Host返回读数据(DQ)，数据掩码(Data Mask，DM)，数据总线翻转(Data Bus Inversion，DBI)，其中，图4是根据本申请实施例的另一种可选的时序调整方法的示意图，HBM DRAM返回数据的格式如图4所示，图4中包含的相关时序参数如下所示：
1.tDQSCK(min/max)：RDQS_c上升沿(或RDQS_t下降沿)与CK_c上升沿(或CK_t下降沿)之间最小和最大的时间范围；
2.tDQSCK：描述了RDQS上升沿与CK上升沿之间的时间延迟；
3.tQSH：描述了RDQS信号持续为高电平的时间延迟；
4.tQSL：描述了RDQS信号持续为低电平的时间延迟；
5.tLZ(min/max)：描述了读数据持续高阻态到低阻抗状态的最小和最大的时间范围；
6.tHZ(min/max)：描述了读数据持续低阻抗状态到高阻态的最小和最大的时间范围；
7.tDQSQ：描述了RDQS_t上升沿(或RDQS_c下降沿)到读出DQ、DM和DBI数据之间的时间延迟；
8.tQH：描述了RDQS_t上升沿(或RDQS_c下降沿)到读出DQ、DM和DBI数据保持稳定的时间延迟。
图5是根据本申请实施例的又一种可选的时序调整方法的示意图，HBM DRAM若采用BL(Burst Length)为2的长度时，读数据输出时序如图5所示，从图5中可以看出，数据读取持续了连续的两个周期。
图6是根据本申请实施例的又一种可选的时序调整方法的示意图，HBM DRAM若采用BL(Burst Length)为4的长度时，读数据输出时序如图6所示。从图6中可以看出，数据读取持续了连续的四个周期。
上述仅是一种示例，本实施例不做任何具体的限定。
在本申请实施例中，上述生成采样信号可以包括但不限于根据不同业务，以CK_c或CK_t对应的差分时钟信号组装对应的采样时钟，也即，不同的采样信号可以包括但不限于根据上述差分时钟信号生成。
图7是根据本申请实施例的又一种可选的时序调整方法的示意图，如图7所示，以HBM进行一次读操作为例，可以包括但不限于如下步骤：
当HBM Host向HBM DRAM发起一次读操作时，HBM DRAM将会返回读数据至HBM Host。同时，HBM DRAM还会向HBM Host返回与读数据相匹配的RDQS(读数据选取脉冲)信号。图6中ACT为一次性激活指令，PRE为一次预充电指令。HBM HOST将采用该信号作为采样读数据的采样信号，因此如果可以保证采样信号RDQS可以对齐至读数据的中心，则采样的准确率是最高的。
上述仅是一种示例，本实施例不做任何具体的限定。
在本申请实施例中，上述训练数据是已知的可以包括但不限于预先配置的用于训练读数据管脚的数据，该训练数据可以包括但不限于采用N个比特表示的数据，例如，包括128bit的DQ、16bit的DM和16bit的DBI路径产生的训练数据。
在本申请实施例中，上述采样信号的采样沿可以包括但不限于采样信号的上升沿或下降沿，N个传输电路上传输的数据信号可以包括但不限于对N个比特表示的数据而言，每个传输电路传输一个比特表示的数据，上述对N个传输电路上传输的数据信号进行采样可以包括但不限于当读数据返回时，通过返回与读数据相匹配的读数据选取脉冲信号，以实现对数据信号进行采样，得到上述第一采样数据。
需要说明的是，上述N个传输电路上传输的数据信号包括训练数据中的N个比特可以理解为每个比特的训练数据作为数据信号传输在对应的传输电路上，以通过N个传输电路读取N个比特表示的训练数据。
在本申请实施例中，上述第一采样数据是采用N个比特表示的数据可以理解为将上述第一采样数据视为上述第一读指令所要读取的数据。
在本申请实施例中，上述训练数据和第一采样数据中的相同比特的取值可以理解为在N个传输电路上传输N个比特的数据信号的过程中，每个传输通道上传输对应比特的数据信号，此时，训练数据是已知的，判断第一采样数据在N个传输电路上传输的数据信号是否与训练数据的取值相同。
例如，可以将训练数据配置为在N个传输电路上均传输“1”作为数据信号的取值，并判断第一采样数据在N个传输电路上传输的数据信号的取值是否等于1，进而，将N个传输电路上传输的数据信号的取值不等于1的传输电路确定为第一传输电路。
图8是根据本申请实施例的又一种可选的时序调整方法的示意图，如图8所示，以HBM进行一次读操作为例，可以包括但不限于如下步骤：
图8示出使用CLK采样Data，在HBM读数据场景中，CLK为HBM DRAM返回的RDQS信号，Data包含了HBM DRAM返回的DQ、DM和DBI数据。在I中，CLK的采样沿位于Data的数据中心位置，此时，采样的准确率最高。在II和III中，出现了读数据和采样RDQS信号不对齐，与数据中心存在偏移的情况。
在II中，时钟采样沿将漂移出读数据窗口；在III中，时钟采样沿虽然未漂移出读数据窗口，但是由于采样沿和数据的建立(或撤销)边沿距离过近，导致本次采样出现setup timing(或hold timing)的时序违例。以上两种情况均会导致读数据的采样错误。
当读取HBM DRAM的数据出现错误时，会影响整个HBM子系统的正确执行，严重时甚至会影响整个芯片的正常工作。
因此，可以将上述II、III对应的传输电路确定为上述第一传输电路。
在本申请实施例中，上述调整第一传输电路上的传输延迟可以包括但不限于通过为第一传输电路添加延迟电路实现，该延迟电路例如可以是反相器电路。
在本申请实施例中，上述直到第一传输电路上传输的数据信号的中心与采样信号的采样沿对齐可以理解为第一传输电路上传输的数据信号的中心与采样信号的采样沿均如图8的I所示，CLK的采样沿位于Data的数据信号的中心。
在本申请实施例中，在需要读取数据时，响应于获取到的第一读指令，生成采样信号，其中，第一读指令用于读取训练数据，其中，训练数据是已知的、采用N个比特表示的数据，N为大于或等于2的正整数，在采样信号的采样沿上对N个传输电路上传输的数据信号进行采样，得到第一采样数据，其中，N个传输电路上传输的数据信号包括训练数据中的所述N个比特，第一采样数据是采用N个比特表示的数据，根据训练数据和第一采样数据中的相同比特的取值，确定N个传输电路中存在时序偏移的第一传输电路，调整第一传输电路上的传输延迟，直到第一传输电路上传输的数据信号的中心与采样信号的采样沿对齐。通过进行读数据的管脚训练，可以将电子设备读取的数据信号和采样信号之间的偏移进行调整，达到了保证采样信号对齐至读数据的数据信号中心的目的，从而实现了提高读取数据的准确性的技术效果，进而解决了相关技术中数据信号与采样信号无法对齐，导致读取数据采样错误的技术问题。
在一种可能的实现方式中，根据训练数据和第一采样数据中的相同比特的取值，确定N个传输电路中的第一传输电路，包括：
S1，确定训练数据和第一采样数据中的相同比特的取值是否相同；
S2，若N个比特中存在取值不同的M个比特，将N个传输电路中的M个传输电路确定为第一传输电路，其中，M个传输电路用于传输M个比特对应的数据信号，M大于或等于1，且小于或等于N。
在本申请实施例中，上述确定训练数据和第一采样数据中的相同比特的取值是否相同可以包括但不限于确定训练数据的bit1的取值与第一采样数据的bit1的取值是否相同，如果相同则认为bit1所在的传输电路不存在时序偏移，如果不同则认为bit1所在的传输电路存在时序偏移，可以将其所在的传输电路确定为第一传输电路，以此类推，bit2、bit3、…、bitN均执行上述判定。
在本申请实施例中，上述在N个比特中存在取值不同的M个比特可以理解为N个传输电路中存在M个传输电路是存在时序偏移的第一传输电路。
通过上述方式，可以较为准确的确定出存在时序偏移的第一传输电路，以便及时对其存在的时序偏移进行调整，提高读取数据的准确性。
在一种可能的实现方式中，调整第一传输电路上的传输延迟，直到第一传输电路上传输的数据信号的中心与采样信号的采样沿对齐，包括：
S1，对第一传输电路上的传输延迟进行第一轮调整，直到N个传输电路中每个传输电路上传输的数据信号的中心分别与采样信号的一个采样沿对齐；
S2，若执行完第一轮调整后得到的N个传输电路中存在传输的数据信号未与目标采样沿对齐的第二传输电路，对第二传输电路上的传输延迟进行第二轮调整，直到N个传输电路中每个传输电路上传输的数据信号的中心均与目标采样沿对齐，其中，在所有采样沿中目标采样沿与N个传输电路上传输的数据信号的中心对齐的次数最多。
在本申请实施例中，上述第一轮调整可以包括但不限于将N个传输电路中的每个传输电路上传输的数据信号的中心分别与采样信号的一个采样沿对齐，也即，N个传输电路中的每个传输电路上传输的数据信号的中心分别与相同或者不同的一个采样沿对齐。
例如，图9是根据本申请实施例的又一种可选的时序调整方法的示意图，如图9所示，clock即为采样信号，包括多个采样沿(采样沿902、采样沿904、采样沿906)，其中，bit0与biti的数据信号的中心均未与采样沿904对齐，而bit1与bitj的数据信号的中心均与采样沿904对齐，此时，则需要对bit0和biti进行上述第一轮调整，以使得bit0和biti的数据信号的中心至少与采样沿902、采样沿904、采样沿906中任一个采样沿对齐。
在本申请实施例中，上述第二轮调整可以包括但不限于先确定目标采样沿，再将不与目标采样沿对齐的第二传输电路上传输的数据信号的中心移动至与目标采样沿对齐。在一种可能的实现方式中，将第二传输电路上传输的数据信号的中心移动至与目标采样沿对齐的方式可以是采用增加与一个采样周期对应时长的延迟单元的方式，将与除目标采样沿之外的其他采样沿对齐的数据信号的中心移动至与目标采样沿对齐。
例如，以图9为例，bit1与bitj的数据信号的中心均与采样沿904对齐，bit0和biti的数据信号的中心在进行第一轮调整后，分别与采样沿902和采样沿906对齐，此时，通过调整bit0和biti对应的数据信号的传输电路的传输延迟，使得bit0和biti也与采样沿904对齐，直到N个传输电路中的每个传输电路上传输的数据信号的中心均与采样沿904对齐。
在本申请实施例中，若执行完第一轮调整后得到的N个传输电路中每个传输电路上传输的数据信号的中心均与目标采样沿对齐，将执行完所述第一轮调整后得到的N个传输电路确定为N个目标传输电路。
通过多轮调整可以保证调整后的每个传输电路上传输的数据信号的中心均与目标采样沿对齐，提高了调整效果，解决了相关技术中数据信号与采样信号无法对齐，导致读取数据采样错误的技术问题。
通过本申请实施例，可在HBM芯片初始工作前，对读数据管脚进行训练，则可以保证芯片初始工作时，避免出现后端时序不收敛以及HBM芯片的生产故障造成芯片读数据通路的采样错误，保证芯片初始工作时，读数据通路的稳定性；可在HBM芯片检测到PVT有明显漂移时，软件配置芯片对读数据管脚进行训练，保证芯片不会因PVT的漂移造成芯片读数据通路的传输数据错误；可使用硬件中包含的定期读数据训练的机制，定期的对HBM芯片进行读数据训练，保证芯片不会在工作过程中出现读数据的采样错误；支持软件 配置的单步读数据训练，因此也可以由软件单独配置完成对整个芯片进行读数据训练。由于软件可以在系统不忙时完成该动作，则可以在保证读数据管脚不会出现采样错误的基础上，同时保证整个系统的效率。
在本申请中，采用了硬件电路实现的自动训练方式。除此方法之外，训练的整个过程可以使用软件配置寄存器的方式来完成，即使用软件配置的寄存器可以手动配置Step counter的数值，且可以配置Host发送读数据指令和MR7寄存器的配置，对HBM DRAM接收到的读数据的内容进行读取和校验。因此，软件可以独立的发起对读数据进行单步的训练的每个步骤。
作为一种可选的方案，对第一传输电路上的传输延迟进行第一轮调整，直到N个传输电路中每个传输电路上传输的数据信号的中心分别与采样信号的一个采样沿对齐，包括：
对N个传输电路中的每个第一传输电路执行以下操作，其中，在执行以下操作时，每个第一传输电路为当前传输电路：
若当前传输电路上传输的数据信号对应于采样信号的高电平，将目标时间窗口的第一边沿确定为第一位置，将目标时间窗口的第二边沿确定为第二位置，目标时间窗口为当前传输电路上传输的数据信号所在的时间窗口；
增加当前传输电路上的传输延迟，直到第一边沿由第一位置移动至目标位置，确定当前传输电路上增加的传输延迟的第一延迟量，其中，目标位置对应于采样信号的采样沿；
降低当前传输电路降低传输延迟，直到第二边沿由第二位置移动至目标位置，确定当前传输电路上降低的传输延迟的第二延迟量；
根据第一延迟量和第二延迟量调整目标时间窗口，使得当前传输电路上传输的数据信号的中心与采样信号的采样沿对齐。
在本申请实施例中，上述当前传输电路上传输的数据信号对应于采样信号的高电平可以包括但不限于数据信号所在的时间窗口的任意部分与采样信号的高电平区间重合。
例如，图10是根据本申请实施例的又一种可选的时序调整方法的示意图，如图10所示，(1)中数据信号的时间窗口的左边沿至A点对应的部分区域与采样信号的高电平区间重合，此时，认为该数据信号对应于采样信号的高电平，(2)中数据信号的时间窗口的左边沿至右边沿对应的全部区域均与采样信号的高电平区间未重合，此时，认为该数据信号对应于采样信号的低电平。
在本申请实施例中，可以将上述时间窗口作为目标时间窗口，将目标时间窗口的上升沿确定为第一边沿，将目标时间窗口的右升沿确定为第二边沿，上述第一位置即为上述左边沿的初始位置，上述第二位置即为上述右边沿的初始位置；
在本申请实施例中，上述增加当前传输电路上的传输延迟可以包括但不限于增加当前传输电路上的延迟电路，以实现增加传输延迟，上述降低当前传输电路上的传输延迟可以包括但不限于降低当前传输电路上的延迟电路，以实现降低传输延迟。
在本申请实施例中，上述第一边沿由第一位置移动至目标位置可以包括但不限于通过增加延迟电路，使得上述当前传输电路上传输的数据信号所在的时间窗口向后移动，直至时间窗口的左边沿与采样信号的采样沿对齐。上述第二边沿由第二位置移动至目标位置可 以包括但不限于通过减少延迟电路，使得上述当前传输电路上传输的数据信号所在的时间窗口向前移动，直至时间窗口的右边沿与采样信号的采样沿对齐。
需要说明的是，上述第一边沿由第一位置移动至目标位置所增加的延迟电路量为第一延迟量，上述第二边沿由第二位置移动至目标位置所减少的延迟电路量为第二延迟量。
在本申请实施例中，上述根据第一延迟量和第二延迟量调整目标时间窗口，使得当前传输电路上传输的数据信号的中心与采样信号的采样沿对齐可以包括但不限于将第一延迟量和第二延迟量的和的一半作为上述当前传输电路上传输的数据信号的中心与采样信号的采样沿对齐所需要调整的传输延迟。
也即，通过调整第一延迟量和第二延迟量的和的一半，使得当前传输电路上传输的数据信号的中心与采样信号的采样沿对齐。
例如，图11是根据本申请实施例的又一种可选的时序调整方法的示意图，如图11所示，在第一轮调整的过程中，读数据的bit(对应于前述的当前传输电路)的最初状态为phase0，此时，读回的该bit的数值应为1(对应于前述的当前传输电路上传输的数据信号对应于采样信号的高电平)。通过调整Step Counter不断增加该bit的电路延迟，最终，会达到读回的该bit的数值应为0(对应于前述的目标位置)，此时记录该Step Counter的值为R_CNT(对应于前述的第一延迟量)。
此后，置位Phase1至Phase0的初始状态，通过调整Step Counter不断降低该bit的电路延迟，最终，会达到读回的该bit的数值应为0(对应于前述的目标位置)，此时记录该Step Counter的值为L_CNT(对应于前述的第二延迟量)。
此时可以计算得出该bit的电路延迟为(R_CNT+L_CNT)/2时，该bit可以达到采样时钟边沿和数据信号的时间窗口的边沿对齐的目的。
继续按照该步骤对每个bit的电路延迟均进行调整和计算，将可以将每个读数据bit的采样RDQS边沿和数据边沿对齐。至此，第一轮调整结束。
作为一种可选的方案，若执行完第一轮调整后得到的N个传输电路中存在传输的数据信号未与目标采样沿对齐的第二传输电路，对第二传输电路上的传输延迟进行第二轮调整，直到N个传输电路中每个传输电路上传输的数据信号的中心均与目标采样沿对齐，包括：
重复执行以下操作，直到N个传输电路中每个传输电路上传输的数据信号的中心均与目标采样沿对齐，其中，当前采样沿被初始化为与目标采样沿相邻的采样沿：
通过时钟门控关闭采样信号中除目标采样沿之外的第一组采样沿，保留目标采样沿；
根据N个传输电路上传输的数据信号的中心是否与目标采样沿对齐，确定在N个传输电路上传输的数据信号中是否存在未与目标采样沿对齐的第一组数据信号；
在存在第一组数据信号的情况下，通过时钟门控关闭采样信号中除当前采样沿之外的第二组采样沿，保留当前采样沿，其中，第二组采样沿包括目标采样沿，当前采样沿与目标采样沿不同；
根据第一组数据信号的中心是否与当前采样沿对齐，确定第一组数据信号中是否存在未与第二组采样沿对齐的第二组数据信号；
在第一组数据信号中存在目标数据信号情况下，对传输了目标数据信号的传输电路上的传输延迟进行调整，其中，目标数据信号的中心在调整前与当前采样沿对齐，在调整后与目标采样沿对齐；
在存在第二组数据信号的情况下，将当前采样沿更新为采样信号中未被时钟门控保留过的采样沿。
在本申请实施例中，上述时钟门控(Clock-Gating)可以是降低微处理器功耗的重要手段，主要针对寄存器翻转带来的动态功耗，可以关闭采样信号的一个或多个采样周期，以关闭需要关闭的采样沿，保留需要保留的采样沿。
在本申请实施例中，上述第一组数据信号中每个数据信号是中心与一个采样沿对齐，但不与目标采样沿对齐的数据信号。当存在第一组数据信号的情况下，此时，可以通过时钟门控关闭采样信号中除当前采样沿之外的第二组采样沿，保留当前采样沿，同时也关闭目标采样沿，查找第一组数据信号是否均与当前采样沿对齐，将与当前采样沿对齐的的数据信号作为目标数据信号进行传输延迟的调整，以使得整后不与当前采样沿对齐，而是与目标采样沿对齐。
在本申请实施例中，上述第二组数据信号中每个数据信号是中心不与当前采样沿对齐，也不与目标采样沿对齐的数据信号，此时，通过将当前采样沿更新为采样信号中未被时钟门控保留过的采样沿，继续判断第二组数据信号中是否存在第一组数据信号，并将与当前采样沿对齐的的数据信号作为目标数据信号进行传输延迟的调整。
例如，图12是根据本申请实施例的又一种可选的时序调整方法的示意图，如图12所示，图12中的A表示的是N个传输电路中数据信号的中心与目标采样沿对齐的多个传输电路，图12中的B表示通过时钟门控关闭除目标采样沿之外的第一组采样沿，保留目标采样沿，根据N个传输电路上传输的数据信号的中心是否与目标采样沿对齐，确定在N个传输电路上传输的数据信号中是否存在未与目标采样沿对齐的第一组数据信号，图12中的C表示在存在第一组数据信号的情况下，通过时钟门控关闭采样信号中除当前采样沿之外的第二组采样沿，保留当前采样沿，根据第一组数据信号的中心是否与当前采样沿对齐，在第一组数据信号中存在目标数据信号情况下，对传输了所述目标数据信号的传输电路上的传输延迟进行调整。
在本申请实施例中，上述在存在第二组数据信号的情况下，将当前采样沿更新为采样信号中未被时钟门控保留过的采样沿可以理解为，将当前采样沿先更新为最靠近目标采样沿，且未被时钟门控保留过的采样沿。
作为一种可选的方案，调整第一传输电路上的传输延迟，直到第一传输电路上传输的数据信号的中心与采样信号的采样沿对齐，包括：
在第一传输电路上设置的延迟控制单元中确定目标延迟单元，并从目标延迟单元的输出位置上传输对应的数据信号，其中，对应的数据信号的中心与采样信号的采样沿对齐，N个传输电路中的每个传输路径上设置一个延迟控制单元，延迟控制单元包括依次串联的预设数量的延迟单元，每个延迟单元用于将传输电路上的传输延迟调整单位时长。
在本申请实施例中，上述延迟控制单元可以包括但不限于延迟控制电路实现，上述延迟控制电路可支持对读数据传输路径上的延迟电路进行动态的调整，支持增加或减少读数据路径上的延迟。在读数据的传输路径上针对每个读数据bit添加了用于调整该bit路径延迟的延迟电路。
例如，图13是根据本申请实施例的又一种可选的时序调整方法的示意图，如图13所示，读数据通路共包含128bit的DQ、16bit的DM和16bit的DBI路径，该DE为延迟单元(Delay Element)单元，可以包括128个DE，每个DE包含了4个反相器(inverter)电路。该延迟控制单元的每个DE之后均包含了抽头接口(对应于前述的输出位置)，图14是根据本申请实施例的又一种可选的时序调整方法的示意图，如图14所示，Step Counter可以用于控制读数据bit的数值从某一个抽头出口中接出。因此，可以达到对读数据的路径延迟可以调整的目的，也就是可以将读数据和RDQS采样沿的相对位置进行移动和调整。
图15是根据本申请实施例的又一种可选的时序调整方法的示意图，上述时序调整的应用环境示意图，如图15所示，HBM Host内包含HBM模式配置、读指令发送单元、读数据路径延迟控制电路和读数据训练单元四部分电路。读数据训练单元负责对其余三个模块完成控制，并对读取到的数据进行比对，完成整个读数据训练的流程。
作为一种可选的方案，在第一传输电路上的传输延迟完成调整后，可以得到N个目标传输电路，其中，N个目标传输电路中每个目标传输电路上传输的数据信号的中心都与采样信号的采样沿对齐。在这种情况下，可以响应于获取到的第二读指令，在采样信号的采样沿上对N个目标传输电路上传输的数据信号进行采样，得到第二采样数据，其中，第二读指令用于读取目标数据，其中，目标数据是未知的、采用N个比特表示的数据，N个目标传输电路上传输的数据信号包括目标数据中的所述N个比特，第二采样数据是采用N个比特表示的数据。
在本申请实施例中，当对N个传输电路的管脚训练完成，也即，N个传输电路中的存在时序偏移的传输电路上的传输延迟完成调整后，上述N个目标传输电路即可开始用于传输未知的目标数据。
作为一种可选的方案，在目标内存被配置为读寄存器模式下，还可以发送第二读指令，其中，内存被划分为多个双字节寄存器，第二读指令用于通过N个目标传输电路读取多个双字节寄存器中目标双字节寄存器中的目标数据。
在本申请实施例中，上述内存可以包括但不限于HBM内存，上述第二读指令用于读取目标数据，HBM模式配置单元用于配置DWORD MISR电路为DWORD读寄存器模式(对应于前述的读寄存器模式)，该配置是通过配置HBM的模式寄存器MR7来完成。
例如，图16是根据本申请实施例的又一种可选的时序调整方法的示意图，MR7的具体模式如图16所示，配置HBM DWORD为读寄存器模式的步骤如下：
配置MR7的值为：8’b00000001，其中OP0为1，表示使能DWORD Loopback模式；OP[5:3]为3’b000，将DWORD寄存器中的默认值复位为0xAAAAAh。其余位均为默认值；
配置MR7的值为：8’b00010011，其中OP0位1，表示使能DWORD Loopback模式；OP[2:1]为2’b01，表示读取MISR寄存器中的值，由于步骤1中对该值做了复位，因此该 值为0xAAAAAh；OP[5:3]为3’b010，将DWORD寄存器配置为读或写寄存器模式。其余位均为默认值；
此时，HBM DRAM已被配置为DWORD读寄存器模式，可通过发送读指令，读取DWORD寄存器中的数值(对应于前述的目标数据)。
上述N可以有不同的取值，根据N取值的不同，N个目标传输电路上传输的数据信号可能有所不同。作为一种可选的方案，N的取值可以为160，此时，160个目标传输电路上传输的数据信号可以包括128比特的内存读数据总线信号、16比特的读数据掩码信号和16比特的数据总线翻转信号。
在本申请实施例中，上述160个目标传输电路上传输的128比特的内存读数据总线信号可以包括但不限于128比特的DQ信号，16比特的读数据掩码信号可以包括但不限于16比特的DBI信号、16比特的数据总线翻转信号可以包括但不限于16比特的DM信号。
需要说明的是，通过将HBM的数据通路的128bit的DWORD分为DWORD0、DWORD1、DWORD2和DWORD3来设计，在每个DWORD中，根据MISR算法的宽度，又分为Byte0、Byte1、Byte2和Byte3共4个数据单元来对比。
例如，图17是根据本申请实施例的又一种可选的时序调整方法的示意图，如图17所示，每个Byte内，从第19bit到第0bit分别为DBI的下降沿数据和DBI的上升沿数据，8bit DQ的每个bit的下降沿的数据和上升沿的数据和DM的下降沿数据和DM的上升沿数据，每个DWORD(例如DWORD0、DWORD1、DWORD2、DWORD3)中的Byte包含20bit的数值，当DWORD寄存器被复位后，该值将变为0xAAAAAh，读指令发送单元负责发送读指令至HBM DRAM。
作为一种可选的方案，调整第一传输电路上的传输延迟，直到第一传输电路上传输的数据信号的中心与采样信号的采样沿对齐，包括：
在采样沿为上升沿的情况下，调整第一传输电路上的传输延迟，直到第一传输电路上传输的数据信号的中心与采样信号的上升沿对齐；或者
在采样沿为下降沿的情况下，调整第一传输电路上的传输延迟，直到第一传输电路上传输的数据信号的中心与采样信号的下降沿对齐。
可选的，在本申请实施例中，上述采样沿可以包括但不限于上升沿和下降沿，可以通过上升沿和下降沿中任意一种实现数据的采样和读取，还可以同时通过上升沿和下降沿实现数据的采样和读取。
作为一种可选的方案，调整第一传输电路上的传输延迟，直到第一传输电路上传输的数据信号的中心与采样信号的采样沿对齐，包括：
调整第一传输电路上的传输延迟，直到第一传输电路上传输的数据信号对应的中心点与采样信号的采样沿对齐，其中，中心点为数据信号所在的时间窗口的中心点；或者
调整第一传输电路上的传输延迟，直到采样信号的采样沿位于第一传输电路上传输的数据信号对应的时间子窗口中，其中，时间子窗口是时间窗口中包括中心点的子窗口。
可以理解的是，在本申请的具体实施方式中，涉及到用户信息等相关的数据，当本申请以上实施例运用到具体产品或技术中时，需要获得用户许可或者同意，且相关数据的收集、使用和处理需要遵守相关国家和地区的相关法律法规和标准。
需要说明的是，对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本申请并不受所描述的动作顺序的限制，因为依据本申请，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作和模块并不一定是本申请所必须的。
根据本申请实施例的另一个方面，还提供了一种用于实施上述时序调整方法的时序调整装置。如图18所示，该装置包括：
生成模块1802，用于响应于获取到的第一读指令，生成采样信号，其中，所述第一读指令用于读取训练数据，其中，所述训练数据是已知的、采用N个比特表示的数据，N为大于或等于2的正整数；
采样模块1804，用于在所述采样信号的采样沿上对N个传输电路上传输的数据信号进行采样，得到第一采样数据，其中，所述N个传输电路上传输的数据信号包括所述训练数据中的所述N个比特，所述第一采样数据是采用N个比特表示的数据；
确定模块1806，用于根据所述训练数据和所述第一采样数据中的相同比特的取值，确定所述N个传输电路中的第一传输电路，所述第一传输电路为所述N个传输电路中存在时序偏移的传输电路；
调整模块1808，用于调整所述第一传输电路上的传输延迟，直到所述第一传输电路上传输的数据信号的中心与所述采样信号的采样沿对齐。
作为一种可选的方案，所述装置用于通过如下方式根据所述训练数据和所述第一采样数据中的相同比特的取值，确定所述N个传输电路中的第一传输电路：确定所述训练数据和所述第一采样数据中的相同比特的取值是否相同；若所述N个比特中存在取值不同的M个比特，将所述N个传输电路中的M个传输电路确定为所述第一传输电路，其中，所述M个传输电路用于传输所述M个比特对应的数据信号，M大于或等于1，且小于或等于N。
作为一种可选的方案，所述装置用于通过如下方式调整所述第一传输电路上的传输延迟，直到所述第一传输电路上传输的数据信号的中心与所述采样信号的采样沿对齐：
对所述第一传输电路上的传输延迟进行第一轮调整，直到所述N个传输电路中每个传输电路上传输的数据信号的中心分别与所述采样信号的一个采样沿对齐；
若执行完所述第一轮调整后得到的N个传输电路中存在传输的数据信号未与目标采样沿对齐的第二传输电路，对所述第二传输电路上的传输延迟进行第二轮调整，直到所述N个传输电路中每个传输电路上传输的数据信号的中心均与所述目标采样沿对齐，其中，在所有采样沿中所述目标采样沿与所述N个传输电路上传输的数据信号的中心对齐的次数最多。
作为一种可选的方案，所述装置用于通过如下方式对所述第一传输电路上的传输延迟进行第一轮调整，直到所述N个传输电路中每个传输电路上传输的数据信号的中心分别与所述采样信号的一个采样沿对齐：
对所述N个传输电路中的每个所述第一传输电路执行以下操作，其中，在执行以下操作时，每个所述第一传输电路为当前传输电路：
若所述当前传输电路上传输的数据信号对应于所述采样信号的高电平，将目标时间窗口的第一边沿确定为第一位置，将所述目标时间窗口的第二边沿确定为第二位置，所述目标时间窗口为所述当前传输电路上传输的数据信号所在的时间窗口；
增加所述当前传输电路上的传输延迟，直到所述第一边沿由所述第一位置移动至目标位置，确定所述当前传输电路上增加的传输延迟的第一延迟量，其中，所述目标位置对应于所述采样信号的采样沿；
降低所述当前传输电路降低传输延迟，直到所述第二边沿由所述第二位置移动至所述目标位置，确定所述当前传输电路上降低的传输延迟的第二延迟量；
根据所述第一延迟量和所述第二延迟量调整所述目标时间窗口，使得所述当前传输电路上传输的数据信号的中心与所述采样信号的采样沿对齐。
作为一种可选的方案，所述装置用于通过如下方式若执行完所述第一轮调整后得到的N个传输电路中存在传输的数据信号未与目标采样沿对齐的第二传输电路，对所述第二传输电路上的传输延迟进行第二轮调整，直到所述N个传输电路中每个传输电路上传输的数据信号的中心均与所述目标采样沿对齐：
重复执行以下操作，直到所述N个传输电路中每个传输电路上传输的数据信号的中心均与所述目标采样沿对齐，其中，当前采样沿被初始化为与所述目标采样沿相邻的采样沿：
通过时钟门控关闭所述采样信号中除所述目标采样沿之外的第一组采样沿，保留所述目标采样沿；
根据所述N个传输电路上传输的数据信号的中心是否与所述目标采样沿对齐，确定在所述N个传输电路上传输的数据信号中是否存在未与所述目标采样沿对齐的第一组数据信号；
在存在所述第一组数据信号的情况下，通过所述时钟门控关闭所述采样信号中除当前采样沿之外的第二组采样沿，保留所述当前采样沿，其中，所述第二组采样沿包括所述目标采样沿，所述当前采样沿与所述目标采样沿不同；
根据所述第一组数据信号的中心是否与所述当前采样沿对齐，确定所述第一组数据信号中是否存在未与所述第二组采样沿对齐的第二组数据信号；
在所述第一组数据信号中存在目标数据信号情况下，对传输了所述目标数据信号的传输电路上的传输延迟进行调整，其中，所述目标数据信号的中心在调整前与所述当前采样沿对齐，在调整后与所述目标采样沿对齐；
在存在所述第二组数据信号的情况下，将所述当前采样沿更新为所述采样信号中未被所述时钟门控保留过的采样沿。
作为一种可选的方案，所述装置用于通过如下方式调整所述第一传输电路上的传输延迟，直到所述第一传输电路上传输的数据信号的中心与所述采样信号的采样沿对齐：
在所述第一传输电路上设置的延迟控制单元中确定目标延迟单元，并从所述目标延迟单元的输出位置上传输对应的数据信号，其中，所述对应的数据信号的中心与所述采样信号的采样沿对齐，所述N个传输电路中的每个传输路径上设置一个所述延迟控制单元，所述延迟控制单元包括依次串联的预设数量的延迟单元，每个所述延迟单元用于将所述传输电路上的传输延迟调整单位时长。
作为一种可选的方案，所述装置还用于：
在所述第一传输电路上的传输延迟完成调整后，得到N个目标传输电路，其中，所述N个目标传输电路中每个目标传输电路上传输的数据信号的中心都与所述采样信号的采样沿对齐；
响应于获取到的第二读指令，在所述采样信号的采样沿上对所述N个目标传输电路上传输的数据信号进行采样，得到第二采样数据，其中，所述第二读指令用于读取目标数据，其中，所述目标数据是未知的、采用N个比特表示的数据，所述N个目标传输电路上传输的数据信号包括所述目标数据中的所述N个比特，所述第二采样数据是采用N个比特表示的数据。
作为一种可选的方案，所述装置还用于：
在内存被配置为读寄存器模式下，发送所述第二读指令，其中，所述内存被划分为多个双字节寄存器，所述第二读指令用于通过所述N个目标传输电路读取所述多个双字节寄存器中目标双字节寄存器中的所述目标数据。
作为一种可选的方案，N的取值为160，所述N个目标传输电路上传输的数据信号包括128比特的内存读数据总线信号、16比特的读数据掩码信号和16比特的数据总线翻转信号。
作为一种可选的方案，所述装置用于通过如下方式调整所述第一传输电路上的传输延迟，直到所述第一传输电路上传输的数据信号的中心与所述采样信号的采样沿对齐：
在所述采样沿为上升沿的情况下，调整所述第一传输电路上的传输延迟，直到所述第一传输电路上传输的数据信号的中心与所述采样信号的所述上升沿对齐；或者
在所述采样沿为下降沿的情况下，调整所述第一传输电路上的传输延迟，直到所述第一传输电路上传输的数据信号的中心与所述采样信号的所述下降沿对齐。
作为一种可选的方案，所述装置用于通过如下方式调整所述第一传输电路上的传输延迟，直到所述第一传输电路上传输的数据信号的中心与所述采样信号的采样沿对齐：
调整所述第一传输电路上的传输延迟，直到所述第一传输电路上传输的数据信号对应的中心点与所述采样信号的采样沿对齐，其中，所述中心点为所述数据信号所在的时间窗口的中心点；或者
所述调整所述第一传输电路上的传输延迟，直到所述采样信号的采样沿位于所述第一传输电路上传输的数据信号对应的时间子窗口中，其中，所述时间子窗口是所述时间窗口中包括所述中心点的子窗口。
根据本申请的一个方面，提供了一种计算机程序产品，该计算机程序产品包括计算机程序，该计算机程序包含用于执行流程图所示的方法的程序代码。在这样的实施例中，该计算机程序可以通过通信部分1909从网络上被下载和安装，和/或从可拆卸介质1911被安装。在该计算机程序被中央处理器1901执行时，执行本申请实施例提供的各种功能。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
图19示意性地示出了用于实现本申请实施例的电子设备的计算机系统结构框图。
需要说明的是，图19示出的电子设备的计算机系统1900仅是一个示例，不应对本申请实施例的功能和使用范围带来任何限制。
如图19所示，计算机系统1900包括中央处理器1901(Central Processing Unit，CPU)，其可以根据存储在只读存储器1902(Read-Only Memory，ROM)中的程序或者从存储部分1908加载到随机访问存储器1903(Random Access Memory，RAM)中的程序而执行各种适当的动作和处理。在随机访问存储器1903中，还存储有系统操作所需的各种程序和数据。中央处理器1901、在只读存储器1902以及随机访问存储器1903通过总线1904彼此相连。输入/输出接口1905(Input/Output接口，即I/O接口)也连接至总线1904。
以下部件连接至输入/输出接口1905：包括键盘、鼠标等的输入部分1906；包括诸如阴极射线管(Cathode Ray Tube，CRT)、液晶显示器(Liquid Crystal Display，LCD)等以及扬声器等的输出部分1907；包括硬盘等的存储部分1908；以及包括诸如局域网卡、调制解调器等的网络接口卡的通信部分1909。通信部分1909经由诸如因特网的网络执行通信处理。驱动器1190也根据需要连接至输入/输出接口1905。可拆卸介质1911，诸如磁盘、光盘、磁光盘、半导体存储器等等，根据需要安装在驱动器1190上，以便于从其上读出的计算机程序根据需要被安装入存储部分1908。
特别地，根据本申请的实施例，各个方法流程图中所描述的过程可以被实现为计算机软件程序。例如，本申请的实施例包括一种计算机程序产品，其包括承载在计算机可读介质上的计算机程序，该计算机程序包含用于执行流程图所示的方法的程序代码。在这样的实施例中，该计算机程序可以通过通信部分1909从网络上被下载和安装，和/或从可拆卸介质1911被安装。在该计算机程序被中央处理器1901执行时，执行本申请的系统中限定的各种功能。
根据本申请实施例的又一个方面，还提供了一种用于实施上述时序调整方法的电子设备，该电子设备可以是图1所示的终端设备或服务器。本实施例以该电子设备为终端设备为例来说明。如图20所示，该电子设备包括存储器2002和处理器2004，该存储器2002中存储有计算机程序，该处理器2004被设置为通过计算机程序执行上述任一项方法实施例中的步骤。
在一种可能的实现方式中，在本实施例中，上述电子设备可以位于计算机网络的多个网络设备中的至少一个网络设备。
在一种可能的实现方式中，在本实施例中，上述处理器可以被设置为通过计算机程序执行以下步骤：
S1，响应于获取到的第一读指令，生成采样信号，其中，第一读指令用于读取训练数据，其中，训练数据是已知的、采用N个比特表示的数据，N为大于或等于2的正整数；
S2，在采样信号的采样沿上对N个传输电路上传输的数据信号进行采样，得到第一采样数据，其中，N个传输电路上传输的数据信号包括训练数据中的N个比特，第一采样数据是采用N个比特表示的数据；
S3，根据训练数据和第一采样数据中的相同比特的取值，确定N个传输电路中的第一传输电路，第一传输电路为N个传输电路中存在时序偏移的传输电路；
S4，调整第一传输电路上的传输延迟，直到第一传输电路上传输的数据信号的中心与采样信号的采样沿对齐。
在一种可能的实现方式中，本领域普通技术人员可以理解，图20所示的结构仅为示意，电子设备也可以是智能手机(如Android手机、iOS手机等)、平板电脑、掌上电脑以及移动互联网设备(Mobile Internet Devices，MID)、PAD等终端设备。图20其并不对上述电子装置电子设备的结构造成限定。例如，电子装置电子设备还可包括比图20中所示更多或者更少的组件(如网络接口等)，或者具有与图20所示不同的配置。
其中，存储器2002可用于存储软件程序以及模块，如本申请实施例中的时序调整方法和装置对应的程序指令/模块，处理器2004通过运行存储在存储器2002内的软件程序以及模块，从而执行各种功能应用以及数据处理，即实现上述的时序调整方法。存储器2002可包括高速随机存储器，还可以包括非易失性存储器，如一个或者多个磁性存储装置、闪存、或者其他非易失性固态存储器。在一些实例中，存储器2002可进一步包括相对于处理器2004远程设置的存储器，这些远程存储器可以通过网络连接至终端。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。其中，存储器2002具体可以但不限于用于存储训练数据、目标数据等信息。作为一种示例，如图20所示，上述存储器2002中可以但不限于包括上述时序调整装置中的生成模块1802、采样模块1804、确定模块1806以及调整模块1808。此外，还可以包括但不限于上述时序调整装置中的其他模块单元，本示例中不再赘述。
在一种可能的实现方式中，上述的传输装置2006用于经由一个网络接收或者发送数据。上述的网络具体实例可包括有线网络及无线网络。在一个实例中，传输装置2006包括一个网络适配器(Network Interface Controller，NIC)，其可通过网线与其他网络设备与路由器相连从而可与互联网或局域网进行通讯。在一个实例中，传输装置2006为射频(Radio Frequency，RF)模块，其用于通过无线方式与互联网进行通讯。
此外，上述电子设备还包括：显示器2008，用于显示上述数据信号；和连接总线2010，用于连接上述电子设备中的各个模块部件。
在其他实施例中，上述终端设备或者服务器可以是一个分布式系统中的一个节点，其中，该分布式系统可以为区块链系统，该区块链系统可以是由该多个节点通过网络通信的形式连接形成的分布式系统。其中，节点之间可以组成点对点(P2P，Peer To Peer)网络，任意形式的计算设备，比如服务器、终端等电子设备都可以通过加入该点对点网络而成为该区块链系统中的一个节点。
根据本申请的一个方面，提供了一种计算机可读存储介质，计算机设备的处理器从计算机可读存储介质读取该计算机指令，处理器执行该计算机指令，使得该计算机设备执行上述时序调整方面的各种可选实现方式中提供的时序调整方法。
在本实施例中，本领域普通技术人员可以理解上述实施例的各种方法中的全部或部分步骤是可以通过程序来指令终端设备相关的硬件来完成，该程序可以存储于一计算机可读存储介质中，存储介质可以包括：闪存盘、只读存储器(Read-Only Memory，ROM)、随机存取器(Random Access Memory，RAM)、磁盘或光盘等。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
上述实施例中的集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在上述计算机可读取的存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在存储介质中，包括若干指令用以使得一台或多台计算机设备(可为个人计算机、服务器或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。
在本申请的上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
在本申请所提供的几个实施例中，应该理解到，所揭露的客户端，可通过其它的方式实现。其中，以上所描述的装置实施例仅仅是示意性的，例如所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，单元或模块的间接耦合或通信连接，可以是电性或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (15)

  1. 一种时序调整方法，所述方法由电子设备执行，包括：
    响应于获取到的第一读指令，生成采样信号，其中，所述第一读指令用于读取训练数据，其中，所述训练数据是已知的、采用N个比特表示的数据，N为大于或等于2的正整数；
    在所述采样信号的采样沿上对N个传输电路上传输的数据信号进行采样，得到第一采样数据，其中，所述N个传输电路上传输的数据信号包括所述训练数据中的所述N个比特，所述第一采样数据是采用N个比特表示的数据；
    根据所述训练数据和所述第一采样数据中的相同比特的取值，确定所述N个传输电路中的第一传输电路，所述第一传输电路为所述N个传输电路中存在时序偏移的传输电路；
    调整所述第一传输电路上的传输延迟，直到所述第一传输电路上传输的数据信号的中心与所述采样信号的采样沿对齐。
  2. 根据权利要求1所述的方法，所述根据所述训练数据和所述第一采样数据中的相同比特的取值，确定所述N个传输电路中的第一传输电路，包括：
    确定所述训练数据和所述第一采样数据中的相同比特的取值是否相同；
    若所述N个比特中存在取值不同的M个比特，将所述N个传输电路中的M个传输电路确定为所述第一传输电路，其中，所述M个传输电路用于传输所述M个比特对应的数据信号，M大于或等于1，且小于或等于N。
  3. 根据权利要求1所述的方法，所述调整所述第一传输电路上的传输延迟，直到所述第一传输电路上传输的数据信号的中心与所述采样信号的采样沿对齐，包括：
    对所述第一传输电路上的传输延迟进行第一轮调整，直到所述N个传输电路中每个传输电路上传输的数据信号的中心分别与所述采样信号的一个采样沿对齐；
    若执行完所述第一轮调整后得到的N个传输电路中存在传输的数据信号未与目标采样沿对齐的第二传输电路，对所述第二传输电路上的传输延迟进行第二轮调整，直到所述N个传输电路中每个传输电路上传输的数据信号的中心均与所述目标采样沿对齐，其中，在所有采样沿中所述目标采样沿与所述N个传输电路上传输的数据信号的中心对齐的次数最多。
  4. 根据权利要求3所述的方法，所述对所述第一传输电路上的传输延迟进行第一轮调整，直到所述N个传输电路中每个传输电路上传输的数据信号的中心分别与所述采样信号的一个采样沿对齐，包括：
    对所述N个传输电路中的每个所述第一传输电路执行以下操作，其中，在执行以下操作时，每个所述第一传输电路为当前传输电路：
    若所述当前传输电路上传输的数据信号对应于所述采样信号的高电平，将目标时间窗口的第一边沿确定为第一位置，将所述目标时间窗口的第二边沿确定为第二位置，所述目标时间窗口为所述当前传输电路上传输的数据信号所在的时间窗口；
    增加所述当前传输电路上的传输延迟，直到所述第一边沿由所述第一位置移动至目标位置，确定所述当前传输电路上增加的传输延迟的第一延迟量，其中，所述目标位置对应于所述采样信号的采样沿；
    降低所述当前传输电路降低传输延迟，直到所述第二边沿由所述第二位置移动至所述目标位置，确定所述当前传输电路上降低的传输延迟的第二延迟量；
    根据所述第一延迟量和所述第二延迟量调整所述目标时间窗口，使得所述当前传输电路上传输的数据信号的中心与所述采样信号的采样沿对齐。
  5. 根据权利要求3所述的方法，所述若执行完所述第一轮调整后得到的N个传输电路中存在传输的数据信号未与目标采样沿对齐的第二传输电路，对所述第二传输电路上的传输延迟进行第二轮调整，直到所述N个传输电路中每个传输电路上传输的数据信号的中心均与所述目标采样沿对齐，包括：
    重复执行以下操作，直到所述N个传输电路中每个传输电路上传输的数据信号的中心均与所述目标采样沿对齐，其中，当前采样沿被初始化为与所述目标采样沿相邻的采样沿：
    通过时钟门控关闭所述采样信号中除所述目标采样沿之外的第一组采样沿，保留所述目标采样沿；
    根据所述N个传输电路上传输的数据信号的中心是否与所述目标采样沿对齐，确定在所述N个传输电路上传输的数据信号中是否存在未与所述目标采样沿对齐的第一组数据信号；
    在存在所述第一组数据信号的情况下，通过所述时钟门控关闭所述采样信号中除当前采样沿之外的第二组采样沿，保留所述当前采样沿，其中，所述第二组采样沿包括所述目标采样沿，所述当前采样沿与所述目标采样沿不同；
    根据所述第一组数据信号的中心是否与所述当前采样沿对齐，确定所述第一组数据信号中是否存在未与所述第二组采样沿对齐的第二组数据信号；
    在所述第一组数据信号中存在目标数据信号情况下，对传输了所述目标数据信号的传输电路上的传输延迟进行调整，其中，所述目标数据信号的中心在调整前与所述当前采样沿对齐，在调整后与所述目标采样沿对齐；
    在存在所述第二组数据信号的情况下，将所述当前采样沿更新为所述采样信号中未被所述时钟门控保留过的采样沿。
  6. 根据权利要求1所述的方法，所述调整所述第一传输电路上的传输延迟，直到所述第一传输电路上传输的数据信号的中心与所述采样信号的采样沿对齐，包括：
    在所述第一传输电路上设置的延迟控制单元中确定目标延迟单元，并从所述目标延迟单元的输出位置上传输对应的数据信号，其中，所述对应的数据信号的中心与所述采样信号的采样沿对齐，所述N个传输电路中的每个传输路径上设置一个所述延迟控制单元，所述延迟控制单元包括依次串联的预设数量的延迟单元，每个所述延迟单元用于将所述传输电路上的传输延迟调整单位时长。
  7. 根据权利要求1所述的方法，所述方法还包括：
    在所述第一传输电路上的传输延迟完成调整后，得到N个目标传输电路，其中，所述N个目标传输电路中每个目标传输电路上传输的数据信号的中心都与所述采样信号的采样沿对齐；
    响应于获取到的第二读指令，在所述采样信号的采样沿上对所述N个目标传输电路上传输的数据信号进行采样，得到第二采样数据，其中，所述第二读指令用于读取目标数据，其中，所述目标数据是未知的、采用N个比特表示的数据，所述N个目标传输电路上传输的数据信号包括所述目标数据中的所述N个比特，所述第二采样数据是采用N个比特表示的数据。
  8. 根据权利要求7所述的方法，所述方法还包括：
    在内存被配置为读寄存器模式下，发送所述第二读指令，其中，所述内存被划分为多个双字节寄存器，所述第二读指令用于通过所述N个目标传输电路读取所述多个双字节寄存器中目标双字节寄存器中的所述目标数据。
  9. 根据权利要求7所述的方法，N的取值为160，所述N个目标传输电路上传输的数据信号包括128比特的内存读数据总线信号、16比特的读数据掩码信号和16比特的数据总线翻转信号。
  10. 根据权利要求1至9中任一项所述的方法，所述调整所述第一传输电路上的传输延迟，直到所述第一传输电路上传输的数据信号的中心与所述采样信号的采样沿对齐，包括：
    在所述采样沿为上升沿的情况下，调整所述第一传输电路上的传输延迟，直到所述第一传输电路上传输的数据信号的中心与所述采样信号的所述上升沿对齐；或者
    在所述采样沿为下降沿的情况下，调整所述第一传输电路上的传输延迟，直到所述第一传输电路上传输的数据信号的中心与所述采样信号的所述下降沿对齐。
  11. 根据权利要求1至9中任一项所述的方法，所述调整所述第一传输电路上的传输延迟，直到所述第一传输电路上传输的数据信号的中心与所述采样信号的采样沿对齐，包括：
    调整所述第一传输电路上的传输延迟，直到所述第一传输电路上传输的数据信号对应的中心点与所述采样信号的采样沿对齐，其中，所述中心点为所述数据信号所在的时间窗口的中心点；或者
    所述调整所述第一传输电路上的传输延迟，直到所述采样信号的采样沿位于所述第一传输电路上传输的数据信号对应的时间子窗口中，其中，所述时间子窗口是所述时间窗口中包括所述中心点的子窗口。
  12. 一种时序调整装置，所述装置部署在电子设备上，包括：
    生成模块，用于响应于获取到的第一读指令，生成采样信号，其中，所述第一读指令用于读取训练数据，其中，所述训练数据是已知的、采用N个比特表示的数据，N为大于或等于2的正整数；
    采样模块，用于在所述采样信号的采样沿上对N个传输电路上传输的数据信号进行采样，得到第一采样数据，其中，所述N个传输电路上传输的数据信号包括所述训练数据中的所述N个比特，所述第一采样数据是采用N个比特表示的数据；
    确定模块，用于根据所述训练数据和所述第一采样数据中的相同比特的取值，确定所述N个传输电路中的第一传输电路，所述第一传输电路为所述N个传输电路中存在时序偏移的传输电路；
    调整模块，用于调整所述第一传输电路上的传输延迟，直到所述第一传输电路上传输的数据信号的中心与所述采样信号的采样沿对齐。
  13. 一种计算机可读的存储介质，所述计算机可读的存储介质包括存储的计算机程序，其中，所述计算机程序可被终端设备或计算机运行时执行所述权利要求1至11任一项中所述的方法。
  14. 一种计算机程序产品，包括计算机程序，该计算机程序被处理器执行时实现权利要求1至11任一项中所述的方法。
  15. 一种电子设备，包括存储器和处理器，所述存储器中存储有计算机程序，所述处理器被设置为通过所述计算机程序执行所述权利要求1至11任一项中所述的方法。
PCT/CN2023/081226 2022-04-25 2023-03-14 时序调整方法和装置、存储介质及电子设备 WO2023207376A1 (zh)

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