WO2023206813A1 - 光电探测器及其制作方法 - Google Patents

光电探测器及其制作方法 Download PDF

Info

Publication number
WO2023206813A1
WO2023206813A1 PCT/CN2022/104075 CN2022104075W WO2023206813A1 WO 2023206813 A1 WO2023206813 A1 WO 2023206813A1 CN 2022104075 W CN2022104075 W CN 2022104075W WO 2023206813 A1 WO2023206813 A1 WO 2023206813A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
type
doped region
protrusion
semiconductor substrate
Prior art date
Application number
PCT/CN2022/104075
Other languages
English (en)
French (fr)
Inventor
霍攀杰
胡艳
Original Assignee
武汉光迅科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉光迅科技股份有限公司 filed Critical 武汉光迅科技股份有限公司
Publication of WO2023206813A1 publication Critical patent/WO2023206813A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a photodetector and a manufacturing method thereof.
  • photodetectors are widely used as a light receiving chip, which realizes long-distance transmission of optical signals by converting optical signals into electrical signals.
  • embodiments of the present disclosure provide a photodetector and a manufacturing method thereof.
  • a photodetector including:
  • An n-type semiconductor substrate having opposing first and second surfaces
  • a light absorption layer and a semiconductor layer are sequentially stacked on the first surface of the n-type semiconductor substrate;
  • a p-type doped region is located in the semiconductor layer, the p-type doped region extends from the top surface of the semiconductor layer toward the light absorption layer and is in contact with the light absorption layer; the p-type doped region
  • the hybrid area includes a body, a first protrusion and a second protrusion; wherein the first protrusion and the second protrusion are located on opposite sides of the body; along a direction parallel to the light absorbing layer , the first protrusion protrudes in a direction away from the second protrusion, and the second protrusion protrudes in a direction away from the first protrusion;
  • a p-type contact layer is located on the p-type doped region and contacts the p-type doped region;
  • the second electrode layer covers and contacts the second surface of the n-type semiconductor substrate, and exposes at least part of the second surface; wherein at least part of the exposed second surface is to receive incident light signals.
  • the photodetector further includes:
  • a protective layer covers the semiconductor layer and exposes the first electrode layer.
  • the second electrode layer includes an opening exposing the n-type semiconductor substrate; wherein an orthographic projection of the opening on the n-type semiconductor substrate is located at The p-type doped region is within an orthographic projection on the n-type semiconductor substrate.
  • the photodetector further includes:
  • An anti-reflection layer is located on the second surface of the n-type semiconductor substrate; wherein the second electrode layer exposes the anti-reflection layer.
  • the n-type semiconductor substrate and the semiconductor layer are composed of materials including: indium phosphide;
  • composition materials of the light absorption layer and the p-type contact layer include: indium gallium arsenic material;
  • the constituent materials of the first electrode layer and the second electrode layer include: titanium, platinum, gold or combinations thereof;
  • composition material of the anti-reflection layer includes: silicon oxide, silicon nitride or a combination thereof.
  • the doping element of the p-type doped region includes zinc.
  • a method for manufacturing a photodetector including:
  • a light absorption layer, a semiconductor layer and a p-type contact layer are formed in sequence on the first surface of the n-type semiconductor substrate; wherein the p-type contact layer covers at least part of the semiconductor layer;
  • a p-type doped region is formed in the semiconductor layer below the p-type contact layer; wherein the p-type doped region extends from the top surface of the semiconductor layer toward the light absorption layer and is connected with the The light absorbing layer contacts;
  • the p-type doped region includes a body, a first protrusion and a second protrusion; the first protrusion and the second protrusion are located on opposite sides of the body; along parallel lines In the direction of the light absorbing layer, the first protrusion protrudes in a direction away from the second protrusion, and the second protrusion protrudes in a direction away from the first protrusion;
  • a second electrode layer is formed on the second surface of the n-type semiconductor substrate; wherein the second electrode layer contacts the second surface and exposes at least part of the second surface, so At least part of the exposed second surface is used to receive incident light signals.
  • the method before forming the p-type doped region, the method further includes:
  • Forming the p-type doped region includes:
  • the remaining dielectric material forms a protective layer; wherein the protective layer covers the semiconductor layer and exposes the p-type contact layer.
  • the method further includes:
  • An opening is formed on the second electrode layer; wherein the opening exposes the n-type semiconductor substrate; the orthographic projection of the opening on the n-type semiconductor substrate is located on the p-type doped semiconductor substrate.
  • the hybrid region is within the orthographic projection on the n-type semiconductor substrate.
  • the method before forming the second electrode layer, the method further includes:
  • an antireflection layer on the second surface of the n-type semiconductor substrate, the area of the antireflection layer being less than or equal to the area of the second surface;
  • Forming the second electrode layer includes:
  • the second electrode layer is formed to cover the second surface and expose the antireflection layer.
  • a p-type contact layer contacting the p-type doped region and a first electrode layer covering and contacting the p-type contact layer are provided on the p-type doped region.
  • the first electrode layer and the p-type doped region in the embodiment of the present disclosure have a larger contact area. Under the action of the same intensity of current, the first electrode layer The current density carried by the electrode layer per unit area is smaller, which is beneficial to reducing electrostatic discharge (ESD) damage.
  • ESD electrostatic discharge
  • embodiments of the present disclosure improve the lateral current expansion performance of the p-type doped region and reduce the unit area of the p-type doped region through the first protrusion and the second protrusion located on opposite sides of the p-type doped region body. ESD current density carried on the photodetector, thereby reducing ESD damage to the photodetector.
  • Embodiments of the present disclosure provide a second electrode layer that exposes at least a portion of the second surface of the n-type semiconductor substrate to receive incident light signals.
  • the first electrode layer is not used to receive the incident light signal, and the area of the first electrode layer is not limited by the incident light signal, which can further increase the The area of the first electrode layer is large to further reduce ESD damage to the photodetector.
  • Figure 1 is a schematic structural diagram showing a photodetector according to an exemplary embodiment
  • FIGS. 2a to 2c are schematic structural diagrams showing a photodetector according to embodiments of the present disclosure
  • Figure 3 is a schematic flowchart illustrating a method of manufacturing a photodetector according to an embodiment of the present disclosure
  • 4a to 4i are schematic diagrams illustrating a method of manufacturing a photodetector according to an embodiment of the present disclosure.
  • the term "A and B are in contact” includes the situation where A and B are in direct contact, or the situation where A and B are interposed with other components and A is in indirect contact with B.
  • the term "layer" refers to a portion of material that includes a region having a thickness.
  • a layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure.
  • a layer may be a region of a homogeneous or non-homogeneous continuous structure having a thickness less than the thickness of the continuous structure.
  • the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal plane at the top and bottom surfaces of the continuous structure. Layers may extend horizontally, vertically and/or along inclined surfaces.
  • a layer may include multiple sub-layers.
  • FIG. 1 is a schematic structural diagram showing a photodetector 100 according to an exemplary embodiment.
  • the photodetector 100 includes:
  • n-type semiconductor substrate 110 having opposing first and second surfaces
  • the light absorption layer 120 and the semiconductor layer 130 are sequentially stacked on the first surface of the n-type semiconductor substrate 110;
  • the p-type doped region 140 is located in the semiconductor layer 130.
  • the p-type doped region 140 extends from the top surface of the semiconductor layer 130 toward the light absorbing layer 120 and is in contact with the light absorbing layer 120;
  • the p-type contact ring 150 is located on the p-type doped region 140 and contacts the p-type doped region 140;
  • the light-transmitting layer 160 covers the semiconductor layer 130 and exposes the p-type contact ring 150;
  • the first electrode ring 171 covers and contacts the p-type contact ring 150;
  • the second electrode layer 172 covers and contacts the second surface of the n-type semiconductor substrate 110 .
  • the first surface may be the upper surface of the n-type semiconductor substrate 110
  • the second surface may be the upper surface of the n-type semiconductor substrate 110 .
  • the first surface may be a side surface of the n-type semiconductor substrate 110 away from the second electrode layer 172
  • the second surface may be a side surface of the n-type semiconductor substrate 110 close to the second electrode layer 172 .
  • the component material of the light absorbing layer 120 includes an intrinsic semiconductor, or an i-type semiconductor with a very small doping concentration that is close to an intrinsic semiconductor.
  • a pin-type photodiode is formed between the p-type doped region 140, the light absorption layer 120 and the n-type semiconductor substrate 110. The three can form a pin junction, in which the light absorption layer 120 is the main absorption layer for optical signals.
  • the photodetector 100 may further include an n-type buffer layer 180 located between the n-type semiconductor substrate 110 and the light absorption layer 120. The n-type buffer layer 180 and the n-type semiconductor substrate together form the n part of the pin junction.
  • the incident light signal can be incident from the middle region of the first electrode ring 171 , pass through the light-transmitting layer 160 located in the middle of the first electrode ring 171 , and the p-type doped region 140 below the light-transmitting layer 160 to reach the light absorber.
  • Layer 120 After the light absorption layer 120 absorbs the incident light signal, it generates photogenerated carriers (including electrons and holes), thereby generating a photocurrent, converting the light signal into an electrical signal, thereby achieving photoelectric conversion.
  • the photocurrent can be connected to an external circuit through the first electrode ring 171 and the second electrode layer 172 to detect changes in the photocurrent to detect changes in the optical signal.
  • the constituent materials of the first electrode ring 171 and the second electrode layer 172 include but are not limited to: titanium, platinum, gold and other conductive materials. Therefore, the light transmittance of the first electrode ring 171 and the second electrode layer 172 is low or substantially opaque.
  • Figure 1 shows a cross-sectional view of the photodetector 100.
  • the first electrode ring 171 in this embodiment does not refer to two components, but a cross-sectional view of one first electrode ring 171. It can be understood that along the z direction, the orthographic projection of the first electrode ring 171 on the semiconductor layer 130 is a closed ring (for example, a circular ring or an elliptical ring).
  • the photodetector 100 further includes an electrode 173 coupled to the first electrode ring 171 for extracting electrical signals from the first electrode ring 171 and interconnecting electrical signals with external packaged devices.
  • the width of the first electrode ring 171 is usually smaller, which will result in the An electrode ring 171 has a smaller area. Therefore, when electrostatic charges accumulate on the first electrode ring 171 or photocurrent passes through it, the charge density carried by the first electrode ring 171 per unit area is relatively large, and an electrostatic discharge (ESD) phenomenon will occur, which affects the p-type doped region. 140 produces ESD damage and even breaks down the p-type doped region 140, causing the photodetector to fail.
  • ESD electrostatic discharge
  • the sensitivity of electronic devices to ESD damage can generally be measured by the ESD threshold.
  • the ESD threshold is proportional to the size of the active area. The smaller the active area, the lower the threshold, and the more susceptible the photodetector is to ESD damage. Referring to FIG. 1 , the active area can be equivalent to the contact area between the p-type doped region 140 and the light absorbing layer 120 .
  • the ESD threshold can be increased by enlarging the p-type doped region 140 to increase the active area to reduce ESD damage.
  • the p-n junction capacitance between the p-type doped region 140 and the n-type semiconductor substrate 110 will be increased, resulting in a reduction in the bandwidth of the photodetector and the photoelectric conversion response rate of the photodetector. decline.
  • FIGS. 2a to 2c are schematic structural diagrams showing a photodetector 200 according to an embodiment of the present disclosure.
  • the photodetector 200 includes:
  • n-type semiconductor substrate 210 having opposing first and second surfaces
  • the light absorption layer 220 and the semiconductor layer 230 are sequentially stacked on the first surface of the n-type semiconductor substrate 210;
  • the p-type doped region 240 is located in the semiconductor layer 230.
  • the p-type doped region 240 extends from the top surface of the semiconductor layer 230 toward the light absorbing layer 220 and contacts the light absorbing layer 220;
  • the p-type doped region 240 includes a body 241 , the first protrusion 242 and the second protrusion 243; wherein, the first protrusion 242 and the second protrusion 243 are located on opposite sides of the body 241; along the direction parallel to the light absorbing layer 220, the first protrusion 242 Protrudes in a direction away from the second protrusion 243, and the second protrusion 243 protrudes in a direction away from the first protrusion 242;
  • the p-type contact layer 250 is located on the p-type doped region 240 and contacts the p-type doped region 240;
  • the first electrode layer 261 covers and contacts the p-type contact layer 250; the p-type contact layer 250 is used to reduce the contact resistance between the first electrode layer 261 and the p-type doped region 240;
  • the second electrode layer 262 covers and contacts the second surface of the n-type semiconductor substrate 210, and exposes at least part of the second surface; wherein at least part of the exposed second surface is used to receive incident light signals.
  • the first surface may be the upper surface of the n-type semiconductor substrate 210
  • the second surface may be the lower surface of the n-type semiconductor substrate 210
  • the first surface may be a side surface of the n-type semiconductor substrate 210 away from the second electrode layer 262
  • the second surface may be a side surface of the n-type semiconductor substrate 210 close to the second electrode layer 262 . No further details will be given later.
  • the constituent materials of the n-type semiconductor substrate 210, the light absorbing layer 220, the semiconductor layer 230 and the p-type contact layer 250 may include: elemental semiconductor materials (such as silicon, germanium), group III-V compound semiconductor materials (such as Indium phosphide, indium gallium arsenide, gallium nitride), II-VI compound semiconductor materials, organic semiconductor materials or other semiconductor materials known in the art.
  • elemental semiconductor materials such as silicon, germanium
  • group III-V compound semiconductor materials such as Indium phosphide, indium gallium arsenide, gallium nitride
  • II-VI compound semiconductor materials organic semiconductor materials or other semiconductor materials known in the art.
  • Semiconductor materials can be doped differently to form n-type semiconductor materials or p-type semiconductor materials.
  • the hole concentration in p-type semiconductor materials is much greater than the free electron concentration.
  • the holes are the majority carriers, and the free electrons are the minority carriers.
  • the holes are mainly used as carriers to conduct electricity.
  • the concentration of free electrons in n-type semiconductor materials is much greater than the concentration of holes. Free electrons are majority carriers, and holes are minority carriers. Free electrons are mainly used as carriers to conduct electricity.
  • the light absorbing layer 220 may include an intrinsic semiconductor, or an i-type semiconductor with a very small doping concentration that is close to an intrinsic semiconductor.
  • the light absorbing layer 220 may include n-type doped or p-type doped indium gallium arsenide (InGaAs) material, the doping concentration may be less than 5 ⁇ 1015 cm ⁇ 3 , and the thickness may be 1.0 ⁇ m to 3.5 ⁇ m.
  • InGaAs indium gallium arsenide
  • the semiconductor layer 230 may include an intrinsic semiconductor, or a material with a very small doping concentration close to an intrinsic semiconductor.
  • the semiconductor layer 230 may be p-type doped indium phosphide (InP), the doping concentration may be less than 5 ⁇ 1015 cm ⁇ 3 , and the thickness may be 0.5 ⁇ m to 1.5 ⁇ m.
  • the p-type doped region 240 is formed by doping a local region of the semiconductor layer 230 (the preset region of the p-type doped region 240), and is located in the semiconductor layer 230.
  • the doping concentration of the p-type doped region 240 is higher than the doping concentration of the semiconductor layer 230 outside the p-type doped region 240 .
  • the dotted line shown in FIG. 2a is only used to distinguish the body 241 of the p-type doped region 240, the first protrusion 242 and the second protrusion 243. It needs to be emphasized that in actual photoelectric detection, In the device 200, the dotted line does not exist.
  • the body 241 of the p-type doped region 240 extends from the top surface of the semiconductor layer 230 toward the semiconductor layer 230 along the z direction and contacts the light absorbing layer 220 .
  • the first protrusion 242 can take the dotted line as the starting point of extension and extend and protrude in the positive direction of the x-axis; the second protrusion 243 can take the dotted line as the starting point of extension and extend and protrude in the negative direction of the x-axis, that is, away from the first protrusion 242 .
  • the direction of the protrusion 242 extends and protrudes.
  • the first protrusion 242 and the second protrusion 243 are located at an end of the body 241 of the p-type doped region 240 relatively away from the light absorption layer 220 , and the first protrusion 242 and the second protrusion 243 are not in contact with the light absorption layer 220 .
  • the active area of the photodetector in this embodiment can be equivalent to the contact area between the body 241 of the p-type doped region 240 and the light absorption layer 220 . It can be understood that the first protrusion 242 and the second protrusion 243 expand the top area of the p-type doped region 240 without increasing the contact area between the body 241 and the light absorption layer 220, which is beneficial to maintaining the photodetector. The high bandwidth is beneficial to maintaining good fast response performance of the photodetector.
  • the first protrusion 242 and the second protrusion 243 can provide an x-direction (lateral) expansion area for the electrons, so that the electrons move along the first protrusion 242 and the second protrusion 243 .
  • the protrusions 243 expand to improve the lateral current expansion performance of the p-type doped region 240, which can reduce the ESD current density carried by the p-type doped region 240 per unit area and reduce ESD damage.
  • the p-type contact layer 250 may have a relatively high doping concentration.
  • the doping concentration of the p-type contact layer 250 may be greater than 1 ⁇ 1019 cm ⁇ 3 .
  • the p-type contact layer 250 may include indium gallium arsenide material, and may have a thickness of 0.05 ⁇ m to 0.2 ⁇ m.
  • the p-type contact layer 250 is disposed between the p-type doped region 240 and the first electrode layer 261 to couple the p-type doped region 240 and the first electrode layer 261 .
  • the p-type contact layer 250 has a narrow bandgap, and can form a good ohmic contact layer when in contact with metal, thereby effectively reducing the contact resistance of the chip.
  • the incident light in this embodiment is incident from the bottom of the photodetector 200 , that is, incident along one end of the second electrode layer 262 , and is absorbed by the light absorption layer 220 to generate a photocurrent.
  • the first electrode layer 261 in this embodiment may include a continuous film layer structure, that is, no openings and other structures are provided in the middle area of the first electrode layer 261.
  • the area of the first electrode layer 261 can be increased (for example, the area of the first electrode layer 261 can be larger than the area of the first electrode ring 171).
  • the first electrode layer 261 may cover part of the semiconductor layer 230 or cover the entire semiconductor layer 230 .
  • the area of the first electrode layer 261 is larger than the area of the first electrode ring 171 , under the action of a current of the same intensity (for example, an ESD-induced current), the current carried by the first electrode layer 261 per unit area
  • the density can be smaller than the charge density carried by the first electrode ring per unit area, thereby reducing the probability of electrostatic discharge in the first electrode layer 261, reducing ESD damage, and maintaining good stability of the photodetector.
  • the second electrode layer 262 is disposed on the second surface of the n-type semiconductor substrate 210 and exposes at least a partial area of the n-type semiconductor substrate so that the incident light signal passes through the exposed second surface of the n-type semiconductor substrate 210 , reaches the light absorbing layer 220. After absorbing the incident light signal, the light absorbing layer 220 generates photogenerated carriers, thereby generating photogenerated current.
  • a p-type contact layer contacting the p-type doped region and a first electrode layer covering and contacting the p-type contact layer are provided on the p-type doped region.
  • the first electrode layer in the embodiment of the present disclosure has a larger area. Under the action of the same intensity of current, the first electrode layer carries The current density is smaller, reducing electrostatic discharge damage.
  • the embodiments of the present disclosure can improve the lateral current expansion performance of the p-type doped region and reduce the unit flow of the p-type doped region through the first protrusion and the second protrusion located on opposite sides of the p-type doped region body. ESD current density carried on the area, thereby reducing ESD damage to the photodetector.
  • the photodetector 200 further includes:
  • the protective layer 270 covers the semiconductor layer 230 and exposes the first electrode layer 261.
  • the protective layer 270 covers the semiconductor layer 230 to reduce oxidation of the semiconductor layer 230 and maintain good performance of the photodetector.
  • the protective layer 270 may include an opening, and the first electrode layer 261 may be exposed from the opening to facilitate interconnection with external devices or circuits.
  • the protective layer 270 can also serve as a doping barrier layer in the doping process of the semiconductor layer 230, thereby adjusting the range of the p-type doped region 240.
  • the opening size of the protective layer 270 can be adjusted through an etching process, and the semiconductor layer 230 under the opening can be doped.
  • the semiconductor layer 230 covered by the protective layer 270 will not come into contact with the doping element and be doped, or doped.
  • the impurity concentration is so low that it can be ignored.
  • the doping process may include: ion implantation or diffusion.
  • the constituent materials of the protective layer 270 include but are not limited to: insulating materials such as silicon dioxide, silicon nitride, silicon oxynitride, or any combination thereof.
  • the protective layer 270 may have a thickness of of silicon nitride with a thickness of A composite film layer of silicon dioxide, in which silicon nitride covers and contacts the semiconductor layer 230 , and the silicon oxide is located on a surface of the silicon nitride away from the semiconductor layer 230 .
  • the photodetector further includes an n-type buffer layer 280.
  • the n-type buffer layer 280 may be made of the same material as the n-type semiconductor substrate 210, such as indium phosphide material.
  • the n-type buffer layer 280 may be an epitaxial layer grown using an epitaxial process based on the first surface of the n-type semiconductor.
  • the doping concentration of the n-type buffer layer 280 may include: 1 ⁇ 1017 cm -3 to 1.5 ⁇ 1017 cm -3 , and the thickness may include: 1.0 ⁇ m to 2.0 ⁇ m.
  • the n-type semiconductor substrate 210 may include a wafer with a relatively thick thickness, typically reaching a thickness of 680 ⁇ m to 750 ⁇ m.
  • the n-type semiconductor substrate 210 can be thinned to a thickness of 130 ⁇ m to 170 ⁇ m, so that the incident light signal can pass through the n-type semiconductor substrate and reach the light absorption layer 220 .
  • the n-type buffer layer 280 has a sufficient doping concentration to maintain good performance of the photodetector.
  • the second electrode layer 262 includes an opening that exposes the n-type semiconductor substrate 210; wherein the orthographic projection of the opening on the n-type semiconductor substrate 210 is located in the p-type doped region 240 in the n-type semiconductor substrate 210. in orthographic projection on the semiconductor substrate 210 .
  • the second electrode layer 262 may be a single continuous material layer covering the n-type semiconductor substrate 210 .
  • the second electrode layer 262 includes openings on the second surface of the n-type semiconductor substrate 210 . It can be exposed from the opening, so that the incident light signal reaches the second surface of the n-type semiconductor substrate 210 through the opening, and then penetrates the n-type semiconductor substrate 210 and the n-type buffer layer 280 to reach the light absorption layer 220.
  • the absorbing layer 220 generates photocurrent after absorbing incident light, completing the conversion of optical signals into electrical signals.
  • This embodiment only shows one opening. This embodiment does not limit the number of openings. For example, the number of openings may include: 1, 2, 3 or more.
  • holes in the p-type doped region 240 and electrons in the n-type semiconductor substrate 210 are in a depleted state in the light absorption layer 220 .
  • the light absorbing layer 220 absorbs the incident light signal, it generates photogenerated carriers (including electrons and holes), and the photogenerated carriers can move under the action of the internal electric field to generate photocurrent.
  • the electrons can move in the direction from the first electrode layer 261 to the second electrode layer 262 to generate a photocurrent.
  • the first electrode layer 261 and the second electrode layer 262 form paths with external devices or circuits to extract the photocurrent generated by the light absorbing layer 220 in order to detect current direction, intensity and other parameters.
  • the portion of the light absorption layer 220 that is in contact with the p-type doped region 240 participates in the construction of a current path inside the photodetector.
  • the light absorbing layer 220 located below the p-type doped region 240 can be more quickly drawn out by the first electrode layer 261 after the photocurrent is formed, and has a higher photoelectric conversion rate and sensitivity. .
  • the orthographic projection of the opening of the second electrode layer 262 on the n-type semiconductor substrate 210 may fall within the orthographic projection of the p-type doped region 240 on the n-type semiconductor substrate 210 .
  • As much of the incident light signal as possible can enter the light absorption layer 220 region below the p-type doped region 240 through the opening, thereby increasing the photoelectric conversion rate of the photodetector and improving the sensitivity of the photodetector.
  • the second electrode layer 262 may be a continuous material layer that does not include openings, and the area of the second electrode layer 262 is smaller than the area of the second surface of the n-type semiconductor substrate 210, so that the second electrode layer 262 may be a continuous material layer without openings.
  • Layer 262 may expose a portion of the second surface of n-type semiconductor substrate 210 .
  • the second electrode layer 262 may include a plurality of second electrodes arranged side by side along a direction parallel to the n-type semiconductor substrate 210 . A partial area of the second surface of the n-type semiconductor substrate 210 is exposed from the gaps of the plurality of second electrodes so as to receive incident light signals.
  • the partial area of the second surface of the n-type semiconductor substrate 210 exposed by the second electrode layer 262, and the orthographic projection on the n-type semiconductor substrate 210 may be located in the p-type doped region 240 on the n-type semiconductor substrate. In the orthographic projection of the bottom. Therefore, as much of the incident light signal as possible can enter the light absorption layer 220 below the p-type doped region 240 through this partial region, thereby improving the photoelectric conversion rate of the photodetector.
  • the photodetector further includes:
  • the anti-reflection layer 290 is located on the second surface of the n-type semiconductor substrate 210; wherein the second electrode layer 262 exposes the anti-reflection layer 290.
  • the anti-reflection layer 290 can be disposed in the opening of the second electrode layer 262 in FIG. 2b.
  • the anti-reflection layer 290 and the second electrode layer 262 can cover the second surface of the n-type semiconductor substrate 210, reducing the amount of the n-type semiconductor substrate. Oxidation of the second surface of bottom 210.
  • the anti-reflection layer 290 can reduce the reflection of the incident light signal, so that more of the incident light signal can pass through the n-type semiconductor substrate 210 to achieve the anti-reflection function.
  • the constituent materials of the n-type semiconductor substrate 210 and the semiconductor layer 230 include: indium phosphide;
  • composition materials of the light absorption layer 220 and the p-type contact layer 250 include: indium gallium arsenic material;
  • the constituent materials of the first electrode layer 261 and the second electrode layer 262 include: titanium, platinum, gold or combinations thereof;
  • composition material of the anti-reflection layer 290 includes: silicon oxide, silicon nitride or a combination thereof.
  • indium phosphide Compared with other common silicon and germanium semiconductor materials, indium phosphide (InP) has a direct band gap structure, high photoelectric conversion efficiency, high electron mobility, and high operating temperature (for example, the maximum operating temperature can reach 400°C to 450°C ), strong radiation resistance and other advantages. Therefore, indium phosphide is often used in photoelectric conversion devices.
  • the n-type semiconductor substrate 210 and the semiconductor layer 230 may be made of indium phosphide to improve the photoelectric conversion efficiency of the photodetector.
  • Indium gallium arsenide which can include the ternary compound In1-xGaxAs, is a direct band gap semiconductor material of Group III-V and can be formed by mixing InAs and GaAa.
  • Indium gallium arsenide material has high mobility and good radiation resistance. It can usually be used to prepare short-wave infrared detectors for detecting optical signals with wavelengths ranging from 900nm to 1700nm. In optical fiber communications, commonly used communication wavelengths may include 800nm to 1600nm, such as 850nm, 1310nm or 1550nm.
  • the light absorption layer 220 of this embodiment is preferably made of indium gallium arsenide material, which can detect a variety of commonly used optical signals for optical fiber communications and expand the operating wavelength range of the photodetector.
  • the p-type contact layer 250 of this embodiment is preferably made of indium gallium arsenide material, which not only reduces the contact resistance between the first electrode layer 261 and the p-type doped region 240, but also The adhesion between the first electrode layer 261 and the p-type doped region 240 can be increased to maintain good stability of the photodetector.
  • the first electrode layer 261 may preferably be stacked in sequence with a thickness of Titanium (Ti), of platinum (Pt) and Composite layer of gold (Au). Titanium is in direct contact with the p-type contact layer 250. Titanium has good compatibility with the indium gallium arsenide material of the p-type contact layer 250, which increases the adhesion between the first electrode layer 261 and the p-type contact layer 250. Platinum and titanium have good compatibility, and gold and platinum have good compatibility. While reducing the total resistance of the first electrode layer 261, it can also increase the adhesion between the various material layers and increase the first electrode layer's compatibility. 261 mechanical strength.
  • the composition material of the second electrode layer 262 may be the same as the first electrode layer 261 , wherein the titanium in the second electrode layer 262 may be in contact with the second surface of the n-type semiconductor substrate 210 .
  • the anti-reflection layer 290 of different materials has different reflectivity and transmittance for incident optical signals of different wavelengths.
  • the anti-reflection layer 290 may have a thickness of to Silicon oxide has a small reflectivity and a large transmittance for the incident light signal with a wavelength of 1.55 ⁇ m, which can increase the transmission of the incident light signal.
  • the anti-reflection layer 290 may also have a thickness of to Silicon nitride has a small reflectivity and a large transmittance for the incident light signal with a wavelength of 1.31 ⁇ m, which can increase the transmission of the incident light signal.
  • the doping element of the p-type doped region 240 includes zinc.
  • the semiconductor layer 230 is p-type doped, and the doping elements may include boron, gallium, indium or zinc elements.
  • the semiconductor layer 230 includes indium phosphide material.
  • the zinc element has a large diffusion coefficient in indium phosphide, which facilitates the diffusion of doping elements in the semiconductor layer 230 and increases the doping elements in the p-type doping region 240 distribution uniformity.
  • FIG. 3 is a schematic flowchart illustrating a method of manufacturing a photodetector according to an embodiment of the present disclosure.
  • 4a to 4e are schematic diagrams illustrating a method of manufacturing a photodetector according to an embodiment of the present disclosure. As shown in Figure 3 and Figure 4a to Figure 4e, the manufacturing method may include the following steps:
  • an n-type semiconductor substrate 210 is provided.
  • the n-type semiconductor substrate 210 has opposite first and second surfaces;
  • S200 Referring to FIG. 4b, form a sequentially stacked light absorption layer 220, a semiconductor layer 230 and a p-type contact layer 250 on the first surface of the n-type semiconductor substrate 210; wherein, the p-type contact layer 250 covers the semiconductor layer. at least part of 230;
  • S300 Referring to FIG. 4c, form a p-type doped region 240 in the semiconductor layer 230 below the p-type contact layer 250; wherein the p-type doped region 240 extends from the top surface of the semiconductor layer 230 to the light absorption layer 220.
  • the p-type doped region 240 includes a body 241, a first protrusion 242 and a second protrusion 243; the first protrusion 242 and the second protrusion 243 are located on opposite sides of the body 241; Along the direction parallel to the light absorbing layer 220, the first protrusion 242 protrudes in a direction away from the second protrusion 243, and the second protrusion 243 protrudes in a direction away from the first protrusion 242;
  • S400 Referring to FIG. 4d, form a first electrode layer 261 covering and contacting the p-type contact layer 250; wherein, the p-type contact layer 250 is used to reduce the contact resistance between the first electrode layer 261 and the p-type doped region 240;
  • S500 Referring to FIG. 4e, form a second electrode layer 262 on the second surface of the n-type semiconductor substrate 210; wherein the second electrode layer 262 is in contact with the second surface and exposes at least part of the second surface, At least a portion of the exposed second surface is used to receive incident light signals.
  • the intrinsic semiconductor substrate may be n-type doped to form an n-type semiconductor substrate 210.
  • the intrinsic indium phosphide substrate is n-type doped, and the n-type doping elements may include nitrogen, phosphorus or arsenic elements.
  • the formation process of the light absorbing layer 220, the semiconductor layer 230 and the p-type contact layer 250 may include any process known in the art, such as a low-temperature chemical vapor deposition process, a low-pressure chemical vapor deposition process, and a rapid thermal chemical vapor deposition process. process, atomic layer deposition process or plasma enhanced chemical vapor deposition process, etc.
  • a p-type contact material layer covering the entire semiconductor layer 230 is formed, and the p-type contact material layer is etched to form a layer as shown in Figure 4b
  • the p-type contact layer 250 covers at least part of the semiconductor layer 230 .
  • the doping process of the p-type doped region 240 may include: ion implantation or diffusion.
  • heat treatment is performed on the p-type doped region 240 to make the distribution of doping elements in the p-type doped region 240 more uniform.
  • the formation process of the first electrode layer 261 and the second electrode layer 262 may include: chemical vapor deposition, physical deposition, and electron beam evaporation coating.
  • S200 also includes: forming an n-type buffer layer 280 on the first surface of the n-type semiconductor substrate 210, and forming sequentially stacked light absorbing layers on the n-type buffer layer 280. layer 220 , semiconductor layer 230 and p-type contact layer 250 .
  • the method before forming the p-type doped region 240, the method further includes:
  • a dielectric material 270' is formed on the semiconductor layer 230; wherein the dielectric material 270' covers the semiconductor layer 230 and the p-type contact layer 250;
  • Forming p-type doped region 240 includes:
  • a first etching is performed on the dielectric material 270' to form a first opening to expose the p-type contact layer 250, and the semiconductor layer 230 under the first opening is first doped;
  • a second etching is performed on the dielectric material 270', the first opening is expanded in a direction parallel to the n-type semiconductor substrate 210 to form a second opening, and the semiconductor layer 230 below the second opening is etched.
  • the remaining dielectric material 270&apos forms a protective layer 270; wherein the protective layer 270 covers the semiconductor layer 230 and exposes the p-type contact layer 250.
  • a dielectric material 270' covering the semiconductor layer 230 and the p-type contact layer 250 is deposited on the semiconductor layer 230.
  • the dielectric material 270' may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.
  • a first etching is performed on the dielectric material 270' to form a first opening exposing the p-type contact layer 250.
  • the remaining dielectric material 270' is used as a doping barrier layer, and the dielectric material 270' under the first opening is etched.
  • the semiconductor layer 230 is p-type doped.
  • the doping process may include: ion implantation or diffusion, and the doping element includes zinc.
  • the doped region formed in FIG. 4g may extend from the upper surface of the semiconductor layer 230 to the semiconductor layer 230 and be in contact with the semiconductor layer 230.
  • the doping element can diffuse into the semiconductor layer 230 through the p-type contact layer 250, and the p-type doped region 240 and the p-type contact layer 250 have the same doping type, so the doping element passes through the p-type contact Layer 250 does not degrade the performance of p-type contact layer 250.
  • the doped region in Figure 4g can be defined as the body 241 of the p-type doped region 240 in Figure 4c.
  • a second etching is performed on the remaining layer of dielectric material 270' in Figure 4g to enlarge the first opening in the x-direction to form a second opening as shown in Figure 4c.
  • the second opening may expose the p-type contact layer 250 and part of the semiconductor layer 230.
  • the semiconductor layer 230 under the second opening is secondly doped to form a top of the p-type doped region 240.
  • the first protrusion 242 and the second protrusion 243 shown in Figure 4c. In the x direction, the first protrusion 242 protrudes in a direction away from the second protrusion 243 , and the second protrusion 243 protrudes in a direction away from the first protrusion 242 .
  • the remaining dielectric material 270' forms the protective layer 270 shown in Figures 2b and 2c to reduce oxidation of the semiconductor layer 230.
  • the first protrusion 242 and the second protrusion 243 can provide electrons with an x-direction (lateral) expansion area, so that the electrons move along the first protrusion 242 and the second protrusion.
  • 243 is expanded to improve the lateral current expansion performance of the p-type doped region 240, which can reduce the ESD current density carried by the p-type doped region 240 per unit area and reduce ESD damage.
  • the first etching process may include dry etching, wet etching, or any combination thereof.
  • the second etching process may be the same as the first etching process.
  • the first doping process and the second doping process may be the same, and the doping elements may be the same, and may include zinc.
  • the method further includes:
  • An opening is formed on the second electrode layer 262; wherein the opening exposes the n-type semiconductor substrate 210; the orthographic projection of the opening on the n-type semiconductor substrate 210 is located in the p-type doped region 240 on the n-type semiconductor substrate 210 in the orthographic projection.
  • a conductive material can be used to first form a second electrode material layer 262' covering the entire second surface of the n-type semiconductor substrate 210, and the second electrode material layer 262' can be etched to form openings to expose the n-type semiconductor substrate. 210, as shown in Figure 4i.
  • the orthographic projection of the opening on the n-type semiconductor substrate 210 can fall within the orthographic projection of the p-type doped region 240 on the n-type semiconductor substrate 210, so that as much of the incident light signal as possible can be
  • the photoelectric conversion rate of the photodetector is increased, and the sensitivity of the photodetector is improved.
  • the method before forming the second electrode layer 262, the method further includes:
  • An anti-reflection layer 290 is formed on the second surface of the n-type semiconductor substrate 210, and the area of the anti-reflection layer 290 is less than or equal to the area of the second surface;
  • forming the second electrode layer 262 includes:
  • a second electrode layer 262 is formed covering the second surface and exposing the antireflection layer 290 .
  • the second surface of the n-type semiconductor substrate 210 shown in FIG. 4d can be thinned.
  • the thickness of the thinned n-type semiconductor substrate 210 is 130 ⁇ m to 170 ⁇ m, which facilitates incident light to pass through.
  • the n-type semiconductor substrate 210 is absorbed by the light absorbing layer 220 .
  • the thinning process may include: dry etching, wet etching, wheel grinding or chemical mechanical grinding, etc.
  • the anti-reflective material layer covering the entire second surface of the n-type semiconductor substrate 210 is deposited.
  • the anti-reflective material layer may include: silicon oxide or silicon nitride, with a thickness of to
  • Coat photoresist 291 on the anti-reflection material layer expose and develop the photoresist 291, and use the patterned photoresist 291 as a mask to etch the anti-reflection material layer to form an anti-reflection layer as shown in Figure 4h 290. It should be emphasized that after development, etching and other processes, the photoresist 291 is still left covering the anti-reflection layer 290 .
  • a deposition or electron beam evaporation coating process is used to form a second electrode material layer 262' covering the second surface of the n-type semiconductor substrate 210 and the photoresist 291.
  • a stripping process is performed to clean and remove the photoresist 291 to peel off the second electrode material layer 262' covering the photoresist 291, and the remaining second electrode material layer 262' forms the second electrode layer 262 as shown in Figure 2c.
  • the second electrode layer 262 formed may include layers stacked in sequence with a thickness of Titanium (Ti), of platinum (Pt) and Gold (Au), wherein titanium is in contact with the n-type semiconductor substrate 210 (indium phosphide substrate), increasing the adhesion between the second electrode layer 262 and the n-type semiconductor substrate 210.
  • Platinum and titanium have good compatibility, and gold and platinum have good compatibility. While reducing the total resistance of the second electrode layer 262, it can also increase the adhesion between the various material layers and increase the second electrode layer's compatibility. 262 mechanical strength.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Light Receiving Elements (AREA)

Abstract

本公开的实施例公开了一种光电探测器及其制作方法。该光电探测器包括：n型半导体衬底，具有相对的第一表面和第二表面；光吸收层以及半导体层，依次层叠设置于n型半导体衬底的第一表面上；p型掺杂区域，位于半导体层中，p型掺杂区域从半导体层的顶表面向光吸收层延伸、并与光吸收层接触；p型掺杂区域包括本体、第一凸起和第二凸起；第一凸起和第二凸起位于本体相对设置的两侧；沿平行于光吸收层的方向，第一凸起朝背离第二凸起的方向突出，第二凸起朝背离第一凸起的方向突出；p型接触层，位于p型掺杂区域上，且接触p型掺杂区域；第一电极层，覆盖并接触p型接触层；第二电极层，覆盖并接触n型半导体衬底的第二表面，且暴露第二表面的至少部分区域。根据本公开的实施例的光电探测器减小了静电放电损伤。

Description

光电探测器及其制作方法 技术领域
本公开的实施例涉及半导体技术领域，特别涉及一种光电探测器及其制作方法。
背景技术
在光纤通信系统中，光电探测器作为一种光接收芯片被广泛应用，其通过将光信号转换为电信号而实现光信号的长距离传输。
随着光纤通信传输速率的不断提高，光电探测器的响应时间也越来越快速。在具有快速响应时间的光电探测器进行光电信号转换的过程中，光电探测器内部或者外部使用环境所造成的静电放电(Electro-Static Discharge，ESD)，会对光电探测器的器件造成损伤，降低光电探测器的稳定性。因此，如何减少静电放电对光电探测器的损伤成为亟待解决的问题。
发明内容
有鉴于此，本公开的实施例提供一种光电探测器及其制作方法。
根据本公开的实施例的第一方面，提供一种光电探测器，包括：
n型半导体衬底，具有相对的第一表面和第二表面；
光吸收层以及半导体层，依次层叠设置于所述n型半导体衬底的所述第一表面上；
p型掺杂区域，位于所述半导体层中，所述p型掺杂区域从所述半导体层的顶表面向所述光吸收层延伸、并与所述光吸收层接触；所述p型掺杂区域包括本体、第一凸起和第二凸起；其中，所述第一凸起和所述第二凸起位于所述本体相对设置的两侧；沿平行于所述光吸收层的方向，所述第一凸起朝背离所述第二凸起的方向突出，所述第二凸起朝背离所述第一凸起的方向突出；
p型接触层，位于所述p型掺杂区域上，且接触所述p型掺杂区域；
第一电极层，覆盖并接触所述p型接触层；其中，所述p型接触层用以 减少所述第一电极层与所述p型掺杂区域的接触电阻；
第二电极层，覆盖并接触所述n型半导体衬底的所述第二表面，且暴露所述第二表面的至少部分区域；其中，所述暴露的所述第二表面的至少部分区域用于接收入射光信号。
在一些实施例中，所述光电探测器还包括：
保护层，覆盖所述半导体层、且暴露所述第一电极层。
在一些实施例中，所述第二电极层包括开孔，所述开孔暴露所述n型半导体衬底；其中，所述开孔在所述n型半导体衬底上的正投影，位于所述p型掺杂区域在所述n型半导体衬底上的正投影内。
在一些实施例中，所述光电探测器还包括：
增透层，位于所述n型半导体衬底的所述第二表面上；其中，所述第二电极层暴露所述增透层。
在一些实施例中，所述n型半导体衬底和所述半导体层的组成材料包括：磷化铟；
所述光吸收层和所述p型接触层的组成材料包括：铟镓砷材料；
所述第一电极层和所述第二电极层的组成材料包括：钛、铂、金或者其组合；
所述增透层的组成材料包括：氧化硅、氮化硅或者其组合。
在一些实施例中，所述p型掺杂区域的掺杂元素包括：锌。
根据本公开的实施例的第二方面，提供一种光电探测器的制作方法，包括：
提供n型半导体衬底，所述n型半导体衬底具有相对的第一表面和第二表面；
在所述n型半导体衬底的所述第一表面上形成依次层叠设置的光吸收层、半导体层以及p型接触层；其中，所述p型接触层覆盖所述半导体层的至少部分区域；
在所述p型接触层下方的所述半导体层中形成p型掺杂区域；其中，所述p型掺杂区域从所述半导体层的顶表面向所述光吸收层延伸、并与所述光吸收层接触；所述p型掺杂区域包括本体、第一凸起和第二凸起；所述第一凸起和所述第二凸起位于所述本体相对设置的两侧；沿平行于所述光吸收层的方向，所述第一凸起朝背离所述第二凸起的方向突出，所述第二凸起朝背 离所述第一凸起的方向突出；
形成覆盖并接触所述p型接触层的第一电极层；其中，所述p型接触层用以减少所述第一电极层与所述p型掺杂区域的接触电阻；
在所述n型半导体衬底的所述第二表面上形成第二电极层；其中，所述第二电极层与所述第二表面接触，且暴露所述第二表面的至少部分区域，所述暴露的所述第二表面的至少部分区域用于接收入射光信号。
在一些实施例中，在形成所述p型掺杂区域之前，所述方法还包括：
在所述半导体层上形成介电材料；其中，所述介电材料覆盖所述半导体层和所述p型接触层；
形成所述p型掺杂区域包括：
对所述介电材料进行第一蚀刻形成第一开口，以暴露所述p型接触层，对所述第一开口下方的所述半导体层进行第一掺杂；
对所述介电材料进行第二蚀刻，在平行于所述n型半导体衬底的方向上扩大所述第一开口以形成第二开口，对所述第二开口下方的所述半导体层进行第二掺杂，以形成所述p型掺杂区域；
执行所述第二蚀刻之后，剩余的所述介电材料形成保护层；其中，所述保护层覆盖所述半导体层且暴露所述p型接触层。
在一些实施例中，所述方法还包括：
在所述第二电极层上形成开孔；其中，所述开孔暴露所述n型半导体衬底；所述开孔在所述n型半导体衬底上的正投影，位于所述p型掺杂区域在所述n型半导体衬底上的正投影内。
在一些实施例中，在形成所述第二电极层之前，所述方法还包括：
在所述n型半导体衬底的所述第二表面上形成增透层，所述增透层的面积小于或者等于所述第二表面的面积；
形成所述第二电极层包括：
形成覆盖所述第二表面、且暴露所述增透层的所述第二电极层。
本公开的实施例，在p型掺杂区域上，设置接触p型掺杂区域的p型接触层，以及覆盖并接触p型接触层的第一电极层。相较于设置覆盖并接触p型接触环的第一电极环，本公开的实施例的第一电极层与p型掺杂区域具有更大的接触面积，在同一强度的电流作用下，第一电极层单位面积上承载的电流密度更小，有利于减少静电放电(ESD)损伤。并且，本公开的实施例 通过位于p型掺杂区域本体相对两侧的第一凸起和第二凸起，提高p型掺杂区域的侧向电流扩展性能，降低p型掺杂区域单位面积上承载的ESD电流密度，从而减少光电探测器的ESD损伤。本公开的实施例设置第二电极层，暴露n型半导体衬底的第二表面的至少部分区域以接收入射光信号。相较于从第一电极环的中间区域接收入射光信号，本公开的实施例中第一电极层不用于入射光信号的接收，第一电极层的面积不受入射光信号的限制，可进一步增大第一电极层的面积，进一步减少光电探测器的ESD损伤。
附图说明
图1是示出根据一示例性实施例的一种光电探测器的结构示意图；
图2a至图2c是示出根据本公开的实施例的一种光电探测器的结构示意图；
图3是示出根据本公开的实施例的一种光电探测器的制作方法的流程示意图；
图4a至图4i是示出根据本公开的实施例的一种光电探测器的制作方法的示意图。
具体实施方式
在本公开的实施例中，术语“第一”、“第二”等是用于区别类似的对象，而不用于描述特定的顺序或先后次序。
在本公开的实施例中，术语“A与B接触”包含A与B直接接触的情形，或者A、B两者之间还间插有其它部件而A间接地与B接触的情形。
在本公开的实施例中，术语“层”是指包括具有厚度的区域的材料部分。层可以在下方或上方结构的整体之上延伸，或者可以具有小于下方或上方结构范围的范围。此外，层可以是厚度小于连续结构厚度的均质或非均质连续结构的区域。例如，层可位于连续结构的顶表面和底表面之间，或者层可在连续结构顶表面和底表面处的任何水平面对之间。层可以水平、垂直和/或沿倾斜表面延伸。并且，层可以包括多个子层。
可以理解的是，本公开中的“在……上”、“在……之上”和“在……上方”的含义应当以最宽方式被解读，以使得“在……上”不仅表示其“在”某物“上”且其间没有居间特征或层(即直接在某物上)的含义，而且还包 括“在”某物“上”且其间有居间特征或层的含义。
需要说明的是，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施方式中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其它实施方式。
图1是示出根据一示例性实施例的一种光电探测器100的结构示意图。参照图1所示，该光电探测器100包括：
n型半导体衬底110，具有相对的第一表面和第二表面；
光吸收层120、半导体层130，依次层叠设置于n型半导体衬底110的第一表面上；
p型掺杂区域140，位于半导体层130中，该p型掺杂区域140从半导体层130的顶表面向光吸收层120延伸、并与光吸收层120接触；
p型接触环150，位于p型掺杂区域140上，且接触p型掺杂区域140；
透光层160，覆盖半导体层130，且暴露p型接触环150；
第一电极环171，覆盖并接触p型接触环150；
第二电极层172，覆盖并接触n型半导体衬底110的第二表面。
具体的，参照图1所示，在垂直于n型半导体衬底110的z方向上，第一表面可以是n型半导体衬底110的上表面，第二表面可以是n型半导体衬底110的下表面。第一表面可以是n型半导体衬底110远离第二电极层172的一侧表面，第二表面可以是n型半导体衬底110靠近第二电极层172的一侧表面。
光吸收层120的组成材料包括本征半导体，或者掺杂浓度极小、接近于本征半导体的i型半导体。p型掺杂区域140、光吸收层120以及n型半导体衬底110之间形成pin型的光电二极管，三者可构成一个pin结，其中光吸收层120是光信号的主要吸收层。该光电探测器100还可包括n型缓冲层180，位于n型半导体衬底110和光吸收层120之间，n型缓冲层180与n型半导体衬底共同构成pin结的n部分。
示例性的，入射光信号可以从第一电极环171的中间区域入射，穿过位于第一电极环171中间的透光层160、该透光层160下方的p型掺杂区域140到达光吸收层120。光吸收层120吸收入射光信号后，产生光生载流子(包括电子和空穴)，从而产生光电流，使光信号变成电信号，实现光电转换。 光电流可通过第一电极环171和第二电极层172与外部电路连接，以探测光电流的变化来探测光信号的变化。
第一电极环171、第二电极层172的组成材料包括但不限于：钛、铂或者金等导电材料。因此，第一电极环171和第二电极层172的透光率较低或者基本不透光。图1示出的是光电探测器100的剖面图，该实施例的第一电极环171并不是指两个部件，而是一个第一电极环171的剖面图。可以理解的是，沿z方向，第一电极环171在半导体层130的正投影为一个封闭的环形(例如，圆环形或者椭圆环形)。
在一些实施例中，该光电探测器100还包括电极173，与第一电极环171耦接，用于将第一电极环171的电信号引出，与外部封装器件进行电信号互联。
可以理解的是，为了使更多的入射光信号可以被光吸收层120吸收，提高光探测器的灵敏度，缩短光电转换的响应时间，第一电极环171的宽度通常较小，这会导致第一电极环171的面积较小。因此，当第一电极环171上聚集有静电电荷或者通过有光电流时，第一电极环171单位面积上承载的电荷密度较大，会发生静电放电(ESD)现象，对p型掺杂区域140产生ESD损伤，甚至是击穿p型掺杂区域140，导致光电探测器失效。
电子器件对于ESD损伤的敏感性一般可用ESD阈值来测量，阈值越高，器件抗损伤的能力越强。通常，在光电探测器中，ESD阈值与有源面积的大小成正比，有源面积越小，阈值越低，光电探测器就越容易受ESD损伤。参照图1所示，有源面积可以等效为p型掺杂区域140与光吸收层120的接触面积。
在一些实施例中，可以通过扩大p型掺杂区域140以提高有源面积，来增加ESD阈值，以减少ESD损伤。然而，在提高有源面积的同时，会增加p型掺杂区域140与n型半导体衬底110之间的p-n结电容，从而导致光电探测器带宽的减少，使得光电探测器的光电转换响应速率下降。
图2a至图2c是示出根据本公开的实施例的一种光电探测器200的结构示意图。参照图2a所示，所述光电探测器200包括：
n型半导体衬底210，具有相对的第一表面和第二表面；
光吸收层220以及半导体层230，依次层叠设置于n型半导体衬底210的第一表面上；
p型掺杂区域240，位于半导体层230中，p型掺杂区域240从半导体层230的顶表面向光吸收层220延伸、并与光吸收层220接触；p型掺杂区域240包括本体241、第一凸起242和第二凸起243；其中，第一凸起242和第二凸起243位于本体241相对设置的两侧；沿平行于光吸收层220的方向，第一凸起242朝背离第二凸起243的方向突出，第二凸起243朝背离第一凸起242的方向突出；
p型接触层250，位于p型掺杂区域240上，且接触p型掺杂区域240；
第一电极层261，覆盖并接触p型接触层250；其中，p型接触层250用以减少第一电极层261与p型掺杂区域240的接触电阻；
第二电极层262，覆盖并接触n型半导体衬底210的第二表面，且暴露第二表面的至少部分区域；其中，暴露的第二表面的至少部分区域用于接收入射光信号。
具体的，参照图2a所示，在z方向上，第一表面可以是n型半导体衬底210的上表面，第二表面可以使n型半导体衬底210的下表面。第一表面可以是n型半导体衬底210远离第二电极层262的一侧表面，第二表面可以是n型半导体衬底210靠近第二电极层262的一侧表面。后文不再赘述。
示例性的，n型半导体衬底210、光吸收层220、半导体层230以及p型接触层250的组成材料可包括：单质半导体材料(例如硅、锗)、Ⅲ-Ⅴ族化合物半导体材料(例如磷化铟、铟镓砷、氮化镓)、Ⅱ-Ⅵ族化合物半导体材料、有机半导体材料或者本领域已知的其它半导体材料。半导体材料可经过不同掺杂形成n型半导体材料或者p型半导体材料。
p型半导体材料(空穴型半导体材料)中的空穴浓度远大于自由电子浓度，空穴为多数载流子，自由电子为少数载流子，主要靠空穴作为载流子导电。
n型半导体材料(电子型半导体材料)中的自由电子浓度远大于空穴浓度，自由电子为多数载流子，空穴为少数载流子，主要靠自由电子作为载流子导电。
光吸收层220可包括本征半导体，或者掺杂浓度极小、接近于本征半导体的i型半导体。例如，光吸收层220可包括n型掺杂或者p型掺杂的铟镓砷(InGaAs)材料，掺杂浓度可小于5×1015cm -3，厚度可以是1.0μm至3.5μm。
半导体层230可包括本征半导体，或者掺杂浓度极小、接近于本征半导体的材料。例如，半导体层230可为p型掺杂的磷化铟(InP)，掺杂浓度可小于5×1015cm -3，厚度可以是0.5μm至1.5μm。
参照图2a所示，p型掺杂区域240，是通过对半导体层230的局部区域(p型掺杂区域240的预设区域)进行掺杂形成，位于半导体层230中。p型掺杂区域240的掺杂浓度，高于p型掺杂区域240之外的半导体层230的掺杂浓度。
在本实施例中，图2a示出的虚线仅用于区分p型掺杂区域240的本体241、第一凸起242以及第二凸起243的区域，需要强调的是，在实际的光电探测器200中，并不存在该虚线。
p型掺杂区域240的本体241从半导体层230的顶表面，沿着z方向向半导体层230延伸、并与光吸收层220接触。第一凸起242可以以虚线为延伸起点，朝着x轴正方向延伸并突出；第二凸起243可以以虚线为延伸起点，朝着x轴负方向延伸并突出，即朝着背离第一凸起242的方向延伸并突出。第一凸起242和第二凸起243位于p型掺杂区域240的本体241相对远离光吸收层220的一端，第一凸起242和第二凸起243不与光吸收层220接触。
本实施例的光电探测器的有源面积，可等效于p型掺杂区域240的本体241与光吸收层220的接触面积。可以理解的是，第一凸起242和第二凸起243在没有增加本体241与光吸收层220的接触面积的同时，扩大了p型掺杂区域240的顶部区域，有利于维持光电探测器的高带宽，并有利于维持光电探测器的快速响应性能良好。并且，在光电探测器受到ESD电压的影响下，第一凸起242和第二凸起243可以给电子提供x方向(侧向)的扩展区域，使得电子沿着第一凸起242和第二凸起243进行扩展，提高p型掺杂区域240的侧向电流扩展性能，可降低p型掺杂区域240单位面积上承载的ESD电流密度，减少ESD损伤。
相较于光吸收层220与半导体层230的低掺杂浓度，p型接触层250可以具有相对较高的掺杂浓度。例如，p型接触层250的掺杂浓度可大于1×1019cm -3。p型接触层250可包括铟镓砷材料，厚度可包括0.05μm至0.2μm。p型接触层250设置于p型掺杂区域240与第一电极层261之间，耦接p型掺杂区域240与第一电极层261。p型接触层250具有较窄的禁带宽度，其与金属接触时可以形成良好的欧姆接触层，从而有效降低芯片的接 触电阻。
参照图2a所示，本实施例的入射光从光电探测器200的底部入射，即沿着第二电极层262的一端入射，被光吸收层220吸收，产生光电流。相较于图1中的第一电极环171，本实施例中的第一电极层261可包括连续的膜层结构，即在第一电极层261的中间区域并不会设置开孔等结构以使入射光信号通过，由此可以增大第一电极层261的面积(例如，第一电极层261的面积可以大于第一电极环171的面积)。第一电极层261可覆盖部分半导体层230，或者覆盖全部半导体层230。
需要强调的是，当第一电极层261的面积大于第一电极环171的面积时，在同一强度的电流(例如，ESD诱发的电流)作用下，第一电极层261单位面积上承载的电流密度，可小于第一电极环单位面积上承载的电荷密度，降低第一电极层261发生静电放电的几率，减少ESD损伤，维持光电探测器的稳定性良好。
第二电极层262设置在n型半导体衬底210的第二表面上，并且暴露n型半导体衬底的至少部分区域，以便于入射光信号穿过暴露的n型半导体衬底210的第二表面，到达光吸收层220。光吸收层220吸收入射光信号后，产生光生载流子，进而产生光生电流。
本公开的实施例，在p型掺杂区域上，设置接触p型掺杂区域的p型接触层，以及覆盖并接触p型接触层的第一电极层。相较于设置覆盖并接触p型接触环的第一电极环，本公开的实施例的第一电极层具有更大的面积，在同一强度的电流作用下，第一电极层单位面积上承载的电流密度更小，减少静电放电损伤。并且，本公开的实施例通过位于p型掺杂区域本体相对两侧的第一凸起和第二凸起，可提高p型掺杂区域的侧向电流扩展性能，降低p型掺杂区域单位面积上承载的ESD电流密度，从而减少光电探测器的ESD损伤。
在一些实施例中，参照图2b和图2c所示，光电探测器200还包括：
保护层270，覆盖半导体层230、且暴露第一电极层261。
保护层270覆盖半导体层230，减少半导体层230的氧化，维持光电探测器的性能良好。保护层270可包括有开口，第一电极层261可从开口中暴露，以便于与外部器件或者电路互联。
在p型掺杂区域240形成的过程中，保护层270还可作为半导体层230 掺杂工艺中的掺杂阻挡层，以此调节p型掺杂区域240的范围。例如，可以通过蚀刻工艺来调节保护层270的开口大小，对该开口下的半导体层230进行掺杂，被保护层270覆盖的半导体层230并不会接触掺杂元素而被掺杂，或者掺杂浓度很低以至于可以忽略不计。掺杂工艺可包括：离子注入或者扩散。
示例性的，保护层270的组成材料包括但不限于：二氧化硅、氮化硅、氮氧化硅等绝缘材料或者其任意组合。例如，保护层270可以是厚度为
Figure PCTCN2022104075-appb-000001
的氮化硅与厚度为
Figure PCTCN2022104075-appb-000002
的二氧化硅的复合膜层，其中，氮化硅覆盖且接触半导体层230，氧化硅位于氮化硅远离半导体层230的一表面上。
在一些实施例中，参照图2b所示，光电探测器还包括n型缓冲层280。n型缓冲层280可与n型半导体衬底210的材料相同，例如磷化铟材料。n型缓冲层280可以是基于n型半导体的第一表面采用外延工艺生长的外延层。n型缓冲层280的掺杂浓度可包括：1×1017cm -3至1.5×1017cm -3，厚度包括：1.0μm至2.0μm。
可以理解的是，n型半导体衬底210可包括晶圆，厚度较厚，通常厚度可达到680μm至750μm。在一些实施例中，可将n型半导体衬底210减薄到厚度为130μm至170μm，便于入射光信号穿过n型半导体衬底到达光吸收层220。n型半导体衬底210减薄后，n型缓冲层280有足够的掺杂浓度，以维持光电探测器的性能良好。
在一些实施例中，第二电极层262包括开孔，开孔暴露n型半导体衬底210；其中，开孔在n型半导体衬底210上的正投影，位于p型掺杂区域240在n型半导体衬底210上的正投影内。
参照图2a和图2b所示，第二电极层262可以是覆盖n型半导体衬底210的单个连续的材料层，第二电极层262包括有开孔，n型半导体衬底210的第二表面可以从开孔中暴露，以便于使入射光信号通过开孔抵达n型半导体衬底210的第二表面，进而穿透n型半导体衬底210、n型缓冲层280抵达光吸收层220，光吸收层220吸收入射光后产生光电流，完成光信号向电信号的转换。本实施例中仅示出一个开口，本实施例对开孔的数量不作限制，例如，开孔的数量可以包括：1个，2个，3个或者更多个。
参照图2b所示，p型掺杂区域240的空穴与n型半导体衬底210(或者，图2b中的n型缓冲层280)的电子在光吸收层220中处于耗尽状态，在光吸 收层220中可存在电场强度近似为常数的内部电场。光吸收层220吸收入射光信号之后，产生光生载流子(包括电子和空穴)，光生载流子可在该内部电场的作用下运动产生光电流。例如，光吸收层220吸收入射光信号后，电子可以沿着第一电极层261指向第二电极层262的方向运动，产生光电流。
可以理解的是，第一电极层261和第二电极层262与外部器件或者电路形成通路，将光吸收层220产生的光电流引出，以便对电流方向、强度等参数进行检测。光吸收层220与p型掺杂区域240接触的部分，参与光电探测器内部的电流通路的构建。相较于光吸收层220的其他区域，位于p型掺杂区域240下方的光吸收层220，形成光电流后可更快速的被第一电极层261引出，具有更高的光电转换速率和灵敏度。
本实施例中，第二电极层262的开孔在n型半导体衬底210上的正投影，可落在p型掺杂区域240在n型半导体衬底210上的正投影内。可使尽可能多的入射光信号通过开孔进入p型掺杂区域240下方的光吸收层220区域，提高光电探测器的光电转换速率，提高光电探测器的灵敏度。
在另外一些实施例中，第二电极层262可以是不包括有开孔的连续的材料层，第二电极层262的面积小于n型半导体衬底210第二表面的面积，从而使得第二电极层262可以暴露出n型半导体衬底210的第二表面的部分区域。第二电极层262可包括多个第二电极，多个第二电极沿着平行于n型半导体衬底210的方向并列排布。n型半导体衬底210的第二表面的部分区域，从多个第二电极的间隙中暴露，以便于接收入射光信号。
该实施例中，第二电极层262暴露的n型半导体衬底210第二表面的部分区域，在n型半导体衬底210上的正投影，可位于p型掺杂区域240在n型半导体衬底上的正投影内。从而可使尽可能多的入射光信号通过该部分区域进入p型掺杂区域240下方的光吸收层220，提高光电探测器的光电转换速率。
在一些实施例中，参照图2c所示，光电探测器还包括：
增透层290，位于n型半导体衬底210的第二表面上；其中，第二电极层262暴露增透层290。
增透层290可设置于图2b中第二电极层262的开孔中，增透层290与第二电极层262可对n型半导体衬底210的第二表面进行覆盖，减少n型半导体衬底210的第二表面的氧化。增透层290可以减少入射光信号的反射， 以使更多的入射光信号透过n型半导体衬底210，以达到增透功能。
在一些实施例中，n型半导体衬底210和半导体层230的组成材料包括：磷化铟；
光吸收层220和p型接触层250的组成材料包括：铟镓砷材料；
第一电极层261和第二电极层262的组成材料包括：钛、铂、金或者其组合；
增透层290的组成材料包括：氧化硅、氮化硅或者其组合。
相较于其他常见的硅、锗半导体材料，磷化铟(InP)具有直接带隙结构，光电转换效率高，电子迁移率高，工作温度高(例如，最高工作温度可达到400℃至450℃)，抗辐射能力强等优势。因此，磷化铟常应用于光电转换器件中。本实施例中的n型半导体衬底210和半导体层230可优选磷化铟材料，提高光电探测器的光电转换效率。
铟镓砷(InGaAs)，可包括三元化合物In1-xGaxAs,是Ⅲ-Ⅴ族的直接带隙半导体材料，可以由InAs与GaAa混合形成。铟镓砷材料具有高迁移率、良好的抗辐射，通常可用于制备短波红外探测器，用于对波长范围为900nm至1700nm的光信号的探测。光纤通信中，常用的通信波长可包括800nm至1600nm，例如850nm、1310nm或者1550nm。本实施例的光吸收层220优选铟镓砷材料，可对多种常用的光纤通信的光信号进行探测，扩大光电探测器的工作波长范围。
铟镓砷与磷化铟具有较好的相容性，本实施例的p型接触层250优选铟镓砷材料，在减少第一电极层261和p型掺杂区域240接触电阻的同时，还可增加第一电极层261和p型掺杂区域240之间的黏附性，维持光电探测器的稳定性良好。
第一电极层261可优选，依次层叠设置的厚度为
Figure PCTCN2022104075-appb-000003
的钛(Ti)、
Figure PCTCN2022104075-appb-000004
的铂(Pt)以及
Figure PCTCN2022104075-appb-000005
的金(Au)的复合材料层。钛与p型接触层250直接接触，钛与p型接触层250的铟镓砷材料具有较好的相容性，增加第一电极层261与p型接触层250的黏附性。铂与钛具有较好的相容性，金与铂有较好的相容性，降低第一电极层261总电阻的同时，也可增加各个材料层之间的黏附性，增加第一电极层261的机械强度。
第二电极层262的组成材料可与第一电极层261相同，其中，第二电极层262中的钛可与n型半导体衬底210的第二表面接触。
不同材料的增透层290对于不同波长的入射光信号具有不同的反射率以及透射率。例如，增透层290可以是厚度为
Figure PCTCN2022104075-appb-000006
至
Figure PCTCN2022104075-appb-000007
的氧化硅，对于波长1.55μm的入射光信号具有较小的反射率以及较大的透射率，可增大对该入射光信号的透射。还例如，增透层290还可以是厚度为
Figure PCTCN2022104075-appb-000008
至
Figure PCTCN2022104075-appb-000009
的氮化硅，对于波长1.31μm的入射光信号具有较小的反射率以及较大的透射率，可增大对该入射光信号的透射。
在一些实施例中，p型掺杂区域240的掺杂元素包括：锌。
对半导体层230进行p型掺杂，掺杂元素可以包括：硼、镓、铟或者锌元素等。本实施例中半导体层230包括磷化铟材料，锌元素在磷化铟中具有较大的扩散系数，利于掺杂元素在半导体层230中的扩散，提高p型掺杂区域240中掺杂元素的分布均一性。
图3是示出根据本公开的实施例的一种光电探测器的制作方法的流程示意图。图4a至图4e是示出根据本公开的实施例的一种光电探测器的制作方法的示意图。结合图3、图4a至图4e所示，所述制作方法可包括以下步骤：
S100：参照图4a所示，提供n型半导体衬底210，n型半导体衬底210具有相对的第一表面和第二表面；
S200：参照图4b所示，在n型半导体衬底210的第一表面上形成依次层叠设置的光吸收层220、半导体层230以及p型接触层250；其中，p型接触层250覆盖半导体层230的至少部分区域；
S300：参照图4c所示，在p型接触层250下方的半导体层230中形成p型掺杂区域240；其中，p型掺杂区域240从半导体层230的顶表面向光吸收层220延伸、并与光吸收层220接触；p型掺杂区域240包括本体241、第一凸起242和第二凸起243；第一凸起242和第二凸起243位于本体241相对设置的两侧；沿平行于光吸收层220的方向，第一凸起242朝背离第二凸起243的方向突出，第二凸起243朝背离第一凸起242的方向突出；
S400：参照图4d所示，形成覆盖并接触p型接触层250的第一电极层261；其中，p型接触层250用以减少第一电极层261与p型掺杂区域240的接触电阻；
S500：参照图4e所示，在n型半导体衬底210的第二表面上形成第二电极层262；其中，第二电极层262与第二表面接触，且暴露第二表面的至少部分区域，暴露的第二表面的至少部分区域用于接收入射光信号。
具体的，参照图4a所示，可以对本征半导体衬底进行n型掺杂，以形成n型半导体衬底210。例如对本征磷化铟衬底进行n型掺杂，n型掺杂元素可包括：氮、磷或者砷元素等。
示例性的，光吸收层220、半导体层230以及p型接触层250的形成工艺可包括本技术领域所知的任何工艺，例如低温化学气相沉积工艺、低压化学气相沉积工艺、快速热化学气相沉积工艺、原子层沉积工艺或者等离子体增强化学气相沉积工艺等。
在n型半导体衬底210的第一表面上，形成光吸收层220和半导体层230后，形成覆盖整个半导体层230的p型接触材料层，蚀刻p型接触材料层，形成如图4b所示的p型接触层250，其中，p型接触层250覆盖半导体层230的至少部分区域。
示例性的，p型掺杂区域240的掺杂工艺可包括：离子注入或者扩散。
在一些实施例中，形成p型掺杂区域240后，对p型掺杂区域240进行热处理，可使p型掺杂区域240中的掺杂元素分布更加均匀。
第一电极层261和第二电极层262的形成工艺可包括：化学气相沉积、物理沉积、电子束蒸发镀膜。
在一些实施例中，参照图4b所示，S200还包括：在n型半导体衬底210的第一表面上形成n型缓冲层280，在n型缓冲层280上再形成依次层叠设置的光吸收层220、半导体层230以及p型接触层250。
在一些实施例中，在形成p型掺杂区域240之前，所述方法还包括：
参照图4f所示，在半导体层230上形成介电材料270’；其中，介电材料270’覆盖半导体层230和p型接触层250；
形成p型掺杂区域240包括：
参照图4g所示，对介电材料270’进行第一蚀刻形成第一开口，以暴露p型接触层250，对第一开口下方的半导体层230进行第一掺杂；
参照图4c所示，对介电材料270’进行第二蚀刻，在平行于n型半导体衬底210的方向上扩大第一开口以形成第二开口，对第二开口下方的半导体层230进行第二掺杂，以形成p型掺杂区域240；
执行第二蚀刻之后，剩余的介电材料270’形成保护层270；其中，保护层270覆盖半导体层230且暴露p型接触层250。
参照图4f所示，在形成p型掺杂区域240之前，先在半导体层230上 沉积形成覆盖半导体层230和p型接触层250的介电材料270’。介电材料270’可包括：氧化硅、氮化硅、氮氧化硅等绝缘材料或者其任意组合。
参照图4g所示，对介电材料270’进行第一蚀刻，以形成暴露p型接触层250的第一开口，以剩余的介电材料270’为掺杂阻挡层，对第一开口下方的半导体层230进行p型掺杂。掺杂工艺可包括：离子注入或者扩散，掺杂元素包括锌元素。图4g中形成的掺杂区域，可从半导体层230的上表面延伸至半导体层230、且与半导体层230接触。
可以理解的是，掺杂元素可穿过p型接触层250扩散进入半导体层230，而p型掺杂区域240与p型接触层250的掺杂类型相同，所以掺杂元素穿过p型接触层250并不会降低p型接触层250的性能。
可将图4g中的掺杂区域定义为图4c中的p型掺杂区域240的本体241。对图4g中剩余的介电材料270’层进行第二蚀刻，在x方向上扩大第一开口，以形成如图4c所示的第二开口。第二开口可暴露出p型接触层250和部分的半导体层230，沿着第二开口，对第二开口下方的半导体层230进行第二掺杂，以在p型掺杂区域240的顶部形成图4c所示的第一凸起242和第二凸起243。在x方向上，第一凸起242朝背离第二凸起243的方向突出，第二凸起243朝背离第一凸起242的方向突出。
在形成第二开口之后，剩余的介电材料270’形成图2b和图2c所示的保护层270，减少半导体层230的氧化。
在光电探测器受到ESD电压的影响下，第一凸起242和第二凸起243可以给电子提供x方向(侧向)的扩展区域，使得电子沿着第一凸起242和第二凸起243进行扩展，提高p型掺杂区域240的侧向电流扩展性能，可降低p型掺杂区域240单位面积上承载的ESD电流密度，减少ESD损伤。
第一蚀刻工艺可包括：干法蚀刻、湿法蚀刻或者其任意组合。第二蚀刻工艺可与第一蚀刻工艺相同。
第一掺杂和第二掺杂工艺可相同，掺杂元素可相同，可包括锌元素。
在一些实施例中，所述方法还包括：
在第二电极层262上形成开孔；其中，开孔暴露n型半导体衬底210；开孔在n型半导体衬底210上的正投影，位于p型掺杂区域240在n型半导体衬底210上的正投影内。
该实施例中，可利用导电材料先形成覆盖整个n型半导体衬底210第二 表面的第二电极材料层262’，蚀刻第二电极材料层262’形成开孔，以暴露n型半导体衬底210，如图4i所示。
在z方向上，开孔在n型半导体衬底210上的正投影，可落在p型掺杂区域240在n型半导体衬底210上的正投影内，以使尽可能多的入射光信号通过开孔进入p型掺杂区域240下方的光吸收层220区域，提高光电探测器的光电转换速率，提高光电探测器的灵敏度。
在一些实施例中，参照图4h所示，在形成第二电极层262之前，所述方法还包括：
在n型半导体衬底210的第二表面上形成增透层290，增透层290的面积小于或者等于第二表面的面积；
参照图2c所示，形成第二电极层262包括：
形成覆盖第二表面、且暴露增透层290的第二电极层262。
在形成增透层之前，可对图4d所示的n型半导体衬底210的第二表面进行减薄，减薄后的n型半导体衬底210的厚度为130μm至170μm，便于入射光穿过n型半导体衬底210被光吸收层220吸收。减薄工艺可包括：干法蚀刻、湿法蚀刻、轮磨或者化学机械研磨等。
沉积形成覆盖全部n型半导体衬底210的第二表面的增透材料层，增透材料层可包括：氧化硅或者氮化硅，厚度为
Figure PCTCN2022104075-appb-000010
至
Figure PCTCN2022104075-appb-000011
在增透材料层上涂覆光刻胶291，对光刻胶291进行曝光显影，以图案化后的光刻胶291为掩膜蚀刻增透材料层，形成如图4h所示的增透层290。需要强调的是，经过显影、蚀刻等工艺后，还留有光刻胶291覆盖增透层290。
参照图4i所示，利用沉积或者电子束蒸发镀膜工艺，形成覆盖n型半导体衬底210第二表面以及光刻胶291的第二电极材料层262’。执行剥离工艺清洗去除光刻胶291，以剥离覆盖光刻胶291的第二电极材料层262’，剩余的第二电极材料层262’形成如图2c所示的第二电极层262。
本实施例可分多次沉积多个第二电极材料层262’，经过剥离后形成具有多个材料层的第二电极层262，增强第二电极层262的机械强度，减少接触电阻。例如形成的第二电极层262可包括，依次层叠设置的厚度为
Figure PCTCN2022104075-appb-000012
的钛(Ti)、
Figure PCTCN2022104075-appb-000013
的铂(Pt)以及
Figure PCTCN2022104075-appb-000014
的金(Au)，其中，钛与n型半导体衬底210(磷化铟衬底)接触，增加第二电极层262与n型半导体衬底210的黏附性。铂与钛具有较好的相容性，金与铂有较好的相容性，降低第二电 极层262总电阻的同时，也可增加各个材料层之间的黏附性，增加第二电极层262的机械强度。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (10)

  1. 一种光电探测器，其特征在于，包括：
    n型半导体衬底，具有相对的第一表面和第二表面；
    光吸收层以及半导体层，依次层叠设置于所述n型半导体衬底的所述第一表面上；
    p型掺杂区域，位于所述半导体层中，所述p型掺杂区域从所述半导体层的顶表面向所述光吸收层延伸、并与所述光吸收层接触；所述p型掺杂区域包括本体、第一凸起和第二凸起；其中，所述第一凸起和所述第二凸起位于所述本体相对设置的两侧；沿平行于所述光吸收层的方向，所述第一凸起朝背离所述第二凸起的方向突出，所述第二凸起朝背离所述第一凸起的方向突出；
    p型接触层，位于所述p型掺杂区域上，且接触所述p型掺杂区域；
    第一电极层，覆盖并接触所述p型接触层；其中，所述p型接触层用以减少所述第一电极层与所述p型掺杂区域的接触电阻；
    第二电极层，覆盖并接触所述n型半导体衬底的所述第二表面，且暴露所述第二表面的至少部分区域；其中，所述暴露的所述第二表面的至少部分区域用于接收入射光信号。
  2. 根据权利要求1所述的光电探测器，其特征在于，所述光电探测器还包括：
    保护层，覆盖所述半导体层、且暴露所述第一电极层。
  3. 根据权利要求1所述的光电探测器，其特征在于，所述第二电极层包括开孔，所述开孔暴露所述n型半导体衬底；其中，所述开孔在所述n型半导体衬底上的正投影，位于所述p型掺杂区域在所述n型半导体衬底上的正投影内。
  4. 根据权利要求1所述的光电探测器，其特征在于，所述光电探测器还包括：
    增透层，位于所述n型半导体衬底的所述第二表面上；其中，所述第二电极层暴露所述增透层。
  5. 根据权利要求4所述的光电探测器，其特征在于，
    所述n型半导体衬底和所述半导体层的组成材料包括：磷化铟；
    所述光吸收层和所述p型接触层的组成材料包括：铟镓砷材料；
    所述第一电极层和所述第二电极层的组成材料包括：钛、铂、金或者其组合；
    所述增透层的组成材料包括：氧化硅、氮化硅或者其组合。
  6. 根据权利要求1所述的光电探测器，其特征在于，所述p型掺杂区域的掺杂元素包括：锌。
  7. 一种光电探测器的制作方法，其特征在于，包括：
    提供n型半导体衬底，所述n型半导体衬底具有相对的第一表面和第二表面；
    在所述n型半导体衬底的所述第一表面上形成依次层叠设置的光吸收层、半导体层以及p型接触层；其中，所述p型接触层覆盖所述半导体层的至少部分区域；
    在所述p型接触层下方的所述半导体层中形成p型掺杂区域；其中，所述p型掺杂区域从所述半导体层的顶表面向所述光吸收层延伸、并与所述光吸收层接触；所述p型掺杂区域包括本体、第一凸起和第二凸起；所述第一凸起和所述第二凸起位于所述本体相对设置的两侧；沿平行于所述光吸收层的方向，所述第一凸起朝背离所述第二凸起的方向突出，所述第二凸起朝背离所述第一凸起的方向突出；
    形成覆盖并接触所述p型接触层的第一电极层；其中，所述p型接触层用以减少所述第一电极层与所述p型掺杂区域的接触电阻；
    在所述n型半导体衬底的所述第二表面上形成第二电极层；其中，所述第二电极层与所述第二表面接触，且暴露所述第二表面的至少部分区域，所述暴露的所述第二表面的至少部分区域用于接收入射光信号。
  8. 根据权利要求7所述的方法，其特征在于，在形成所述p型掺杂区域之前，所述方法还包括：
    在所述半导体层上形成介电材料；其中，所述介电材料覆盖所述半导体层和所述p型接触层；
    形成所述p型掺杂区域包括：
    对所述介电材料进行第一蚀刻形成第一开口，以暴露所述p型接触层，对所述第一开口下方的所述半导体层进行第一掺杂；
    对所述介电材料进行第二蚀刻，在平行于所述n型半导体衬底的方向上 扩大所述第一开口以形成第二开口，对所述第二开口下方的所述半导体层进行第二掺杂，以形成所述p型掺杂区域；
    执行所述第二蚀刻之后，剩余的所述介电材料形成保护层；其中，所述保护层覆盖所述半导体层且暴露所述p型接触层。
  9. 根据权利要求7所述的方法，其特征在于，所述方法还包括：
    在所述第二电极层上形成开孔；其中，所述开孔暴露所述n型半导体衬底；所述开孔在所述n型半导体衬底上的正投影，位于所述p型掺杂区域在所述n型半导体衬底上的正投影内。
  10. 根据权利要求7所述的方法，其特征在于，在形成所述第二电极层之前，所述方法还包括：
    在所述n型半导体衬底的所述第二表面上形成增透层，所述增透层的面积小于或者等于所述第二表面的面积；
    形成所述第二电极层包括：
    形成覆盖所述第二表面、且暴露所述增透层的所述第二电极层。
PCT/CN2022/104075 2022-04-28 2022-07-06 光电探测器及其制作方法 WO2023206813A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210469403.5 2022-04-28
CN202210469403.5A CN117012774A (zh) 2022-04-28 2022-04-28 光电探测器及其制作方法

Publications (1)

Publication Number Publication Date
WO2023206813A1 true WO2023206813A1 (zh) 2023-11-02

Family

ID=88517119

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/104075 WO2023206813A1 (zh) 2022-04-28 2022-07-06 光电探测器及其制作方法

Country Status (2)

Country Link
CN (1) CN117012774A (zh)
WO (1) WO2023206813A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6515315B1 (en) * 1999-08-05 2003-02-04 Jds Uniphase, Corp. Avalanche photodiode for high-speed applications
US20030137026A1 (en) * 2002-01-21 2003-07-24 Park Chan Yong Avalanche photodiode having an electrically isolated deep guard ring
US20030178636A1 (en) * 2002-02-11 2003-09-25 Jds Uniphase Corporation Back illuminated photodiodes
US20140175511A1 (en) * 2012-12-24 2014-06-26 Electronics And Telecommunications Research Institute Avalanche photodiode
CN105070780A (zh) * 2015-07-30 2015-11-18 中国电子科技集团公司第四十四研究所 一种平面型三阶梯结雪崩光电二极管及制作方法
US20170084773A1 (en) * 2015-09-18 2017-03-23 Princeton Lightwave, Inc. APD Focal Plane Arrays with Backside Vias

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6515315B1 (en) * 1999-08-05 2003-02-04 Jds Uniphase, Corp. Avalanche photodiode for high-speed applications
US20030137026A1 (en) * 2002-01-21 2003-07-24 Park Chan Yong Avalanche photodiode having an electrically isolated deep guard ring
US20030178636A1 (en) * 2002-02-11 2003-09-25 Jds Uniphase Corporation Back illuminated photodiodes
US20140175511A1 (en) * 2012-12-24 2014-06-26 Electronics And Telecommunications Research Institute Avalanche photodiode
CN105070780A (zh) * 2015-07-30 2015-11-18 中国电子科技集团公司第四十四研究所 一种平面型三阶梯结雪崩光电二极管及制作方法
US20170084773A1 (en) * 2015-09-18 2017-03-23 Princeton Lightwave, Inc. APD Focal Plane Arrays with Backside Vias

Also Published As

Publication number Publication date
CN117012774A (zh) 2023-11-07

Similar Documents

Publication Publication Date Title
US7893464B2 (en) Semiconductor photodiode and method of manufacture thereof
US7898055B2 (en) Photodiode with controlled current leakage
US7476598B2 (en) Photodiode and method of manufacturing the same
US9825190B2 (en) Solar cell and method for manufacturing the same
US5880482A (en) Low dark current photodetector
JP2013098564A (ja) 半導体光検出デバイスを作成する方法
KR20140071940A (ko) 다중 접합 다중 탭 광전 소자
US5449943A (en) Visible and infrared indium antimonide (INSB) photodetector with non-flashing light receiving surface
US8999744B2 (en) Avalanche photodiodes and methods of fabricating the same
CN108630781B (zh) 3～5μm红外波段雪崩光电二极管探测器及其制作方法
WO2023206813A1 (zh) 光电探测器及其制作方法
RU2469438C1 (ru) Полупроводниковый фотодиод для инфракрасного излучения
CN115939153A (zh) 一种光电子集成芯片及其制备方法
CN117117012A (zh) 一种雪崩光电二极管及其制作方法
GB1561953A (en) Photodiodes
TW202010141A (zh) 檢光二極體及其製造方法
RU221645U1 (ru) Полупроводниковый фотодиод для инфракрасного излучения
CN219892188U (zh) 一种半导体光敏器件
KR100654014B1 (ko) 대구경 수광부를 위한 전극구조를 구비한 포토 다이오드
CN118039724A (zh) 光电探测器、光接收模块及电子设备
Sun et al. The influence of unpassivated photosensitive surface on the characteristics of photodiode
JP2023097802A (ja) 受光素子及び受光素子の製造方法
CN117894812A (zh) 单光子雪崩二极管的结构和制备方法
KR102082880B1 (ko) 태양 전지의 제조 방법
KR20230016567A (ko) Nir 센서를 위한 도핑된 반도체 구조물

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22939641

Country of ref document: EP

Kind code of ref document: A1