WO2023206668A1 - 显示面板以及显示装置 - Google Patents

显示面板以及显示装置 Download PDF

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Publication number
WO2023206668A1
WO2023206668A1 PCT/CN2022/094216 CN2022094216W WO2023206668A1 WO 2023206668 A1 WO2023206668 A1 WO 2023206668A1 CN 2022094216 W CN2022094216 W CN 2022094216W WO 2023206668 A1 WO2023206668 A1 WO 2023206668A1
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WO
WIPO (PCT)
Prior art keywords
display panel
connection
connection part
display
display area
Prior art date
Application number
PCT/CN2022/094216
Other languages
English (en)
French (fr)
Inventor
牛艳芬
张筱霞
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/781,004 priority Critical patent/US20240161688A1/en
Publication of WO2023206668A1 publication Critical patent/WO2023206668A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present application relates to the technical field of display devices, and in particular, to a display panel and a display device.
  • AMOLED display technology as an emerging panel technology, has been widely used due to its display advantages such as low power consumption, low cost, wide color gamut, high resolution and high color saturation, as well as its bendability and ease of changing shapes to be carried around.
  • the industry is recognized as the display technology with the most development potential.
  • Display panels usually need to provide signal lines that provide signals for sub-pixels.
  • the signal lines are connected to the driving switches through connecting wires.
  • the same power supply voltage is used to supply each pixel unit in its display area.
  • a large light-transmitting area is formed on the display panel, and the light-transmitting area forms a fixed grating effect, which causes uneven visual display in the screen-off and screen-on states ( Mura) problem, affecting the display effect of the display panel.
  • This application provides a display panel and a display device to solve the problem of poor display effect of the display panel.
  • this application provides a display panel, which includes:
  • each sub-pixel includes a pixel circuit and a light-emitting element, the pixel circuit is used to drive the light-emitting element, the pixel circuit includes a driving transistor, and the light-emitting element includes a pixel electrode ;
  • a plurality of first connection portions each of the first connection portions is respectively connected to one of the pixel electrodes and one of the driving transistors.
  • the first connection portions are also used to connect signal wirings.
  • the plurality of first connection portions are The connecting portion extends along the first direction, adjacent first connecting portions are spaced apart, and a first bending portion is provided in the middle of the first connecting portion.
  • the first connection part is a serpentine connection part.
  • the first bending part is a bending part having at least one shape of a folding line, a curve, and an arc.
  • the display panel further includes:
  • each of the second connection parts is respectively connected to one of the pixel electrodes and one of the driving transistors, and the adjacent second connection parts are spaced apart along the first direction to form a first accommodation. space;
  • the second connecting part and the first connecting part are offset along a second direction, the first direction and the second direction intersect, and the first bending part is located in the first accommodation space.
  • a second bending portion is provided in the middle of the second connecting portion, and the adjacent first connecting portions are spaced apart along the first direction to form a second accommodation space.
  • the second bending portion is located in the second accommodation space.
  • the first connection part further includes two first bent end parts, and the first bent end parts form a first escape space;
  • the second connecting part also includes two second bent ends, the second bent ends form a second shelter space, and the first bent end is at least partially located in the second shelter space. Inside, the second bent end is at least partially located within the first escape space.
  • the first connection part and the second connection part are made of transparent conductive material.
  • the display panel further includes:
  • a plurality of third connection parts, the first connection part and the third connection part are arranged on the same layer, each of the third connection parts is connected to one of the pixel electrodes and one of the driving transistors respectively, and the third connection part is The three connecting parts are linear and extend along the first direction;
  • the third connecting portion extends along the first direction, adjacent third connecting portions are spaced apart, and each third connecting portion is disposed between two adjacent first connecting portions.
  • the first connection part includes a first via hole and a second via hole, and the first connection part is connected to the pixel electrode through the first via hole.
  • a connection portion is connected to the driving transistor through the second via hole.
  • the first via hole and the second via hole are arranged adjacently or spaced apart.
  • the display panel includes a first display area and a fan-out area, the fan-out area overlaps the first display area, and the fan-out area and the second display area arranged at intervals, and the first connecting portion is located in the first display area.
  • the display panel further includes a second display area, the first display area and the second display area are arranged adjacently, and the display panel further includes:
  • a plurality of fourth connection parts is provided in the second display area, and each of the fourth connection parts is respectively connected to one of the pixel electrodes and one of the driving transistors;
  • the fourth connecting portion extends along the first direction, adjacent fourth connecting portions are spaced apart along the first direction, and a third bending portion is provided in the middle of the fourth connecting portion.
  • the third connecting portion extends along the second display area toward the first display area in the first direction.
  • this application also provides a display device, which includes a display panel, where the display panel includes:
  • each sub-pixel includes a pixel circuit and a light-emitting element, the pixel circuit is used to drive the light-emitting element, the pixel circuit includes a driving transistor, and the light-emitting element includes a pixel electrode ;
  • a plurality of first connection portions each of the first connection portions is respectively connected to one of the pixel electrodes and one of the driving transistors.
  • the first connection portions are also used to connect signal wirings.
  • the plurality of first connection portions are The connecting portion extends along the first direction, adjacent first connecting portions are spaced apart, and a first bending portion is provided in the middle of the first connecting portion.
  • the first connection part is a serpentine connection part
  • the first bending part is a bending part having at least one shape of a folded line, a curve, or an arc.
  • the display panel further includes:
  • each of the second connection parts is respectively connected to one of the pixel electrodes and one of the driving transistors, and the adjacent second connection parts are spaced apart along the first direction to form a first accommodation. space;
  • the second connecting part and the first connecting part are offset along a second direction, the first direction and the second direction intersect, and the first bending part is located in the first accommodation space.
  • a second bending portion is provided in the middle of the second connecting portion, and the adjacent first connecting portions are spaced apart along the first direction to form a second accommodation space.
  • the second bending part is located in the second accommodation space;
  • the first connection part and the second connection part are made of transparent conductive material.
  • the display panel further includes:
  • a plurality of third connection parts, the first connection part and the third connection part are arranged on the same layer, each of the third connection parts is connected to one of the pixel electrodes and one of the driving transistors respectively, and the third connection part is The three connecting parts are linear and extend along the first direction;
  • the third connecting portion extends along the first direction, adjacent third connecting portions are spaced apart, and each third connecting portion is disposed between two adjacent first connecting portions.
  • the display panel further includes a first display area and a second display area, the first display area and the second display area are arranged adjacently, and the display panel further includes:
  • a plurality of fourth connection parts is provided in the second display area, and each of the fourth connection parts is respectively connected to one of the pixel electrodes and one of the driving transistors;
  • the fourth connecting portion extends along the first direction, adjacent fourth connecting portions are spaced apart along the first direction, and a third bending portion is provided in the middle of the fourth connecting portion.
  • the present application provides a display panel and a display device.
  • a first connection part for connecting an external signal line is provided between a driving transistor and a pixel electrode, so that each first connection part is connected to one of the pixel electrodes respectively.
  • the first connection portion Connected to one of the driving transistors, the first connection portion extends along the first direction, adjacent first connection portions are spaced apart, and a first bending portion is provided in the middle of the first connection portion, so that The length of each first connection part is increased as much as possible within the unit area, thereby increasing the distribution area of the first connection part, which is beneficial to reducing the amount of light transmission of the display panel and preventing the first connection part from being too sparsely distributed. This causes a grating effect problem to be formed between the adjacent first connection portions, thereby improving the display uniformity of the display panel and conducive to improving the display effect.
  • FIG. 1 is a schematic top structural view of a display panel provided by an embodiment of the present application.
  • Figure 2 is an enlarged structural schematic diagram of position A in Figure 1 of the present application.
  • FIG. 3 is a schematic cross-sectional structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 4 is a schematic top view of a display panel according to another embodiment of the present application.
  • Figure 5 is an enlarged structural schematic diagram of position B in Figure 4 of the present application.
  • FIG. 6 is a schematic structural diagram of each area of the display panel provided by the embodiment of the present application.
  • FIG. 7 is a schematic top structural view of a display panel provided by yet another embodiment of the present application.
  • Figure 8 is an enlarged structural schematic diagram of position C in Figure 7 of the present application.
  • “plurality” means two or more than two, unless otherwise explicitly and specifically limited.
  • the term “above” or “below” a first feature on a second feature may include direct contact between the first and second features, or may also include the first and second features. Not in direct contact but through additional characteristic contact between them.
  • the terms “above”, “above” and “above” a first feature on a second feature include the first feature being directly above and diagonally above the second feature, or simply mean that the first feature is higher in level than the second feature.
  • “Below”, “under” and “under” the first feature is the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature is less horizontally than the second feature.
  • “plurality” means two or more than two, unless otherwise explicitly and specifically limited.
  • Embodiments of the present application provide a display panel and a display device, which are described in detail below.
  • embodiments of the present application provide a display panel, in which the display panel is provided with multiple sub-pixels (not shown), and at least one sub-pixel includes a pixel circuit (not shown) and a light-emitting element 30 .
  • the pixel circuit is used to drive the connected light emitting element 30 .
  • the pixel circuit is configured to provide a driving current to drive the light emitting element 30 to emit light.
  • the pixel circuit may include a plurality of thin film transistors and at least one capacitor.
  • the pixel circuit may have a 3T1C (3 thin film transistors and 1 capacitor) structure, a 7T1C (7 thin film transistors and 1 capacitor) structure, or a 5T1C (5 thin film transistor and 1 capacitor) structure, etc.
  • Corresponding scanning signals, light-emitting driving signals, data signals, etc. can be received through the pixel circuit to drive the light-emitting element 30 to emit light.
  • the specific principle of the pixel circuit driving the light-emitting element 30 to emit light will not be described again here.
  • the pixel circuit includes a driving transistor 20, and the light-emitting element 30 includes a pixel electrode 31, where the pixel electrode 31 may be an anode of an OLED light-emitting device.
  • the base substrate 10 may be a flexible base substrate 10 or a rigid base substrate 10 .
  • the substrate 10 may be made of polyimide (PI), polyethylene naphthalate (PEN), thermoplastic polyester (PET), etc. material; when the base substrate 10 is a rigid base substrate 10, the base substrate 10 can be made of rigid materials such as glass, quartz, etc.
  • the substrate 10 may adopt a single-layer PI structure, or the substrate 10 may adopt a double-layer PI structure.
  • the substrate 10 includes a PI substrate along its thickness direction.
  • the first PI substrate 11, the first buffer layer 12, the second PI substrate 13 and the second buffer layer 14 are arranged in sequence from bottom to top.
  • a plurality of driving transistors 20 are arranged in an array on the base substrate 10 , and a plurality of pixel electrodes 31 are arranged on the driving transistors 20 .
  • the display panel is an OLED display panel as an example.
  • the light-emitting element 30 can be an organic light-emitting diode (OLED).
  • OLED organic light-emitting diode
  • the light-emitting element 30 emits red light, green light, and blue light under the driving of its corresponding pixel circuit. , or white light, etc.
  • the color of the light emitted by the light emitting element 30 can be determined according to needs.
  • the pixel electrode 31 in the embodiment of the present application may be the anode of the light-emitting element 30.
  • the light-emitting element 30 may include: an anode, a cathode, and a light-emitting functional layer located between the anode and the cathode.
  • the anode of the light emitting element 30 may be electrically connected to the driving transistor 20 in the corresponding pixel circuit.
  • film layers such as an encapsulation layer, a touch layer, a polarizing layer, and a cover plate can also be provided on the pixel electrode 31 .
  • Each first connection part 40 is connected to one pixel electrode 31 and one driving transistor 20 respectively.
  • the driving transistor 20 sequentially includes an active layer 21 , a gate layer 22 and a source-drain layer 23 from top to bottom along the thickness direction of the base substrate 10 , wherein the active layer 21 is disposed on the base substrate 10 On one side of 10, the gate layer 22 is disposed on the active layer 21, the source-drain layer 23 is disposed on the gate layer 22, and the active layer 21, the gate layer 22 and the source-drain layer 23 are insulated from each other. .
  • the first connection part 40 is connected between the source-drain layer 23 and the pixel electrode 31 . Specifically, the first connection part 40 may be connected to the source in the source-drain layer 23 .
  • a bridge layer 24 can also be provided between the first connection part 40 and the source-drain layer 23.
  • the material of the bridge layer 24 can be the same as the material of the source-drain layer 23.
  • the bridge layer 24 can be used to connect the voltage signal path. line VDD, thereby increasing the number of connections between the driving transistor 20 and the signal line VDD, thereby enhancing the display driving capability.
  • the first connection portion 40 extends along the first direction Y, and is arranged in an array corresponding to the sub-pixels on the display panel. Specifically, for example, the first connecting portions 40 may be arranged in multiple rows along the first direction Y and arranged in multiple rows along the second direction X. Wherein, the first connection parts 40 arranged in a row along the second direction Department 40.
  • the first connection portion 40 is used to connect signal traces. For example, the first connection portion 40 in the same column can be electrically connected to a voltage signal trace VDD.
  • the first direction Y may be a vertical direction parallel to the display plane of the display panel
  • the second direction X may be a horizontal direction parallel to the display plane of the display panel.
  • first connecting portions 40 extending along the first direction Y are arranged at intervals along the second direction X. Adjacent first connecting portions 40 are spaced apart, and a first bending portion 41 is provided in the middle of the first connecting portion 40 , wherein the first bending portion 41 is used to increase the length of the first bending portion 41 .
  • the display panel of the embodiment of the present application disposes a first connection part 40 for connecting external signal wiring between the driving transistor 20 and the pixel electrode 31, so that each first connection part 40 is connected to one pixel electrode 31 and one driving transistor respectively.
  • the first connecting portion 40 extends along the first direction Y, adjacent first connecting portions 40 are arranged at intervals, and a first bending portion 41 is provided in the middle of the first connecting portion 40, so that the first connecting portion 40 can be as large as possible within the unit area.
  • the length of each first connecting portion 40 is increased thereby increasing the distribution area of the first connecting portion 40, which is beneficial to reducing the amount of light transmission of the display panel, avoiding light leakage, and preventing the first connecting portions 40 from being too sparsely distributed.
  • a grating effect problem is formed between the adjacent first connecting portions 40 , thereby improving the display uniformity of the display panel and improving the display effect.
  • the first connection part 40 is a serpentine connection part. Specifically, it may be a connection part composed of an S-shaped curve. That is, when the first connection part 40 forms a trace, it may be a serpentine winding. .
  • the length of the first connecting part 40 can be increased in the first direction Y, and the structural compactness of the first connecting part 40 can be increased, thus facilitating the improvement of the first connecting part 40
  • the distribution density can better avoid problems such as light leakage and grating effects, which will help further improve the display uniformity of the display panel.
  • the first connecting part 40 further includes two first bent ends 42
  • the first bent ends 42 form a first escape space 402
  • the second connecting part 50 further includes It includes two second bent end portions 52.
  • the second bent end portions 52 form a second shelter space 502.
  • the first bent end portion 42 is at least partially located in the second shelter space 502.
  • the second bent end portions 52 is located at least partially within the first shelter space 402.
  • the display panel further includes a plurality of second connection parts 50 .
  • the second connection parts 50 may also be arranged in an array. For example, they may be arranged in multiple directions along the first direction Y. rows, and arranged into multiple rows along the second direction X.
  • Each second connection part 50 is connected to a pixel electrode 31 and a driving transistor 20 respectively.
  • Adjacent second connection parts 50 are spaced apart along the first direction Y to form a first accommodation space 501, wherein the first bending part 41 is located in the first accommodation space 501.
  • the second connecting part 50 and the first connecting part 40 are offset along the second direction X. Specifically, the first connecting part 40 and the second connecting part 50 may be arranged in parallel.
  • the first connecting part 40 and the second connecting part 50 have the same function.
  • the only difference between the first connecting part 40 and the second connecting part 50 is in their shapes.
  • the first bending part 41 and the second bending part 51 have different shapes.
  • the bending direction is opposite.
  • the first accommodating space 501 provides a sufficiently large bending and winding space for the first bending portion 41 so that the first bending portion 41 can form a longer bending length in the first accommodating space 501, so that The first bending portions 41 can be distributed as much as possible in the first accommodation space 501, thereby increasing the distribution area of the second connecting portion 50, which is beneficial to reducing the amount of light transmission of the display panel, avoiding light leakage and avoiding second If the connecting portions 50 are too sparsely distributed, a grating effect will occur between adjacent second connecting portions 50 , which is beneficial to improving the display uniformity of the display panel.
  • the first direction Y and the second direction X intersect, and the first direction Y and the second direction
  • the two directions X may be mutually perpendicular directions
  • the first direction Y may be a vertical direction
  • the second direction X may be a horizontal direction.
  • parallel refers to the state in which the angle formed by two straight lines is -10° or more and 10° or less, and therefore, it also includes the state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • a second bending portion 51 is provided in the middle of the second connecting portion 50 , wherein the first bending portion 41 and the second bending portion 51 have opposite bending directions, and the adjacent first connecting portions have opposite bending directions. 40 are spaced apart along the first direction Y to form a second accommodation space 401, and the second bending portion 51 is located in the second accommodation space 401.
  • the second accommodating space 401 is used to provide a sufficiently large bending and winding space for the second bending portion 51 , so that the second bending portion 51 can form a longer bend in the second accommodating space 401 .
  • the compact structure between the first portion 50 and the second connection portion 50 can better avoid problems such as light leakage and grating effects, and is conducive to further improving the display uniformity of the display panel.
  • the first bending portion 41 and the second bending portion 51 may be bending portions having at least one shape of a folding line, a curve, and an arc.
  • the second bending part 51 may be a bending part composed of any one of a bending line, a curve, and an arc shape, or the second bending part 51 may be a bending part composed of both a bending line and a curve. etc.;
  • the second bending part 51 may be in a zigzag shape composed of multiple continuous segments of folding lines, or may be in a wavy shape composed of multiple segments of continuous curves.
  • the shape of the second bending part 51 is not modified. Specific restrictions.
  • the first connection part 40 and the second connection part 50 are made of transparent conductive material.
  • both the first connection part 40 and the second connection part 50 may be made of indium tin oxide (Indium Tin Oxide, ITO), indium zinc oxide (Indium Zinc Oxide, IZO), or indium gallium zinc oxide (Indium Gallium Zinc Oxide, Any one or more of IGZO). Since the grating effect of transparent conductive materials is small, by using the first connection part 40 and the second connection part 50 to also be made of transparent conductive materials, the metal production of the first connection part 40 and the second connection part can be effectively reduced. The grating effect of 50 is conducive to further improving the display effect of the display panel.
  • the display panel includes a first display area 101 and a fan-out area 103 .
  • the fan-out area 103 overlaps the first display area 101 .
  • the fan-out area 103 overlaps the first display area 103 .
  • 101 indicates partial overlap, that is, the first display area 101 includes the fan-out area 103 .
  • the first connection part 40 is located in the first display area 101 , that is, the first connection part 40 is also located in the fan-out area 103 .
  • the first display area 101 is an area in the display panel where images are actually displayed.
  • the fan-out area 103 refers to an area where multiple data lines of the display panel are gathered together in a fan shape. One end of the fan-out area 103 is electrically connected to the multiple data lines of the display panel, and one end is electrically connected to the gate drive circuit, so that the gate drive circuit can realize Progressive scan driver.
  • the fan-out area 103 is located in the non-display area of the display panel, which is not conducive to the realization of a narrow frame or frameless display panel.
  • the fan-out area 103 coincides with the first display area 101 (Fanout in AA, FIAA), that is, along the thickness direction of the display panel, the fan-out area 103 is located below the first display area 101, and the sub-pixels used for display in the fan-out area 103 are compressed, that is, by reducing the size of the switching device and The distribution of trace line widths, etc., allows a part of the space to be used for traces such as data lines connecting the fan-out area 103, so that the fan-out area 103 can be reused as an area for displaying images.
  • the fan-out area 103 may be arranged on the same layer as the gate driving circuit, or may be arranged on a different layer than the gate driving circuit, as long as the fan-out area 103 is located below the first display area 101, and there is no specific limitation.
  • the fan-out area 103 By arranging the fan-out area 103 to coincide with the first display area 101, the non-display area of the display panel is further reduced or eliminated, which is beneficial to the realization of a narrow frame or frameless display panel; in addition, due to the sub-pixels in the fan-out area 103, Due to the size compression of switching devices and metal traces, some traces, especially the traces of the first connection part 40 are relatively sparse, resulting in horizontal visual display unevenness in the screen off and on screen states. Therefore, by setting the fan The first connecting portion 40 in the fan-out area 103 is also beneficial to improving the display uniformity of the fan-out area 103 .
  • the first display area 101 may have various shapes.
  • the first display area 101 may be a rectangle, such as a rounded rectangle.
  • the first display area 101 may also be a circle or an ellipse.
  • the first display area 101 may have a round shape.
  • the display area 101 may also be in a rectangular, semicircular, pentagonal or other shape. This embodiment does not specifically limit this.
  • the display panel further includes a second display area 102, and the first display area 101 and the second display area 102 are arranged adjacently.
  • the second display area 102 is an area in the display panel where the image is actually displayed. Relative to the first display area 101 , the second display area 102 is a conventional display area, that is, the second display area 102 does not overlap with the fan-out area 103 .
  • the first display area 101 may be located at the top middle position of the display panel.
  • the second display area 102 may surround the first display area 101 .
  • this embodiment is not limited to this.
  • the first display area 101 may be located at other locations such as the upper left corner or the upper right corner of the display panel, or the second display area 102 may surround at least one side of the first display area 101 .
  • the second display area 102 may have a variety of shapes.
  • the second display area 102 may be a rectangle, such as a rounded rectangle.
  • the second display area 102 may also be a circle or an ellipse.
  • the second display area 102 may have a round shape.
  • the display area 102 may also be in a rectangular, semicircular, pentagonal or other shape. This embodiment does not specifically limit this.
  • the display panel further includes a plurality of third connection portions 60 .
  • the main difference between the first connection part 40 and the third connection part 60 is the difference in distribution shape.
  • the third connection part 60 is located in at least one area among the first display area 101, the fan-out area 103 and the second display area 102, wherein the first connection part 40 and the third connection part 60 are arranged on the same layer, each The third connection portion 60 is connected to one pixel electrode 31 and one driving transistor 20 respectively.
  • the third connection portion 60 is linear and extends along the first direction Y.
  • the third connection portion 60 can be in the first direction Y. , extending sequentially along the second display area 102 , the fan-out area 103 and the first display area 101 , or the third connection part 60 may only extend along the first direction Y within the fan-out area 103 .
  • Adjacent third connecting portions 60 are spaced apart along the second direction X, and each third connecting portion 60 is disposed between two adjacent first connecting portions 40 . Since the first connection part 40 and the third connection part 60 are arranged on the same layer, and both the first connection part 40 and the third connection part 60 are connection parts for electrical connection, therefore, on the basis of the first connection part 40 Providing the third connection part 60 can improve the structural compactness between the first connection part 40 and the second connection part 50 , and is conducive to increasing the metal area of the film layer where the first connection part 40 and the third connection part 60 are located. By increasing Distribution density can further avoid problems such as light leakage and grating effects.
  • the display panel also includes a plurality of fourth connection parts 70 .
  • the fourth connecting portion 70 is disposed in the second display area 102.
  • the fourth connecting portion 70 can also be arranged in an array. For example, it can be arranged in multiple rows along the first direction Y and in multiple rows along the second direction X.
  • Each fourth connection portion 70 is connected to a pixel electrode 31 and a driving transistor 20 respectively.
  • the fourth connection portions 70 extend along the first direction Y.
  • the adjacent fourth connection portions 70 are spaced apart along the first direction Y.
  • the fourth connection portions 70 are spaced apart along the first direction Y.
  • a third bending portion 71 is provided in the middle of the connecting portion 70 , and a fourth bending portion 72 is formed at an end of the fourth connecting portion 70 .
  • the middle part of the fourth connection part 70 is a bending part in the second display area 102, the length of each first connection part 40 is increased as much as possible within the unit area, thereby increasing the number of the fourth connection parts.
  • the distribution area is 70, which is beneficial to reducing the amount of light transmission in the second display area 102 of the display panel, avoiding light leakage and preventing the fourth connection portions 70 from being too sparsely distributed and causing a grating effect problem between adjacent fourth connection portions 70.
  • the display uniformity of the first display area 101 and the second display area 102 in the display panel can be improved, which is conducive to further improving the overall display effect of the display panel.
  • the display panel may further include a plurality of fifth connection portions 80 .
  • the plurality of fifth connecting portions 80 may also be arranged in an array, for example, they may be arranged in multiple rows along the first direction Y and in multiple rows along the second direction X.
  • the fifth connection part 80 is located in the first display area 101, and each fifth connection part 80 is connected between a pixel electrode 31 and a first connection part 40; or, each fifth connection part 80 is connected to a pixel electrode 31 and a second connecting part 50.
  • the fifth connection portion 80 can be used to connect the voltage signal line VDD, thereby increasing the number of connections between the driving transistor 20 and the signal line VDD, thereby enhancing the display driving capability.
  • the first connection part 40 includes a first via hole 403 and a second via hole 404, as shown in FIG. 8 , where the first connection part 40 is connected to the pixel electrode 31 through the first via hole 403.
  • the connection part 40 is connected to the driving transistor 20 through the second via hole 404.
  • the first via hole 403 and the second via hole 404 can be arranged adjacently, or the first via hole 403 and the second via hole 404 can also be arranged at intervals. Among them, the length of the first via hole 403 and the second via hole 404 on the base substrate 10 will also affect the length of the fifth connecting portion 80.
  • the distance between the first via hole 403 and the second via hole 404 is The longer the distance between the first via hole 403 and the second via hole 404 on the base substrate 10 , the longer the trace length of the fifth connection part 80 will be. The length will also be shorter. Therefore, adjusting the via position distance between the first via hole 403 and the second via hole 404 according to the actual length of the fifth connection part 80 is beneficial to improving the flexibility of the first connection part 40 in realizing connection.
  • the distribution of the area of the fifth connection part 80 can be set to have regularity, thereby preventing In the installation area of the fifth connecting portion 80, due to the different areas of the fifth connecting portion 80, the continuous reflection of light causes the brightness of the sub-pixels above the different fifth connecting portions 80 to be different, causing obvious differences in the display brightness at a certain location.
  • the sudden change that is, by controlling the distribution density of the fifth connection portion 80, the display area where the fifth connection portion 80 is located plays a transition role in the display effect, thereby reducing the problem of uneven display caused by the arrangement of the fifth connection portion 80.
  • the first via hole 403 and the second via hole 404 can also be provided on the third connection part 60 and can have the same effect, which will not be discussed here. Repeat.
  • the third connection part 60 , the fourth connection part 70 and the fifth connection part 80 can also be made of transparent conductive material.
  • the third connection part 60 , the fourth connection part 70 and the fifth connection part 80 may all adopt indium tin oxide (Indium Tin Oxide, ITO), indium zinc oxide (Indium Zinc Oxide, IZO), or indium gallium zinc oxide. (Indium Gallium Zinc Oxide, IGZO) is formed from any one or more of them.
  • the materials of the first connecting part 40 , the second connecting part 50 , the third connecting part 60 , the fourth connecting part 70 and the fifth connecting part 80 may be the same or different, and are not specifically limited here.
  • This application also provides a display device, which includes the above-mentioned display panel.
  • the display panel in the display device of the embodiment of the present application disposes a first connection part 40 for connecting external signal wiring between the driving transistor 20 and the pixel electrode 31, so that each first connection part 40 is connected to one pixel electrode 31 respectively.
  • the first connection part 40 Connected to a driving transistor 20, the first connection part 40 extends along the first direction Y, adjacent first connection parts 40 are spaced apart, and a first bending part 41 is provided in the middle of the first connection part 40, so that the unit can
  • the length of each first connection part 40 is increased as much as possible within the area, thereby increasing the distribution area of the first connection part 40, which is beneficial to reducing the amount of light transmission of the display panel, avoiding light leakage and avoiding the distribution of the first connection part 40 Too sparse will cause a grating effect problem between adjacent first connection portions 40, which can improve the display uniformity of the display panel and help improve the display effect.
  • the display device Since the display device has the above-mentioned display panel, it has all the same beneficial effects, which will not be described again in this embodiment.
  • the embodiments of the present application do not specifically limit the application of the display device, which may be a television, a laptop, a tablet, a wearable display device (such as a smart bracelet, a smart watch, etc.), a mobile phone, a virtual reality device, an augmented reality device, or a mobile phone.
  • each of the above units or structures can be implemented as an independent entity, or can be combined in any way and implemented as the same or several entities.
  • each of the above units or structures please refer to the previous method embodiments. Here No longer.

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Abstract

一种显示面板以及显示装置，通过在显示面板中的第一连接部（40）的中部设置有第一弯折部（41），从而可以在单位面积内尽可能地增加每个第一连接部（40）的长度，由此增加了第一连接部（40）的分布面积，从而有利于减少显示面板的透光量，避免漏光以及光栅效应问题，进而可以提高显示面板的显示均一性，有利于提升显示效果。

Description

显示面板以及显示装置 技术领域
本申请涉及显示器件技术领域，尤其涉及一种显示面板以及显示装置。
 背景技术
AMOLED显示技术作为一种新兴面板技术，因其低功耗、低成本、色域广、高分辨率和高色彩饱和度等显示方面的优点和可弯折、易于变换形态随身携带等特点，被业界公认为是最具有发展潜力的显示技术。
显示面板中通常需要设置为子像素提供信号的信号线，信号线通过连接走线与驱动开关连接，然而，对于高分辨率的AMOLED显示装置，在使用同一电源电压向其显示区的各像素单元供电时，由于连接走线的布线方式并不理想，导致显示面板上的大片透光区域，透光区域形成了固定的光栅效应，会造成熄屏和亮屏状态下的可视显示不均（Mura）的问题，影响了显示面板的显示效果。
 技术问题
本申请提供一种显示面板以及显示装置，以解决显示面板显示效果不佳的问题。
 技术解决方案
一方面，本申请提供一种显示面板，其包括：
衬底基板；
子像素，阵列设置于所述衬底基板上，每个子像素包括像素电路和发光元件，所述像素电路用于驱动所述发光元件，所述像素电路包括驱动晶体管，所述发光元件包括像素电极；
多个第一连接部，每个所述第一连接部分别与一个所述像素电极和一个所述驱动晶体管连接，所述第一连接部还用于连接信号走线，多个所述第一连接部沿第一方向延伸，相邻的所述第一连接部间隔设置，所述第一连接部的中部设置有第一弯折部。
在本申请所述的显示面板中，所述第一连接部为蛇形连接部。
在本申请所述的显示面板中，所述第一弯折部为具有折线、曲线以及弧线中的至少一种形状的弯折部。
在本申请所述的显示面板中，所述显示面板还包括：
多个第二连接部，每个所述第二连接部分别与一个所述像素电极和一个所述驱动晶体管连接，相邻的所述第二连接部沿第一方向间隔设置形成第一容置空间；
所述第二连接部和所述第一连接部沿第二方向错位设置，所述第一方向和所述第二方向交叉，所述第一弯折部位于所述第一容置空间内。
在本申请所述的显示面板中，所述第二连接部的中部设置有第二弯折部，相邻的所述第一连接部沿第一方向间隔设置形成第二容置空间，所述第二弯折部位于所述第二容置空间内。
在本申请所述的显示面板中，所述第一连接部还包括两个第一弯折端部，所述第一弯折端部形成第一避位空间；
所述第二连接部还包括两个第二弯折端部，所述第二弯折端部形成第二避位空间，所述第一弯折端部至少部分位于所述第二避位空间内，所述第二弯折端部至少部分位于所述第一避位空间内。
在本申请所述的显示面板中，所述第一连接部和所述第二连接部采用透明导电材质制成。
在本申请所述的显示面板中，所述显示面板还包括：
多个第三连接部，所述第一连接部和所述第三连接部同层设置，每个所述第三连接部分别与一个所述像素电极和一个所述驱动晶体管连接，所述第三连接部呈直线状且沿所述第一方向延伸；
所述第三连接部沿所述第一方向延伸，相邻的所述第三连接部间隔设置，每个所述第三连接部设置于相邻的两个第一连接部之间。
在本申请所述的显示面板中，所述第一连接部包括第一过孔和第二过孔，所述第一连接部通过所述第一过孔与所述像素电极连接，所述第一连接部通过所述第二过孔与所述驱动晶体管连接。
在本申请所述的显示面板中，所述第一过孔和所述第二过孔相邻设置或间隔设置。
在本申请所述的显示面板中，所述显示面板包括第一显示区以及扇出区，所述扇出区与所述第一显示区重合，所述扇出区与所述第二显示区间隔设置，所述第一连接部位于所述第一显示区内。
在本申请所述的显示面板中，所述显示面板还包括第二显示区，所述第一显示区和所述第二显示区相邻设置，所述显示面板还包括：
多个第四连接部，所述第四连接部设置于所述第二显示区内，每个所述第四连接部分别与一个所述像素电极和一个所述驱动晶体管连接；
所述第四连接部沿所述第一方向延伸，相邻的所述第四连接部沿第一方向间隔设置，所述第四连接部的中部设置有第三弯折部。
在本申请所述的显示面板中，所述第三连接部在所述第一方向上，沿着所述第二显示区向所述第一显示区延伸。
另一方面，本申请还提供一种显示装置，其包括显示面板，所述显示面板包括：
衬底基板；
子像素，阵列设置于所述衬底基板上，每个子像素包括像素电路和发光元件，所述像素电路用于驱动所述发光元件，所述像素电路包括驱动晶体管，所述发光元件包括像素电极；
多个第一连接部，每个所述第一连接部分别与一个所述像素电极和一个所述驱动晶体管连接，所述第一连接部还用于连接信号走线，多个所述第一连接部沿第一方向延伸，相邻的所述第一连接部间隔设置，所述第一连接部的中部设置有第一弯折部。
在本申请所述的显示装置中，所述第一连接部为蛇形连接部，所述第一弯折部为具有折线、曲线以及弧线中的至少一种形状的弯折部。
在本申请所述的显示装置中，所述显示面板还包括：
多个第二连接部，每个所述第二连接部分别与一个所述像素电极和一个所述驱动晶体管连接，相邻的所述第二连接部沿第一方向间隔设置形成第一容置空间；
所述第二连接部和所述第一连接部沿第二方向错位设置，所述第一方向和所述第二方向交叉，所述第一弯折部位于所述第一容置空间内。
在本申请所述的显示装置中，所述第二连接部的中部设置有第二弯折部，相邻的所述第一连接部沿第一方向间隔设置形成第二容置空间，所述第二弯折部位于所述第二容置空间内；
所述第一连接部和所述第二连接部采用透明导电材质制成。
在本申请所述的显示装置中，所述显示面板还包括：
多个第三连接部，所述第一连接部和所述第三连接部同层设置，每个所述第三连接部分别与一个所述像素电极和一个所述驱动晶体管连接，所述第三连接部呈直线状且沿所述第一方向延伸；
所述第三连接部沿所述第一方向延伸，相邻的所述第三连接部间隔设置，每个所述第三连接部设置于相邻的两个第一连接部之间。
在本申请所述的显示装置中，所述显示面板还包括第一显示区和第二显示区，所述第一显示区和所述第二显示区相邻设置，所述显示面板还包括：
多个第四连接部，所述第四连接部设置于所述第二显示区内，每个所述第四连接部分别与一个所述像素电极和一个所述驱动晶体管连接；
所述第四连接部沿所述第一方向延伸，相邻的所述第四连接部沿第一方向间隔设置，所述第四连接部的中部设置有第三弯折部。
 有益效果
本申请提供的一种显示面板以及显示装置，通过在驱动晶体管和像素电极之间设置用于连接外部信号走线第一连接部，使得每个所述第一连接部分别与一个所述像素电极和一个所述驱动晶体管连接，所述第一连接部沿第一方向延伸，相邻的所述第一连接部间隔设置，所述第一连接部的中部设置有第一弯折部，从而可以在单位面积内尽可能地增加每个第一连接部的长度，由此增加了第一连接部的分布面积，从而有利于减少显示面板的透光量，避免所述第一连接部分布过于稀疏致使相邻的所述第一连接部之间形成光栅效应问题，进而可以提高显示面板的显示均一性，有利于提升显示效果。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请实施例提供的显示面板的俯视结构示意图。
图2为本申请图1中A处的放大结构示意图。
图3为本申请实施例提供的显示面板的剖面结构示意图。
图4为本申请又一实施例提供的显示面板的俯视结构示意图。
图5为本申请图4中B处的放大结构示意图。
图6为本申请实施例提供的显示面板的各个区域的结构示意图。
图7为本申请又一实施例提供的显示面板的俯视结构示意图。
图8为本申请图7中C处的放大结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
此外，在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。
本申请实施例提供了一种显示面板以及显示装置，以下分别进行详细介绍。
请参考图1-图8，本申请实施例提供一种显示面板，其中，显示面板设置有多个子像素（图未示），至少一个子像素包括像素电路（图未示）和发光元件30。
像素电路用于驱动所连接的发光元件30。例如，像素电路配置为提供驱动电流以驱动发光元件30发光。其中，像素电路可以包括多个薄膜晶体管和至少一个电容，例如，像素电路可以为3T1C(3个薄膜晶体管和1个电容)结构、7T1C(7个薄膜晶体管和1个电容)结构或者5T1C(5个薄膜晶体管和1个电容)结构等。通过像素电路即可接收相应的扫描信号、发光驱动信号和数据信号等，以驱动发光元件30进行发光，像素电路驱动发光元件30进行发光的具体原理在此不再赘述。
在本申请实施例中，像素电路包括驱动晶体管20，发光元件30包括像素电极31，其中，像素电极31可以为OLED发光器件的阳极。
其中，衬底基板10可以为柔性衬底基板10或者刚性衬底基板10。示例性地，当衬底基板10为柔性衬底基板10时，衬底基板10可以采用聚酰亚胺(PI)、聚萘二甲酸乙二醇酯(PEN)、热塑性聚酯(PET)等的材料；当衬底基板10为刚性衬底基板10时，衬底基板10可以为玻璃、石英等刚性材料。以衬底基板10为PI基板为例，衬底基板10可以采用单层PI结构，衬底基板10也可以采用双层PI结构，如图4所示，衬底基板10包括沿着其厚度方向自下而上依次设置的第一PI衬底11、第一缓冲层12、第二PI衬底13以及第二缓冲层14。
多个驱动晶体管20阵列设置于衬底基板10上，多个像素电极31设置于驱动晶体管20上。其中，本实施例以显示面板为OLED显示面板为例，对应地，发光元件30可以为有机发光二极管(OLED)，发光元件30在其对应的像素电路的驱动下发出红光、绿光、蓝光、或者白光等。发光元件30发光的颜色可根据需要而定。本申请实施例的像素电极31可以为发光元件30的阳极，具体地，发光元件30可以包括：阳极、阴极以及位于阳极和阴极之间的发光功能层。发光元件30的阳极可以与对应的像素电路中的驱动晶体管20电连接。需要说明的是，在显示面板中，像素电极31之上除了发光功能层、还可以设置封装层、触控层、偏光层以及盖板等膜层。
每个第一连接部40分别与一个像素电极31和一个驱动晶体管20连接。具体地，驱动晶体管20沿着衬底基板10的厚度方向自上而下依次包括有源层21、栅极层22以及源漏极层23，其中，其中，有源层21设置于衬底基板10的一侧，栅极层22设置于有源层21上，源漏极层23设置于栅极层22上，有源层21、栅极层22以及源漏极层23之间相互绝缘设置。第一连接部40连接于源漏极层23和像素电极31之间，第一连接部40具体可以与源漏极层23中的源极连接。其中，第一连接部40和源漏极层23之间还可以设置桥接层24，其中，桥接层24的材质可以和源漏极层23的材质相同，桥接层24可以用于连接电压信号走线VDD，以此增加驱动晶体管20与信号走线VDD的连接数量，从而可以增强显示驱动能力。
第一连接部40沿第一方向Y延伸，第一连接部40在显示面板上对应于子像素呈阵列排布。具体地，该第一连接部40例如可以沿第一方向Y排列为多排，并沿第二方向X排列为多排。其中，可以将沿第二方向X排列成一排的第一连接部40称为同一行第一连接部40，将沿第一方向Y排列成一排的第一连接部40称为同一列第一连接部40。第一连接部40用于连接信号走线，示例性地，同一列第一连接部40可以与一条电压信号走线VDD电连接。其中，第一方向Y可以是平行于显示面板的显示平面的竖直方向，第二方向X可以是平行于显示面板的显示平面的水平方向。
其中，多个沿第一方向Y延伸的第一连接部40沿着第二方向X间隔设置。相邻的第一连接部40间隔设置，第一连接部40的中部设置有第一弯折部41，其中，第一弯折部41用于增加第一弯折部41的长度。
本申请实施例的显示面板通过在驱动晶体管20和像素电极31之间设置用于连接外部信号走线第一连接部40，使得每个第一连接部40分别与一个像素电极31和一个驱动晶体管20连接，第一连接部40沿第一方向Y延伸，相邻的第一连接部40间隔设置，第一连接部40的中部设置有第一弯折部41，从而可以在单位面积内尽可能地增加每个第一连接部40的长度，由此增加了第一连接部40的分布面积，从而有利于减少显示面板的透光量，避免漏光以及避免第一连接部40分布过于稀疏致使相邻的第一连接部40之间形成光栅效应问题，进而可以提高显示面板的显示均一性，有利于提升显示效果。
在一些实施例中，第一连接部40为蛇形连接部，具体地，其可以是由S形曲线构成的连接部，即第一连接部40形成走线时，其可以是蛇形绕线。通过将第一连接部40设置蛇形连接部，从而在第一方向Y上可以增加第一连接部40的长度，可以增加第一连接部40结构紧凑性，从而有利于提高第一连接部40的分布密度，可以更好地避免漏光以及光栅效应等问题，进而有利于进一步提高显示面板的显示均一性。
在一些实施例中，如图5所示，第一连接部40还包括两个第一弯折端部42，第一弯折端部42形成第一避位空间402，第二连接部50还包括两个第二弯折端部52，第二弯折端部52形成第二避位空间502，第一弯折端部42至少部分位于第二避位空间502内，第二弯折端部52至少部分位于第一避位空间402内。通过设置第一避位空间402和第二避位空间502的设置，从而有利于提高第一连接部40和第二连接部50之间的结构紧凑性，从而增加第一连接部40和第二连接部50的分布密度，可以更好地避免漏光以及光栅效应等问题，进而有利于进一步提高显示面板的显示均一性。
在一些实施例中，如图4和图5所示，显示面板还包括多个第二连接部50，该第二连接部50也可以呈阵列排布，例如可以沿第一方向Y排列为多排，并沿第二方向X排列为多排。每个第二连接部50分别与一个像素电极31和一个驱动晶体管20连接，相邻的第二连接部50沿第一方向Y间隔设置形成第一容置空间501，其中，第一弯折部41位于第一容置空间501内。第二连接部50和第一连接部40沿第二方向X错位设置，具体地，第一连接部40和第二连接部50可以是平行设置。第一连接部40和第二连接部50的作用相同，第一连接部40和第二连接部50的区别仅在于形状不同，具体地，第一弯折部41和第二弯折部51的弯折方向相反。通过第一容置空间501为第一弯折部41提高足够大的弯折绕线空间，使得第一弯折部41在第一容置空间501中可以形成较长的弯折长度，以使得第一弯折部41可以尽可能地分布于第一容置空间501中，由此增加了第二连接部50的分布面积，从而有利于减少显示面板的透光量，避免漏光以及避免第二连接部50分布过于稀疏致使相邻的第二连接部50之间形成光栅效应问题，进而有利于提高显示面板的显示均一性。
其中，第一方向Y和第二方向X交叉，第一方向Y与第二方向X可以设置为平行于显示面板的同一显示平面内，具体地，在本实施例中，第一方向Y和第二方向X可以是相互垂直的方向，第一方向Y可以是竖直方向，第二方向X可以为水平方向。需要说明的是，平行是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在一些实施例中，第二连接部50的中部设置有第二弯折部51，其中，第一弯折部41和第二弯折部51的弯折方向相反，相邻的第一连接部40沿第一方向Y间隔设置形成第二容置空间401，第二弯折部51位于第二容置空间401内。本申请实施例通过第二容置空间401为第二弯折部51提高足够大的弯折绕线空间，使得第二弯折部51在第二容置空间401中可以形成较长的弯折长度，以使得第二弯折部51可以尽可能地分布于第二容置空间401中，从而有利于在第一容置空间501和第一弯折部41的基础上，进一步提高第二连接部50和第二连接部50之间的结构紧凑性，可以更好地避免漏光以及光栅效应等问题，有利于进一步提高显示面板的显示均一性。
在一些实施例中，第一弯折部41和第二弯折部51可以是具有折线、曲线以及弧线中的至少一种形状的弯折部。例如，第二弯折部51可以为仅由折线、曲线以及弧线中的任意一种形状构成的弯折部，第二弯折部51可以是由折线和曲线两种形状构成的弯折部等；示例性地，第二弯折部51可以是由连续多段折线构成的锯齿状，也可以是由多段连续的曲线构成的波浪线状，本实施在不对第二弯折部51的形状做具体限制。
在一些实施例中，第一连接部40和第二连接部50采用透明导电材质制成。具体地，第一连接部40和第二连接部50均可以采用氧化铟锡(Indium Tin Oxide，ITO)、氧化铟锌(Indium Zinc Oxide，IZO)、铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)中的任一种或几种形成。由于透明导电材料光栅效应较小，因此，通过将第一连接部40和第二连接部50采用也采用透明导电材料制成，从而可以有效减小金属制作第一连接部40和第二连接部50的光栅效应，有利于进一步提高显示面板的显示效果。
在一些实施例中，如图6所示，显示面板包括第一显示区101以及扇出区103，扇出区103与第一显示区101重合，具体地，扇出区103与第一显示区101为部分重合，即第一显示区101包括扇出区103。第一连接部40位于第一显示区101内，即，第一连接部40也位于扇出区103内。
其中，第一显示区101为显示面板中实际显示图像的区域。扇出区103指显示面板的多条数据线呈扇形聚拢的区域，扇出区103一端与显示面板的多条数据线电连接，一端与栅极驱动电路电连接，以使栅极驱动电路实现逐行扫描驱动。一般情况下，扇出区103位于显示面板的非显示区域，不利于显示面板的窄边框或无边框的实现。当扇出区103与第一显示区101重合（Fanout in AA,FIAA），即沿着显示面板的厚度方向，扇出区103位于第一显示区101的下方，对于扇出区103内用于显示的子像素进行压缩，即通过减少开关器件的尺寸以及走线线宽等的分布，使得一部分空间用于连接扇出区103的数据线等走线，从而扇出区103可以复用为显示图像的区域。示例性地，扇出区103可以与栅极驱动电路同层设置，也可以与栅极驱动电路非同层设置，只要扇出区103位于第一显示区101的下方即可，具体不作限制。通过设置扇出区103与第一显示区101重合，以进一步减小或者消除显示面板的非显示区域，有利于显示面板窄边框或无边框的实现；此外，由于扇出区103内的子像素由于开关器件以及金属走线由于尺寸压缩导致部分走线，尤其是第一连接部40的走线较为稀疏，造成熄屏和亮屏状态下的横向可视显示不均现象，因此，通过设置扇出区103内的第一连接部40的同时也有利于改善扇出区103显示时的均一性。
其中，第一显示区101的形状可以为多种，示例性地，第一显示区101可以为矩形，例如圆角矩形，第一显示区101还可以为圆形或椭圆形，当然，第一显示区101也可以为矩形、半圆形、五边形等其他形状。本实施例对此不做具体限定。
在一些实施例中，显示面板还包括第二显示区102，第一显示区101和第二显示区102相邻设置。其中，第二显示区102为显示面板中实际显示图像的区域。相对于第一显示区101，第二显示区102为常规显示区，即第二显示区102不与扇出区103重合。具体地，第一显示区101可以位于显示面板的顶部正中间位置。第二显示区102可以围绕在第一显示区101的四周。然而，本实施例对此并不限定。示例性地，第一显示区101可以位于显示面板的左上角或者右上角等其他位置，或者，第二显示区102可以围绕在第一显示区101的至少一侧。其中，第二显示区102的形状可以为多种，示例性地，第二显示区102可以为矩形，例如圆角矩形，第二显示区102还可以为圆形或椭圆形，当然，第二显示区102也可以为矩形、半圆形、五边形等其他形状。本实施例对此不做具体限定。
在一些实施例中，如图7和图8所示，显示面板还包括多个第三连接部60。其中，第一连接部40和第三连接部60的主要区别在于分布形状的不同。
其中，第三连接部60位于第一显示区101、扇出区103以及第二显示区102中的至少一个区域内，其中，第一连接部40和第三连接部60同层设置，每个第三连接部60分别与一个像素电极31和一个驱动晶体管20连接，第三连接部60呈直线状且沿第一方向Y延伸，示例性地，第三连接部60可以在第一方向Y上，沿着第二显示区102、扇出区103以及第一显示区101依次延伸，或者，第三连接部60也可以仅仅在扇出区103内沿着第一方向Y延伸。相邻的第三连接部60沿第二方向X上间隔设置，每个第三连接部60设置于相邻的两个第一连接部40之间。由于第一连接部40和第三连接部60同层设置，且第一连接部40和第三连接部60均为起到电性连接的连接部，因此，在第一连接部40的基础上设置第三连接部60可以提高第一连接部40和第二连接部50之间的结构紧凑性，有利于增加第一连接部40和第三连接部60所在膜层的金属的面积，通过增加分布密度，从而可以进一步避免漏光以及光栅效应等问题。
其中，请继续参考图8，显示面板还包括多个第四连接部70。第四连接部70设置于第二显示区102内，该第四连接部70也可以呈阵列排布，例如可以沿第一方向Y排列为多排，并沿第二方向X排列为多排。每个第四连接部70分别与一个像素电极31和一个驱动晶体管20连接，第四连接部70沿第一方向Y延伸，相邻的第四连接部70沿第一方向Y间隔设置，第四连接部70的中部设置有第三弯折部71,第四连接部70的端部形成有第四弯折部72。
通过在第二显示区102内，将第四连接部70的中部设置为弯折部，从而在单位面积内尽可能地增加每个第一连接部40的长度，由此增加了第四连接部70的分布面积，从而有利于减少显示面板的第二显示区102的透光量，避免漏光以及避免第四连接部70分布过于稀疏致使相邻的第四连接部70之间形成光栅效应问题，进而可以提高显示面板中的第一显示区101和第二显示区102的显示均一性，有利于进一步提升显示面板整体的显示效果。
在一些实施例中，如图3所示，显示面板还可以包括多个第五连接部80。多个第五连接部80也可以呈阵列排布，例如可以沿第一方向Y排列为多排，并沿第二方向X排列为多排。第五连接部80位于第一显示区101内，每个第五连接部80连接于一像素电极31和一第一连接部40之间；或者，每个第五连接部80连接于一像素电极31和一第二连接部50之间。其中，第五连接部80可以用于连接电压信号走线VDD，以此增加驱动晶体管20与信号走线VDD的连接数量，从而可以增强显示驱动能力。
在一些实施例中，第一连接部40包括第一过孔403和第二过孔404，如图8所示，其中第一连接部40通过第一过孔403与像素电极31连接，第一连接部40通过第二过孔404与驱动晶体管20连接，第一过孔403和第二过孔404可以相邻设置，或者第一过孔403和第二过孔404也可以间隔设置。其中，第一过孔403和第二过孔404在衬底基板10上的距离的长短也会影响到第五连接部80的长度，具体地，第一过孔403和第二过孔404之间的距离越长，第五连接部80的走线长度也会越长，第一过孔403和第二过孔404在衬底基板10上的距离越短，第五连接部80的走线长度也会越短。因此，通过第五连接部80的实际长度需要，从而调整第一过孔403和第二过孔404的过孔位置距离，有利于提高第一连接部40实现连接的灵活性。示例性地，通过设每一行的第一连接部40上第一过孔403和第二过孔404的距离相同，从而可以设置第五连接部80的面积的分布具有规律性，从而可以防止在第五连接部80的设置区域中，由于第五连接部80面积不同，导致光的不断反射导致不同的第五连接部80上方的子像素的亮度不同，使得某一处的显示亮度发生明显的突变，即通过控制第五连接部80分布的密度，使得第五连接部80所在的显示区域起到显示效果过渡的作用，以此减弱因第五连接部80的设置引起的显示不均的问题。
由于第三连接部60和第一连接部40的连接关系相同，因此第一过孔403和第二过孔404也可以设置于第三连接部60上，可以具有相同的效果，在此不再赘述。
需要说明的是，第三连接部60、第四连接部70以及第五连接部80也均可以采用透明导电材质制成。具体地，第三连接部60、第四连接部70以及第五连接部80均可以采用氧化铟锡(Indium Tin Oxide，ITO)、氧化铟锌(Indium Zinc Oxide，IZO)、铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)中的任一种或几种形成。其中，第一连接部40、第二连接部50、第三连接部60、第四连接部70以及第五连接部80的材质可以相同，也可以不同，在此不做具体限制。
本申请还提供一种显示装置，该显示装置包括上述的显示面板。本申请实施例的显示装置中的显示面板通过在驱动晶体管20和像素电极31之间设置用于连接外部信号走线第一连接部40，使得每个第一连接部40分别与一个像素电极31和一个驱动晶体管20连接，第一连接部40沿第一方向Y延伸，相邻的第一连接部40间隔设置，第一连接部40的中部设置有第一弯折部41，从而可以在单位面积内尽可能地增加每个第一连接部40的长度，由此增加了第一连接部40的分布面积，从而有利于减少显示面板的透光量，避免漏光以及避免第一连接部40分布过于稀疏致使相邻的第一连接部40之间形成光栅效应问题，进而可以提高显示面板的显示均一性，有利于提升显示效果。
由于该显示装置具有上述显示面板，因此具有全部相同的有益效果，本实施例在此不再赘述。本申请实施例对于所述显示装置的适用不做具体限制，其可以是电视机、笔记本电脑、平板电脑、可穿戴显示设备（如智能手环、智能手表等）、手机、虚拟现实设备、增强现实设备、车载显示、广告灯箱等任何具有显示功能的产品或部件。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
具体实施时，以上各个单元或结构可以作为独立的实体来实现，也可以进行任意组合，作为同一或若干个实体来实现，以上各个单元或结构的具体实施可参见前面的方法实施例，在此不再赘述。
以上对本申请实施例所提供的一种显示面板以及显示装置进行了详细介绍，本文中应用了具体个例对本申请实施例的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请实施例的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其包括：
    衬底基板；
    子像素，阵列设置于所述衬底基板上，每个子像素包括像素电路和发光元件，所述像素电路用于驱动所述发光元件，所述像素电路包括驱动晶体管，所述发光元件包括像素电极；
    多个第一连接部，每个所述第一连接部分别与一个所述像素电极和一个所述驱动晶体管连接，所述第一连接部还用于连接信号走线，多个所述第一连接部沿第一方向延伸，相邻的所述第一连接部间隔设置，所述第一连接部的中部设置有第一弯折部。
  2. 根据权利要求1所述的显示面板，其中，所述第一连接部为蛇形连接部。
  3. 根据权利要求2所述的显示面板，其中，所述第一弯折部为具有折线、曲线以及弧线中的至少一种形状的弯折部。
  4. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    多个第二连接部，每个所述第二连接部分别与一个所述像素电极和一个所述驱动晶体管连接，相邻的所述第二连接部沿第一方向间隔设置形成第一容置空间；
    所述第二连接部和所述第一连接部沿第二方向错位设置，所述第一方向和所述第二方向交叉，所述第一弯折部位于所述第一容置空间内。
  5. 根据权利要求4所述的显示面板，其中，所述第二连接部的中部设置有第二弯折部，相邻的所述第一连接部沿第一方向间隔设置形成第二容置空间，所述第二弯折部位于所述第二容置空间内。
  6. 根据权利要求4所述的显示面板，其中，所述第一连接部还包括两个第一弯折端部，所述第一弯折端部形成第一避位空间；
    所述第二连接部还包括两个第二弯折端部，所述第二弯折端部形成第二避位空间，所述第一弯折端部至少部分位于所述第二避位空间内，所述第二弯折端部至少部分位于所述第一避位空间内。
  7. 根据权利要求4所述的显示面板，其中，所述第一连接部和所述第二连接部采用透明导电材质制成。
  8. 根据权利要求1所述的显示面板，其中，所述驱动晶体管包括：
    有源层，设置于所述衬底基板的一侧；
    栅极层，设置于所述有源层上；
    源漏极层，设置于所述栅极层上，所述第一连接部连接于所述源漏极层和所述像素电极之间。
  9. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    多个第三连接部，所述第一连接部和所述第三连接部同层设置，每个所述第三连接部分别与一个所述像素电极和一个所述驱动晶体管连接，所述第三连接部呈直线状且沿所述第一方向延伸；
    所述第三连接部沿所述第一方向延伸，相邻的所述第三连接部间隔设置，每个所述第三连接部设置于相邻的两个第一连接部之间。
  10. 根据权利要求1所述的显示面板，其中，所述第一连接部包括第一过孔和第二过孔，所述第一连接部通过所述第一过孔与所述像素电极连接，所述第一连接部通过所述第二过孔与所述驱动晶体管连接。
  11. 根据权利要求10所述的显示面板，其中，所述第一过孔和所述第二过孔相邻设置或间隔设置。
  12. 根据权利要求1所述的显示面板，其中，所述显示面板包括第一显示区以及扇出区，所述扇出区与所述第一显示区重合，所述扇出区与所述第二显示区间隔设置，所述第一连接部位于所述第一显示区内。
  13. 根据权利要求12所述的显示面板，其中，所述显示面板还包括第二显示区，所述第一显示区和所述第二显示区相邻设置，所述显示面板还包括：
    多个第四连接部，所述第四连接部设置于所述第二显示区内，每个所述第四连接部分别与一个所述像素电极和一个所述驱动晶体管连接；
    所述第四连接部沿所述第一方向延伸，相邻的所述第四连接部沿第一方向间隔设置，所述第四连接部的中部设置有第三弯折部。
  14. 根据权利要求13所述的显示面板，其中，所述第三连接部在所述第一方向上，沿着所述第二显示区向所述第一显示区延伸。
  15. 一种显示装置，其包括显示面板，所述显示面板包括：
    衬底基板；
    子像素，阵列设置于所述衬底基板上，每个子像素包括像素电路和发光元件，所述像素电路用于驱动所述发光元件，所述像素电路包括驱动晶体管，所述发光元件包括像素电极；
    多个第一连接部，每个所述第一连接部分别与一个所述像素电极和一个所述驱动晶体管连接，所述第一连接部还用于连接信号走线，多个所述第一连接部沿第一方向延伸，相邻的所述第一连接部间隔设置，所述第一连接部的中部设置有第一弯折部。
  16. 根据权利要求15所述的显示装置，其中，所述第一连接部为蛇形连接部，所述第一弯折部为具有折线、曲线以及弧线中的至少一种形状的弯折部。
  17. 根据权利要求15所述的显示装置，其中，所述显示面板还包括：
    多个第二连接部，每个所述第二连接部分别与一个所述像素电极和一个所述驱动晶体管连接，相邻的所述第二连接部沿第一方向间隔设置形成第一容置空间；
    所述第二连接部和所述第一连接部沿第二方向错位设置，所述第一方向和所述第二方向交叉，所述第一弯折部位于所述第一容置空间内。
  18. 根据权利要求17所述的显示装置，其中，所述第二连接部的中部设置有第二弯折部，相邻的所述第一连接部沿第一方向间隔设置形成第二容置空间，所述第二弯折部位于所述第二容置空间内；
    所述第一连接部和所述第二连接部采用透明导电材质制成。
  19. 根据权利要求18所述的显示装置，其中，所述显示面板还包括：
    多个第三连接部，所述第一连接部和所述第三连接部同层设置，每个所述第三连接部分别与一个所述像素电极和一个所述驱动晶体管连接，所述第三连接部呈直线状且沿所述第一方向延伸；
    所述第三连接部沿所述第一方向延伸，相邻的所述第三连接部间隔设置，每个所述第三连接部设置于相邻的两个第一连接部之间。
  20. 根据权利要求19所述的显示装置，其中，所述显示面板还包括第一显示区和第二显示区，所述第一显示区和所述第二显示区相邻设置，所述显示面板还包括：
    多个第四连接部，所述第四连接部设置于所述第二显示区内，每个所述第四连接部分别与一个所述像素电极和一个所述驱动晶体管连接；
    所述第四连接部沿所述第一方向延伸，相邻的所述第四连接部沿第一方向间隔设置，所述第四连接部的中部设置有第三弯折部。
PCT/CN2022/094216 2022-04-26 2022-05-20 显示面板以及显示装置 WO2023206668A1 (zh)

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