WO2023206422A1 - 驱动方法和显示设备 - Google Patents

驱动方法和显示设备 Download PDF

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Publication number
WO2023206422A1
WO2023206422A1 PCT/CN2022/090471 CN2022090471W WO2023206422A1 WO 2023206422 A1 WO2023206422 A1 WO 2023206422A1 CN 2022090471 W CN2022090471 W CN 2022090471W WO 2023206422 A1 WO2023206422 A1 WO 2023206422A1
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WIPO (PCT)
Prior art keywords
time difference
effective
drive signal
gate drive
signal
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PCT/CN2022/090471
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English (en)
French (fr)
Inventor
董杭
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/246,051 priority Critical patent/US20240144886A1/en
Priority to CN202280001033.0A priority patent/CN117321674A/zh
Priority to PCT/CN2022/090471 priority patent/WO2023206422A1/zh
Publication of WO2023206422A1 publication Critical patent/WO2023206422A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
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    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
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    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
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    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a driving method and a display device.
  • a display device such as an OLED display, may include a display panel, a gate driver, a data driver, and a timing controller.
  • the display panel includes a pixel array composed of a plurality of pixels.
  • the gate drive signal generated by the gate driver is provided to the pixel rows, and the data driver provides data voltage to the pixels.
  • the present disclosure provides a driving method and a display device.
  • the present disclosure provides a driving method that sets the timing of a gate drive signal according to an effective time difference between a data signal and an effective signal of the gate drive signal; and drives a pixel array through the gate drive signal.
  • the effective time difference includes the first time difference between the application time of the data signal and the starting time of the effective level of the gate drive signal; according to the effective time difference, setting the timing of the gate drive signal includes: setting the timing of the gate drive signal, Such that, while keeping the effective level durations of the data signal and the gate drive signal unchanged, the first time difference between the application time of the data signal and the start time of the effective level of the gate drive signal is greater than 0.5 of the effective time difference. times and less than the effective time difference.
  • the range of the ratio of the effective time difference to the scanning period of the gate driving signal is 35% to 45%.
  • the ratio of the effective time difference to the scan period of the gate drive signal is 39%.
  • the range of the ratio of the first time difference to the scanning period of the gate driving signal is 22% to 37%.
  • the scanning period of the gate driving signal is 8.7 ⁇ s
  • the first time difference ranges from 1.9 ⁇ s to 3.2 ⁇ s.
  • the first time difference is greater than the transition time of the power supply voltage.
  • the driving method further includes setting the duration of the latch input period according to the effective time difference, so that the time difference between the end time of the latch input period and the start time of the effective level of the gate drive signal of the next scan cycle is greater than the effective time difference. 0.5 times the time difference and less than the effective time difference.
  • the method according to the embodiment of the present disclosure further includes: in the first driving mode, the first time difference is A1; in the second driving mode, the first time difference is A2, and A1 is greater than A2.
  • the present disclosure provides a display device, including: a pixel array; a timing controller; a source driver configured to generate a data signal under the control of the timing controller; and a gate driver configured to generate a data signal under the control of the timing controller.
  • the gate drive signal is generated, wherein the timing controller is configured to set the timing of the gate drive signal according to the effective time difference between the data signal and the effective signal of the gate drive signal, so that the gate drive signal passes Drive the pixel array.
  • the effective time difference includes a first time difference between the application time of the data signal and the starting time of the effective level of the gate drive signal; the timing controller is further configured to: set the timing of the gate drive signal so that when the data signal and When the effective level duration of the gate drive signal remains unchanged, the first time difference between the application time of the data signal and the start time of the effective level of the gate drive signal is greater than 0.5 times the effective time difference and less than the effective time difference.
  • the range of the ratio of the effective time difference to the scanning period of the gate driving signal is 35% to 45%.
  • the ratio of the effective time difference to the scan period of the gate drive signal is 39%.
  • the range of the ratio of the first time difference to the scanning period of the gate driving signal is 22% to 37%.
  • the scanning period of the gate driving signal is 8.7 ⁇ s
  • the first time difference ranges from 1.9 ⁇ s to 3.2 ⁇ s.
  • the first time difference is greater than the transition time of the power supply voltage.
  • the timing controller is further configured to set the duration of the latch input period according to the effective time difference, such that the time difference between the end time of the latch input period and the start time of the effective level of the gate drive signal of the next scan cycle Greater than 0.5 times the effective time difference and less than the effective time difference.
  • the display device of the embodiment of the present disclosure further includes an external sink power supply disposed between the voltage source of the source driver and the pixel array.
  • the display device of the embodiment of the present disclosure further includes a resistor disposed between the voltage source of the source driver and the pixel array.
  • the timing controller is further configured to set: in the first driving mode, the first time difference is A1; in the second driving mode, the first time difference is A2, and A1 is greater than A2.
  • Figure 1A is a signal timing diagram for driving a display panel according to an example
  • Figure 1B is a schematic diagram of an abnormal display screen of the display device driven by the signal timing diagram of Figure 1A;
  • Figure 2 is a flow chart of a driving method according to an embodiment of the present disclosure
  • Figure 3 is a signal timing diagram according to an embodiment of the present disclosure.
  • Figure 4 is a signal timing diagram according to another embodiment of the present disclosure.
  • Figure 5A is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • Figure 5B is a signal timing diagram of the pixel circuit in Figure 5A;
  • Figure 6 is a block diagram of a display device according to one embodiment of the present disclosure.
  • FIG. 7 is a block diagram of a display device according to another embodiment of the present disclosure.
  • connection may mean that two components are directly connected, or may mean that two components are connected via one or more other components. Additionally, the two components can be connected or coupled via wired or wireless means.
  • the symbol Vdata can represent both the data signal and the level of the data signal.
  • the symbol Gate can represent both the gate drive signal and the level of the gate drive signal
  • the symbol VINT can represent both the predetermined initial voltage terminal and the voltage of the initial signal
  • the symbol ELVDD can represent both the power supply and the power supply. supply voltage provided.
  • FIG. 1A is a signal timing diagram for driving a display panel according to an example.
  • FIG. 1B is a schematic diagram of an abnormal display screen of the display device driven by the signal timing diagram of FIG. 1A.
  • the period a may be a period in which the start time of the effective level of the gate drive signal Gate is later than the application time of the data signal Vdata
  • the period b may be a time period in which the end time of the effective level of the gate drive signal Gate is later than the end application time of the data signal Vdata. period in advance. If the noise generated by the jump of the power supply voltage VDD is not eliminated at the starting moment of the effective level of the gate drive signal Gate, that is, during period a, crosstalk will appear on the display screen of the display panel, affecting the performance of the display panel. display effect.
  • the display panel includes pixel units 110, 120, and 130.
  • the gate driving signal Gate scans the pixel unit line by line.
  • the applied data signal Vdata causes the pixel unit 110 to display a black image, and the pixel unit 120 and the pixel unit 130 to display a white image. Due to the noise generated by the jump of the power supply voltage VDD, the pixel unit 120 and the pixel unit 130 are affected by the crosstalk of the pixel unit 110, and the pixel unit 120 and the pixel unit 130 are actually displayed as gray images, thereby affecting the display effect of the display panel.
  • the present disclosure provides a driving method for driving a pixel array, including setting the timing of a gate drive signal according to an effective time difference between a data signal and an effective signal of the gate drive signal; and driving the pixel array through the gate drive signal.
  • FIG. 2 is a flowchart of a driving method according to an embodiment of the present disclosure.
  • the driving method may include operations S210 to S220.
  • the application time of the data signal is before the start time of the effective level of the gate drive signal, and the end application time of the data signal is after the end time of the effective level of the gate drive signal.
  • the range of the ratio of the effective time difference to the scanning period of the gate driving signal is 35% to 45%.
  • the effective time difference between the data signal and the effective signal of the gate driving signal shown in FIG. 1A includes a period a and a period b.
  • the scanning period of the gate driving signal is 1H.
  • the scanning period of the gate driving signal is the time required to scan one row of the pixel array.
  • the effective time difference can be fixed. According to the effective time difference, setting the timing of the gate drive signal can completely eliminate the noise caused by the jump of the power supply voltage VDD before the starting moment of the effective level of the gate drive signal, thereby mitigating the crosstalk that occurs on the display panel. Phenomenon.
  • the pixel array is driven by the gate drive signal.
  • a display panel includes a pixel array, and by setting the timing of a gate drive signal according to disclosed embodiments, and the gate drive signal drives the pixel array, the crosstalk phenomenon occurring on the display panel can be alleviated.
  • the noise caused by the jump of the power supply voltage VDD can be completely eliminated before the starting moment of the effective level of the gate drive signal, thereby alleviating the crosstalk phenomenon on the display panel.
  • the present disclosure provides an embodiment of setting the timing of a gate drive signal.
  • the effective time difference includes a first time difference between the application time of the data signal and the start time of the effective level of the gate drive signal.
  • the step of setting the timing of the gate drive signal includes setting the timing of the gate drive signal such that the validity of the data signal and the gate drive signal is maintained.
  • the first time difference is greater than 0.5 times the effective time difference and less than the effective time difference.
  • the range of the ratio of the first time difference to the scanning period of the gate driving signal is 22% to 37%.
  • the first time difference and the second time difference may be equal to 0.5 times the effective time difference.
  • the first time difference and the second time difference are both 1.7 ⁇ s.
  • the default value of the first time difference and the second time difference can be 0.5 times the effective time difference, for example, 1.7 ⁇ s.
  • the first time difference can be increased by delaying the starting moment of the effective level of the gate drive signal, so that the first time difference is greater than 0.5 times the effective time difference and Less than the effective time difference.
  • the first time can be greater than the duration of the supply voltage jump.
  • the noise generated by the jump of the power supply voltage VDD can be completely eliminated before the starting moment of the effective level of the gate drive signal, thereby mitigating the crosstalk phenomenon on the display panel.
  • the effective time difference (period a and period b) can be considered to be unchanged.
  • the first time difference (period a) increases relative to the default value (the first time difference is 0.5 times the effective time difference)
  • the second time difference (period b) will decrease accordingly.
  • the first time difference also needs to be smaller than the effective time difference. If the first time difference is increased without limit, the second time difference will not exist, that is, the end time of applying the data signal is before the end time of the effective level of the gate drive signal, which will cause the drive transistor to have no data when it is turned on. Signals can be written to.
  • the present disclosure provides a driving method of another embodiment.
  • the driving method also includes setting the duration of the latch input period according to the effective time difference, so that the end time of the latch input period starts with the effective level of the gate drive signal of the next scan cycle.
  • the time difference between moments is greater than 0.5 times the effective time difference and less than the effective time difference.
  • the interval between two adjacent data signals is the latch input period.
  • Changing the latch input period Latch Input will cause the frequency of the data signal to change, causing the application time of the data signal to change in the next scan cycle.
  • reducing the latch input period Latch Input will cause the application time of the data signal in the next scan cycle to advance.
  • changes in the latch input period Latch Input also cause changes in the data signal reference voltage AVDD, thereby changing the transition time point of the power supply voltage signal VDD.
  • Figure 4 is a signal timing diagram according to another embodiment of the present disclosure.
  • Gate(N) represents the gate signal of the Nth row pixel
  • Gate(N+1) represents the gate signal of the N+1th row pixel
  • Gate(N+2) represents the N+2th row.
  • the duration of the first latch input period of the ordinary timing of the data signal is Latch input 1.
  • the signal timing diagram shown in Figure 4 can be achieved by first setting the timing of the gate drive signal and then setting the duration of the latch input period while keeping the effective level duration of the gate drive signal unchanged. Time gets.
  • FIG. 4 is only for showing the change in the first time difference caused by the change in the latch input period.
  • the duration of the latch input period remains unchanged.
  • the duration of the latch input period in the timing sequence of the data signal is set to Latch input 2.
  • the driving method may also be to set the duration of the latch input period without changing the default timing of the gate drive signal, so that the end moment of the latch input period coincides with the validity of the gate drive signal of the next scan cycle.
  • the time difference between the level starting moments is greater than 0.5 times the effective time difference and less than the effective time difference.
  • the duration of the latch input period may be 1.5 ⁇ s.
  • the first time difference can be increased by reducing the duration of the latch input period, so that the first time difference is greater than 0.5 times the effective time difference and less than Effective time difference.
  • the duration of the latch input period can be set from 1.2 ⁇ s to 0.3 ⁇ s.
  • the duration of the latch input period can be set to 0.4 ⁇ s.
  • the overlap length of the data signal application duration and the gate drive signal turn-on duration can be kept fixed. In this way, it is ensured that when the gate drive signal is output to each row, the effective data signal time loaded by it is basically the same.
  • the transistors T1 to T7 may be P-type transistors.
  • the low level of the reset signal Reste1 is the effective level.
  • the initialization signal VINT initializes the gate of the driving transistor T3, thereby initializing the gate voltage of the driving transistor T3 to VINT and charging the storage capacitor CST at the same time.
  • the low level of the gate drive signal Gate and the low level of the reset signal Reste2 are effective levels. Under the control of the gate drive signal Gate, the transistors T2 and T4 are turned on. The driving transistor T3 is driven by the voltage signal stored in the storage capacitor CST to be turned on. The data signal Vdata is written to the node N1 via the transistors T4, T3 and T2 along from the data signal terminal to the node N1.
  • the transistor T7 Under the control of the reset signal Reste2, the transistor T7 is turned on, and the initialization signal VINT is written to the anode of the light-emitting element EL along the initialization path from the predetermined initial voltage terminal to the light-emitting element EL, thereby initializing the anode voltage of the light-emitting element EL. is VINT.
  • VINT-ELVSS the voltage difference between the initial signal terminal VINT and the second power terminal ELVSS (VINT-ELVSS) should be less than the threshold voltage Voled of the light-emitting element EL.
  • ELVSS is the voltage at the second terminal of the light-emitting element OLED
  • Voled is the light-emitting threshold voltage of the light-emitting element EL. This ensures that the light-emitting element EL does not emit light during the data writing phase.
  • the low level of the light-emitting control signal EM is the effective level.
  • the transistor T5 and the transistor T6 are turned on.
  • the driving transistor T3 is driven by the voltage signal stored in the storage capacitor CST to be turned on.
  • the transistor T5 and the transistor T6 are turned on, and the driving current is applied to the light-emitting element EL along the light-emitting path from the power supply to the light-emitting element EL via the transistor T5, the driving transistor T3 and the transistor T6, so that the light-emitting element EL emits light.
  • transistors T1 to T2 are N-type transistors, and T3 to T7 can be P-type transistors.
  • a crosstalk test is performed on a display panel including the pixel circuit shown in Figure 5A.
  • the display scanning frame frequency is 60Hz
  • the resolution of the display panel is 1915 lines
  • the effective time difference a+b 3.4 ⁇ s
  • the first time difference a and The default value of the second time difference b is 1.7 ⁇ s.
  • the ratio of the effective time difference to the scanning period of the gate drive signal is 39%.
  • the scanning period H of the gate driving signal Gate can be determined by the scanning frame frequency and the number of resolution lines of the display panel.
  • the scanning frame rate is 60Hz and the resolution of the display panel is 1915 lines.
  • the resolution rows of the display panel may include real rows and virtual rows.
  • the real behavior has 1888 lines and the virtual behavior has 27 lines.
  • the gate drive signal scans the virtual rows first and then the real rows.
  • the display panel can also have other resolutions, such as 10-30HZ, or 90HZ-120HZ, or other resolutions, such as a resolution of 2360 lines, etc.
  • the values of the first time difference a and the second time difference b are changed by setting the timing of the gate drive signal and/or setting the duration of the latch input period.
  • the first time difference a is about 22 to 37% of 1/F
  • F driving frequency * number of resolution lines.
  • Embodiments of the present disclosure change the ratio of the first time difference a to the second time difference b by setting the timing of the gate drive signal and/or setting the duration of the latch input period.
  • the display panel including the pixel circuit shown in FIG. 5A was subjected to a crosstalk test using the driving method according to the embodiment of the present disclosure. The test results are shown in Table 1. During the test, the ratio a/b of the first time difference to the second time difference ranges from 0.0625 to 16. The lower the crosstalk level, the more serious the crosstalk phenomenon is.
  • the ratio a/b of the first time difference to the second time difference can range from 1.27 to 16, and the range of the first time difference can be set to 1.9 ⁇ s ⁇ 3.2 ⁇ s.
  • test points are randomly selected in the display area of the display panel including the pixel circuit shown in Figure 5A, and crosstalk test values are performed on the test points.
  • the crosstalk test values in the horizontal and vertical directions of each test point are tested by setting the timing of the gate drive signal and setting the duration of the latch input period.
  • the crosstalk test values of 4 test points are as shown in Table 2, and the crosstalk test values of 4 test points using the technical solution according to the embodiment of the present disclosure are as follows As shown in Table 3.
  • the duration of the latch input period is 1.5 ⁇ s
  • the ratio a/b of the first time difference to the second time difference ranges from 1.
  • the first time difference and the second time difference can both be set to the default value of 1.7 ⁇ s.
  • the duration of the latch input period is 0.4 ⁇ s
  • the ratio a/b of the first time difference to the second time difference ranges from 1.27 to 16
  • the duration of the first time difference and the latch input period The ratio range is 475 to 8.
  • the first time difference is 3.2
  • the second time difference is 0.2
  • the ratio of the first time difference to the duration of the latch input period is 8.
  • the crosstalk test value of test point 2 in the horizontal direction H is 2.35%, indicating that test point 2 has serious crosstalk in the horizontal direction.
  • the crosstalk test values of the four test points in the horizontal and vertical directions are all less than 2.00%, indicating that almost all test points according to the technical solution of the embodiment of the present disclosure have no Crosstalk occurs.
  • the crosstalk test value of test point 2 in the horizontal direction H is 0.95%, indicating that there is almost no crosstalk phenomenon in the horizontal direction of test point 2. , it can be verified that the crosstalk phenomenon is improved by setting the timing of the gate drive signal and setting the duration of the latch input period. After increasing the ratio a/b of the first time difference to the second time difference, the crosstalk phenomenon of the display panel is obtained ease.
  • the working modes include high-frequency drive and low-frequency drive.
  • the first drive mode is high-frequency drive (for example: 60HZ-240HZ)
  • the second drive mode is low-frequency drive (for example: 10HZ-50HZ); of course, the second drive mode can also be high-frequency drive (for example: 10HZ-50HZ).
  • the first drive mode is low-frequency drive (for example: 10HZ-50HZ).
  • the first time difference in the high-frequency driving mode (120HZ) is smaller than the first time difference in the low-frequency driving mode (30HZ).
  • the timing of the gate drive signal and/or the duration of the latch input period is set so that the first time difference and the second time difference have a ratio greater than 1.
  • the first time difference is greater than 0.5 times the effective time difference
  • the power supply voltage ELVDD jumps away from the effective level of the gate drive signal, and the noise generated by the jump of the power supply voltage ELVDD can occur at the beginning of the effective level of the gate drive signal. Eliminate before time.
  • the jumped power supply voltage ELVDD has basically returned to the normal power supply voltage ELVDD, preventing noise interference from being written into the storage capacitor CST and improving the crosstalk phenomenon.
  • the timing of the light emission control signal EM can also be set according to the timing of the gate drive signal. Since the starting moment of the valid level of the gate drive signal is delayed relative to the starting moment of the valid level in the ordinary timing sequence, the reset signal Reste1 can be set so that the duration of the valid level of the reset signal Reste1 remains unchanged. In the case of , the starting time of the effective level of the reset signal Reste1 is delayed by the same amplitude as the starting time of the effective level of the gate drive signal. Therefore, by setting the timing of the light emission control signal, the duration of the effective level of the light emission control signal in the previous scanning period can be extended relative to the default duration of the effective level of the light emission control signal. By extending the duration of the effective level of the light-emitting control signal, the average current density can be reduced, thereby extending the life of the light-emitting element EL.
  • FIG. 6 is a block diagram of a display device according to one embodiment of the present disclosure.
  • the display device 600 may include a pixel array 610, a timing controller 620, a source driver 630, and a gate driver 640.
  • Pixel array 610 includes a plurality of pixels.
  • the plurality of pixels are located in the intersection areas of the plurality of scan lines S, the plurality of data lines DL, and the plurality of light emission control lines EM.
  • the source driver 630 is configured to generate a data signal under the control of the timing controller 620 .
  • the gate driver 640 is configured to generate a gate drive signal under the control of the timing controller 620,
  • the timing controller 620 is configured to set the timing of the gate drive signal according to the effective time difference between the data signal and the effective signal of the gate drive signal, so that the pixel array is driven by the gate drive signal.
  • the timing controller 620 , the source driver 630 and the gate driver 640 are configured to perform the driving method of the previously described embodiment to drive the pixel array 610 .
  • the timing controller 620 is configured to perform the operation S210 described above, which will not be described again here.
  • the effective time difference includes a first time difference between the application time of the data signal and the start time of the effective level of the gate drive signal.
  • the timing controller 620 is further configured to set the timing of the gate drive signal so that, while keeping the effective level durations of the data signal and the gate drive signal unchanged, the application moment of the data signal is consistent with the effective level of the gate drive signal.
  • the first time difference between the flat start times is greater than 0.5 times the effective time difference and less than the effective time difference.
  • the range of the ratio of the effective time difference to the scanning period of the gate driving signal is 35% to 45%.
  • the ratio of the effective time difference to the scan period of the gate drive signal is 39%.
  • the range of the ratio of the first time difference to the scanning period of the gate driving signal is 22% to 37%.
  • the scanning period of the gate driving signal is 8.7 ⁇ s
  • the first time difference ranges from 1.9 ⁇ s to 3.2 ⁇ s.
  • the first time difference is greater than the transition time of the power supply voltage, and the transition time of the power supply voltage is related to the reference voltage of the data signal.
  • the timing controller 620 is further configured to set the duration of the latch input period according to the effective time difference, so that the time between the end time of the latch input period and the start time of the effective level of the gate drive signal of the next scan cycle is The time difference is less than the effective time difference.
  • FIG. 7 is a block diagram of a display device according to another embodiment of the present disclosure.
  • the display device 700 may include a pixel array 710, a timing controller 720, a source driver 730, a gate driver 740, a power supply chip Power IC 750, and a gamma correction chip GAM IC 760.
  • the pixel array 710, the timing controller 720, the source driver 730 and the gate driver 740 respectively have similar functions to the display device shown in FIG. 6 including the pixel array 610, the timing controller 620, the source driver 630 and the gate driver 640. . For the sake of simplicity, no further details are provided in this disclosure.
  • the power chip Power IC 750 is used to input the reference voltage AVDD of the data signal to the gamma correction chip GAM IC760.
  • the gamma correction chip GAM IC 760 is used to perform gamma correction on the reference voltage AVDD of the data signal and convert the corrected data signal
  • the reference voltage AVDD is input to the pixel array 610 .
  • the power chip Power IC 750 is also configured to input an initialization signal VINT to the pixel array 610.
  • the display panel can be tested for the water ripple phenomenon by arranging external devices, such as external power supply, voltage stabilizing capacitor or filter resistor, at the N point, P point and Q point as shown in Figure 7. Crosstalk test.
  • external devices such as external power supply, voltage stabilizing capacitor or filter resistor
  • the water ripple test and crosstalk test were performed on the display panel including the pixel circuit shown in Figure 5A.
  • the hardware conditions for the test include setting relevant external devices at N point, P point and Q point respectively on the path of the reference voltage of the input data signal as shown in Figure 7, modifying the working mode of Power IC750 and replacing Power IC750 with Power IC 2 .
  • the duration of the latch input period of the data line input during testing includes 0.4 ⁇ s and 1.5 ⁇ s.
  • the test results are shown in Table 4.
  • N means that the phenomenon shown in the table does not exist, and Y means that the phenomenon shown in the table exists. Since the purpose of setting external devices at Q point is to improve the water ripple phenomenon, Table 4 does not show the test results of setting relevant external devices at Q point.
  • the reference voltage of the data signal can be optimized to improve the water ripple problem.
  • An external power supply or filter resistor can also be set between the power chip Power IC 750 and the pixel array 710 to optimize the reference voltage of the data signal, thereby alleviating the water ripple problem.
  • each block in the flowchart or block diagrams may represent a module, segment, or portion of code that contains one or more logic functions that implement the specified executable instructions.
  • the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown one after another may actually execute substantially in parallel, or they may sometimes execute in the reverse order, depending on the functionality involved.
  • each block in the block diagram or flowchart illustration, and combinations of blocks in the block diagram or flowchart illustration can be implemented by special purpose hardware-based systems that perform the specified functions or operations, or may be implemented by special purpose hardware-based systems that perform the specified functions or operations. Achieved by a combination of specialized hardware and computer instructions.

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Abstract

一种驱动方法，涉及显示技术领域。驱动方法用于驱动像素阵列，包括操作(S210)至操作(S220)：在操作(S210)，根据数据信号(Vdata)和栅极驱动信号(Gate)的有效信号之间的有效时间差，设置栅极驱动信号(Gate)的时序；在操作(S220)，通过栅极驱动信号(Gate)驱动像素阵列。还提供了一种显示设备(600)。

Description

驱动方法和显示设备 技术领域
本公开涉及显示技术领域，尤其涉及一种驱动方法和显示设备。
背景技术
显示设备(例如OLED显示器)可以包括显示面板、栅极驱动器、数据驱动器和时序控制器。显示面板中包含由多个像素构成的像素阵列，栅极驱动器产生的栅极驱动信号被提供至像素行，数据驱动器向像素提供数据电压。
然而，数据信号的变化会引起电源电压的波动，从而使显示面板在显示画面时出现串扰现象，影响显示面板的显示效果。
发明内容
本公开提供了一种驱动方法和显示设备。
根据第一方面，本公开提供了一种驱动方法，根据数据信号和栅极驱动信号的有效信号之间的有效时间差，设置栅极驱动信号的时序；以及通过栅极驱动信号驱动像素阵列。
例如，有效时间差包括数据信号的施加时刻与栅极驱动信号的有效电平起始时刻之间的第一时间差；根据有效时间差，设置栅极驱动信号的时序包括：设置栅极驱动信号的时序，使得在保持数据信号和栅极驱动信号的有效电平持续时间不变的情况下，数据信号的施加时刻与栅极驱动信号的有效电平起始时刻之间的第一时间差大于有效时间差的0.5倍且小于有效时间差。
例如，有效时间差与栅极驱动信号的扫描周期比值的范围为35～45％。
例如，有效时间差与栅极驱动信号的扫描周期比值为39％。
例如，第一时间差与栅极驱动信号的扫描周期比值的范围为22～37％。
例如，栅极驱动信号的扫描周期为8.7μs，第一时间差的范围为1.9μs～3.2μs。
例如，第一时间差大于电源电压的跳变时间。
例如，驱动方法还包括根据有效时间差，设置锁存输入时段的持续时间，使得锁存输入时段的结束时刻与下一扫描周期的栅极驱动信号的有效电平起始时刻之间的时间差大于有效时间差的0.5倍且小于有效时间差。
例如，根据本公开实施例的方法还包括：第一驱动模式，第一时间差为A1；第二驱动模式，第一时间差为A2，A1大于A2。
根据第二方面，本公开提供了一种显示设备，包括：像素阵列；时序控制器；源极驱动器，配置为在时序控制器的控制下，生成数据信号；以及栅极驱动器，配置为在时序控制器的控制下，生成栅极驱动信号，其中，时序控制器配置为根据数据信号和栅极驱动信号的有效信号之间的有效时间差，设置栅极驱动信号的时序，以便通过栅极驱动信号驱动像素阵列。
例如，有效时间差包括数据信号的施加时刻与栅极驱动信号的有效电平起始时刻之间的第一时间差；时序控制器还配置为：设置栅极驱动信号的时序，使得在保持数据信号和栅极驱动信号的有效电平持续时间不变的情况下，数据信号的施加时刻与栅极驱动信号的有效电平起始时刻之间的第一时间差大于有效时间差的0.5倍且小于有效时间差。
例如，有效时间差与栅极驱动信号的扫描周期比值的范围为35～45％。
例如，有效时间差与栅极驱动信号的扫描周期比值为39％。
例如，第一时间差与栅极驱动信号的扫描周期比值的范围为22～37％。
例如，栅极驱动信号的扫描周期为8.7μs，第一时间差的范围为1.9μs～3.2μs。
例如，第一时间差大于电源电压的跳变时间。
例如，时序控制器还配置为根据有效时间差，设置锁存输入时段的持续时间，使得锁存输入时段的结束时刻与下一扫描周期的栅极驱动信号的有效电平起始时刻之间的时间差大于有效时间差的0.5倍且小于有效时间差。
例如，本公开实施例的显示设备还包括外灌电源，设置在源极驱动器的电压源与像素阵列之间。
例如，本公开实施例的显示设备还包括电阻，设置在源极驱动器的电压源与像素阵列之间。
例如，时序控制器还配置为设置：第一驱动模式，第一时间差为A1；第二驱动模式，第一时间差为A2，A1大于A2。
附图说明
图1A是根据一个示例驱动显示面板的信号时序图；
图1B是显示设备在图1A信号时序图驱动下异常显示画面的示意图；
图2是根据本公开一个实施例的驱动方法的流程图；
图3是根据本公开一个实施例的信号时序图；
图4是根据本公开另一个实施例的信号时序图；
图5A是根据本公开一个实施例的像素电路的结构示意图；
图5B为图5A中像素电路的信号时序图；
图6是根据本公开一个实施例的显示设备的框图；以及
图7是根据本公开另一个实施例的显示设备的框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部。基于所描述的本公开实施例，本领域普通技术人员在无需创造性劳动的前提下获得的所有其他实施例都属于本公开保护的范围。应注意，贯穿附图，相同的元素由相同或相近的附图标记来表示。在以下描述中，一些具体实施例仅用于描述目的，而不应该理解为对本公开有任何限制，而只是本公开实施例的示例。在可能导致对本公开的理解造成混淆时，将省略常规结构或配置。应注意，图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。
除非另外定义，本公开实施例使用的技术术语或科学术语应当是本领域技术人员所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似词语并不表示任何顺序、数量或重要性，而只是用于区分不同的组成部分。
此外，在本公开实施例的描述中，术语“相连”或“连接至”可以是指两个组件直接连接，也可以是指两个组件之间经由一个或多个其他组件相连。此外，这两个组件可以通过有线或无线方式相连或相耦合。
需要说明是，在本公开实施例的说明中，符号Vdata既可以表示数据信号又可以表示数据信号的电平。同样地，符号Gate既可以表示栅极驱动信号又可以表示栅极驱动信号的电平，符号VINT既可以表示预定初始电压端又可以表示初始信号的电压，符号ELVDD既可以表示电源又可以表示电源提供的电源电压。以下各实施例与此相同，不再赘述。
图1A是根据一个示例驱动显示面板的信号时序图。图1B是显示设备在图1A信号时序图驱动下异常显示画面的示意图。
如图1A所示，在施加数据信号Vdata时，数据信号Vdata的参考电压AVDD的变 化会引起电源电压VDD的跳变。时段a可以是栅极驱动信号Gate有效电平的起始时刻比数据信号Vdata的施加时刻延迟的时段，时段b可以是栅极驱动信号Gate有效电平的结束时刻比数据信号Vdata的结束施加时刻提前的时段。若在栅极驱动信号Gate有效电平的起始时刻，也就是在时段a内，由于电源电压VDD跳变所产生的噪声未消除，显示面板的显示画面上会出现串扰现象，影响显示面板的显示效果。
如图1B所示，显示面板包括像素单元110、120和130。在显示过程中，栅极驱动信号Gate逐行扫描像素单元。施加的数据信号Vdata使像素单元110显示黑色图像，使像素单元120和像素单元130显示白色图像。由于电源电压VDD跳变所产生的噪声，像素单元120和像素单元130受像素单元110的串扰影响，像素单元120和像素单元130实际显示为灰色图像，从而影响显示面板的显示效果。
本公开提供一种驱动方法，用于驱动像素阵列，包括根据数据信号和栅极驱动信号的有效信号之间的有效时间差，设置栅极驱动信号的时序；以及通过栅极驱动信号驱动像素阵列。
图2是根据本公开一个实施例的驱动方法的流程图。
如图2所示，驱动方法可以包括操作S210至操作S220。
在操作S210，根据数据信号和栅极驱动信号的有效信号之间的有效时间差，设置栅极驱动信号的时序。
例如，数据信号比栅极驱动信号的有效电平的持续时间长，可以避免驱动晶体管在导通的情况下未写入数据信号。在一个扫描周期内，数据信号的施加时刻位于栅极驱动信号的有效电平起始时刻之前，数据信号的结束施加时刻位于栅极驱动信号有效电平的结束时刻之后。有效时间差与栅极驱动信号的扫描周期比值的范围为35～45％。可参见图1A示出的数据信号和栅极驱动信号的有效信号之间的有效时间差包括时段a和时段b。栅极驱动信号的扫描周期为1H，例如：栅极驱动信号的扫描周期为扫描像素阵列的一行所需要的时间。
例如，对于任意的像素阵列，有效时间差可以是固定不变的。根据有效时间差，设置栅极驱动信号的时序，可以使由于电源电压VDD跳变所产生的噪声在栅极驱动信号有效电平的起始时刻之前完全被消除，从而能够缓解显示面板上出现的串扰现象。
在操作220，通过栅极驱动信号驱动像素阵列。
例如，显示面板包括像素阵列，通过根据公开实施例设置栅极驱动信号的时序，栅极驱动信号驱动像素阵列，能够缓解显示面板上出现的串扰现象。
通过本公开实施例，可以让由于电源电压VDD跳变所产生的噪声在栅极驱动信号有效电平的起始时刻之前完全消除，缓解显示面板上出现的串扰现象。
本公开提供一种设置栅极驱动信号的时序的实施例。有效时间差包括数据信号的施加时刻与栅极驱动信号的有效电平起始时刻之间的第一时间差。
操作S210，根据数据信号和栅极驱动信号的有效信号之间的有效时间差，设置栅极驱动信号的时序的步骤包括设置栅极驱动信号的时序，使得在保持数据信号和栅极驱动信号的有效电平持续时间不变的情况下，第一时间差大于有效时间差的0.5倍且小于有效时间差。第一时间差与栅极驱动信号的扫描周期比值的范围为22～37％。
图3是根据本公开一个实施例的信号时序图。如图3所示，栅极驱动信号的低电平为有效电平。图3的示例中，Gate(N)表示第N行像素的栅极信号，Gate(N+1)表示第N+1行像素的栅极信号，其中，N为大于等于1的整数。第一时间差为时段a，第一时间差大于有效时间差的0.5倍且小于有效时间差。有效时间差还包括栅极驱动信号有效电平的结束时刻与数据信号的结束施加时刻之间的第二时间差。第二时间差为时段b。第二时间差b小于有效时间差的0.5倍且大于0。
例如，对于栅极驱动信号的一种普通时序，第一时间差与第二时间差可以均等于有效时间差的0.5倍。例如，对于栅极驱动信号的默认时序，栅极驱动信号有效电平的持续时间与数据信号的有效时间差为3.4μs时，第一时间差和第二时间差均为1.7μs。此时，可认为第一时间差和第二时间差的默认值可以为有效时间差的0.5倍，例如1.7μs。在保持栅极驱动信号的有效电平持续时间不变的情况，可以通过延迟栅极驱动信号的有效电平的起始时刻，增大第一时间差，使得第一时间差大于有效时间差的0.5倍且小于有效时间差。
第一时间可以大于电源电压跳变的持续时间。在第一时间差足够大的情况下，电源电压VDD跳变所产生的噪声可以在栅极驱动信号有效电平的起始时刻之前完全被消除，从而缓解显示面板上出现的串扰现象。
可选的，第一时间差为电源电压VDD跳变时间的1.2倍-2.4倍，如此可以更好的保证电源电压VDD跳变所产生的噪声可以在栅极驱动信号有效电平的起始时刻之前完全被消除。例如：第一时间差为2.4-3.2μs，大于电源电压跳变的持续时间2.0μs。
由于数据信号和栅极驱动信号的有效电平持续时间不变，因此有效时间差(时段a和时段b)可以认为是不变的。在第一时间差(时段a)相对于默认值(第一时间差为有效时间差的0.5倍)增大的情况下，第二时间差(时段b)会相应地减小。此外，第 一时间差也需要小于有效时间差。如果无限制地增加第一时间差，会使得第二时间差不存在，也就是数据信号的结束施加时刻在栅极驱动信号有效电平的结束时刻之前，进而造成驱动晶体管在导通的情况下无数据信号可以写入。
本公开提供另一实施例的驱动方法。驱动方法在操作S210至操作S220的基础上还包括根据有效时间差，设置锁存输入时段的持续时间，使得锁存输入时段的结束时刻与下一扫描周期的栅极驱动信号的有效电平起始时刻之间的时间差大于有效时间差的0.5倍且小于有效时间差。
相邻两个数据信号之间的间隔为锁存输入时段Latch input。改变锁存输入时段Latch Input会导致数据信号频率的变化，使下一扫描周期内数据信号的施加时刻改变。例如，减小锁存输入时段Latch Input会导致下一扫描周期内数据信号的施加时刻提前。同时锁存输入时段Latch Input的改变也导致数据信号参考电压AVDD的变化，进而改变电源电压信号VDD的跳变时间点。
图4是根据本公开另一个实施例的信号时序图。图4的示例中，Gate(N)表示第N行像素的栅极信号，Gate(N+1)表示第N+1行像素的栅极信号，Gate(N+2)表示第N+2行像素的栅极信号。如图4所示，数据信号的普通时序的第一锁存输入时段的持续时间为Latch input 1。例如，图4所示出的信号时序图可以是在保持栅极驱动信号的有效电平持续时间不变的情况下，通过先设置栅极驱动信号的时序，再通过设置锁存输入时段的持续时间得到的。先设置栅极驱动信号的时序，使得第一时间差(时段a)大于有效时间差的0.5倍且小于有效时间差。再设置第二锁存输入时段的持续时间为Latch input 2，第二锁存输入时段的持续时间Latch input 2小于第一锁存输入时段的持续时间Latch input 1短，使得此时针对第N+1行像素的数据信号的施加开始时刻与下一行栅极驱动信号Gate(N+1)的有效电平起始时刻之间的第一时间差(时段a’)大于针对第N行像素的数据信号的施加开始时刻与第N行栅极驱动信号Gate(N)的有效电平起始时刻之间的第一时间差(时段a)。第二时间差a’也大于有效时间差的0.5倍且小于有效时间差。
需要说明的是，图4仅为了示出由于锁存输入时段Latch input持续时间的变化会导致第一时间差的改变。可选的，在实际的驱动应用中，在设置锁存输入时段的持续时间后，锁存输入时段的持续时间不变。例如，在本公开实施例中，设置数据信号的时序中锁存输入时段的持续时间为Latch input 2。
例如，驱动方法还可以是在不改变栅极驱动信号的默认时序的情况下，设置锁存输 入时段的持续时间，使得锁存输入时段的结束时刻与下一扫描周期的栅极驱动信号的有效电平起始时刻之间的时间差大于有效时间差的0.5倍且小于有效时间差。
例如，数据信号的上述普通时序中，锁存输入时段的持续时间可以为1.5μs。在保持数据信号施加持续时间和栅极驱动信号的普通时序不变的情况，可以通过减小锁存输入时段的持续时间，增大第一时间差，使得第一时间差大于有效时间差的0.5倍且小于有效时间差。锁存输入时段的持续时间可以被设置1.2μs-0.3μs。
可选的，锁存输入时段的持续时间可以被设置为0.4μs。
可选的，可以保持数据信号施加持续时间与栅极驱动信号开启的持续时间交叠长度固定。如此，保证栅极驱动信号输出到各行时，其加载的有效数据信号时间基本一致。
图5A是根据本公开一个实施例的像素电路的结构示意图。图5B为图5A中像素电路的信号时序图。
图5A和5B所示，在图5A的示例中，晶体管T1～T7可以为P型晶体管。在初始化阶段，复位信号Reste1的低电平为有效电平。
在复位信号Reste1的控制下，晶体管T1导通。初始化信号VINT对驱动晶体管T3的栅极进行初始化，从而将驱动晶体管T3的栅极电压初始化为VINT，同时对存储电容CST充电。
在数据写入阶段，栅极驱动信号Gate的低电平和复位信号Reste2的低电平为有效电平。在栅极驱动信号Gate的控制下，晶体管T2和T4导通。驱动晶体管T3在存储电容CST存储的电压信号的驱动下导通。数据信号Vdata沿着从数据信号端到节点N1经由晶体管T4、T3和T2被写入到节点N1。在复位信号Reste2的控制下，晶体管T7导通，初始化信号VINT沿着从预定初始电压端到发光元件EL的初始化路径，被写入到发光元件EL的阳极，从而将发光元件EL的阳极电压初始化为VINT。
可以理解，初始信号端VINT与第二电源端ELVSS的电压差(VINT-ELVSS)应小于发光元件EL的阈值电压Voled。ELVSS为发光元件OLED的第二端的电压，Voled是发光元件EL的发光阈值电压。由此可以确保在数据写入阶段中发光元件EL不会发光。
在发光阶段，发光控制信号EM的低电平为有效电平。在发光控制信号EM的控制下，晶体管T5和晶体管T6导通。驱动晶体管T3在存储电容CST存储的电压信号的驱动下导通。晶体管T5和晶体管T6导通，驱动电流沿着从电源到发光元件EL经由晶体 管T5、驱动晶体管T3和晶体管T6的发光路径，被施加至发光元件EL以使发光元件EL发光。
当然，还可以适用于其他像素电路。例如：晶体管T1～T2是N型晶体管，T3～T7可以为P型晶体管。
例如，对包含图5A所示像素电路的显示面板进行串扰测试。在一个示例中，显示扫描帧频为60Hz，显示面板的分辨率行为1915行，由此栅极驱动信号Gate的扫描周期1H＝8.7μs，有效时间差a+b＝3.4μs，第一时间差a和第二时间差b的默认值为1.7μs。此时，有效时间差与栅极驱动信号的扫描周期比值为39％。
可选的，栅极驱动信号Gate的扫描周期H可通过扫描帧频和显示面板的分辨率行数决定。例如，扫描帧频为60Hz，显示面板的分辨率行为1915行。需要说明的是，显示面板的分辨率行可以包括真实行和虚拟行。例如，真实行为1888行，虚拟行为27行。栅极驱动信号先扫描虚拟行，再扫描真实行。栅极驱动信号Gate的扫描周期1H＝1/F＝1/(60*1915)＝8.7μs，其中：F＝驱动频率*分辨率行数。
当然，一些实施例中适用其他驱动频率或分辨率。可选的，显示面板的还可以是其他分辨率，例如10-30HZ，或者90HZ-120HZ等，也可以其他分辨率，例如：分辨率行为2360行等。
可选的，通过设置栅极驱动信号的时序和/或设置锁存输入时段的持续时间的方法，改变第一时间差a与第二时间差b的值。例如：第一时间差a约为1/F的22～37％，其中：F＝驱动频率*分辨率行数。本公开实施例通过设置栅极驱动信号的时序和/或设置锁存输入时段的持续时间的方法，改变第一时间差a与第二时间差b的比值。为了测试在设置不同比值a/b下的串扰现象，使用根据本公开实施例的所示的驱动方法对包括图5A所示像素电路的显示面板进行串扰测试，测试结果如表1所示。测试时第一时间差与第二时间差的比值a/b范围为0.0625～16。串扰等级越低表示串扰现象越严重。
表1
a 3.2 3.0 2.5 2.0 1.7 1.4 0.9 0.4 0.2
b 0.2 0.4 0.9 1.4 1.7 2.0 2.5 3.0 3.2
串扰等级 4 3 2 4 0 -1 -2 -3 -4
如表1所示，从默认值a＝b＝1.7us开始，随着比值a/b的增加，串扰现象逐渐减轻。 在a/b＝16，a＝3.2us时，串扰等级达到最高。随着比值a/b的减小，串扰等级降低，串扰现象逐渐严重。在a/b＝0.0625，a＝0.2us时，串扰等级达到最高。
在栅极驱动信号的扫描周期H为8.7μs时，为保证缓解串扰现象，第一时间差与第二时间差的比值a/b范围可以为1.27～16，第一时间差的范围可以设置为1.9μs～3.2μs。
例如，在包含图5A所示像素电路的显示面板中显示区域任意选择4个测试点，并对测试点进行串扰测试数值。通过设置栅极驱动信号的时序和设置锁存输入时段的持续时间的方法对每个测试点水平方向和垂直方向的串扰测试数值进行测试。对于同一显示面板，在相同测试条件下，一种比较方案中，4个测试点的串扰测试数值如表2所示，使用根据本公开实施例的技术方案的4个测试点的串扰测试数值如表3所示。上述比较方案中锁存输入时段的持续时间为1.5μs，第一时间差与第二时间差的比值a/b范围为1，例如，第一时间差与第二时间差可以均被设置为默认值1.7μs。根据本公开实施例的技术方案中，锁存输入时段的持续时间为0.4μs，第一时间差与第二时间差的比值a/b范围为1.27～16，第一时间差与锁存输入时段的持续时间的比值范围为475～8，例如，第一时间差为3.2，第二时间差为0.2，第一时间差与锁存输入时段的持续时间的比值为8。
表2
Figure PCTCN2022090471-appb-000001
表3
Figure PCTCN2022090471-appb-000002
如表2所示，利用上述比较方案，测试点2在水平方向H的串扰测试数值为2.35％，说明测试点2在水平方向存在严重的串扰现象。如表3所示，根据本公开实施例的技术方案，4个测试点的水平方向和垂直方向的串扰测试数值均小于2.00％，说明根据本公开实施例的技术方案的所有测试点几乎都未出现串扰现象。其中测试点2在水平方向H的串扰测试数值为0.95％，说明测试点2在水平方向几乎未出现串扰现象。，由此可以验证通过设置栅极驱动信号的时序和设置锁存输入时段的持续时间的方法改善串扰现 象，增大第一时间差与第二时间差的比值a/b后，显示面板的串扰现象得到缓解。
本公开还对多种工作模式下显示面板进行串扰测试和改善。例如工作模式包括高频驱动和低频驱动。例如：在第一驱动模式下，第一时间差为A1，例如A1＝2.6μs-3μs；在第二驱动模式下，第一时间差为A2，A1＝2.0μs-2.4μs，其中第一时间差为A1大于A2。可选的，第一驱动模式为高频驱动(例如：60HZ-240HZ)，第二驱动模式为低频驱动(例如：10HZ-50HZ)；当然，也可以是第二驱动模式为高频驱动(例如：60HZ-240HZ)，第一驱动模式为低频驱动(例如：10HZ-50HZ)。在一个实施例中，为缓解显示面板的串扰现象，高频驱动模式(120HZ)下的第一时间差小于低频驱动模式(30HZ)的第一时间差。
通过本公开实施例，设置栅极驱动信号的时序和/或设置锁存输入时段的持续时间，使第一时间差与第二时间差具有大于1的比值。在第一时间差大于有效时间差的0.5倍的情况下，电源电压ELVDD跳变远离栅极驱动信号的有效电平，电源电压ELVDD跳变所产生的噪声可以在栅极驱动信号有效电平的起始时刻之前消除。在到达栅极驱动信号Gate有效电平的起始时刻时，跳变的电源电压ELVDD已经基本恢复到正常的电源电压ELVDD，避免噪声干扰被写入存储电容CST中，改善串扰现象。
在本公开实施例中，还可以根据栅极驱动信号的时序，设置发光控制信号EM的时序。由于栅极驱动信号的有效电平的起始时刻相对于普通时序中有效电平的起始时刻延后，因此可以设置复位信号Reste1，使得在保持复位信号Reste1的有效电平的持续时间不变的情况下，复位信号Reste1的有效电平的起始时刻随栅极驱动信号的有效电平的起始时刻以相同的幅度延后。由此，可以通过设置发光控制信号的时序，使前一个扫描周期内的发光控制信号的有效电平的持续时间相对于发光控制信号的有效电平的默认持续时间延长。通过延长发光控制信号的有效电平的持续时间，可以使平均电流密度会下降，从而延长发光元件EL的寿命。
图6是根据本公开一个实施例的显示设备的框图。如图6所示，显示设备600可以包括：像素阵列610、时序控制器620、源极驱动器630和栅极驱动器640。
像素阵列610包括多个像素。多个像素位于多个扫描线S、多个数据线DL以及多个光发射控制线EM的交叉区域。
源极驱动器630配置为在时序控制器620的控制下，生成数据信号。栅极驱动器640配置为在时序控制器620的控制下，生成栅极驱动信号，
时序控制器620配置为根据数据信号和栅极驱动信号的有效信号之间的有效时间差， 设置栅极驱动信号的时序，以便通过栅极驱动信号驱动像素阵列。
时序控制器620、源极驱动器630和栅极驱动器640配置为执行前文描述的实施例的驱动方法，以驱动像素阵列610。时序控制器620配置为执行前文描述的操作S210，在此不再赘述。
例如，有效时间差包括数据信号的施加时刻与栅极驱动信号的有效电平起始时刻之间的第一时间差。时序控制器620还配置为设置栅极驱动信号的时序，使得在保持数据信号和栅极驱动信号的有效电平持续时间不变的情况下，数据信号的施加时刻与栅极驱动信号的有效电平起始时刻之间的第一时间差大于有效时间差的0.5倍且小于有效时间差。
例如，有效时间差与栅极驱动信号的扫描周期比值的范围为35～45％。
例如，有效时间差与栅极驱动信号的扫描周期比值为39％。
例如，第一时间差与栅极驱动信号的扫描周期比值的范围为22～37％。
例如，栅极驱动信号的扫描周期为8.7μs，第一时间差的范围为1.9μs～3.2μs。
例如，第一时间差大于电源电压的跳变时间，电源电压的跳变时间与数据信号的参考电压相关。
例如，时序控制器620还配置为根据有效时间差，设置锁存输入时段的持续时间，使得锁存输入时段的结束时刻与下一扫描周期的栅极驱动信号的有效电平起始时刻之间的时间差小于有效时间差。
图7是根据本公开另一个实施例的显示设备的框图。
显示设备700可以包括像素阵列710、时序控制器720、源极驱动器730、栅极驱动器740、电源芯片Power IC 750和伽马校正芯片GAM IC 760。
像素阵列710、时序控制器720、源极驱动器730和栅极驱动器740分别与图6所示的显示设备包括像素阵列610、时序控制器620、源极驱动器630和栅极驱动器640具有类似的功能。为了简明，本公开不再赘述。
电源芯片Power IC 750用于向伽马校正芯片GAM IC760输入数据信号的参考电压AVDD，伽马校正芯片GAM IC 760用于对数据信号的参考电压AVDD进行伽马校正，并将校正后的数据信号的参考电压AVDD输入像素阵列610。电源芯片Power IC 750还配置为向像素阵列610输入初始化信号VINT。
在本公开实施例中，可以通过在如图7所示的N点、P点和Q点上设置外部器件，例如外灌电源、稳压电容或滤波电阻，对显示面板进行水波纹现象测试和串扰测试。
例如，为了测试在不同硬件条件下显示面板的水波纹现象和串扰现象，对包含图5A所示像素电路的显示面板进行水波纹测试和串扰测试。测试的硬件条件包括在如图7所示的输入数据信号的参考电压的路径上的N点、P点和Q点分别设置相关外部器件、修改Power IC750的工作模式以及更换Power IC750为Power IC 2。测试时数据线输入的锁存输入时段的持续时间包括0.4μs和1.5μs。测试结果如表4所示。N表示不存在表格所示出的现象，Y表示存在表格所示出的现象。由于在Q点设置外部器件时，均为改善水波纹现象，因此表4中未示出在Q点分别设置相关外部器件的测试结果。
表4
Figure PCTCN2022090471-appb-000003
如表4所示，在设置锁存输入时段的持续时间为1.5μs时，表4所示出的显示装置的显示面板均出现串扰现象。在设置锁存输入时段的持续时间为0.4μs时，可认为没有出现串扰现象。在设置锁存输入时段的持续时间为0.4μs时，通过在N点或P点设置外灌电源时，可认为没有出现水波纹现象，在N点设置滤波电阻也可认为没有出现水波纹现象，Power IC 750采用常规工作模式而非节能模式可认为没有出现水波纹现象，在将Power IC 750更换为其他电源芯片时也可认为没有出现水波纹现象。
通过本公开实施例，通过在电源芯片Power IC 750与伽马校正芯片GAM IC 760之间设置外灌电源或滤波电阻可以优化数据信号的参考电压，以改善水波纹问题。还可以在电源芯片Power IC 750与像素阵列710之间设置外灌电源或滤波电阻以优化数据信号的参考电压，从而缓解水波纹问题。
附图中的流程图和框图，图示了按照本公开各种实施例的系统、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以 代表一个模块、程序段、或代码的一部分，上述模块、程序段、或代码的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。也应当注意，在有些作为替换的实现中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个接连地表示的方框实际上可以基本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。也要注意的是，框图或流程图中的每个方框、以及框图或流程图中的方框的组合，可以用执行规定的功能或操作的专用的基于硬件的系统来实现，或者可以用专用硬件与计算机指令的组合来实现。
本领域技术人员可以理解，本公开的各个实施例和/或权利要求中记载的特征可以进行多种组合和/或结合，即使这样的组合或结合没有明确记载于本公开中。特别地，在不脱离本公开精神和教导的情况下，本公开的各个实施例和/或权利要求中记载的特征可以进行多种组合和/或结合。所有这些组合和/或结合均落入本公开的范围。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。本公开的范围由所附权利要求及其等同物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (20)

  1. 一种驱动方法，用于驱动像素阵列，包括：
    根据数据信号和栅极驱动信号的有效信号之间的有效时间差，设置所述栅极驱动信号的时序；以及
    通过所述栅极驱动信号驱动所述像素阵列。
  2. 根据权利要求1所述的方法，其中，所述有效时间差包括所述数据信号的施加时刻与所述栅极驱动信号的有效电平起始时刻之间的第一时间差；所述根据所述有效时间差，设置所述栅极驱动信号的时序包括：
    设置所述栅极驱动信号的时序，使得在保持所述数据信号和所述栅极驱动信号的有效电平持续时间不变的情况下，所述第一时间差大于所述有效时间差的0.5倍且小于所述有效时间差。
  3. 根据权利要求2所述的方法，其中，所述有效时间差与所述栅极驱动信号的扫描周期比值的范围为35～45％。
  4. 根据权利要求3所述的方法，其中，所述有效时间差与所述栅极驱动信号的扫描周期比值为39％。
  5. 根据权利要求2所述的方法，其中，所述第一时间差与所述栅极驱动信号的扫描周期比值的范围为22～37％。
  6. 根据权利要求3至5中任一项所述的方法，其中，所述栅极驱动信号的扫描周期为8.7μs，所述第一时间差的范围为1.9μs～3.2μs。
  7. 根据权利要求2所述的方法，其中，所述第一时间差大于电源电压的跳变时间。
  8. 根据权利要求2所述的方法，还包括：
    根据所述有效时间差，设置锁存输入时段的持续时间，使得所述锁存输入时段的结束时刻与下一扫描周期的栅极驱动信号的有效电平起始时刻之间的时间差大于有效 时间差的0.5倍且小于所述有效时间差。
  9. 根据权利要求2所述的方法，还包括：第一驱动模式，所述第一时间差为A1；第二驱动模式，所述第一时间差为A2，所述A1大于A2。
  10. 一种显示设备，包括：
    像素阵列；
    时序控制器；
    源极驱动器，配置为在所述时序控制器的控制下，生成数据信号；以及
    栅极驱动器，配置为在所述时序控制器的控制下，生成栅极驱动信号，
    其中，所述时序控制器配置为：
    根据所述数据信号和所述栅极驱动信号的有效信号之间的有效时间差，设置所述栅极驱动信号的时序，以便通过所述栅极驱动信号驱动所述像素阵列。
  11. 根据权利要求10所述的显示设备，其中，所述有效时间差包括所述数据信号的施加时刻与所述栅极驱动信号的有效电平起始时刻之间的第一时间差；
    所述时序控制器还配置为：
    设置所述栅极驱动信号的时序，使得在保持所述数据信号和所述栅极驱动信号的有效电平持续时间不变的情况下，所述数据信号的施加时刻与所述栅极驱动信号的有效电平起始时刻之间的第一时间差大于所述有效时间差的0.5倍且小于所述有效时间差。
  12. 根据权利要求11所述的显示设备，其中，所述有效时间差与所述栅极驱动信号的扫描周期比值的范围为35～45％。
  13. 根据权利要求11所述的显示设备，其中，所述有效时间差与所述栅极驱动信号的扫描周期比值为39％。
  14. 根据权利要求11所述的显示设备，其中，所述第一时间差与所述栅极驱动信号的扫描周期比值的范围为22～37％。
  15. 根据权利要求12至14中任一项所述的显示设备，其中，所述栅极驱动信号的扫描周期为8.7μs，所述第一时间差的范围为1.9μs～3.2μs。
  16. 根据权利要求11所述的显示设备，其中，所述第一时间差大于电源电压的跳变时间。
  17. 根据权利要求10所述的显示设备，其中，所述时序控制器还配置为根据所述有效时间差，设置锁存输入时段的持续时间，使得锁存输入时段的结束时刻与下一扫描周期的所述栅极驱动信号的有效电平起始时刻之间的时间差大于有效时间差的0.5倍且小于所述有效时间差。
  18. 根据权利要求10所述的显示设备，还包括：
    外灌电源，设置在所述源极驱动器的电压源与像素阵列之间。
  19. 根据权利要求10所述的显示设备，还包括：
    电阻，设置在所述源极驱动器的电压源与像素阵列之间。
  20. 根据权利要求11所述的显示设备，其中，所述时序控制器还配置为设置：第一驱动模式，所述第一时间差为A1；第二驱动模式，所述第一时间差为A2，所述A1大于A2。
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