WO2023202724A1

WO2023202724A1 - Chip packaging structure and method

Info

Publication number: WO2023202724A1
Application number: PCT/CN2023/097453
Authority: WO
Inventors: 倪建兴; 王华磊
Original assignee: 锐石创芯(重庆)科技有限公司
Priority date: 2022-04-18
Filing date: 2023-05-31
Publication date: 2023-10-26
Also published as: CN115000024B; CN116845032A; CN115000024A

Abstract

The present application relates to a chip packaging structure. A protective layer is introduced, and the protective layer comprises a first portion, which is arranged on a chip pad at a first surface of a substrate; and a second portion, which is arranged outside the chip pad. An interconnection bump, which is connected to the chip pad, on a bottom surface of a chip to be packaged is at least partially surrounded by the first portion of the protective layer. The bottom surface of said chip comprises a first region having a longitudinal projection overlapping with a longitudinal projection of the second portion of the protective layer. The bottom surface of said chip is opposite the first surface, and a cavity is formed between the bottom surface of said chip and the substrate.

Description

A chip packaging structure and method

This application claims priority to the Chinese patent application submitted to the China Patent Office on April 18, 2022, with the application number CN202210404319.5 and the application title "A chip packaging structure and method", the entire content of which is incorporated herein by reference. Applying.

Technical field

The present application belongs to the field of packaging technology, and in particular relates to a chip packaging structure and method.

Background technique

With the rapid development of the new generation of information technology, higher and higher requirements have been placed on various technologies in the semiconductor field. As the core support of many technologies, chips also play an increasingly important role.

Some chips with special functions require a cavity structure between them and the substrate during the packaging process to meet their functions, performance or other special requirements. For example, surface acoustic wave (Surface Acoustic Wave, SAW) filter chip and bulk acoustic wave (Bulk Acoustic Wave, BAW) filter chip, etc. Surface acoustic wave filter chips and bulk acoustic wave filter chips play a vital role in the radio frequency field. For users, the requirements for integration and miniaturization are constantly testing the design and layout of products, such as mobile terminals. Especially in the 5G scenario, there is an increasing demand for filter chips in the radio frequency front-end of mobile terminals. Therefore, for the increasing number of chips required, how to ensure the reliability of the chips in packaging design is an urgent problem that needs to be solved.

Application content

This application solves the technical problem of low chip reliability in the prior art and provides a chip packaging structure and method.

In a first aspect, embodiments of the present application provide a chip packaging structure, including:

A substrate with a chip pad provided on the first surface;

A protective layer including a first portion disposed on the chip pad on the first surface, and a second portion disposed outside the chip pad;

A packaged chip is provided on the first surface of the substrate, and the bottom surface of the packaged chip is provided with interconnection bumps, The interconnection bumps are connected to the chip pads, the interconnection bumps are at least partially surrounded by the first portion of the protective layer, and the bottom surface of the packaged chip is opposite to the first surface;

The bottom surface of the packaged chip further includes a first area that overlaps with the second part of the protective layer in a longitudinal projection, and a cavity is formed between the bottom surface of the packaged chip and the substrate.

In a second aspect, an embodiment of the present application provides a chip packaging structure, including:

A substrate including a chip pad disposed on a first surface;

A support layer formed on the first surface of the substrate;

A protective layer, including a first part provided on the chip pad, and a second part provided on the support layer;

A packaged chip is disposed on the first surface of the substrate, and the bottom surface of the packaged chip is provided with bumps, the bumps are connected to the chip pads, and the bumps are at least partially protected by the protection surrounded by layers;

The bottom surface of the packaged chip further includes a first area that overlaps with the second portion of the protective layer in a longitudinal projection, and a second area that overlaps with the support layer in a longitudinal projection, the The bottom surface of the packaged chip is opposite to the first surface, and a cavity is formed between the bottom surface of the packaged chip and the substrate.

In a third aspect, an embodiment of the present application provides a chip packaging method, including:

forming a protective layer on the first surface of the substrate, the protective layer comprising a first portion disposed on the chip pad on the first surface, and a second portion disposed outside the chip pad;

A package chip is provided on the first surface of the substrate, a bottom surface of the package chip is provided with bumps, the bumps are connected to the chip pads, and the bumps are at least partially surrounded by the protective layer; The bottom surface of the packaged chip includes a first area that overlaps with the second portion of the protective layer in a longitudinal projection, the bottom surface of the packaged chip is opposite to the first surface, and the bottom surface of the packaged chip A cavity is formed between the substrate and the substrate.

In a fourth aspect, an embodiment of the present application provides a chip packaging structure, including:

A substrate with a chip pad provided on the first surface;

A packaged chip is provided on the first surface of the substrate, and the bottom surface of the packaged chip is provided with interconnection bumps, and the interconnection bumps are connected to the chip pads. The bottom surface of the packaged chip Opposite the first surface;

A support layer is formed on the first surface of the substrate, the bottom surface of the package chip includes a second area that overlaps with the support layer in a longitudinal projection, the bottom surface of the package chip, the support layer and forming a cavity between the first surfaces of the substrate;

A protective layer surrounding at least part of the interconnection bumps and/or the chip pads.

In a fifth aspect, an embodiment of the present application provides a chip packaging structure, including:

A substrate with a chip pad provided on the first surface;

A packaged chip is provided on the first surface of the substrate, and the bottom surface of the packaged chip is provided with interconnection bumps, and the interconnection bumps are connected to the chip pads. The bottom surface of the packaged chip Opposite to the first surface, a cavity is formed between the bottom surface of the package chip and the first surface of the substrate;

The chip packaging structure and method provided in the embodiments of the present application include: a substrate with a chip pad provided on the first surface; a protective layer including a first portion provided on the chip pad on the first surface; a second part outside the chip pad; a packaged chip, disposed on the first surface of the substrate, and the bottom surface of the packaged chip is provided with interconnection bumps, the interconnection bumps are connected to the The chip pad connection, the interconnection bump is at least partially surrounded by the first part of the protective layer, the bottom surface of the packaged chip is opposite to the first surface; the bottom surface of the packaged chip also includes a protective layer The first area where the second portion of the layer overlaps in longitudinal projection forms a cavity between the bottom surface of the packaged chip and the substrate. By introducing a protective layer, the protective layer includes a first portion disposed on the chip pad on the first surface, and a second portion disposed outside the chip pad. The first part can act as a flux and reduce the risk of solder joint detachment that may occur after high-temperature remelting of the chip connection points. The arrangement of the second part further ensures the formation of a cavity between the bottom surface of the chip and the substrate, which can effectively prevent other materials from entering the cavity, ensuring the overall performance of the chip and improving the reliability of the chip.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features and advantages of the application will be apparent from the description, drawings, and claims.

Description of the drawings

In order to explain the technical solutions of the embodiments of the present application more clearly, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. , for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without exerting creative labor.

Figure 1 is a schematic structural diagram of a chip packaging structure in an embodiment of the present application;

Figure 2 is a schematic structural diagram of a chip packaging structure in another embodiment of the present application;

Figure 3 is a schematic structural diagram of a chip packaging structure in another embodiment of the present application;

Figure 4 is a schematic structural diagram of a chip packaging structure in another embodiment of the present application;

Figure 5 is a schematic structural diagram of a chip packaging structure in another embodiment of the present application;

Figure 6 is a schematic structural diagram of a chip packaging structure in another embodiment of the present application;

FIG. 7 is a schematic structural diagram of a chip packaging structure in another embodiment of the present application.

The reference symbols in this manual are as follows:
10. Substrate; 11. First surface; 12. Chip pad;
20. Protective layer; 21. First part; 22. Second part; 221. First block; 222. Second block;
30. Package the chip; 31. Connect the bumps;
40. Support layer.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

It will be understood that the application may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, like reference numerals refer to the same elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to," "connected to," "connected to" another element or layer, it will be understood that It may be directly on, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the application.

Spatial relational terms such as "under", "under", "under", "under", "on", "above", etc. may be used here for convenience of description This describes the relationship of one element or feature to other elements or features illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "under" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" may include both upper and lower orientations. Device may be otherwise oriented (rotated 90 degrees or other orientation) and the spatial descriptors used herein are interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the terms "consisting of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts but do not exclude one or more others The presence or addition of features, integers, steps, operations, elements, parts, and/or groups. When used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to fully understand the present application, detailed structures and steps will be provided in the following description to explain the technical solutions proposed in the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementations.

An embodiment of the present application provides a chip packaging structure, including: a substrate with a chip pad provided on a first surface; a protective layer including a first portion provided on the chip pad on the first surface; and a protective layer provided on the chip. The second part other than the pad; the packaged chip is disposed on the first surface of the substrate, and the bottom surface of the packaged chip is provided with interconnection bumps. The interconnection bumps are connected to the chip pads, and at least part of the interconnection bumps Surrounded by a protective layer; the bottom surface of the packaged chip also includes a first area that overlaps with the second part of the protective layer in a longitudinal projection, the bottom surface of the packaged chip is opposite to the first surface, and there is a gap between the bottom surface of the packaged chip and the substrate Create a cavity.

As shown in FIG. 1 , the substrate 10 in the chip packaging structure includes a first surface 11 , where the substrate 10 can be a resin substrate, a ceramic substrate, a glass substrate, or other types of substrates. In a specific embodiment, the substrate 10 is a resin substrate. The protective layer 20 includes a first portion 21 disposed on the chip pad 12 of the first surface 11 and a second portion 22 disposed outside the chip pad.

The first portion 21 of the protective layer 20 is disposed on the chip pad 12 of the first surface 11 of the substrate 10 . Wherein, the chip pad 12 provided on the first surface may be provided on the first surface 11 of the substrate (that is, protruding from the first surface 11 ), or the chip pad 12 may be embedded in the first surface ( As shown in FIG. 1 ), alternatively, the chip pad 12 can also be embedded in the first surface and protrude from the first surface 11 , or other feasible chip pad arrangement methods are not specifically limited here. In this embodiment, the chip bonding pad is disposed on the first surface 11 as an example. As shown in FIG. 1 , the first surface 11 of the substrate 10 may include multiple chip bonding pads 12 , and the first part 21 is disposed on at least one chip. It suffices that the first part 21 must be disposed on all the chip bonding pads 12 on the substrate. The second part 22 is disposed outside the chip pad, where the second part 22 can be directly disposed on the first surface 11 of the substrate 10 or indirectly disposed on the first surface 11 of the substrate 10 ( That is, there are other layers between the second part 22 and the substrate 10, such as a support layer). In one embodiment, as shown in FIG. 1 , the second portion 22 is directly disposed on the first surface of the substrate 10 Above 11.

In one embodiment, the protective layer 20 may be made of insulating material. In one embodiment, the protective layer may be made of low-volatility materials. In one embodiment, the protective layer 20 may be made of low-volatile resin material. In one embodiment, the protective layer 20 may be made of low-volatility insulating resin material. In one embodiment, the protective layer 20 can also be made of resin glue, ultraviolet rays (Ultraviolet Rays, UV) glue or other commonly used glue materials. The use of low-volatile materials for the protective layer 20 means that the protective layer 20 includes low-volatile substances, or the overall volatility of the protective layer 20 is low, or the protective layer 20 does not contain volatile materials. In one embodiment, low volatility can be understood as meaning that the entire protective layer 20 will not volatilize during the packaging process (for example, reflow soldering process), or there will be a smaller proportion of volatilization but will not cause contamination to the cavity, or Causes minor pollution and will not affect chip performance or cause chip failure.

In this embodiment, because some chips need to form a closed cavity mechanism with the surface of the substrate to ensure the realization of chip functions, the protective layer 20 is made of low-volatile materials, which can reduce the risk of the protective layer 20 during packaging or other processes. The contamination of the cavity caused by volatilization better ensures the realization of chip functions and improves the reliability of the overall chip packaging structure.

In one embodiment, the protective layer is a low volatility insulating material. By selecting low-volatility insulating materials, it can be ensured that the protective layer 20 can better protect the connection between the interconnection bumps 31 and the chip pads 12 and will not cause excessive volatilization due to packaging or other environmental factors. It can be understood that the above-mentioned low volatility means that the protective layer 20 still surrounds at least part of the interconnection bumps 31 after the chip packaging is completed. Alternatively, the low volatility means that the protective layer 20 still surrounds at least part of the interconnection bumps 31 in a normal use environment after the chip packaging is completed.

In one embodiment, the protective layer 20 is a non-volatile resin material. For example, volatile-free epoxy resin or other resin-based materials that do not contain volatile matter, etc. In a specific embodiment, the protective layer is a resin material without volatile organic compounds.

The chip packaging structure also includes a packaging chip 30. As shown in FIG. 1, the packaging chip 30 is disposed on the first surface 11 of the substrate 10. The bottom surface of the packaging chip 30 is provided with interconnection bumps 31. The interconnection bumps 31 is connected to the chip pad 12 , and the interconnection bump 31 is at least partially surrounded by the protective layer 20 . The bottom surface of the package chip 30 is opposite to the first surface 11 .

The bottom surface of the package chip 30 includes a plurality of interconnection bumps 31 , wherein each interconnection bump 31 is connected to a chip pad 12 on the first surface 11 of the substrate 10 . Wherein, the interconnection bump 31 is at least partially surrounded by the protective layer, that is, by the first portion 21 of the protective layer. It can be understood that as long as at least one interconnection bump 31 is at least partially surrounded by the protective layer 21 , it should not be limited to the fact that all interconnection bumps 31 need to be at least partially surrounded by the protective layer 21 .

The interconnection bump 31 is at least partially surrounded by the first portion 21 of the protection layer 20 . It can be understood that the first portion 21 of the protection layer 20 only needs to partially surround the interconnection bump 31 . In a specific embodiment, at least the lower half of the interconnect bump 31 is surrounded by the first portion 21 of the protective layer 20 . In one embodiment, the first portion 21 of the protective layer 20 covers at least the mutual The connection portion in the interconnection bump 31 is a portion of the interconnection bump 31 that is connected to the connected chip pad 12 to prevent the connection portion from being exposed.

The bottom surface of the packaged chip 30 also includes a first area that overlaps the second portion 22 of the protective layer 20 in longitudinal projection. It can be understood that the longitudinal direction in the embodiment of the present application is a relative concept. It can be understood that the longitudinal direction does not mean that it is required to be absolutely vertical or overhanging, and a slightly inclined direction is also allowed. Taking Figure 1 as an example, the longitudinal direction here refers to the thickness direction in the chip packaging structure (such as the thickness direction of the substrate 10); in a specific embodiment, longitudinal projection means projecting the object onto a plane perpendicular to the longitudinal direction, or longitudinal projection. Projection is the projection of an object onto a plane perpendicular to the direction perpendicular to the horizontal plane.

As shown in FIG. 1 , the package chip 30 is disposed on the first surface 11 of the substrate 10 , and the outer edge of the bottom surface of the package chip 30 overlaps the second portion 22 of the protective layer 20 in longitudinal projection. Taking the bottom surface of the packaged chip 30 in Figure 1 as a rectangular structure as an example, the bottom surface of the packaged chip 30 includes four sides. In Figure 1, one side and the second part 22 of the bottom surface of the packaged chip are projected longitudinally. Overlap. For the settings on the other three sides, any existing conventional setting method can be used, as long as it is reasonable. In a specific embodiment, the remaining three sides of the bottom surface of the package chip 30 may overlap with any one of a support frame, a support layer, the second portion 22 of the protective layer 20 , etc. in a longitudinal projection. It can be understood that the above-mentioned first region may be formed on one side of the package chip 30 , or may be formed on a part of one side, or may be formed on multiple sides of the package chip 30 . In one embodiment, the first region is formed on the first side of the package chip 30 .

Specifically, the outer periphery of the bottom surface of the package chip 30 includes a first area that overlaps with the second part of the protective layer 20 in a longitudinal projection, and other areas except the first area, and for the arrangement of other areas, Any existing conventional setting method can be used, as long as it is reasonable. In a specific embodiment, in the periphery of the bottom surface of the package chip 30, other areas except the first area may be vertically aligned with any one of a support frame, a support layer, the second part 22 of the protective layer 20, etc. Overlay on projection.

A cavity is formed between the bottom surface of the package chip 30 and the substrate 10 . Wherein, the outer periphery of the bottom surface of the package chip 30 includes a first area that overlaps with the second part 22 of the protective layer 20 in a longitudinal projection, and other areas except the first area, and for the arrangement of other areas , any existing conventional arrangement method can be used as long as it is reasonable, so that a cavity is formed between the bottom surface of the package chip 30 and the substrate 10 . In a specific embodiment, the package chip 30 can be a SAW filter chip, a BAW filter chip or other chips that require a cavity.

In this embodiment, the package chip 30 is disposed on the first surface of the substrate 10 , and the bottom surface further includes a first area that overlaps with the second portion 22 of the protective layer 20 in a longitudinal projection. Specifically, the first region and the second part 22 of the protective layer 20 may be attached to each other, or there may be a slight distance or gap between the first region and the second part 22 in the longitudinal direction. This small distance or gap can prevent subsequent plastic packaging materials or other materials from flowing into the above-mentioned cavity, or can only allow a small amount of plastic packaging material or very few other materials to flow into the above-mentioned cavity, but does not affect the performance of the packaged chip 30 implementation and its reliability. In a specific embodiment, the distance between the first area and the second part 22 of the protective layer 20 is less than 20um (micron), 15um or 5um, etc. In one embodiment, the distance between the first area and the second portion 22 of the protective layer 20 is in the interval [0.1um, 5um]. In one embodiment, the first area of the bottom surface of the package chip 30 is attached to the second portion 22 of the protective layer 20 . It can be understood that the first area of the bottom surface is attached to the second part 22 of the protective layer 20 to better prevent other materials from flowing into the cavity and provide better protection.

In this embodiment, a protective layer 20 is introduced, and the protective layer 20 includes a first portion 21 disposed on the chip pad 12 on the first surface 11 , and a second portion 22 disposed outside the chip pad 12 . The first part 21 can reduce the risk of solder joint detachment that may occur after high-temperature remelting of the chip connection point. The setting of the second part 22 further ensures the formation of a cavity between the bottom surface of the packaged chip 30 and the substrate 10, which can effectively prevent other materials from entering the cavity, ensures the realization of the overall performance of the packaged chip 30, and improves the efficiency of the packaged chip. 30% reliability.

In one embodiment, the chip packaging structure further includes a sealing layer, and the sealing layer covers at least the packaging chip 30 and the second part 22 of the protective layer. The sealing layer can be made of insulating resin material or other conventional plastic sealing materials. In some embodiments, the sealing layer is a resin material containing particulate matter. The particles may be silicon dioxide (SiO ₂ ) particles or aluminum trioxide (Al ₂ O ₃ ) particles, which are not limited in the embodiments of this application. It is understood that other materials that can achieve the sealing function can also be used, which will not be described again here.

In one embodiment, the longitudinal distance between the first region of the packaged chip 30 and the second portion 22 of the protective layer 20 is configured to be less than a first threshold to block the sealing layer from entering the cavity. In a specific embodiment, the first threshold is 5um, 10um or 15um, etc. In one embodiment, the first threshold is in the interval [0.1um, 5um].

In one embodiment, the first threshold is less than or equal to a maximum particle size of the particles of the sealing layer.

In one embodiment, the chip packaging structure further includes a support layer formed on the first surface of the substrate 10 , and the bottom surface of the package chip 30 further includes a second area that overlaps with the support layer in longitudinal projection.

As shown in FIG. 2 , the support layer 40 is formed on the first surface of the substrate 10 , and the bottom surface of the package chip 30 further includes a second area that overlaps with the support layer 40 in a longitudinal projection. Taking the bottom surface of the packaged chip 30 in Figure 2 as a rectangular structure as an example, the bottom surface of the packaged chip 30 includes four sides. In Figure 2, the left side of the bottom surface of the packaged chip 30 and the support layer 40 are projected longitudinally. The upper part overlaps. For the settings on the other three sides, any existing conventional method can be used, as long as it is reasonable. In a specific embodiment, the remaining three sides of the bottom surface of the package chip 30 may overlap with any one of a support frame, a support layer, the second portion 22 of the protective layer 20 , etc. in a longitudinal projection. It can be understood that the above-mentioned second region may be formed on one side of the package chip 30 , or may be formed on a part of one side, or may be formed on multiple sides of the package chip 30 . In one embodiment, the support layer 40 may also be a solder resist layer, and the support layer may be formed of a solder resist material. In this embodiment, the support layer 40 is a solder resist layer formed on the first surface 11 of the substrate 10 . Through the solder mask on the substrate To act as a support layer, it reduces the formation of additional layers and reduces the consumption of additional materials and processes.

Specifically, the outer periphery of the bottom surface of the package chip 30 includes a second area that overlaps with the support layer 40 in a longitudinal projection, a first area that overlaps with the second portion 22 of the protective layer 20 in a longitudinal projection, and other than For other areas other than the first area and the second area, for the settings of other areas, any existing conventional method can be used, as long as it is reasonable. In a specific embodiment, in the outer periphery of the bottom surface of the package chip 30, other areas except the first area and the second area may be any other areas related to a support frame, a support layer, the second part 22 of the protective layer 20, etc. One overlaps in longitudinal projection.

In this embodiment, the packaged chip 30 is disposed on the first surface 11 of the substrate 10 , and the bottom surface of the packaged chip 30 further includes a second area that overlaps with the supporting layer 40 in longitudinal projection. Specifically, the second region and the support layer 40 may be attached to each other, or there may be a slight distance or gap between the second region and the support layer 40 in the longitudinal direction. This small distance or gap can prevent subsequent plastic packaging materials or other materials from flowing into the above-mentioned cavity, or can only allow a small amount of plastic packaging material or other materials to flow into the above-mentioned cavity, but does not affect the realization of the performance of the packaged chip 30 and its reliability. In one embodiment, the distance between the second region and the support layer 40 is less than 5um, 10um, or 15um, etc. In one embodiment, the distance between the second region and the support layer 40 is in the interval [0.1um, 5um].

In one embodiment, the longitudinal distance between the second region and the support layer is configured to be less than a second threshold to block the sealing layer from entering the cavity.

In a specific embodiment, the second threshold may be 5um, 10um or 15um, etc. In one embodiment, the second threshold is in the interval [0.1um, 5um].

In one embodiment, the second threshold is less than or equal to the maximum particle size of the particles of the sealing layer.

In one embodiment, at least one side of the packaged chip 30 includes a third region that overlaps in lateral projection with the second portion 22 of the support layer and/or protective layer 20 .

In one embodiment, the horizontal direction is a relative concept. It can be understood that the horizontal direction does not mean that it requires absolute horizontality. It can have a certain angle with the horizontal plane, and the angle is not equal to 90 degrees. Taking Figure 5 as an example, the vertical direction Refers to the horizontal direction in the chip packaging structure; in a specific embodiment, lateral projection is to project the object onto a plane perpendicular to the lateral or horizontal direction.

In one embodiment, at least one side of the packaged chip 30 includes a third area that overlaps the support layer 40 in a lateral projection. Specifically, the third region and the support layer 40 may be attached to each other, or there may be a slight distance or gap between the third region and the support layer 40 in the lateral direction. In this embodiment, as shown in FIG. 5 , the support layer 40 includes a first support layer and a second support layer. Wherein, the first support layer is disposed on the first surface 11 of the substrate 10, and the second support layer is disposed on the first support layer. That is, the second support layer is located on the surface of the first support layer away from the substrate 10 , and the second support layer and the first support layer are arranged in a stepped manner at least on one side. In this way, the bottom surface of the package chip 30 includes a portion that overlaps with the first support layer in a longitudinal projection. The second region, at least one side of the packaged chip, includes a third region that overlaps in lateral projection with the second support layer.

In one embodiment, at least one side of the packaged chip 30 includes a third region that overlaps in lateral projection with the second portion 22 of the protective layer 20 . Specifically, the third region and the second part of the protective layer 20 may be attached to each other, or there may be a slight distance or gap in the lateral direction between the third region and the second part 22 of the protective layer 20 . As shown in FIG. 5 , the second portion 22 of the protective layer 20 may be disposed on the first support layer and the second support layer.

The above-mentioned tiny distance or gap can prevent subsequent plastic packaging materials or other materials from flowing into the cavity, or can only allow a small amount of plastic packaging materials or other materials to flow into the cavity, but does not affect the realization of the performance of the packaged chip and its other functions. reliability.

In one embodiment, a lateral upward distance between the third region and the protective layer is configured to be less than a third threshold to block the sealing layer from entering the cavity.

In a specific embodiment, the third threshold may be 5um, 10um or 15um, etc. In one embodiment, the second threshold is in the interval [0.1um, 5um].

In one embodiment, the third threshold is less than or equal to the maximum particle size of the particles of the sealing layer.

In one embodiment, the first area and the second area at least partially overlap. As shown in FIG. 3 , in this embodiment, the bottom surface of the packaged chip has a portion that overlaps with the second portion 22 of the protective layer and the support layer in longitudinal projection. In this embodiment, the second portion 22 of the protective layer 20 is at least partially disposed on the support layer 40 so as to overlap the support layer 40 in a longitudinal projection. Alternatively, the support layer 40 is formed at least partially over the second portion 22 of the protective layer 20 so as to overlap the second portion 22 of the protective layer 20 in a longitudinal projection. In one embodiment, the second portion 22 of the protective layer 20 is at least partially formed on the support layer 40 .

In one embodiment, the support layer 40 is formed on the first surface 11 of the substrate 10 , and the second part 22 of the protective layer 20 includes at least a first block 221 formed on the support layer 40 , and also includes a first block 221 formed directly on the first surface 11 of the substrate 10 . A second piece 222 on surface 11 . As shown in FIG. 3 , the bottom surface of the package chip 30 includes a first area that overlaps with the second portion 22 of the protective layer 20 in a longitudinal projection. At this time, the first area is a set of two discrete areas, including and the first area. The portion that overlaps the longitudinal projection of one piece 221 and the portion that overlaps the second piece 222 longitudinally. The bottom surface of the package chip 30 also includes a second area that overlaps the support layer 40 in longitudinal projection. In this embodiment, the first region and the second region partially overlap, that is, the portion of the first region that overlaps with the first block 221 in longitudinal projection partially overlaps with the second region.

In one embodiment, the support layer 40 is formed on the first surface 11 of the substrate 10 and the second portion 22 of the protective layer 20 is formed over the support layer 40 . As shown in FIG. 4 , the support layer 40 is formed on the first surface 11 of the substrate 10 , and the second part 22 of the protective layer 20 is formed on the support layer 40 . The bottom surface of the package chip 30 is in contact with the second part of the protective layer 20 . The portion 22 and the support layer 40 have overlapping portions in longitudinal projection. The bottom surface of the package chip 30 includes a third layer with the protective layer 20 The first area where the two parts 22 overlap in the longitudinal projection. The bottom surface of the package chip 30 also includes a second area that overlaps with the support layer 40 in the longitudinal projection. In this embodiment, the first area and the second area At least partially overlap.

In one embodiment, the first area and the second area do not overlap in longitudinal projection. As shown in FIG. 2 , the support layer 40 is formed on the first surface 11 of the substrate 10 , the second part 22 of the protective layer is also formed on the first surface 11 of the substrate 10 , and the support layer 40 and the second part of the protective layer 22 are respectively formed in different areas on the first surface 11 .

In one embodiment, the first area is on a first side of the packaged chip, and the second area is on at least one side of the packaged chip other than the first side. As shown in FIG. 2 , the outer edge of the bottom surface of the package chip 30 overlaps with the support layer 40 in a longitudinal projection, and the outer edge of the bottom surface of the package chip 30 overlaps with the second portion 22 of the protective layer in a longitudinal projection. . Taking the bottom surface of the packaged chip 30 in Figure 2 as a rectangular structure as an example, the bottom surface of the packaged chip 30 includes four sides. In Figure 2, one side of the bottom surface of the packaged chip and the support layer 40 are in longitudinal projection. overlap, while the other side and the second portion 22 of the protective layer overlap in longitudinal projection. For the settings on the other two sides, any existing conventional method can be used, as long as it is reasonable. In a specific embodiment, the remaining two sides of the bottom surface of the package chip 30 may overlap with at least one of the support layer 40 or the second portion 22 of the protective layer 20 in a longitudinal projection. It can be understood that the above-mentioned first region may be formed on one side of the package chip 30 , or may be formed on a part of one side, or may be formed on multiple sides of the package chip 30 . Similarly, the above-mentioned second area may be formed on one side of the package chip 30 , or may be formed on a part of one side, or may be formed on multiple sides of the package chip 30 . In one embodiment, the second region is formed on a first side of the packaged chip, and the first region is formed on at least one other side of the packaged chip except the first side. Further, the second area is formed on the first side of the packaged chip, and the first area is formed on all other sides of the packaged chip except the first side.

In one embodiment, the first portion disposed on the chip pad on the first surface and the second portion disposed outside the chip pad are formed in one process.

In this embodiment, the first part and the second part of the protective layer are formed in one process, which saves process steps and reduces chip packaging costs. In a specific embodiment, the first part and the second part of the protective layer are formed by a screen printing process.

An embodiment of the present application also provides a chip packaging structure, including:

A substrate including a chip pad disposed on a first surface;

a support layer formed on the first surface of the substrate;

The protective layer includes a first part provided on the chip pad and a second part provided on the support layer;

The packaged chip is disposed on the first surface of the substrate, and the bottom surface of the packaged chip is provided with interconnection bumps, the interconnection bumps are connected to the chip pads, and the interconnection bumps are at least partially surrounded by a protective layer;

The bottom surface of the packaged chip further includes a first area that overlaps in longitudinal projection with the second portion disposed on the support layer, and a second area that overlaps with the support layer in longitudinal projection, the bottom surface of the packaged chip is opposite to the first surface, and a cavity is formed between the bottom surface of the packaged chip and the substrate.

As shown in FIG. 4 , the substrate 10 in the chip packaging structure includes a first surface 11 and a chip pad 12 disposed on the first surface. The substrate 10 may be a resin substrate, a ceramic substrate, a glass substrate or other types of substrates. In a specific embodiment, the substrate 10 is a resin substrate. The support layer 40 is formed on the first surface 11 of the substrate 10. The support layer 40 can be made of resin or other commonly used support layer materials.

In one embodiment, the support layer 40 is provided with a first opening. In a specific embodiment, the first opening may extend longitudinally to the first surface 11 of the substrate 10, as shown in FIG. 2 . It is understood that the first opening may not extend to the first surface 11 of the substrate 10 , that is, in this case, the first opening is equivalent to a groove structure provided in the support layer 40 . Wherein, if the first opening does not extend to the first surface 11 of the substrate 10 , the first opening also includes at least a second opening, and the second opening extends to the first surface 11 of the substrate 10 to expose the first surface of the substrate 10 11 chip pads 12.

The first portion 21 of the protective layer 20 is disposed on the chip pad 12 on the first surface 11 of the substrate 10 . It can be understood that the first surface 11 of the substrate 10 may include a plurality of bonding pads 12, and the first part 21 is provided on at least one chip bonding pad 12, and it should not be limited to that the first part 21 must be provided over all chip pads 12 on the substrate 10 . The second portion 22 is disposed on the support layer 40 . In a specific embodiment, the first portion 21 at least surrounds the connection portion of the interconnection bump 31 and the chip pad 12 .

The bottom surface of the package chip 30 includes a plurality of interconnection bumps 31 , wherein each interconnection bump 31 is connected to a chip pad 12 on the first surface 11 of the substrate 10 . Wherein, the interconnection bumps 31 are at least partially surrounded by the protective layer 10 , that is, surrounded by the first portion 21 of the protective layer 10 . It can be understood that as long as at least one interconnection bump 31 is at least partially surrounded by the protection layer 20 , it should not be limited to all interconnection bumps 31 needing to be at least partially surrounded by the protection layer 20 .

The interconnection bump 31 is at least partially surrounded by the first portion 21 of the protection layer 20 . It can be understood that the first portion 21 of the protection layer 20 only needs to partially surround the interconnection bump 31 . In a specific embodiment, at least the lower half of the interconnect bump 31 is surrounded by the first portion 21 of the protective layer 20 . In one embodiment, the first portion 21 of the protective layer 20 at least covers the connection portion of the interconnection bump 31 that interconnects with the chip pad 12 to prevent the connection portion from being exposed.

The bottom surface of the packaged chip 30 also includes a first area that overlaps the second portion 22 of the protective layer 20 in longitudinal projection. It can be understood that the longitudinal direction in the embodiment of the present application is a relative concept. It can be understood that the longitudinal direction does not mean that it is required to be absolutely vertical or overhanging, and a slightly inclined direction is also allowed. Take Figure 2 as an example. The vertical direction here refers to the chip packaging structure. thickness direction (such as the thickness direction of the substrate).

Further, the bottom surface of the package chip 30 also includes a second area that overlaps with the support layer 40 in longitudinal projection.

In one embodiment, the above-mentioned first area and the second area are both arranged in the peripheral area of the bottom surface of the package chip 30 . In a specific embodiment, the first region and the second region at least partially overlap. In a specific embodiment, the first area and the second area do not overlap.

In one embodiment, the second part 22 of the protective layer 20 at least includes a first block formed on the support layer 40 , and other parts of the second part 22 except the first block may be connected to the first block and suspended. It is arranged that other parts of the second part 22 except the first block are not in direct contact with the support layer 40, and the first area includes the portion where the bottom surface of the packaged chip 30 overlaps the first block in longitudinal projection and the packaged chip. The portion where the bottom surface of 30 overlaps with other parts of the second part 22 except the first block. The at least partial overlap of the first area and the second area is the bottom surface of the packaged chip and the first block in the longitudinal projection. The overlapping portion overlaps with the second area; in some embodiments, there is no overlapping portion between the bottom surface of the packaged chip 30 and the first block in longitudinal projection, then the first area includes the bottom surface of the packaged chip 30 and the first block. In the overlapping portions of the two parts 22 except for the first block, the first area and the second area do not overlap.

In this embodiment, a protective layer is introduced, and the protective layer includes a first part disposed on the chip pad on the first surface, and a second part disposed outside the chip pad. The first part can avoid the risk of solder joint detachment that may occur after high-temperature remelting of the chip connection point. The setting of the second part further ensures the formation of a cavity between the bottom surface of the chip and the substrate, which can effectively prevent other materials from entering the cavity, ensuring the overall performance of the chip and improving the reliability of the chip.

An embodiment of the present application also provides a chip packaging method, including:

forming a protective layer on the first surface of the substrate, the protective layer including a first portion disposed on the chip pad on the first surface, and a second portion disposed outside the chip pad;

A packaged chip is provided on the first surface of the substrate. The bottom surface of the packaged chip is provided with interconnection bumps. The interconnection bumps are connected to the chip pads. The interconnection bumps are at least partially surrounded by a protective layer. The bottom surface of the package chip includes In the first area overlapping the second part of the protective layer in longitudinal projection, the bottom surface of the packaged chip is opposite to the first surface, and a cavity is formed between the bottom surface of the packaged chip and the substrate.

As shown in Figure 1, a protective layer 20 is formed on the first surface 11 of the substrate 1-. The protective layer includes a first portion 21 disposed on the chip pad 12 on the first surface 11, and a first portion 21 disposed outside the chip pad. The second part of 22.

The package chip 30 is provided. In a specific embodiment, the package chip 30 can be provided on the first surface 11 of the substrate through an undercut process. The bottom surface of the package chip 30 includes a plurality of interconnection bumps 31 , wherein each interconnection bump 31 is connected to a chip pad on the first surface of the substrate. Among them, the interconnection bump 31 is at least partially surrounded by a protective layer, that is, it is protected by The first part 21 is surrounded by sheath. It can be understood that as long as at least one interconnection bump 31 is at least partially surrounded by a protective layer, it should not be limited to the fact that all interconnection bumps 31 need to be at least partially surrounded by a protective layer.

In one embodiment, forming a protective layer on the first surface of a substrate in a chip packaging method includes:

A protective layer is formed on the first surface of the substrate through a screen printing process.

or,

The first part of the protective layer is formed by a dipping process, and the second part of the protective layer is formed by a screen printing process.

In one embodiment, both the first part and the second part of the protective layer can be formed on the first surface of the substrate through a screen printing process, which can simplify the process and reduce packaging costs.

In one embodiment, the first portion of the protective layer is formed by a dipping process and the second portion of the protective layer is formed by a screen printing process. Forming the first part of the protective layer through a dipping process allows for a more precise formation of the first part of the protective layer to better protect the connection between the interconnect bumps and the chip pads. The second part of the protective layer is formed through a screen printing process, which can reduce the cost of process implementation while ensuring the reliability of chip packaging.

In one embodiment, a chip packaging structure is provided, including:

The substrate is provided with a chip pad on the first surface.

The packaged chip is disposed on the first surface of the substrate, and the bottom surface of the packaged chip is provided with interconnection bumps. The interconnection bumps are connected to the chip pads, and the bottom surface of the packaged chip is opposite to the first surface.

A support layer is formed on the first surface of the substrate. The bottom surface of the package chip includes a second area that overlaps with the support layer in a longitudinal projection. A space is formed between the bottom surface of the package chip, the support layer and the first surface of the substrate. cavity.

A protective layer that surrounds at least part of the interconnect bumps and/or chip pads.

In this embodiment, the bottom surface of the packaged chip includes a second area that overlaps the support layer in longitudinal projection.

In one embodiment, as shown in FIG. 6 , the outer edge of the bottom surface of the package chip 30 overlaps the support layer 40 in longitudinal projection. Taking the bottom surface of the packaged chip 30 in Figure 6 as a rectangular structure as an example, the bottom surface of the packaged chip 30 includes four sides. In Figure 6, at least one side of the bottom surface of the packaged chip and the support layer 40 are projected vertically. Overlap. For the settings on the other three sides, any existing conventional method can be used, as long as it is reasonable. In a specific embodiment, the remaining three sides of the bottom surface of the package chip 30 may overlap with the support layer 40 in a longitudinal projection. It can be understood that the above-mentioned second area may be formed on one side of the package chip 30 , or may be formed on a part of one side, or may be formed on multiple sides of the package chip 30 . In one embodiment, the second region is formed on the first side of the packaged chip 30 .

As shown in FIG. 6 , in this embodiment, the protective layer 20 is equivalent to the first part 21 of the protective layer 20 in other embodiments. The protective layer 20 surrounds at least part of the interconnect bumps 31 and/or the chip pads 12 . The protective layer 20 at least surrounds the interconnection bumps 31 and/or the chip pads 12 to protect the connection between the interconnection bumps 31 and the chip pads 12 and reduce the risk of subsequent damage. There is a risk of detachment or cracking of the connection during subsequent processes or actual applications.

In one embodiment, the protective layer 20 is a low-volatility material. In one embodiment, the protective layer 20 is a low-volatility insulating material. In a specific embodiment, the protective layer is a low-volatile resin material. In a specific embodiment, the protective layer is a non-volatile resin material. Since a cavity structure is formed between the bottom surface of the package chip 30 and the first surface 11 of the substrate 10 , by setting the protective layer to be a low-volatility material, the subsequent need to further clean up the volatiles formed inside the cavity can be reduced. steps, or can reduce the impact on chip performance caused by the inability to clean the volatiles formed inside the cavity, further ensuring the reliability of the chip packaging structure.

In one embodiment, the second area is an annular area disposed outside the bottom surface of the packaged chip. That is, the outside of the bottom surface of the package chip overlaps with the support layer in longitudinal projection.

In one embodiment, at least one side of the packaged chip 30 includes a third area that overlaps the support layer 40 in a lateral projection. As shown in FIG. 7 , in this embodiment, at least one side of the package chip 30 includes a third area that overlaps the support layer 40 in a lateral projection.

In one embodiment, the protective layer 20 surrounds at least the connecting portions of the interconnect bumps 31 and the chip pads 12 . By surrounding the connection portion of the interconnection bump 31 and the chip pad 12, the stability of the connection between the interconnection bump 31 and the chip pad 12 is fully ensured while saving materials.

In one embodiment, a chip packaging structure is provided, including:

A substrate with a chip pad provided on the first surface;

The packaged chip is arranged on the first surface of the substrate, and the bottom surface of the packaged chip is provided with interconnection bumps. The interconnection bumps are connected to the chip pads. The bottom surface of the packaged chip is opposite to the first surface. The bottom surface of the packaged chip is A cavity is formed between the surface and the first surface of the substrate;

In this embodiment, the protective layer corresponds to the first part 21 of the protective layer described above. The protective layer does not include volatile materials, or the protective layer is made of low-volatile materials, or the protective layer is made of non-volatile materials.

In one embodiment, the protective layer is a non-volatile resin material.

In this embodiment, the protective layer at least surrounds the interconnection bumps and/or the chip pads to protect the connection between the interconnection bumps and the chip pads, thereby reducing the risk of subsequent processes or actual Risk of the connection detaching or cracking during application. Moreover, by configuring the protective layer to be made of volatile materials, low-volatile materials, non-volatile materials, etc., it can reduce the need for further cleaning steps of volatiles formed inside the cavity, or can reduce the need to clean the cavity due to the inability to clean the cavity. The impact of internally formed volatiles on chip performance further ensures the reliability of the chip packaging structure.

It is understandable that, in order to avoid redundancy, the details of some of the same or similar technical features in the above description are not included in some actual situations. The description is not expanded in the embodiments or implementations, but essentially these details are also applicable to different embodiments or implementations.

The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application. .

Claims

A chip packaging structure, which includes:

A substrate with a chip pad provided on the first surface;

A protective layer including a first portion disposed on the chip pad on the first surface, and a second portion disposed outside the chip pad;

A packaged chip is provided on the first surface of the substrate, and the bottom surface of the packaged chip is provided with interconnection bumps, the interconnection bumps are connected to the chip pads, and the interconnection bumps are at least Partially surrounded by the first portion of the protective layer, the bottom surface of the packaged chip is opposite to the first surface;

The bottom surface of the packaged chip further includes a first area that overlaps with the second part of the protective layer in a longitudinal projection, and a cavity is formed between the bottom surface of the packaged chip and the substrate.
The chip packaging structure according to claim 1, wherein the protective layer is a low-volatile insulating material or a non-volatile resin material.
The chip packaging structure of claim 1, wherein the chip packaging structure further includes a sealing layer covering at least the second portion of the protective layer and the packaged chip.
The chip packaging structure according to claim 1, wherein the first area of the bottom surface of the package chip is attached to the second part of the protective layer.
The chip packaging structure of claim 1, wherein a longitudinal distance between the first region of the bottom surface of the packaged chip and the second portion of the protective layer is configured to be less than a first threshold.
The chip packaging structure according to claim 1, wherein the chip packaging structure further includes a support layer formed on the first surface of the substrate, and the bottom surface of the package chip further includes a support layer in a longitudinal projection with the support layer. The overlapping second area.
The chip packaging structure of claim 6, wherein the second region is attached to the support layer.
The chip packaging structure of claim 6, wherein a longitudinal distance between the second region and the support layer is configured to be less than a second threshold.
The chip packaging structure of claim 8, wherein the second threshold is 5um, 10um or 15um.
The chip packaging structure of claim 6, wherein at least one side of the packaged chip includes a third area that overlaps the second portion of the support layer and/or the protective layer in a lateral projection.
The chip packaging structure according to claim 6, wherein the support layer includes a first support layer and a second support layer, the first support layer is disposed on the first surface, and the second support layer is disposed On top of the first support layer, At least one side of the packaged chip includes a third region that overlaps the second support layer in a lateral projection.
The chip packaging structure according to claim 11, wherein the second part of the protective layer is disposed on the first support layer and the second support layer, and at least one side of the package chip includes a and a third area where the second portion of the protective layer overlaps in lateral projection.
The chip packaging structure of claim 6, wherein the first region and the second region at least partially overlap.
The chip packaging structure of claim 6, wherein the second portion of the protective layer is at least partially formed on the support layer.
The chip packaging structure of claim 6, wherein the second portion of the protective layer includes at least a first block formed on the support layer, and the first region includes a bottom surface of the packaged chip. The portion of the bottom surface of the package chip that overlaps with the first block in longitudinal projection, and the portion of the bottom surface of the package chip that overlaps with the first block in longitudinal projection at least partially overlaps with the second area.
The chip packaging structure of claim 6, wherein the support layer is at least partially formed on the second portion of the protective layer.
The chip packaging structure of claim 6, wherein the first region and the second region do not overlap.
The chip packaging structure of claim 17, wherein the first area is on a first side of the packaged chip, and the second area is on at least one side of the packaged chip except the first side. .
The chip packaging structure of claim 1, wherein the first portion disposed on the chip pad on the first surface and the second portion disposed outside the chip pad are formed in one process. .
The chip packaging structure of claim 1, wherein the first portion of the protective layer surrounds at least a connection portion of the interconnect bump and the chip pad.
A chip packaging structure, which includes:

A substrate including a chip pad disposed on a first surface;

A support layer formed on the first surface of the substrate;

A protective layer, including a first part provided on the chip pad, and a second part provided on the support layer;

A packaged chip is disposed on the first surface of the substrate, and the bottom surface of the packaged chip is provided with interconnection bumps. The interconnection bumps are connected to the chip pads. The interconnection bumps being at least partially surrounded by a first portion of said protective layer;

The bottom surface of the packaged chip further includes a first area that overlaps with the second portion of the protective layer in a longitudinal projection, and a second area that overlaps with the support layer in a longitudinal projection, the The bottom surface of the packaged chip is opposite to the first surface, and a cavity is formed between the bottom surface of the packaged chip and the substrate.
The chip packaging structure of claim 21, wherein the support layer is provided with a first opening extending longitudinally to the first surface of the substrate.
The chip packaging structure of claim 21, wherein the support layer is provided with a first opening, a second opening is provided in the first opening, and the second opening extends longitudinally to the first surface of the substrate .
The chip packaging structure of claim 21, wherein the first portion of the protective layer surrounds at least a connection portion of the interconnect bump and the chip pad.
The chip packaging structure of claim 21 , wherein at least one side of the packaged chip includes a third area that overlaps the second portion of the support layer and/or the protective layer in a lateral projection.
The chip packaging structure according to claim 21, wherein the support layer includes a first support layer and a second support layer, the first support layer is disposed on the first surface, and the second support layer is disposed Above the first support layer, at least one side of the packaged chip includes a third area that overlaps the second support layer in a lateral projection.
The chip packaging structure according to claim 21, wherein the second part of the protective layer is disposed on the first support layer and the second support layer, and at least one side of the package chip includes a and a third area where the second portion of the protective layer overlaps in lateral projection.
According to the chip packaging structure of claim 21, the first region and the second region at least partially overlap.
The chip packaging structure of claim 21, wherein the second portion of the protective layer includes at least a first block formed on the support layer, and the first region includes a bottom surface of the packaged chip. The portion of the bottom surface of the package chip that overlaps with the first block in longitudinal projection, and the portion of the bottom surface of the package chip that overlaps with the first block in longitudinal projection at least partially overlaps with the second area.
The chip packaging structure of claim 21, wherein the first region and the second region do not overlap.
The chip packaging structure of claim 30, wherein the second part of the protective layer at least includes a first block formed on the support layer, and the bottom surface of the package chip is in contact with the first block. There is no overlap in the vertical projection.
The chip packaging structure of claim 21, wherein the first portion disposed on the chip pad on the first surface and the second portion disposed on the support layer are formed in one process.
A chip packaging method, which includes:

forming a protective layer on the first surface of the substrate, the protective layer comprising a first portion disposed on the chip pad on the first surface, and a second portion disposed outside the chip pad;

A package chip is provided on the first surface of the substrate, a bottom surface of the package chip is provided with bumps, the bumps are connected to the chip pads, and the bumps are at least partially surrounded by the protective layer; The bottom surface of the packaged chip includes The first area where the second part of the protective layer overlaps in longitudinal projection, the bottom surface of the package chip is opposite to the first surface, and a cavity is formed between the bottom surface of the package chip and the substrate .
The chip packaging method according to claim 33, wherein forming the protective layer on the first surface of the substrate includes:

forming the protective layer on the first surface of the substrate through a screen printing process;

or,

The first part of the protective layer is formed by a dipping process, and the second part of the protective layer is formed by a screen printing process.
A chip packaging structure, which includes:

A substrate with a chip pad provided on the first surface;

A packaged chip is provided on the first surface of the substrate, and the bottom surface of the packaged chip is provided with interconnection bumps, and the interconnection bumps are connected to the chip pads. The bottom surface of the packaged chip Opposite the first surface;

A support layer is formed on the first surface of the substrate, the bottom surface of the package chip includes a second area that overlaps with the support layer in a longitudinal projection, the bottom surface of the package chip, the support layer and forming a cavity between the first surfaces of the substrate;

A protective layer surrounding at least part of the interconnection bumps and/or the chip pads.
The chip packaging structure of claim 35, wherein at least one side of the packaged chip includes a second area that overlaps the support layer in a lateral projection.
The chip packaging structure of claim 35, wherein the protective layer surrounds at least a connection portion of the interconnection bump and the chip pad.
The chip packaging structure of claim 35, wherein the second area is an annular area disposed outside the bottom surface of the packaged chip.
The chip packaging structure according to claim 35, wherein the support layer includes a first support layer and a second support layer, the first support layer is disposed on the first surface, and the second support layer is disposed Above the first support layer, a bottom surface of the packaged chip includes a second area that overlaps with the second support layer in a longitudinal projection, and at least one side surface of the packaged chip includes a second area that overlaps with the second support layer. The third area where the support layers overlap in transverse projection.
A chip packaging structure, which includes:

A substrate with a chip pad provided on the first surface;

A packaged chip is provided on the first surface of the substrate, and the bottom surface of the packaged chip is provided with interconnection bumps, and the interconnection bumps are connected to the chip pads. The bottom surface of the packaged chip Opposite the first surface, the package A cavity is formed between the bottom surface of the chip and the first surface of the substrate;

A protective layer surrounding at least part of the interconnection bumps and/or the chip pads.
The chip packaging structure of claim 40, wherein the protective layer surrounds at least a connection portion of the interconnection bump and the chip pad.