WO2023202009A1 - 半导体结构的制备方法、半导体结构和存储器 - Google Patents

半导体结构的制备方法、半导体结构和存储器 Download PDF

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Publication number
WO2023202009A1
WO2023202009A1 PCT/CN2022/125746 CN2022125746W WO2023202009A1 WO 2023202009 A1 WO2023202009 A1 WO 2023202009A1 CN 2022125746 W CN2022125746 W CN 2022125746W WO 2023202009 A1 WO2023202009 A1 WO 2023202009A1
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conductive layer
area
layer
initial
semiconductor structure
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PCT/CN2022/125746
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English (en)
French (fr)
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曾以志
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长鑫存储技术有限公司
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Priority to US18/363,901 priority Critical patent/US20230389270A1/en
Publication of WO2023202009A1 publication Critical patent/WO2023202009A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure, a semiconductor structure and a memory.
  • DRAM Dynamic Random Access Memory
  • a DRAM includes a substrate, and the substrate includes an array area and a peripheral area disposed outside the array area.
  • an isolation layer is usually formed on a substrate. The isolation layer extends from the array area to the peripheral area, and a conductive layer is formed on the isolation layer.
  • Embodiments of the present application provide a method for preparing a semiconductor structure, a semiconductor structure and a memory, which can improve the flatness of the surface of the conductive layer, thereby avoiding affecting the structure and performance of the semiconductor structure and the memory.
  • the first aspect of the embodiment of the present application provides a method for preparing a semiconductor structure, including: providing a substrate including an array region, a core region, and a boundary region between the array region and the core region; forming a first initial isolation layer, The first initial isolation layer is located in the array area, the boundary area and the core area, and the first initial isolation layer covers the substrate; the first initial isolation layer located in the core area and the first part of the boundary area adjacent to the core area is removed to obtain the first isolation layer layer; forming a first initial conductive layer, the first initial conductive layer is located in the array area, the boundary area and the core area, the first initial conductive layer covers the base and the first isolation layer; the first initial conductive layer is planarized to obtain the first middle conductive layer; and removing the first middle conductive layer located in the array area and the second partial boundary area adjacent to the array area to obtain the first conductive layer; wherein the orthographic projection of the first conductive layer on the substrate is equal to The orthographic projection of the first isolation layer on the substrate partially overlap
  • a second aspect of the embodiments of the present application provides a semiconductor structure, which is prepared by the method for preparing the semiconductor structure in the first aspect.
  • a third aspect of the embodiments of the present application provides a memory, including a semiconductor structure prepared by the method for preparing a semiconductor structure in the first aspect.
  • Embodiments of the present application provide a method for preparing a semiconductor structure, a semiconductor structure, and a memory.
  • the method for preparing a semiconductor structure may include providing a substrate.
  • the substrate includes an array region, a core region, and a boundary region between the array region and the core region; Forming a first initial isolation layer, the first initial isolation layer is located in the array area, the boundary area and the core area, and the first initial isolation layer covers the substrate; removing the first initial isolation layer located in the core area and the first part of the boundary area adjacent to the core area layer to obtain the first isolation layer; forming a first initial conductive layer, the first initial conductive layer is located in the array area, the boundary area and the core area, and the first initial conductive layer covers the substrate and the first isolation layer; for the first initial conductive layer Performing a planarization process to obtain a first intermediate conductive layer; and removing the first intermediate conductive layer located in the array area and the second partial boundary area adjacent to the array area to obtain a first conductive layer;
  • the surface flatness of the formed first conductive layer is better, so that other functional layers prepared above the first conductive layer can have better flatness.
  • the thickness of the functional layer above the layer is relatively uniform, which avoids or reduces the occurrence of functional layer residues during the etching process, thereby avoiding or reducing the impact on the structure and performance of the semiconductor structure and memory.
  • Figure 1 is a schematic structural diagram of a semiconductor structure
  • Figure 2 is a schematic flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present application
  • Figure 3 is a schematic structural diagram of a substrate provided by an embodiment of the present application.
  • Figure 4 is a schematic structural diagram of forming a first initial isolation layer according to an embodiment of the present application.
  • Figure 5 is a schematic structural diagram of forming a first isolation layer according to an embodiment of the present application.
  • Figure 6 is a schematic structural diagram of forming a first initial conductive layer according to an embodiment of the present application.
  • Figure 7 is a schematic structural diagram of planarizing the first initial conductive layer according to an embodiment of the present application.
  • Figure 8 is a schematic structural diagram of forming a second initial mask layer according to an embodiment of the present application.
  • Figure 9 is a schematic structural diagram of forming a second mask layer according to an embodiment of the present application.
  • Figure 10 is a schematic structural diagram of ion implantation provided by an embodiment of the present application.
  • Figure 11 is a schematic structural diagram of removing the second mask layer according to an embodiment of the present application.
  • Figure 12 is a schematic structural diagram of the first initial conductive layer treated by thermal annealing according to an embodiment of the present application
  • Figure 13 is a schematic structural diagram of forming a first conductive layer according to an embodiment of the present application.
  • Figure 14 is a schematic structural diagram of forming a second conductive layer according to an embodiment of the present application.
  • Figure 15 is a schematic structural diagram of forming a third conductive layer according to an embodiment of the present application.
  • Figure 16 is a schematic structural diagram of forming a second isolation layer according to an embodiment of the present application.
  • Figure 17 is a schematic structural diagram of the second conductive layer, the third conductive layer and the second isolation layer in the boundary region removed according to an embodiment of the present application;
  • FIG. 18 is a schematic structural diagram of the first conductive layer with the boundary region removed according to an embodiment of the present application.
  • 110a-array area 110b-core area
  • DRAM includes multiple repeated memory cells.
  • Each memory unit includes a capacitor and a transistor.
  • the gate of the transistor is connected to the word line (WL), and one of the drain and source is connected to the bit line. , the source and the other of the source are connected to the capacitor.
  • the voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.
  • the word line is connected to the word line driver (Word line driver) through a contact structure (Local interconnect contact, LICON for short) located on the periphery of the memory cell, thereby facilitating the word line driver to input voltage signals into the word line. As shown in FIG.
  • the DRAM may include a substrate 110.
  • the substrate 110 includes an array area 110a, a boundary area 110c, and a core area 110b.
  • the boundary area 110c is located between the array area 110a and the core area 110b.
  • a first isolation layer 122 is first formed on the substrate.
  • the first isolation layer 122 is located in a portion of the array area 110 a and the boundary area 110 c close to the array area 110 a to expose the rest of the substrate 110 .
  • the first conductive layer 133 is then disposed on the first isolation layer 122 and the exposed substrate 110 in the partial boundary region 110c.
  • the first isolation layer 122 covers the array area 110a and the partial area of the boundary area 110c close to the array area 110a, the partial area of the boundary area 110c close to the core area 110b and the core area 110b are not Covering the first isolation layer 122 results in a step between the area covered with the first isolation layer 122 and the area not covered with the first isolation layer 122 , resulting in the first conductive layer 133 in the boundary region 110c and the first conductive layer covering the
  • the other functional layers on the first conductive layer 133 all form steps, so that the surface flatness of the first conductive layer 133 and the functional layers located on the first conductive layer 133 is poor.
  • the thickness of the functional layer located at the step is larger than the rest of the functional layer, A Parts of the functional layer are not easily etched cleanly compared to other areas of the functional layer, and residues are prone to appear, thereby affecting the structure and performance of the DRAM.
  • Embodiments of the present application provide a method for preparing a semiconductor structure, a semiconductor structure, and a memory.
  • the method for preparing a semiconductor structure may include providing a substrate.
  • the substrate includes an array region, a core region, and a boundary region between the array region and the core region; Forming a first initial isolation layer, the first initial isolation layer is located in the array area, the boundary area and the core area, and the first initial isolation layer covers the substrate; removing the first initial isolation layer located in the core area and the first part of the boundary area adjacent to the core area layer to obtain the first isolation layer; forming a first initial conductive layer, the first initial conductive layer is located in the array area, the boundary area and the core area, and the first initial conductive layer covers the substrate and the first isolation layer; for the first initial conductive layer Performing a planarization process to obtain a first intermediate conductive layer; and removing the first intermediate conductive layer located in the array area and the second partial boundary area adjacent to the array area to obtain a first conductive layer;
  • the surface flatness of the formed first conductive layer is better, so that other functional layers prepared above the first conductive layer can have better flatness.
  • the thickness of the functional layer above the layer is relatively uniform, which avoids or reduces the occurrence of functional layer residues during the etching process, thereby avoiding or reducing the impact on the structure and performance of the semiconductor structure and memory.
  • the preparation method of the semiconductor structure 100 may include the following steps:
  • S100 Provide a substrate, which includes an array area, a core area, and a boundary area between the array area and the core area.
  • the substrate 110 may include an array region 110a, a border region 110c and a core region 110b arranged adjacent in sequence.
  • the border region 110c is located between the array region 110a and the core region 110b.
  • the border area 110c and the core area 110b may be located on at least one side of the array area 110a.
  • the boundary area 110c may be disposed on the outer periphery of the array area 110a, that is, the boundary area 110c may surround the array area 110a.
  • the core area 110b may be disposed on the outer periphery of the boundary area 110c, that is, the core area 110b may surround the boundary area 110c.
  • a capacitor may be subsequently formed above the array region 110a of the substrate 110; a peripheral circuit may be subsequently formed above the core region 110b of the substrate 110.
  • the peripheral circuit may include a transistor.
  • the boundary area 110c is a transition area between the array area 110a and the core area 110b.
  • the boundary area 110c includes a first partial boundary area 110d, a second partial boundary area 110e, and a third partial boundary area 110f located between the first partial boundary area 110d and the second partial boundary area 110e.
  • the first part of the boundary area 110d is a part of the boundary area 110c close to the core area 110b.
  • the first part of the boundary area 110d is adjacent to the core area 110b.
  • the second part of the boundary area 110e is a part of the boundary area 110c close to the array area 110a.
  • the partial boundary area 110e is adjacent to the array area 110a;
  • the third partial boundary area 110f is the area in the boundary area 110c located between the first partial boundary area 110d and the second partial boundary area 110e.
  • an active region 111 may be provided in the substrate 110 .
  • Part of the active region 111 may be located in the array region 110 a and used to form transistors.
  • the active regions 111 located in the array region 110 a may be arranged in an array.
  • Part of the active region 111 may be located in the core region 110b and used to form transistors.
  • Isolation structures 112 are provided between the active areas 111 to separate each active area 111 from each other.
  • isolation structure 112 may include an oxide, such as silicon oxide.
  • the substrate 110 may include a substrate and an oxide layer located on the substrate, and both the active region 111 and the isolation structure 112 may be located within the substrate.
  • the oxide layer on the substrate can prevent the active area 111 from being exposed.
  • the thickness of the oxide layer located in the array region 110a may be greater than the thickness of the oxide layer located in the core region 110b.
  • a thick oxide layer can be formed on the substrate first, and the thick oxide layer located in the core area 110b is removed, leaving the thick oxide layer located in the array area 110a.
  • part or all of the thick oxide layer in the boundary area 110c can be removed, or , retaining the thick oxide layer of the boundary region 110c.
  • a thin oxide layer is formed on the substrate of the core region 110b.
  • the thin oxide layer may be a high-quality oxide layer to improve the performance of devices (eg, transistors) with thin oxide layers.
  • the thin oxide layer may have a higher dielectric constant, making the thin oxide layer more insulating and increasing the breakdown voltage of the transistor containing the thin oxide layer.
  • high dielectric constant materials may include tantalum oxide (Ta 2 O 5 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO), silicon titanium oxide (SiTiO 3 ), hafnium silicon oxide (HfSiO), nitrogen Any one or more of hafnium silicon oxide (HfSiON) and zirconium silicon oxynitride (ZrSiON).
  • the material of the substrate can be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium silicide, silicon carbide, gallium nitride, etc.
  • the substrate can be a bulk silicon (Bulk Silicon) substrate or a silicon on insulator (SOI) substrate.
  • the substrate can provide a supporting base for other structural layers on the substrate.
  • S200 Form a first initial isolation layer.
  • the first initial isolation layer is located in the array area, the boundary area and the core area, and the first initial isolation layer covers the substrate.
  • a first initial isolation layer 121 is formed on the substrate 110 , and the first initial isolation layer 121 covers the array area 110 a , the boundary area 110 c and the core area 110 b of the substrate 110 .
  • the material of the first initial isolation layer 121 may be silicon nitride, and silicon nitride has a better isolation effect.
  • the first initial isolation layer 121 may be formed on the substrate 110 through a deposition process.
  • the first initial isolation layer 121 can be formed on the substrate through processes such as chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD), physical vapor deposition (Physical Vapor Deposition, referred to as PVD) or atomic layer deposition (Atomic Layer Deposition, referred to as ALD). 110 on.
  • CVD chemical Vapor Deposition
  • PVD Physical vapor deposition
  • ALD atomic layer deposition
  • S300 Remove the first initial isolation layer located in the core area and the first portion of the boundary area adjacent to the core area to obtain a first isolation layer.
  • first isolation layer 122 is used to isolate the substrate 110 located below the first isolation layer 122 from the substrate 110 located above the first isolation layer 122 .
  • the first initial isolation layer 121 in the core area 110b and the boundary area 110c can be removed, the first initial isolation layer 121 in the array area 110a is retained, and the first isolation layer 122 is formed on the substrate 110 in the array area 110a.
  • the first initial isolation layer 121 in the core area 110b and the first partial boundary area 110d can be removed, and the first initial isolation layer 121 in the array area 110a, the second partial boundary area 110e and the third partial boundary area 110f can be retained.
  • a first initial isolation layer 121 is used to form a first isolation layer 122 on the substrate 110 of the array area 110a, the second partial boundary area 110e, and the third partial boundary area 110f.
  • the orthographic projection of the array area 110a on the substrate 110 is located within the orthographic projection of the first isolation layer 122 on the substrate 110, so that the first isolation layer 122 completely covers the array area 110a, which has an isolation effect on the substrate 110 of the array area 110a. better.
  • S300 can include:
  • the initial mask layer is formed on the first initial isolation layer 121.
  • the initial mask layer may be a first initial mask layer covering the array area 110a, the boundary area 110c and the core area 110b of the substrate 110.
  • the first initial mask layer may be photoresist.
  • the first initial mask layer in the core area 110b and the first partial boundary area 110d is removed to form a first mask layer covering the array area 110a, the second partial boundary area 110e and the third partial boundary area 110f.
  • the first initial isolation layer 121 exposes the first initial isolation layer 121 in the core area 110b and the first partial boundary area 110d.
  • first mask layer As a mask, remove the first initial isolation layer 121 in the area not covered by the first mask layer, namely the core area 110b and the first part of the boundary area 110d, to form the first isolation layer 122.
  • Layer 122 is located on the substrate 110 of the array area 110a, the second partial boundary area 110e, and the third partial boundary area 110f.
  • the first mask layer is removed to expose the first isolation layer 122 .
  • a thick oxide layer located in the array region 110a and a thin oxide layer located in the core region 110b may be formed respectively, and the first initial isolation layer 121 covers the thick oxide layer. layer and thin oxide layer.
  • a thick oxide layer may be formed first. The thick oxide layer covers the substrate of the array area 110a, the boundary area 110c and the core area 110b. The first initial isolation layer 121 covers the thick oxide layer.
  • a thin oxide layer is then formed on the substrate in the core region 110b and the first portion of the boundary region 110d. Part of the thin oxide layer may cover an edge of the first isolation layer 122 to avoid exposing the substrate and protect the substrate.
  • S400 Form a first initial conductive layer.
  • the first initial conductive layer is located in the array area, the boundary area and the core area.
  • the first initial conductive layer covers the substrate and the first isolation layer.
  • a first initial conductive layer 131 is formed on the first isolation layer 122 and the exposed substrate 110, and the first initial conductive layer 131 is located in the array area 110a, the boundary area 110c and the core area 110b. Since there are steps between the substrate 110 covered with the first isolation layer 122 and not covered with the first isolation layer 122 , there are steps in the first initial conductive layer 131 , thereby forming a step portion 134 on the upper part of the first initial conductive layer 131 . The step portion 134 will cause other functional layers subsequently formed on the first initial conductive layer 131 to also have steps, affecting the flatness of other functional layers, thus affecting the structure and performance of the semiconductor structure 100 .
  • the material of the first initial conductive layer 131 may be polycrystalline silicon.
  • the thickness d (in FIG. 6 ) of the first initial conductive layer 131 may range from 40 nm to 120 nm.
  • the thickness d of the first initial conductive layer 131 may be 40 nm, 60 nm, 80 nm, 100 nm, 120 nm, and 40 nm. Any thickness between -120nm. Therefore, the thickness of the first initial conductive layer 131 can be avoided from being too low.
  • the thickness of the remaining first initial conductive layer 131 can be avoided from being too low; and the first initial conductive layer 131 can be prevented from being too low.
  • the thickness of layer 131 is too high to prevent the subsequent planarization process from taking too long.
  • S500 Perform planarization processing on the first initial conductive layer to obtain a first intermediate conductive layer.
  • the first initial conductive layer 131 is planarized, a part of the thickness of the first initial conductive layer 131 is removed, and a part of the thickness of the first initial conductive layer 131 is retained, thereby obtaining the first intermediate conductive layer 132 .
  • S500 can include:
  • the first initial conductive layer 131 located in the array area 110a and the boundary area 110c is doped.
  • the step portion 134 is doped to change the properties of the doped first initial conductive layer 131, so that the doped first initial conductive layer 131 is easier to remove, and the doped first initial conductive layer 131 is The removal speed of the layer 131 is faster, while the removal speed of the undoped first initial conductive layer 131 is slower, so that part of the thickness of the first initial conductive layer 131 can be removed while the step portion 134 is removed, so that the remaining The top surface of the first initial conductive layer 131 forms a relatively flat surface.
  • the thickness of the doped first initial conductive layer 131 may range from 5 nm to 10 nm. That is, the doping thickness of the step portion 134 may range from 5 nm to 10 nm.
  • the thickness of the doped step portion 134 may be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, or any thickness between 5 nm and 10 nm. Therefore, it can be avoided that the thickness of the doped step portion 134 is too low and the step portion 134 cannot be removed well; and it can also be avoided that the thickness of the doped step portion 134 is too high and the doping accuracy is reduced.
  • the doped material 135 may include any one or more of Group V elements such as arsenic atoms and phosphorus atoms, and Group IV elements such as carbon atoms.
  • the first initial conductive layer 131 is etched or chemically mechanically polished to obtain the first intermediate conductive layer 132 .
  • the planarization process may include methods such as dry etching, wet etching, or chemical mechanical polishing. Part of the thickness of the first initial conductive layer 131 is removed through the planarization process, and the remaining first initial conductive layer 131 forms the first intermediate conductive layer.
  • Layer 132, the top surface of the first intermediate conductive layer 132 can be a plane, and its flatness is good to avoid or reduce the impact on the flatness of other functional layers subsequently formed on the first intermediate conductive layer 132, thereby avoiding or Effects on the structure and performance of the semiconductor structure 100 are reduced.
  • the step of doping the first initial conductive layer 131 located in the array region 110a and the boundary region 110c may include:
  • an initial mask layer is formed.
  • the initial mask layer is located in the array area 110a, the boundary area 110c and the core area 110b.
  • the initial mask layer covers the first initial conductive layer 131.
  • An initial mask layer is formed on the first initial conductive layer 131.
  • the initial mask layer may be a second initial mask layer 141.
  • the second initial mask layer 141 is located in the array area 110a, the boundary area 110c and the core area 110b.
  • the second initial mask layer 141 may be photoresist.
  • the second initial mask layer 141 located in the array area 110 a and the boundary area 110 c is removed to obtain a mask layer, which may be a second mask layer 142 . That is, the second initial mask layer 141 above the step portion 134 can be removed, thereby exposing the step portion 134 to facilitate the doping process of the step portion 134 .
  • the side wall surface of the step portion 134 close to the core area 110b may be a curved surface, that is, the height of the side wall surface of the step portion 134 gradually increases, and the side wall surface is inclined.
  • the second mask layer 142 can cover part of the sidewall surface of the step part 134 close to the core region 110b, thereby avoiding doping processing of part of the sidewall surface of the step part 134 close to the core region 110b, causing the doping material 135 to be along the
  • the sidewall distribution thickness is large, and the thickness of the doping process cannot be accurately controlled, and even causes the doping material 135 to enter under the step portion 134 through the sidewall surface with a small height, thus affecting the uniformity of the doping process and the accuracy of the thickness control. .
  • ion implantation is performed on the first initial conductive layer 131 in the array area 110 a and the boundary area 110 c.
  • the doping treatment may include ion implantation.
  • the dose range of ion implantation is 10 13 atoms/cm2 to 10 15 atoms/cm2.
  • the dose range of ion implantation is 10 13 atoms/cm2, 10 14 atoms/cm2, 10 15 atoms/cm2, or between 10 13 atoms/cm2 and 10 15 atoms/cm2. Any dose. This can prevent the dose of ion implantation from being too small and the content of the doping material 135 incorporated into the first initial conductive layer 131 from being too low, thereby improving the properties of the first initial conductive layer 131 better; and also avoiding ions. The injected dose is too large, which is beneficial to controlling the content of the doping material 135 incorporated into the first initial conductive layer 131 .
  • the energy range of ion implantation may be 30keV-100keV.
  • the energy of ion implantation can be 30keV, 50keV, 70keV, 90keV, 100keV or any energy between 30keV and 100keV. This can avoid the energy of ion implantation being too low, the content of the doping material 135 injected into the first initial conductive layer 131 being too low, or the implantation depth being too shallow, thereby improving the properties of the first initial conductive layer 131 better. ; It can also prevent the ion implantation energy from being too high, thereby avoiding the implantation depth of the doping material 135 being too deep, and allowing better control of the thickness (ie, depth) of the doping process.
  • the second mask layer 142 is removed. After the doping process, the second mask layer 142 can be removed to expose the first initial conductive layer 131 located in the core region 110b.
  • the first initial conductive layer 131 located in the array region 110a and the boundary region 110c is doped and processed, and before the step of etching or chemical mechanical polishing the first initial conductive layer 131 to obtain the first intermediate conductive layer 132, It may include: thermal annealing the first initial conductive layer 131 .
  • the doped first initial conductive layer 131 may be thermally annealed. Thermal annealing treatment can repair the surface crystal damage of the first initial conductive layer 131 caused by ion implantation, activate the ion implanted doping material 135, and at the same time make the doping material 135 evenly distributed in the first initial conductive layer 131 of the required thickness. .
  • the first intermediate conductive layer 132 located in the array area 110a and the second partial boundary area 110e is removed, and the first intermediate conductive layer 132 located in the first partial boundary area 110d, the third partial boundary area 110f and the core area 110b is retained.
  • An intermediate conductive layer 132 is formed to form a first conductive layer 133 .
  • the first conductive layer 133 covers the first partial boundary area 110d, the third partial boundary area 110f and the core area 110b.
  • the orthographic projection of the first conductive layer 133 on the substrate 110 partially overlaps with the orthographic projection of the first isolation layer 122 on the substrate 110 , and the orthographic projection of the first conductive layer 133 on the substrate 110 overlaps with the orthographic projection of the first conductive layer 133 on the substrate 110 .
  • An overlapping portion of the orthographic projection of an isolation layer 122 on the substrate 110 is located in the third partial boundary region 110f. The overlapping portion of the first conductive layer 133 and the first isolation layer 122 can prevent the substrate 110 from being exposed, thereby protecting the substrate 110 .
  • the step of obtaining the first conductive layer 133 it may also include:
  • a second conductive layer 151 is formed.
  • the second conductive layer 151 is located in the array area 110a, the boundary area 110c and the core area 110b.
  • the second conductive layer 151 covers the first isolation layer 122 and the first conductive layer 133. That is, the second conductive layer 151 is formed on the first conductive layer 133 and the first isolation layer 122, and the second conductive layer 151 covers the array area 110a, the boundary area 110c and the core area 110b.
  • the step of forming the second conductive layer 151 may also include:
  • a third conductive layer 152 is formed.
  • the third conductive layer 152 is located in the array area 110 a, the boundary area 110 c and the core area 110 b.
  • the third conductive layer 152 covers the second conductive layer 151 . That is, the third conductive layer 152 is formed on the second conductive layer 151, and the third conductive layer 152 covers the array area 110a, the boundary area 110c and the core area 110b.
  • the material of the second conductive layer 151 may be titanium nitride
  • the material of the third conductive layer 152 may be tungsten.
  • Titanium nitride can prevent tungsten from diffusing and reacting with silicon to form a low-resistance ohmic contact, which is beneficial to improving the adhesion of tungsten. Additionally, tungsten has good step coverage.
  • the step of forming the third conductive layer 152 may also include:
  • a second isolation layer 153 is formed.
  • the second isolation layer 153 is located in the array area 110a, the boundary area 110c and the core area 110b.
  • the second isolation layer 153 covers the third conductive layer 152. That is, the second isolation layer 153 is formed on the third conductive layer 152, and the second isolation layer 153 covers the array area 110a, the boundary area 110c and the core area 110b.
  • the material of the second isolation layer 153 may be silicon nitride.
  • any one or more of the second conductive layer 151, the third conductive layer 152, and the second isolation layer 153 can form the functional layer in the above embodiment.
  • the second conductive layer 151 and the third conductive layer 152 located in the array area 110a may subsequently form bit lines.
  • the thin oxide layer located in the core region 110b, the first conductive layer 133, the second conductive layer 151, the third conductive layer 152 and the active region 111 in the substrate 110 may subsequently form a device, such as a transistor.
  • the second isolation layer 153 may also include:
  • the second isolation layer 153 , the third conductive layer 152 and the second conductive layer 151 located in the boundary region 110 c are sequentially removed.
  • the second conductive layer 151 located in the core region 110 b and the second conductive layer 151 located in the array region 110 a are removed in sequence.
  • the layer 151 is electrically isolated, and the third conductive layer 152 located in the core region 110b is electrically isolated from the third conductive layer 152 located in the array region 110a.
  • the second conductive layer 133 located above the first conductive layer 133 is The thickness of the isolation layer 153, the third conductive layer 152 and the second conductive layer 151 is relatively uniform, which can avoid or reduce the residual of the second conductive layer 151, thereby avoiding or reducing the impact of the residual second conductive layer 151 on the structure and structure of the semiconductor structure 100. Performance impact.
  • part or all of the first conductive layer 133 in the boundary area 110c can also be removed (FIG. 18), or the first conductive layer 133 in the boundary area 110c can also be retained (FIG. 17 ).
  • insulating material may also be filled in the boundary region 110c to ensure necessary electrical isolation between the array region 110a and the core region 110b.
  • the embodiment of the present application also provides a semiconductor structure 100, which can be prepared by using the method for manufacturing the semiconductor structure 100 in the above embodiment.
  • the semiconductor structure 100 may include a substrate 110 including an array region 110a, a core region 110b, and a boundary region 110c between the array region 110a and the core region 110b.
  • the first isolation layer 122 and the first conductive layer 133 are sequentially stacked on the substrate 110.
  • the first isolation layer 122 covers the substrate 110 of the array area 110a, the second partial boundary area 110e and the third partial boundary area 110f.
  • the conductive layer 133 covers the first isolation layer 122 and the substrate 110 in the core region 110b, the first partial boundary region 110d and the third partial boundary region 110f.
  • the top surface of the first conductive layer 133 may be flat, so that the top surface of the first conductive layer 133 has better flatness.
  • the first conductive layer 133 may be planarized so that the top surface of the first conductive layer 133 forms a flat surface to avoid damage to other functional layers (eg, second functional layers) subsequently formed on the first conductive layer 133 .
  • the flatness of the conductive layer 151, the third conductive layer 152, the second isolation layer 153, etc.) is affected to avoid or reduce the functional layer remaining in the boundary region 110c in the subsequent etching process, thereby avoiding or reducing damage to the semiconductor structure 100. Structural and performance effects.
  • the orthographic projection of the first conductive layer 133 on the substrate 110 partially overlaps with the orthographic projection of the first isolation layer 122 on the substrate 110 , and the orthographic projection of the first conductive layer 133 on the substrate 110 overlaps with the first isolation layer 122
  • the overlapping portion of the orthographic projection on the substrate 110 is located in the third partial boundary area 110f, so that the substrate 110 can be prevented from being exposed to form protection for the substrate 110 .
  • the first conductive layer 133 in the boundary region 110c may be retained (FIG. 17), or part or all of the first conductive layer 133 in the boundary region 110c may be removed (FIG. 17). 18).
  • the semiconductor structure 100 may be a semiconductor structure 100 formed by retaining at least part of the first conductive layer 133 in the boundary region 110c, or may be a semiconductor structure 100 formed by removing the first conductive layer 133 in the boundary region 110c.
  • An embodiment of the present application also provides a memory, which may include a semiconductor structure 100 prepared using the method for manufacturing the semiconductor structure 100 in the above embodiment.
  • the memory may include, for example, dynamic random access memory, static random access memory (Static Random Access Memory, SRAM for short), flash memory, and electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM for short), Phase Change Random Access Memory (PRAM for short) or Magnetoresistive Random Access Memory (MRAM for short).
  • SRAM static random access memory
  • EEPROM Electrically erasable programmable read-only memory
  • PRAM Phase Change Random Access Memory
  • MRAM Magnetoresistive Random Access Memory
  • the semiconductor structure 100 in the above embodiment can be applied to non-memory devices.
  • the non-memory device may be a logic device (such as a microprocessor, digital signal processor, or microcontroller) or similar device.
  • the embodiment of this application takes DRAM memory as an example for description.
  • the semiconductor structure 100 in the above embodiment can be applied to a memory, and the memory includes the semiconductor structure 100 .
  • the semiconductor structure 100 may include a substrate 110 including an array region 110a, a core region 110b, and a boundary region 110c between the array region 110a and the core region 110b.
  • the first isolation layer 122 and the first conductive layer 133 are sequentially stacked on the substrate 110.
  • the first isolation layer 122 covers the substrate 110 of the array area 110a, the second partial boundary area 110e and the third partial boundary area 110f.
  • the conductive layer 133 covers the first isolation layer 122 and the substrate 110 in the core region 110b, the first partial boundary region 110d and the third partial boundary region 110f.
  • the top surface of the first conductive layer 133 may be flat, so that the top surface of the first conductive layer 133 has better flatness.
  • the first conductive layer 133 may be planarized so that the top surface of the first conductive layer 133 forms a flat surface to avoid damage to other functional layers subsequently formed on the first conductive layer 133 (eg, the second conductive layer 133 ).
  • the flatness of the conductive layer 151, the third conductive layer 152, the second isolation layer 153, etc.) is affected to avoid or reduce the functional layer remaining in the boundary region 110c in the subsequent etching process, thereby avoiding or reducing the impact on the structure and structure of the memory. Performance impact.
  • the orthographic projection of the first conductive layer 133 on the substrate 110 partially overlaps with the orthographic projection of the first isolation layer 122 on the substrate 110 , and the orthographic projection of the first conductive layer 133 on the substrate 110 overlaps with the first isolation layer 122
  • the overlapping portion of the orthographic projection on the substrate 110 is located in the third partial boundary area 110f, so that the substrate 110 can be prevented from being exposed to form protection for the substrate 110 .
  • the first conductive layer 133 in the boundary region 110c can be removed to electrically isolate the first conductive layer 133 located in the core region 110b and the array region 110a. . In other examples, part or all of the first conductive layer 133 in the boundary region 110c may also be retained.

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Abstract

本申请提供一种半导体结构的制备方法、半导体结构和存储器，包括提供基底，基底包括阵列区、核心区、以及位于阵列区和核心区之间的边界区；形成第一隔离层，第一隔离层位于阵列区和邻接阵列区的第二部分边界区；形成第一导电层，第一导电层位于核心区和邻接核心区的第一部分边界区。其中，对第一导电层进行平坦化处理，以得到平整的顶面。因此，本申请提供的半导体结构的制备方法、半导体结构和存储器，能够提高第一导电层的表面的平整性，从而避免或减少对半导体结构和存储器的结构和性能的影响。

Description

半导体结构的制备方法、半导体结构和存储器
本申请要求于2022年04月18日提交中国专利局、申请号为202210404527.5、申请名称为“半导体结构的制备方法、半导体结构和存储器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构的制备方法、半导体结构和存储器。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)是一种高速地、随机地写入和读取数据的半导体存储器，被广泛地应用到数据存储设备或装置中。
相关技术中，DRAM包括衬底，衬底包括阵列区和设置在阵列区外的外围区。在制备DRAM时，通常在衬底上形成隔离层，隔离层由阵列区延伸至外围区，并于隔离层上形成导电层。
然而，在上述DRAM的制程中，导电层的表面平整性较差，从而影响DRAM的结构和性能。
发明内容
本申请实施例提供一种半导体结构的制备方法、半导体结构和存储器，能够提高导电层的表面的平整性，从而避免影响半导体结构和存储器的结构和性能。
本申请实施例提供如下技术方案：
本申请实施例的第一方面提供一种半导体结构的制备方法，包括：提供基底，基底包括阵列区、核心区、以及位于阵列区和核心区之间的边界区；形成第一初始隔离层，第一初始隔离层位于阵列区、边界区和核心区，第一初始隔离层覆盖基底；去除位于核心区以及与核心区邻接的第一部分边界区中的第一初始隔离层，以得到第一隔离层；形成第一初始导电层，第一初始导电层位于阵列区、边界区和核心区，第一初始导电层覆盖基底和第一隔离层；对第一初始导电层进行平坦化处理，以得到第一中间导电层；以及去除位于阵列区以及与阵列区邻接的第二部分边界区中的第一中间导电层，以得到第一导电层；其中，第一导电层在基底上的正投影与第一隔离层在基底上的正投影部分交叠，且第一导电层在基底上的正投影与第一隔离层在基底上的正投影的交叠部分位于边界区内。
本申请实施例的第二方面提供一种半导体结构，通过上述第一方面中的半导体结 构的制备方法制备而成。
本申请实施例的第三方面提供一种存储器，包括通过上述第一方面中的半导体结构的制备方法制备而成的半导体结构。
本申请实施例的提供的半导体结构的制备方法、半导体结构和存储器，该半导体结构的制备方法可以包括提供基底，基底包括阵列区、核心区、以及位于阵列区和核心区之间的边界区；形成第一初始隔离层，第一初始隔离层位于阵列区、边界区和核心区，第一初始隔离层覆盖基底；去除位于核心区以及与核心区邻接的第一部分边界区中的第一初始隔离层，以得到第一隔离层；形成第一初始导电层，第一初始导电层位于阵列区、边界区和核心区，第一初始导电层覆盖基底和第一隔离层；对第一初始导电层进行平坦化处理，以得到第一中间导电层；以及去除位于阵列区以及与阵列区邻接的第二部分边界区中的第一中间导电层，以得到第一导电层；其中，第一导电层在基底上的正投影与第一隔离层在基底上的正投影部分交叠，且第一导电层在基底上的正投影与第一隔离层在基底上的正投影的交叠部分位于边界区内。由于对第一初始导电层进行平坦化处理，使得形成的第一导电层的表面平整性较好，从而可以使得制备在第一导电层上方的其他功能层的平整性较好，位于第一导电层上方的该功能层的厚度较为均匀，避免或减少在刻蚀工序中出现功能层残留，从而避免或减少对半导体结构和存储器的结构和性能的影响。
本申请的构造以及它的其他发明目的及有益效果将会通过结合附图而对优选实施例的描述而更加明显易懂。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作以简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种半导体结构的结构示意图；
图2为本申请实施例提供的半导体结构的制备方法的流程示意图；
图3为本申请实施例提供的提供基底的结构示意图；
图4为本申请实施例提供的形成第一初始隔离层的结构示意图；
图5为本申请实施例提供的形成第一隔离层的结构示意图；
图6为本申请实施例提供的形成第一初始导电层的结构示意图；
图7为本申请实施例提供的对第一初始导电层进行平坦化处理的结构示意图；
图8为本申请实施例提供的形成第二初始掩膜层的结构示意图；
图9为本申请实施例提供的形成第二掩膜层的结构示意图；
图10为本申请实施例提供的离子注入的结构示意图；
图11为本申请实施例提供的去除第二掩膜层的结构示意图；
图12为本申请实施例提供的热退火处理第一初始导电层的结构示意图；
图13为本申请实施例提供的形成第一导电层的结构示意图；
图14为本申请实施例提供的形成第二导电层的结构示意图；
图15为本申请实施例提供的形成第三导电层的结构示意图；
图16为本申请实施例提供的形成第二隔离层的结构示意图；
图17为本申请实施例提供的去除边界区的第二导电层、第三导电层和第二隔离层的结构示意图；
图18为本申请实施例提供的去除边界区的第一导电层的结构示意图。
附图标记说明：
100-半导体结构；             110-基底；
110a-阵列区；                110b-核心区；
110c-边界区；                110d-第一部分边界区；
110e-第二部分边界区；        110f-第三部分边界区；
111-有源区；                 112-隔离结构；
121-第一初始隔离层；         122-第一隔离层；
131-第一初始导电层；         132-第一中间导电层；
133-第一导电层；             134-台阶部；
135-掺杂材料；               141-第二初始掩膜层；
142-第二掩膜层；             151-第二导电层；
152-第三导电层；             153-第二隔离层。
具体实施方式
相关技术中，DRAM包括多个重复的存储单元，每个存储单元包括电容器和晶体管，晶体管的栅极与字线(Word line，简称为WL)相连、漏极和源极之一与位线相连、源极和源极之另一与电容器相连。字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。字线通过位于存储单元的外围的接触结构(Local interconnect contact，简称为LICON)与字线驱动器(Word line driver)连接，从而便于字线驱动器向字线中输入电压信号。如图1所示，DRAM可以包括基底110，基底110包括阵列区110a、边界区110c和核心区110b，边界区110c位于阵列区110a和核心区110b之间。在制备DRAM时，先在衬底上形成第一隔离层122，第一隔离层122位于阵列区110a和边界区110c的靠近阵列区110a的部分区域，以暴露出其余区域的基底110。然后在部分边界区110c的第一隔离层122和暴露的基底110上设置第一导电层133。
然而，在上述DRAM的制程中，由于第一隔离层122覆盖在阵列区110a和边界区110c的靠近阵列区110a的部分区域，而边界区110c的靠近核心区110b的部分区域以及核心区110b未覆盖第一隔离层122，导致覆盖有第一隔离层122的区域与未覆盖第一隔离层122的区域之间存在台阶，从而导致边界区110c的第一导电层133以及覆盖在第一导电层133上的其他功能层均形成台阶，而使得第一导电层133以及位于第一导电层133上的功能层的表面平整性较差。其中，以图1中A部分所在的 功能层为例，在实际工艺中，位于台阶处的该功能层(即图1中A部分)相比于该功能层的其余区域的厚度更大，A部分的该功能层相较于其他区域的该功能层不易刻蚀干净，容易出现残留，从而对DRAM的结构和性能造成影响。
虽然可以采取过度刻蚀的方法以将残留的部分该功能层去除干净，但是，这样很可能会对其余未残留该功能层的区域中的其他结构层造成损伤，从而影响DRAM的结构和性能。
本申请实施例提供一种半导体结构的制备方法、半导体结构和存储器，该半导体结构的制备方法可以包括提供基底，基底包括阵列区、核心区、以及位于阵列区和核心区之间的边界区；形成第一初始隔离层，第一初始隔离层位于阵列区、边界区和核心区，第一初始隔离层覆盖基底；去除位于核心区以及与核心区邻接的第一部分边界区中的第一初始隔离层，以得到第一隔离层；形成第一初始导电层，第一初始导电层位于阵列区、边界区和核心区，第一初始导电层覆盖基底和第一隔离层；对第一初始导电层进行平坦化处理，以得到第一中间导电层；以及去除位于阵列区以及与阵列区邻接的第二部分边界区中的第一中间导电层，以得到第一导电层；其中，第一导电层在基底上的正投影与第一隔离层在基底上的正投影部分交叠，且第一导电层在基底上的正投影与第一隔离层在基底上的正投影的交叠部分位于边界区内。由于对第一初始导电层进行平坦化处理，使得形成的第一导电层的表面平整性较好，从而可以使得制备在第一导电层上方的其他功能层的平整性较好，位于第一导电层上方的该功能层的厚度较为均匀，避免或减少在刻蚀工序中出现功能层残留，从而避免或减小对半导体结构和存储器的结构和性能的影响。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
以下将结合图1-图18对本申请实施例提供的半导体结构100的制备方法进行说明。
如图2所示，该半导体结构100的制备方法可以包括以下步骤：
S100：提供基底，基底包括阵列区、核心区、以及位于阵列区和核心区之间的边界区。
如图3所示，首先提供基底110，基底110可以包括依次相邻设置的阵列区110a、边界区110c和核心区110b，边界区110c位于阵列区110a和核心区110b之间。例如，边界区110c和核心区110b可以位于阵列区110a的至少一侧。示例性的，边界区110c可以设置在阵列区110a的外周，即边界区110c可以环绕阵列区110a一周。另外，核心区110b可以设置在边界区110c的外周，即核心区110b可以环绕边界区110c一周。
基底110的阵列区110a的上方后续可以形成有电容器；基底110的核心区110b的上方后续可以形成有外围电路，例如，外围电路可以包括晶体管等。边界区110c为位于阵列区110a和核心区110b之间的过渡区。
示例性的，如图3所示，边界区110c包括第一部分边界区110d、第二部分边界 区110e、以及位于第一部分边界区110d和第二部分边界区110e之间的第三部分边界区110f。第一部分边界区110d为边界区110c中靠近核心区110b的部分区域，第一部分边界区110d与核心区110b邻接；第二部分边界区110e为边界区110c中靠近阵列区110a的部分区域，第二部分边界区110e与阵列区110a邻接；第三部分边界区110f为边界区110c中位于第一部分边界区110d和第二部分边界区110e之间的区域。
继续参考图3，基底110内可以设置有源区111，部分有源区111可以位于阵列区110a并用于形成晶体管，位于阵列区110a的有源区111可以呈阵列排布。部分有源区111可以位于核心区110b并用于形成晶体管。例如，位于阵列区110a内的有源区111的间隔较小，位于核心区110b内的有源区111间隔较大。有源区111之间设置有隔离结构112，以将各个有源区111之间隔开。例如，隔离结构112可以包括氧化物，例如氧化硅。
示例性的，基底110可以包括衬底和位于衬底上的氧化层，有源区111和隔离结构112均可以位于衬底内。衬底上的氧化层可以避免有源区111暴露。其中，位于阵列区110a的氧化层的厚度可以大于位于核心区110b的氧化层的厚度。可以先在衬底上形成一层厚氧化层，去除位于核心区110b的厚氧化层，保留位于阵列区110a的厚氧化层，另外，还可以去除部分或者全部边界区110c的厚氧化层，或者，保留边界区110c的厚氧化层。然后在核心区110b的衬底上形成一层薄氧化层，薄氧化层可以为高质量的氧化层，以提高具有薄氧化层的器件(例如晶体管)的性能。
例如，薄氧化层可以具有较高的介电常数，以使薄氧化层的绝缘性较好，提高包含该薄氧化层的晶体管的击穿电压。其中，高介电常数的材料可以包括氧化钽(Ta 2O 5)、氧化铝(Al 2O 3)、氧化铪(HfO)、氧化钛硅(SiTiO 3)、氧化硅铪(HfSiO)、氮氧化硅铪(HfSiON)、氮氧化硅锆(ZrSiON)中的任意一种或多种。
例如衬底的材料可以是单晶硅、多晶硅、无定型硅、硅化锗、碳化硅、氮化镓等。衬底可以为体硅(Bulk Silicon)衬底，也可以是绝缘体上硅(Silicon On Insulator，简称SOI)衬底。衬底可以为衬底上的其他结构层提供支撑基础。
S200：形成第一初始隔离层，第一初始隔离层位于阵列区、边界区和核心区，第一初始隔离层覆盖基底。
如图4所示，在基底110上形成第一初始隔离层121，第一初始隔离层121覆盖基底110的阵列区110a、边界区110c和核心区110b。示例性的，第一初始隔离层121的材料可以为氮化硅，氮化硅隔离效果较好。
第一初始隔离层121可以通过沉积工艺形成在基底110上。例如，第一初始隔离层121可以通过化学气相沉积(Chemical Vapor Deposition，简称CVD)、物理气相沉积(Physical Vapor Deposition，简称PVD)或者原子层沉积(Atomic Layer Deposition，简称ALD)等工艺形成在基底110上。
S300：去除位于核心区以及与核心区邻接的第一部分边界区中的第一初始隔离层，以得到第一隔离层。
如图5所示，去除部分第一初始隔离层121，以形成第一隔离层122，第一隔离层122用于隔离位于第一隔离层122下方的基底110与位于第一隔离层122上方的其他结构层。
示例性的，可以去除核心区110b和边界区110c中的第一初始隔离层121，保留阵列区110a中的第一初始隔离层121，阵列区110a的基底110上形成第一隔离层122。
示例性的，如图5所示，可以去除核心区110b以及第一部分边界区110d中的第一初始隔离层121，保留阵列区110a、第二部分边界区110e以及第三部分边界区110f中的第一初始隔离层121，以在阵列区110a、第二部分边界区110e以及第三部分边界区110f的基底110上形成第一隔离层122。例如，阵列区110a在基底110上的正投影位于第一隔离层122在基底110上的正投影内，从而使得第一隔离层122完全覆盖阵列区110a，对阵列区110a的基底110的隔离效果较好。
例如，S300可以包括：
在第一初始隔离层121上形成初始掩膜层，该初始掩膜层可以为第一初始掩膜层，第一初始掩膜层覆盖基底110的阵列区110a、边界区110c和核心区110b。第一初始掩膜层可以为光刻胶。
去除核心区110b以及第一部分边界区110d中的第一初始掩膜层，形成第一掩膜层，第一掩膜层覆盖阵列区110a、第二部分边界区110e以及第三部分边界区110f的第一初始隔离层121，暴露出核心区110b以及第一部分边界区110d中的第一初始隔离层121。
以第一掩膜层为掩膜，去除第一掩膜层未覆盖的区域即核心区110b以及第一部分边界区110d中的第一初始隔离层121，以形成第一隔离层122，第一隔离层122位于阵列区110a、第二部分边界区110e以及第三部分边界区110f的基底110上。
去除第一掩膜层，暴露第一隔离层122。
需要说明的是，一些示例中，在形成第一初始隔离层121之前，可以分别形成位于阵列区110a的厚氧化层和位于核心区110b的薄氧化层，第一初始隔离层121覆盖在厚氧化层和薄氧化层上。另一些示例中，在形成第一初始隔离层121之前，可以先形成厚氧化层，厚氧化层覆盖阵列区110a、边界区110c和核心区110b的衬底，第一初始隔离层121覆盖在厚氧化层上；然后在去除核心区110b和第一部分边界区110d中的第一初始隔离层121的同时，去除核心区110b和第一部分边界区110d中的厚氧化层，从而无需分次去除厚氧化层和第一初始隔离层121，能够简化制备工艺。然后在核心区110b和第一部分边界区110d中的衬底上形成薄氧化层，部分薄氧化层可以覆盖在第一隔离层122的边缘的上方，从而避免暴露衬底而对衬底形成保护。
S400：形成第一初始导电层，第一初始导电层位于阵列区、边界区和核心区，第一初始导电层覆盖基底和第一隔离层。
如图6所示，在第一隔离层122以及暴露的基底110上形成第一初始导电层131，第一初始导电层131位于阵列区110a、边界区110c和核心区110b中。由于覆盖有第一隔离层122和未覆盖第一隔离层122的基底110之间存在台阶，导致第一初始导电层131存在台阶，从而在第一初始导电层131的上部形成台阶部134。台阶部134会导致后续形成在第一初始导电层131上的其他功能层也存在台阶，影响其他功能层的平整性，从而影响半导体结构100的结构和性能。
示例性的，第一初始导电层131的材料可以为多晶硅(polycrystalline silicon)。
示例性的，第一初始导电层131的厚度d(图6中)的范围可以为40nm-120nm， 例如，第一初始导电层131的厚度d可以为40nm、60nm、80nm、100nm、120nm以及40nm-120nm之间的任意厚度。从而可以避免第一初始导电层131的厚度过低，在第一初始导电层131进行后续的平坦化处理后，避免保留的第一初始导电层131的厚度过低；又可以避免第一初始导电层131的厚度过高，避免后续平坦化处理的时间过长。
S500：对第一初始导电层进行平坦化处理，以得到第一中间导电层。
如图7所示，对第一初始导电层131进行平坦化处理，去除部分厚度的第一初始导电层131，保留部分厚度的第一初始导电层131，从而得到第一中间导电层132。
例如，S500可以包括：
掺杂处理位于阵列区110a和边界区110c中的第一初始导电层131。
对台阶部134进行掺杂处理，以改变掺杂处理的第一初始导电层131的性质，使得掺杂处理后的第一初始导电层131更容易被去除，掺杂处理后的第一初始导电层131的去除速度较快，而未掺杂处理的第一初始导电层131的去除速度较慢，从而可以在去除部分厚度的第一初始导电层131的同时，去除台阶部134，以使保留的第一初始导电层131的顶面形成较为平整的表面。
示例性的，掺杂处理的第一初始导电层131的厚度范围可以为5nm-10nm。即对台阶部134的掺杂厚度的范围可以为5nm-10nm。例如，被掺杂处理的台阶部134的厚度可以为5nm、6nm、7nm、8nm、9nm、10nm或5nm-10nm之间的任意厚度。从而可以避免被掺杂处理的台阶部134的厚度过低而无法很好的去除台阶部134；又可以避免被掺杂处理的台阶部134的厚度过高而降低掺杂的精度。
示例性的，掺杂处理的掺杂材料135可以包括砷原子、磷原子等V族元素，碳原子等IV族元素中的任意一种或多种。
对第一初始导电层131进行刻蚀或化学机械抛光，以得到第一中间导电层132。平坦化处理可以包括干法刻蚀、湿法刻蚀或者化学机械抛光等方法，通过平坦化处理以去除部分厚度的第一初始导电层131，剩余的第一初始导电层131形成第一中间导电层132，第一中间导电层132的顶面可以为平面，其平整性较好，避免或减小对后续形成在第一中间导电层132上的其他功能层的平整性的影响，从而避免或减小影响半导体结构100的结构和性能。
例如，如图8-图12所示，掺杂处理位于阵列区110a和边界区110c中的第一初始导电层131的步骤可以包括：
如图8所示，形成初始掩膜层，初始掩膜层位于阵列区110a、边界区110c和核心区110b，初始掩膜层覆盖第一初始导电层131。在第一初始导电层131上形成初始掩膜层，该初始掩膜层可以为第二初始掩膜层141，第二初始掩膜层141位于阵列区110a、边界区110c和核心区110b。例如，第二初始掩膜层141可以为光刻胶。
如图9所示，去除位于阵列区110a和边界区110c中的第二初始掩膜层141，以得到掩膜层，该掩膜层可以为第二掩膜层142。即可以去除台阶部134上方的第二初始掩膜层141，从而暴露出台阶部134，以便于对台阶部134进行掺杂处理。
需要说明的是，如图9所示，台阶部134的靠近核心区110b的侧壁面可以为弧面，即台阶部134的侧壁面的高度是逐渐增加，该侧壁面为倾斜设置。此时，第二掩 膜层142可以覆盖台阶部134的靠近核心区110b的部分侧壁面，从而避免对台阶部134的靠近核心区110b的部分侧壁面进行掺杂处理，导致掺杂材料135沿侧壁分布厚度较大，无法准确控制掺杂处理的厚度，甚至导致掺杂材料135通过高度较小的侧壁面进入台阶部134的下方，从而影响掺杂处理的均匀性和厚度控制的准确性。
如图10所示，对阵列区110a和边界区110c中的第一初始导电层131进行离子注入。其中，掺杂处理的方式可以包括离子注入。
示例性的，离子注入的剂量范围为10 13原子数/平方厘米-10 15原子数/平方厘米。例如，离子注入的剂量范围为10 13原子数/平方厘米、10 14原子数/平方厘米、10 15原子数/平方厘米或者10 13原子数/平方厘米-10 15原子数/平方厘米之间的任意剂量。从而可以避免离子注入的剂量过小，避免掺入到第一初始导电层131的掺杂材料135的含量过低，从而对第一初始导电层131的性质的改善效果较好；又可以避免离子注入的剂量过大，有利于控制掺入到第一初始导电层131的掺杂材料135的含量。
示例性的，离子注入的能量范围可以为30keV-100keV。例如，离子注入的能量可以为30keV、50keV、70keV、90keV、100keV或者30keV-100keV之间的任意能量。从而可以避免离子注入的能量过低，避免注入到第一初始导电层131中的掺杂材料135的含量过低或注入深度过浅，从而对第一初始导电层131的性质的改善效果较好；又可以避免离子注入的能量过高，从而避免掺杂材料135注入的深度过深，可以较好的控制掺杂处理的厚度(即深度)。
如图11所示，去除第二掩膜层142。掺杂处理之后，可以将第二掩膜层142去除，以暴露出位于核心区110b的第一初始导电层131。
在掺杂处理位于阵列区110a和边界区110c中的第一初始导电层131之后，对第一初始导电层131进行刻蚀或化学机械抛光，以得到第一中间导电层132的步骤之前，还可以包括：热退火处理第一初始导电层131。如图12所示，在去除第二掩膜层142之后，可以对掺杂处理的第一初始导电层131进行热退火处理。通过热退火处理可以修复离子注入造成的第一初始导电层131的表面晶体损伤，激活离子注入的掺杂材料135，同时使得掺杂材料135均匀分布在所需厚度的第一初始导电层131中。
S600：去除位于阵列区以及与阵列区邻接的第二部分边界区中的第一中间导电层，以得到第一导电层。
如图13所示，去除位于阵列区110a以及与第二部分边界区110e中的第一中间导电层132，保留位于第一部分边界区110d、第三部分边界区110f以及核心区110b中的第一中间导电层132，以形成第一导电层133。第一导电层133覆盖在第一部分边界区110d、第三部分边界区110f以及核心区110b中。
如图13所示，第一导电层133在基底110上的正投影与第一隔离层122在基底110上的正投影部分交叠，且第一导电层133在基底110上的正投影与第一隔离层122在基底110上的正投影的交叠部分位于第三部分边界区110f中。交叠部分的第一导电层133和第一隔离层122可以避免基底110暴露，而对基底110形成保护。
得到第一导电层133的步骤之后，还可以包括：
如图14所示，形成第二导电层151，第二导电层151位于阵列区110a、边界区110c和核心区110b中，第二导电层151覆盖第一隔离层122和第一导电层133。即 在第一导电层133和第一隔离层122上形成第二导电层151，第二导电层151覆盖阵列区110a、边界区110c和核心区110b。
形成第二导电层151的步骤之后，还可以包括：
如图15所示，形成第三导电层152，第三导电层152位于阵列区110a、边界区110c和核心区110b中，第三导电层152覆盖第二导电层151。即在第二导电层151上形成第三导电层152，第三导电层152覆盖阵列区110a、边界区110c和核心区110b。
示例性的，第二导电层151的材料可以为氮化钛，第三导电层152的材料可以为钨。氮化钛可以防止钨扩散与硅反应形成低阻的欧姆接触，有利于提高钨的附着性。另外，钨具有良好的台阶覆盖率。
形成第三导电层152的步骤之后，还可以包括：
如图16所示，形成第二隔离层153，第二隔离层153位于阵列区110a、边界区110c和核心区110b中，第二隔离层153覆盖第三导电层152。即在第三导电层152上形成第二隔离层153，第二隔离层153覆盖阵列区110a、边界区110c和核心区110b。
示例性的，第二隔离层153的材料可以为氮化硅。
需要说明的是，第二导电层151、第三导电层152、第二隔离层153中的任意一者或多者均可以形成上述实施例中的功能层。
位于阵列区110a的第二导电层151、第三导电层152后续可以形成位线。
位于核心区110b的薄氧化层、第一导电层133、第二导电层151、第三导电层152以及基底110中的有源区111后续可以形成器件，例如晶体管。
形成第二隔离层153的步骤之后，还可以包括：
如图17所示，依次去除位于边界区110c的第二隔离层153、第三导电层152和第二导电层151，位于核心区110b的第二导电层151与位于阵列区110a的第二导电层151电性隔离，位于核心区110b的第三导电层152与位于阵列区110a的第三导电层152电性隔离。
在去除边界区110c的第二隔离层153、第三导电层152和第二导电层151时，由于第一导电层133的顶面平整性较好，使得位于第一导电层133上方的第二隔离层153、第三导电层152和第二导电层151的厚度较为均匀，能够避免或减少第二导电层151的残留，从而避免或减少残留的第二导电层151对半导体结构100的结构和性能影响。
在去除边界区110c的第二导电层151之后，还可以去除边界区110c的部分或者全部第一导电层133(图18)，或者，也可以保留边界区110c的第一导电层133(图17)。
例如，还可以在边界区110c中填充绝缘材料，以确保阵列区110a和核心区110b之间必要的电性隔离。
本申请实施例还提供一种半导体结构100，该半导体结构100可以采用上述实施例中的半导体结构100的制备方法制备而成。
如图13所示，半导体结构100可以包括基底110，基底110包括阵列区110a、核心区110b、以及位于阵列区110a和核心区110b之间的边界区110c。基底110上依次层叠设置有第一隔离层122和第一导电层133，第一隔离层122覆盖在阵列区 110a、第二部分边界区110e以及第三部分边界区110f的基底110上、第一导电层133覆盖在核心区110b、第一部分边界区110d以及第三部分边界区110f的第一隔离层122和基底110上。第一导电层133的顶面可以为平面，从而使得第一导电层133的顶面的平整性较好。例如，可以对第一导电层133进行平坦化处理，从而使得第一导电层133的顶面形成平整的表面，以避免对后续形成在第一导电层133上的其他功能层(例如，第二导电层151、第三导电层152以及第二隔离层153等)的平整性造成影响，避免或减少功能层在后续的刻蚀工序中残留在边界区110c，从而避免或减少对半导体结构100的结构和性能的影响。
其中，第一导电层133在基底110上的正投影与第一隔离层122在基底110上的正投影部分交叠，且第一导电层133在基底110上的正投影与第一隔离层122在基底110上的正投影的交叠部分位于第三部分边界区110f内，从而可以避免基底110暴露，以对基底110形成保护。
需要说明的是，一些示例中，在后续工艺中，可以保留边界区110c中的第一导电层133(图17)，也可以去除边界区110c中的部分或者全部的第一导电层133(图18)。该半导体结构100可以是保留边界区110c中至少部分第一导电层133而形成的半导体结构100，也可以是去除边界区110c中第一导电层133而形成的半导体结构100。
本申请实施例还提供一种存储器，该存储器可以包括采用上述实施例中的半导体结构100的制备方法制备而成的半导体结构100。
示例性的，存储器可以包括例如动态随机存取存储器、静态随机存取存储器(Static Random Access Memory，简称SRAM)、快闪存储器、电可擦可编程只读存储器(Electrically Erasable Programmable Read-Only Memory，简称EEPROM)、相变随机存取存储器(Phase Change Random Access Memory，简称PRAM)或磁阻随机存取存储器(Magnetoresistive Random Access Memory，简称MRAM)。
示例性的，上述实施例中的半导体结构100可以应用于非存储器件。非存储器件可以是逻辑器件(例如微处理器、数字信号处理器或微型控制器)或与其类似的器件。
本申请实施例以DRAM存储器为例进行说明。
可以将上述实施例中的半导体结构100应用于存储器，存储器包括半导体结构100。半导体结构100可以包括基底110，基底110包括阵列区110a、核心区110b、以及位于阵列区110a和核心区110b之间的边界区110c。基底110上依次层叠设置有第一隔离层122和第一导电层133，第一隔离层122覆盖在阵列区110a、第二部分边界区110e以及第三部分边界区110f的基底110上、第一导电层133覆盖在核心区110b、第一部分边界区110d以及第三部分边界区110f的第一隔离层122和基底110上。第一导电层133的顶面可以为平面，从而使得第一导电层133的顶面的平整性较好。例如，可以对第一导电层133进行平坦化处理，从而使得第一导电层133的顶面形成平整的表面，以避免对后续形成在第一导电层133上的其他功能层(例如，第二导电层151、第三导电层152以及第二隔离层153等)的平整性造成影响，避免或减少功能层在后续的刻蚀工序中残留在边界区110c，从而避免或减少对存储器的结构和性能的影响。
其中，第一导电层133在基底110上的正投影与第一隔离层122在基底110上的正投影部分交叠，且第一导电层133在基底110上的正投影与第一隔离层122在基底110上的正投影的交叠部分位于第三部分边界区110f内，从而可以避免基底110暴露，以对基底110形成保护。
需要说明的是，一些示例中，在后续工艺中，可以去除边界区110c中的第一导电层133，以使得位于核心区110b和位于阵列区110a中的第一导电层133之间电性隔离。另一些示例中，也可以保留边界区110c中的部分或者全部的第一导电层133。
这里需要说明的是，本申请实施例涉及的数值和数值范围为近似值，受制造工艺的影响，可能会存在一定范围的误差，这部分误差本领域技术人员可以认为忽略不计。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (19)

  1. 一种半导体结构的制备方法，包括：
    提供基底，所述基底包括阵列区、核心区、以及位于所述阵列区和所述核心区之间的边界区；
    形成第一初始隔离层，所述第一初始隔离层位于所述阵列区、所述边界区和所述核心区，所述第一初始隔离层覆盖所述基底；
    去除位于所述核心区以及与所述核心区邻接的第一部分边界区中的所述第一初始隔离层，以得到第一隔离层；
    形成第一初始导电层，所述第一初始导电层位于所述阵列区、所述边界区和所述核心区，所述第一初始导电层覆盖所述基底和所述第一隔离层；
    对所述第一初始导电层进行平坦化处理，以得到第一中间导电层；以及
    去除位于所述阵列区以及与所述阵列区邻接的第二部分边界区中的所述第一中间导电层，以得到第一导电层；
    其中，所述第一导电层在所述基底上的正投影与所述第一隔离层在所述基底上的正投影部分交叠，且所述第一导电层在所述基底上的正投影与所述第一隔离层在所述基底上的正投影的交叠部分位于所述边界区内。
  2. 根据权利要求1所述的半导体结构的制备方法，其中，对所述第一初始导电层进行所述平坦化处理，以得到所述第一中间导电层，包括：
    掺杂处理位于所述阵列区和所述边界区中的所述第一初始导电层；以及
    对所述第一初始导电层进行刻蚀或化学机械抛光，以得到所述第一中间导电层。
  3. 根据权利要求2所述的半导体结构的制备方法，其中，掺杂处理位于所述阵列区和所述边界区中的所述第一初始导电层包括：
    形成初始掩膜层，所述初始掩膜层位于所述阵列区、所述边界区和所述核心区，所述初始掩膜层覆盖所述第一初始导电层；
    去除位于所述阵列区和所述边界区中的所述初始掩膜层，以得到掩膜层；
    对所述阵列区和所述边界区中的所述第一初始导电层进行离子注入；以及
    去除所述掩膜层。
  4. 根据权利要求2或3所述的半导体结构的制备方法，其中，在掺杂处理位于所述阵列区和所述边界区中的所述第一初始导电层之后，对所述第一初始导电层进行刻蚀或化学机械抛光，以得到所述第一中间导电层之前，还包括：热退火处理所述第一初始导电层。
  5. 根据权利要求1-3任一所述的半导体结构的制备方法，其中，所述第一初始导电层的厚度范围为40nm-120nm。
  6. 根据权利要求1-3任一所述的半导体结构的制备方法，其中，所述第一初始导电层的材料为多晶硅。
  7. 根据权利要求2或3所述的半导体结构的制备方法，其中，掺杂处理的所述第一初始导电层的厚度大于5nm而小于10nm。
  8. 根据权利要求3所述的半导体结构的制备方法，其中，
    离子注入的剂量范围为10 13原子数/平方厘米-10 15原子数/平方厘米，离子注入的能量范围为30keV-100keV。
  9. 根据权利要求2或3任一所述的半导体结构的制备方法，其中，所述掺杂处理的掺杂材料包括砷、磷或碳原子。
  10. 根据权利要求1-3任一所述的半导体结构的制备方法，其中，所述边界区包括所述第一部分边界区、所述第二部分边界区、以及位于所述第一部分边界区和所述第二部分边界区之间的第三部分边界区，所述第一导电层在所述基底上的正投影与所述第一隔离层在所述基底上的正投影的交叠部分位于所述第三部分边界区内。
  11. 根据权利要求1-3任一所述的半导体结构的制备方法，其中，得到所述第一导电层之后，还包括：
    形成第二导电层，所述第二导电层位于所述阵列区、所述边界区和所述核心区中，所述第二导电层覆盖所述第一隔离层和所述第一导电层。
  12. 根据权利要求11所述的半导体结构的制备方法，其中，所述第二导电层的材料为氮化钛。
  13. 根据权利要求11所述的半导体结构的制备方法，其中，形成所述第二导电层之后，还包括：
    形成第三导电层，所述第三导电层位于所述阵列区、所述边界区和所述核心区中，所述第三导电层覆盖所述第二导电层。
  14. 根据权利要求13所述的半导体结构的制备方法，其中，所述第三导电层的材料为钨。
  15. 根据权利要求13所述的半导体结构的制备方法，其中，形成所述第三导电层之后，还包括：
    形成第二隔离层，所述第二隔离层位于所述阵列区、所述边界区和所述核心区中，所述第二隔离层覆盖所述第三导电层。
  16. 根据权利要求15所述的半导体结构的制备方法，其中，所述第一隔离层和/或所述第二隔离层的材料为氮化硅。
  17. 根据权利要求15所述的半导体结构的制备方法，其中，形成所述第二隔离层之后，还包括：
    依次去除位于所述边界区的所述第二隔离层、所述第三导电层和所述第二导电层，位于所述核心区的所述第二导电层与位于所述阵列区的所述第二导电层电性隔离，位于所述核心区的所述第三导电层与位于所述阵列区的所述第三导电层电性隔离。
  18. 一种半导体结构，通过上述权利要求1-17中任一项所述的半导体结构的制备方法制备而成。
  19. 一种存储器，包括根据权利要求17所述的半导体结构的制备方法制备得到的半导体结构。
PCT/CN2022/125746 2022-04-18 2022-10-17 半导体结构的制备方法、半导体结构和存储器 WO2023202009A1 (zh)

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